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use new consts module
2020-07-04 Luke Kenneth Casson... use new consts module
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2020-07-04 Luke Kenneth Casson... sorting out trap fastregs
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2020-07-04 Luke Kenneth Casson... sort out trap test reg checking
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2020-07-04 Luke Kenneth Casson... resolve spr names in ISACaller
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2020-07-04 Luke Kenneth Casson... rename spr1 to fast1 in trap data
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2020-07-04 Luke Kenneth Casson... sorting out fast/spr naming
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2020-07-04 Luke Kenneth Casson... oops initialise Function Unit class with idx
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2020-07-04 Luke Kenneth Casson... add first cookie-cut test_trap_compunit.py
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2020-07-04 Luke Kenneth Casson... add gitignores
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2020-07-04 Luke Kenneth Casson... debugging decoding of SPRs (fast)
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2020-07-04 Luke Kenneth Casson... add spr test, add decode of spr in/out
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2020-07-04 Luke Kenneth Casson... add spr main stage
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2020-07-04 Luke Kenneth Casson... add spr input record
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2020-07-04 Luke Kenneth Casson... add SPR pipeline
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2020-07-04 Luke Kenneth Casson... reduce steps per stage to 8
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2020-07-03 Luke Kenneth Casson... set only div/rem supported
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2020-07-02 Luke Kenneth Casson... allow flexible selection of the types of ALUs
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2020-07-02 Luke Kenneth Casson... fix unit tests due to change in using pspec
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2020-07-02 Luke Kenneth Casson... use Mock class (more convenient)
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2020-07-02 Luke Kenneth Casson... allow ALU names to propagate through from FU to CompUnit ALU
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2020-07-02 Luke Kenneth Casson... name function unit ALUs
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2020-07-02 Luke Kenneth Casson... comment out DIV unit for now
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2020-07-02 Luke Kenneth Casson... increase combinatorial stages to 8
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2020-07-02 Luke Kenneth Casson... reduce DIV radix to 1
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2020-07-02 Luke Kenneth Casson... add DIV function unit to compunits
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2020-07-02 Luke Kenneth Casson... add trap function unit into compunits
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2020-07-02 Luke Kenneth Casson... add bare wishbone option to TestIssuer, sort out ports
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2020-07-02 Luke Kenneth Casson... use single-arg pspec for TestIssuer and Core
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2020-07-02 Luke Kenneth Casson... first experimental index.rst for sphinx documentation
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2020-07-02 Luke Kenneth Casson... add sphinx doc preliminary start
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2020-07-01 Luke Kenneth Casson... whoops missed some cases in unit test changing ALUHelpers
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2020-07-01 Luke Kenneth Casson... minor reorg on how Bus and Config classes are set up
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2020-07-01 Luke Kenneth Casson... whoops swapped trap test instructions accidentally
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2020-07-01 Luke Kenneth Casson... print out msr for debug
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2020-07-01 Luke Kenneth Casson... attempting to add SPRs to rfid test
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2020-07-01 Luke Kenneth Casson... add OP_SC
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2020-07-01 Luke Kenneth Casson... trap test check results
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2020-07-01 Luke Kenneth Casson... add name "test_issuer" to ilang conversion
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2020-07-01 Luke Kenneth Casson... add in trap compunit
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2020-07-01 Luke Kenneth Casson... add rfid and td/tw trap test
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2020-07-01 Luke Kenneth Casson... continue debugging trap pipeline
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2020-07-01 Luke Kenneth Casson... debugging trap pipeline
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2020-07-01 Luke Kenneth Casson... start running trap unit test, fixing errors
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2020-06-30 Luke Kenneth Casson... add lte ltu for use by twi and other trap functions
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2020-06-30 Luke Kenneth Casson... add in pseudocode keyword into mdwn isa files
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2020-06-30 Luke Kenneth Casson... code-morph on div pipeline
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2020-06-29 Luke Kenneth Casson... add README for fu directory
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2020-06-29 Luke Kenneth Casson... use correct ALUHelpers in div test
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2020-06-29 Luke Kenneth Casson... sort out syntax errors in div
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2020-06-29 Luke Kenneth Casson... first unit test for div
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2020-06-29 Luke Kenneth Casson... update submodule to fix div bug
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2020-06-29 Luke Kenneth Casson... add ignore for parsetab.py
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2020-06-29 Luke Kenneth Casson... add autogenerated do not commit comment
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2020-06-29 Luke Kenneth Casson... update submodule to div overflow
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2020-06-29 Luke Kenneth Casson... separate out divide by zero cases
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2020-06-29 Luke Kenneth Casson... update OV and OV32 ISACaller flags if overflow occurs
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2020-06-29 Luke Kenneth Casson... attempting to add overflow setting in ISACaller
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2020-06-29 Luke Kenneth Casson... whoops, hex parser digits are in multiples of 4 bits
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2020-06-29 Luke Kenneth Casson... fetch instructions from bare wishbone fetch unit
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2020-06-28 Luke Kenneth Casson... add cached fetch unit pass-through args
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2020-06-28 Luke Kenneth Casson... need args to WishboneArbiter, match data width size
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2020-06-28 Luke Kenneth Casson... read from instruction memory using FetchUnitInterface
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2020-06-28 Luke Kenneth Casson... add Config Fetch interface and quick unit test
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2020-06-28 Luke Kenneth Casson... add test instruction memory
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2020-06-28 Luke Kenneth Casson... add readonly option to TestMemory
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2020-06-28 Luke Kenneth Casson... expand instruction bus width to 64 bit, start on a...
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2020-06-28 Luke Kenneth Casson... parameterise minerva i-cache
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2020-06-28 Luke Kenneth Casson... got Pi2LSUI FSM working
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2020-06-28 Luke Kenneth Casson... sram address do not cut by LSBs
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2020-06-28 Luke Kenneth Casson... new Pi2LSUI working, using PortInterfaceBase
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2020-06-28 Luke Kenneth Casson... start new version of Pi2LSUI based on PortInterfaceBase
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2020-06-28 Luke Kenneth Casson... pass addr/mask through to PortInterfaceBase rd/wr addr
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2020-06-28 Luke Kenneth Casson... cleanup (remove unneeded imports)
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2020-06-28 Luke Kenneth Casson... more code-shuffle for TestMemoryPortInterface
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2020-06-28 Luke Kenneth Casson... more code-shuffle for TestMemoryPortInterface
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2020-06-28 Luke Kenneth Casson... minor cleanup, put get/set rdport/wrport into function
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2020-06-28 Luke Kenneth Casson... merge LDSTPort into TestMemoryPortInterface
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2020-06-28 Luke Kenneth Casson... use PortInterface connect_port
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2020-06-28 Luke Kenneth Casson... use PortInterface connect_port
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2020-06-28 Luke Kenneth Casson... attempt to get Pi2LSUI FSM working
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2020-06-27 Luke Kenneth Casson... only activate ld_in_progress if addr is ok
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2020-06-27 Luke Kenneth Casson... make Memory accessible via TestSRAMBareLoadStoreUnit
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2020-06-27 Luke Kenneth Casson... increase (double) address width in TstL0CacheBuffer
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2020-06-27 Luke Kenneth Casson... increase (double) address width in TstL0CacheBuffer
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2020-06-27 Luke Kenneth Casson... unit test in l0_cache to connect to testpi and test_bare_wb
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2020-06-27 Luke Kenneth Casson... make PortInterface modules consistent with same API
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2020-06-27 Luke Kenneth Casson... use ConfigMemoryPortInterface in TstL0CacheBuffer
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2020-06-27 Luke Kenneth Casson... fix TestMemLoadStoreUnit, it required a FSM to monitor...
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2020-06-27 Luke Kenneth Casson... add wishbone Pi2LSUI test
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2020-06-27 Luke Kenneth Casson... reconfigureable PortInterface testing now possible
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2020-06-26 Luke Kenneth Casson... name issue in Pi2LSUI
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2020-06-26 Luke Kenneth Casson... whitespace and imports
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2020-06-26 Luke Kenneth Casson... whitespace
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2020-06-26 Luke Kenneth Casson... slight reorg on test_pi2ls.py
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2020-06-26 Luke Kenneth Casson... correct address in pi2ls
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2020-06-26 Luke Kenneth Casson... oops forgot to initialise base class of TestMemLoadStoreUnit
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2020-06-26 Luke Kenneth Casson... add in LenExpand shift/mask
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2020-06-26 Luke Kenneth Casson... add quick test showing Pi2LSUI not quite reading/writing to
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2020-06-26 Luke Kenneth Casson... remove extraneous yields
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2020-06-26 Luke Kenneth Casson... set address ok and fix unit test to check it properly
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