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add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex
2020-09-30 Luke Kenneth Casson... hmm only set wishbone address if ack is actually received
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2020-09-30 Luke Kenneth Casson... add more debug prints in icache
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2020-09-30 Luke Kenneth Casson... remove more reviewed comments
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2020-09-30 Luke Kenneth Casson... remove reviewed comments
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2020-09-30 Luke Kenneth Casson... comb on wr_index not sync
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2020-09-30 Luke Kenneth Casson... start removing reviewed comments
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2020-09-30 Luke Kenneth Casson... use same constant name (confusing otherwise)
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2020-09-30 Luke Kenneth Casson... need asserts
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2020-09-30 Luke Kenneth Casson... halve the number of icache lines for now
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2020-09-30 Luke Kenneth Casson... use Repl rather than for-loop to copy bit
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2020-09-30 Luke Kenneth Casson... move loop invariant test out of loop
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2020-09-30 Luke Kenneth Casson... reduce size of ilang file by a factor of FIVE
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2020-09-30 Luke Kenneth Casson... store tag in temp signal
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2020-09-30 Luke Kenneth Casson... reduce gate usage by getting cache row only not entire...
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2020-09-30 Luke Kenneth Casson... fix read_tag to use word_select correctly
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2020-09-30 Luke Kenneth Casson... forgot to add PLRUs as submodules
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2020-09-28 Luke Kenneth Casson... reduce not-connected IO pins
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2020-09-28 Luke Kenneth Casson... missing pspec
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2020-09-28 Luke Kenneth Casson... connect SDRAM dqm to wrdata_mask
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2020-09-28 Luke Kenneth Casson... lots of sorting out iopads
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2020-09-28 Luke Kenneth Casson... add "nocore" option to build verilog
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2020-09-28 Luke Kenneth Casson... switch off internal gpio (testing)
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2020-09-28 Luke Kenneth Casson... rewrite ilang file after litex ls180 build
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2020-09-28 Luke Kenneth Casson... had to over-ride the wishbone functions on C4M TAP
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2020-09-27 Luke Kenneth Casson... add Makefile for creating ls180.il
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2020-09-27 Luke Kenneth Casson... rename sys_clk_i to clk_24_i
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2020-09-27 Luke Kenneth Casson... add clock selection mechanism
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2020-09-26 Luke Kenneth Casson... DMI-to-JTAG needed to be "sync" to get ack/resp right
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2020-09-26 Luke Kenneth Casson... do not use simdec2 in test_pipe_caller
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2020-09-26 Luke Kenneth Casson... fix annoying alu test_pipe_caller bug, missing asmcode
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2020-09-26 Luke Kenneth Casson... add alternative PowerDecode2 to branch test_pipe_caller
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2020-09-26 Luke Kenneth Casson... try svf test of DMI MSR
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2020-09-26 Luke Kenneth Casson... make check of LDSTMode.update conditional in PowerDecoder2
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2020-09-26 Luke Kenneth Casson... add ls180io.py
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2020-09-26 Luke Kenneth Casson... add openocd script to fire off svf test
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2020-09-26 Luke Kenneth Casson... get openocd svf test running, replicating jtag test
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2020-09-26 Luke Kenneth Casson... put test into "server" mode for connecting with openocd
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2020-09-26 Luke Kenneth Casson... create client-server version of jtag debug unit test
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2020-09-26 Luke Kenneth Casson... create client-server version of jtag debug unit test
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2020-09-26 Luke Kenneth Casson... class-ify jtagremote
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2020-09-26 Luke Kenneth Casson... send/receive jtagremote protocol
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2020-09-26 Luke Kenneth Casson... basic client/server socket example
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2020-09-26 Luke Kenneth Casson... add openocd configs
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2020-09-26 Luke Kenneth Casson... reduce sdram pins to smaller address and only 1 cs_n
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2020-09-26 Luke Kenneth Casson... only enable pads connections for ls180 for now
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2020-09-24 Luke Kenneth Casson... do not have to use uart_litex gpio_litex names
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2020-09-24 Luke Kenneth Casson... add comments
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2020-09-24 Luke Kenneth Casson... enable GPIO pads through C4M JTAG
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2020-09-24 Luke Kenneth Casson... c4m iopad integration working
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2020-09-24 Luke Kenneth Casson... brackets round imports looks cleaner?
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2020-09-24 Luke Kenneth Casson... add jtag c4m pins which gives us a way to connect IO...
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2020-09-23 Luke Kenneth Casson... cs_n and cke in sdram need to match in length
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2020-09-23 Luke Kenneth Casson... change litex sdram pinouts to ASIC type
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2020-09-23 Luke Kenneth Casson... redo litex SDCard to send out data/cmd o/i/en pins
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2020-09-23 Luke Kenneth Casson... sort out GPIO with i/o/oe in ls180
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2020-09-23 Luke Kenneth Casson... add ls180 pinmap text file
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2020-09-23 Luke Kenneth Casson... attempt GPIO bi-directional
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2020-09-23 Luke Kenneth Casson... add I2C master to ls180
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2020-09-22 Luke Kenneth Casson... add 2 PWMs (quick, easy to do)
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2020-09-22 Luke Kenneth Casson... move dmi_sim to separate module
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2020-09-22 Luke Kenneth Casson... add openocd.cfg experiment
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2020-09-22 Luke Kenneth Casson... create a JTAG platform and connect it up. jtagremote...
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2020-09-22 Luke Kenneth Casson... add jtagremote to litex sim, add new "variant" to core...
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2020-09-22 Luke Kenneth Casson... link litex ls180soc JTAG pads
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2020-09-22 Luke Kenneth Casson... add jtag wishbone and jtag ports to libresoc litex...
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2020-09-22 Luke Kenneth Casson... add jtag interface to issuer_verilog
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2020-09-22 Luke Kenneth Casson... add sys_rst to Clock Reset Generator
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2020-09-22 Luke Kenneth Casson... add JTAG IOpads and rename rst to sys_rst
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2020-09-22 Luke Kenneth Casson... add similar platforms to ls180.py
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2020-09-22 Luke Kenneth Casson... add JTAG bus module
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2020-09-22 Luke Kenneth Casson... split out dmi2jtag into own unit test
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2020-09-22 Luke Kenneth Casson... submodule update
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2020-09-22 Luke Kenneth Casson... disable pia in div tests
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2020-09-22 Luke Kenneth Casson... add MMU (commented out)
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2020-09-21 Luke Kenneth Casson... add missing file
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2020-09-21 Luke Kenneth Casson... add quick wishbone jtag test
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2020-09-21 Luke Kenneth Casson... experiment set dmi msr read
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2020-09-21 Luke Kenneth Casson... add DMI JTAG test
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2020-09-21 Luke Kenneth Casson... add JTAG basic unit test
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2020-09-21 Luke Kenneth Casson... arg complete rewrite of JTAG2DMI, based it on staf...
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2020-09-20 Luke Kenneth Casson... resolve issues in async sim: must not drive async clock...
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2020-09-20 Luke Kenneth Casson... still experimenting with async FF sync
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2020-09-20 Luke Kenneth Casson... continuing async clock experimenting
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2020-09-20 Luke Kenneth Casson... add an async clock synchronizer experiment
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2020-09-20 Luke Kenneth Casson... first version code-morph on dmi2jtag
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2020-09-19 Luke Kenneth Casson... add pc_o not connected
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2020-09-19 Luke Kenneth Casson... set ROM to empty, set SRAM to tiny 0x200, get things...
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2020-09-19 Luke Kenneth Casson... urk. wishbone slave devices declared incorrectly (I...
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2020-09-19 Luke Kenneth Casson... disable internal RAM set SRAM to much smaller
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2020-09-19 Luke Kenneth Casson... shrink size of SRAM to 8k, move things around
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2020-09-19 Luke Kenneth Casson... add (disabled) tri-state GPIO
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2020-09-19 Luke Kenneth Casson... remove the gpio peripheral which was previously hard...
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2020-09-19 Luke Kenneth Casson... add 3x EINTs to ls180soc
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2020-09-18 Luke Kenneth Casson... add SPI, sdcard, preliminary GPIO to ls180 pinouts
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2020-09-18 Luke Kenneth Casson... argh got fed up trying to shoe-horn into sim.py
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2020-09-18 Luke Kenneth Casson... can remove unneeded overrides of Prev/Next Control
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2020-09-17 Luke Kenneth Casson... add versa ecp5 fpga litex build script
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2020-09-16 Luke Kenneth Casson... make a start on LS180 platform
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2020-09-15 Luke Kenneth Casson... add back (totally confusing) accidentally-removed code...
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2020-09-15 Luke Kenneth Casson... instantiate MMU from AllFunctionUnits
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