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Remove extra yield from test case.
2020-07-20 Cesar StraussRemove extra yield from test case.
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2020-07-19 Cesar StraussImplement control path and unit test.
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2020-07-18 Cesar StraussImplement the Shifter data path
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2020-07-18 Cesar StraussDocument move of the next port data
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2020-07-09 Cesar StraussDefine ports for a simple sequential Shifter
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2020-07-08 Cesar StraussStart the FSM-based ALU example.
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2020-07-07 Cesar StraussClear input data along with valid_i
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2020-07-06 Cesar StraussAssert n.ready_i at the beginning of the cycle
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2020-07-06 Cesar StraussRemove wait state to demonstrate zero-delay reception.
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2020-07-06 Cesar StraussSimplify waiting loops
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2020-07-06 Cesar StraussFinally add some well needed comments
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2020-07-06 Cesar StraussSimplify waiting loops
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2020-07-06 Cesar StraussAdd some wait states in each process
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2020-07-06 Cesar StraussNegate inputs after use
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2020-07-06 Cesar StraussAdd other tests
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2020-07-06 Cesar StraussImplement receiver
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2020-07-06 Cesar StraussImplement sender.
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2020-07-06 Cesar StraussBegin a new parallel test
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2020-07-02 Cesar StraussPresent the ALU result only when valid_o is active
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2020-06-28 Cesar StraussStart with a simpler test case
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2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
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2020-06-28 Cesar StraussAdd missing ports to the test ALU
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2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
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2020-06-09 Cesar StraussKeep the sequencer in the "done" state until ready_i...
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2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
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2020-06-07 Cesar StraussAssign the one-clock delay operation from ADD to SHR
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2020-06-07 Cesar StraussTry responding with ready_i on the same cycle as valid_o
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2020-06-07 Cesar StraussAssert valid_o one clock early, as alu_done is asserted
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2020-06-07 Cesar StraussMake the test ALU conform to the valid/ready protocol
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2020-06-03 Cesar StraussCheck completion of the sub-processes
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2020-06-03 Cesar StraussSimplify immediate check
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2020-06-03 Cesar StraussPreliminary check of the alu protocol
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2020-06-03 Cesar StraussPass along the operand, in the cycle in which go is...
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2020-06-02 Cesar StraussAllow at least one operand to be fetched
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2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
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2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
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2020-05-29 Cesar StraussAllow immediate assertion of go in the same cycle as rel
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2020-05-29 Cesar StraussCorrect typo
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2020-05-29 Cesar StraussSend a one-clock "go" pulse after a configurable number...
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2020-05-28 Cesar StraussCheck that rd rises after issue_i, unless it's immediate
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2020-05-28 Cesar StraussStore and present parameters together with issue_i
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2020-05-27 Cesar StraussMove test case parameters to an "operation" member...
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2020-05-27 Cesar StraussRemove the monitor process
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2020-05-25 Cesar StraussCheck that busy_o doesn't rise on its own
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2020-05-25 Cesar StraussImplement the issue_i/busy_o protocol check.
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2020-05-25 Cesar StraussMove process list to CompUnitParallelTest
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2020-05-25 Cesar StraussFix detection of busy_o inside the monitor process
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2020-05-25 Cesar StraussProof of concept of a parallel test
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2020-05-25 Cesar StraussShow oper_r and oper_i in the signal list, in simulation
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2020-05-24 Cesar StraussAvoid overwriting the first vcd file with the second one
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2020-05-24 Cesar StraussRename the internal DFF of latchregisters to avoid...
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2020-05-23 Cesar StraussAdd a few test cases with zero_a set, in combination...
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2020-05-23 Cesar StraussAllow zero_a to be set when simulating an operation
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2020-05-23 Cesar StraussChoose between RA (src1) and zero immediate, conditioned...
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2020-05-21 Cesar StraussFixed typo and left-over from refactoring
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