2020-08-17 |
Luke Kenneth Casson... | turn SelectableInt less/greater into signed versions.
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2020-08-17 |
Luke Kenneth Casson... | use longer memtest in litex sim
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2020-08-17 |
Luke Kenneth Casson... | adjust litex bios cmp test
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2020-08-17 |
Luke Kenneth Casson... | fix signed variants of cmp in alu
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2020-08-17 |
Luke Kenneth Casson... | add new cmp test for alu
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2020-08-17 |
Luke Kenneth Casson... | use shift module in mmu. to be moved to nmutil
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2020-08-16 |
Luke Kenneth Casson... | attempting to track down bug in litex bios memtest
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2020-08-16 |
Luke Kenneth Casson... | read delay on getting regfile data
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2020-08-16 |
Luke Kenneth Casson... | limit debug reporting in litex sim to range of pc
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2020-08-16 |
Luke Kenneth Casson... | cmp test from litex bios
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2020-08-16 |
Luke Kenneth Casson... | remove vhdl comments
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2020-08-16 |
Luke Kenneth Casson... | use simple one-line mask-generation
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2020-08-16 |
Luke Kenneth Casson... | fix LD/ST pimem issue with rising_edge detection
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2020-08-16 |
Luke Kenneth Casson... | missing vars, spelling corrections
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2020-08-16 |
Luke Kenneth Casson... | big reorg, shuffle code to functions, makes the FSM...
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2020-08-16 |
Luke Kenneth Casson... | spelling error, move perm_ok to local
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2020-08-16 |
Luke Kenneth Casson... | more comment removal
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2020-08-16 |
Luke Kenneth Casson... | more remove comments
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2020-08-16 |
Luke Kenneth Casson... | removing more comments, tidyup
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2020-08-16 |
Luke Kenneth Casson... | restore incorrect removal of zero-Cat at LHS (should...
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2020-08-16 |
Luke Kenneth Casson... | continue tidyup, comment removal/review. use byte_reverse...
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2020-08-16 |
Luke Kenneth Casson... | fix batch of syntax errors found by running mmu.py
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2020-08-16 |
Luke Kenneth Casson... | begin tidyup, removing comments after line-by-line...
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2020-08-15 |
Luke Kenneth Casson... | thanks to daveshah, added simulation of dram
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2020-08-15 |
Luke Kenneth Casson... | rather big change to interaction between regfile and...
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2020-08-15 |
Luke Kenneth Casson... | clear compalu data latch always on issue
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2020-08-14 |
Luke Kenneth Casson... | remove latchregister, use sync to capture compunit...
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2020-08-14 |
Luke Kenneth Casson... | ha! "state" (pc, msr) not properly passed to core
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2020-08-14 |
Luke Kenneth Casson... | drop in insn_state synchronously in issuer, at same...
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2020-08-14 |
Luke Kenneth Casson... | submodule update
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2020-08-14 |
Luke Kenneth Casson... | hrfid unit test sets up HSRR0 and HSRR1
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2020-08-14 |
Luke Kenneth Casson... | bad hack to get HSRR0/1 to be "same" as SRR0/1
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2020-08-14 |
Luke Kenneth Casson... | bug in isa parser not recognising MSR as declared variable
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2020-08-14 |
Luke Kenneth Casson... | hack to get hrfid not to alter msr 51
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2020-08-14 |
Luke Kenneth Casson... | stop trying to read swap files
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2020-08-14 |
Luke Kenneth Casson... | sync on alu results in compalu
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2020-08-14 |
Luke Kenneth Casson... | update submodule, add hrfid
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2020-08-14 |
Luke Kenneth Casson... | update submodule, add hrfid
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2020-08-14 |
Luke Kenneth Casson... | finally, fix decoder combinatorial loop
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2020-08-14 |
Luke Kenneth Casson... | fix test_compunit.py after moving decoder rdflags function
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2020-08-14 |
Luke Kenneth Casson... | add hrfid unit test
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2020-08-14 |
Luke Kenneth Casson... | sync up the core decode-execute state,
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2020-08-14 |
Luke Kenneth Casson... | move instruction decoder out of core
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2020-08-14 |
Luke Kenneth Casson... | move regspec / rdflag decoding functions out of PowerDecode2
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2020-08-14 |
Luke Kenneth Casson... | sort out instruction stop/cancel when adding a new...
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2020-08-14 |
Luke Kenneth Casson... | put multi-ports back (for read) on int and fast regfiles
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2020-08-14 |
Luke Kenneth Casson... | reduce decoder pathways when exception occurs
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2020-08-14 |
Luke Kenneth Casson... | divide shiftrot pipeline into 2 (simple last)
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2020-08-14 |
Luke Kenneth Casson... | divide alu pipeline into 2 (simple last)
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2020-08-14 |
Luke Kenneth Casson... | divide logical pipe into 2 (simple phase last)
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2020-08-13 |
Luke Kenneth Casson... | fix dmi reg read
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2020-08-13 |
Luke Kenneth Casson... | code-shuffle
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2020-08-13 |
Luke Kenneth Casson... | remove use of latchregigister, replace with sync on...
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2020-08-13 |
Luke Kenneth Casson... | sync on pc writing when changed
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2020-08-13 |
Luke Kenneth Casson... | sync on reset in compalu
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2020-08-13 |
Luke Kenneth Casson... | add forwarding-bus mode to Regfile Memory (and disable it)
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2020-08-13 |
Luke Kenneth Casson... | sync on port interface address in ld/st compunit, and...
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2020-08-13 |
Luke Kenneth Casson... | another sync to cut latency
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2020-08-13 |
Luke Kenneth Casson... | remove latchregister, sync src oper_i into MultiCompUnit
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2020-08-13 |
Luke Kenneth Casson... | minor tidyup on alu compunit:
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2020-08-13 |
Luke Kenneth Casson... | plenty of time to wait for operand, so use "sync" in...
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2020-08-13 |
Luke Kenneth Casson... | sigh. convert Fast regfile to binary
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2020-08-13 |
Luke Kenneth Casson... | sync on read of regfile ports
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2020-08-13 |
Luke Kenneth Casson... | sigh. convert INT regfile to binary addressing
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2020-08-13 |
Luke Kenneth Casson... | create a RegFileMem class that uses Memory
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2020-08-11 |
Luke Kenneth Casson... | sigh, remove yet another int regfile read port
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2020-08-11 |
Luke Kenneth Casson... | massive reduction in gate count by using alternative...
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2020-08-11 |
Luke Kenneth Casson... | reduce regfile port usage for INT and FAST
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2020-08-11 |
Luke Kenneth Casson... | prepare write ports to be shared
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2020-08-11 |
Luke Kenneth Casson... | move write regfile picker creation to new function
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2020-08-11 |
Luke Kenneth Casson... | reduce regfile ports by creating separate STATE regfile
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2020-08-11 |
Luke Kenneth Casson... | whoops fix change of variable (state) msr/pc
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2020-08-11 |
Luke Kenneth Casson... | reducing regfile port usage by sharing read ports
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2020-08-09 |
Luke Kenneth Casson... | stop combinatorial loop in pi2ls
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2020-08-09 |
Luke Kenneth Casson... | write pulse in issuer
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2020-08-09 |
Luke Kenneth Casson... | fix combinatorial loop in ldst compunit
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2020-08-09 |
Luke Kenneth Casson... | use rising edge detection on st go_i/rel_o
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2020-08-09 |
Luke Kenneth Casson... | add logical test issuer case
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2020-08-09 |
Luke Kenneth Casson... | get rid of MSR read combinatorial loop
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2020-08-09 |
Luke Kenneth Casson... | delay go_st by one cycle, break combinatorial loop
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2020-08-09 |
Luke Kenneth Casson... | divwo case makes test_issuer stay busy!
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2020-08-09 |
Luke Kenneth Casson... | add extra divwo regression test
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2020-08-09 |
Luke Kenneth Casson... | compalu combinatorial loop detected
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2020-08-06 |
Luke Kenneth Casson... | fix LDST PortInterface FSM interaction
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2020-08-06 |
Luke Kenneth Casson... | MULS on parameter b needed to check whether it was...
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2020-08-05 |
Luke Kenneth Casson... | rename ibus/dbus (shorten)
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2020-08-05 |
Luke Kenneth Casson... | clear sel on loadstore
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2020-08-05 |
Luke Kenneth Casson... | adding bus data width of 64 in litex sim doesnt work
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2020-08-05 |
Luke Kenneth Casson... | add div test cases into test_issuer.py
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2020-08-05 |
Luke Kenneth Casson... | add div FSM as default for test_issuer in verilog and...
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2020-08-04 |
Luke Kenneth Casson... | read/set pc outside of FSM so that DMI interface can...
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2020-08-04 |
Luke Kenneth Casson... | swap over byte-reverse if/else in LDSTCompUnit
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2020-08-04 |
Luke Kenneth Casson... | tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
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2020-08-04 |
Luke Kenneth Casson... | whitespace after autopep8 messed up
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2020-08-04 |
Luke Kenneth Casson... | msr and pc moved to "state" in PowerDecode2
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2020-08-04 |
Luke Kenneth Casson... | whoops must output NIA not PC to debug DMI query in...
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2020-08-04 |
Luke Kenneth Casson... | allow instruction to run if initiated whilst "stopped...
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2020-08-04 |
Luke Kenneth Casson... | cycle through INT regs, read and debug in litex sim
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2020-08-04 |
Luke Kenneth Casson... | add DMI debug interface to libresoc litex sim
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2020-08-04 |
Luke Kenneth Casson... | single-step and print out PC using DMI in litex sim
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