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add python3 env-var if not set in Makefile
2020-06-06
Luke Kenneth Casson...
add python3 env-var if not set in Makefile
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2020-06-06
Luke Kenneth Casson...
experimenting with setting up and testing memory
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2020-06-06
Luke Kenneth Casson...
expand regwid to 64 in l0_cache test
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2020-06-06
Luke Kenneth Casson...
work out how to initialise memory directly
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2020-06-06
Luke Kenneth Casson...
initialise L0 Memory from simulator memory
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2020-06-06
Luke Kenneth Casson...
wait a little for wr.rel to activate if wrmask is active
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2020-06-06
Luke Kenneth Casson...
missing test.mem arg for ISA in test_core
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2020-06-06
Luke Kenneth Casson...
allow Mem initialisation in ISACaller
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2020-06-06
Luke Kenneth Casson...
shift-mask in Simulator Mem class not quite right
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2020-06-06
Luke Kenneth Casson...
write-mask made from LD and Update mode (for data_o...
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2020-06-06
Luke Kenneth Casson...
allow Mem in Simulator to be initialised
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2020-06-06
Luke Kenneth Casson...
use name of unit to write simulator/vcd file
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2020-06-06
Luke Kenneth Casson...
LDSTCompUnit test data structures linked up, starting...
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2020-06-06
Luke Kenneth Casson...
allow CompLDSTOpSubset to be passed through to LDSTCompUnit
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2020-06-06
Luke Kenneth Casson...
set up LDSTCompUnit using regspec
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2020-06-06
Luke Kenneth Casson...
add extra bugreport link
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2020-06-06
Luke Kenneth Casson...
whitespace
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2020-06-06
Luke Kenneth Casson...
whitespace indentation
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2020-06-06
Luke Kenneth Casson...
add special-case LDSTFunctionUnit
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2020-06-06
Luke Kenneth Casson...
whoops dest%d_o not dest%d_i
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2020-06-06
Luke Kenneth Casson...
add beginnings of LDST compunit test
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2020-06-06
Luke Kenneth Casson...
whitespace
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2020-06-06
Luke Kenneth Casson...
whitespace / code-munge
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2020-06-06
Luke Kenneth Casson...
comments / whitespace
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2020-06-06
Luke Kenneth Casson...
update stage docstring
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2020-06-06
Luke Kenneth Casson...
code-munge
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2020-06-06
Luke Kenneth Casson...
remove unneeded imports
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2020-06-06
Luke Kenneth Casson...
noticed the regular pattern in all pipe_data.py (regspecs).
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2020-06-05
Luke Kenneth Casson...
comment out CR assertion for now
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2020-06-05
Luke Kenneth Casson...
update comments
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2020-06-05
Luke Kenneth Casson...
add comments and start of elaborate
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2020-06-05
Luke Kenneth Casson...
more comments
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2020-06-05
Luke Kenneth Casson...
more comments
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2020-06-05
Luke Kenneth Casson...
a_i not b_in
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2020-06-05
Luke Kenneth Casson...
add comments
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2020-06-05
Luke Kenneth Casson...
experimenting with CR, not quite right
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2020-06-05
Luke Kenneth Casson...
whoops returning cr2 for cr3 regspec map
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2020-06-05
Luke Kenneth Casson...
name regfile ports by name not numerical position
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2020-06-05
Luke Kenneth Casson...
whoops connecting up CR in wrong order. fixing with...
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2020-06-05
Luke Kenneth Casson...
fix syntax errors and use correct FastRegs (SRR0/1...
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2020-06-05
Luke Kenneth Casson...
add TODO for MFSPR/MTSPR
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2020-06-05
Luke Kenneth Casson...
refer to srr0/1 not a/b
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2020-06-05
Luke Kenneth Casson...
add msr_copy function and use it in OP_TRAP, OP_RFID...
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2020-06-05
Luke Kenneth Casson...
set SRR0 in OP_SC
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2020-06-05
Luke Kenneth Casson...
add OP_RFID SRR0/SRR1 in PowerDecode2
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2020-06-04
Luke Kenneth Casson...
testing CRs after writing: not in the right bit-order
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2020-06-04
Luke Kenneth Casson...
remove unneeded code
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2020-06-04
Luke Kenneth Casson...
use common TestCase class in logical
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2020-06-04
Luke Kenneth Casson...
add branch test case to core
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2020-06-04
Luke Kenneth Casson...
no global variables in test suites
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2020-06-04
Luke Kenneth Casson...
sigh. because POWER. CR index inversion
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2020-06-04
Luke Kenneth Casson...
sigh. weirdness involving bit-inversion, inconsistency...
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2020-06-04
Luke Kenneth Casson...
no global variables in test suites
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2020-06-04
Luke Kenneth Casson...
add ShiftRot test case (works only because CRs are...
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2020-06-04
Luke Kenneth Casson...
add both logical and ALU test core
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2020-06-04
Luke Kenneth Casson...
no global variables in test suites
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2020-06-04
Luke Kenneth Casson...
no global variables in test suites
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2020-06-04
Luke Kenneth Casson...
no global variables in test suites
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2020-06-04
Luke Kenneth Casson...
whoops, docstring indentation
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2020-06-04
Luke Kenneth Casson...
add docstrings for read/write port connection
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2020-06-04
Luke Kenneth Casson...
move core code into separate functions, for clarity
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2020-06-04
Luke Kenneth Casson...
reduce amount of code in SelectableInt
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2020-06-04
Luke Kenneth Casson...
oops forgot to switch write-enable off
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2020-06-04
Luke Kenneth Casson...
comment clarify on core
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2020-06-04
Luke Kenneth Casson...
initialise XER from simulation
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2020-06-04
Luke Kenneth Casson...
messing with valid/busy signals in core test
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2020-06-04
Luke Kenneth Casson...
add extra argument (not used) to regfile.py
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2020-06-04
Luke Kenneth Casson...
hmmm sync-delay wport write and wen
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2020-06-04
Luke Kenneth Casson...
whitespace
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2020-06-04
Luke Kenneth Casson...
test actual reg values being produced in core test
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2020-06-04
Luke Kenneth Casson...
use common TestCase in branch
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2020-06-04
Luke Kenneth Casson...
use common TestCase in shift_rot
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2020-06-04
Luke Kenneth Casson...
use common TestCase in alu
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2020-06-04
Luke Kenneth Casson...
move TestCase to common location
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2020-06-04
Luke Kenneth Casson...
move reg setup to earlier in test
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2020-06-04
Luke Kenneth Casson...
comment out wrflag as it should already be in the fu...
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2020-06-04
Luke Kenneth Casson...
test against Logical (hard-coded change)
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2020-06-04
Luke Kenneth Casson...
add first cut at test core
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2020-06-04
Luke Kenneth Casson...
sync onto fu.go_wr_i otherwise a loop occurs
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2020-06-04
Luke Kenneth Casson...
add rdmask and issue/busy setting
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2020-06-04
Luke Kenneth Casson...
remove unneeded imports
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2020-06-04
Luke Kenneth Casson...
use copy of FHDLTestCase
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2020-06-04
Luke Kenneth Casson...
connect up write-ports from Regfiles to FUs
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2020-06-04
Luke Kenneth Casson...
docstring for AllFunctionUnits
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2020-06-04
Luke Kenneth Casson...
missing a fastregs write-port
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2020-06-04
Luke Kenneth Casson...
update docstring on simple/core.py
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2020-06-04
Luke Kenneth Casson...
move regfile/spec organiser to separate function
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2020-06-04
Luke Kenneth Casson...
mention convenience variables
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2020-06-04
Luke Kenneth Casson...
rename trap to use convenience variables
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2020-06-04
Luke Kenneth Casson...
collate fu-enable signals
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2020-06-04
Luke Kenneth Casson...
connect up Function Unit operand subsets
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2020-06-03
Luke Kenneth Casson...
forgot to add in rdflag enable
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2020-06-03
Luke Kenneth Casson...
whoops, regfiles are uppercase
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2020-06-03
Luke Kenneth Casson...
whoops needed a bit of a reorg of the data structure...
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2020-06-03
Luke Kenneth Casson...
hmmm got naming wrong in regfile-fu connectivity
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2020-06-03
Luke Kenneth Casson...
whoops names of regfiles are lower-case
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2020-06-03
Luke Kenneth Casson...
munge/redirect the regfile port based on the naming
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2020-06-03
Luke Kenneth Casson...
connect read-enable and src_i to regfile ports
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2020-06-03
Luke Kenneth Casson...
link up PriorityPickers on read channels
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2020-06-03
Luke Kenneth Casson...
put rdspecs into a different dictionary
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