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2020-07-21	Luke Kenneth Casson...	set ISACaller.msr rather than namespace[MSR]	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	when running an exception (trap) after "reset" must...	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	spurious imports of FHDLTestCase, should be from nmutil	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	add PC (CIA) to PowerDecode2 "state" for passing into...	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	add msr exception bits setting function in hardware	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	make cxxsim optional and print warning	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	corrections to trap proof see	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	use alias for msr_i in trap proof	commit \| commitdiff \| tree
2020-07-21	Luke Kenneth Casson...	correct trap spec page interrupt ref	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	do not start core in terminated mode	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	explicitly set up a pc_i_ok signal in test_microwatt.py	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	expose core_stop_i to outside as well	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	set go_insn_i to non-resetless	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	add issuer verilog generator	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	update to expose signals at top-level of issuer	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	convert compalu multi test to Simulator() (was run_simulation)	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	convert compalu multi test to Simulator() (was run_simulation)	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	use same write_vcd for cxxsim as pysim	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	fix bug in alu_fsm.py found by cxxsim: missing one...	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	add some CompUnit demo tests of the alu_fsm example	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	move sdir to CompFSMOpSubset in alu_fsm example	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	add CompFSMOpSubset, also change dir to sdir	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	remove unneeded import	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	if nmigen.sim.pysim import fails use nmigen.back.pysim	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	use iocontrol PrevControl / NextControl instead of...	commit \| commitdiff \| tree
2020-07-19	Luke Kenneth Casson...	add DivTestCase to test_issuer.py (commented out for...	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	worked out that DivPipeSpec can be given a default...	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	missing conversion of DIV to Div	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	add option to generate verilog	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	whoops use slice not range	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	syntax error	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	add SR latch cxxrtl backend demo	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	add comment and copy of pseudo-code for OP_RFID into...	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	review of OP_RFID showed up some errors	commit \| commitdiff \| tree
2020-07-18	Luke Kenneth Casson...	corrections to trap main_stage.py OP_RFID according...	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	comment explaining why not to call self.trap in PowerDecode2	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	likewise cut across latest Minerva loadstore with line...	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	sigh easier to just do a line-for-line comparison of...	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	port minerva cache fixes	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	forward-port minerva loadstore bugfix	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	comments	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	submodule update (again. sigh)	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	use convenience vars in spr proof	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-07-17	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	whoops tried doing mtspr priv, it failed but failed...	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	get shiftrot compunit working	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	more tidyup on use of CompOpSubsetBase	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	use CompOpSubsetBase in ldst record	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	sigh, bug in sprset.patch	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	update cr input record to use new CompOpSubsetBase	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	add regression test on setb simulator error	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	use CompOpSubsetBase class in Branch op record	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	get branch compunit working (missing bigendian arg)	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	get trap compunit test working, adding bigendian and msr	commit \| commitdiff \| tree
2020-07-16	Luke Kenneth Casson...	add mfmsr trap tests	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	use new CompOpSubsetBase in trap	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	remove unneeded comment in trap msin stage	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	remove unneeded comment in trap pipe_data	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	document branch pipeline relationship with PowerDecode2	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	simplify instr_is_priv	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	move traptype to soc.consts	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	add better comments on mul overflow	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	test privileged rfid call	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	spelling error	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	range of testing overflow was incorrect in mul	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	set MSR up properly for privileged mtmsr test	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	whoops forgot to update PC after trap in ISACaller	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	move priv test to above illegal/trap test	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	comments on IntegerData class	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	import PipeContext not FPPipeContext	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	minor reorg on PowerDecoder2, use switch/case rather...	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	comments on SPRmap done in PowerDecode2	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	comments on SPRmap done in PowerDecode2	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	use case statement in PowerDecode2	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	select RA based on LDSTMode.update in PowerDecode2	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	add cache cx to LDSTMode	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	remove unused class XerBits	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	use Record Assert and also check muxid	commit \| commitdiff \| tree
2020-07-15	Luke Kenneth Casson...	no need to check individual port members, just check...	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	cookie-cut setup from alu proof_main_stage.py	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	reduce code size by using CompOpSubsetBase for ALU...	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	split out CompOpSubsetBase (meaning to do for a while)	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	update docstrings	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	adding MSR.PR unit test intended to activate privileged...	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	attempting to access self.msr directly	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	set up masks for OP_RL* formal proof	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	add priv instruction checking to ISACaller simulator	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	add in privileged instruction decision-making in PowerDecode2	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	add MSR reading to issue FSM	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	comments on PowerDecode2	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	add MSR to PowerDecoder2	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	disable cxxsim test	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	attempting running cxxsim on ALU pipeline test	commit \| commitdiff \| tree
2020-07-14	Luke Kenneth Casson...	first attempt running cxxsim	commit \| commitdiff \| tree
2020-07-13	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-07-13	Luke Kenneth Casson...	formal proof of OP_EXTSWSLI	commit \| commitdiff \| tree
2020-07-13	Luke Kenneth Casson...	quick test showing how left/right mask work	commit \| commitdiff \| tree
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