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add a DIVS function as separate and discrete from floor_div
2020-07-05 Luke Kenneth Casson... stop debug output in power_decoder
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2020-07-05 Luke Kenneth Casson... comments in power_regspec_map.py
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2020-07-05 Luke Kenneth Casson... comment on spr2, not needed
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2020-07-05 Luke Kenneth Casson... check xer_out not xer_in
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2020-07-05 Luke Kenneth Casson... split out Decode2ToExecuteType fields involving registers
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2020-07-05 Luke Kenneth Casson... sigh read and write xer detection, fix spr and trap...
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2020-07-05 Luke Kenneth Casson... check spr1 in test spr compunit
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2020-07-05 Luke Kenneth Casson... get/set slow spr in spr test_pipe_caller
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2020-07-05 Luke Kenneth Casson... add first spr compunit test (not working yet)
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2020-07-05 Luke Kenneth Casson... add SPR test case, commented out for now
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2020-07-05 Luke Kenneth Casson... move valid signal out of Decode2ToExecute1Type and...
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2020-07-05 Luke Kenneth Casson... add slow spr regfile regspec support
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2020-07-05 Luke Kenneth Casson... remap SPR PowerISA numbers to internal SPR enum
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2020-07-05 Luke Kenneth Casson... comment out SPR for now, needs SPR regfile
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2020-07-05 Luke Kenneth Casson... add SPR compunit
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2020-07-05 Luke Kenneth Casson... missing initialisation of disasm_start
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2020-07-05 Luke Kenneth Casson... check NIA on trap fu test
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2020-07-05 Luke Kenneth Casson... OP_RFID needs to read SRR0/1, OP_SC needs to write
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2020-07-05 Luke Kenneth Casson... fix qemu trap test
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2020-07-04 Luke Kenneth Casson... cater for illegal instruction (generates a trap)
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2020-07-04 Luke Kenneth Casson... add sc back in
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2020-07-04 Luke Kenneth Casson... comments in trap about exceptions using microcoding
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2020-07-04 Luke Kenneth Casson... add pspec to test_core.py
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2020-07-04 Luke Kenneth Casson... add pspec to test_core.py
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2020-07-04 Luke Kenneth Casson... more rename spr1/spr2 to fast1/fast2
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2020-07-04 Luke Kenneth Casson... whitespace
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2020-07-04 Luke Kenneth Casson... more updating spr1/spr2 to fast1/fast2
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2020-07-04 Luke Kenneth Casson... more updating spr1/spr2 to fast1/fast2
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2020-07-04 Luke Kenneth Casson... rename spr1/spr2 to fast1/fast2 in branch
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2020-07-04 Luke Kenneth Casson... update trap docstring
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2020-07-04 Luke Kenneth Casson... use new consts module
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2020-07-04 Luke Kenneth Casson... sorting out trap fastregs
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2020-07-04 Luke Kenneth Casson... sort out trap test reg checking
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2020-07-04 Luke Kenneth Casson... resolve spr names in ISACaller
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2020-07-04 Luke Kenneth Casson... rename spr1 to fast1 in trap data
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2020-07-04 Luke Kenneth Casson... sorting out fast/spr naming
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2020-07-04 Luke Kenneth Casson... oops initialise Function Unit class with idx
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2020-07-04 Luke Kenneth Casson... add first cookie-cut test_trap_compunit.py
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2020-07-04 Luke Kenneth Casson... add gitignores
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2020-07-04 Luke Kenneth Casson... debugging decoding of SPRs (fast)
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2020-07-04 Luke Kenneth Casson... add spr test, add decode of spr in/out
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2020-07-04 Luke Kenneth Casson... add spr main stage
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2020-07-04 Luke Kenneth Casson... add spr input record
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2020-07-04 Luke Kenneth Casson... add SPR pipeline
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2020-07-04 Luke Kenneth Casson... reduce steps per stage to 8
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2020-07-03 Luke Kenneth Casson... set only div/rem supported
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2020-07-02 Luke Kenneth Casson... allow flexible selection of the types of ALUs
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2020-07-02 Luke Kenneth Casson... fix unit tests due to change in using pspec
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2020-07-02 Luke Kenneth Casson... use Mock class (more convenient)
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2020-07-02 Luke Kenneth Casson... allow ALU names to propagate through from FU to CompUnit ALU
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2020-07-02 Luke Kenneth Casson... name function unit ALUs
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2020-07-02 Luke Kenneth Casson... comment out DIV unit for now
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2020-07-02 Luke Kenneth Casson... increase combinatorial stages to 8
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2020-07-02 Luke Kenneth Casson... reduce DIV radix to 1
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2020-07-02 Luke Kenneth Casson... add DIV function unit to compunits
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2020-07-02 Luke Kenneth Casson... add trap function unit into compunits
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2020-07-02 Luke Kenneth Casson... add bare wishbone option to TestIssuer, sort out ports
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2020-07-02 Luke Kenneth Casson... use single-arg pspec for TestIssuer and Core
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2020-07-02 Luke Kenneth Casson... first experimental index.rst for sphinx documentation
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2020-07-02 Luke Kenneth Casson... add sphinx doc preliminary start
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2020-07-01 Luke Kenneth Casson... whoops missed some cases in unit test changing ALUHelpers
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2020-07-01 Luke Kenneth Casson... minor reorg on how Bus and Config classes are set up
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2020-07-01 Luke Kenneth Casson... whoops swapped trap test instructions accidentally
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2020-07-01 Luke Kenneth Casson... print out msr for debug
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2020-07-01 Luke Kenneth Casson... attempting to add SPRs to rfid test
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2020-07-01 Luke Kenneth Casson... add OP_SC
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2020-07-01 Luke Kenneth Casson... trap test check results
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2020-07-01 Luke Kenneth Casson... add name "test_issuer" to ilang conversion
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2020-07-01 Luke Kenneth Casson... add in trap compunit
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2020-07-01 Luke Kenneth Casson... add rfid and td/tw trap test
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2020-07-01 Luke Kenneth Casson... continue debugging trap pipeline
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2020-07-01 Luke Kenneth Casson... debugging trap pipeline
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2020-07-01 Luke Kenneth Casson... start running trap unit test, fixing errors
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2020-06-30 Luke Kenneth Casson... add lte ltu for use by twi and other trap functions
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2020-06-30 Luke Kenneth Casson... add in pseudocode keyword into mdwn isa files
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2020-06-30 Luke Kenneth Casson... code-morph on div pipeline
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2020-06-29 Luke Kenneth Casson... add README for fu directory
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2020-06-29 Luke Kenneth Casson... use correct ALUHelpers in div test
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2020-06-29 Luke Kenneth Casson... sort out syntax errors in div
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2020-06-29 Luke Kenneth Casson... first unit test for div
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2020-06-29 Luke Kenneth Casson... update submodule to fix div bug
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2020-06-29 Luke Kenneth Casson... add ignore for parsetab.py
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2020-06-29 Luke Kenneth Casson... add autogenerated do not commit comment
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2020-06-29 Luke Kenneth Casson... update submodule to div overflow
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2020-06-29 Luke Kenneth Casson... separate out divide by zero cases
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2020-06-29 Luke Kenneth Casson... update OV and OV32 ISACaller flags if overflow occurs
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2020-06-29 Luke Kenneth Casson... attempting to add overflow setting in ISACaller
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2020-06-29 Luke Kenneth Casson... whoops, hex parser digits are in multiples of 4 bits
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2020-06-29 Luke Kenneth Casson... fetch instructions from bare wishbone fetch unit
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2020-06-28 Luke Kenneth Casson... add cached fetch unit pass-through args
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2020-06-28 Luke Kenneth Casson... need args to WishboneArbiter, match data width size
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2020-06-28 Luke Kenneth Casson... read from instruction memory using FetchUnitInterface
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2020-06-28 Luke Kenneth Casson... add Config Fetch interface and quick unit test
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2020-06-28 Luke Kenneth Casson... add test instruction memory
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2020-06-28 Luke Kenneth Casson... add readonly option to TestMemory
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2020-06-28 Luke Kenneth Casson... expand instruction bus width to 64 bit, start on a...
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2020-06-28 Luke Kenneth Casson... parameterise minerva i-cache
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2020-06-28 Luke Kenneth Casson... got Pi2LSUI FSM working
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2020-06-28 Luke Kenneth Casson... sram address do not cut by LSBs
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2020-06-28 Luke Kenneth Casson... new Pi2LSUI working, using PortInterfaceBase
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