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2020-10-21	Cole Poirier	versa_ecp5 adds ability to build and load for ulx3s85f...	commit \| commitdiff \| tree
2020-10-18	Cole Poirier	use random.seed to generate repro cases of the two...	commit \| commitdiff \| tree
2020-10-14	Cole Poirier	Makefile develop, when running setup.py develop specify...	commit \| commitdiff \| tree
2020-10-14	Cole Poirier	issuer_verilog.py update to use commandline args using...	commit \| commitdiff \| tree
2020-10-13	Cole Poirier	move pia from install_requires to test_requires	commit \| commitdiff \| tree
2020-10-12	Cole Poirier	litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5...	commit \| commitdiff \| tree
2020-10-12	Cole Poirier	fix ModuleNotFound/Import errors found when running...	commit \| commitdiff \| tree
2020-10-12	Cole Poirier	add tested working fpga compile/build/load file for...	commit \| commitdiff \| tree
2020-10-10	Cole Poirier	florent/versa_ecp5.py remove uneccessary imports, specify...	commit \| commitdiff \| tree
2020-10-08	Cole Poirier	second attempt at https://bugs.libre-soc.org/show_bug...	commit \| commitdiff \| tree
2020-10-08	Cole Poirier	remove singleton dict per https://bugs.libre-soc.org...	commit \| commitdiff \| tree
2020-10-08	Cole Poirier	first attempt at 3) of	commit \| commitdiff \| tree
2020-10-08	Cole Poirier	modify wb_get per 1) of https://bugs.libre-soc.org...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py fix ispow2() util fn per https://bugs.libre...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py add python asserts that were a TODO commented...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py fix formatting, mostly due to reduced indentation...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py remove comment that contained the entirety...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py move icache_miss WAIT_ACK FSM state into...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py move icache_miss CLR_TAG FSM state into method...	commit \| commitdiff \| tree
2020-10-05	Cole Poirier	icache.py move icache_miss IDLE FSM state into method...	commit \| commitdiff \| tree
2020-10-02	Cole Poirier	icache.py add req_hit_way as arg to icache_comb, actually...	commit \| commitdiff \| tree
2020-10-01	Cole Poirier	icache.py add missing comb signal assignments per https...	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py fix combinatorial loop with by testing temp...	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py fix is_last_row_addr, get_next_row_addr	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py trying to sort out test failure, added r...	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py fix test stbs_done signal, not stbs_zero...	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py fix rarange	commit \| commitdiff \| tree
2020-09-29	Cole Poirier	icache.py fixed numerous bugs as specified by lkcl...	commit \| commitdiff \| tree
2020-09-28	Cole Poirier	icache.py use d_out as input to assignment instead...	commit \| commitdiff \| tree
2020-09-27	Cole Poirier	icache.py fix translation mistake	commit \| commitdiff \| tree
2020-09-25	Cole Poirier	icache.py fix several subtle bugs that were lines that...	commit \| commitdiff \| tree
2020-09-25	Cole Poirier	wb_types.py add reset value of 0b11111111 for WBSelType...	commit \| commitdiff \| tree
2020-09-24	Cole Poirier	icache.py add some missing lines from icache.vhdl,...	commit \| commitdiff \| tree
2020-09-24	Cole Poirier	mem_types.py wb_types.py add name constructor to all...	commit \| commitdiff \| tree
2020-09-24	Cole Poirier	icache.py fixed all errors that raised python exceptions...	commit \| commitdiff \| tree
2020-09-16	Cole Poirier	complete first translation pass of dmi_dtm_xilinx.vhdl...	commit \| commitdiff \| tree
2020-09-16	Cole Poirier	initial commit of JTAGToDMI debug interface translated...	commit \| commitdiff \| tree
2020-09-16	Cole Poirier	add template file/starting point (copy of litex/boards...	commit \| commitdiff \| tree
2020-09-14	Cole Poirier	icache.py add missing funciton bodies, add missing...	commit \| commitdiff \| tree
2020-09-14	Cole Poirier	icache.py connect up all the sub-functions, fix typos...	commit \| commitdiff \| tree
2020-09-14	Cole Poirier	icache.py add parameters to 'process' functions, fix...	commit \| commitdiff \| tree
2020-09-13	Cole Poirier	icache.py move get/read/write functions out of ICache...	commit \| commitdiff \| tree
2020-09-13	Cole Poirier	icache.py copy simulation code from dcache.py, fix...	commit \| commitdiff \| tree
2020-09-13	Cole Poirier	icache.py fix syntax, move all constants and Array...	commit \| commitdiff \| tree
2020-09-13	Cole Poirier	icache.py fix syntax errors that occured when running...	commit \| commitdiff \| tree
2020-09-11	Cole Poirier	icache.py add test_icache and icache_sim derived from...	commit \| commitdiff \| tree
2020-09-11	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-09-11	Cole Poirier	icache.py fix spelling, syntax	commit \| commitdiff \| tree
2020-09-10	Cole Poirier	icache.py rearrange the code within the base class...	commit \| commitdiff \| tree
2020-09-09	Cole Poirier	icache.py complete first translation pass of icache...	commit \| commitdiff \| tree
2020-09-07	Cole Poirier	icache.py commit translation progress, about one third...	commit \| commitdiff \| tree
2020-08-30	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-30	Cole Poirier	icache.py commit progress, about a third through the...	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	mmu.py, dcache.py, mem_types.py change types capitalization...	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	mem_types add more types from common.vhdl specifially...	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	mem_types.py arrange in alphabetical order for ease...	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	mmu.py remove duplicate comment left over from mmu...	commit \| commitdiff \| tree
2020-08-29	Cole Poirier	icache.py initial commit of first attempt at translation...	commit \| commitdiff \| tree
2020-08-28	Cole Poirier	dcache.py add first attempt at translation of dcache_tb...	commit \| commitdiff \| tree
2020-08-27	Cole Poirier	dcache.py add skeleton sim and test adapted from mmu...	commit \| commitdiff \| tree
2020-08-27	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-27	Cole Poirier	dcache.py implement the remaining vhdl generate statements...	commit \| commitdiff \| tree
2020-08-26	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-26	Cole Poirier	dcache.py replace subtypes/types/constant aliases with...	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py rearrange, transform classes into functions...	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py fix whitespace, fomatting, syntax	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py fix formatting	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py move Reservation RecordObject to top of file	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py move RegStage1 RecordObject to top of file	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py move MemAccessRequest RecordObject to top...	commit \| commitdiff \| tree
2020-08-25	Cole Poirier	dcache.py move Stage0 RecordObject to top of file	commit \| commitdiff \| tree
2020-08-24	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-24	Cole Poirier	dcache.py commit first full tranlation pass, about...	commit \| commitdiff \| tree
2020-08-21	Cole Poirier	dcache.py fix asserts, use backslash and two strings...	commit \| commitdiff \| tree
2020-08-21	Cole Poirier	dcache.py replace functions that return signals with...	commit \| commitdiff \| tree
2020-08-21	Cole Poirier	wb_types fix typo	commit \| commitdiff \| tree
2020-08-21	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-21	Cole Poirier	dcache.py commit today and yesterday's progress (sorry...	commit \| commitdiff \| tree
2020-08-18	Cole Poirier	fu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov...	commit \| commitdiff \| tree
2020-08-17	Cole Poirier	dcache.py commit today's progress on translating dcache...	commit \| commitdiff \| tree
2020-08-17	Cole Poirier	Create file experiment/wb_types.py to mirror microwatt...	commit \| commitdiff \| tree
2020-08-16	Cole Poirier	mmu.py fix formatting 80 char limit	commit \| commitdiff \| tree
2020-08-15	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	commit \| commitdiff \| tree
2020-08-15	Cole Poirier	mmu.py fix Cat() semantics fixes https://bugs.libre...	commit \| commitdiff \| tree
2020-08-15	Cole Poirier	mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...	commit \| commitdiff \| tree
2020-08-15	Cole Poirier	mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...	commit \| commitdiff \| tree
2020-08-15	Cole Poirier	mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...	commit \| commitdiff \| tree
2020-08-13	Cole Poirier	dcache.py add initial imports	commit \| commitdiff \| tree
2020-08-13	Cole Poirier	mem_types.py add more types from common.vhdl	commit \| commitdiff \| tree
2020-08-13	Cole Poirier	move memory related types from mmu.py into new file...	commit \| commitdiff \| tree
2020-08-13	Cole Poirier	Initial commit of translation of microwatt dcache.vhdl...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	mmu.py add skeleton sim and test functions from regfile...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	Delete unnecessary mmu dir, move mmu.py out of mmu...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	Revert "Remove mmu dir and associated mmu/test/ dir...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	Remove mmu dir and associated mmu/test/ dir	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	Remove rst signals, fix len of hex Consts, fix variable...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	Create dir experiment/mmu then mmu/test with skeleton...	commit \| commitdiff \| tree
2020-08-12	Cole Poirier	mmu.py add RecordObject classes from common.vhdl input...	commit \| commitdiff \| tree
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