| 2020-07-24 |
Luke Kenneth Casson... | Revert "working on div's test_pipe_caller"
|
commit | commitdiff | tree |
| 2020-07-24 |
Luke Kenneth Casson... | bug found in pseudocode reader when assembly code has...
|
commit | commitdiff | tree |
| 2020-07-24 |
Luke Kenneth Casson... | submodule update
|
commit | commitdiff | tree |
| 2020-07-24 |
Luke Kenneth Casson... | code review comments for trap and proof
|
commit | commitdiff | tree |
| 2020-07-24 |
Luke Kenneth Casson... | made it clear what is meant by the slice numbering...
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | syntax error
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | support 32-bit mem width setting
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | try SDRAM SDR
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | allow imem to be 64/32 bit wide
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | begin core in running state
|
commit | commitdiff | tree |
| 2020-07-23 |
Luke Kenneth Casson... | try different MEMTEST_xxx sizes with 64 bit bus width
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | re-add CRG (clock reset generator)
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | missing ports from issuer, when doing verilog
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | add clock domain using snippet taken from random file
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | cleanup in litex core.py
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | update comments
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | add dummy irq set/get
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | add boot-helper.S etc from microwatt litex core
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | set additional MSR bits according to v3.0B spec when...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | use (new) MSRb and PIb which has auto-bigendian numbers
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | sigh, auto-create some little/big-endian classes for...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | missed import of Builder, set cpu_type to "None" temporarily
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | begin converting litex sim to libre-soc
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | whoops forgot field accessor
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | do not use wildcard import
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | start from vexriscv sim.py from
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | correct syntax error
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | first version of litex core (to be submitted upstream...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | whoops typo, 63-start not 3-start (doh)
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | field number ordering wrong way round?
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | syntax error
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | review trap main_stage.py modifications: we are not...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | comments, add page spec numbers for branch ops into...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | add comment headings with spec page numbers
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | comment on op.insn ordering
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | code-shuffle, add comments
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | add TT.size and use it in PowerDecoder and trap input...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | inline comments in trap proof
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | note that traptype MUST increase in bitwidth corresponding...
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | fix branch main_stage proof, add ctr 32-bit, fix BCREG
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | rework branch proof to use br_input_record
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | update README for pipe_data.py
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | reduce number of FastRegs read ports
|
commit | commitdiff | tree |
| 2020-07-22 |
Luke Kenneth Casson... | comments on what goes into CommonPipeSpec
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | convert branch pipeline to use msr/cia as immediates
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | put set_msr and set_cia back in for now
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | interesting bug in test_compunit.py when there are...
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | testing if MultiCompUnit can handle no input regs ...
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | disable cxxsim for now
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | move cia and msr to trap input record
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | set ISACaller.msr rather than namespace[MSR]
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | when running an exception (trap) after "reset" must...
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | spurious imports of FHDLTestCase, should be from nmutil
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | add PC (CIA) to PowerDecode2 "state" for passing into...
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | add msr exception bits setting function in hardware
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | make cxxsim optional and print warning
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | corrections to trap proof see
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | use alias for msr_i in trap proof
|
commit | commitdiff | tree |
| 2020-07-21 |
Luke Kenneth Casson... | correct trap spec page interrupt ref
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | do not start core in terminated mode
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | explicitly set up a pc_i_ok signal in test_microwatt.py
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | expose core_stop_i to outside as well
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | set go_insn_i to non-resetless
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | add issuer verilog generator
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | update to expose signals at top-level of issuer
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | convert compalu multi test to Simulator() (was run_simulation)
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | convert compalu multi test to Simulator() (was run_simulation)
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | use same write_vcd for cxxsim as pysim
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | fix bug in alu_fsm.py found by cxxsim: missing one...
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | add some CompUnit demo tests of the alu_fsm example
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | move sdir to CompFSMOpSubset in alu_fsm example
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | add CompFSMOpSubset, also change dir to sdir
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | remove unneeded import
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | if nmigen.sim.pysim import fails use nmigen.back.pysim
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | use iocontrol PrevControl / NextControl instead of...
|
commit | commitdiff | tree |
| 2020-07-19 |
Luke Kenneth Casson... | add DivTestCase to test_issuer.py (commented out for...
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | worked out that DivPipeSpec can be given a default...
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | missing conversion of DIV to Div
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | add option to generate verilog
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | whoops use slice not range
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | syntax error
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | add SR latch cxxrtl backend demo
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | add comment and copy of pseudo-code for OP_RFID into...
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | review of OP_RFID showed up some errors
|
commit | commitdiff | tree |
| 2020-07-18 |
Luke Kenneth Casson... | corrections to trap main_stage.py OP_RFID according...
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | comment explaining why not to call self.trap in PowerDecode2
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | likewise cut across latest Minerva loadstore with line...
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | sigh easier to just do a line-for-line comparison of...
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | port minerva cache fixes
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | forward-port minerva loadstore bugfix
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | submodule update (again. sigh)
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | use convenience vars in spr proof
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-07-17 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-07-16 |
Luke Kenneth Casson... | whoops tried doing mtspr priv, it failed but failed...
|
commit | commitdiff | tree |
| 2020-07-16 |
Luke Kenneth Casson... | get shiftrot compunit working
|
commit | commitdiff | tree |
| 2020-07-16 |
Luke Kenneth Casson... | more tidyup on use of CompOpSubsetBase
|
commit | commitdiff | tree |
| next |
projects / soc.git / search