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connect wishbone bus to test memory
2020-04-03
Tobias Platen
fix power_pseudo.py to work with latest nmigen
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2020-01-25
Tobias Platen
convert ram tp modules
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2020-01-24
Tobias Platen
translate slice_top and rab_slice from systemverilog...
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2020-01-23
Tobias Platen
add more converted header files
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2020-01-23
Tobias Platen
begin axi_rab to nmigen conversion
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2019-09-16
Tobias Platen
tlb_content now supports 512G pages
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2019-09-11
Tobias Platen
terapage lookup
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2019-09-10
Tobias Platen
tlb_content update test
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2019-09-09
Tobias Platen
add unittest for tlb_content.py
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2019-08-25
Tobias Platen
forgot to add one signal
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2019-08-24
Tobias Platen
add is_512G to the data structure
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2019-08-07
Tobias Platen
partial Unit Test for TLB
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2019-08-04
Tobias Platen
tlb_test WIP
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2019-07-25
Tobias Platen
Merge branch 'master' of https://git.libre-riscv.org...
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2019-07-25
Tobias Platen
fix UnusedElaboratable warning in TLB code
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2019-07-21
Tobias Platen
TLB testbench WIP
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