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whoops tried doing mtspr priv, it failed but failed by trying to run TRAP
2020-07-14 Tobias Platenfix path to nmigen-soc.git
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2020-07-13 Tobias Platenadd nmigen-soc to .gitlab-ci.yml
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2020-06-10 Tobias Platenmake resetless for all signals in DataMergerRecord
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2020-06-10 Tobias PlatenPortInterface refactoring
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2020-06-10 Tobias Platenexception if rolls in addr_split.py
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2020-06-09 Tobias Platenundo code removed by commit 12297566322355ce5fed2e2a5460bea5...
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2020-06-09 Tobias Platenelaborate function for DualPortSplitter
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2020-06-09 Tobias Platenfixes for DualPortSplitter
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2020-06-05 Tobias Platenfix proof_datamerger (see 216#c56)
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2020-06-05 Tobias Platenimplement init function of DualPortSplitter
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2020-06-05 Tobias Platenuncomment rtlil.convert in test_l0_cache that causes...
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2020-06-03 Tobias Platenmore work on proof_datamerger.py
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2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03 Tobias Platenwhitespace fix for proof_datamerger.py
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2020-06-02 Tobias Platenproof_datamerger: proof that output is zero when idle
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2020-06-01 Tobias Platenproof_datamerger wip
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2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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2020-05-30 Tobias Platenunit test for DataMerger
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2020-05-29 Tobias Platenfixes for DataMerger
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2020-05-29 Tobias PlatenDataMerger: rename addr_match_i to addr_array_i
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2020-05-29 Tobias Platenfixed 'return m is missing'
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2020-05-29 Tobias Platenwhitespace fixes
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2020-05-28 Tobias Platenindention
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2020-05-28 Tobias Platenunittest for DataMerger
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2020-05-28 Tobias Platenmore fixes for DataMerger
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2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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2020-05-28 Tobias Platenfixes for l0_cache.py
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2020-05-27 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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2020-05-27 Tobias Platenelaborate function for DataMerger
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2020-05-25 Tobias Platenfix own copy/paste error
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2020-05-25 Tobias Platenwhitespace fix in docstring
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2020-05-25 Tobias Platenrefactoring (see #216 Comment 43)
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2020-05-25 Tobias Platenwhitespace changes
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2020-05-25 Tobias Platenimplement DataMerger interface
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2020-05-22 Tobias Platenfix ModuleNotFoundError
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2020-05-15 Tobias Platenconverted countzero from microwatt
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2020-05-04 Tobias Platenupdate cr0 when rc is set
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2020-04-20 Tobias Platentestcase fo mulli
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2020-04-20 Tobias Platentestcase for addis
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2020-04-20 Tobias Platenadd with carry cleanup and test case
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2020-04-17 Tobias Platenadd with carry instructions
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2020-04-15 Tobias Platenfix a bug in QemuController.get_register
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2020-04-09 Tobias Platenfix 'Object is not an nMigen signal' error in test_sim.py
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2020-04-03 Tobias Platenfix power_pseudo.py to work with latest nmigen
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2020-01-25 Tobias Platenconvert ram tp modules
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2020-01-24 Tobias Platentranslate slice_top and rab_slice from systemverilog...
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2020-01-23 Tobias Platenadd more converted header files
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2020-01-23 Tobias Platenbegin axi_rab to nmigen conversion
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2019-09-16 Tobias Platentlb_content now supports 512G pages
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2019-09-11 Tobias Platenterapage lookup
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2019-09-10 Tobias Platentlb_content update test
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2019-09-09 Tobias Platenadd unittest for tlb_content.py
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2019-08-25 Tobias Platenforgot to add one signal
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2019-08-24 Tobias Platenadd is_512G to the data structure
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2019-08-07 Tobias Platenpartial Unit Test for TLB
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2019-08-04 Tobias Platentlb_test WIP
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2019-07-25 Tobias PlatenMerge branch 'master' of https://git.libre-riscv.org...
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2019-07-25 Tobias Platenfix UnusedElaboratable warning in TLB code
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2019-07-21 Tobias PlatenTLB testbench WIP
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