soc.git
13 min ago Luke Kenneth... in loadstore.py set align_intr from request which comes... master
16 min ago Luke Kenneth... driver conflict on priv_mode and virt_mode, do not...
111 min ago Luke Kenneth... fix up test_loadstore1.py
114 min ago Luke Kenneth... in loadstore.py, when an exception is done or if the FSM
115 min ago Luke Kenneth... fix PortInterfaceBase
117 min ago Luke Kenneth... fix up LDST test functions pi_ld and pi_st to respect...
3 hours ago Luke Kenneth... whitespace
4 hours ago Luke Kenneth... add misaligned ld/st to trigger an exception
4 hours ago Luke Kenneth... comment out dsisr and dar in mmu FSM for now
24 hours ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
24 hours ago Tobias Platencleanup test_compldst_multi_mmu.py
26 hours ago Luke Kenneth... add a bitvector remap function, the plan is to use...
27 hours ago Tobias Platenfix test_random in test_loadstore1
28 hours ago Luke Kenneth... use new namedtuple in core when calling regspec_decode()
28 hours ago Luke Kenneth... add module parameter to regspec_decode and therefore...
40 hours ago Jacob Lifshayremove bitmanip fu cuz ternlogi (the only instruction...
40 hours ago Jacob Lifshayadd ternlogi to shiftrot
41 hours ago Jacob Lifshayformat code
47 hours ago Luke Kenneth... stack of changes to MultiCompUnit to speed it up
2 days ago Luke Kenneth... experimenting with option to shorten MultiCompUnit...
2 days ago Luke Kenneth... create single-stage ALU pipeline, shorten latency on...
2 days ago Luke Kenneth... allow MultiCompUnit to set read and write latches to...
2 days ago Luke Kenneth... FunctionUnitBaseMulti which derives from ReservationSta...
2 days ago Luke Kenneth... better name for read latch in core.py
2 days ago Luke Kenneth... use m.submodules[name] instead of getattr
2 days ago Luke Kenneth... remove redundant / mis-named variable in core
2 days ago Luke Kenneth... code-comments
2 days ago Luke Kenneth... remove unneeded data structure in core
2 days ago Luke Kenneth... whoops treereduce on write-vector set/clr error
2 days ago Luke Kenneth... more code-cleanup
2 days ago Luke Kenneth... use new regspec_decode and fu.get_iospec functions
2 days ago Luke Kenneth... core tidyup
2 days ago Luke Kenneth... add Regspecs get_io_spec function
3 days ago Luke Kenneth... start allocating more FUs (more ReservationStations)
3 days ago Tobias Platenrandom loadstore1 test: readback written data
3 days ago Tobias Platenreenable dcbz test case
3 days ago Tobias Platenreturn correct data from microwatt
3 days ago Tobias Platencleanup test_loadstore1.py
3 days ago Tobias Platenloadstore: add done_delay
3 days ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
3 days ago Luke Kenneth... add LogicalTestCases back in to test_core.py (pass)
3 days ago Luke Kenneth... let PowerDecode2 decide which operand class to use...
3 days ago Luke Kenneth... use latched readflag (recspec_decode_read "ok") instead...
3 days ago Luke Kenneth... tidyup on read-flag latches
3 days ago Luke Kenneth... fix read-decode information by latching not just the...
3 days ago Luke Kenneth... fix write-after-write hazard checking
3 days ago Luke Kenneth... allow busy to settle before checking state in test_core.py
3 days ago Luke Kenneth... only check regs right at the end in test_core.py overla...
3 days ago Luke Kenneth... move sim call before core run in test_core.py
3 days ago Luke Kenneth... getting formerly unused test_core.py operational
4 days ago Luke Kenneth... whoops missed make_hazard_vec test
4 days ago Luke Kenneth... whoops do the set/get of the write-vector at a single...
4 days ago Luke Kenneth... always set fwd_bus_mode=False on regfiles
4 days ago Luke Kenneth... add MMU and SPR to list of FUs that must report "busy...
4 days ago Luke Kenneth... disallow overlap in core on LDST, Branch, and Trap.
4 days ago Luke Kenneth... use dict style not setattr on submodules
5 days ago Tobias Platenupdate loadstore1 testcase
6 days ago Luke Kenneth... code-comments
6 days ago Luke Kenneth... fix instructions of the type "read-reg-is-same-as-write"
6 days ago Tobias Platenloadstore testcase: read at random addresses
6 days ago Luke Kenneth... FU-Regs matrix tidyup and comments
6 days ago Luke Kenneth... minor tidyup on FU-Regs Matrix
6 days ago Luke Kenneth... update FURegDepMatrix to multi-dest
6 days ago Luke Kenneth... update naming on Reg_Rsv signals
6 days ago Luke Kenneth... add copyright and attribution notices
6 days ago Luke Kenneth... update FU_RW_Pending vectors to multi-dest
6 days ago Luke Kenneth... convert DependencyRow to multiple destination latches
6 days ago Luke Kenneth... add copyright and attribution notices to dependence_cell.py
6 days ago Luke Kenneth... update license and attribution in fu_reg_matrix.py
7 days ago Luke Kenneth... convert score6600_multi over to using RegSpecs (in...
7 days ago Luke Kenneth... early use of Array unnecessarily (all uses are static...
7 days ago Luke Kenneth... early use of Array unnecessarily (all uses are static...
7 days ago Luke Kenneth... get score6600_multi operational again
7 days ago Luke Kenneth... add debug prints in old simulator
7 days ago Luke Kenneth... add debug prints in old simulator
8 days ago Tobias Platenseperate invalid test case from other test cases
8 days ago Tobias Platenmmu: add debug output
8 days ago Tobias Platenadd testcase for invalid pagetable
8 days ago Tobias Platenpimem: reset on exception
8 days ago Tobias Platenremove unuses dsisr signal
8 days ago Tobias Platenreset state to idle on exception
8 days ago Luke Kenneth... more sorting scoremulti
8 days ago Luke Kenneth... more sorting out scoremulti
8 days ago Luke Kenneth... add test pspec for scoremulti to work
8 days ago Luke Kenneth... convert hazard bitvectors to Reset-Priority SRLatch...
9 days ago Tobias Platenfix exception handling in pi_ld
9 days ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
9 days ago Tobias Platenimprove debug output in mmu.py
9 days ago Luke Kenneth... fix write-after-write hazard detection
9 days ago Luke Kenneth... when allow_overlap enabled do a manual wait until all...
9 days ago Luke Kenneth... code-comments
9 days ago Luke Kenneth... add write-after-write hazard detection
9 days ago Luke Kenneth... add 2nd hazard bitvector port for write-after-write
9 days ago Luke Kenneth... whoops merged the two write-ports for RT and RA-with...
9 days ago Luke Kenneth... disable hazard vectors when overlap is not requested...
9 days ago Luke Kenneth... update submodules
9 days ago Luke Kenneth... more comments
10 days ago Tobias Platenpimem changes for st exception handling
10 days ago Tobias Platenfix test_loadstore1.py
10 days ago Luke Kenneth... add FU write-after-write hazard detection Signal (dummy...
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