soc.git
9 min ago Tobias Platenrefactoring (see #216 Comment 43) master
47 min ago Tobias Platenwhitespace changes
2 hours ago Luke Kenneth... quick addition of zero+immed test to LDSTCompUnit
3 hours ago Luke Kenneth... must not do rd-req checking when both imm and zero...
4 hours ago Tobias Platenimplement DataMerger interface
10 hours ago Luke Kenneth... add zero immed on LDST, untested
11 hours ago Luke Kenneth... comment out invalid test
11 hours ago Luke Kenneth... lots of greater than 80 chars
11 hours ago Luke Kenneth... switch out req rel if immediate enabled
13 hours ago Cesar StraussShow oper_r and oper_i in the signal list, in simulation
13 hours ago Luke Kenneth... mention zeroing
13 hours ago Luke Kenneth... add links to pseudocode
13 hours ago Luke Kenneth... spelling
13 hours ago Luke Kenneth... spelling
15 hours ago Luke Kenneth... add comments for SPR pipe_data
16 hours ago Luke Kenneth... add SPR pipe_data.py
16 hours ago Luke Kenneth... over 80 char limit
17 hours ago Luke Kenneth... add test of reg output, for MFCRF and ISEL
18 hours ago Cesar StraussAvoid overwriting the first vcd file with the second one
18 hours ago Cesar StraussRename the internal DFF of latchregisters to avoid...
18 hours ago Luke Kenneth... add gitignore for branch fu formal
18 hours ago Luke Kenneth... add OP_CMPB formal proof
18 hours ago Michael NolanAssert that ctr is only written when needed
18 hours ago Luke Kenneth... split out Popcount into separate module: visually it...
18 hours ago Luke Kenneth... copy code for MTMSR from microwatt into comments
18 hours ago Luke Kenneth... add links for trap main stage
18 hours ago Luke Kenneth... add untested OP_MTMSR and OP_MFMSR
18 hours ago Luke Kenneth... update to new CSV files in submodule
19 hours ago Luke Kenneth... add MFMSR and MTMSRD enums to Function
19 hours ago Luke Kenneth... comment and add links to branch formal proof
19 hours ago Luke Kenneth... add copy of bpermd proof to logical formal proof (not...
19 hours ago Luke Kenneth... track down overwrite of variable b
21 hours ago Michael NolanFix proof of bpermd module
21 hours ago Michael NolanFix bpermd and make tests pass
21 hours ago Michael NolanFix test_pipe_caller to conform to new Data() interface...
22 hours ago Luke Kenneth... add stub regfiles.py
23 hours ago Luke Kenneth... hmm...
23 hours ago Luke Kenneth... add very rapid DummyALU for test purposes in MultiCompUnit
24 hours ago Luke Kenneth... comments on branch pipeline
24 hours ago Luke Kenneth... convert CR pipeline to Data.ok
24 hours ago Luke Kenneth... convert ALU to output Data on int reg
24 hours ago Luke Kenneth... convert logical to output Data on int reg
25 hours ago Luke Kenneth... start using Data in pipelines
25 hours ago Luke Kenneth... cleanup/code-munge on ALU main stage proof
25 hours ago Luke Kenneth... error in alu output stage formal proof setup
25 hours ago Luke Kenneth... output registers need to be Data type (consistently)
25 hours ago Luke Kenneth... spelling mistake in variable
25 hours ago Luke Kenneth... TODO mention OP_MTMSR/OP_MFMSR
25 hours ago Luke Kenneth... add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
33 hours ago Luke Kenneth... move docstring to wiki for compunit
38 hours ago colepoirierAdded branch and shift_rot imports to fu/compunits...
38 hours ago Cesar StraussAdd a few test cases with zero_a set, in combination...
39 hours ago Cesar StraussAllow zero_a to be set when simulating an operation
39 hours ago Luke Kenneth... add input / output stage missing modules
41 hours ago Luke Kenneth... common function for op zero and op immed
42 hours ago Cesar StraussChoose between RA (src1) and zero immediate, conditione...
42 hours ago Luke Kenneth... update docs on compunits
43 hours ago Luke Kenneth... remove extraneous test_isel
43 hours ago Luke Kenneth... add comments
43 hours ago Luke Kenneth... document purpose of regspec module
43 hours ago Luke Kenneth... split out RegSpecs into separate module
43 hours ago Luke Kenneth... add TODO on multi-in multi-out Function Units
44 hours ago Luke Kenneth... split out RegSpec API into separate class (TODO: move...
44 hours ago Luke Kenneth... add notes on FunctionUnit API
44 hours ago Luke Kenneth... make MultiCompUnit and testing ALU use regspec API...
44 hours ago Luke Kenneth... remove unneeded imports
44 hours ago Luke Kenneth... make demo/test ALU look like nmigen pipeline API
46 hours ago Luke Kenneth... add stub DataMerger class
46 hours ago Luke Kenneth... add link to regspecs on wiki
47 hours ago Luke Kenneth... add regspec capability to MultiCompUnit
2 days ago Michael NolanModify proof of isel to use full CR register
2 days ago Michael NolanAdd test_isel
2 days ago Luke Kenneth... make immediate-or-RA selection optional based on awaren...
2 days ago Luke Kenneth... start to morph MultiCompUnit to take "regspec" as the...
2 days ago Luke Kenneth... add CR_ISEL formal proof to CR pipeline
2 days ago Luke Kenneth... add CR_ISEL (and unit test) to CR pipeline
2 days ago Luke Kenneth... update to (corrected) csv files for CR_ISEL
2 days ago Luke Kenneth... select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
2 days ago Luke Kenneth... add gitignore
2 days ago Luke Kenneth... CR field on Br input data is specd as 0:3 range
2 days ago Luke Kenneth... add b to CR pipe input data, for isel
2 days ago Luke Kenneth... add TODO and link to SHIFT_ROT formal bugreport
2 days ago Luke Kenneth... remove xer.so from ShiftRot formal proof
2 days ago Luke Kenneth... remove sticky overflow from Shift Rot pipeline
2 days ago Luke Kenneth... test branch ctr ok flag
2 days ago Luke Kenneth... cleaner way to test link register ok
2 days ago Luke Kenneth... whitespace
2 days ago Michael NolanFix link handling in branch proof
2 days ago Michael NolanUpdate to latest wiki version - fix cr0 input for OP_CNTZ
2 days ago Luke Kenneth... variable-name munging for branch formal
2 days ago Michael NolanAdd formal proof for branch unit, fix bug with bcreg
2 days ago Luke Kenneth... cleanup logical pipe formal proof
2 days ago Luke Kenneth... split out Logical Input and Output stages to common...
2 days ago Luke Kenneth... div probably uses ALU not Logical, needs double-checkin...
2 days ago Luke Kenneth... update comments for ALUCompUnit
2 days ago Luke Kenneth... soc.fu.logical.input_stage no different from ALU: delete
2 days ago Luke Kenneth... covert ALU FU to CommonInputStage
2 days ago Luke Kenneth... create common input pipe spec to avoid code-duplication
2 days ago Luke Kenneth... move CR over to CompCROpSubset
2 days ago Michael NolanConvert branch unit to new CR interface
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