2020-12-06 Luke Kenneth... attempt to split into two separate GPIO banks due to...
2020-12-06 Cesar StraussWhitespace
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof...
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset
2020-12-03 Luke Kenneth... put ls180 litex bus width back to 32 bit temporarily
2020-12-03 Luke Kenneth... argh issue with yosys ABC
2020-12-03 Luke Kenneth... add 3 more 4k SRAMs, change WB bus width to 64 in ls180...
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-22 Luke Kenneth... simplify litex-core wishbone interfaces
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-17 Tobias Platentestcase for dcbz
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-11-14 Luke Kenneth... sigh, direction wrong in IOtypes litex core
2020-11-13 Luke Kenneth... reduce number of nc in ls180 to 24
2020-11-13 Luke Kenneth... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth... rename and add pll lock signal to ls180
2020-11-13 Luke Kenneth... rename ls180 litex pll_48 output to pll_18
2020-11-13 Luke Kenneth... add enable/disable arguments (not ideal but it works...
2020-11-13 Luke Kenneth... remove io_in/out now it is not needed for niolib
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete
2020-11-11 Tobias Platenfu/mmu/test/ test case for mfspr
2020-11-10 Luke Kenneth... add build commands to Makefile for versa ecp5
2020-11-10 Luke Kenneth... submodule update
2020-11-10 Luke Kenneth... remove ClockSelect module, use DummyPLL
2020-11-10 Luke Kenneth... add separate DummyPLL module, according to API discussed at
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi...
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr
2020-11-07 Luke Kenneth... update submodule
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/
2020-11-06 Luke Kenneth... sigh sorting out litex pin-connections to sdram
2020-11-04 Luke Kenneth... move back to 3.3v on X3 VERSA ECP5 connector
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz'
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction...
2020-11-03 Luke Kenneth... swap jtag pinorder to match ulx3s
2020-11-03 Luke Kenneth... change LVCMOS level on versa ecp5 jtag to 2.5v
2020-11-01 Cesar StraussAdd a check for liveness.
2020-10-31 Cole add 4 arbitrarily assigned gpio pins...
2020-10-31 Cesar StraussCheck that the read and write counters differ at most...
2020-10-31 Cesar StraussRemove stray comment
2020-10-30 Luke Kenneth... add JTAG extension to versa_ecp5 then we can use it
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o...
2020-10-24 Luke Kenneth... submodule update
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests
2020-10-22 Luke Kenneth... add query about cross-domain on the JTAG enable of WB
2020-10-22 Luke Kenneth... add detection and disable of Instruction Wishbone based...
2020-10-22 Luke Kenneth... add detection and disable of LoadStore Wishbone based...
2020-10-22 Luke Kenneth... add JTAG enable/disable of wishbone to TestIssuer
2020-10-22 Luke Kenneth... add means to JTAG interface to enable/disable "stuff...
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f...
2020-10-21 Luke Kenneth... fix up asserts (check correct pads/cores)
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two...
2020-10-16 Luke Kenneth... experiment swapping dummy trap stage over to input
2020-10-16 Luke Kenneth... re-enable tests
2020-10-16 Luke Kenneth... manually run coresync clock for test issuer
2020-10-16 Luke Kenneth... set defaults in pspec
2020-10-16 Luke Kenneth... update submodule
2020-10-16 Luke Kenneth... add extra (test dummy stage in trap to see if combinato...
2020-10-16 Luke Kenneth... add LGPLv3+ notice and add copyright holders
2020-10-15 Luke Kenneth... add commented-out connection to JTAG in ECP5 litex
2020-10-15 Luke Kenneth... wrong pspec variable in selecting pll clock
2020-10-15 Luke Kenneth... sorting out missing clock somewhere
2020-10-15 Luke Kenneth... use "enable" and set default actions in getopt
2020-10-15 Luke Kenneth... add extra variant to litex core
2020-10-15 Luke Kenneth... syntax error
2020-10-15 Luke Kenneth... disable gpio in litex core
2020-10-15 Luke Kenneth... enable/disable litex irqs based on variant name
2020-10-14 Cole PoirierMakefile develop, when running develop specify...
2020-10-14 Cole update to use commandline args using...
2020-10-13 Cole Poiriermove pia from install_requires to test_requires
2020-10-12 Cole Poirierlitex/florent/ add arg --fpga [versa_ecp5...
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-12 Tobias Platenupdate gitlab ci
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for...
2020-10-11 Luke Kenneth... add way to bypass PLL for ECP5 and sim
2020-10-11 Luke Kenneth... comment out XICS/GPIO interrupt test, causes ECP5 litex...
2020-10-11 Luke Kenneth... record commands for building ECP5
2020-10-11 Luke Kenneth... litex operational
2020-10-10 Cole Poirierflorent/ remove uneccessary imports, speci...
2020-10-10 Luke Kenneth... add debug start/stop to firmware_upload script
2020-10-10 Luke Kenneth... add DMI status / reset to firmware upload script
2020-10-10 Luke Kenneth... add first version of firmware uploader
2020-10-09 Jacob Lifshayupdate submodule
2020-10-09 Jacob Lifshayupdate submodule