soc.git
2020-10-09 Luke Kenneth... submodule update
2020-10-09 Luke Kenneth... drop in "undefined" function into ISAcaller namespace
2020-10-09 Luke Kenneth... rename undef to undefined (preserving the fact that...
2020-10-09 Luke Kenneth... missing yields in JTAG pads test to allow settling
2020-10-09 Jacob Lifshayfinish converting mul tests to use common code
2020-10-09 Jacob Lifshayworking on splitting out common mul pipe test code
2020-10-09 Jacob Lifshayadd carry handling to pia_res_to_output
2020-10-09 Jacob Lifshaymove pia_res_to_output to common test helpers
2020-10-09 Jacob Lifshaymove mul pipe ilang test to separate file
2020-10-09 Jacob Lifshayadd undef()
2020-10-09 Jacob Lifshayupdate submodule
2020-10-08 Jacob Lifshayupdate submodule
2020-10-08 Luke Kenneth... missing yields in JTAG pads test to allow settling
2020-10-08 Luke Kenneth... minor icache cleanup
2020-10-08 Cole Poiriersecond attempt at https://bugs.libre-soc.org/show_bug...
2020-10-08 Cole Poirierremove singleton dict per https://bugs.libre-soc.org...
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth... add incoming PortInterface to be connected to LoadStore...
2020-10-08 Luke Kenneth... JTAG boundary scan test 1st attempt
2020-10-08 Luke Kenneth... rework jtag test to use JTAG class not DMITAP
2020-10-08 Luke Kenneth... split out jtag util functions to separate module
2020-10-08 Cole Poirierfirst attempt at 3) of
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org...
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox
2020-10-07 Luke Kenneth... missing invert_in field from shiftrot input record
2020-10-07 Luke Kenneth... git submodule update
2020-10-07 Luke Kenneth... reorder / reorganise reset signals slightly
2020-10-07 Jacob Lifshayfix div tests
2020-10-07 Jacob Lifshayupdate submodule
2020-10-07 Jacob LifshayFix forgotten test_pipe_caller changes from e0b4334c7d8...
2020-10-06 Tobias Platenremove redunant signals
2020-10-06 Luke Kenneth... update comments on pimem.py
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-06 Luke Kenneth... comments
2020-10-06 Luke Kenneth... add ports function to DummyPLL
2020-10-06 Luke Kenneth... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-10-06 Luke Kenneth... skip Decode2ToOperand from PowerDecodeSubset
2020-10-06 Luke Kenneth... comment SRR1 mem.exception
2020-10-06 Luke Kenneth... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth... add LDSTException decode/handling in PowerDecoder2
2020-10-06 Luke Kenneth... make LDSTException fields added from list of fieldnames
2020-10-06 Luke Kenneth... move LDSTException to mem_types
2020-10-06 Luke Kenneth... submodule update
2020-10-06 Luke Kenneth... add LDSTException to PortInterface
2020-10-06 Luke Kenneth... add sdr bypass routing via JTAG boundary scan
2020-10-06 Jacob Lifshayadd divde regression test
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd moduw regression test
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd modsw regression
2020-10-06 Jacob Lifshayadd test case for divweu regression
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayprint regs in hex
2020-10-05 Luke Kenneth... add debug / investigation print statements
2020-10-05 Jacob Lifshay`deepcopy` from cache instead of recreating parsers...
2020-10-05 Jacob Lifshayformat code
2020-10-05 Cole Poiriericache.py fix ispow2() util fn per https://bugs.libre...
2020-10-05 Luke Kenneth... whoops fix syntax error
2020-10-05 Luke Kenneth... whoops fix syntax error
2020-10-05 Luke Kenneth... return test rather than "if test return True else False"
2020-10-05 Luke Kenneth... whitespace
2020-10-05 Luke Kenneth... whitespace
2020-10-05 Cole Poiriericache.py add python asserts that were a TODO commented...
2020-10-05 Cole Poiriericache.py fix formatting, mostly due to reduced indenta...
2020-10-05 Cole Poiriericache.py remove comment that contained the entirety...
2020-10-05 Cole Poiriericache.py move icache_miss WAIT_ACK FSM state into...
2020-10-05 Cole Poiriericache.py move icache_miss CLR_TAG FSM state into metho...
2020-10-05 Cole Poiriericache.py move icache_miss IDLE FSM state into method...
2020-10-05 Jacob Lifshaysimplify create_args
2020-10-05 Jacob LifshaySort returned variables to make sure `overflow` is...
2020-10-05 Jacob Lifshayformat caller.py
2020-10-04 Jacob Lifshaychange div FSM pipeline unit to not have a combinatoria...
2020-10-04 Luke Kenneth... significant reorg of the litex pinspecs to use pinmux...
2020-10-04 Luke Kenneth... submodule update
2020-10-04 Luke Kenneth... remove ls180io import
2020-10-04 Luke Kenneth... move ls180io.py back into ls180.py
2020-10-03 Luke Kenneth... allow i2c to be routed via JTAG
2020-10-03 Luke Kenneth... nope. put it back and connect to platform pads in...
2020-10-03 Luke Kenneth... move iopad litex creation to ls180soc.py
2020-10-03 Luke Kenneth... minor reorg on JTAG, allow alternative pinset dict...
2020-10-03 Jacob Lifshayadd regression testcase
2020-10-03 Jacob Lifshayupdate submodule
2020-10-02 Cole Poiriericache.py add req_hit_way as arg to icache_comb, actual...
2020-10-02 Luke Kenneth... add pinmux generator to create litex pinmap
2020-10-02 Luke Kenneth... add pinmux as submodule
2020-10-01 Cole Poiriericache.py add missing comb signal assignments per https...
2020-10-01 Luke Kenneth... arg CacheRam read output needs delay by 1 cycle
2020-10-01 Luke Kenneth... do not pass cache row array around, just the current row
2020-10-01 Luke Kenneth... revert bug in icache wishbone ack
2020-10-01 Luke Kenneth... add clksel, pll to ls180
2020-10-01 Luke Kenneth... create dummy PLL block, connect up to core and clock...
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
2020-09-30 Luke Kenneth... add I2C into ls180
2020-09-30 Luke Kenneth... add ASIC version of I2C Master
2020-09-30 Luke Kenneth... clean up row store and wb adr in icache
2020-09-30 Luke Kenneth... hmm only set wishbone address if ack is actually received
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