2021-01-23 Luke Kenneth... capture CR 3 and 5 bit sv encodings
2021-01-23 Luke Kenneth... start decoding EXTRA2/3
2021-01-23 Luke Kenneth... start decoding sv EXTRAs and identifying them
2021-01-23 Luke Kenneth... start to read RM CSV files
2021-01-23 Luke Kenneth... add beginnings of svp64 assembly translator
2021-01-22 Luke Kenneth... add example on how to access regs list for cmp
2021-01-19 Tobias test both ld and st instr...
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenuncomment #FIXME in unit_test
2021-01-18 Tobias Platenfu/mmu/ connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-17 Tobias Platencleanup
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-16 Tobias Platenadd new unittest:
2021-01-15 Tobias Platencleanup
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits
2021-01-15 Tobias fix hanging test
2021-01-15 Tobias wire instruction decoder...
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore
2021-01-10 Tobias Platenadd microwatt mmu config option to
2021-01-08 Tobias Platenfix broken testcase for simple core
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog
2021-01-07 Tobias Platenmfspr is RT, SPR
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load
2021-01-06 Tobias Platenfu/mmu/ mfspr!=mtspr
2021-01-04 Tobias rename output files
2021-01-01 Cesar StraussAdd zero CR test case and fix comments
2021-01-01 Cesar StraussAdd test cases with rc=1
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU
2021-01-01 Cesar StraussAdd CR output port to test cases
2021-01-01 Cesar StraussAdd CR to the output data port
2021-01-01 Cesar StraussMake output write enables independent of valid_o
2021-01-01 Cesar StraussMove NOP test case earlier
2021-01-01 Cesar StraussDisable data value output on NOP
2021-01-01 Cesar StraussAdd condition register (CR) output
2020-12-31 Cesar StraussImplement and test NOP in the test ALU
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussSign extend the second input port
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussAdd sign extend to the Test ALU
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-29 Cesar StraussRemove left-over comments.
2020-12-28 Luke Kenneth... add CR1 to power_enums
2020-12-20 Cesar StraussAdd support for CXXSim simulation
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-12-12 Luke Kenneth... skip madd, not implemented
2020-12-09 Luke Kenneth... update submodules
2020-12-09 Luke Kenneth... update submodules
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
2020-12-06 Luke Kenneth... attempt to split into two separate GPIO banks due to...
2020-12-06 Cesar StraussWhitespace
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof...
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset
2020-12-03 Luke Kenneth... put ls180 litex bus width back to 32 bit temporarily
2020-12-03 Luke Kenneth... argh issue with yosys ABC
2020-12-03 Luke Kenneth... add 3 more 4k SRAMs, change WB bus width to 64 in ls180...
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-22 Luke Kenneth... simplify litex-core wishbone interfaces
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-17 Tobias Platentestcase for dcbz
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-11-14 Luke Kenneth... sigh, direction wrong in IOtypes litex core
2020-11-13 Luke Kenneth... reduce number of nc in ls180 to 24
2020-11-13 Luke Kenneth... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth... rename and add pll lock signal to ls180
2020-11-13 Luke Kenneth... rename ls180 litex pll_48 output to pll_18
2020-11-13 Luke Kenneth... add enable/disable arguments (not ideal but it works...
2020-11-13 Luke Kenneth... remove io_in/out now it is not needed for niolib
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete
2020-11-11 Tobias Platenfu/mmu/test/ test case for mfspr
2020-11-10 Luke Kenneth... add build commands to Makefile for versa ecp5
2020-11-10 Luke Kenneth... submodule update
2020-11-10 Luke Kenneth... remove ClockSelect module, use DummyPLL
2020-11-10 Luke Kenneth... add separate DummyPLL module, according to API discussed at
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi...
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://