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last changeSat, 4 Dec 2021 04:06:53 +0000 (04:06 +0000)
shortlog
7 hours ago Luke Kenneth... not busy if excrption occurs on MMU_LOOKUP in loadstore.py master
10 hours ago Luke Kenneth... add means to update dsisr from MMU FSM. TODO: add a...
16 hours ago Luke Kenneth... priv_mode/virt_mode are set in the request, which is...
16 hours ago Luke Kenneth... in loadstore.py set align_intr from request which comes...
16 hours ago Luke Kenneth... driver conflict on priv_mode and virt_mode, do not...
18 hours ago Luke Kenneth... fix up test_loadstore1.py
18 hours ago Luke Kenneth... in loadstore.py, when an exception is done or if the FSM
18 hours ago Luke Kenneth... fix PortInterfaceBase
18 hours ago Luke Kenneth... fix up LDST test functions pi_ld and pi_st to respect...
19 hours ago Luke Kenneth... whitespace
20 hours ago Luke Kenneth... add misaligned ld/st to trigger an exception
20 hours ago Luke Kenneth... comment out dsisr and dar in mmu FSM for now
40 hours ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
40 hours ago Tobias Platencleanup test_compldst_multi_mmu.py
42 hours ago Luke Kenneth... add a bitvector remap function, the plan is to use...
43 hours ago Tobias Platenfix test_random in test_loadstore1
...
tags
8 months ago convert-csv-opcode-to-binary
10 months ago 24jan2021_ls180
14 months ago semi_working_ecp5
16 months ago div_pipeline
heads
7 hours ago master
8 weeks ago pr
4 months ago jn-tests