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last changeMon, 14 Jun 2021 18:02:49 +0000 (20:02 +0200)
shortlog
3 days ago Tobias Platenupdate testcase for ldst master
7 days ago Luke Kenneth... whoops Popcount datalen too big (wasted bits). reduce
8 days ago Luke Kenneth... git submodule update
8 days ago Luke Kenneth... disconnect pll clock, connected in peripheral interconnect
8 days ago Luke Kenneth... add in/out of ref_clk and pllclk_clk when PLL enabled
11 days ago Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-03 Luke Kenneth... comment out domains that have already been created
2021-06-03 Luke Kenneth... no, do not assign clock to clock!
2021-06-03 Luke Kenneth... rename ref to ref_v in PLL due to ref being a verilog...
2021-06-03 Luke Kenneth... sort out PLL domains but bypass PLL due to lack of...
2021-06-03 Luke Kenneth... use DomainRenamer on all sub-components of TestIssuer
2021-06-03 Luke Kenneth... make core_rst a member of TestIssuerInternal
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-27 Luke Kenneth... adjust PLL connections looking for coriolis2 issue
...
tags
3 months ago convert-csv-opcode-to-binary
4 months ago 24jan2021_ls180
8 months ago semi_working_ecp5
11 months ago div_pipeline
heads
3 days ago master