add register specs to pipeline in/out so that they can be used to connect up
[soc.git] / src / soc / fu / alu /
drwxr-xr-x   ..
-rw-r--r-- 2839 alu_input_record.py
drwxr-xr-x - formal
-rw-r--r-- 1734 input_stage.py
-rw-r--r-- 4099 main_stage.py
-rw-r--r-- 3228 output_stage.py
-rw-r--r-- 2991 pipe_data.py
-rw-r--r-- 808 pipeline.py
drwxr-xr-x - test