remove SPR3 from Branch Data, rename lr and spr to SPR1 and SPR2
[soc.git] / src / soc / fu / branch /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 2859 br_input_record.py
drwxr-xr-x - formal
-rw-r--r-- 2000 input_stage.py
-rw-r--r-- 5381 main_stage.py
-rw-r--r-- 2632 pipe_data.py
-rw-r--r-- 635 pipeline.py
drwxr-xr-x - test