add register specs to pipeline in/out so that they can be used to connect up
[soc.git] / src / soc / fu / logical /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 2775 bpermd.py
-rw-r--r-- 5009 countzero.py
drwxr-xr-x - formal
-rw-r--r-- 2000 input_stage.py
-rw-r--r-- 5519 main_stage.py
-rw-r--r-- 994 pipe_data.py
-rw-r--r-- 832 pipeline.py
drwxr-xr-x - test