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add register specs to pipeline in/out so that they can be used to connect up
[soc.git] / src / soc / fu /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
drwxr-xr-x - alu tree | history
drwxr-xr-x - branch tree | history
drwxr-xr-x - cr tree | history
drwxr-xr-x - logical tree | history
drwxr-xr-x - shift_rot tree | history
drwxr-xr-x - trap tree | history