add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex
[soc.git] / src / soc / litex / florent /
drwxr-xr-x   ..
-rw-r--r-- 650 Makefile
-rw-r--r-- 295 README.txt
-rw-r--r-- 560 idcode_test.svf
-rw-r--r-- 864 idcode_test2.svf
drwxr-xr-x - libresoc
-rw-r--r-- 1930 ls180pins.txt
-rwxr-xr-x 31192 ls180soc.py
drwxr-xr-x - microwatt
-rw-r--r-- 456 openocd.cfg
-rwxr-xr-x 17166 sim.py
-rwxr-xr-x 5427 versa_ecp5.py