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add DEC and TB to State regfile
[soc.git] / src / soc / regfile /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
drwxr-xr-x - formal tree | history
-rw-r--r-- 13265 regfile.py blob | history | raw
-rw-r--r-- 6536 regfiles.py blob | history | raw
-rw-r--r-- 838 util.py blob | history | raw
-rw-r--r-- 6279 virtual_port.py blob | history | raw