err trying to put in some FSM handshake signals, getting confused
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 21897 core.py
-rw-r--r-- 28453 issuer.py
-rw-r--r-- 3474 issuer_verilog.py
drwxr-xr-x - test