wrong pspec variable in selecting pll clock
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 21852 core.py
-rw-r--r-- 20576 issuer.py
-rw-r--r-- 2408 issuer_verilog.py
drwxr-xr-x - test