reorder / reorganise reset signals slightly
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 21779 core.py
-rw-r--r-- 20342 issuer.py
-rw-r--r-- 1331 issuer_verilog.py
drwxr-xr-x - test