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fix regfile port names for "fast" port access (regreduce=False)
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 28388 core.py blob | history | raw
-rw-r--r-- 2942 core_data.py blob | history | raw
-rw-r--r-- 60690 issuer.py blob | history | raw
-rw-r--r-- 5101 issuer_verilog.py blob | history | raw
drwxr-xr-x - test tree | history