byte-reverse Tercel read/write data and config bus. urr...
[soc.git] / src / soc /
drwxr-xr-x   ..
drwxr-xr-x - TestUtil
-rw-r--r-- 0 __init__.py
drwxr-xr-x - bus
drwxr-xr-x - clock
drwxr-xr-x - config
-rw-r--r-- 166 consts.py
drwxr-xr-x - debug
drwxr-xr-x - decoder
drwxr-xr-x - experiment
drwxr-xr-x - fu
drwxr-xr-x - interrupts
drwxr-xr-x - litex
drwxr-xr-x - memory_pipe_experiment
drwxr-xr-x - minerva
drwxr-xr-x - regfile
drwxr-xr-x - scoreboard
drwxr-xr-x - scoremulti
drwxr-xr-x - simple
m--------- - soc-cocotb-sim
drwxr-xr-x - sv