1 from nmigen
.cli
import rtlil
2 from ieee754
.part
.test
.test_partsig
import TestAddMod2
5 from nmigen
import Signal
9 pmask
= Signal(3) # divide into 4-bits
10 module
= TestAddMod2(width
, pmask
)
11 sim
= create_ilang(module
,
33 def run_yosys(test_name
):
34 liberty_file
= os
.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
35 print("test_name:",test_name
)
37 "read_ilang part_sig_add.il",
38 "hierarchy -check -top part_sig_add",
39 "synth -top part_sig_add",
40 "dfflibmap -liberty "+liberty_file
,
41 "abc -liberty "+liberty_file
,
43 "write_blif test.blif"
46 subprocess
.call(["yosys","-p",cmd
])
48 def create_ilang(dut
, ports
, test_name
):
49 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
50 with
open("%s.il" % test_name
, "w") as f
:
55 if __name__
== "__main__":