use --recursive on git submodule not --remote - one does a "latest update"
[soclayout.git] / experiments10 / doDesign.py
1
2 from __future__ import print_function
3 import sys
4 import traceback
5 import CRL
6 import helpers
7 from helpers.io import ErrorMessage
8 from helpers.io import WarningMessage
9 from helpers import trace
10 from helpers import l, u, n
11 import plugins
12 from Hurricane import DbU
13 from plugins.alpha.block.block import Block
14 from plugins.alpha.block.configuration import IoPin
15 from plugins.alpha.block.configuration import GaugeConf
16 from plugins.alpha.core2chip.niolib import CoreToChip
17 from plugins.alpha.chip.configuration import ChipConf
18 from plugins.alpha.chip.chip import Chip
19
20
21 af = CRL.AllianceFramework.get()
22
23
24 def scriptMain ( **kw ):
25 """The mandatory function to be called by Coriolis CGT/Unicorn."""
26 global af
27 rvalue = True
28 try:
29 helpers.setTraceLevel( 550 )
30 usePadsPosition = True
31 buildChip = True
32 cell, editor = plugins.kwParseMain( **kw )
33 cell = af.getCell( 'add', CRL.Catalog.State.Logical )
34 if cell is None:
35 print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
36 sys.exit( 1 )
37 if editor: editor.setCell( cell )
38 # Spec:
39 # | Side | Pos | Instance | Pad net |Core net | Direction |
40 ioPadsSpec = [
41 (IoPin.SOUTH, None, 'p_a0' , 'a(0)' , 'a(0)' )
42 , (IoPin.SOUTH, None, 'p_a1' , 'a(1)' , 'a(1)' )
43 , (IoPin.SOUTH, None, 'iopower_0' , 'iovdd' )
44 , (IoPin.SOUTH, None, 'power_0' , 'vdd' )
45 , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' )
46 , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' )
47 , (IoPin.EAST , None, 'p_tms_0' , 'tms' , 'tms' )
48 , (IoPin.EAST , None, 'p_tdo_0' , 'tdo' , 'tdo' )
49 , (IoPin.EAST , None, 'ground_0' , 'vss' )
50 , (IoPin.EAST , None, 'p_clk' , 'clk' , 'clk' )
51 , (IoPin.EAST , None, 'p_tck' , 'tck' , 'tck' )
52 , (IoPin.EAST , None, 'p_tdi_0' , 'tdi' , 'tdi' )
53 , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' )
54 , (IoPin.NORTH, None, 'ioground_0' , 'iovss' )
55 , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' )
56 , (IoPin.NORTH, None, 'ground_1' , 'vss' )
57 , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' )
58 , (IoPin.NORTH, None, 'rst' , 'rst' , 'rst' )
59 , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' )
60 , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' )
61 , (IoPin.WEST , None, 'power_1' , 'vdd' )
62 , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' )
63 , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' )
64 , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' )
65 ]
66 adderConf = ChipConf( cell, ioPads=ioPadsSpec )
67 adderConf.cfg.etesian.bloat = 'nsxlib'
68 adderConf.cfg.etesian.uniformDensity = True
69 adderConf.cfg.etesian.aspectRatio = 1.0
70 adderConf.cfg.etesian.spaceMargin = 0.05
71 adderConf.cfg.block.spareSide = l(700)
72 adderConf.cfg.chip.padCoreSide = 'North'
73 adderConf.editor = editor
74 adderConf.useSpares = True
75 adderConf.useClockTree = True
76 adderConf.bColumns = 2
77 adderConf.bRows = 2
78 adderConf.chipConf.name = 'chip'
79 adderConf.chipConf.ioPadGauge = 'niolib'
80 adderConf.coreSize = ( l(2000), l(2000) )
81 adderConf.chipSize = ( l(5900), l(5900) )
82 adderToChip = CoreToChip( adderConf )
83 adderToChip.buildChip()
84 chipBuilder = Chip( adderConf )
85 rvalue = chipBuilder.doPnR()
86 chipBuilder.save()
87 except Exception, e:
88 helpers.io.catch( e )
89 rvalue = False
90 sys.stdout.flush()
91 sys.stderr.flush()
92 return rvalue