experiments13/Makefile

   1 # -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
   2
   3         LOGICAL_SYNTHESIS = Yosys
   4        PHYSICAL_SYNTHESIS = Coriolis
   5                DESIGN_KIT = sxlib
   6
   7 #           YOSYS_FLATTEN = Yes
   8                      CHIP = chip
   9                      CORE = memory
  10                    MARGIN = 2
  11                   BOOMOPT =  # -A
  12                   BOOGOPT =
  13                   LOONOPT =
  14                 NSL2VHOPT = -vasy # -split -p
  15             USE_CLOCKTREE = Yes
  16                 USE_DEBUG = No
  17                  USE_KITE = No
  18 #                 RM_CHIP = Yes
  19
  20                  NETLISTS = $(shell cat nets.txt)
  21 #                PATTERNS = memory_r
  22
  23
  24  include ./mk/design-flow.mk
  25
  26
  27 blif:      memory.blif
  28 vst:       memory.vst
  29
  30 lvx:       lvx-chip_cts_r
  31 druc:      druc-chip_cts_r
  32 dreal:     dreal-chip_cts_r
  33 flatph:     flatph-chip_cts_r
  34 view:      cgt-chip_cts_r
  35
  36 layout:    chip_cts_r.ap
  37 gds:       chip_cts_r.gds
  38 gds_flat:  chip_cts_r_flat.gds
  39 cif:       chip_cts_r.cif
  40
  41
  42 view:      cgt-chip_cts_r
  43 sim:       asimut-memory_cts_r