experiments2/Makefile

   1 # -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
   2
   3         LOGICAL_SYNTHESIS = Yosys
   4        PHYSICAL_SYNTHESIS = Coriolis
   5                DESIGN_KIT = sxlib
   6
   7 #           YOSYS_FLATTEN = Yes
   8             USE_CLOCKTREE = Yes
   9                 USE_DEBUG = No
  10                  USE_KITE = No
  11
  12                  NETLISTS = $(shell cat nets2.txt)
  13
  14                 VST_FLAGS = --vst-use-concat
  15
  16  include ./mk/design-flow.mk
  17
  18
  19 blif:      part_sig_add.blif
  20 vst:       part_sig_add.vst
  21 layout:    part_sig_add_cts_r.ap
  22 gds:       part_sig_add_cts_r.gds
  23
  24 lvx:       lvx-part_sig_add_cts_r
  25 druc:      druc-part_sig_add_cts_r
  26 view:      cgt-part_sig_add_cts_r