experiments2/part_sig_add.py

   1 from nmigen.cli import rtlil
   2 from test_partsig import TestAddMod2, TestLS
   3 import subprocess
   4 import os
   5 from nmigen import Signal
   6
   7 def test():
   8     width = 16
   9     pmask = Signal(3)  # divide into 4-bits
  10     #module = TestAddMod2(width, pmask)
  11     module = TestLS(width, pmask)
  12     sim = create_ilang(module, [pmask] + module.ports(),
  13                                "part_sig_add")
  14
  15 def create_ilang(dut, ports, test_name):
  16     vl = rtlil.convert(dut, name=test_name, ports=ports)
  17     with open("%s.il" % test_name, "w") as f:
  18         f.write(vl)
  19
  20 if __name__ == "__main__":
  21     test()