1 from nmigen
.cli
import rtlil
2 from test_partsig
import TestAddMod2
5 from nmigen
import Signal
9 pmask
= Signal(3) # divide into 4-bits
10 module
= TestAddMod2(width
, pmask
)
11 sim
= create_ilang(module
,
25 def create_ilang(dut
, ports
, test_name
):
26 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
27 with
open("%s.il" % test_name
, "w") as f
:
30 if __name__
== "__main__":