experiments2/test_partsig.py

   1 #!/usr/bin/env python3
   2 # SPDX-License-Identifier: LGPL-2.1-or-later
   3 # See Notices.txt for copyright information
   4
   5 from nmigen import Signal, Module, Elaboratable
   6 from nmigen.back.pysim import Simulator, Delay
   7 from nmigen.cli import rtlil
   8
   9 from ieee754.part.partsig import PartitionedSignal
  10 from ieee754.part_mux.part_mux import PMux
  11
  12
  13 # XXX this is for coriolis2 experimentation
  14 class TestLS(Elaboratable):
  15     def __init__(self, width, partpoints):
  16         self.partpoints = partpoints
  17         self.a = PartitionedSignal(partpoints, width, name="a")
  18         self.b = PartitionedSignal(partpoints, width, name="b")
  19         self.ls_output = Signal(width) # left shift
  20         self.dummy_output = Signal(width)
  21         self.dummy_mask = Signal(self.partpoints.shape())
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         comb = m.d.comb
  26         sync = m.d.sync
  27         self.a.set_module(m)
  28         self.b.set_module(m)
  29         # left shift
  30         wid = len(self.partpoints)
  31         sync += self.dummy_mask.eq(self.partpoints)
  32         sync += self.dummy_output.eq(self.b.sig + self.a.sig) # stops ignored
  33         sync += self.ls_output.eq(self.a << self.b)
  34         ppts = self.partpoints
  35
  36         return m
  37
  38     def ports(self):
  39         return [self.a.sig, self.b.sig,
  40                 self.ls_output,
  41                 self.dummy_output,
  42                 self.dummy_mask]
  43
  44
  45 # XXX this is for coriolis2 experimentation
  46 class TestAddMod2(Elaboratable):
  47     def __init__(self, width, partpoints):
  48         self.partpoints = partpoints
  49         self.a = PartitionedSignal(partpoints, width, name="a")
  50         self.b = PartitionedSignal(partpoints, width, name="b")
  51         self.add_output = Signal(width)
  52         self.ls_output = Signal(width) # left shift
  53         self.sub_output = Signal(width)
  54         self.carry_in = Signal(len(partpoints)+1)
  55         self.add_carry_out = Signal(len(partpoints)+1)
  56         self.sub_carry_out = Signal(len(partpoints)+1)
  57         self.neg_output = Signal(width)
  58
  59     def elaborate(self, platform):
  60         m = Module()
  61         comb = m.d.comb
  62         sync = m.d.sync
  63         self.a.set_module(m)
  64         self.b.set_module(m)
  65         # add
  66         add_out, add_carry = self.a.add_op(self.a, self.b,
  67                                            self.carry_in)
  68         sync += self.add_output.eq(add_out)
  69         sync += self.add_carry_out.eq(add_carry)
  70         # sub
  71         sub_out, sub_carry = self.a.sub_op(self.a, self.b,
  72                                            self.carry_in)
  73         sync += self.sub_output.eq(sub_out)
  74         sync += self.sub_carry_out.eq(sub_carry)
  75         # neg
  76         sync += self.neg_output.eq(-self.a)
  77         # left shift
  78         sync += self.ls_output.eq(self.a << self.b)
  79         ppts = self.partpoints
  80
  81         return m
  82
  83     def ports(self):
  84         return [self.a.sig, self.b.sig,
  85                 self.add_output,
  86                 self.ls_output,
  87                 self.sub_output,
  88                 self.carry_in,
  89                 self.add_carry_out,
  90                 self.sub_carry_out,
  91                 self.neg_output]
  92
  93