do an SRAM search by looking for matching along the path
[soclayout.git] / experiments3 / test_part_add.py
1 #!/usr/bin/env python3
2 # SPDX-License-Identifier: LGPL-2.1-or-later
3 # See Notices.txt for copyright information
4
5 from nmigen import Signal, Module, Elaboratable
6 from nmigen.cli import rtlil
7
8 from ieee754.part.partsig import PartitionedSignal
9
10 def create_ilang(dut, traces, test_name):
11 vl = rtlil.convert(dut, ports=traces, name=test_name)
12 with open("%s.il" % test_name, "w") as f:
13 f.write(vl)
14
15
16
17 class TestAddMod(Elaboratable):
18 def __init__(self, width, partpoints):
19 self.partpoints = partpoints
20 self.a = PartitionedSignal(partpoints, width)
21 self.b = PartitionedSignal(partpoints, width)
22 self.add_output = Signal(width)
23 self.carry_in = Signal(len(partpoints)+1)
24 self.add_carry_out = Signal(len(partpoints)+1)
25
26 def elaborate(self, platform):
27 m = Module()
28 comb = m.d.comb
29 sync = m.d.sync
30 self.a.set_module(m)
31 self.b.set_module(m)
32 # add
33 add_out, add_carry = self.a.add_op(self.a, self.b,
34 self.carry_in)
35 sync += self.add_output.eq(add_out)
36 sync += self.add_carry_out.eq(add_carry)
37
38 return m
39
40 if __name__ == '__main__':
41 width = 16
42 pmask = Signal(3) # divide into 4-bits
43 module = TestAddMod(width, pmask)
44
45 create_ilang(module,
46 [pmask,
47 module.a.sig,
48 module.b.sig,
49 module.add_output,
50 module.carry_in,
51 module.add_carry_out,
52 ],
53 "test_part_add")
54 print (dir(module))
55 add_1 = module.a.m.submodules.add_1
56 print (dir(add_1.part_pts))
57 create_ilang(add_1,
58 [pmask,
59 add_1.a,
60 add_1.b,
61 add_1.output,
62 add_1.carry_in,
63 add_1.carry_out,
64 ],
65 "test_add")