experiments5/Makefile

   1 # -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
   2
   3         LOGICAL_SYNTHESIS = Yosys
   4        PHYSICAL_SYNTHESIS = Coriolis
   5                DESIGN_KIT = sxlib
   6
   7 #           YOSYS_FLATTEN = Yes
   8             USE_CLOCKTREE = No
   9                 USE_DEBUG = No
  10                  USE_KITE = No
  11
  12                  NETLISTS = $(shell cat nets.txt)
  13                  PATTERNS = alu_hier_r
  14
  15
  16  include ./mk/design-flow.mk
  17
  18
  19 blif:      alu_hier.blif
  20 vst:       alu_hier.vst
  21 layout:    alu_hier_r.ap
  22 gds:       alu_hier_r.gds
  23
  24 lvx:       lvx-alu_hier_r
  25 druc:      druc-alu_hier_r
  26 view:      cgt-alu_hier_r
  27 sim:       asimut-alu_hier_r