experiments7/Makefile

   1        LOGICAL_SYNTHESIS = Yosys
   2        PHYSICAL_SYNTHESIS = Coriolis
   3                DESIGN_KIT = sxlib
   4
   5             USE_CLOCKTREE = No
   6                 USE_DEBUG = No
   7                  USE_KITE = No
   8
   9                  NETLISTS = alu16 \
  10                             add   \
  11                             sub
  12                  PATTERNS = alu16_r
  13
  14
  15  include ./mk/design-flow.mk
  16
  17 alu16_r.ap alu16_r.vst: alu16.vst
  18         -@echo "Overriding rules to generate layout by doAlu16.py custom script."
  19         -$(call scl_cols,$(call c2env, ./doAlu16.py))
  20
  21 blif:      alu16.blif
  22 vst:       alu16.vst
  23 layout:    alu16_r.ap
  24 gds:       alu16_r.gds
  25
  26 lvx:       lvx-alu16_r
  27 druc:      druc-alu16_r
  28 view:      cgt-alu16_r
  29 sim:       asimut-alu16_r