experiments7/alu16.py

   1 from nmigen import *
   2 from nmigen.cli import rtlil
   3
   4
   5 class Adder(Elaboratable):
   6     def __init__(self, width):
   7         self.a = Signal(width)
   8         self.b = Signal(width)
   9         self.o = Signal(width)
  10
  11     def elaborate(self, platform):
  12         m = Module()
  13         m.d.comb += self.o.eq(self.a + self.b)
  14         return m
  15
  16
  17 class Subtractor(Elaboratable):
  18     def __init__(self, width):
  19         self.a = Signal(width)
  20         self.b = Signal(width)
  21         self.o = Signal(width)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         m.d.comb += self.o.eq(self.a - self.b)
  26         return m
  27
  28
  29 class ALU(Elaboratable):
  30     def __init__(self, width):
  31         self.op = Signal()
  32         self.a = Signal(width)
  33         self.b = Signal(width)
  34         self.o = Signal(width)
  35
  36         self.add = Adder(width)
  37         self.sub = Subtractor(width)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41
  42         m.submodules.add = self.add
  43         m.submodules.sub = self.sub
  44         m.d.comb += [
  45             self.add.a.eq(self.a),
  46             self.sub.a.eq(self.a),
  47             self.add.b.eq(self.b),
  48             self.sub.b.eq(self.b),
  49         ]
  50         with m.If(self.op):
  51             m.d.sync += self.o.eq(self.sub.o)
  52         with m.Else():
  53             m.d.sync += self.o.eq(self.add.o)
  54         return m
  55
  56
  57 def create_ilang(dut, ports, test_name):
  58     vl = rtlil.convert(dut, name=test_name, ports=ports)
  59     with open("%s.il" % test_name, "w") as f:
  60         f.write(vl)
  61
  62
  63 if __name__ == "__main__":
  64     alu = ALU(width=16)
  65     create_ilang(alu, [alu.op, alu.a, alu.b, alu.o], "alu16")