experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6          YOSYS_BLACKBOXES = pll spblock512w64b8w
   7 #            YOSYS_SET_TOP = Yes
   8                     CHIP  = chip
   9                     CORE  = ls180
  10             USE_CLOCKTREE = Yes
  11                 USE_DEBUG = No
  12                  USE_KITE = No
  13                  RM_CHIP  = Yes
  14                  # must make VST names unique (for re-importing to GHDL)
  15                 VST_FLAGS = --vst-uniquify-uppercase
  16
  17                  #NETLISTS = $(shell cat cells.lst)
  18                  NETLISTS = ls180 libresoc
  19 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  20
  21
  22
  23  include ./mk/design-flow.mk
  24
  25 chip_r.vst: ls180.vst
  26         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  27
  28 chip_r.ap: chip_r.vst
  29
  30 pinmux:
  31         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  32         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  33         ln -f -s coriolis2/ls180 ls180
  34
  35 # comment out for now
  36 blif:      ls180.blif
  37 vst:       ls180.vst
  38
  39 lvx:       lvx-chip_r
  40 druc:      druc-chip_r
  41 dreal:     dreal-chip_r
  42 flatph:     flatph-chip_r
  43 view:      cgt-chip_r
  44
  45 layout:    chip_r.ap
  46 gds:       chip_r.gds
  47 gds_flat:  chip_r_flat.gds
  48 cif:       chip_r.cif
  49
  50
  51 view:      cgt-chip_r
  52 sim:       asimut-ls180_r