8 if 'NDA_TOP' in os
.environ
:
9 NdaDirectory
= os
.environ
['NDA_TOP']
11 hostname
= socket
.gethostname()
12 if hostname
.startswith('lepka'):
13 NdaDirectory
= '/dsk/l1/jpc/crypted/soc/techno'
14 if not os
.path
.isdir(NdaDirectory
):
15 print( '[ERROR] You forgot to mount the NDA '
16 'encrypted directory, stupid!' )
18 NdaDirectory
= '/users/soft/techno/techno'
19 helpers
.setNdaTopDir( NdaDirectory
)
22 from Hurricane
import DataBase
, Cell
, Instance
, Net
23 from CRL
import AllianceFramework
24 from helpers
import overlay
, l
, u
, n
25 from NDA
.node180
.tsmc_c018
import (techno
, FlexLib
,
26 LibreSOCIO
, LibreSOCMem
, pll
)
34 # XXX TODO, important! fix the directions of the PLL cells
35 # https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/47
37 for cell
in pll
.getCells():
38 for net
in cell
.getNets():
40 if net
.getName() == 'vdd':
41 net
.setType( Net
.Type
.POWER
)
42 net
.setDirection( Net
.Direction
.IN
)
44 elif net
.getName() == 'vss':
45 net
.setType( Net
.Type
.GROUND
)
46 net
.setDirection( Net
.Direction
.IN
)
48 elif net
.getName() == 'ck':
49 net
.setType( Net
.Type
.CLOCK
)
50 net
.setDirection( Net
.Direction
.IN
)
51 # TODO review, should be good
52 elif net
.getName() in ['div_out_test', 'vco_test_ana', 'out_v']:
53 net
.setDirection( Net
.Direction
.OUT
)
54 # last option, set it as an input
56 net
.setDirection( Net
.Direction
.IN
)
58 # XXX TODO uncomment this line: fix_pll()
60 # XXX TODO same thing for spblock_512xxxetcxxx for "q" output data
63 af
= AllianceFramework
.get()
66 def createBlackbox (name
, libname
, cellName
, blackboxNames
, real_name
):
68 print( ' o Creating %s blackboxes for "ls180" design.' % name
)
69 rootlib
= db
.getRootLibrary()
70 lib
= rootlib
.getLibrary( libname
)
71 libcell
= lib
.getCell( cellName
)
73 raise ErrorMessage( 1, 'settings.createSramBlocks(): '
74 '%s SRAM Cell "%s" not found.' % \
76 libcell
.setAbstractedSupply( True )
77 for blackboxName
in blackboxNames
:
78 cell
= Cell
.create( lib
, blackboxName
)
79 instance
= Instance
.create( cell
, real_name
, libcell
)
80 state
= af
.getCatalog().getState( blackboxName
, True )
82 state
.setLogical( True )
83 state
.setInMemory( True )
84 print( ' - {}.'.format(cell
) )
85 for masterNet
in libcell
.getNets():
86 if not masterNet
.isExternal():
88 net
= Net
.create( cell
, masterNet
.getName() )
89 net
.setDirection( masterNet
.getDirection() )
90 net
.setType( masterNet
.getType() )
91 net
.setExternal( True )
92 net
.setGlobal( masterNet
.isGlobal() )
93 if masterNet
.isSupply():
95 plug
= instance
.getPlug( masterNet
)
99 #TODO, JP, check this, it's cut/paste and guessing
100 def createPLLBlackbox ():
101 createBlackbox(name
='PLL',
104 blackboxNames
= [ 'pll'
106 real_name
='real_pll') # probably
109 def createSramBlackbox ():
110 createBlackbox(name
='SRAM',
111 libname
='LibreSOCMem',
112 cellName
='spblock_512w64b8w',
113 # go back to only one blackbox
114 blackboxNames
= [ 'spblock_512w64b8w'
116 real_name
='real_sram')
119 with overlay
.CfgCache(priority
=Cfg
.Parameter
.Priority
.UserFile
) as cfg
:
120 cfg
.misc
.catchCore
= False
121 cfg
.misc
.minTraceLevel
= 12300
122 cfg
.misc
.maxTraceLevel
= 12400
123 cfg
.misc
.info
= False
124 cfg
.misc
.paranoid
= False
126 cfg
.misc
.logMode
= True
127 cfg
.misc
.verboseLevel1
= True
128 cfg
.misc
.verboseLevel2
= True
129 cfg
.etesian
.graphics
= 3
130 cfg
.etesian
.spaceMargin
= 0.10
131 cfg
.katana
.eventsLimit
= 4000000
132 env
= af
.getEnvironment()
133 env
.setCLOCK( '^sys_pllclk$|^ck|^jtag_tck$' )
135 #with overlay.UpdateSession():
136 # createSramBlackbox()
137 # createPLLBlackbox ()