LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = cmos45
            YOSYS_FLATTEN = No
                     CHIP = chip
                     CORE = add
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No
                  RM_CHIP = Yes

                 NETLISTS = $(shell cat netlists.txt)
#                PATTERNS = add_r


 include ./mk/design-flow.mk

chip_r.vst: add.vst
	-$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))

chip_r.ap: chip_r.vst


blif:      add.blif
vst:       add.vst

lvx:       lvx-chip_r
druc:      druc-chip_r
dreal:     dreal-chip_r
flatph:    flatph-chip_r
view:      cgt-chip_r

layout:    chip_r.ap
gds:       chip_r.gds
gds_flat:  chip_r_flat.gds
cif:  	   chip_r.cif

view:      cgt-chip_r
sim:       asimut-add_r