LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = FlexLib018
            YOSYS_FLATTEN = No
            YOSYS_SET_TOP = Yes
                    CHIP  = chip
                    CORE  = ls180
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No
                 RM_CHIP  = Yes
#               VST_FLAGS = --vst-use-concat

                 NETLISTS = ls180
#                NETLISTS = $(shell cat cells.lst)
#           YOSYS_FLATTEN = $(shell cat flatten.lst)



 include ./mk/design-flow.mk

chip_r.vst: ls180.vst
	-$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))

chip_r.ap: chip_r.vst

blif:      ls180.blif
vst:       ls180.vst
view:      cgt-chip_r
layout:    chip_r.ap