# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*- LOGICAL_SYNTHESIS = Yosys PHYSICAL_SYNTHESIS = Coriolis DESIGN_KIT = sxlib # YOSYS_FLATTEN = Yes USE_CLOCKTREE = Yes USE_DEBUG = No USE_KITE = No NETLISTS = $(shell cat nets2.txt) VST_FLAGS = --vst-use-concat include ./mk/design-flow.mk blif: part_sig_add.blif vst: part_sig_add.vst layout: part_sig_add_cts_r.ap gds: part_sig_add_cts_r.gds lvx: lvx-part_sig_add_cts_r druc: druc-part_sig_add_cts_r view: cgt-part_sig_add_cts_r