# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-

        LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

#           YOSYS_FLATTEN = Yes
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No

                 NETLISTS = $(shell cat nets4.txt)

                VST_FLAGS = --vst-use-concat

 include ./mk/design-flow.mk


blif:      test_add.blif
vst:       test_add.vst
layout:    test_add_cts_r.ap
gds:       test_add_cts_r.gds

lvx:       lvx-test_add_cts_r
druc:      druc-test_add_cts_r
view:      cgt-test_add_cts_r