# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-

        LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

#           YOSYS_FLATTEN = Yes
                     CHIP = chip
                     CORE = add
                   MARGIN = 2
                  BOOMOPT =  # -A
                  BOOGOPT =
                  LOONOPT =
                NSL2VHOPT = -vasy # -split -p
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No
#                 RM_CHIP = Yes

                 NETLISTS = $(shell cat nets.txt)
#                PATTERNS = add_r


 include ./mk/design-flow.mk


blif:      add.blif
vst:       add.vst

lvx:       lvx-chip_cts_r
druc:      druc-chip_cts_r
dreal:     dreal-chip_cts_r
flatph:     flatph-chip_cts_r
view:      cgt-chip_cts_r

layout:    chip_cts_r.ap
gds:       chip_cts_r.gds
gds_flat:  chip_cts_r_flat.gds
cif:  	   chip_cts_r.cif


view:      cgt-chip_cts_r
sim:       asimut-add_cts_r