# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-

        LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

#           YOSYS_FLATTEN = Yes
            USE_CLOCKTREE = No
                USE_DEBUG = No
                 USE_KITE = No

                 NETLISTS = $(shell cat nets.txt)
                 PATTERNS = alu_hier_r


 include ./mk/design-flow.mk


blif:      alu_hier.blif
vst:       alu_hier.vst
layout:    alu_hier_r.ap
gds:       alu_hier_r.gds

lvx:       lvx-alu_hier_r
druc:      druc-alu_hier_r
view:      cgt-alu_hier_r
sim:       asimut-alu_hier_r