LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

            USE_CLOCKTREE = No
                USE_DEBUG = No
                 USE_KITE = No
                VST_FLAGS = --vst-use-concat

                 NETLISTS = test_fu_fu_matrix


 include ./mk/design-flow.mk


%_flat.vst: %.vst ;  $(FLATLO) -r $* $*_flat


blif:      test_fu_fu_matrix.blif
vst:       test_fu_fu_matrix.vst
vstf:      test_fu_fu_matrix_flat.vst

#blif:      test_fu_reg_matrix.blif
#vst:       test_fu_reg_matrix.vst
#layout:    test_fu_reg_matrix_r.ap
#gds:       test_fu_reg_matrix_r.gds
#
#lvx:       lvx-test_fu_reg_matrix_r
#druc:      druc-test_fu_reg_matrix_r
#view:      cgt-test_fu_reg_matrix_r
viewf:     cgt-test_fu_fu_matrix_flat
#sim:       asimut-test_fu_reg_matrix_r