add TODO into tsmc_c018 coriolis2 settings.py

diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index 70993c75dcf9b1a35a5d9f9c626857dd6a8ab1cf..2a72d23035e6033c40147c1632670a9bd6eb60d9 100644 (file)
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -32,6 +32,33 @@ LibreSOCIO.setup()
 LibreSOCMem.setup()
 pll.setup()
 
+# XXX TODO, important! fix the directions of the PLL cells
+# https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/47
+def fix_pll():
+    for cell in pll.getCells():
+        for net in cell.getNets():
+            # TODO: review
+            if net.getName() == 'vdd':
+                net.setType( Net.Type.POWER )
+                net.setDirection( Net.Direction.IN )
+            # TODO: review
+            elif net.getName() == 'vss':
+                net.setType( Net.Type.GROUND )
+                net.setDirection( Net.Direction.IN )
+            # TODO: review
+            elif net.getName() == 'ck':
+                net.setType( Net.Type.CLOCK )
+                net.setDirection( Net.Direction.IN )
+            # TODO review, should be good
+            elif net.getName() in ['div_out_test', 'vco_test_ana', 'out_v']:
+                net.setDirection( Net.Direction.OUT )
+            # last option, set it as an input
+            else:
+                net.setDirection( Net.Direction.IN )
+
+# XXX TODO uncomment this line: fix_pll()
+
+# XXX TODO same thing for spblock_512xxxetcxxx for "q" output data
 
 db = DataBase.getDB()
 af = AllianceFramework.get()