wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_adr;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_addr_acked;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
input alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \alu_op__zero_a$71 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] \br_op__sv_saturate$29 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *)
(* generator = "nMigen" *)
module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *)
(* generator = "nMigen" *)
module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *)
(* generator = "nMigen" *)
module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *)
(* generator = "nMigen" *)
module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *)
(* generator = "nMigen" *)
module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *)
(* generator = "nMigen" *)
module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [63:0] fast1;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *)
(* generator = "nMigen" *)
module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, fast3_ok, nia_ok, msr_ok, svstate_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, o, fast1, fast2, fast3, nia, msr, svstate, ra, rb, \fast1$1 , \fast2$2 , \fast3$3 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [63:0] fast1;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_busy;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *)
output corebusy_o;
reg corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" *)
reg [1:0] counter = 2'h0;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] data_i;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_cyc;
wire \$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
wire \$99 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
input [6:0] core_dbg_core_dbg_dststep;
wire [63:0] log_dmi_data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *)
wire [31:0] log_write_addr_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *)
wire [63:0] stat_reg;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
(* generator = "nMigen" *)
module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest1__addr;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus" *)
(* generator = "nMigen" *)
module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_idx_l;
wire a_stall_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *)
input a_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
reg [44:0] f_badaddr_o = 45'h000000000000;
reg [63:0] ibus_rdata = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *)
reg [63:0] \ibus_rdata$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
input wb_icache_en;
(* generator = "nMigen" *)
module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [4:0] dest1__addr;
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *)
reg TAP_tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
input dmi0__ack_o;
wire posjtag_clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
wire posjtag_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
(* \nmigen.hierarchy = "test_issuer.ti.core.l0" *)
(* generator = "nMigen" *)
module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
wire [95:0] \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *)
wire [95:0] \$27 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
reg \idx_l$16 = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire alu_valid;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452" *)
wire cancel;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
input cu_ad__go_i;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$76 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$57 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *)
wire \$95 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$62 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$68 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg busy_l_r_busy;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
reg busy_l_s_busy;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
wire cyc_l_q_cyc;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$22 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] \br_op__sv_saturate$45 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$30 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
wire \alu_op__zero_a$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__zero_a$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$77 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_fast1;
reg \alu_op__zero_a$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \alu_op__zero_a$80 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$59 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$38 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$86 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output [3:0] cr_a;
wire \$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
input div_by_zero;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$78 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
output div_by_zero;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest10__data_i;
reg [63:0] \cia0__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia0__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest11__data_i;
reg [63:0] \cia1__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia1__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest12__data_i;
reg [63:0] \cia2__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia2__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest13__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest14__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest15__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest16__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest17__data_i;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [6:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [6:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [6:0] q_int = 7'h00;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [1:0] q_int = 2'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
output cr_a_ok;
(* generator = "nMigen" *)
module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *)
wire [3:0] memory_r_addr;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_0_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_1_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_2_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_3_wb__ack;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg [63:0] cia__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] cia__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] data_i;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer" *)
(* top = 1 *)
(* generator = "nMigen" *)
-module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *)
+module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *)
wire [1:0] \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tck;
output TAP_bus__tdo;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tms;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *)
input clk_sel_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
input core_bigendian_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
output jtag_wb__stb;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *)
output jtag_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:242" *)
input memerr_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input mspi0_clk__core__o;
input [63:0] pc_i;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input pc_i_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *)
output [63:0] pc_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1235" *)
- output pll_test_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *)
+ output pll_test_o;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *)
output pll_vco_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1252" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *)
wire pllclk_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1252" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *)
wire pllclk_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [63:0] sram4k_0_wb__dat_w;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
- input sram4k_0_wb__err;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [7:0] sram4k_0_wb__sel;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_0_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [63:0] sram4k_1_wb__dat_w;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
- input sram4k_1_wb__err;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [7:0] sram4k_1_wb__sel;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_1_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [63:0] sram4k_2_wb__dat_w;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
- input sram4k_2_wb__err;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [7:0] sram4k_2_wb__sel;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_2_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [63:0] sram4k_3_wb__dat_w;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
- input sram4k_3_wb__err;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input [7:0] sram4k_3_wb__sel;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
wire ti_coresync_clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
wire wrappll_clk_24_i;
wire wrappll_pll_test_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
wire wrappll_pll_vco_o;
- assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *) clk_sel_i;
+ assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *) clk_sel_i;
ti ti (
.TAP_bus__tck(TAP_bus__tck),
.TAP_bus__tdi(TAP_bus__tdi),
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *)
wire [6:0] \$101 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$104 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$106 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$108 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
wire \$11 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$110 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$112 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$114 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
wire \$116 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$118 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$120 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
wire [7:0] \$122 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
- wire [7:0] \$123 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
+ wire [7:0] \$123 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *)
wire [7:0] \$125 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *)
wire [7:0] \$126 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *)
wire \$128 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
wire [2:0] \$13 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$130 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$132 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$134 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$136 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$138 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
wire [2:0] \$14 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$140 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$142 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$144 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *)
wire \$146 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$148 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$150 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$152 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
wire \$154 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$156 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$158 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
wire \$16 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$160 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$162 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$164 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$166 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$168 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$170 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$172 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$174 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$176 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$178 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
wire \$18 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$180 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$182 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$184 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *)
wire [2:0] \$185 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$188 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$190 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$192 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$194 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$196 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$198 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
wire \$20 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
wire \$200 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$202 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$204 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$206 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$208 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$210 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$212 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$214 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$216 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$218 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *)
wire [2:0] \$219 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$22 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$222 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$224 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
wire \$226 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$228 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$230 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$232 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$234 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$236 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$238 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$24 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
wire \$240 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *)
wire [63:0] \$242 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *)
wire \$244 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
wire \$246 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
wire \$248 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [63:0] \$250 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [63:0] \$252 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
wire [64:0] \$254 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
wire [64:0] \$255 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
wire [64:0] \$257 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
wire [64:0] \$258 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
wire \$26 ;
wire [63:0] \$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$44 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$46 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$48 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$50 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$52 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$54 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$56 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$58 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
wire \$60 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$62 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$64 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$68 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
wire \$70 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$72 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$76 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$78 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
wire \$80 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
wire \$82 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$84 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
wire \$86 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
wire \$88 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *)
wire [64:0] \$90 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *)
wire [64:0] \$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
wire [31:0] \$93 ;
wire [6:0] \$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
wire [31:0] \$97 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *)
wire [64:0] \$98 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *)
wire [64:0] \$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tck;
output TAP_bus__tdo;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tms;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *)
reg [7:0] core_asmcode = 8'h00;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *)
reg [7:0] \core_asmcode$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
input core_bigendian_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
reg \core_bigendian_i$3 = 1'h0;
reg [2:0] \core_core_xer_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *)
wire core_corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
wire core_coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
reg core_cr_out_ok = 1'h0;
reg core_xer_out = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *)
reg \core_xer_out$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
reg cu_st__rel_o_dly = 1'h0;
wire \cu_st__rel_o_dly$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
wire cu_st__rel_o_rise;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
reg d_cr_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
reg \d_cr_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *)
reg d_reg_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *)
reg \d_reg_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
reg d_xer_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
reg \d_xer_delay$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
wire [6:0] dbg_core_dbg_core_dbg_dststep;
wire [2:0] dec2_xer_in;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *)
wire dec2_xer_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
reg [1:0] delay = 2'h3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
reg [1:0] \delay$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output eint_0__core__i;
output eint_2__core__i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input eint_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" *)
wire exc_happened;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
reg exec_fsm_state = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
reg \exec_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1033" *)
reg exec_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1031" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
reg exec_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1037" *)
reg exec_pc_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1035" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
reg exec_pc_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
reg [1:0] fetch_fsm_state = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
reg [1:0] \fetch_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021" *)
reg fetch_insn_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *)
reg fetch_insn_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" *)
reg fetch_pc_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1015" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
reg fetch_pc_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
reg [1:0] fsm_state = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
reg [1:0] \fsm_state$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output gpio_e10__core__i;
reg imem_f_valid_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
wire imem_wb_icache_en;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" *)
reg insn_done;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
input [15:0] int_level_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:774" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:775" *)
reg is_last;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1008" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1009" *)
wire is_svp64_mode;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
reg [2:0] issue_fsm_state = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
reg [2:0] \issue_fsm_state$next ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
reg jtag_dmi0__ack_o = 1'h0;
input mspi0_mosi__core__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output mspi0_mosi__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
reg msr_read = 1'h1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
reg \msr_read$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input mtwi_scl__core__o;
output mtwi_sda__pad__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output mtwi_sda__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1156" *)
reg [63:0] new_dec;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
reg [6:0] new_svstate_dststep;
reg [1:0] new_svstate_svstep;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *)
reg [6:0] new_svstate_vl;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
reg [63:0] new_tb;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
wire [6:0] next_dststep;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *)
wire [6:0] next_srcstep;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *)
reg [63:0] nia = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *)
reg [63:0] \nia$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg [63:0] pc;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
reg pc_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
reg \pc_changed$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input [63:0] pc_i;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
input pc_i_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *)
output [63:0] pc_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg pc_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg \pc_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:929" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
wire por_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1025" *)
wire pred_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1023" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
reg pred_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1029" *)
reg pred_mask_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1027" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *)
wire pred_mask_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *)
reg sv_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *)
reg \sv_changed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg [63:0] svstate;
reg svstate_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg \svstate_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:934" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *)
wire ti_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" *)
reg update_svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
wire xics_icp_core_irq_o;
wire [7:0] xics_ics_icp_o_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
wire [3:0] xics_ics_icp_o_src;
- assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
- assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4;
+ assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read;
+ assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *) 3'h4;
assign \$101 = \$98 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
assign \$97 = imem_f_instr_o >> \$101 ;
- assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$106 ;
- assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$112 ;
- assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
- assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
- assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) 1'h0;
- assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
- assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1;
- assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1;
- assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) core_exc_o_happened;
- assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$132 ;
- assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$138 ;
- assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
- assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$142 ;
- assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) is_svp64_mode;
- assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h1;
- assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$150 ;
- assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
- assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
- assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
- assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$162 ;
- assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) dbg_core_rst_o;
- assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$168 ;
- assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$174 ;
- assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$180 ;
- assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 1'h1;
+ assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$106 ;
+ assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$112 ;
+ assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
+ assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
+ assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h0;
+ assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
+ assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1;
+ assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *) 1'h1;
+ assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_exc_o_happened;
+ assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$132 ;
+ assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$138 ;
+ assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
+ assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$142 ;
+ assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *) is_svp64_mode;
+ assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) 1'h1;
+ assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$150 ;
+ assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
+ assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
+ assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
+ assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$162 ;
+ assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) dbg_core_rst_o;
+ assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$168 ;
+ assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$174 ;
+ assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$180 ;
+ assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *) 1'h1;
assign \$184 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$185 ;
- assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) rst;
- assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$190 ;
- assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$196 ;
- assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
- assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
- assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
- assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) \$18 ;
- assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$208 ;
- assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$214 ;
- assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) 3'h4;
+ assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) rst;
+ assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$190 ;
+ assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$196 ;
+ assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
+ assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
+ assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
+ assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) \$18 ;
+ assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$208 ;
+ assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$214 ;
+ assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *) 3'h4;
assign \$218 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$219 ;
- assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
- assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$222 ;
- assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
- assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+ assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
+ assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$222 ;
+ assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
+ assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
- assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$230 ;
- assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$236 ;
- assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) dec2_cur_cur_vl;
+ assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$230 ;
+ assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$236 ;
+ assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) dec2_cur_cur_vl;
assign \$242 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
- assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) 7'h01;
- assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
- assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
+ assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *) 7'h01;
+ assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
+ assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
assign \$24 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$22 ;
assign \$250 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
assign \$252 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
- assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) 1'h1;
- assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) 1'h1;
+ assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) 1'h1;
+ assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) 1'h1;
assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok;
assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$40 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) svstate_i;
assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
- assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$46 ;
- assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
- assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$50 ;
- assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$56 ;
- assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
- assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
- assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
- assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
- assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
- assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$68 ;
- assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
- assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$72 ;
- assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
- assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
- assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$78 ;
- assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
- assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
- assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
- assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
- assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4;
+ assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$46 ;
+ assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
+ assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$50 ;
+ assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$56 ;
+ assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
+ assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
+ assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
+ assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
+ assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
+ assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$68 ;
+ assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
+ assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$72 ;
+ assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
+ assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$78 ;
+ assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
+ assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
+ assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
+ assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read;
+ assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *) 3'h4;
assign \$94 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
assign \$93 = imem_f_instr_o >> \$94 ;
always @(posedge clk)
always @* begin
if (\initial ) begin end
\delay$next = delay;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
casez (\$11 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" */
1'h1:
\delay$next = \$13 [1:0];
endcase
\core_core_srcstep$next = core_core_srcstep;
\core_core_vl$next = core_core_vl;
\core_core_maxvl$next = core_core_maxvl;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
{ \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_core_msr$next , \core_core_pc$next } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc };
endcase
always @* begin
if (\initial ) begin end
\core_raw_insn_i$next = core_raw_insn_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
\core_raw_insn_i$next = dec2_raw_opcode_in;
endcase
always @* begin
if (\initial ) begin end
\core_bigendian_i$3$next = \core_bigendian_i$3 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
\core_bigendian_i$3$next = core_bigendian_i;
endcase
always @* begin
if (\initial ) begin end
exec_insn_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
exec_insn_valid_i = 1'h1;
endcase
if (\initial ) begin end
exec_pc_ready_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$232 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
exec_pc_ready_i = 1'h1;
endcase
if (\initial ) begin end
is_last = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$238 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
is_last = \$240 ;
endcase
always @* begin
if (\initial ) begin end
\core_wen$4 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
1'h1:
\core_wen$4 = 3'h4;
endcase
always @* begin
if (\initial ) begin end
\core_data_i$5 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
1'h1:
\core_data_i$5 = \$242 ;
endcase
always @* begin
if (\initial ) begin end
exec_insn_ready_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
exec_insn_ready_o = 1'h1;
endcase
if (\initial ) begin end
core_ivalid_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
1'h1:
core_ivalid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *)
casez (\$244 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" */
1'h1:
core_ivalid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
1'h1:
core_issue_i = 1'h1;
endcase
if (\initial ) begin end
\exec_fsm_state$next = exec_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
1'h1:
\exec_fsm_state$next = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
casez (\$246 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */
1'h1:
\exec_fsm_state$next = 1'h0;
endcase
if (\initial ) begin end
exec_pc_valid_o = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
casez (\$248 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
1'h1:
exec_pc_valid_o = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_dmi__addr = 5'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
1'h1:
core_dmi__addr = dbg_d_gpr_addr[4:0];
endcase
always @* begin
if (\initial ) begin end
core_dmi__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
1'h1:
core_dmi__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */
1'h1:
dbg_d_gpr_data = core_dmi__data_o;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */
1'h1:
dbg_d_gpr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd2__ren = 8'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" *)
casez (dbg_d_cr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" */
1'h1:
core_full_rd2__ren = 8'hff;
endcase
always @* begin
if (\initial ) begin end
dbg_d_cr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */
1'h1:
dbg_d_cr_data = \$250 ;
endcase
always @* begin
if (\initial ) begin end
dbg_d_cr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */
1'h1:
dbg_d_cr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd__ren = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" *)
casez (dbg_d_xer_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" */
1'h1:
core_full_rd__ren = 3'h7;
endcase
always @* begin
if (\initial ) begin end
dbg_d_xer_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */
1'h1:
dbg_d_xer_data = \$252 ;
endcase
always @* begin
if (\initial ) begin end
dbg_d_xer_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */
1'h1:
dbg_d_xer_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue__addr = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
core_issue__addr = 4'h6;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
core_issue__addr = 4'h7;
endcase
always @* begin
if (\initial ) begin end
core_issue__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
core_issue__ren = 1'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
core_issue__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
\fsm_state$next = 2'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
\fsm_state$next = 2'h2;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
\fsm_state$next = 2'h3;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
2'h3:
\fsm_state$next = 2'h0;
endcase
always @* begin
if (\initial ) begin end
new_dec = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
new_dec = \$254 [63:0];
endcase
if (\initial ) begin end
\core_issue__addr$6 = 4'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
\core_issue__addr$6 = 4'h6;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
2'h3:
\core_issue__addr$6 = 4'h7;
endcase
if (\initial ) begin end
core_issue__wen = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
core_issue__wen = 1'h1;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
2'h3:
core_issue__wen = 1'h1;
endcase
if (\initial ) begin end
core_issue__data_i = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
core_issue__data_i = new_dec;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
2'h3:
core_issue__data_i = new_tb;
endcase
if (\initial ) begin end
new_tb = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
2'h3:
new_tb = \$257 [63:0];
endcase
\dec2_cur_cur_vl$next = dec2_cur_cur_vl;
\dec2_cur_cur_maxvl$next = dec2_cur_cur_maxvl;
\dec2_cur_eint$next = xics_icp_core_irq_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" */
1'h1:
{ \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
begin
\dec2_cur_pc$next = pc;
end
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
casez (\$9 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */
1'h1:
\dec2_cur_msr$next = core_msr__data_o;
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
1'h1:
{ \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
2'h1:
\dec2_cur_dec$next = new_dec;
endcase
if (\initial ) begin end
core_wen = 3'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$48 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
casez (\$52 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$58 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez ({ \$64 , \$60 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
2'b1?:
core_wen = 3'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
1'h1:
core_wen = 3'h1;
endcase
if (\initial ) begin end
core_data_i = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$70 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
1'h1:
core_data_i = pc_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
casez (\$74 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
1'h1:
core_data_i = nia;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$80 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez ({ \$86 , \$82 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
2'b1?:
core_data_i = nia;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
1'h1:
core_data_i = pc_i;
endcase
always @* begin
if (\initial ) begin end
core_msr__ren = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
core_msr__ren = 3'h2;
endcase
always @* begin
if (\initial ) begin end
fetch_pc_ready_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
fetch_pc_ready_o = 1'h1;
endcase
always @* begin
if (\initial ) begin end
imem_a_pc_i = 48'h000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
imem_a_pc_i = pc[47:0];
endcase
always @* begin
if (\initial ) begin end
imem_a_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
2'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
imem_f_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
2'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
\msr_read$next = msr_read;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
\msr_read$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
casez (\$88 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */
1'h1:
\msr_read$next = 1'h1;
endcase
if (\initial ) begin end
\fetch_fsm_state$next = fetch_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
1'h1:
\fetch_fsm_state$next = 2'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
default:
\fetch_fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
2'h3:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
default:
\fetch_fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "INSN_READY/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */
2'h2:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" *)
casez (fetch_insn_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" */
1'h1:
\fetch_fsm_state$next = 2'h0;
endcase
always @* begin
if (\initial ) begin end
\nia$next = nia;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
default:
\nia$next = \$90 [63:0];
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" */
1'h1:
\nia$next = 64'h0000000000000000;
endcase
always @* begin
if (\initial ) begin end
\dec2_raw_opcode_in$next = dec2_raw_opcode_in;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
default:
\dec2_raw_opcode_in$next = \$93 ;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
2'h3:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
default:
\dec2_raw_opcode_in$next = \$97 ;
endcase
if (\initial ) begin end
fetch_insn_valid_o = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
2'h1:
/* empty */;
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
2'h3:
/* empty */;
/* \nmigen.decoding = "INSN_READY/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */
2'h2:
fetch_insn_valid_o = 1'h1;
endcase
if (\initial ) begin end
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep };
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$108 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$114 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez ({ \$120 , \$116 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
2'b1?:
begin
new_svstate_srcstep = 7'h00;
new_svstate_dststep = 7'h00;
end
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
default:
begin
new_svstate_srcstep = next_srcstep;
end
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
always @* begin
if (\initial ) begin end
fetch_pc_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$134 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
fetch_pc_valid_i = 1'h1;
endcase
if (\initial ) begin end
\issue_fsm_state$next = issue_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$140 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *)
casez (fetch_pc_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */
1'h1:
\issue_fsm_state$next = 3'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
casez (\$144 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
1'h1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:648" */
default:
\issue_fsm_state$next = 3'h2;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *)
casez (pred_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" */
1'h1:
\issue_fsm_state$next = 3'h4;
endcase
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" *)
casez (pred_mask_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" */
1'h1:
\issue_fsm_state$next = 3'h5;
endcase
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *)
casez (\$146 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" */
1'h1:
\issue_fsm_state$next = 3'h2;
endcase
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
\issue_fsm_state$next = 3'h6;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *)
casez (exec_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */
1'h1:
\issue_fsm_state$next = 3'h7;
endcase
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$152 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez ({ \$158 , \$154 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
2'b?1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
2'b1?:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
default:
\issue_fsm_state$next = 3'h5;
endcase
if (\initial ) begin end
dbg_core_stopped_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$164 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
dbg_core_stopped_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$170 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
dbg_core_stopped_i = 1'h1;
endcase
if (\initial ) begin end
\pc_changed$next = pc_changed;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$176 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$182 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
1'h1:
\pc_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *)
casez (\$184 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" */
1'h1:
\pc_changed$next = 1'h1;
endcase
if (\initial ) begin end
update_svstate = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$192 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
update_svstate = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$198 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez ({ \$204 , \$200 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
2'b1?:
update_svstate = 1'h1;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
default:
update_svstate = 1'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
update_svstate = 1'h1;
endcase
if (\initial ) begin end
\sv_changed$next = sv_changed;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
casez (\$210 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
casez (\$216 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
1'h1:
\sv_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *)
casez (\$218 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
\sv_changed$next = 1'h1;
endcase
always @* begin
if (\initial ) begin end
fetch_insn_ready_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
fetch_insn_ready_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
insn_done = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
casez (\$224 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
1'h1:
insn_done = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
casez (\$226 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */
1'h1:
insn_done = 1'h1;
endcase
always @* begin
if (\initial ) begin end
pred_insn_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
pred_insn_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
pred_mask_ready_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
pred_mask_ready_i = 1'h1;
endcase
\core_core_core_cr_wr$next = core_core_core_cr_wr;
\core_core_cr_wr_ok$next = core_core_cr_wr_ok;
\core_core_core_is_32bit$next = core_core_core_is_32bit;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
3'h2:
{ \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_happened$next , \core_core_core_exc_segment_fault$next , \core_core_core_exc_rc_error$next , \core_core_core_exc_perm_error$next , \core_core_core_exc_badtree$next , \core_core_core_exc_invalid$next , \core_core_core_exc_instr_fault$next , \core_core_core_exc_alignment$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment, dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$8 , \dec2_cr_in2$7 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
endcase
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] data_i;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
output core_irq_o;
reg [7:0] min_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *)
reg [7:0] pending_priority;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
reg wb_ack = 1'h0;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
reg [3:0] cur_idx0;
wire reg_is_debug;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *)
wire reg_is_xive;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *)
wire wb_valid;
projects / soclayout.git / commitdiff