# Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os)
-autoidx 15032
+autoidx 14844
attribute \src "libresoc.v:5.1-335.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21209.7-21209.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 6 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21271.7-21271.15"
wire \initial
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 33 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 25 \src1_i
+ wire width 64 input 26 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 26 \src2_i
+ wire width 64 input 25 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 27 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 18 \alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 28 \cr_a
wire input 13 \br_op__lk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 20 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0"
attribute \generator "nMigen"
module \alu_cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 12 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0"
attribute \generator "nMigen"
module \alu_div0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 35 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 27 \cr_a
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26289.7-26289.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26351.7-26351.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26413.7-26413.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26475.7-26475.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26537.7-26537.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26599.7-26599.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26661.7-26661.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26723.7-26723.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26785.7-26785.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26847.7-26847.15"
wire \initial
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0"
attribute \generator "nMigen"
module \alu_logical0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0"
attribute \generator "nMigen"
module \alu_mul0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 21 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0"
attribute \generator "nMigen"
module \alu_shift_rot0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0"
attribute \generator "nMigen"
module \alu_spr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 28 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 output 16 \fast1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0"
attribute \generator "nMigen"
module \alu_trap0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 output 19 \fast1
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31623.7-31623.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31685.7-31685.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31747.7-31747.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31809.7-31809.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31871.7-31871.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31933.7-31933.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31995.7-31995.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:32057.7-32057.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:32119.7-32119.15"
wire \initial
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 11 \cu_busy_o
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "libresoc.v:34588.7-34588.15"
wire \initial
connect \pair2 \sig_in [3:2]
connect \pair0 \sig_in [1:0]
end
-attribute \src "libresoc.v:36261.1-49193.10"
+attribute \src "libresoc.v:36261.1-49121.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core"
attribute \generator "nMigen"
module \core
- attribute \src "libresoc.v:46639.3-46659.6"
- wire $0\core_terminate_o$next[0:0]$2673
- attribute \src "libresoc.v:43030.3-43031.49"
+ attribute \src "libresoc.v:46594.3-46614.6"
+ wire $0\core_terminate_o$next[0:0]$2679
+ attribute \src "libresoc.v:42990.3-42991.49"
wire $0\core_terminate_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $0\corebusy_o[0:0]
- attribute \src "libresoc.v:46479.3-46509.6"
- wire width 2 $0\counter$next[1:0]$2654
- attribute \src "libresoc.v:43032.3-43033.31"
+ attribute \src "libresoc.v:46424.3-46454.6"
+ wire width 2 $0\counter$next[1:0]$2657
+ attribute \src "libresoc.v:42992.3-42993.31"
wire width 2 $0\counter[1:0]
- attribute \src "libresoc.v:46460.3-46468.6"
+ attribute \src "libresoc.v:46396.3-46404.6"
wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648
- attribute \src "libresoc.v:42966.3-42967.57"
+ attribute \src "libresoc.v:42926.3-42927.57"
wire $0\dp_CR_cr_a_branch0_1[0:0]
- attribute \src "libresoc.v:46441.3-46449.6"
+ attribute \src "libresoc.v:46377.3-46385.6"
wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642
- attribute \src "libresoc.v:42968.3-42969.49"
+ attribute \src "libresoc.v:42928.3-42929.49"
wire $0\dp_CR_cr_a_cr0_0[0:0]
- attribute \src "libresoc.v:46510.3-46518.6"
- wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660
- attribute \src "libresoc.v:42964.3-42965.49"
+ attribute \src "libresoc.v:46415.3-46423.6"
+ wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2654
+ attribute \src "libresoc.v:42924.3-42925.49"
wire $0\dp_CR_cr_b_cr0_0[0:0]
- attribute \src "libresoc.v:46620.3-46628.6"
- wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667
- attribute \src "libresoc.v:42962.3-42963.49"
+ attribute \src "libresoc.v:46465.3-46473.6"
+ wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666
+ attribute \src "libresoc.v:42922.3-42923.49"
wire $0\dp_CR_cr_c_cr0_0[0:0]
- attribute \src "libresoc.v:46422.3-46430.6"
+ attribute \src "libresoc.v:46358.3-46366.6"
wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636
- attribute \src "libresoc.v:42970.3-42971.55"
+ attribute \src "libresoc.v:42930.3-42931.55"
wire $0\dp_CR_full_cr_cr0_0[0:0]
- attribute \src "libresoc.v:46660.3-46668.6"
- wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678
- attribute \src "libresoc.v:42960.3-42961.63"
+ attribute \src "libresoc.v:46575.3-46583.6"
+ wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2673
+ attribute \src "libresoc.v:42920.3-42921.63"
wire $0\dp_FAST_fast1_branch0_0[0:0]
- attribute \src "libresoc.v:46727.3-46735.6"
- wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691
- attribute \src "libresoc.v:42956.3-42957.57"
+ attribute \src "libresoc.v:46682.3-46690.6"
+ wire $0\dp_FAST_fast1_branch0_3$next[0:0]$2697
+ attribute \src "libresoc.v:42914.3-42915.63"
+ wire $0\dp_FAST_fast1_branch0_3[0:0]
+ attribute \src "libresoc.v:46634.3-46642.6"
+ wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2690
+ attribute \src "libresoc.v:42916.3-42917.57"
wire $0\dp_FAST_fast1_spr0_2[0:0]
- attribute \src "libresoc.v:46679.3-46687.6"
+ attribute \src "libresoc.v:46615.3-46623.6"
wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684
- attribute \src "libresoc.v:42958.3-42959.59"
+ attribute \src "libresoc.v:42918.3-42919.59"
wire $0\dp_FAST_fast1_trap0_1[0:0]
- attribute \src "libresoc.v:46775.3-46783.6"
- wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698
- attribute \src "libresoc.v:42954.3-42955.63"
- wire $0\dp_FAST_fast2_branch0_0[0:0]
- attribute \src "libresoc.v:46794.3-46802.6"
- wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704
- attribute \src "libresoc.v:42952.3-42953.59"
- wire $0\dp_FAST_fast2_trap0_1[0:0]
- attribute \src "libresoc.v:45871.3-45879.6"
- wire $0\dp_INT_ra_alu0_0$next[0:0]$2474
- attribute \src "libresoc.v:43028.3-43029.49"
- wire $0\dp_INT_ra_alu0_0[0:0]
- attribute \src "libresoc.v:45890.3-45898.6"
- wire $0\dp_INT_ra_cr0_1$next[0:0]$2478
- attribute \src "libresoc.v:43026.3-43027.47"
- wire $0\dp_INT_ra_cr0_1[0:0]
- attribute \src "libresoc.v:45966.3-45974.6"
- wire $0\dp_INT_ra_div0_5$next[0:0]$2502
- attribute \src "libresoc.v:43018.3-43019.49"
- wire $0\dp_INT_ra_div0_5[0:0]
- attribute \src "libresoc.v:46023.3-46031.6"
- wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520
- attribute \src "libresoc.v:43012.3-43013.51"
- wire $0\dp_INT_ra_ldst0_8[0:0]
- attribute \src "libresoc.v:45928.3-45936.6"
- wire $0\dp_INT_ra_logical0_3$next[0:0]$2490
- attribute \src "libresoc.v:43022.3-43023.57"
- wire $0\dp_INT_ra_logical0_3[0:0]
- attribute \src "libresoc.v:45985.3-45993.6"
- wire $0\dp_INT_ra_mul0_6$next[0:0]$2508
- attribute \src "libresoc.v:43016.3-43017.49"
- wire $0\dp_INT_ra_mul0_6[0:0]
- attribute \src "libresoc.v:46004.3-46012.6"
- wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514
- attribute \src "libresoc.v:43014.3-43015.59"
- wire $0\dp_INT_ra_shiftrot0_7[0:0]
- attribute \src "libresoc.v:45947.3-45955.6"
- wire $0\dp_INT_ra_spr0_4$next[0:0]$2496
- attribute \src "libresoc.v:43020.3-43021.49"
- wire $0\dp_INT_ra_spr0_4[0:0]
- attribute \src "libresoc.v:45909.3-45917.6"
- wire $0\dp_INT_ra_trap0_2$next[0:0]$2484
- attribute \src "libresoc.v:43024.3-43025.51"
- wire $0\dp_INT_ra_trap0_2[0:0]
- attribute \src "libresoc.v:46042.3-46050.6"
- wire $0\dp_INT_rb_alu0_0$next[0:0]$2526
- attribute \src "libresoc.v:43010.3-43011.49"
- wire $0\dp_INT_rb_alu0_0[0:0]
- attribute \src "libresoc.v:46061.3-46069.6"
- wire $0\dp_INT_rb_cr0_1$next[0:0]$2530
- attribute \src "libresoc.v:43008.3-43009.47"
- wire $0\dp_INT_rb_cr0_1[0:0]
- attribute \src "libresoc.v:46118.3-46126.6"
- wire $0\dp_INT_rb_div0_4$next[0:0]$2548
- attribute \src "libresoc.v:43002.3-43003.49"
- wire $0\dp_INT_rb_div0_4[0:0]
- attribute \src "libresoc.v:46175.3-46183.6"
- wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566
- attribute \src "libresoc.v:42996.3-42997.51"
- wire $0\dp_INT_rb_ldst0_7[0:0]
- attribute \src "libresoc.v:46099.3-46107.6"
- wire $0\dp_INT_rb_logical0_3$next[0:0]$2542
- attribute \src "libresoc.v:43004.3-43005.57"
- wire $0\dp_INT_rb_logical0_3[0:0]
- attribute \src "libresoc.v:46137.3-46145.6"
- wire $0\dp_INT_rb_mul0_5$next[0:0]$2554
- attribute \src "libresoc.v:43000.3-43001.49"
- wire $0\dp_INT_rb_mul0_5[0:0]
- attribute \src "libresoc.v:46156.3-46164.6"
- wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560
- attribute \src "libresoc.v:42998.3-42999.59"
- wire $0\dp_INT_rb_shiftrot0_6[0:0]
- attribute \src "libresoc.v:46080.3-46088.6"
- wire $0\dp_INT_rb_trap0_2$next[0:0]$2536
- attribute \src "libresoc.v:43006.3-43007.51"
- wire $0\dp_INT_rb_trap0_2[0:0]
- attribute \src "libresoc.v:46213.3-46221.6"
- wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576
- attribute \src "libresoc.v:42992.3-42993.51"
- wire $0\dp_INT_rc_ldst0_1[0:0]
- attribute \src "libresoc.v:46194.3-46202.6"
- wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572
- attribute \src "libresoc.v:42994.3-42995.59"
- wire $0\dp_INT_rc_shiftrot0_0[0:0]
- attribute \src "libresoc.v:46843.3-46851.6"
- wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711
- attribute \src "libresoc.v:42950.3-42951.53"
+ attribute \src "libresoc.v:46701.3-46709.6"
+ wire $0\dp_FAST_fast1_trap0_4$next[0:0]$2703
+ attribute \src "libresoc.v:42912.3-42913.59"
+ wire $0\dp_FAST_fast1_trap0_4[0:0]
+ attribute \src "libresoc.v:45807.3-45815.6"
+ wire $0\dp_INT_rabc_alu0_0$next[0:0]$2474
+ attribute \src "libresoc.v:42988.3-42989.53"
+ wire $0\dp_INT_rabc_alu0_0[0:0]
+ attribute \src "libresoc.v:45997.3-46005.6"
+ wire $0\dp_INT_rabc_alu0_10$next[0:0]$2530
+ attribute \src "libresoc.v:42968.3-42969.55"
+ wire $0\dp_INT_rabc_alu0_10[0:0]
+ attribute \src "libresoc.v:45826.3-45834.6"
+ wire $0\dp_INT_rabc_cr0_1$next[0:0]$2478
+ attribute \src "libresoc.v:46016.3-46024.6"
+ wire $0\dp_INT_rabc_cr0_11$next[0:0]$2534
+ attribute \src "libresoc.v:42966.3-42967.53"
+ wire $0\dp_INT_rabc_cr0_11[0:0]
+ attribute \src "libresoc.v:42986.3-42987.51"
+ wire $0\dp_INT_rabc_cr0_1[0:0]
+ attribute \src "libresoc.v:46092.3-46100.6"
+ wire $0\dp_INT_rabc_div0_15$next[0:0]$2558
+ attribute \src "libresoc.v:42958.3-42959.55"
+ wire $0\dp_INT_rabc_div0_15[0:0]
+ attribute \src "libresoc.v:45883.3-45891.6"
+ wire $0\dp_INT_rabc_div0_4$next[0:0]$2496
+ attribute \src "libresoc.v:42980.3-42981.53"
+ wire $0\dp_INT_rabc_div0_4[0:0]
+ attribute \src "libresoc.v:46149.3-46157.6"
+ wire $0\dp_INT_rabc_ldst0_18$next[0:0]$2576
+ attribute \src "libresoc.v:42952.3-42953.57"
+ wire $0\dp_INT_rabc_ldst0_18[0:0]
+ attribute \src "libresoc.v:45940.3-45948.6"
+ wire $0\dp_INT_rabc_ldst0_7$next[0:0]$2514
+ attribute \src "libresoc.v:42974.3-42975.55"
+ wire $0\dp_INT_rabc_ldst0_7[0:0]
+ attribute \src "libresoc.v:45978.3-45986.6"
+ wire $0\dp_INT_rabc_ldst0_9$next[0:0]$2524
+ attribute \src "libresoc.v:42970.3-42971.55"
+ wire $0\dp_INT_rabc_ldst0_9[0:0]
+ attribute \src "libresoc.v:46054.3-46062.6"
+ wire $0\dp_INT_rabc_logical0_13$next[0:0]$2546
+ attribute \src "libresoc.v:42962.3-42963.63"
+ wire $0\dp_INT_rabc_logical0_13[0:0]
+ attribute \src "libresoc.v:45864.3-45872.6"
+ wire $0\dp_INT_rabc_logical0_3$next[0:0]$2490
+ attribute \src "libresoc.v:42982.3-42983.61"
+ wire $0\dp_INT_rabc_logical0_3[0:0]
+ attribute \src "libresoc.v:46111.3-46119.6"
+ wire $0\dp_INT_rabc_mul0_16$next[0:0]$2564
+ attribute \src "libresoc.v:42956.3-42957.55"
+ wire $0\dp_INT_rabc_mul0_16[0:0]
+ attribute \src "libresoc.v:45902.3-45910.6"
+ wire $0\dp_INT_rabc_mul0_5$next[0:0]$2502
+ attribute \src "libresoc.v:42978.3-42979.53"
+ wire $0\dp_INT_rabc_mul0_5[0:0]
+ attribute \src "libresoc.v:46130.3-46138.6"
+ wire $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570
+ attribute \src "libresoc.v:42954.3-42955.65"
+ wire $0\dp_INT_rabc_shiftrot0_17[0:0]
+ attribute \src "libresoc.v:45921.3-45929.6"
+ wire $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508
+ attribute \src "libresoc.v:42976.3-42977.63"
+ wire $0\dp_INT_rabc_shiftrot0_6[0:0]
+ attribute \src "libresoc.v:45959.3-45967.6"
+ wire $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520
+ attribute \src "libresoc.v:42972.3-42973.63"
+ wire $0\dp_INT_rabc_shiftrot0_8[0:0]
+ attribute \src "libresoc.v:46073.3-46081.6"
+ wire $0\dp_INT_rabc_spr0_14$next[0:0]$2552
+ attribute \src "libresoc.v:42960.3-42961.55"
+ wire $0\dp_INT_rabc_spr0_14[0:0]
+ attribute \src "libresoc.v:46035.3-46043.6"
+ wire $0\dp_INT_rabc_trap0_12$next[0:0]$2540
+ attribute \src "libresoc.v:42964.3-42965.57"
+ wire $0\dp_INT_rabc_trap0_12[0:0]
+ attribute \src "libresoc.v:45845.3-45853.6"
+ wire $0\dp_INT_rabc_trap0_2$next[0:0]$2484
+ attribute \src "libresoc.v:42984.3-42985.55"
+ wire $0\dp_INT_rabc_trap0_2[0:0]
+ attribute \src "libresoc.v:46749.3-46757.6"
+ wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2710
+ attribute \src "libresoc.v:42910.3-42911.53"
wire $0\dp_SPR_spr1_spr0_0[0:0]
- attribute \src "libresoc.v:46346.3-46354.6"
+ attribute \src "libresoc.v:46282.3-46290.6"
wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616
- attribute \src "libresoc.v:42978.3-42979.57"
+ attribute \src "libresoc.v:42938.3-42939.57"
wire $0\dp_XER_xer_ca_alu0_0[0:0]
- attribute \src "libresoc.v:46384.3-46392.6"
+ attribute \src "libresoc.v:46320.3-46328.6"
wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626
- attribute \src "libresoc.v:42974.3-42975.67"
+ attribute \src "libresoc.v:42934.3-42935.67"
wire $0\dp_XER_xer_ca_shiftrot0_2[0:0]
- attribute \src "libresoc.v:46365.3-46373.6"
+ attribute \src "libresoc.v:46301.3-46309.6"
wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622
- attribute \src "libresoc.v:42976.3-42977.57"
+ attribute \src "libresoc.v:42936.3-42937.57"
wire $0\dp_XER_xer_ca_spr0_1[0:0]
- attribute \src "libresoc.v:46403.3-46411.6"
+ attribute \src "libresoc.v:46339.3-46347.6"
wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630
- attribute \src "libresoc.v:42972.3-42973.57"
+ attribute \src "libresoc.v:42932.3-42933.57"
wire $0\dp_XER_xer_ov_spr0_0[0:0]
- attribute \src "libresoc.v:46232.3-46240.6"
+ attribute \src "libresoc.v:46168.3-46176.6"
wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582
- attribute \src "libresoc.v:42990.3-42991.57"
+ attribute \src "libresoc.v:42950.3-42951.57"
wire $0\dp_XER_xer_so_alu0_0[0:0]
- attribute \src "libresoc.v:46289.3-46297.6"
+ attribute \src "libresoc.v:46225.3-46233.6"
wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598
- attribute \src "libresoc.v:42984.3-42985.57"
+ attribute \src "libresoc.v:42944.3-42945.57"
wire $0\dp_XER_xer_so_div0_3[0:0]
- attribute \src "libresoc.v:46251.3-46259.6"
+ attribute \src "libresoc.v:46187.3-46195.6"
wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588
- attribute \src "libresoc.v:42988.3-42989.65"
+ attribute \src "libresoc.v:42948.3-42949.65"
wire $0\dp_XER_xer_so_logical0_1[0:0]
- attribute \src "libresoc.v:46308.3-46316.6"
+ attribute \src "libresoc.v:46244.3-46252.6"
wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604
- attribute \src "libresoc.v:42982.3-42983.57"
+ attribute \src "libresoc.v:42942.3-42943.57"
wire $0\dp_XER_xer_so_mul0_4[0:0]
- attribute \src "libresoc.v:46327.3-46335.6"
+ attribute \src "libresoc.v:46263.3-46271.6"
wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610
- attribute \src "libresoc.v:42980.3-42981.67"
+ attribute \src "libresoc.v:42940.3-42941.67"
wire $0\dp_XER_xer_so_shiftrot0_5[0:0]
- attribute \src "libresoc.v:46270.3-46278.6"
+ attribute \src "libresoc.v:46206.3-46214.6"
wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594
- attribute \src "libresoc.v:42986.3-42987.57"
+ attribute \src "libresoc.v:42946.3-42947.57"
wire $0\dp_XER_xer_so_spr0_2[0:0]
- attribute \src "libresoc.v:47618.3-47646.6"
- wire $0\fus_cu_issue_i$13[0:0]$2821
- attribute \src "libresoc.v:47952.3-47980.6"
+ attribute \src "libresoc.v:47563.3-47591.6"
+ wire $0\fus_cu_issue_i$13[0:0]$2824
+ attribute \src "libresoc.v:47888.3-47916.6"
wire $0\fus_cu_issue_i$16[0:0]$2862
- attribute \src "libresoc.v:48271.3-48299.6"
+ attribute \src "libresoc.v:48207.3-48235.6"
wire $0\fus_cu_issue_i$19[0:0]$2881
- attribute \src "libresoc.v:43916.3-43944.6"
+ attribute \src "libresoc.v:43852.3-43880.6"
wire $0\fus_cu_issue_i$22[0:0]$2359
- attribute \src "libresoc.v:44090.3-44118.6"
+ attribute \src "libresoc.v:44026.3-44054.6"
wire $0\fus_cu_issue_i$25[0:0]$2373
- attribute \src "libresoc.v:44586.3-44614.6"
+ attribute \src "libresoc.v:44522.3-44550.6"
wire $0\fus_cu_issue_i$28[0:0]$2398
- attribute \src "libresoc.v:44908.3-44936.6"
+ attribute \src "libresoc.v:44844.3-44872.6"
wire $0\fus_cu_issue_i$31[0:0]$2417
- attribute \src "libresoc.v:45375.3-45403.6"
+ attribute \src "libresoc.v:45311.3-45339.6"
wire $0\fus_cu_issue_i$34[0:0]$2441
- attribute \src "libresoc.v:45813.3-45841.6"
+ attribute \src "libresoc.v:45749.3-45777.6"
wire $0\fus_cu_issue_i$37[0:0]$2464
- attribute \src "libresoc.v:47401.3-47429.6"
+ attribute \src "libresoc.v:47355.3-47383.6"
wire $0\fus_cu_issue_i[0:0]
- attribute \src "libresoc.v:47656.3-47684.6"
- wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829
- attribute \src "libresoc.v:47981.3-48009.6"
+ attribute \src "libresoc.v:47610.3-47638.6"
+ wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2835
+ attribute \src "libresoc.v:47917.3-47945.6"
wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867
- attribute \src "libresoc.v:48300.3-48328.6"
+ attribute \src "libresoc.v:48236.3-48264.6"
wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886
- attribute \src "libresoc.v:43945.3-43973.6"
+ attribute \src "libresoc.v:43881.3-43909.6"
wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364
- attribute \src "libresoc.v:44119.3-44147.6"
+ attribute \src "libresoc.v:44055.3-44083.6"
wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378
- attribute \src "libresoc.v:44615.3-44643.6"
+ attribute \src "libresoc.v:44551.3-44579.6"
wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403
- attribute \src "libresoc.v:44937.3-44965.6"
+ attribute \src "libresoc.v:44873.3-44901.6"
wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422
- attribute \src "libresoc.v:45404.3-45432.6"
+ attribute \src "libresoc.v:45340.3-45368.6"
wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446
- attribute \src "libresoc.v:45842.3-45870.6"
+ attribute \src "libresoc.v:45778.3-45806.6"
wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469
- attribute \src "libresoc.v:47448.3-47476.6"
+ attribute \src "libresoc.v:47393.3-47421.6"
wire width 4 $0\fus_cu_rdmaskn_i[3:0]
- attribute \src "libresoc.v:47325.3-47353.6"
+ attribute \src "libresoc.v:47270.3-47298.6"
wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "libresoc.v:46746.3-46774.6"
+ attribute \src "libresoc.v:46720.3-46748.6"
wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47146.3-47174.6"
+ attribute \src "libresoc.v:47100.3-47128.6"
wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "libresoc.v:47363.3-47391.6"
+ attribute \src "libresoc.v:47308.3-47336.6"
wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "libresoc.v:46698.3-46726.6"
+ attribute \src "libresoc.v:46653.3-46681.6"
wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "libresoc.v:46985.3-47013.6"
+ attribute \src "libresoc.v:46939.3-46967.6"
wire $0\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "libresoc.v:47070.3-47098.6"
+ attribute \src "libresoc.v:47015.3-47043.6"
wire $0\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "libresoc.v:47240.3-47268.6"
+ attribute \src "libresoc.v:47185.3-47213.6"
wire $0\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "libresoc.v:47278.3-47306.6"
+ attribute \src "libresoc.v:47223.3-47251.6"
wire $0\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $0\fus_oper_i_alu_alu0__oe__oe[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $0\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "libresoc.v:47193.3-47221.6"
+ attribute \src "libresoc.v:47147.3-47175.6"
wire $0\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $0\fus_oper_i_alu_alu0__rc__ok[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $0\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "libresoc.v:47108.3-47136.6"
+ attribute \src "libresoc.v:47053.3-47081.6"
wire $0\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "libresoc.v:47032.3-47060.6"
+ attribute \src "libresoc.v:46977.3-47005.6"
wire $0\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "libresoc.v:47703.3-47731.6"
+ attribute \src "libresoc.v:47648.3-47676.6"
wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "libresoc.v:47788.3-47816.6"
+ attribute \src "libresoc.v:47733.3-47761.6"
wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47826.3-47854.6"
+ attribute \src "libresoc.v:47771.3-47799.6"
wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "libresoc.v:47741.3-47769.6"
+ attribute \src "libresoc.v:47686.3-47714.6"
wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "libresoc.v:47923.3-47951.6"
+ attribute \src "libresoc.v:47859.3-47887.6"
wire $0\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "libresoc.v:47894.3-47922.6"
+ attribute \src "libresoc.v:47830.3-47858.6"
wire $0\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "libresoc.v:47533.3-47561.6"
+ attribute \src "libresoc.v:47478.3-47506.6"
wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "libresoc.v:47580.3-47608.6"
+ attribute \src "libresoc.v:47525.3-47553.6"
wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "libresoc.v:47486.3-47514.6"
+ attribute \src "libresoc.v:47440.3-47468.6"
wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "libresoc.v:44528.3-44556.6"
+ attribute \src "libresoc.v:44464.3-44492.6"
wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "libresoc.v:44177.3-44205.6"
+ attribute \src "libresoc.v:44113.3-44141.6"
wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44354.3-44382.6"
+ attribute \src "libresoc.v:44290.3-44318.6"
wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "libresoc.v:44557.3-44585.6"
+ attribute \src "libresoc.v:44493.3-44521.6"
wire width 32 $0\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "libresoc.v:44148.3-44176.6"
+ attribute \src "libresoc.v:44084.3-44112.6"
wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "libresoc.v:44296.3-44324.6"
+ attribute \src "libresoc.v:44232.3-44260.6"
wire $0\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "libresoc.v:44383.3-44411.6"
+ attribute \src "libresoc.v:44319.3-44347.6"
wire $0\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "libresoc.v:44470.3-44498.6"
+ attribute \src "libresoc.v:44406.3-44434.6"
wire $0\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "libresoc.v:44499.3-44527.6"
+ attribute \src "libresoc.v:44435.3-44463.6"
wire $0\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $0\fus_oper_i_alu_div0__oe__oe[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $0\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "libresoc.v:44441.3-44469.6"
+ attribute \src "libresoc.v:44377.3-44405.6"
wire $0\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $0\fus_oper_i_alu_div0__rc__ok[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $0\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "libresoc.v:44412.3-44440.6"
+ attribute \src "libresoc.v:44348.3-44376.6"
wire $0\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "libresoc.v:44325.3-44353.6"
+ attribute \src "libresoc.v:44261.3-44289.6"
wire $0\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "libresoc.v:43858.3-43886.6"
+ attribute \src "libresoc.v:43794.3-43822.6"
wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "libresoc.v:48358.3-48386.6"
+ attribute \src "libresoc.v:48294.3-48322.6"
wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "libresoc.v:48535.3-48563.6"
+ attribute \src "libresoc.v:48471.3-48499.6"
wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "libresoc.v:43887.3-43915.6"
+ attribute \src "libresoc.v:43823.3-43851.6"
wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "libresoc.v:48329.3-48357.6"
+ attribute \src "libresoc.v:48265.3-48293.6"
wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "libresoc.v:48477.3-48505.6"
+ attribute \src "libresoc.v:48413.3-48441.6"
wire $0\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "libresoc.v:48564.3-48592.6"
+ attribute \src "libresoc.v:48500.3-48528.6"
wire $0\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "libresoc.v:43800.3-43828.6"
+ attribute \src "libresoc.v:43736.3-43764.6"
wire $0\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "libresoc.v:43829.3-43857.6"
+ attribute \src "libresoc.v:43765.3-43793.6"
wire $0\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $0\fus_oper_i_alu_logical0__oe__oe[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $0\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "libresoc.v:43771.3-43799.6"
+ attribute \src "libresoc.v:43707.3-43735.6"
wire $0\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $0\fus_oper_i_alu_logical0__rc__ok[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $0\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "libresoc.v:48593.3-48621.6"
+ attribute \src "libresoc.v:48529.3-48557.6"
wire $0\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "libresoc.v:48506.3-48534.6"
+ attribute \src "libresoc.v:48442.3-48470.6"
wire $0\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "libresoc.v:44673.3-44701.6"
+ attribute \src "libresoc.v:44609.3-44637.6"
wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44879.3-44907.6"
+ attribute \src "libresoc.v:44815.3-44843.6"
wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "libresoc.v:44644.3-44672.6"
+ attribute \src "libresoc.v:44580.3-44608.6"
wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "libresoc.v:44821.3-44849.6"
+ attribute \src "libresoc.v:44757.3-44785.6"
wire $0\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "libresoc.v:44850.3-44878.6"
+ attribute \src "libresoc.v:44786.3-44814.6"
wire $0\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $0\fus_oper_i_alu_mul0__oe__oe[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $0\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $0\fus_oper_i_alu_mul0__rc__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $0\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "libresoc.v:44792.3-44820.6"
+ attribute \src "libresoc.v:44728.3-44756.6"
wire $0\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "libresoc.v:44995.3-45023.6"
+ attribute \src "libresoc.v:44931.3-44959.6"
wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45172.3-45200.6"
+ attribute \src "libresoc.v:45108.3-45136.6"
wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "libresoc.v:45230.3-45258.6"
+ attribute \src "libresoc.v:45166.3-45194.6"
wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "libresoc.v:45346.3-45374.6"
+ attribute \src "libresoc.v:45282.3-45310.6"
wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "libresoc.v:44966.3-44994.6"
+ attribute \src "libresoc.v:44902.3-44930.6"
wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "libresoc.v:45143.3-45171.6"
+ attribute \src "libresoc.v:45079.3-45107.6"
wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "libresoc.v:45288.3-45316.6"
+ attribute \src "libresoc.v:45224.3-45252.6"
wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "libresoc.v:45317.3-45345.6"
+ attribute \src "libresoc.v:45253.3-45281.6"
wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "libresoc.v:45201.3-45229.6"
+ attribute \src "libresoc.v:45137.3-45165.6"
wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "libresoc.v:45259.3-45287.6"
+ attribute \src "libresoc.v:45195.3-45223.6"
wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "libresoc.v:45114.3-45142.6"
+ attribute \src "libresoc.v:45050.3-45078.6"
wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "libresoc.v:44003.3-44031.6"
+ attribute \src "libresoc.v:43939.3-43967.6"
wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "libresoc.v:44032.3-44060.6"
+ attribute \src "libresoc.v:43968.3-43996.6"
wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "libresoc.v:43974.3-44002.6"
+ attribute \src "libresoc.v:43910.3-43938.6"
wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "libresoc.v:44061.3-44089.6"
+ attribute \src "libresoc.v:43997.3-44025.6"
wire $0\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "libresoc.v:48126.3-48154.6"
+ attribute \src "libresoc.v:48062.3-48090.6"
wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "libresoc.v:48039.3-48067.6"
+ attribute \src "libresoc.v:47975.3-48003.6"
wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "libresoc.v:48068.3-48096.6"
+ attribute \src "libresoc.v:48004.3-48032.6"
wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "libresoc.v:48010.3-48038.6"
+ attribute \src "libresoc.v:47946.3-47974.6"
wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "libresoc.v:48155.3-48183.6"
+ attribute \src "libresoc.v:48091.3-48119.6"
wire $0\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "libresoc.v:48242.3-48270.6"
+ attribute \src "libresoc.v:48178.3-48206.6"
wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "libresoc.v:48097.3-48125.6"
+ attribute \src "libresoc.v:48033.3-48061.6"
wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "libresoc.v:48213.3-48241.6"
+ attribute \src "libresoc.v:48149.3-48177.6"
wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "libresoc.v:48184.3-48212.6"
+ attribute \src "libresoc.v:48120.3-48148.6"
wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "libresoc.v:45697.3-45725.6"
+ attribute \src "libresoc.v:45633.3-45661.6"
wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "libresoc.v:45668.3-45696.6"
+ attribute \src "libresoc.v:45604.3-45632.6"
wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "libresoc.v:45462.3-45490.6"
+ attribute \src "libresoc.v:45398.3-45426.6"
wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45784.3-45812.6"
+ attribute \src "libresoc.v:45720.3-45748.6"
wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "libresoc.v:45433.3-45461.6"
+ attribute \src "libresoc.v:45369.3-45397.6"
wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "libresoc.v:45610.3-45638.6"
+ attribute \src "libresoc.v:45546.3-45574.6"
wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "libresoc.v:45639.3-45667.6"
+ attribute \src "libresoc.v:45575.3-45603.6"
wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "libresoc.v:45755.3-45783.6"
+ attribute \src "libresoc.v:45691.3-45719.6"
wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "libresoc.v:45726.3-45754.6"
+ attribute \src "libresoc.v:45662.3-45690.6"
wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "libresoc.v:45521.3-45549.6"
+ attribute \src "libresoc.v:45457.3-45485.6"
wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "libresoc.v:45899.3-45908.6"
- wire width 64 $0\fus_src1_i$42[63:0]$2481
- attribute \src "libresoc.v:45918.3-45927.6"
- wire width 64 $0\fus_src1_i$45[63:0]$2487
- attribute \src "libresoc.v:45937.3-45946.6"
- wire width 64 $0\fus_src1_i$48[63:0]$2493
- attribute \src "libresoc.v:45956.3-45965.6"
- wire width 64 $0\fus_src1_i$51[63:0]$2499
- attribute \src "libresoc.v:45975.3-45984.6"
- wire width 64 $0\fus_src1_i$54[63:0]$2505
- attribute \src "libresoc.v:45994.3-46003.6"
- wire width 64 $0\fus_src1_i$57[63:0]$2511
- attribute \src "libresoc.v:46013.3-46022.6"
- wire width 64 $0\fus_src1_i$60[63:0]$2517
- attribute \src "libresoc.v:46032.3-46041.6"
- wire width 64 $0\fus_src1_i$63[63:0]$2523
- attribute \src "libresoc.v:46669.3-46678.6"
- wire width 64 $0\fus_src1_i$86[63:0]$2681
- attribute \src "libresoc.v:45880.3-45889.6"
+ attribute \src "libresoc.v:46025.3-46034.6"
+ wire width 64 $0\fus_src1_i$62[63:0]$2537
+ attribute \src "libresoc.v:46044.3-46053.6"
+ wire width 64 $0\fus_src1_i$63[63:0]$2543
+ attribute \src "libresoc.v:46063.3-46072.6"
+ wire width 64 $0\fus_src1_i$64[63:0]$2549
+ attribute \src "libresoc.v:46082.3-46091.6"
+ wire width 64 $0\fus_src1_i$67[63:0]$2555
+ attribute \src "libresoc.v:46101.3-46110.6"
+ wire width 64 $0\fus_src1_i$68[63:0]$2561
+ attribute \src "libresoc.v:46120.3-46129.6"
+ wire width 64 $0\fus_src1_i$69[63:0]$2567
+ attribute \src "libresoc.v:46139.3-46148.6"
+ wire width 64 $0\fus_src1_i$70[63:0]$2573
+ attribute \src "libresoc.v:46158.3-46167.6"
+ wire width 64 $0\fus_src1_i$71[63:0]$2579
+ attribute \src "libresoc.v:46584.3-46593.6"
+ wire width 64 $0\fus_src1_i$86[63:0]$2676
+ attribute \src "libresoc.v:46006.3-46015.6"
wire width 64 $0\fus_src1_i[63:0]
- attribute \src "libresoc.v:46070.3-46079.6"
- wire width 64 $0\fus_src2_i$64[63:0]$2533
- attribute \src "libresoc.v:46089.3-46098.6"
- wire width 64 $0\fus_src2_i$65[63:0]$2539
- attribute \src "libresoc.v:46108.3-46117.6"
- wire width 64 $0\fus_src2_i$66[63:0]$2545
- attribute \src "libresoc.v:46127.3-46136.6"
- wire width 64 $0\fus_src2_i$67[63:0]$2551
- attribute \src "libresoc.v:46146.3-46155.6"
- wire width 64 $0\fus_src2_i$68[63:0]$2557
- attribute \src "libresoc.v:46165.3-46174.6"
- wire width 64 $0\fus_src2_i$69[63:0]$2563
- attribute \src "libresoc.v:46184.3-46193.6"
- wire width 64 $0\fus_src2_i$70[63:0]$2569
- attribute \src "libresoc.v:46784.3-46793.6"
- wire width 64 $0\fus_src2_i$89[63:0]$2701
- attribute \src "libresoc.v:46852.3-46861.6"
- wire width 64 $0\fus_src2_i$91[63:0]$2714
- attribute \src "libresoc.v:46051.3-46060.6"
+ attribute \src "libresoc.v:45835.3-45844.6"
+ wire width 64 $0\fus_src2_i$42[63:0]$2481
+ attribute \src "libresoc.v:45854.3-45863.6"
+ wire width 64 $0\fus_src2_i$45[63:0]$2487
+ attribute \src "libresoc.v:45873.3-45882.6"
+ wire width 64 $0\fus_src2_i$48[63:0]$2493
+ attribute \src "libresoc.v:45892.3-45901.6"
+ wire width 64 $0\fus_src2_i$51[63:0]$2499
+ attribute \src "libresoc.v:45911.3-45920.6"
+ wire width 64 $0\fus_src2_i$54[63:0]$2505
+ attribute \src "libresoc.v:45930.3-45939.6"
+ wire width 64 $0\fus_src2_i$57[63:0]$2511
+ attribute \src "libresoc.v:45949.3-45958.6"
+ wire width 64 $0\fus_src2_i$60[63:0]$2517
+ attribute \src "libresoc.v:46691.3-46700.6"
+ wire width 64 $0\fus_src2_i$89[63:0]$2700
+ attribute \src "libresoc.v:46758.3-46767.6"
+ wire width 64 $0\fus_src2_i$91[63:0]$2713
+ attribute \src "libresoc.v:45816.3-45825.6"
wire width 64 $0\fus_src2_i[63:0]
- attribute \src "libresoc.v:46222.3-46231.6"
- wire width 64 $0\fus_src3_i$71[63:0]$2579
- attribute \src "libresoc.v:46241.3-46250.6"
+ attribute \src "libresoc.v:45987.3-45996.6"
+ wire width 64 $0\fus_src3_i$61[63:0]$2527
+ attribute \src "libresoc.v:46177.3-46186.6"
wire $0\fus_src3_i$72[0:0]$2585
- attribute \src "libresoc.v:46260.3-46269.6"
+ attribute \src "libresoc.v:46196.3-46205.6"
wire $0\fus_src3_i$73[0:0]$2591
- attribute \src "libresoc.v:46298.3-46307.6"
+ attribute \src "libresoc.v:46234.3-46243.6"
wire $0\fus_src3_i$74[0:0]$2601
- attribute \src "libresoc.v:46317.3-46326.6"
+ attribute \src "libresoc.v:46253.3-46262.6"
wire $0\fus_src3_i$75[0:0]$2607
- attribute \src "libresoc.v:46431.3-46440.6"
+ attribute \src "libresoc.v:46367.3-46376.6"
wire width 32 $0\fus_src3_i$79[31:0]$2639
- attribute \src "libresoc.v:46469.3-46478.6"
+ attribute \src "libresoc.v:46405.3-46414.6"
wire width 4 $0\fus_src3_i$83[3:0]$2651
- attribute \src "libresoc.v:46688.3-46697.6"
+ attribute \src "libresoc.v:46624.3-46633.6"
wire width 64 $0\fus_src3_i$87[63:0]$2687
- attribute \src "libresoc.v:46736.3-46745.6"
- wire width 64 $0\fus_src3_i$88[63:0]$2694
- attribute \src "libresoc.v:46203.3-46212.6"
+ attribute \src "libresoc.v:46643.3-46652.6"
+ wire width 64 $0\fus_src3_i$88[63:0]$2693
+ attribute \src "libresoc.v:45968.3-45977.6"
wire width 64 $0\fus_src3_i[63:0]
- attribute \src "libresoc.v:46336.3-46345.6"
+ attribute \src "libresoc.v:46272.3-46281.6"
wire $0\fus_src4_i$76[0:0]$2613
- attribute \src "libresoc.v:46355.3-46364.6"
+ attribute \src "libresoc.v:46291.3-46300.6"
wire width 2 $0\fus_src4_i$77[1:0]$2619
- attribute \src "libresoc.v:46450.3-46459.6"
+ attribute \src "libresoc.v:46386.3-46395.6"
wire width 4 $0\fus_src4_i$80[3:0]$2645
- attribute \src "libresoc.v:46803.3-46812.6"
- wire width 64 $0\fus_src4_i$90[63:0]$2707
- attribute \src "libresoc.v:46279.3-46288.6"
+ attribute \src "libresoc.v:46710.3-46719.6"
+ wire width 64 $0\fus_src4_i$90[63:0]$2706
+ attribute \src "libresoc.v:46215.3-46224.6"
wire $0\fus_src4_i[0:0]
- attribute \src "libresoc.v:46412.3-46421.6"
+ attribute \src "libresoc.v:46348.3-46357.6"
wire width 2 $0\fus_src5_i$78[1:0]$2633
- attribute \src "libresoc.v:46519.3-46528.6"
+ attribute \src "libresoc.v:46455.3-46464.6"
wire width 4 $0\fus_src5_i$84[3:0]$2663
- attribute \src "libresoc.v:46393.3-46402.6"
+ attribute \src "libresoc.v:46329.3-46338.6"
wire width 2 $0\fus_src5_i[1:0]
- attribute \src "libresoc.v:46629.3-46638.6"
- wire width 4 $0\fus_src6_i$85[3:0]$2670
- attribute \src "libresoc.v:46374.3-46383.6"
+ attribute \src "libresoc.v:46474.3-46483.6"
+ wire width 4 $0\fus_src6_i$85[3:0]$2669
+ attribute \src "libresoc.v:46310.3-46319.6"
wire width 2 $0\fus_src6_i[1:0]
attribute \src "libresoc.v:36262.7-36262.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:46910.3-46918.6"
- wire $0\wr_pick_dly$1010$next[0:0]$2724
- attribute \src "libresoc.v:42944.3-42945.51"
- wire $0\wr_pick_dly$1010[0:0]$2307
+ attribute \src "libresoc.v:46816.3-46824.6"
+ wire $0\wr_pick_dly$1008$next[0:0]$2723
+ attribute \src "libresoc.v:42904.3-42905.51"
+ wire $0\wr_pick_dly$1008[0:0]$2307
+ attribute \src "libresoc.v:41734.7-41734.32"
+ wire $0\wr_pick_dly$1008[0:0]$2945
+ attribute \src "libresoc.v:46855.3-46863.6"
+ wire $0\wr_pick_dly$1029$next[0:0]$2727
+ attribute \src "libresoc.v:42902.3-42903.51"
+ wire $0\wr_pick_dly$1029[0:0]$2305
+ attribute \src "libresoc.v:41738.7-41738.32"
+ wire $0\wr_pick_dly$1029[0:0]$2947
+ attribute \src "libresoc.v:46864.3-46872.6"
+ wire $0\wr_pick_dly$1047$next[0:0]$2730
+ attribute \src "libresoc.v:42900.3-42901.51"
+ wire $0\wr_pick_dly$1047[0:0]$2303
+ attribute \src "libresoc.v:41742.7-41742.32"
+ wire $0\wr_pick_dly$1047[0:0]$2949
+ attribute \src "libresoc.v:46873.3-46881.6"
+ wire $0\wr_pick_dly$1069$next[0:0]$2733
+ attribute \src "libresoc.v:42898.3-42899.51"
+ wire $0\wr_pick_dly$1069[0:0]$2301
+ attribute \src "libresoc.v:41746.7-41746.32"
+ wire $0\wr_pick_dly$1069[0:0]$2951
+ attribute \src "libresoc.v:46912.3-46920.6"
+ wire $0\wr_pick_dly$1089$next[0:0]$2737
+ attribute \src "libresoc.v:42896.3-42897.51"
+ wire $0\wr_pick_dly$1089[0:0]$2299
+ attribute \src "libresoc.v:41750.7-41750.32"
+ wire $0\wr_pick_dly$1089[0:0]$2953
+ attribute \src "libresoc.v:46921.3-46929.6"
+ wire $0\wr_pick_dly$1109$next[0:0]$2740
+ attribute \src "libresoc.v:42894.3-42895.51"
+ wire $0\wr_pick_dly$1109[0:0]$2297
+ attribute \src "libresoc.v:41754.7-41754.32"
+ wire $0\wr_pick_dly$1109[0:0]$2955
+ attribute \src "libresoc.v:46930.3-46938.6"
+ wire $0\wr_pick_dly$1128$next[0:0]$2743
+ attribute \src "libresoc.v:42892.3-42893.51"
+ wire $0\wr_pick_dly$1128[0:0]$2295
+ attribute \src "libresoc.v:41758.7-41758.32"
+ wire $0\wr_pick_dly$1128[0:0]$2957
+ attribute \src "libresoc.v:46968.3-46976.6"
+ wire $0\wr_pick_dly$1146$next[0:0]$2747
+ attribute \src "libresoc.v:42890.3-42891.51"
+ wire $0\wr_pick_dly$1146[0:0]$2293
+ attribute \src "libresoc.v:41762.7-41762.32"
+ wire $0\wr_pick_dly$1146[0:0]$2959
+ attribute \src "libresoc.v:47006.3-47014.6"
+ wire $0\wr_pick_dly$1220$next[0:0]$2751
+ attribute \src "libresoc.v:42888.3-42889.51"
+ wire $0\wr_pick_dly$1220[0:0]$2291
+ attribute \src "libresoc.v:41766.7-41766.32"
+ wire $0\wr_pick_dly$1220[0:0]$2961
+ attribute \src "libresoc.v:47044.3-47052.6"
+ wire $0\wr_pick_dly$1248$next[0:0]$2755
+ attribute \src "libresoc.v:42886.3-42887.51"
+ wire $0\wr_pick_dly$1248[0:0]$2289
+ attribute \src "libresoc.v:41770.7-41770.32"
+ wire $0\wr_pick_dly$1248[0:0]$2963
+ attribute \src "libresoc.v:47082.3-47090.6"
+ wire $0\wr_pick_dly$1268$next[0:0]$2759
+ attribute \src "libresoc.v:42884.3-42885.51"
+ wire $0\wr_pick_dly$1268[0:0]$2287
attribute \src "libresoc.v:41774.7-41774.32"
- wire $0\wr_pick_dly$1010[0:0]$2945
- attribute \src "libresoc.v:46919.3-46927.6"
- wire $0\wr_pick_dly$1031$next[0:0]$2727
- attribute \src "libresoc.v:42942.3-42943.51"
- wire $0\wr_pick_dly$1031[0:0]$2305
+ wire $0\wr_pick_dly$1268[0:0]$2965
+ attribute \src "libresoc.v:47091.3-47099.6"
+ wire $0\wr_pick_dly$1288$next[0:0]$2762
+ attribute \src "libresoc.v:42882.3-42883.51"
+ wire $0\wr_pick_dly$1288[0:0]$2285
attribute \src "libresoc.v:41778.7-41778.32"
- wire $0\wr_pick_dly$1031[0:0]$2947
- attribute \src "libresoc.v:46958.3-46966.6"
- wire $0\wr_pick_dly$1049$next[0:0]$2731
- attribute \src "libresoc.v:42940.3-42941.51"
- wire $0\wr_pick_dly$1049[0:0]$2303
+ wire $0\wr_pick_dly$1288[0:0]$2967
+ attribute \src "libresoc.v:47129.3-47137.6"
+ wire $0\wr_pick_dly$1308$next[0:0]$2766
+ attribute \src "libresoc.v:42880.3-42881.51"
+ wire $0\wr_pick_dly$1308[0:0]$2283
attribute \src "libresoc.v:41782.7-41782.32"
- wire $0\wr_pick_dly$1049[0:0]$2949
- attribute \src "libresoc.v:46967.3-46975.6"
- wire $0\wr_pick_dly$1071$next[0:0]$2734
- attribute \src "libresoc.v:42938.3-42939.51"
- wire $0\wr_pick_dly$1071[0:0]$2301
+ wire $0\wr_pick_dly$1308[0:0]$2969
+ attribute \src "libresoc.v:47138.3-47146.6"
+ wire $0\wr_pick_dly$1328$next[0:0]$2769
+ attribute \src "libresoc.v:42878.3-42879.51"
+ wire $0\wr_pick_dly$1328[0:0]$2281
attribute \src "libresoc.v:41786.7-41786.32"
- wire $0\wr_pick_dly$1071[0:0]$2951
- attribute \src "libresoc.v:46976.3-46984.6"
- wire $0\wr_pick_dly$1091$next[0:0]$2737
- attribute \src "libresoc.v:42936.3-42937.51"
- wire $0\wr_pick_dly$1091[0:0]$2299
+ wire $0\wr_pick_dly$1328[0:0]$2971
+ attribute \src "libresoc.v:47176.3-47184.6"
+ wire $0\wr_pick_dly$1348$next[0:0]$2773
+ attribute \src "libresoc.v:42876.3-42877.51"
+ wire $0\wr_pick_dly$1348[0:0]$2279
attribute \src "libresoc.v:41790.7-41790.32"
- wire $0\wr_pick_dly$1091[0:0]$2953
- attribute \src "libresoc.v:47014.3-47022.6"
- wire $0\wr_pick_dly$1111$next[0:0]$2741
- attribute \src "libresoc.v:42934.3-42935.51"
- wire $0\wr_pick_dly$1111[0:0]$2297
+ wire $0\wr_pick_dly$1348[0:0]$2973
+ attribute \src "libresoc.v:47214.3-47222.6"
+ wire $0\wr_pick_dly$1395$next[0:0]$2777
+ attribute \src "libresoc.v:42874.3-42875.51"
+ wire $0\wr_pick_dly$1395[0:0]$2277
attribute \src "libresoc.v:41794.7-41794.32"
- wire $0\wr_pick_dly$1111[0:0]$2955
- attribute \src "libresoc.v:47023.3-47031.6"
- wire $0\wr_pick_dly$1130$next[0:0]$2744
- attribute \src "libresoc.v:42932.3-42933.51"
- wire $0\wr_pick_dly$1130[0:0]$2295
+ wire $0\wr_pick_dly$1395[0:0]$2975
+ attribute \src "libresoc.v:47252.3-47260.6"
+ wire $0\wr_pick_dly$1411$next[0:0]$2781
+ attribute \src "libresoc.v:42872.3-42873.51"
+ wire $0\wr_pick_dly$1411[0:0]$2275
attribute \src "libresoc.v:41798.7-41798.32"
- wire $0\wr_pick_dly$1130[0:0]$2957
- attribute \src "libresoc.v:47061.3-47069.6"
- wire $0\wr_pick_dly$1148$next[0:0]$2748
- attribute \src "libresoc.v:42930.3-42931.51"
- wire $0\wr_pick_dly$1148[0:0]$2293
+ wire $0\wr_pick_dly$1411[0:0]$2977
+ attribute \src "libresoc.v:47261.3-47269.6"
+ wire $0\wr_pick_dly$1427$next[0:0]$2784
+ attribute \src "libresoc.v:42870.3-42871.51"
+ wire $0\wr_pick_dly$1427[0:0]$2273
attribute \src "libresoc.v:41802.7-41802.32"
- wire $0\wr_pick_dly$1148[0:0]$2959
- attribute \src "libresoc.v:47099.3-47107.6"
- wire $0\wr_pick_dly$1222$next[0:0]$2752
- attribute \src "libresoc.v:42928.3-42929.51"
- wire $0\wr_pick_dly$1222[0:0]$2291
+ wire $0\wr_pick_dly$1427[0:0]$2979
+ attribute \src "libresoc.v:47299.3-47307.6"
+ wire $0\wr_pick_dly$1461$next[0:0]$2788
+ attribute \src "libresoc.v:42868.3-42869.51"
+ wire $0\wr_pick_dly$1461[0:0]$2271
attribute \src "libresoc.v:41806.7-41806.32"
- wire $0\wr_pick_dly$1222[0:0]$2961
- attribute \src "libresoc.v:47137.3-47145.6"
- wire $0\wr_pick_dly$1250$next[0:0]$2756
- attribute \src "libresoc.v:42926.3-42927.51"
- wire $0\wr_pick_dly$1250[0:0]$2289
+ wire $0\wr_pick_dly$1461[0:0]$2981
+ attribute \src "libresoc.v:47337.3-47345.6"
+ wire $0\wr_pick_dly$1477$next[0:0]$2792
+ attribute \src "libresoc.v:42866.3-42867.51"
+ wire $0\wr_pick_dly$1477[0:0]$2269
attribute \src "libresoc.v:41810.7-41810.32"
- wire $0\wr_pick_dly$1250[0:0]$2963
- attribute \src "libresoc.v:47175.3-47183.6"
- wire $0\wr_pick_dly$1270$next[0:0]$2760
- attribute \src "libresoc.v:42924.3-42925.51"
- wire $0\wr_pick_dly$1270[0:0]$2287
+ wire $0\wr_pick_dly$1477[0:0]$2983
+ attribute \src "libresoc.v:47346.3-47354.6"
+ wire $0\wr_pick_dly$1493$next[0:0]$2795
+ attribute \src "libresoc.v:42864.3-42865.51"
+ wire $0\wr_pick_dly$1493[0:0]$2267
attribute \src "libresoc.v:41814.7-41814.32"
- wire $0\wr_pick_dly$1270[0:0]$2965
- attribute \src "libresoc.v:47184.3-47192.6"
- wire $0\wr_pick_dly$1290$next[0:0]$2763
- attribute \src "libresoc.v:42922.3-42923.51"
- wire $0\wr_pick_dly$1290[0:0]$2285
+ wire $0\wr_pick_dly$1493[0:0]$2985
+ attribute \src "libresoc.v:47384.3-47392.6"
+ wire $0\wr_pick_dly$1509$next[0:0]$2799
+ attribute \src "libresoc.v:42862.3-42863.51"
+ wire $0\wr_pick_dly$1509[0:0]$2265
attribute \src "libresoc.v:41818.7-41818.32"
- wire $0\wr_pick_dly$1290[0:0]$2967
- attribute \src "libresoc.v:47222.3-47230.6"
- wire $0\wr_pick_dly$1310$next[0:0]$2767
- attribute \src "libresoc.v:42920.3-42921.51"
- wire $0\wr_pick_dly$1310[0:0]$2283
+ wire $0\wr_pick_dly$1509[0:0]$2987
+ attribute \src "libresoc.v:47422.3-47430.6"
+ wire $0\wr_pick_dly$1545$next[0:0]$2803
+ attribute \src "libresoc.v:42860.3-42861.51"
+ wire $0\wr_pick_dly$1545[0:0]$2263
attribute \src "libresoc.v:41822.7-41822.32"
- wire $0\wr_pick_dly$1310[0:0]$2969
- attribute \src "libresoc.v:47231.3-47239.6"
- wire $0\wr_pick_dly$1330$next[0:0]$2770
- attribute \src "libresoc.v:42918.3-42919.51"
- wire $0\wr_pick_dly$1330[0:0]$2281
+ wire $0\wr_pick_dly$1545[0:0]$2989
+ attribute \src "libresoc.v:47431.3-47439.6"
+ wire $0\wr_pick_dly$1561$next[0:0]$2806
+ attribute \src "libresoc.v:42858.3-42859.51"
+ wire $0\wr_pick_dly$1561[0:0]$2261
attribute \src "libresoc.v:41826.7-41826.32"
- wire $0\wr_pick_dly$1330[0:0]$2971
- attribute \src "libresoc.v:47269.3-47277.6"
- wire $0\wr_pick_dly$1350$next[0:0]$2774
- attribute \src "libresoc.v:42916.3-42917.51"
- wire $0\wr_pick_dly$1350[0:0]$2279
+ wire $0\wr_pick_dly$1561[0:0]$2991
+ attribute \src "libresoc.v:47469.3-47477.6"
+ wire $0\wr_pick_dly$1577$next[0:0]$2810
+ attribute \src "libresoc.v:42856.3-42857.51"
+ wire $0\wr_pick_dly$1577[0:0]$2259
attribute \src "libresoc.v:41830.7-41830.32"
- wire $0\wr_pick_dly$1350[0:0]$2973
- attribute \src "libresoc.v:47307.3-47315.6"
- wire $0\wr_pick_dly$1397$next[0:0]$2778
- attribute \src "libresoc.v:42914.3-42915.51"
- wire $0\wr_pick_dly$1397[0:0]$2277
+ wire $0\wr_pick_dly$1577[0:0]$2993
+ attribute \src "libresoc.v:47507.3-47515.6"
+ wire $0\wr_pick_dly$1593$next[0:0]$2814
+ attribute \src "libresoc.v:42854.3-42855.51"
+ wire $0\wr_pick_dly$1593[0:0]$2257
attribute \src "libresoc.v:41834.7-41834.32"
- wire $0\wr_pick_dly$1397[0:0]$2975
- attribute \src "libresoc.v:47316.3-47324.6"
- wire $0\wr_pick_dly$1413$next[0:0]$2781
- attribute \src "libresoc.v:42912.3-42913.51"
- wire $0\wr_pick_dly$1413[0:0]$2275
+ wire $0\wr_pick_dly$1593[0:0]$2995
+ attribute \src "libresoc.v:47516.3-47524.6"
+ wire $0\wr_pick_dly$1635$next[0:0]$2817
+ attribute \src "libresoc.v:42852.3-42853.51"
+ wire $0\wr_pick_dly$1635[0:0]$2255
attribute \src "libresoc.v:41838.7-41838.32"
- wire $0\wr_pick_dly$1413[0:0]$2977
- attribute \src "libresoc.v:47354.3-47362.6"
- wire $0\wr_pick_dly$1429$next[0:0]$2785
- attribute \src "libresoc.v:42910.3-42911.51"
- wire $0\wr_pick_dly$1429[0:0]$2273
+ wire $0\wr_pick_dly$1635[0:0]$2997
+ attribute \src "libresoc.v:47554.3-47562.6"
+ wire $0\wr_pick_dly$1654$next[0:0]$2821
+ attribute \src "libresoc.v:42850.3-42851.51"
+ wire $0\wr_pick_dly$1654[0:0]$2253
attribute \src "libresoc.v:41842.7-41842.32"
- wire $0\wr_pick_dly$1429[0:0]$2979
- attribute \src "libresoc.v:47392.3-47400.6"
- wire $0\wr_pick_dly$1463$next[0:0]$2789
- attribute \src "libresoc.v:42908.3-42909.51"
- wire $0\wr_pick_dly$1463[0:0]$2271
+ wire $0\wr_pick_dly$1654[0:0]$2999
+ attribute \src "libresoc.v:47592.3-47600.6"
+ wire $0\wr_pick_dly$1670$next[0:0]$2829
+ attribute \src "libresoc.v:42848.3-42849.51"
+ wire $0\wr_pick_dly$1670[0:0]$2251
attribute \src "libresoc.v:41846.7-41846.32"
- wire $0\wr_pick_dly$1463[0:0]$2981
- attribute \src "libresoc.v:47430.3-47438.6"
- wire $0\wr_pick_dly$1479$next[0:0]$2793
- attribute \src "libresoc.v:42906.3-42907.51"
- wire $0\wr_pick_dly$1479[0:0]$2269
+ wire $0\wr_pick_dly$1670[0:0]$3001
+ attribute \src "libresoc.v:47601.3-47609.6"
+ wire $0\wr_pick_dly$1686$next[0:0]$2832
+ attribute \src "libresoc.v:42846.3-42847.51"
+ wire $0\wr_pick_dly$1686[0:0]$2249
attribute \src "libresoc.v:41850.7-41850.32"
- wire $0\wr_pick_dly$1479[0:0]$2983
- attribute \src "libresoc.v:47439.3-47447.6"
- wire $0\wr_pick_dly$1495$next[0:0]$2796
- attribute \src "libresoc.v:42904.3-42905.51"
- wire $0\wr_pick_dly$1495[0:0]$2267
+ wire $0\wr_pick_dly$1686[0:0]$3003
+ attribute \src "libresoc.v:47639.3-47647.6"
+ wire $0\wr_pick_dly$1702$next[0:0]$2840
+ attribute \src "libresoc.v:42844.3-42845.51"
+ wire $0\wr_pick_dly$1702[0:0]$2247
attribute \src "libresoc.v:41854.7-41854.32"
- wire $0\wr_pick_dly$1495[0:0]$2985
- attribute \src "libresoc.v:47477.3-47485.6"
- wire $0\wr_pick_dly$1511$next[0:0]$2800
- attribute \src "libresoc.v:42902.3-42903.51"
- wire $0\wr_pick_dly$1511[0:0]$2265
+ wire $0\wr_pick_dly$1702[0:0]$3005
+ attribute \src "libresoc.v:47677.3-47685.6"
+ wire $0\wr_pick_dly$1746$next[0:0]$2844
+ attribute \src "libresoc.v:42842.3-42843.51"
+ wire $0\wr_pick_dly$1746[0:0]$2245
attribute \src "libresoc.v:41858.7-41858.32"
- wire $0\wr_pick_dly$1511[0:0]$2987
- attribute \src "libresoc.v:47515.3-47523.6"
- wire $0\wr_pick_dly$1547$next[0:0]$2804
- attribute \src "libresoc.v:42900.3-42901.51"
- wire $0\wr_pick_dly$1547[0:0]$2263
+ wire $0\wr_pick_dly$1746[0:0]$3007
+ attribute \src "libresoc.v:47715.3-47723.6"
+ wire $0\wr_pick_dly$1762$next[0:0]$2848
+ attribute \src "libresoc.v:42840.3-42841.51"
+ wire $0\wr_pick_dly$1762[0:0]$2243
attribute \src "libresoc.v:41862.7-41862.32"
- wire $0\wr_pick_dly$1547[0:0]$2989
- attribute \src "libresoc.v:47524.3-47532.6"
- wire $0\wr_pick_dly$1563$next[0:0]$2807
- attribute \src "libresoc.v:42898.3-42899.51"
- wire $0\wr_pick_dly$1563[0:0]$2261
+ wire $0\wr_pick_dly$1762[0:0]$3009
+ attribute \src "libresoc.v:47724.3-47732.6"
+ wire $0\wr_pick_dly$1786$next[0:0]$2851
+ attribute \src "libresoc.v:42838.3-42839.51"
+ wire $0\wr_pick_dly$1786[0:0]$2241
attribute \src "libresoc.v:41866.7-41866.32"
- wire $0\wr_pick_dly$1563[0:0]$2991
- attribute \src "libresoc.v:47562.3-47570.6"
- wire $0\wr_pick_dly$1579$next[0:0]$2811
- attribute \src "libresoc.v:42896.3-42897.51"
- wire $0\wr_pick_dly$1579[0:0]$2259
+ wire $0\wr_pick_dly$1786[0:0]$3011
+ attribute \src "libresoc.v:47762.3-47770.6"
+ wire $0\wr_pick_dly$1806$next[0:0]$2855
+ attribute \src "libresoc.v:42836.3-42837.51"
+ wire $0\wr_pick_dly$1806[0:0]$2239
attribute \src "libresoc.v:41870.7-41870.32"
- wire $0\wr_pick_dly$1579[0:0]$2993
- attribute \src "libresoc.v:47571.3-47579.6"
- wire $0\wr_pick_dly$1595$next[0:0]$2814
- attribute \src "libresoc.v:42894.3-42895.51"
- wire $0\wr_pick_dly$1595[0:0]$2257
- attribute \src "libresoc.v:41874.7-41874.32"
- wire $0\wr_pick_dly$1595[0:0]$2995
- attribute \src "libresoc.v:47609.3-47617.6"
- wire $0\wr_pick_dly$1637$next[0:0]$2818
- attribute \src "libresoc.v:42892.3-42893.51"
- wire $0\wr_pick_dly$1637[0:0]$2255
- attribute \src "libresoc.v:41878.7-41878.32"
- wire $0\wr_pick_dly$1637[0:0]$2997
- attribute \src "libresoc.v:47647.3-47655.6"
- wire $0\wr_pick_dly$1656$next[0:0]$2826
- attribute \src "libresoc.v:42890.3-42891.51"
- wire $0\wr_pick_dly$1656[0:0]$2253
- attribute \src "libresoc.v:41882.7-41882.32"
- wire $0\wr_pick_dly$1656[0:0]$2999
- attribute \src "libresoc.v:47685.3-47693.6"
- wire $0\wr_pick_dly$1672$next[0:0]$2834
- attribute \src "libresoc.v:42888.3-42889.51"
- wire $0\wr_pick_dly$1672[0:0]$2251
- attribute \src "libresoc.v:41886.7-41886.32"
- wire $0\wr_pick_dly$1672[0:0]$3001
- attribute \src "libresoc.v:47694.3-47702.6"
- wire $0\wr_pick_dly$1688$next[0:0]$2837
- attribute \src "libresoc.v:42886.3-42887.51"
- wire $0\wr_pick_dly$1688[0:0]$2249
- attribute \src "libresoc.v:41890.7-41890.32"
- wire $0\wr_pick_dly$1688[0:0]$3003
- attribute \src "libresoc.v:47732.3-47740.6"
- wire $0\wr_pick_dly$1704$next[0:0]$2841
- attribute \src "libresoc.v:42884.3-42885.51"
- wire $0\wr_pick_dly$1704[0:0]$2247
- attribute \src "libresoc.v:41894.7-41894.32"
- wire $0\wr_pick_dly$1704[0:0]$3005
- attribute \src "libresoc.v:47770.3-47778.6"
- wire $0\wr_pick_dly$1748$next[0:0]$2845
- attribute \src "libresoc.v:42882.3-42883.51"
- wire $0\wr_pick_dly$1748[0:0]$2245
- attribute \src "libresoc.v:41898.7-41898.32"
- wire $0\wr_pick_dly$1748[0:0]$3007
- attribute \src "libresoc.v:47779.3-47787.6"
- wire $0\wr_pick_dly$1764$next[0:0]$2848
- attribute \src "libresoc.v:42880.3-42881.51"
- wire $0\wr_pick_dly$1764[0:0]$2243
- attribute \src "libresoc.v:41902.7-41902.32"
- wire $0\wr_pick_dly$1764[0:0]$3009
- attribute \src "libresoc.v:47817.3-47825.6"
- wire $0\wr_pick_dly$1788$next[0:0]$2852
- attribute \src "libresoc.v:42878.3-42879.51"
- wire $0\wr_pick_dly$1788[0:0]$2241
- attribute \src "libresoc.v:41906.7-41906.32"
- wire $0\wr_pick_dly$1788[0:0]$3011
- attribute \src "libresoc.v:47855.3-47863.6"
- wire $0\wr_pick_dly$1808$next[0:0]$2856
- attribute \src "libresoc.v:42876.3-42877.51"
- wire $0\wr_pick_dly$1808[0:0]$2239
- attribute \src "libresoc.v:41910.7-41910.32"
- wire $0\wr_pick_dly$1808[0:0]$3013
- attribute \src "libresoc.v:46871.3-46879.6"
- wire $0\wr_pick_dly$991$next[0:0]$2720
- attribute \src "libresoc.v:42946.3-42947.49"
- wire $0\wr_pick_dly$991[0:0]$2309
- attribute \src "libresoc.v:41914.7-41914.31"
- wire $0\wr_pick_dly$991[0:0]$3015
- attribute \src "libresoc.v:46862.3-46870.6"
+ wire $0\wr_pick_dly$1806[0:0]$3013
+ attribute \src "libresoc.v:46807.3-46815.6"
+ wire $0\wr_pick_dly$989$next[0:0]$2720
+ attribute \src "libresoc.v:42906.3-42907.49"
+ wire $0\wr_pick_dly$989[0:0]$2309
+ attribute \src "libresoc.v:41874.7-41874.31"
+ wire $0\wr_pick_dly$989[0:0]$3015
+ attribute \src "libresoc.v:46798.3-46806.6"
wire $0\wr_pick_dly$next[0:0]$2717
- attribute \src "libresoc.v:42948.3-42949.39"
+ attribute \src "libresoc.v:42908.3-42909.39"
wire $0\wr_pick_dly[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $10\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $11\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $12\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $13\corebusy_o[0:0]
- attribute \src "libresoc.v:46639.3-46659.6"
- wire $1\core_terminate_o$next[0:0]$2674
- attribute \src "libresoc.v:38311.7-38311.30"
+ attribute \src "libresoc.v:46594.3-46614.6"
+ wire $1\core_terminate_o$next[0:0]$2680
+ attribute \src "libresoc.v:38307.7-38307.30"
wire $1\core_terminate_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $1\corebusy_o[0:0]
- attribute \src "libresoc.v:46479.3-46509.6"
- wire width 2 $1\counter$next[1:0]$2655
- attribute \src "libresoc.v:38324.13-38324.27"
+ attribute \src "libresoc.v:46424.3-46454.6"
+ wire width 2 $1\counter$next[1:0]$2658
+ attribute \src "libresoc.v:38320.13-38320.27"
wire width 2 $1\counter[1:0]
- attribute \src "libresoc.v:46460.3-46468.6"
+ attribute \src "libresoc.v:46396.3-46404.6"
wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649
- attribute \src "libresoc.v:39491.7-39491.34"
+ attribute \src "libresoc.v:39487.7-39487.34"
wire $1\dp_CR_cr_a_branch0_1[0:0]
- attribute \src "libresoc.v:46441.3-46449.6"
+ attribute \src "libresoc.v:46377.3-46385.6"
wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643
- attribute \src "libresoc.v:39495.7-39495.30"
+ attribute \src "libresoc.v:39491.7-39491.30"
wire $1\dp_CR_cr_a_cr0_0[0:0]
- attribute \src "libresoc.v:46510.3-46518.6"
- wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661
- attribute \src "libresoc.v:39499.7-39499.30"
+ attribute \src "libresoc.v:46415.3-46423.6"
+ wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2655
+ attribute \src "libresoc.v:39495.7-39495.30"
wire $1\dp_CR_cr_b_cr0_0[0:0]
- attribute \src "libresoc.v:46620.3-46628.6"
- wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668
- attribute \src "libresoc.v:39503.7-39503.30"
+ attribute \src "libresoc.v:46465.3-46473.6"
+ wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667
+ attribute \src "libresoc.v:39499.7-39499.30"
wire $1\dp_CR_cr_c_cr0_0[0:0]
- attribute \src "libresoc.v:46422.3-46430.6"
+ attribute \src "libresoc.v:46358.3-46366.6"
wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637
- attribute \src "libresoc.v:39507.7-39507.33"
+ attribute \src "libresoc.v:39503.7-39503.33"
wire $1\dp_CR_full_cr_cr0_0[0:0]
- attribute \src "libresoc.v:46660.3-46668.6"
- wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679
- attribute \src "libresoc.v:39511.7-39511.37"
+ attribute \src "libresoc.v:46575.3-46583.6"
+ wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2674
+ attribute \src "libresoc.v:39507.7-39507.37"
wire $1\dp_FAST_fast1_branch0_0[0:0]
- attribute \src "libresoc.v:46727.3-46735.6"
- wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692
+ attribute \src "libresoc.v:46682.3-46690.6"
+ wire $1\dp_FAST_fast1_branch0_3$next[0:0]$2698
+ attribute \src "libresoc.v:39511.7-39511.37"
+ wire $1\dp_FAST_fast1_branch0_3[0:0]
+ attribute \src "libresoc.v:46634.3-46642.6"
+ wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2691
attribute \src "libresoc.v:39515.7-39515.34"
wire $1\dp_FAST_fast1_spr0_2[0:0]
- attribute \src "libresoc.v:46679.3-46687.6"
+ attribute \src "libresoc.v:46615.3-46623.6"
wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685
attribute \src "libresoc.v:39519.7-39519.35"
wire $1\dp_FAST_fast1_trap0_1[0:0]
- attribute \src "libresoc.v:46775.3-46783.6"
- wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699
- attribute \src "libresoc.v:39523.7-39523.37"
- wire $1\dp_FAST_fast2_branch0_0[0:0]
- attribute \src "libresoc.v:46794.3-46802.6"
- wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705
- attribute \src "libresoc.v:39527.7-39527.35"
- wire $1\dp_FAST_fast2_trap0_1[0:0]
- attribute \src "libresoc.v:45871.3-45879.6"
- wire $1\dp_INT_ra_alu0_0$next[0:0]$2475
- attribute \src "libresoc.v:39531.7-39531.30"
- wire $1\dp_INT_ra_alu0_0[0:0]
- attribute \src "libresoc.v:45890.3-45898.6"
- wire $1\dp_INT_ra_cr0_1$next[0:0]$2479
- attribute \src "libresoc.v:39535.7-39535.29"
- wire $1\dp_INT_ra_cr0_1[0:0]
- attribute \src "libresoc.v:45966.3-45974.6"
- wire $1\dp_INT_ra_div0_5$next[0:0]$2503
- attribute \src "libresoc.v:39539.7-39539.30"
- wire $1\dp_INT_ra_div0_5[0:0]
- attribute \src "libresoc.v:46023.3-46031.6"
- wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521
- attribute \src "libresoc.v:39543.7-39543.31"
- wire $1\dp_INT_ra_ldst0_8[0:0]
- attribute \src "libresoc.v:45928.3-45936.6"
- wire $1\dp_INT_ra_logical0_3$next[0:0]$2491
- attribute \src "libresoc.v:39547.7-39547.34"
- wire $1\dp_INT_ra_logical0_3[0:0]
- attribute \src "libresoc.v:45985.3-45993.6"
- wire $1\dp_INT_ra_mul0_6$next[0:0]$2509
- attribute \src "libresoc.v:39551.7-39551.30"
- wire $1\dp_INT_ra_mul0_6[0:0]
- attribute \src "libresoc.v:46004.3-46012.6"
- wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515
- attribute \src "libresoc.v:39555.7-39555.35"
- wire $1\dp_INT_ra_shiftrot0_7[0:0]
- attribute \src "libresoc.v:45947.3-45955.6"
- wire $1\dp_INT_ra_spr0_4$next[0:0]$2497
- attribute \src "libresoc.v:39559.7-39559.30"
- wire $1\dp_INT_ra_spr0_4[0:0]
- attribute \src "libresoc.v:45909.3-45917.6"
- wire $1\dp_INT_ra_trap0_2$next[0:0]$2485
- attribute \src "libresoc.v:39563.7-39563.31"
- wire $1\dp_INT_ra_trap0_2[0:0]
- attribute \src "libresoc.v:46042.3-46050.6"
- wire $1\dp_INT_rb_alu0_0$next[0:0]$2527
- attribute \src "libresoc.v:39567.7-39567.30"
- wire $1\dp_INT_rb_alu0_0[0:0]
- attribute \src "libresoc.v:46061.3-46069.6"
- wire $1\dp_INT_rb_cr0_1$next[0:0]$2531
- attribute \src "libresoc.v:39571.7-39571.29"
- wire $1\dp_INT_rb_cr0_1[0:0]
- attribute \src "libresoc.v:46118.3-46126.6"
- wire $1\dp_INT_rb_div0_4$next[0:0]$2549
- attribute \src "libresoc.v:39575.7-39575.30"
- wire $1\dp_INT_rb_div0_4[0:0]
- attribute \src "libresoc.v:46175.3-46183.6"
- wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567
- attribute \src "libresoc.v:39579.7-39579.31"
- wire $1\dp_INT_rb_ldst0_7[0:0]
- attribute \src "libresoc.v:46099.3-46107.6"
- wire $1\dp_INT_rb_logical0_3$next[0:0]$2543
- attribute \src "libresoc.v:39583.7-39583.34"
- wire $1\dp_INT_rb_logical0_3[0:0]
- attribute \src "libresoc.v:46137.3-46145.6"
- wire $1\dp_INT_rb_mul0_5$next[0:0]$2555
- attribute \src "libresoc.v:39587.7-39587.30"
- wire $1\dp_INT_rb_mul0_5[0:0]
- attribute \src "libresoc.v:46156.3-46164.6"
- wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561
- attribute \src "libresoc.v:39591.7-39591.35"
- wire $1\dp_INT_rb_shiftrot0_6[0:0]
- attribute \src "libresoc.v:46080.3-46088.6"
- wire $1\dp_INT_rb_trap0_2$next[0:0]$2537
- attribute \src "libresoc.v:39595.7-39595.31"
- wire $1\dp_INT_rb_trap0_2[0:0]
- attribute \src "libresoc.v:46213.3-46221.6"
- wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577
- attribute \src "libresoc.v:39599.7-39599.31"
- wire $1\dp_INT_rc_ldst0_1[0:0]
- attribute \src "libresoc.v:46194.3-46202.6"
- wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573
- attribute \src "libresoc.v:39603.7-39603.35"
- wire $1\dp_INT_rc_shiftrot0_0[0:0]
- attribute \src "libresoc.v:46843.3-46851.6"
- wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712
- attribute \src "libresoc.v:39607.7-39607.32"
+ attribute \src "libresoc.v:46701.3-46709.6"
+ wire $1\dp_FAST_fast1_trap0_4$next[0:0]$2704
+ attribute \src "libresoc.v:39523.7-39523.35"
+ wire $1\dp_FAST_fast1_trap0_4[0:0]
+ attribute \src "libresoc.v:45807.3-45815.6"
+ wire $1\dp_INT_rabc_alu0_0$next[0:0]$2475
+ attribute \src "libresoc.v:39527.7-39527.32"
+ wire $1\dp_INT_rabc_alu0_0[0:0]
+ attribute \src "libresoc.v:45997.3-46005.6"
+ wire $1\dp_INT_rabc_alu0_10$next[0:0]$2531
+ attribute \src "libresoc.v:39531.7-39531.33"
+ wire $1\dp_INT_rabc_alu0_10[0:0]
+ attribute \src "libresoc.v:45826.3-45834.6"
+ wire $1\dp_INT_rabc_cr0_1$next[0:0]$2479
+ attribute \src "libresoc.v:46016.3-46024.6"
+ wire $1\dp_INT_rabc_cr0_11$next[0:0]$2535
+ attribute \src "libresoc.v:39539.7-39539.32"
+ wire $1\dp_INT_rabc_cr0_11[0:0]
+ attribute \src "libresoc.v:39535.7-39535.31"
+ wire $1\dp_INT_rabc_cr0_1[0:0]
+ attribute \src "libresoc.v:46092.3-46100.6"
+ wire $1\dp_INT_rabc_div0_15$next[0:0]$2559
+ attribute \src "libresoc.v:39543.7-39543.33"
+ wire $1\dp_INT_rabc_div0_15[0:0]
+ attribute \src "libresoc.v:45883.3-45891.6"
+ wire $1\dp_INT_rabc_div0_4$next[0:0]$2497
+ attribute \src "libresoc.v:39547.7-39547.32"
+ wire $1\dp_INT_rabc_div0_4[0:0]
+ attribute \src "libresoc.v:46149.3-46157.6"
+ wire $1\dp_INT_rabc_ldst0_18$next[0:0]$2577
+ attribute \src "libresoc.v:39551.7-39551.34"
+ wire $1\dp_INT_rabc_ldst0_18[0:0]
+ attribute \src "libresoc.v:45940.3-45948.6"
+ wire $1\dp_INT_rabc_ldst0_7$next[0:0]$2515
+ attribute \src "libresoc.v:39555.7-39555.33"
+ wire $1\dp_INT_rabc_ldst0_7[0:0]
+ attribute \src "libresoc.v:45978.3-45986.6"
+ wire $1\dp_INT_rabc_ldst0_9$next[0:0]$2525
+ attribute \src "libresoc.v:39559.7-39559.33"
+ wire $1\dp_INT_rabc_ldst0_9[0:0]
+ attribute \src "libresoc.v:46054.3-46062.6"
+ wire $1\dp_INT_rabc_logical0_13$next[0:0]$2547
+ attribute \src "libresoc.v:39563.7-39563.37"
+ wire $1\dp_INT_rabc_logical0_13[0:0]
+ attribute \src "libresoc.v:45864.3-45872.6"
+ wire $1\dp_INT_rabc_logical0_3$next[0:0]$2491
+ attribute \src "libresoc.v:39567.7-39567.36"
+ wire $1\dp_INT_rabc_logical0_3[0:0]
+ attribute \src "libresoc.v:46111.3-46119.6"
+ wire $1\dp_INT_rabc_mul0_16$next[0:0]$2565
+ attribute \src "libresoc.v:39571.7-39571.33"
+ wire $1\dp_INT_rabc_mul0_16[0:0]
+ attribute \src "libresoc.v:45902.3-45910.6"
+ wire $1\dp_INT_rabc_mul0_5$next[0:0]$2503
+ attribute \src "libresoc.v:39575.7-39575.32"
+ wire $1\dp_INT_rabc_mul0_5[0:0]
+ attribute \src "libresoc.v:46130.3-46138.6"
+ wire $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571
+ attribute \src "libresoc.v:39579.7-39579.38"
+ wire $1\dp_INT_rabc_shiftrot0_17[0:0]
+ attribute \src "libresoc.v:45921.3-45929.6"
+ wire $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509
+ attribute \src "libresoc.v:39583.7-39583.37"
+ wire $1\dp_INT_rabc_shiftrot0_6[0:0]
+ attribute \src "libresoc.v:45959.3-45967.6"
+ wire $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521
+ attribute \src "libresoc.v:39587.7-39587.37"
+ wire $1\dp_INT_rabc_shiftrot0_8[0:0]
+ attribute \src "libresoc.v:46073.3-46081.6"
+ wire $1\dp_INT_rabc_spr0_14$next[0:0]$2553
+ attribute \src "libresoc.v:39591.7-39591.33"
+ wire $1\dp_INT_rabc_spr0_14[0:0]
+ attribute \src "libresoc.v:46035.3-46043.6"
+ wire $1\dp_INT_rabc_trap0_12$next[0:0]$2541
+ attribute \src "libresoc.v:39595.7-39595.34"
+ wire $1\dp_INT_rabc_trap0_12[0:0]
+ attribute \src "libresoc.v:45845.3-45853.6"
+ wire $1\dp_INT_rabc_trap0_2$next[0:0]$2485
+ attribute \src "libresoc.v:39599.7-39599.33"
+ wire $1\dp_INT_rabc_trap0_2[0:0]
+ attribute \src "libresoc.v:46749.3-46757.6"
+ wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2711
+ attribute \src "libresoc.v:39603.7-39603.32"
wire $1\dp_SPR_spr1_spr0_0[0:0]
- attribute \src "libresoc.v:46346.3-46354.6"
+ attribute \src "libresoc.v:46282.3-46290.6"
wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617
- attribute \src "libresoc.v:39611.7-39611.34"
+ attribute \src "libresoc.v:39607.7-39607.34"
wire $1\dp_XER_xer_ca_alu0_0[0:0]
- attribute \src "libresoc.v:46384.3-46392.6"
+ attribute \src "libresoc.v:46320.3-46328.6"
wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627
- attribute \src "libresoc.v:39615.7-39615.39"
+ attribute \src "libresoc.v:39611.7-39611.39"
wire $1\dp_XER_xer_ca_shiftrot0_2[0:0]
- attribute \src "libresoc.v:46365.3-46373.6"
+ attribute \src "libresoc.v:46301.3-46309.6"
wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623
- attribute \src "libresoc.v:39619.7-39619.34"
+ attribute \src "libresoc.v:39615.7-39615.34"
wire $1\dp_XER_xer_ca_spr0_1[0:0]
- attribute \src "libresoc.v:46403.3-46411.6"
+ attribute \src "libresoc.v:46339.3-46347.6"
wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631
- attribute \src "libresoc.v:39623.7-39623.34"
+ attribute \src "libresoc.v:39619.7-39619.34"
wire $1\dp_XER_xer_ov_spr0_0[0:0]
- attribute \src "libresoc.v:46232.3-46240.6"
+ attribute \src "libresoc.v:46168.3-46176.6"
wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583
- attribute \src "libresoc.v:39627.7-39627.34"
+ attribute \src "libresoc.v:39623.7-39623.34"
wire $1\dp_XER_xer_so_alu0_0[0:0]
- attribute \src "libresoc.v:46289.3-46297.6"
+ attribute \src "libresoc.v:46225.3-46233.6"
wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599
- attribute \src "libresoc.v:39631.7-39631.34"
+ attribute \src "libresoc.v:39627.7-39627.34"
wire $1\dp_XER_xer_so_div0_3[0:0]
- attribute \src "libresoc.v:46251.3-46259.6"
+ attribute \src "libresoc.v:46187.3-46195.6"
wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589
- attribute \src "libresoc.v:39635.7-39635.38"
+ attribute \src "libresoc.v:39631.7-39631.38"
wire $1\dp_XER_xer_so_logical0_1[0:0]
- attribute \src "libresoc.v:46308.3-46316.6"
+ attribute \src "libresoc.v:46244.3-46252.6"
wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605
- attribute \src "libresoc.v:39639.7-39639.34"
+ attribute \src "libresoc.v:39635.7-39635.34"
wire $1\dp_XER_xer_so_mul0_4[0:0]
- attribute \src "libresoc.v:46327.3-46335.6"
+ attribute \src "libresoc.v:46263.3-46271.6"
wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611
- attribute \src "libresoc.v:39643.7-39643.39"
+ attribute \src "libresoc.v:39639.7-39639.39"
wire $1\dp_XER_xer_so_shiftrot0_5[0:0]
- attribute \src "libresoc.v:46270.3-46278.6"
+ attribute \src "libresoc.v:46206.3-46214.6"
wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595
- attribute \src "libresoc.v:39647.7-39647.34"
+ attribute \src "libresoc.v:39643.7-39643.34"
wire $1\dp_XER_xer_so_spr0_2[0:0]
- attribute \src "libresoc.v:47618.3-47646.6"
- wire $1\fus_cu_issue_i$13[0:0]$2822
- attribute \src "libresoc.v:47952.3-47980.6"
+ attribute \src "libresoc.v:47563.3-47591.6"
+ wire $1\fus_cu_issue_i$13[0:0]$2825
+ attribute \src "libresoc.v:47888.3-47916.6"
wire $1\fus_cu_issue_i$16[0:0]$2863
- attribute \src "libresoc.v:48271.3-48299.6"
+ attribute \src "libresoc.v:48207.3-48235.6"
wire $1\fus_cu_issue_i$19[0:0]$2882
- attribute \src "libresoc.v:43916.3-43944.6"
+ attribute \src "libresoc.v:43852.3-43880.6"
wire $1\fus_cu_issue_i$22[0:0]$2360
- attribute \src "libresoc.v:44090.3-44118.6"
+ attribute \src "libresoc.v:44026.3-44054.6"
wire $1\fus_cu_issue_i$25[0:0]$2374
- attribute \src "libresoc.v:44586.3-44614.6"
+ attribute \src "libresoc.v:44522.3-44550.6"
wire $1\fus_cu_issue_i$28[0:0]$2399
- attribute \src "libresoc.v:44908.3-44936.6"
+ attribute \src "libresoc.v:44844.3-44872.6"
wire $1\fus_cu_issue_i$31[0:0]$2418
- attribute \src "libresoc.v:45375.3-45403.6"
+ attribute \src "libresoc.v:45311.3-45339.6"
wire $1\fus_cu_issue_i$34[0:0]$2442
- attribute \src "libresoc.v:45813.3-45841.6"
+ attribute \src "libresoc.v:45749.3-45777.6"
wire $1\fus_cu_issue_i$37[0:0]$2465
- attribute \src "libresoc.v:47401.3-47429.6"
+ attribute \src "libresoc.v:47355.3-47383.6"
wire $1\fus_cu_issue_i[0:0]
- attribute \src "libresoc.v:47656.3-47684.6"
- wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830
- attribute \src "libresoc.v:47981.3-48009.6"
+ attribute \src "libresoc.v:47610.3-47638.6"
+ wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2836
+ attribute \src "libresoc.v:47917.3-47945.6"
wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868
- attribute \src "libresoc.v:48300.3-48328.6"
+ attribute \src "libresoc.v:48236.3-48264.6"
wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887
- attribute \src "libresoc.v:43945.3-43973.6"
+ attribute \src "libresoc.v:43881.3-43909.6"
wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365
- attribute \src "libresoc.v:44119.3-44147.6"
+ attribute \src "libresoc.v:44055.3-44083.6"
wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379
- attribute \src "libresoc.v:44615.3-44643.6"
+ attribute \src "libresoc.v:44551.3-44579.6"
wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404
- attribute \src "libresoc.v:44937.3-44965.6"
+ attribute \src "libresoc.v:44873.3-44901.6"
wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423
- attribute \src "libresoc.v:45404.3-45432.6"
+ attribute \src "libresoc.v:45340.3-45368.6"
wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447
- attribute \src "libresoc.v:45842.3-45870.6"
+ attribute \src "libresoc.v:45778.3-45806.6"
wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470
- attribute \src "libresoc.v:47448.3-47476.6"
+ attribute \src "libresoc.v:47393.3-47421.6"
wire width 4 $1\fus_cu_rdmaskn_i[3:0]
- attribute \src "libresoc.v:47325.3-47353.6"
+ attribute \src "libresoc.v:47270.3-47298.6"
wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "libresoc.v:46746.3-46774.6"
+ attribute \src "libresoc.v:46720.3-46748.6"
wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47146.3-47174.6"
+ attribute \src "libresoc.v:47100.3-47128.6"
wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "libresoc.v:47363.3-47391.6"
+ attribute \src "libresoc.v:47308.3-47336.6"
wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "libresoc.v:46698.3-46726.6"
+ attribute \src "libresoc.v:46653.3-46681.6"
wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "libresoc.v:46985.3-47013.6"
+ attribute \src "libresoc.v:46939.3-46967.6"
wire $1\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "libresoc.v:47070.3-47098.6"
+ attribute \src "libresoc.v:47015.3-47043.6"
wire $1\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "libresoc.v:47240.3-47268.6"
+ attribute \src "libresoc.v:47185.3-47213.6"
wire $1\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "libresoc.v:47278.3-47306.6"
+ attribute \src "libresoc.v:47223.3-47251.6"
wire $1\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $1\fus_oper_i_alu_alu0__oe__oe[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $1\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "libresoc.v:47193.3-47221.6"
+ attribute \src "libresoc.v:47147.3-47175.6"
wire $1\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $1\fus_oper_i_alu_alu0__rc__ok[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $1\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "libresoc.v:47108.3-47136.6"
+ attribute \src "libresoc.v:47053.3-47081.6"
wire $1\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "libresoc.v:47032.3-47060.6"
+ attribute \src "libresoc.v:46977.3-47005.6"
wire $1\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "libresoc.v:47703.3-47731.6"
+ attribute \src "libresoc.v:47648.3-47676.6"
wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "libresoc.v:47788.3-47816.6"
+ attribute \src "libresoc.v:47733.3-47761.6"
wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47826.3-47854.6"
+ attribute \src "libresoc.v:47771.3-47799.6"
wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "libresoc.v:47741.3-47769.6"
+ attribute \src "libresoc.v:47686.3-47714.6"
wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "libresoc.v:47923.3-47951.6"
+ attribute \src "libresoc.v:47859.3-47887.6"
wire $1\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "libresoc.v:47894.3-47922.6"
+ attribute \src "libresoc.v:47830.3-47858.6"
wire $1\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "libresoc.v:47533.3-47561.6"
+ attribute \src "libresoc.v:47478.3-47506.6"
wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "libresoc.v:47580.3-47608.6"
+ attribute \src "libresoc.v:47525.3-47553.6"
wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "libresoc.v:47486.3-47514.6"
+ attribute \src "libresoc.v:47440.3-47468.6"
wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "libresoc.v:44528.3-44556.6"
+ attribute \src "libresoc.v:44464.3-44492.6"
wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "libresoc.v:44177.3-44205.6"
+ attribute \src "libresoc.v:44113.3-44141.6"
wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44354.3-44382.6"
+ attribute \src "libresoc.v:44290.3-44318.6"
wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "libresoc.v:44557.3-44585.6"
+ attribute \src "libresoc.v:44493.3-44521.6"
wire width 32 $1\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "libresoc.v:44148.3-44176.6"
+ attribute \src "libresoc.v:44084.3-44112.6"
wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "libresoc.v:44296.3-44324.6"
+ attribute \src "libresoc.v:44232.3-44260.6"
wire $1\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "libresoc.v:44383.3-44411.6"
+ attribute \src "libresoc.v:44319.3-44347.6"
wire $1\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "libresoc.v:44470.3-44498.6"
+ attribute \src "libresoc.v:44406.3-44434.6"
wire $1\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "libresoc.v:44499.3-44527.6"
+ attribute \src "libresoc.v:44435.3-44463.6"
wire $1\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $1\fus_oper_i_alu_div0__oe__oe[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $1\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "libresoc.v:44441.3-44469.6"
+ attribute \src "libresoc.v:44377.3-44405.6"
wire $1\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $1\fus_oper_i_alu_div0__rc__ok[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $1\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "libresoc.v:44412.3-44440.6"
+ attribute \src "libresoc.v:44348.3-44376.6"
wire $1\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "libresoc.v:44325.3-44353.6"
+ attribute \src "libresoc.v:44261.3-44289.6"
wire $1\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "libresoc.v:43858.3-43886.6"
+ attribute \src "libresoc.v:43794.3-43822.6"
wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "libresoc.v:48358.3-48386.6"
+ attribute \src "libresoc.v:48294.3-48322.6"
wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "libresoc.v:48535.3-48563.6"
+ attribute \src "libresoc.v:48471.3-48499.6"
wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "libresoc.v:43887.3-43915.6"
+ attribute \src "libresoc.v:43823.3-43851.6"
wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "libresoc.v:48329.3-48357.6"
+ attribute \src "libresoc.v:48265.3-48293.6"
wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "libresoc.v:48477.3-48505.6"
+ attribute \src "libresoc.v:48413.3-48441.6"
wire $1\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "libresoc.v:48564.3-48592.6"
+ attribute \src "libresoc.v:48500.3-48528.6"
wire $1\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "libresoc.v:43800.3-43828.6"
+ attribute \src "libresoc.v:43736.3-43764.6"
wire $1\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "libresoc.v:43829.3-43857.6"
+ attribute \src "libresoc.v:43765.3-43793.6"
wire $1\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $1\fus_oper_i_alu_logical0__oe__oe[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $1\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "libresoc.v:43771.3-43799.6"
+ attribute \src "libresoc.v:43707.3-43735.6"
wire $1\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $1\fus_oper_i_alu_logical0__rc__ok[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $1\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "libresoc.v:48593.3-48621.6"
+ attribute \src "libresoc.v:48529.3-48557.6"
wire $1\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "libresoc.v:48506.3-48534.6"
+ attribute \src "libresoc.v:48442.3-48470.6"
wire $1\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "libresoc.v:44673.3-44701.6"
+ attribute \src "libresoc.v:44609.3-44637.6"
wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44879.3-44907.6"
+ attribute \src "libresoc.v:44815.3-44843.6"
wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "libresoc.v:44644.3-44672.6"
+ attribute \src "libresoc.v:44580.3-44608.6"
wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "libresoc.v:44821.3-44849.6"
+ attribute \src "libresoc.v:44757.3-44785.6"
wire $1\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "libresoc.v:44850.3-44878.6"
+ attribute \src "libresoc.v:44786.3-44814.6"
wire $1\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $1\fus_oper_i_alu_mul0__oe__oe[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $1\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $1\fus_oper_i_alu_mul0__rc__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $1\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "libresoc.v:44792.3-44820.6"
+ attribute \src "libresoc.v:44728.3-44756.6"
wire $1\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "libresoc.v:44995.3-45023.6"
+ attribute \src "libresoc.v:44931.3-44959.6"
wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45172.3-45200.6"
+ attribute \src "libresoc.v:45108.3-45136.6"
wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "libresoc.v:45230.3-45258.6"
+ attribute \src "libresoc.v:45166.3-45194.6"
wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "libresoc.v:45346.3-45374.6"
+ attribute \src "libresoc.v:45282.3-45310.6"
wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "libresoc.v:44966.3-44994.6"
+ attribute \src "libresoc.v:44902.3-44930.6"
wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "libresoc.v:45143.3-45171.6"
+ attribute \src "libresoc.v:45079.3-45107.6"
wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "libresoc.v:45288.3-45316.6"
+ attribute \src "libresoc.v:45224.3-45252.6"
wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "libresoc.v:45317.3-45345.6"
+ attribute \src "libresoc.v:45253.3-45281.6"
wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "libresoc.v:45201.3-45229.6"
+ attribute \src "libresoc.v:45137.3-45165.6"
wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "libresoc.v:45259.3-45287.6"
+ attribute \src "libresoc.v:45195.3-45223.6"
wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "libresoc.v:45114.3-45142.6"
+ attribute \src "libresoc.v:45050.3-45078.6"
wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "libresoc.v:44003.3-44031.6"
+ attribute \src "libresoc.v:43939.3-43967.6"
wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "libresoc.v:44032.3-44060.6"
+ attribute \src "libresoc.v:43968.3-43996.6"
wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "libresoc.v:43974.3-44002.6"
+ attribute \src "libresoc.v:43910.3-43938.6"
wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "libresoc.v:44061.3-44089.6"
+ attribute \src "libresoc.v:43997.3-44025.6"
wire $1\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "libresoc.v:48126.3-48154.6"
+ attribute \src "libresoc.v:48062.3-48090.6"
wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "libresoc.v:48039.3-48067.6"
+ attribute \src "libresoc.v:47975.3-48003.6"
wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "libresoc.v:48068.3-48096.6"
+ attribute \src "libresoc.v:48004.3-48032.6"
wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "libresoc.v:48010.3-48038.6"
+ attribute \src "libresoc.v:47946.3-47974.6"
wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "libresoc.v:48155.3-48183.6"
+ attribute \src "libresoc.v:48091.3-48119.6"
wire $1\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "libresoc.v:48242.3-48270.6"
+ attribute \src "libresoc.v:48178.3-48206.6"
wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "libresoc.v:48097.3-48125.6"
+ attribute \src "libresoc.v:48033.3-48061.6"
wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "libresoc.v:48213.3-48241.6"
+ attribute \src "libresoc.v:48149.3-48177.6"
wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "libresoc.v:48184.3-48212.6"
+ attribute \src "libresoc.v:48120.3-48148.6"
wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "libresoc.v:45697.3-45725.6"
+ attribute \src "libresoc.v:45633.3-45661.6"
wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "libresoc.v:45668.3-45696.6"
+ attribute \src "libresoc.v:45604.3-45632.6"
wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "libresoc.v:45462.3-45490.6"
+ attribute \src "libresoc.v:45398.3-45426.6"
wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45784.3-45812.6"
+ attribute \src "libresoc.v:45720.3-45748.6"
wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "libresoc.v:45433.3-45461.6"
+ attribute \src "libresoc.v:45369.3-45397.6"
wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "libresoc.v:45610.3-45638.6"
+ attribute \src "libresoc.v:45546.3-45574.6"
wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "libresoc.v:45639.3-45667.6"
+ attribute \src "libresoc.v:45575.3-45603.6"
wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "libresoc.v:45755.3-45783.6"
+ attribute \src "libresoc.v:45691.3-45719.6"
wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "libresoc.v:45726.3-45754.6"
+ attribute \src "libresoc.v:45662.3-45690.6"
wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "libresoc.v:45521.3-45549.6"
+ attribute \src "libresoc.v:45457.3-45485.6"
wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "libresoc.v:45899.3-45908.6"
- wire width 64 $1\fus_src1_i$42[63:0]$2482
- attribute \src "libresoc.v:45918.3-45927.6"
- wire width 64 $1\fus_src1_i$45[63:0]$2488
- attribute \src "libresoc.v:45937.3-45946.6"
- wire width 64 $1\fus_src1_i$48[63:0]$2494
- attribute \src "libresoc.v:45956.3-45965.6"
- wire width 64 $1\fus_src1_i$51[63:0]$2500
- attribute \src "libresoc.v:45975.3-45984.6"
- wire width 64 $1\fus_src1_i$54[63:0]$2506
- attribute \src "libresoc.v:45994.3-46003.6"
- wire width 64 $1\fus_src1_i$57[63:0]$2512
- attribute \src "libresoc.v:46013.3-46022.6"
- wire width 64 $1\fus_src1_i$60[63:0]$2518
- attribute \src "libresoc.v:46032.3-46041.6"
- wire width 64 $1\fus_src1_i$63[63:0]$2524
- attribute \src "libresoc.v:46669.3-46678.6"
- wire width 64 $1\fus_src1_i$86[63:0]$2682
- attribute \src "libresoc.v:45880.3-45889.6"
+ attribute \src "libresoc.v:46025.3-46034.6"
+ wire width 64 $1\fus_src1_i$62[63:0]$2538
+ attribute \src "libresoc.v:46044.3-46053.6"
+ wire width 64 $1\fus_src1_i$63[63:0]$2544
+ attribute \src "libresoc.v:46063.3-46072.6"
+ wire width 64 $1\fus_src1_i$64[63:0]$2550
+ attribute \src "libresoc.v:46082.3-46091.6"
+ wire width 64 $1\fus_src1_i$67[63:0]$2556
+ attribute \src "libresoc.v:46101.3-46110.6"
+ wire width 64 $1\fus_src1_i$68[63:0]$2562
+ attribute \src "libresoc.v:46120.3-46129.6"
+ wire width 64 $1\fus_src1_i$69[63:0]$2568
+ attribute \src "libresoc.v:46139.3-46148.6"
+ wire width 64 $1\fus_src1_i$70[63:0]$2574
+ attribute \src "libresoc.v:46158.3-46167.6"
+ wire width 64 $1\fus_src1_i$71[63:0]$2580
+ attribute \src "libresoc.v:46584.3-46593.6"
+ wire width 64 $1\fus_src1_i$86[63:0]$2677
+ attribute \src "libresoc.v:46006.3-46015.6"
wire width 64 $1\fus_src1_i[63:0]
- attribute \src "libresoc.v:46070.3-46079.6"
- wire width 64 $1\fus_src2_i$64[63:0]$2534
- attribute \src "libresoc.v:46089.3-46098.6"
- wire width 64 $1\fus_src2_i$65[63:0]$2540
- attribute \src "libresoc.v:46108.3-46117.6"
- wire width 64 $1\fus_src2_i$66[63:0]$2546
- attribute \src "libresoc.v:46127.3-46136.6"
- wire width 64 $1\fus_src2_i$67[63:0]$2552
- attribute \src "libresoc.v:46146.3-46155.6"
- wire width 64 $1\fus_src2_i$68[63:0]$2558
- attribute \src "libresoc.v:46165.3-46174.6"
- wire width 64 $1\fus_src2_i$69[63:0]$2564
- attribute \src "libresoc.v:46184.3-46193.6"
- wire width 64 $1\fus_src2_i$70[63:0]$2570
- attribute \src "libresoc.v:46784.3-46793.6"
- wire width 64 $1\fus_src2_i$89[63:0]$2702
- attribute \src "libresoc.v:46852.3-46861.6"
- wire width 64 $1\fus_src2_i$91[63:0]$2715
- attribute \src "libresoc.v:46051.3-46060.6"
+ attribute \src "libresoc.v:45835.3-45844.6"
+ wire width 64 $1\fus_src2_i$42[63:0]$2482
+ attribute \src "libresoc.v:45854.3-45863.6"
+ wire width 64 $1\fus_src2_i$45[63:0]$2488
+ attribute \src "libresoc.v:45873.3-45882.6"
+ wire width 64 $1\fus_src2_i$48[63:0]$2494
+ attribute \src "libresoc.v:45892.3-45901.6"
+ wire width 64 $1\fus_src2_i$51[63:0]$2500
+ attribute \src "libresoc.v:45911.3-45920.6"
+ wire width 64 $1\fus_src2_i$54[63:0]$2506
+ attribute \src "libresoc.v:45930.3-45939.6"
+ wire width 64 $1\fus_src2_i$57[63:0]$2512
+ attribute \src "libresoc.v:45949.3-45958.6"
+ wire width 64 $1\fus_src2_i$60[63:0]$2518
+ attribute \src "libresoc.v:46691.3-46700.6"
+ wire width 64 $1\fus_src2_i$89[63:0]$2701
+ attribute \src "libresoc.v:46758.3-46767.6"
+ wire width 64 $1\fus_src2_i$91[63:0]$2714
+ attribute \src "libresoc.v:45816.3-45825.6"
wire width 64 $1\fus_src2_i[63:0]
- attribute \src "libresoc.v:46222.3-46231.6"
- wire width 64 $1\fus_src3_i$71[63:0]$2580
- attribute \src "libresoc.v:46241.3-46250.6"
+ attribute \src "libresoc.v:45987.3-45996.6"
+ wire width 64 $1\fus_src3_i$61[63:0]$2528
+ attribute \src "libresoc.v:46177.3-46186.6"
wire $1\fus_src3_i$72[0:0]$2586
- attribute \src "libresoc.v:46260.3-46269.6"
+ attribute \src "libresoc.v:46196.3-46205.6"
wire $1\fus_src3_i$73[0:0]$2592
- attribute \src "libresoc.v:46298.3-46307.6"
+ attribute \src "libresoc.v:46234.3-46243.6"
wire $1\fus_src3_i$74[0:0]$2602
- attribute \src "libresoc.v:46317.3-46326.6"
+ attribute \src "libresoc.v:46253.3-46262.6"
wire $1\fus_src3_i$75[0:0]$2608
- attribute \src "libresoc.v:46431.3-46440.6"
+ attribute \src "libresoc.v:46367.3-46376.6"
wire width 32 $1\fus_src3_i$79[31:0]$2640
- attribute \src "libresoc.v:46469.3-46478.6"
+ attribute \src "libresoc.v:46405.3-46414.6"
wire width 4 $1\fus_src3_i$83[3:0]$2652
- attribute \src "libresoc.v:46688.3-46697.6"
+ attribute \src "libresoc.v:46624.3-46633.6"
wire width 64 $1\fus_src3_i$87[63:0]$2688
- attribute \src "libresoc.v:46736.3-46745.6"
- wire width 64 $1\fus_src3_i$88[63:0]$2695
- attribute \src "libresoc.v:46203.3-46212.6"
+ attribute \src "libresoc.v:46643.3-46652.6"
+ wire width 64 $1\fus_src3_i$88[63:0]$2694
+ attribute \src "libresoc.v:45968.3-45977.6"
wire width 64 $1\fus_src3_i[63:0]
- attribute \src "libresoc.v:46336.3-46345.6"
+ attribute \src "libresoc.v:46272.3-46281.6"
wire $1\fus_src4_i$76[0:0]$2614
- attribute \src "libresoc.v:46355.3-46364.6"
+ attribute \src "libresoc.v:46291.3-46300.6"
wire width 2 $1\fus_src4_i$77[1:0]$2620
- attribute \src "libresoc.v:46450.3-46459.6"
+ attribute \src "libresoc.v:46386.3-46395.6"
wire width 4 $1\fus_src4_i$80[3:0]$2646
- attribute \src "libresoc.v:46803.3-46812.6"
- wire width 64 $1\fus_src4_i$90[63:0]$2708
- attribute \src "libresoc.v:46279.3-46288.6"
+ attribute \src "libresoc.v:46710.3-46719.6"
+ wire width 64 $1\fus_src4_i$90[63:0]$2707
+ attribute \src "libresoc.v:46215.3-46224.6"
wire $1\fus_src4_i[0:0]
- attribute \src "libresoc.v:46412.3-46421.6"
+ attribute \src "libresoc.v:46348.3-46357.6"
wire width 2 $1\fus_src5_i$78[1:0]$2634
- attribute \src "libresoc.v:46519.3-46528.6"
+ attribute \src "libresoc.v:46455.3-46464.6"
wire width 4 $1\fus_src5_i$84[3:0]$2664
- attribute \src "libresoc.v:46393.3-46402.6"
+ attribute \src "libresoc.v:46329.3-46338.6"
wire width 2 $1\fus_src5_i[1:0]
- attribute \src "libresoc.v:46629.3-46638.6"
- wire width 4 $1\fus_src6_i$85[3:0]$2671
- attribute \src "libresoc.v:46374.3-46383.6"
+ attribute \src "libresoc.v:46474.3-46483.6"
+ wire width 4 $1\fus_src6_i$85[3:0]$2670
+ attribute \src "libresoc.v:46310.3-46319.6"
wire width 2 $1\fus_src6_i[1:0]
- attribute \src "libresoc.v:46910.3-46918.6"
- wire $1\wr_pick_dly$1010$next[0:0]$2725
- attribute \src "libresoc.v:46919.3-46927.6"
- wire $1\wr_pick_dly$1031$next[0:0]$2728
- attribute \src "libresoc.v:46958.3-46966.6"
- wire $1\wr_pick_dly$1049$next[0:0]$2732
- attribute \src "libresoc.v:46967.3-46975.6"
- wire $1\wr_pick_dly$1071$next[0:0]$2735
- attribute \src "libresoc.v:46976.3-46984.6"
- wire $1\wr_pick_dly$1091$next[0:0]$2738
- attribute \src "libresoc.v:47014.3-47022.6"
- wire $1\wr_pick_dly$1111$next[0:0]$2742
- attribute \src "libresoc.v:47023.3-47031.6"
- wire $1\wr_pick_dly$1130$next[0:0]$2745
- attribute \src "libresoc.v:47061.3-47069.6"
- wire $1\wr_pick_dly$1148$next[0:0]$2749
- attribute \src "libresoc.v:47099.3-47107.6"
- wire $1\wr_pick_dly$1222$next[0:0]$2753
- attribute \src "libresoc.v:47137.3-47145.6"
- wire $1\wr_pick_dly$1250$next[0:0]$2757
- attribute \src "libresoc.v:47175.3-47183.6"
- wire $1\wr_pick_dly$1270$next[0:0]$2761
- attribute \src "libresoc.v:47184.3-47192.6"
- wire $1\wr_pick_dly$1290$next[0:0]$2764
- attribute \src "libresoc.v:47222.3-47230.6"
- wire $1\wr_pick_dly$1310$next[0:0]$2768
- attribute \src "libresoc.v:47231.3-47239.6"
- wire $1\wr_pick_dly$1330$next[0:0]$2771
- attribute \src "libresoc.v:47269.3-47277.6"
- wire $1\wr_pick_dly$1350$next[0:0]$2775
- attribute \src "libresoc.v:47307.3-47315.6"
- wire $1\wr_pick_dly$1397$next[0:0]$2779
- attribute \src "libresoc.v:47316.3-47324.6"
- wire $1\wr_pick_dly$1413$next[0:0]$2782
- attribute \src "libresoc.v:47354.3-47362.6"
- wire $1\wr_pick_dly$1429$next[0:0]$2786
- attribute \src "libresoc.v:47392.3-47400.6"
- wire $1\wr_pick_dly$1463$next[0:0]$2790
- attribute \src "libresoc.v:47430.3-47438.6"
- wire $1\wr_pick_dly$1479$next[0:0]$2794
- attribute \src "libresoc.v:47439.3-47447.6"
- wire $1\wr_pick_dly$1495$next[0:0]$2797
- attribute \src "libresoc.v:47477.3-47485.6"
- wire $1\wr_pick_dly$1511$next[0:0]$2801
- attribute \src "libresoc.v:47515.3-47523.6"
- wire $1\wr_pick_dly$1547$next[0:0]$2805
- attribute \src "libresoc.v:47524.3-47532.6"
- wire $1\wr_pick_dly$1563$next[0:0]$2808
- attribute \src "libresoc.v:47562.3-47570.6"
- wire $1\wr_pick_dly$1579$next[0:0]$2812
- attribute \src "libresoc.v:47571.3-47579.6"
- wire $1\wr_pick_dly$1595$next[0:0]$2815
- attribute \src "libresoc.v:47609.3-47617.6"
- wire $1\wr_pick_dly$1637$next[0:0]$2819
- attribute \src "libresoc.v:47647.3-47655.6"
- wire $1\wr_pick_dly$1656$next[0:0]$2827
- attribute \src "libresoc.v:47685.3-47693.6"
- wire $1\wr_pick_dly$1672$next[0:0]$2835
- attribute \src "libresoc.v:47694.3-47702.6"
- wire $1\wr_pick_dly$1688$next[0:0]$2838
- attribute \src "libresoc.v:47732.3-47740.6"
- wire $1\wr_pick_dly$1704$next[0:0]$2842
- attribute \src "libresoc.v:47770.3-47778.6"
- wire $1\wr_pick_dly$1748$next[0:0]$2846
- attribute \src "libresoc.v:47779.3-47787.6"
- wire $1\wr_pick_dly$1764$next[0:0]$2849
- attribute \src "libresoc.v:47817.3-47825.6"
- wire $1\wr_pick_dly$1788$next[0:0]$2853
- attribute \src "libresoc.v:47855.3-47863.6"
- wire $1\wr_pick_dly$1808$next[0:0]$2857
- attribute \src "libresoc.v:46871.3-46879.6"
- wire $1\wr_pick_dly$991$next[0:0]$2721
- attribute \src "libresoc.v:46862.3-46870.6"
+ attribute \src "libresoc.v:46816.3-46824.6"
+ wire $1\wr_pick_dly$1008$next[0:0]$2724
+ attribute \src "libresoc.v:46855.3-46863.6"
+ wire $1\wr_pick_dly$1029$next[0:0]$2728
+ attribute \src "libresoc.v:46864.3-46872.6"
+ wire $1\wr_pick_dly$1047$next[0:0]$2731
+ attribute \src "libresoc.v:46873.3-46881.6"
+ wire $1\wr_pick_dly$1069$next[0:0]$2734
+ attribute \src "libresoc.v:46912.3-46920.6"
+ wire $1\wr_pick_dly$1089$next[0:0]$2738
+ attribute \src "libresoc.v:46921.3-46929.6"
+ wire $1\wr_pick_dly$1109$next[0:0]$2741
+ attribute \src "libresoc.v:46930.3-46938.6"
+ wire $1\wr_pick_dly$1128$next[0:0]$2744
+ attribute \src "libresoc.v:46968.3-46976.6"
+ wire $1\wr_pick_dly$1146$next[0:0]$2748
+ attribute \src "libresoc.v:47006.3-47014.6"
+ wire $1\wr_pick_dly$1220$next[0:0]$2752
+ attribute \src "libresoc.v:47044.3-47052.6"
+ wire $1\wr_pick_dly$1248$next[0:0]$2756
+ attribute \src "libresoc.v:47082.3-47090.6"
+ wire $1\wr_pick_dly$1268$next[0:0]$2760
+ attribute \src "libresoc.v:47091.3-47099.6"
+ wire $1\wr_pick_dly$1288$next[0:0]$2763
+ attribute \src "libresoc.v:47129.3-47137.6"
+ wire $1\wr_pick_dly$1308$next[0:0]$2767
+ attribute \src "libresoc.v:47138.3-47146.6"
+ wire $1\wr_pick_dly$1328$next[0:0]$2770
+ attribute \src "libresoc.v:47176.3-47184.6"
+ wire $1\wr_pick_dly$1348$next[0:0]$2774
+ attribute \src "libresoc.v:47214.3-47222.6"
+ wire $1\wr_pick_dly$1395$next[0:0]$2778
+ attribute \src "libresoc.v:47252.3-47260.6"
+ wire $1\wr_pick_dly$1411$next[0:0]$2782
+ attribute \src "libresoc.v:47261.3-47269.6"
+ wire $1\wr_pick_dly$1427$next[0:0]$2785
+ attribute \src "libresoc.v:47299.3-47307.6"
+ wire $1\wr_pick_dly$1461$next[0:0]$2789
+ attribute \src "libresoc.v:47337.3-47345.6"
+ wire $1\wr_pick_dly$1477$next[0:0]$2793
+ attribute \src "libresoc.v:47346.3-47354.6"
+ wire $1\wr_pick_dly$1493$next[0:0]$2796
+ attribute \src "libresoc.v:47384.3-47392.6"
+ wire $1\wr_pick_dly$1509$next[0:0]$2800
+ attribute \src "libresoc.v:47422.3-47430.6"
+ wire $1\wr_pick_dly$1545$next[0:0]$2804
+ attribute \src "libresoc.v:47431.3-47439.6"
+ wire $1\wr_pick_dly$1561$next[0:0]$2807
+ attribute \src "libresoc.v:47469.3-47477.6"
+ wire $1\wr_pick_dly$1577$next[0:0]$2811
+ attribute \src "libresoc.v:47507.3-47515.6"
+ wire $1\wr_pick_dly$1593$next[0:0]$2815
+ attribute \src "libresoc.v:47516.3-47524.6"
+ wire $1\wr_pick_dly$1635$next[0:0]$2818
+ attribute \src "libresoc.v:47554.3-47562.6"
+ wire $1\wr_pick_dly$1654$next[0:0]$2822
+ attribute \src "libresoc.v:47592.3-47600.6"
+ wire $1\wr_pick_dly$1670$next[0:0]$2830
+ attribute \src "libresoc.v:47601.3-47609.6"
+ wire $1\wr_pick_dly$1686$next[0:0]$2833
+ attribute \src "libresoc.v:47639.3-47647.6"
+ wire $1\wr_pick_dly$1702$next[0:0]$2841
+ attribute \src "libresoc.v:47677.3-47685.6"
+ wire $1\wr_pick_dly$1746$next[0:0]$2845
+ attribute \src "libresoc.v:47715.3-47723.6"
+ wire $1\wr_pick_dly$1762$next[0:0]$2849
+ attribute \src "libresoc.v:47724.3-47732.6"
+ wire $1\wr_pick_dly$1786$next[0:0]$2852
+ attribute \src "libresoc.v:47762.3-47770.6"
+ wire $1\wr_pick_dly$1806$next[0:0]$2856
+ attribute \src "libresoc.v:46807.3-46815.6"
+ wire $1\wr_pick_dly$989$next[0:0]$2721
+ attribute \src "libresoc.v:46798.3-46806.6"
wire $1\wr_pick_dly$next[0:0]$2718
- attribute \src "libresoc.v:41772.7-41772.25"
+ attribute \src "libresoc.v:41732.7-41732.25"
wire $1\wr_pick_dly[0:0]
- attribute \src "libresoc.v:46639.3-46659.6"
- wire $2\core_terminate_o$next[0:0]$2675
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46594.3-46614.6"
+ wire $2\core_terminate_o$next[0:0]$2681
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $2\corebusy_o[0:0]
- attribute \src "libresoc.v:46479.3-46509.6"
- wire width 2 $2\counter$next[1:0]$2656
- attribute \src "libresoc.v:47618.3-47646.6"
- wire $2\fus_cu_issue_i$13[0:0]$2823
- attribute \src "libresoc.v:47952.3-47980.6"
+ attribute \src "libresoc.v:46424.3-46454.6"
+ wire width 2 $2\counter$next[1:0]$2659
+ attribute \src "libresoc.v:47563.3-47591.6"
+ wire $2\fus_cu_issue_i$13[0:0]$2826
+ attribute \src "libresoc.v:47888.3-47916.6"
wire $2\fus_cu_issue_i$16[0:0]$2864
- attribute \src "libresoc.v:48271.3-48299.6"
+ attribute \src "libresoc.v:48207.3-48235.6"
wire $2\fus_cu_issue_i$19[0:0]$2883
- attribute \src "libresoc.v:43916.3-43944.6"
+ attribute \src "libresoc.v:43852.3-43880.6"
wire $2\fus_cu_issue_i$22[0:0]$2361
- attribute \src "libresoc.v:44090.3-44118.6"
+ attribute \src "libresoc.v:44026.3-44054.6"
wire $2\fus_cu_issue_i$25[0:0]$2375
- attribute \src "libresoc.v:44586.3-44614.6"
+ attribute \src "libresoc.v:44522.3-44550.6"
wire $2\fus_cu_issue_i$28[0:0]$2400
- attribute \src "libresoc.v:44908.3-44936.6"
+ attribute \src "libresoc.v:44844.3-44872.6"
wire $2\fus_cu_issue_i$31[0:0]$2419
- attribute \src "libresoc.v:45375.3-45403.6"
+ attribute \src "libresoc.v:45311.3-45339.6"
wire $2\fus_cu_issue_i$34[0:0]$2443
- attribute \src "libresoc.v:45813.3-45841.6"
+ attribute \src "libresoc.v:45749.3-45777.6"
wire $2\fus_cu_issue_i$37[0:0]$2466
- attribute \src "libresoc.v:47401.3-47429.6"
+ attribute \src "libresoc.v:47355.3-47383.6"
wire $2\fus_cu_issue_i[0:0]
- attribute \src "libresoc.v:47656.3-47684.6"
- wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831
- attribute \src "libresoc.v:47981.3-48009.6"
+ attribute \src "libresoc.v:47610.3-47638.6"
+ wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2837
+ attribute \src "libresoc.v:47917.3-47945.6"
wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869
- attribute \src "libresoc.v:48300.3-48328.6"
+ attribute \src "libresoc.v:48236.3-48264.6"
wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888
- attribute \src "libresoc.v:43945.3-43973.6"
+ attribute \src "libresoc.v:43881.3-43909.6"
wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366
- attribute \src "libresoc.v:44119.3-44147.6"
+ attribute \src "libresoc.v:44055.3-44083.6"
wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380
- attribute \src "libresoc.v:44615.3-44643.6"
+ attribute \src "libresoc.v:44551.3-44579.6"
wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405
- attribute \src "libresoc.v:44937.3-44965.6"
+ attribute \src "libresoc.v:44873.3-44901.6"
wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424
- attribute \src "libresoc.v:45404.3-45432.6"
+ attribute \src "libresoc.v:45340.3-45368.6"
wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448
- attribute \src "libresoc.v:45842.3-45870.6"
+ attribute \src "libresoc.v:45778.3-45806.6"
wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471
- attribute \src "libresoc.v:47448.3-47476.6"
+ attribute \src "libresoc.v:47393.3-47421.6"
wire width 4 $2\fus_cu_rdmaskn_i[3:0]
- attribute \src "libresoc.v:47325.3-47353.6"
+ attribute \src "libresoc.v:47270.3-47298.6"
wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "libresoc.v:46746.3-46774.6"
+ attribute \src "libresoc.v:46720.3-46748.6"
wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47146.3-47174.6"
+ attribute \src "libresoc.v:47100.3-47128.6"
wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "libresoc.v:47363.3-47391.6"
+ attribute \src "libresoc.v:47308.3-47336.6"
wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "libresoc.v:46698.3-46726.6"
+ attribute \src "libresoc.v:46653.3-46681.6"
wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "libresoc.v:46985.3-47013.6"
+ attribute \src "libresoc.v:46939.3-46967.6"
wire $2\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "libresoc.v:47070.3-47098.6"
+ attribute \src "libresoc.v:47015.3-47043.6"
wire $2\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "libresoc.v:47240.3-47268.6"
+ attribute \src "libresoc.v:47185.3-47213.6"
wire $2\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "libresoc.v:47278.3-47306.6"
+ attribute \src "libresoc.v:47223.3-47251.6"
wire $2\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $2\fus_oper_i_alu_alu0__oe__oe[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $2\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "libresoc.v:47193.3-47221.6"
+ attribute \src "libresoc.v:47147.3-47175.6"
wire $2\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $2\fus_oper_i_alu_alu0__rc__ok[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $2\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "libresoc.v:47108.3-47136.6"
+ attribute \src "libresoc.v:47053.3-47081.6"
wire $2\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "libresoc.v:47032.3-47060.6"
+ attribute \src "libresoc.v:46977.3-47005.6"
wire $2\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "libresoc.v:47703.3-47731.6"
+ attribute \src "libresoc.v:47648.3-47676.6"
wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "libresoc.v:47788.3-47816.6"
+ attribute \src "libresoc.v:47733.3-47761.6"
wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47826.3-47854.6"
+ attribute \src "libresoc.v:47771.3-47799.6"
wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "libresoc.v:47741.3-47769.6"
+ attribute \src "libresoc.v:47686.3-47714.6"
wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "libresoc.v:47923.3-47951.6"
+ attribute \src "libresoc.v:47859.3-47887.6"
wire $2\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "libresoc.v:47894.3-47922.6"
+ attribute \src "libresoc.v:47830.3-47858.6"
wire $2\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "libresoc.v:47533.3-47561.6"
+ attribute \src "libresoc.v:47478.3-47506.6"
wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "libresoc.v:47580.3-47608.6"
+ attribute \src "libresoc.v:47525.3-47553.6"
wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "libresoc.v:47486.3-47514.6"
+ attribute \src "libresoc.v:47440.3-47468.6"
wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "libresoc.v:44528.3-44556.6"
+ attribute \src "libresoc.v:44464.3-44492.6"
wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "libresoc.v:44177.3-44205.6"
+ attribute \src "libresoc.v:44113.3-44141.6"
wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44354.3-44382.6"
+ attribute \src "libresoc.v:44290.3-44318.6"
wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "libresoc.v:44557.3-44585.6"
+ attribute \src "libresoc.v:44493.3-44521.6"
wire width 32 $2\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "libresoc.v:44148.3-44176.6"
+ attribute \src "libresoc.v:44084.3-44112.6"
wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "libresoc.v:44296.3-44324.6"
+ attribute \src "libresoc.v:44232.3-44260.6"
wire $2\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "libresoc.v:44383.3-44411.6"
+ attribute \src "libresoc.v:44319.3-44347.6"
wire $2\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "libresoc.v:44470.3-44498.6"
+ attribute \src "libresoc.v:44406.3-44434.6"
wire $2\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "libresoc.v:44499.3-44527.6"
+ attribute \src "libresoc.v:44435.3-44463.6"
wire $2\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $2\fus_oper_i_alu_div0__oe__oe[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $2\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "libresoc.v:44441.3-44469.6"
+ attribute \src "libresoc.v:44377.3-44405.6"
wire $2\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $2\fus_oper_i_alu_div0__rc__ok[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $2\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "libresoc.v:44412.3-44440.6"
+ attribute \src "libresoc.v:44348.3-44376.6"
wire $2\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "libresoc.v:44325.3-44353.6"
+ attribute \src "libresoc.v:44261.3-44289.6"
wire $2\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "libresoc.v:43858.3-43886.6"
+ attribute \src "libresoc.v:43794.3-43822.6"
wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "libresoc.v:48358.3-48386.6"
+ attribute \src "libresoc.v:48294.3-48322.6"
wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "libresoc.v:48535.3-48563.6"
+ attribute \src "libresoc.v:48471.3-48499.6"
wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "libresoc.v:43887.3-43915.6"
+ attribute \src "libresoc.v:43823.3-43851.6"
wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "libresoc.v:48329.3-48357.6"
+ attribute \src "libresoc.v:48265.3-48293.6"
wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "libresoc.v:48477.3-48505.6"
+ attribute \src "libresoc.v:48413.3-48441.6"
wire $2\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "libresoc.v:48564.3-48592.6"
+ attribute \src "libresoc.v:48500.3-48528.6"
wire $2\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "libresoc.v:43800.3-43828.6"
+ attribute \src "libresoc.v:43736.3-43764.6"
wire $2\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "libresoc.v:43829.3-43857.6"
+ attribute \src "libresoc.v:43765.3-43793.6"
wire $2\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $2\fus_oper_i_alu_logical0__oe__oe[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $2\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "libresoc.v:43771.3-43799.6"
+ attribute \src "libresoc.v:43707.3-43735.6"
wire $2\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $2\fus_oper_i_alu_logical0__rc__ok[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $2\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "libresoc.v:48593.3-48621.6"
+ attribute \src "libresoc.v:48529.3-48557.6"
wire $2\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "libresoc.v:48506.3-48534.6"
+ attribute \src "libresoc.v:48442.3-48470.6"
wire $2\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "libresoc.v:44673.3-44701.6"
+ attribute \src "libresoc.v:44609.3-44637.6"
wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44879.3-44907.6"
+ attribute \src "libresoc.v:44815.3-44843.6"
wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "libresoc.v:44644.3-44672.6"
+ attribute \src "libresoc.v:44580.3-44608.6"
wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "libresoc.v:44821.3-44849.6"
+ attribute \src "libresoc.v:44757.3-44785.6"
wire $2\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "libresoc.v:44850.3-44878.6"
+ attribute \src "libresoc.v:44786.3-44814.6"
wire $2\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $2\fus_oper_i_alu_mul0__oe__oe[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $2\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $2\fus_oper_i_alu_mul0__rc__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $2\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "libresoc.v:44792.3-44820.6"
+ attribute \src "libresoc.v:44728.3-44756.6"
wire $2\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "libresoc.v:44995.3-45023.6"
+ attribute \src "libresoc.v:44931.3-44959.6"
wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45172.3-45200.6"
+ attribute \src "libresoc.v:45108.3-45136.6"
wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "libresoc.v:45230.3-45258.6"
+ attribute \src "libresoc.v:45166.3-45194.6"
wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "libresoc.v:45346.3-45374.6"
+ attribute \src "libresoc.v:45282.3-45310.6"
wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "libresoc.v:44966.3-44994.6"
+ attribute \src "libresoc.v:44902.3-44930.6"
wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "libresoc.v:45143.3-45171.6"
+ attribute \src "libresoc.v:45079.3-45107.6"
wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "libresoc.v:45288.3-45316.6"
+ attribute \src "libresoc.v:45224.3-45252.6"
wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "libresoc.v:45317.3-45345.6"
+ attribute \src "libresoc.v:45253.3-45281.6"
wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "libresoc.v:45201.3-45229.6"
+ attribute \src "libresoc.v:45137.3-45165.6"
wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "libresoc.v:45259.3-45287.6"
+ attribute \src "libresoc.v:45195.3-45223.6"
wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "libresoc.v:45114.3-45142.6"
+ attribute \src "libresoc.v:45050.3-45078.6"
wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "libresoc.v:44003.3-44031.6"
+ attribute \src "libresoc.v:43939.3-43967.6"
wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "libresoc.v:44032.3-44060.6"
+ attribute \src "libresoc.v:43968.3-43996.6"
wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "libresoc.v:43974.3-44002.6"
+ attribute \src "libresoc.v:43910.3-43938.6"
wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "libresoc.v:44061.3-44089.6"
+ attribute \src "libresoc.v:43997.3-44025.6"
wire $2\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "libresoc.v:48126.3-48154.6"
+ attribute \src "libresoc.v:48062.3-48090.6"
wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "libresoc.v:48039.3-48067.6"
+ attribute \src "libresoc.v:47975.3-48003.6"
wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "libresoc.v:48068.3-48096.6"
+ attribute \src "libresoc.v:48004.3-48032.6"
wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "libresoc.v:48010.3-48038.6"
+ attribute \src "libresoc.v:47946.3-47974.6"
wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "libresoc.v:48155.3-48183.6"
+ attribute \src "libresoc.v:48091.3-48119.6"
wire $2\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "libresoc.v:48242.3-48270.6"
+ attribute \src "libresoc.v:48178.3-48206.6"
wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "libresoc.v:48097.3-48125.6"
+ attribute \src "libresoc.v:48033.3-48061.6"
wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "libresoc.v:48213.3-48241.6"
+ attribute \src "libresoc.v:48149.3-48177.6"
wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "libresoc.v:48184.3-48212.6"
+ attribute \src "libresoc.v:48120.3-48148.6"
wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "libresoc.v:45697.3-45725.6"
+ attribute \src "libresoc.v:45633.3-45661.6"
wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "libresoc.v:45668.3-45696.6"
+ attribute \src "libresoc.v:45604.3-45632.6"
wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "libresoc.v:45462.3-45490.6"
+ attribute \src "libresoc.v:45398.3-45426.6"
wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45784.3-45812.6"
+ attribute \src "libresoc.v:45720.3-45748.6"
wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "libresoc.v:45433.3-45461.6"
+ attribute \src "libresoc.v:45369.3-45397.6"
wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "libresoc.v:45610.3-45638.6"
+ attribute \src "libresoc.v:45546.3-45574.6"
wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "libresoc.v:45639.3-45667.6"
+ attribute \src "libresoc.v:45575.3-45603.6"
wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "libresoc.v:45755.3-45783.6"
+ attribute \src "libresoc.v:45691.3-45719.6"
wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "libresoc.v:45726.3-45754.6"
+ attribute \src "libresoc.v:45662.3-45690.6"
wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "libresoc.v:45521.3-45549.6"
+ attribute \src "libresoc.v:45457.3-45485.6"
wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "libresoc.v:46639.3-46659.6"
- wire $3\core_terminate_o$next[0:0]$2676
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46594.3-46614.6"
+ wire $3\core_terminate_o$next[0:0]$2682
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $3\corebusy_o[0:0]
- attribute \src "libresoc.v:46479.3-46509.6"
- wire width 2 $3\counter$next[1:0]$2657
- attribute \src "libresoc.v:47618.3-47646.6"
- wire $3\fus_cu_issue_i$13[0:0]$2824
- attribute \src "libresoc.v:47952.3-47980.6"
+ attribute \src "libresoc.v:46424.3-46454.6"
+ wire width 2 $3\counter$next[1:0]$2660
+ attribute \src "libresoc.v:47563.3-47591.6"
+ wire $3\fus_cu_issue_i$13[0:0]$2827
+ attribute \src "libresoc.v:47888.3-47916.6"
wire $3\fus_cu_issue_i$16[0:0]$2865
- attribute \src "libresoc.v:48271.3-48299.6"
+ attribute \src "libresoc.v:48207.3-48235.6"
wire $3\fus_cu_issue_i$19[0:0]$2884
- attribute \src "libresoc.v:43916.3-43944.6"
+ attribute \src "libresoc.v:43852.3-43880.6"
wire $3\fus_cu_issue_i$22[0:0]$2362
- attribute \src "libresoc.v:44090.3-44118.6"
+ attribute \src "libresoc.v:44026.3-44054.6"
wire $3\fus_cu_issue_i$25[0:0]$2376
- attribute \src "libresoc.v:44586.3-44614.6"
+ attribute \src "libresoc.v:44522.3-44550.6"
wire $3\fus_cu_issue_i$28[0:0]$2401
- attribute \src "libresoc.v:44908.3-44936.6"
+ attribute \src "libresoc.v:44844.3-44872.6"
wire $3\fus_cu_issue_i$31[0:0]$2420
- attribute \src "libresoc.v:45375.3-45403.6"
+ attribute \src "libresoc.v:45311.3-45339.6"
wire $3\fus_cu_issue_i$34[0:0]$2444
- attribute \src "libresoc.v:45813.3-45841.6"
+ attribute \src "libresoc.v:45749.3-45777.6"
wire $3\fus_cu_issue_i$37[0:0]$2467
- attribute \src "libresoc.v:47401.3-47429.6"
+ attribute \src "libresoc.v:47355.3-47383.6"
wire $3\fus_cu_issue_i[0:0]
- attribute \src "libresoc.v:47656.3-47684.6"
- wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832
- attribute \src "libresoc.v:47981.3-48009.6"
+ attribute \src "libresoc.v:47610.3-47638.6"
+ wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2838
+ attribute \src "libresoc.v:47917.3-47945.6"
wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870
- attribute \src "libresoc.v:48300.3-48328.6"
+ attribute \src "libresoc.v:48236.3-48264.6"
wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889
- attribute \src "libresoc.v:43945.3-43973.6"
+ attribute \src "libresoc.v:43881.3-43909.6"
wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367
- attribute \src "libresoc.v:44119.3-44147.6"
+ attribute \src "libresoc.v:44055.3-44083.6"
wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381
- attribute \src "libresoc.v:44615.3-44643.6"
+ attribute \src "libresoc.v:44551.3-44579.6"
wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406
- attribute \src "libresoc.v:44937.3-44965.6"
+ attribute \src "libresoc.v:44873.3-44901.6"
wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425
- attribute \src "libresoc.v:45404.3-45432.6"
+ attribute \src "libresoc.v:45340.3-45368.6"
wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449
- attribute \src "libresoc.v:45842.3-45870.6"
+ attribute \src "libresoc.v:45778.3-45806.6"
wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472
- attribute \src "libresoc.v:47448.3-47476.6"
+ attribute \src "libresoc.v:47393.3-47421.6"
wire width 4 $3\fus_cu_rdmaskn_i[3:0]
- attribute \src "libresoc.v:47325.3-47353.6"
+ attribute \src "libresoc.v:47270.3-47298.6"
wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "libresoc.v:46746.3-46774.6"
+ attribute \src "libresoc.v:46720.3-46748.6"
wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0]
- attribute \src "libresoc.v:46813.3-46842.6"
+ attribute \src "libresoc.v:46768.3-46797.6"
wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47146.3-47174.6"
+ attribute \src "libresoc.v:47100.3-47128.6"
wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "libresoc.v:47363.3-47391.6"
+ attribute \src "libresoc.v:47308.3-47336.6"
wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "libresoc.v:46698.3-46726.6"
+ attribute \src "libresoc.v:46653.3-46681.6"
wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "libresoc.v:46985.3-47013.6"
+ attribute \src "libresoc.v:46939.3-46967.6"
wire $3\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "libresoc.v:47070.3-47098.6"
+ attribute \src "libresoc.v:47015.3-47043.6"
wire $3\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "libresoc.v:47240.3-47268.6"
+ attribute \src "libresoc.v:47185.3-47213.6"
wire $3\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "libresoc.v:47278.3-47306.6"
+ attribute \src "libresoc.v:47223.3-47251.6"
wire $3\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $3\fus_oper_i_alu_alu0__oe__oe[0:0]
- attribute \src "libresoc.v:46928.3-46957.6"
+ attribute \src "libresoc.v:46882.3-46911.6"
wire $3\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "libresoc.v:47193.3-47221.6"
+ attribute \src "libresoc.v:47147.3-47175.6"
wire $3\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $3\fus_oper_i_alu_alu0__rc__ok[0:0]
- attribute \src "libresoc.v:46880.3-46909.6"
+ attribute \src "libresoc.v:46825.3-46854.6"
wire $3\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "libresoc.v:47108.3-47136.6"
+ attribute \src "libresoc.v:47053.3-47081.6"
wire $3\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "libresoc.v:47032.3-47060.6"
+ attribute \src "libresoc.v:46977.3-47005.6"
wire $3\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "libresoc.v:47703.3-47731.6"
+ attribute \src "libresoc.v:47648.3-47676.6"
wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "libresoc.v:47788.3-47816.6"
+ attribute \src "libresoc.v:47733.3-47761.6"
wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0]
- attribute \src "libresoc.v:47864.3-47893.6"
+ attribute \src "libresoc.v:47800.3-47829.6"
wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47826.3-47854.6"
+ attribute \src "libresoc.v:47771.3-47799.6"
wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "libresoc.v:47741.3-47769.6"
+ attribute \src "libresoc.v:47686.3-47714.6"
wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "libresoc.v:47923.3-47951.6"
+ attribute \src "libresoc.v:47859.3-47887.6"
wire $3\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "libresoc.v:47894.3-47922.6"
+ attribute \src "libresoc.v:47830.3-47858.6"
wire $3\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "libresoc.v:47533.3-47561.6"
+ attribute \src "libresoc.v:47478.3-47506.6"
wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "libresoc.v:47580.3-47608.6"
+ attribute \src "libresoc.v:47525.3-47553.6"
wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "libresoc.v:47486.3-47514.6"
+ attribute \src "libresoc.v:47440.3-47468.6"
wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "libresoc.v:44528.3-44556.6"
+ attribute \src "libresoc.v:44464.3-44492.6"
wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "libresoc.v:44177.3-44205.6"
+ attribute \src "libresoc.v:44113.3-44141.6"
wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0]
- attribute \src "libresoc.v:44206.3-44235.6"
+ attribute \src "libresoc.v:44142.3-44171.6"
wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44354.3-44382.6"
+ attribute \src "libresoc.v:44290.3-44318.6"
wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "libresoc.v:44557.3-44585.6"
+ attribute \src "libresoc.v:44493.3-44521.6"
wire width 32 $3\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "libresoc.v:44148.3-44176.6"
+ attribute \src "libresoc.v:44084.3-44112.6"
wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "libresoc.v:44296.3-44324.6"
+ attribute \src "libresoc.v:44232.3-44260.6"
wire $3\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "libresoc.v:44383.3-44411.6"
+ attribute \src "libresoc.v:44319.3-44347.6"
wire $3\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "libresoc.v:44470.3-44498.6"
+ attribute \src "libresoc.v:44406.3-44434.6"
wire $3\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "libresoc.v:44499.3-44527.6"
+ attribute \src "libresoc.v:44435.3-44463.6"
wire $3\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $3\fus_oper_i_alu_div0__oe__oe[0:0]
- attribute \src "libresoc.v:44266.3-44295.6"
+ attribute \src "libresoc.v:44202.3-44231.6"
wire $3\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "libresoc.v:44441.3-44469.6"
+ attribute \src "libresoc.v:44377.3-44405.6"
wire $3\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $3\fus_oper_i_alu_div0__rc__ok[0:0]
- attribute \src "libresoc.v:44236.3-44265.6"
+ attribute \src "libresoc.v:44172.3-44201.6"
wire $3\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "libresoc.v:44412.3-44440.6"
+ attribute \src "libresoc.v:44348.3-44376.6"
wire $3\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "libresoc.v:44325.3-44353.6"
+ attribute \src "libresoc.v:44261.3-44289.6"
wire $3\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "libresoc.v:43858.3-43886.6"
+ attribute \src "libresoc.v:43794.3-43822.6"
wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "libresoc.v:48358.3-48386.6"
+ attribute \src "libresoc.v:48294.3-48322.6"
wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0]
- attribute \src "libresoc.v:48387.3-48416.6"
+ attribute \src "libresoc.v:48323.3-48352.6"
wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "libresoc.v:48535.3-48563.6"
+ attribute \src "libresoc.v:48471.3-48499.6"
wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "libresoc.v:43887.3-43915.6"
+ attribute \src "libresoc.v:43823.3-43851.6"
wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "libresoc.v:48329.3-48357.6"
+ attribute \src "libresoc.v:48265.3-48293.6"
wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "libresoc.v:48477.3-48505.6"
+ attribute \src "libresoc.v:48413.3-48441.6"
wire $3\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "libresoc.v:48564.3-48592.6"
+ attribute \src "libresoc.v:48500.3-48528.6"
wire $3\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "libresoc.v:43800.3-43828.6"
+ attribute \src "libresoc.v:43736.3-43764.6"
wire $3\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "libresoc.v:43829.3-43857.6"
+ attribute \src "libresoc.v:43765.3-43793.6"
wire $3\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $3\fus_oper_i_alu_logical0__oe__oe[0:0]
- attribute \src "libresoc.v:48447.3-48476.6"
+ attribute \src "libresoc.v:48383.3-48412.6"
wire $3\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "libresoc.v:43771.3-43799.6"
+ attribute \src "libresoc.v:43707.3-43735.6"
wire $3\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $3\fus_oper_i_alu_logical0__rc__ok[0:0]
- attribute \src "libresoc.v:48417.3-48446.6"
+ attribute \src "libresoc.v:48353.3-48382.6"
wire $3\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "libresoc.v:48593.3-48621.6"
+ attribute \src "libresoc.v:48529.3-48557.6"
wire $3\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "libresoc.v:48506.3-48534.6"
+ attribute \src "libresoc.v:48442.3-48470.6"
wire $3\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "libresoc.v:44673.3-44701.6"
+ attribute \src "libresoc.v:44609.3-44637.6"
wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0]
- attribute \src "libresoc.v:44702.3-44731.6"
+ attribute \src "libresoc.v:44638.3-44667.6"
wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44879.3-44907.6"
+ attribute \src "libresoc.v:44815.3-44843.6"
wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "libresoc.v:44644.3-44672.6"
+ attribute \src "libresoc.v:44580.3-44608.6"
wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "libresoc.v:44821.3-44849.6"
+ attribute \src "libresoc.v:44757.3-44785.6"
wire $3\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "libresoc.v:44850.3-44878.6"
+ attribute \src "libresoc.v:44786.3-44814.6"
wire $3\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $3\fus_oper_i_alu_mul0__oe__oe[0:0]
- attribute \src "libresoc.v:44762.3-44791.6"
+ attribute \src "libresoc.v:44698.3-44727.6"
wire $3\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $3\fus_oper_i_alu_mul0__rc__ok[0:0]
- attribute \src "libresoc.v:44732.3-44761.6"
+ attribute \src "libresoc.v:44668.3-44697.6"
wire $3\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "libresoc.v:44792.3-44820.6"
+ attribute \src "libresoc.v:44728.3-44756.6"
wire $3\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "libresoc.v:44995.3-45023.6"
+ attribute \src "libresoc.v:44931.3-44959.6"
wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
- attribute \src "libresoc.v:45024.3-45053.6"
+ attribute \src "libresoc.v:44960.3-44989.6"
wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45172.3-45200.6"
+ attribute \src "libresoc.v:45108.3-45136.6"
wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "libresoc.v:45230.3-45258.6"
+ attribute \src "libresoc.v:45166.3-45194.6"
wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "libresoc.v:45346.3-45374.6"
+ attribute \src "libresoc.v:45282.3-45310.6"
wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "libresoc.v:44966.3-44994.6"
+ attribute \src "libresoc.v:44902.3-44930.6"
wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "libresoc.v:45143.3-45171.6"
+ attribute \src "libresoc.v:45079.3-45107.6"
wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "libresoc.v:45288.3-45316.6"
+ attribute \src "libresoc.v:45224.3-45252.6"
wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "libresoc.v:45317.3-45345.6"
+ attribute \src "libresoc.v:45253.3-45281.6"
wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
- attribute \src "libresoc.v:45084.3-45113.6"
+ attribute \src "libresoc.v:45020.3-45049.6"
wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "libresoc.v:45201.3-45229.6"
+ attribute \src "libresoc.v:45137.3-45165.6"
wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "libresoc.v:45259.3-45287.6"
+ attribute \src "libresoc.v:45195.3-45223.6"
wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
- attribute \src "libresoc.v:45054.3-45083.6"
+ attribute \src "libresoc.v:44990.3-45019.6"
wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "libresoc.v:45114.3-45142.6"
+ attribute \src "libresoc.v:45050.3-45078.6"
wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "libresoc.v:44003.3-44031.6"
+ attribute \src "libresoc.v:43939.3-43967.6"
wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "libresoc.v:44032.3-44060.6"
+ attribute \src "libresoc.v:43968.3-43996.6"
wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "libresoc.v:43974.3-44002.6"
+ attribute \src "libresoc.v:43910.3-43938.6"
wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "libresoc.v:44061.3-44089.6"
+ attribute \src "libresoc.v:43997.3-44025.6"
wire $3\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "libresoc.v:48126.3-48154.6"
+ attribute \src "libresoc.v:48062.3-48090.6"
wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "libresoc.v:48039.3-48067.6"
+ attribute \src "libresoc.v:47975.3-48003.6"
wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "libresoc.v:48068.3-48096.6"
+ attribute \src "libresoc.v:48004.3-48032.6"
wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "libresoc.v:48010.3-48038.6"
+ attribute \src "libresoc.v:47946.3-47974.6"
wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "libresoc.v:48155.3-48183.6"
+ attribute \src "libresoc.v:48091.3-48119.6"
wire $3\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "libresoc.v:48242.3-48270.6"
+ attribute \src "libresoc.v:48178.3-48206.6"
wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "libresoc.v:48097.3-48125.6"
+ attribute \src "libresoc.v:48033.3-48061.6"
wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "libresoc.v:48213.3-48241.6"
+ attribute \src "libresoc.v:48149.3-48177.6"
wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "libresoc.v:48184.3-48212.6"
+ attribute \src "libresoc.v:48120.3-48148.6"
wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "libresoc.v:45697.3-45725.6"
+ attribute \src "libresoc.v:45633.3-45661.6"
wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "libresoc.v:45668.3-45696.6"
+ attribute \src "libresoc.v:45604.3-45632.6"
wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "libresoc.v:45462.3-45490.6"
+ attribute \src "libresoc.v:45398.3-45426.6"
wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
- attribute \src "libresoc.v:45491.3-45520.6"
+ attribute \src "libresoc.v:45427.3-45456.6"
wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45784.3-45812.6"
+ attribute \src "libresoc.v:45720.3-45748.6"
wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "libresoc.v:45433.3-45461.6"
+ attribute \src "libresoc.v:45369.3-45397.6"
wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "libresoc.v:45610.3-45638.6"
+ attribute \src "libresoc.v:45546.3-45574.6"
wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "libresoc.v:45639.3-45667.6"
+ attribute \src "libresoc.v:45575.3-45603.6"
wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "libresoc.v:45755.3-45783.6"
+ attribute \src "libresoc.v:45691.3-45719.6"
wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0]
- attribute \src "libresoc.v:45580.3-45609.6"
+ attribute \src "libresoc.v:45516.3-45545.6"
wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0]
- attribute \src "libresoc.v:45550.3-45579.6"
+ attribute \src "libresoc.v:45486.3-45515.6"
wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "libresoc.v:45726.3-45754.6"
+ attribute \src "libresoc.v:45662.3-45690.6"
wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "libresoc.v:45521.3-45549.6"
+ attribute \src "libresoc.v:45457.3-45485.6"
wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $4\corebusy_o[0:0]
- attribute \src "libresoc.v:46479.3-46509.6"
- wire width 2 $4\counter$next[1:0]$2658
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46424.3-46454.6"
+ wire width 2 $4\counter$next[1:0]$2661
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $5\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $6\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $7\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $8\corebusy_o[0:0]
- attribute \src "libresoc.v:46529.3-46619.6"
+ attribute \src "libresoc.v:46484.3-46574.6"
wire $9\corebusy_o[0:0]
- attribute \src "libresoc.v:42151.20-42151.122"
- wire $and$libresoc.v:42151$1506_Y
- attribute \src "libresoc.v:42153.20-42153.122"
- wire $and$libresoc.v:42153$1508_Y
- attribute \src "libresoc.v:42154.20-42154.126"
- wire $and$libresoc.v:42154$1509_Y
- attribute \src "libresoc.v:42156.20-42156.110"
- wire $and$libresoc.v:42156$1511_Y
- attribute \src "libresoc.v:42157.20-42157.123"
- wire $and$libresoc.v:42157$1512_Y
- attribute \src "libresoc.v:42159.20-42159.122"
- wire $and$libresoc.v:42159$1514_Y
- attribute \src "libresoc.v:42160.20-42160.126"
- wire $and$libresoc.v:42160$1515_Y
- attribute \src "libresoc.v:42162.20-42162.110"
- wire $and$libresoc.v:42162$1517_Y
- attribute \src "libresoc.v:42163.20-42163.123"
- wire $and$libresoc.v:42163$1518_Y
- attribute \src "libresoc.v:42165.20-42165.123"
- wire $and$libresoc.v:42165$1520_Y
- attribute \src "libresoc.v:42166.20-42166.126"
- wire $and$libresoc.v:42166$1521_Y
- attribute \src "libresoc.v:42168.20-42168.110"
- wire $and$libresoc.v:42168$1523_Y
- attribute \src "libresoc.v:42169.20-42169.123"
- wire $and$libresoc.v:42169$1524_Y
- attribute \src "libresoc.v:42171.20-42171.123"
- wire $and$libresoc.v:42171$1526_Y
- attribute \src "libresoc.v:42172.20-42172.126"
- wire $and$libresoc.v:42172$1527_Y
- attribute \src "libresoc.v:42174.20-42174.110"
- wire $and$libresoc.v:42174$1529_Y
- attribute \src "libresoc.v:42175.20-42175.123"
- wire $and$libresoc.v:42175$1530_Y
- attribute \src "libresoc.v:42177.20-42177.123"
- wire $and$libresoc.v:42177$1532_Y
- attribute \src "libresoc.v:42178.20-42178.126"
- wire $and$libresoc.v:42178$1533_Y
- attribute \src "libresoc.v:42180.20-42180.110"
- wire $and$libresoc.v:42180$1535_Y
- attribute \src "libresoc.v:42181.20-42181.123"
- wire $and$libresoc.v:42181$1536_Y
- attribute \src "libresoc.v:42183.20-42183.123"
- wire $and$libresoc.v:42183$1538_Y
- attribute \src "libresoc.v:42184.20-42184.126"
- wire $and$libresoc.v:42184$1539_Y
- attribute \src "libresoc.v:42186.20-42186.110"
- wire $and$libresoc.v:42186$1541_Y
+ attribute \src "libresoc.v:42112.20-42112.122"
+ wire $and$libresoc.v:42112$1507_Y
+ attribute \src "libresoc.v:42113.20-42113.126"
+ wire $and$libresoc.v:42113$1508_Y
+ attribute \src "libresoc.v:42115.20-42115.110"
+ wire $and$libresoc.v:42115$1510_Y
+ attribute \src "libresoc.v:42116.20-42116.123"
+ wire $and$libresoc.v:42116$1511_Y
+ attribute \src "libresoc.v:42118.20-42118.122"
+ wire $and$libresoc.v:42118$1513_Y
+ attribute \src "libresoc.v:42119.20-42119.126"
+ wire $and$libresoc.v:42119$1514_Y
+ attribute \src "libresoc.v:42121.20-42121.110"
+ wire $and$libresoc.v:42121$1516_Y
+ attribute \src "libresoc.v:42122.20-42122.123"
+ wire $and$libresoc.v:42122$1517_Y
+ attribute \src "libresoc.v:42124.20-42124.123"
+ wire $and$libresoc.v:42124$1519_Y
+ attribute \src "libresoc.v:42125.20-42125.126"
+ wire $and$libresoc.v:42125$1520_Y
+ attribute \src "libresoc.v:42127.20-42127.110"
+ wire $and$libresoc.v:42127$1522_Y
+ attribute \src "libresoc.v:42128.20-42128.123"
+ wire $and$libresoc.v:42128$1523_Y
+ attribute \src "libresoc.v:42130.20-42130.123"
+ wire $and$libresoc.v:42130$1525_Y
+ attribute \src "libresoc.v:42131.20-42131.126"
+ wire $and$libresoc.v:42131$1526_Y
+ attribute \src "libresoc.v:42133.20-42133.110"
+ wire $and$libresoc.v:42133$1528_Y
+ attribute \src "libresoc.v:42134.20-42134.123"
+ wire $and$libresoc.v:42134$1529_Y
+ attribute \src "libresoc.v:42136.20-42136.123"
+ wire $and$libresoc.v:42136$1531_Y
+ attribute \src "libresoc.v:42137.20-42137.126"
+ wire $and$libresoc.v:42137$1532_Y
+ attribute \src "libresoc.v:42139.20-42139.110"
+ wire $and$libresoc.v:42139$1534_Y
+ attribute \src "libresoc.v:42140.20-42140.123"
+ wire $and$libresoc.v:42140$1535_Y
+ attribute \src "libresoc.v:42142.20-42142.123"
+ wire $and$libresoc.v:42142$1537_Y
+ attribute \src "libresoc.v:42143.20-42143.126"
+ wire $and$libresoc.v:42143$1538_Y
+ attribute \src "libresoc.v:42145.20-42145.110"
+ wire $and$libresoc.v:42145$1540_Y
+ attribute \src "libresoc.v:42146.20-42146.123"
+ wire $and$libresoc.v:42146$1541_Y
+ attribute \src "libresoc.v:42148.20-42148.113"
+ wire $and$libresoc.v:42148$1543_Y
+ attribute \src "libresoc.v:42149.20-42149.126"
+ wire $and$libresoc.v:42149$1544_Y
+ attribute \src "libresoc.v:42151.20-42151.110"
+ wire $and$libresoc.v:42151$1546_Y
+ attribute \src "libresoc.v:42152.20-42152.123"
+ wire $and$libresoc.v:42152$1547_Y
+ attribute \src "libresoc.v:42154.20-42154.114"
+ wire $and$libresoc.v:42154$1549_Y
+ attribute \src "libresoc.v:42155.20-42155.126"
+ wire $and$libresoc.v:42155$1550_Y
+ attribute \src "libresoc.v:42157.20-42157.110"
+ wire $and$libresoc.v:42157$1552_Y
+ attribute \src "libresoc.v:42158.20-42158.123"
+ wire $and$libresoc.v:42158$1553_Y
attribute \src "libresoc.v:42187.20-42187.123"
- wire $and$libresoc.v:42187$1542_Y
- attribute \src "libresoc.v:42189.20-42189.113"
- wire $and$libresoc.v:42189$1544_Y
- attribute \src "libresoc.v:42190.20-42190.126"
- wire $and$libresoc.v:42190$1545_Y
- attribute \src "libresoc.v:42192.20-42192.110"
- wire $and$libresoc.v:42192$1547_Y
- attribute \src "libresoc.v:42193.20-42193.123"
- wire $and$libresoc.v:42193$1548_Y
- attribute \src "libresoc.v:42195.20-42195.114"
- wire $and$libresoc.v:42195$1550_Y
- attribute \src "libresoc.v:42196.20-42196.126"
- wire $and$libresoc.v:42196$1551_Y
- attribute \src "libresoc.v:42198.20-42198.110"
- wire $and$libresoc.v:42198$1553_Y
- attribute \src "libresoc.v:42199.20-42199.123"
- wire $and$libresoc.v:42199$1554_Y
- attribute \src "libresoc.v:42228.20-42228.123"
- wire $and$libresoc.v:42228$1583_Y
- attribute \src "libresoc.v:42229.20-42229.128"
- wire $and$libresoc.v:42229$1584_Y
- attribute \src "libresoc.v:42230.20-42230.133"
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- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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wire \$1213
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wire \$1215
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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wire \$1233
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1235
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wire \$1237
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wire \$1239
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1241
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1243
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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wire width 256 \$1261
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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wire width 256 \$1380
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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wire \$1386
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wire \$1388
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wire \$1390
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1398
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1430
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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wire \$1450
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wire \$1452
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wire \$1454
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1512
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- wire width 3 \$1520
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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wire \$1534
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1536
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1538
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1540
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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wire \$1556
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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wire \$1572
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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wire \$1588
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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wire \$1622
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1624
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1626
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1628
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1630
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1639
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1657
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1673
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1689
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1705
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- wire \$1707
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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wire width 64 \$1717
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 64 \$1719
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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wire width 3 \$1725
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 3 \$1727
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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wire \$1733
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire \$1735
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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wire \$1737
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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wire \$1739
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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wire \$1741
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- wire \$1743
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
- wire \$1746
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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wire \$1757
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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wire \$1781
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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wire \$1801
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- wire \$1803
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$1809
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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wire \$181
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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wire width 14 \$182
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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wire \$185
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$186
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$189
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$190
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$193
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$194
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$197
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$198
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$201
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$202
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$205
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$206
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$209
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$210
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$213
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$214
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire \$217
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
wire width 14 \$218
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
wire \$221
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
wire width 3 \$223
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
wire width 3 \$224
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
wire \$226
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 4 \$228
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$229
wire \$245
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
wire \$247
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 6 \$250
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 3 \$252
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 4 \$254
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 3 \$256
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$257
wire \$265
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
wire \$267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 6 \$270
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$271
wire \$295
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
wire \$297
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 3 \$300
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$301
wire \$309
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
wire \$311
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 3 \$314
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$315
wire \$323
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
wire \$325
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 5 \$328
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
wire \$329
wire \$345
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
wire \$347
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
wire width 3 \$350
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$352
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$354
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$356
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$358
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$360
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$362
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$364
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$366
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$368
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$370
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$372
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$374
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$376
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$378
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$380
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$382
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$384
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$386
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$388
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$390
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$392
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$394
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$396
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$398
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$400
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$402
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$404
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$406
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$408
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$410
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$412
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$414
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$416
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$418
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$420
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$422
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$424
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$426
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$428
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$430
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$432
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$434
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$436
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$438
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$440
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$442
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$444
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$446
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$448
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
wire \$450
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$452
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
wire \$454
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
wire \$456
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
wire width 7 \$458
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ wire \$460
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ wire \$462
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ wire \$464
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ wire \$466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ wire \$468
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ wire width 7 \$470
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ wire \$472
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ wire \$474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ wire \$476
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ wire \$480
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
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+ wire \$484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ wire \$492
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
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+ wire \$496
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ wire \$500
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
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+ wire \$520
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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+ wire width 7 \$542
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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+ wire \$548
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wire \$647
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wire \$653
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wire \$657
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wire \$661
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wire \$663
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wire \$665
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wire \$667
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wire \$669
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wire \$673
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wire \$675
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wire \$677
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wire \$681
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wire \$689
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
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wire \$691
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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wire \$695
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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wire \$699
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wire \$701
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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wire \$710
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire \$712
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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wire \$725
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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wire \$727
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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wire \$729
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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wire \$731
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- wire width 2 \$735
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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wire \$737
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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wire \$739
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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wire \$741
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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wire \$743
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- wire \$745
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$993
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417"
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wire width 7 \addr_en
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wire width 256 \addr_en_CR_cr_a_branch0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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wire width 256 \addr_en_CR_cr_a_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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wire width 256 \addr_en_CR_cr_b_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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wire width 256 \addr_en_CR_cr_c_cr0_0
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wire width 8 \addr_en_CR_full_cr_cr0_0
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wire width 3 \addr_en_FAST_fast1_branch0_0
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+ wire width 3 \addr_en_FAST_fast1_branch0_3
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wire width 3 \addr_en_FAST_fast1_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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wire width 3 \addr_en_FAST_fast1_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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- wire width 7 \addr_en_INT_ra_alu0_0
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- wire width 7 \addr_en_INT_ra_cr0_1
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- wire width 7 \addr_en_INT_ra_logical0_3
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- wire width 7 \addr_en_INT_rb_ldst0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
- wire width 7 \addr_en_INT_rb_logical0_3
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
- wire width 7 \addr_en_INT_rb_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
- wire width 7 \addr_en_INT_rc_ldst0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
- wire width 7 \addr_en_INT_rc_shiftrot0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 3 \addr_en_FAST_fast1_trap0_4
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+ wire width 7 \addr_en_INT_rabc_alu0_0
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+ wire width 7 \addr_en_INT_rabc_alu0_10
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+ wire width 7 \addr_en_INT_rabc_cr0_1
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+ wire width 7 \addr_en_INT_rabc_cr0_11
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+ wire width 7 \addr_en_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+ wire width 7 \addr_en_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire width 10 \addr_en_SPR_spr1_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire width 2 \addr_en_XER_xer_ca_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire width 2 \addr_en_XER_xer_ca_shiftrot0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire width 2 \addr_en_XER_xer_ca_spr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire width 3 \addr_en_XER_xer_ov_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_div0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_logical0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_mul0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_shiftrot0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
wire \addr_en_XER_xer_so_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
wire input 67 \bigendian_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 8 \cia__data_o
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 10 input 24 \core_spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
wire output 14 \core_terminate_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
wire \core_terminate_o$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
wire width 3 input 27 \core_xer_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
wire output 2 \corebusy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 97 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192"
wire width 2 \counter
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192"
wire width 2 \counter$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \cr_data_i
wire width 64 output 76 \dmi__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 75 \dmi__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_a_branch0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_a_branch0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_a_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_a_cr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_b_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_b_cr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_c_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_cr_c_cr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_full_cr_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_CR_full_cr_cr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_branch0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_FAST_fast1_branch0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_FAST_fast1_branch0_3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_spr0_2$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_FAST_fast1_trap0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_FAST_fast2_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_FAST_fast2_branch0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_FAST_fast2_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_FAST_fast2_trap0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_alu0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_cr0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_div0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_div0_5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_ldst0_8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_ldst0_8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_logical0_3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_mul0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_mul0_6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_shiftrot0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_shiftrot0_7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_spr0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_spr0_4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_ra_trap0_2$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_alu0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_cr0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_div0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_div0_4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_ldst0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_ldst0_7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_logical0_3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_mul0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_mul0_5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_shiftrot0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_shiftrot0_6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rb_trap0_2$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rc_ldst0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rc_ldst0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rc_shiftrot0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
- wire \dp_INT_rc_shiftrot0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_FAST_fast1_trap0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_FAST_fast1_trap0_4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_alu0_0$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_alu0_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_alu0_10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_cr0_1$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_cr0_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_cr0_11$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_div0_15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_div0_15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_div0_4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_18$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_ldst0_9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_logical0_13$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_logical0_3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_mul0_16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_mul0_5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_shiftrot0_8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_spr0_14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_trap0_12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
+ wire \dp_INT_rabc_trap0_2$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_SPR_spr1_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_SPR_spr1_spr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_alu0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_shiftrot0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_shiftrot0_2$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_spr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ca_spr0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ov_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_ov_spr0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_alu0_0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_div0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_div0_3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_logical0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_logical0_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_mul0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_mul0_4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_shiftrot0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_shiftrot0_5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_spr0_2$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \ea_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_alu0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_branch0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_div0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_ldst0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_logical0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_mul0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_shiftrot0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_spr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
wire \en_trap0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \fast_dest1__addr
wire width 64 \fast_src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \fast_src1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 3 \fast_src2__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \fast_src2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \fast_src2__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177"
wire width 10 \fu_enable
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 32 output 78 \full_rd2__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__go_i$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 6 \fus_cu_rd__go_i$50
+ wire width 3 \fus_cu_rd__go_i$50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__go_i$53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 \fus_cu_rd__go_i$56
+ wire width 5 \fus_cu_rd__go_i$56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 5 \fus_cu_rd__go_i$59
+ wire width 3 \fus_cu_rd__go_i$59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 \fus_cu_rd__go_i$62
+ wire width 6 \fus_cu_rd__go_i$66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__go_i$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__rel_o$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 6 \fus_cu_rd__rel_o$49
+ wire width 3 \fus_cu_rd__rel_o$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__rel_o$52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 \fus_cu_rd__rel_o$55
+ wire width 5 \fus_cu_rd__rel_o$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 5 \fus_cu_rd__rel_o$58
+ wire width 3 \fus_cu_rd__rel_o$58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 \fus_cu_rd__rel_o$61
+ wire width 6 \fus_cu_rd__rel_o$65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 \fus_cu_rd__rel_o$81
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 \fus_src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$42
+ wire width 64 \fus_src1_i$62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$45
+ wire width 64 \fus_src1_i$63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$48
+ wire width 64 \fus_src1_i$64
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$51
+ wire width 64 \fus_src1_i$67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$54
+ wire width 64 \fus_src1_i$68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$57
+ wire width 64 \fus_src1_i$69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$60
+ wire width 64 \fus_src1_i$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src1_i$63
+ wire width 64 \fus_src1_i$71
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 \fus_src1_i$86
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 \fus_src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$64
+ wire width 64 \fus_src2_i$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$65
+ wire width 64 \fus_src2_i$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$66
+ wire width 64 \fus_src2_i$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$67
+ wire width 64 \fus_src2_i$51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$68
+ wire width 64 \fus_src2_i$54
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$69
+ wire width 64 \fus_src2_i$57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src2_i$70
+ wire width 64 \fus_src2_i$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 \fus_src2_i$89
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 \fus_src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 \fus_src3_i$71
+ wire width 64 \fus_src3_i$61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire \fus_src3_i$72
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \int_dest1__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 \int_src1__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \int_src1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \int_src1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 \int_src2__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \int_src2__data_o
+ wire width 5 \int_src__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \int_src2__ren
+ wire width 64 \int_src__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 \int_src3__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \int_src3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \int_src3__ren
+ wire \int_src__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 81 \issue__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 82 \issue__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 85 \issue__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
wire input 72 \issue_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
wire input 71 \ivalid_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 15 \msr__data_o
wire width 3 input 13 \msr__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_cr_a_branch0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_cr_a_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_cr_b_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_cr_c_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_full_cr_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_FAST_fast1_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_FAST_fast1_branch0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_FAST_fast1_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_FAST_fast1_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_FAST_fast2_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_FAST_fast2_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_div0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_ldst0_8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_mul0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_shiftrot0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_spr0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_ra_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_div0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_ldst0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_mul0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_shiftrot0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rb_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rc_ldst0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
- wire \pick_INT_rc_shiftrot0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_FAST_fast1_trap0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_alu0_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_cr0_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_div0_15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
+ wire \pick_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_SPR_spr1_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_ca_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_ca_shiftrot0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_ca_spr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_ov_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_div0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_logical0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_mul0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_shiftrot0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_XER_xer_so_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
wire width 32 input 66 \raw_insn_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_CR_cr_a_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_CR_cr_b_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_CR_cr_c_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_CR_full_cr_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_FAST_fast1_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
- wire \rdflag_FAST_fast2_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
- wire \rdflag_INT_ra_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
- wire \rdflag_INT_rb_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
- wire \rdflag_INT_rc_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
+ wire \rdflag_FAST_fast1_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
+ wire \rdflag_INT_rabc_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
+ wire \rdflag_INT_rabc_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
+ wire \rdflag_INT_rabc_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_SPR_spr1_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_XER_xer_ca_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_XER_xer_ov_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256"
wire \rdflag_XER_xer_so_0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire \rdpick_CR_cr_a_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire \rdpick_FAST_fast1_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 3 \rdpick_FAST_fast1_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 3 \rdpick_FAST_fast1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire \rdpick_FAST_fast2_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 2 \rdpick_FAST_fast2_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 2 \rdpick_FAST_fast2_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire \rdpick_INT_ra_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 9 \rdpick_INT_ra_i
+ wire width 5 \rdpick_FAST_fast1_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 9 \rdpick_INT_ra_o
+ wire width 5 \rdpick_FAST_fast1_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire \rdpick_INT_rb_en_o
+ wire \rdpick_INT_rabc_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 8 \rdpick_INT_rb_i
+ wire width 19 \rdpick_INT_rabc_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 8 \rdpick_INT_rb_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire \rdpick_INT_rc_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 2 \rdpick_INT_rc_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 2 \rdpick_INT_rc_o
+ wire width 19 \rdpick_INT_rabc_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire \rdpick_SPR_spr1_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 6 \rdpick_XER_xer_so_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
wire width 6 \rdpick_XER_xer_so_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_CR_cr_a_branch0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_CR_cr_a_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_CR_cr_b_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_CR_cr_c_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_CR_full_cr_cr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_FAST_fast1_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_FAST_fast1_branch0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_FAST_fast1_spr0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_FAST_fast1_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_FAST_fast2_branch0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_FAST_fast2_trap0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_div0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_ldst0_8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_mul0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_shiftrot0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_spr0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_ra_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_cr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_div0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_ldst0_7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_logical0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_mul0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_shiftrot0_6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rb_trap0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rc_ldst0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
- wire \rp_INT_rc_shiftrot0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_FAST_fast1_trap0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_alu0_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_cr0_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_div0_15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+ wire \rp_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_SPR_spr1_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_ca_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_ca_shiftrot0_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_ca_spr0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_ov_spr0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_alu0_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_div0_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_logical0_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_mul0_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_shiftrot0_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_spr0_2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 7 \spr_spr1__addr
wire width 64 output 10 \sv__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 9 \sv__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire input 68 \sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
wire \sv_a_nz$176
wire width 3 input 11 \wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 69 \wen$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
wire \wp
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1020
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1038
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1060
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1080
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1137
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1153
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1227
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1255
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1275
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1295
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1315
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1335
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1355
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1402
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1418
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1434
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1468
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1484
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1500
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1516
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1552
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1568
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1584
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1600
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1645
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1661
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1677
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1693
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1709
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1753
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1769
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1793
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$1813
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418"
- wire \wp$999
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1018
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1036
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1058
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1078
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1098
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1151
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1225
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1253
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1273
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1293
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1313
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1353
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1400
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1432
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1498
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1550
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1566
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1598
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1643
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1659
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1675
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1691
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1751
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1767
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1791
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$1811
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423"
+ wire \wp$997
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
wire \wr_pick
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1007
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1028
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1046
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1068
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1088
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1145
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1219
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1247
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1287
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1307
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1327
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1347
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1394
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1410
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1426
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1460
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1476
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1492
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1508
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1544
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1560
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1576
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1592
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1634
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1653
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1669
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1685
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1701
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1745
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1761
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1785
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$1805
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410"
- wire \wr_pick$988
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1005
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1026
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1044
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1066
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1086
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1143
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1217
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1245
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1265
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1285
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1305
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1408
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1424
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1458
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1490
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1506
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1542
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1558
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1590
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1632
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1667
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1683
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1699
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1743
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1759
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1783
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$1803
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415"
+ wire \wr_pick$986
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
wire \wr_pick_dly
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1010
+ wire \wr_pick_dly$1008
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1010$next
+ wire \wr_pick_dly$1008$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1031
+ wire \wr_pick_dly$1029
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1031$next
+ wire \wr_pick_dly$1029$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1049
+ wire \wr_pick_dly$1047
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1049$next
+ wire \wr_pick_dly$1047$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1071
+ wire \wr_pick_dly$1069
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1071$next
+ wire \wr_pick_dly$1069$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1091
+ wire \wr_pick_dly$1089
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1091$next
+ wire \wr_pick_dly$1089$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1111
+ wire \wr_pick_dly$1109
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1111$next
+ wire \wr_pick_dly$1109$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1130
+ wire \wr_pick_dly$1128
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1130$next
+ wire \wr_pick_dly$1128$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1148
+ wire \wr_pick_dly$1146
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1148$next
+ wire \wr_pick_dly$1146$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1222
+ wire \wr_pick_dly$1220
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1222$next
+ wire \wr_pick_dly$1220$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1250
+ wire \wr_pick_dly$1248
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1250$next
+ wire \wr_pick_dly$1248$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1270
+ wire \wr_pick_dly$1268
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1270$next
+ wire \wr_pick_dly$1268$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1290
+ wire \wr_pick_dly$1288
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1290$next
+ wire \wr_pick_dly$1288$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1310
+ wire \wr_pick_dly$1308
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1310$next
+ wire \wr_pick_dly$1308$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1330
+ wire \wr_pick_dly$1328
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1330$next
+ wire \wr_pick_dly$1328$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1350
+ wire \wr_pick_dly$1348
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1350$next
+ wire \wr_pick_dly$1348$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1397
+ wire \wr_pick_dly$1395
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1397$next
+ wire \wr_pick_dly$1395$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1413
+ wire \wr_pick_dly$1411
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1413$next
+ wire \wr_pick_dly$1411$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1429
+ wire \wr_pick_dly$1427
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1429$next
+ wire \wr_pick_dly$1427$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1463
+ wire \wr_pick_dly$1461
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1463$next
+ wire \wr_pick_dly$1461$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1479
+ wire \wr_pick_dly$1477
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1479$next
+ wire \wr_pick_dly$1477$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1495
+ wire \wr_pick_dly$1493
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1495$next
+ wire \wr_pick_dly$1493$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1511
+ wire \wr_pick_dly$1509
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1511$next
+ wire \wr_pick_dly$1509$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1547
+ wire \wr_pick_dly$1545
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1547$next
+ wire \wr_pick_dly$1545$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1563
+ wire \wr_pick_dly$1561
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1563$next
+ wire \wr_pick_dly$1561$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1579
+ wire \wr_pick_dly$1577
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1579$next
+ wire \wr_pick_dly$1577$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1595
+ wire \wr_pick_dly$1593
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1595$next
+ wire \wr_pick_dly$1593$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1637
+ wire \wr_pick_dly$1635
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1637$next
+ wire \wr_pick_dly$1635$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1656
+ wire \wr_pick_dly$1654
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1656$next
+ wire \wr_pick_dly$1654$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1672
+ wire \wr_pick_dly$1670
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1672$next
+ wire \wr_pick_dly$1670$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1688
+ wire \wr_pick_dly$1686
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1688$next
+ wire \wr_pick_dly$1686$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1704
+ wire \wr_pick_dly$1702
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1704$next
+ wire \wr_pick_dly$1702$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1748
+ wire \wr_pick_dly$1746
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1748$next
+ wire \wr_pick_dly$1746$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1764
+ wire \wr_pick_dly$1762
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1764$next
+ wire \wr_pick_dly$1762$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1788
+ wire \wr_pick_dly$1786
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1788$next
+ wire \wr_pick_dly$1786$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1808
+ wire \wr_pick_dly$1806
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$1808$next
+ wire \wr_pick_dly$1806$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$991
+ wire \wr_pick_dly$989
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
- wire \wr_pick_dly$991$next
+ wire \wr_pick_dly$989$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
wire \wr_pick_dly$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1011
+ wire \wr_pick_rise$1009
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
+ wire \wr_pick_rise$1014
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
+ wire \wr_pick_rise$1015
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1016
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1017
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1018
+ wire \wr_pick_rise$1030
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1019
+ wire \wr_pick_rise$1035
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1032
+ wire \wr_pick_rise$1048
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1037
+ wire \wr_pick_rise$1053
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1050
+ wire \wr_pick_rise$1054
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1055
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1057
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1058
+ wire \wr_pick_rise$1070
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1059
+ wire \wr_pick_rise$1075
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1072
+ wire \wr_pick_rise$1076
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1077
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1078
+ wire \wr_pick_rise$1090
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1079
+ wire \wr_pick_rise$1095
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1092
+ wire \wr_pick_rise$1096
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$1097
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1098
+ wire \wr_pick_rise$1110
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1099
+ wire \wr_pick_rise$1115
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1112
+ wire \wr_pick_rise$1116
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1117
+ wire \wr_pick_rise$1129
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1118
+ wire \wr_pick_rise$1134
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1131
+ wire \wr_pick_rise$1636
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1136
+ wire \wr_pick_rise$1641
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1638
+ wire \wr_pick_rise$1642
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1643
+ wire \wr_pick_rise$976
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$1644
+ wire \wr_pick_rise$977
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$978
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \wr_pick_rise$979
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$980
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$981
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$992
+ wire \wr_pick_rise$990
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$997
+ wire \wr_pick_rise$995
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
- wire \wr_pick_rise$998
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ wire \wr_pick_rise$996
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_alu0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_alu0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_alu0_xer_ca_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_alu0_xer_ov_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_alu0_xer_so_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_branch0_fast1_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_branch0_fast1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_branch0_nia_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_cr0_cr_a_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_cr0_full_cr_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_cr0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_div0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_div0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_div0_xer_ov_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_div0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_ldst0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_ldst0_o_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_logical0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_logical0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_mul0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_mul0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_mul0_xer_ov_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_mul0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_shiftrot0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_shiftrot0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_shiftrot0_xer_ca_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_fast1_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_spr1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_xer_ca_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_xer_ov_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_spr0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_trap0_fast1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_trap0_fast1_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_trap0_msr_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_trap0_nia_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
wire \wrflag_trap0_o_0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire \wrpick_CR_cr_a_en_o
wire width 3 \xer_wen$171
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \xer_wen$173
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42151$1506
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$988
- connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42151$1506_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42153$1508
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
+ cell $and $and$libresoc.v:42112$1507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$95
connect \B \fus_cu_busy_o$20
- connect \Y $and$libresoc.v:42153$1508_Y
+ connect \Y $and$libresoc.v:42112$1507_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
- cell $and $and$libresoc.v:42154$1509
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
+ cell $and $and$libresoc.v:42113$1508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [2]
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42154$1509_Y
+ connect \Y $and$libresoc.v:42113$1508_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42156$1511
+ cell $and $and$libresoc.v:42115$1510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1007
- connect \B \$1012
- connect \Y $and$libresoc.v:42156$1511_Y
+ connect \A \wr_pick$1005
+ connect \B \$1010
+ connect \Y $and$libresoc.v:42115$1510_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42157$1512
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42116$1511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1007
+ connect \A \wr_pick$1005
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42157$1512_Y
+ connect \Y $and$libresoc.v:42116$1511_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42159$1514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
+ cell $and $and$libresoc.v:42118$1513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$98
connect \B \fus_cu_busy_o$23
- connect \Y $and$libresoc.v:42159$1514_Y
+ connect \Y $and$libresoc.v:42118$1513_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
- cell $and $and$libresoc.v:42160$1515
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
+ cell $and $and$libresoc.v:42119$1514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [3]
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42160$1515_Y
+ connect \Y $and$libresoc.v:42119$1514_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42162$1517
+ cell $and $and$libresoc.v:42121$1516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1028
- connect \B \$1033
- connect \Y $and$libresoc.v:42162$1517_Y
+ connect \A \wr_pick$1026
+ connect \B \$1031
+ connect \Y $and$libresoc.v:42121$1516_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42163$1518
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42122$1517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1028
+ connect \A \wr_pick$1026
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42163$1518_Y
+ connect \Y $and$libresoc.v:42122$1517_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42165$1520
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
+ cell $and $and$libresoc.v:42124$1519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$101
connect \B \fus_cu_busy_o$26
- connect \Y $and$libresoc.v:42165$1520_Y
+ connect \Y $and$libresoc.v:42124$1519_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
- cell $and $and$libresoc.v:42166$1521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
+ cell $and $and$libresoc.v:42125$1520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [4]
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42166$1521_Y
+ connect \Y $and$libresoc.v:42125$1520_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42168$1523
+ cell $and $and$libresoc.v:42127$1522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1046
- connect \B \$1051
- connect \Y $and$libresoc.v:42168$1523_Y
+ connect \A \wr_pick$1044
+ connect \B \$1049
+ connect \Y $and$libresoc.v:42127$1522_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42169$1524
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42128$1523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1046
+ connect \A \wr_pick$1044
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42169$1524_Y
+ connect \Y $and$libresoc.v:42128$1523_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42171$1526
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
+ cell $and $and$libresoc.v:42130$1525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$104
connect \B \fus_cu_busy_o$29
- connect \Y $and$libresoc.v:42171$1526_Y
+ connect \Y $and$libresoc.v:42130$1525_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
- cell $and $and$libresoc.v:42172$1527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
+ cell $and $and$libresoc.v:42131$1526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [5]
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42172$1527_Y
+ connect \Y $and$libresoc.v:42131$1526_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42174$1529
+ cell $and $and$libresoc.v:42133$1528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1068
- connect \B \$1073
- connect \Y $and$libresoc.v:42174$1529_Y
+ connect \A \wr_pick$1066
+ connect \B \$1071
+ connect \Y $and$libresoc.v:42133$1528_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42175$1530
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42134$1529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1068
+ connect \A \wr_pick$1066
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42175$1530_Y
+ connect \Y $and$libresoc.v:42134$1529_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$107
connect \B \fus_cu_busy_o$32
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [6]
connect \B \wrpick_INT_o_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1088
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1088
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connect \B \wrpick_INT_o_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$110
connect \B \fus_cu_busy_o$35
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [7]
connect \B \wrpick_INT_o_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1108
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1108
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connect \B \wrpick_INT_o_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \fus_cu_busy_o$38
- connect \Y $and$libresoc.v:42189$1544_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [8]
connect \B \wrpick_INT_o_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42192$1547
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1127
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1127
+ connect \A \wr_pick$1125
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42193$1548_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ea_ok
connect \B \fus_cu_busy_o$38
- connect \Y $and$libresoc.v:42195$1550_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [9]
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42196$1551_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42198$1553
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1145
- connect \B \$1149
- connect \Y $and$libresoc.v:42198$1553_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1145
+ connect \A \wr_pick$1143
connect \B \wrpick_INT_o_en_o
- connect \Y $and$libresoc.v:42199$1554_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_full_cr_ok
connect \B \fus_cu_busy_o$14
- connect \Y $and$libresoc.v:42228$1583_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [1]
connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42229$1584_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_full_cr_o
connect \B \wrpick_CR_full_cr_en_o
- connect \Y $and$libresoc.v:42230$1585_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42232$1587
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1219
- connect \B \$1223
- connect \Y $and$libresoc.v:42232$1587_Y
+ connect \A \wr_pick$1217
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1219
+ connect \A \wr_pick$1217
connect \B \wrpick_CR_full_cr_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok
connect \B \fus_cu_busy_o
- connect \Y $and$libresoc.v:42235$1590_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [1]
connect \B \fu_enable [0]
- connect \Y $and$libresoc.v:42236$1591_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [2]
connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42237$1592_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$99 [1]
connect \B \fu_enable [4]
- connect \Y $and$libresoc.v:42238$1593_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$105 [1]
connect \B \fu_enable [6]
- connect \Y $and$libresoc.v:42239$1594_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$108 [1]
connect \B \fu_enable [7]
- connect \Y $and$libresoc.v:42240$1595_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$111 [1]
connect \B \fu_enable [8]
- connect \Y $and$libresoc.v:42241$1596_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [0]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42242$1597_Y
+ connect \Y $and$libresoc.v:42201$1596_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42244$1599
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1247
- connect \B \$1251
- connect \Y $and$libresoc.v:42244$1599_Y
+ connect \A \wr_pick$1245
+ connect \B \$1249
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42245$1600
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1247
+ connect \A \wr_pick$1245
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42245$1600_Y
+ connect \Y $and$libresoc.v:42204$1599_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$122
connect \B \fus_cu_busy_o$14
- connect \Y $and$libresoc.v:42249$1604_Y
+ connect \Y $and$libresoc.v:42208$1603_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [1]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42250$1605_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42252$1607
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1267
- connect \B \$1271
- connect \Y $and$libresoc.v:42252$1607_Y
+ connect \A \wr_pick$1265
+ connect \B \$1269
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1267
+ connect \A \wr_pick$1265
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42253$1608_Y
+ connect \Y $and$libresoc.v:42212$1607_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$123
connect \B \fus_cu_busy_o$23
- connect \Y $and$libresoc.v:42257$1612_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [2]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42258$1613_Y
+ connect \Y $and$libresoc.v:42217$1612_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42260$1615
+ cell $and $and$libresoc.v:42219$1614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1287
- connect \B \$1291
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+ connect \A \wr_pick$1285
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1287
+ connect \A \wr_pick$1285
connect \B \wrpick_CR_cr_a_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$124
connect \B \fus_cu_busy_o$29
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [3]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42266$1621_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42268$1623
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1307
- connect \B \$1311
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+ connect \B \$1309
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1307
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connect \B \wrpick_CR_cr_a_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$125
connect \B \fus_cu_busy_o$32
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [4]
connect \B \wrpick_CR_cr_a_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42276$1631
+ cell $and $and$libresoc.v:42235$1630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1327
- connect \B \$1331
- connect \Y $and$libresoc.v:42276$1631_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1327
+ connect \A \wr_pick$1325
connect \B \wrpick_CR_cr_a_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$126
connect \B \fus_cu_busy_o$35
- connect \Y $and$libresoc.v:42281$1636_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [5]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42282$1637_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42284$1639
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1347
- connect \B \$1351
- connect \Y $and$libresoc.v:42284$1639_Y
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+ connect \Y $and$libresoc.v:42243$1638_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42285$1640
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42244$1639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1347
+ connect \A \wr_pick$1345
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42285$1640_Y
+ connect \Y $and$libresoc.v:42244$1639_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42299$1654
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok
connect \B \fus_cu_busy_o
- connect \Y $and$libresoc.v:42299$1654_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42300$1655
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [2]
connect \B \fu_enable [0]
- connect \Y $and$libresoc.v:42300$1655_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42301$1656
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$102 [5]
connect \B \fu_enable [5]
- connect \Y $and$libresoc.v:42301$1656_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42302$1657
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$111 [2]
connect \B \fu_enable [8]
- connect \Y $and$libresoc.v:42302$1657_Y
+ connect \Y $and$libresoc.v:42261$1656_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [0]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42303$1658_Y
+ connect \Y $and$libresoc.v:42262$1657_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42305$1660
+ cell $and $and$libresoc.v:42264$1659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1394
- connect \B \$1398
- connect \Y $and$libresoc.v:42305$1660_Y
+ connect \A \wr_pick$1392
+ connect \B \$1396
+ connect \Y $and$libresoc.v:42264$1659_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42306$1661
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
+ cell $and $and$libresoc.v:42265$1660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1394
+ connect \A \wr_pick$1392
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42306$1661_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42308$1663
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok$132
connect \B \fus_cu_busy_o$26
- connect \Y $and$libresoc.v:42308$1663_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [1]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42309$1664_Y
+ connect \Y $and$libresoc.v:42268$1663_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42311$1666
+ cell $and $and$libresoc.v:42270$1665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1410
- connect \B \$1414
- connect \Y $and$libresoc.v:42311$1666_Y
+ connect \A \wr_pick$1408
+ connect \B \$1412
+ connect \Y $and$libresoc.v:42270$1665_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1410
+ connect \A \wr_pick$1408
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42312$1667_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok$133
connect \B \fus_cu_busy_o$35
- connect \Y $and$libresoc.v:42314$1669_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [2]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42315$1670_Y
+ connect \Y $and$libresoc.v:42274$1669_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42317$1672
+ cell $and $and$libresoc.v:42276$1671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1426
- connect \B \$1430
- connect \Y $and$libresoc.v:42317$1672_Y
+ connect \A \wr_pick$1424
+ connect \B \$1428
+ connect \Y $and$libresoc.v:42276$1671_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42318$1673
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1426
+ connect \A \wr_pick$1424
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $and$libresoc.v:42318$1673_Y
+ connect \Y $and$libresoc.v:42277$1672_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
- cell $and $and$libresoc.v:42325$1681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ov_ok
connect \B \fus_cu_busy_o
- connect \Y $and$libresoc.v:42325$1681_Y
+ connect \Y $and$libresoc.v:42284$1680_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42326$1682
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
+ cell $and $and$libresoc.v:42285$1681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [3]
connect \B \fu_enable [0]
- connect \Y $and$libresoc.v:42326$1682_Y
+ connect \Y $and$libresoc.v:42285$1681_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42327$1683
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
+ cell $and $and$libresoc.v:42286$1682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$102 [4]
connect \B \fu_enable [5]
- connect \Y $and$libresoc.v:42327$1683_Y
+ connect \Y $and$libresoc.v:42286$1682_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42328$1684
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$105 [2]
connect \B \fu_enable [6]
- connect \Y $and$libresoc.v:42328$1684_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
- cell $and $and$libresoc.v:42329$1685
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$108 [2]
connect \B \fu_enable [7]
- connect \Y $and$libresoc.v:42329$1685_Y
+ connect \Y $and$libresoc.v:42288$1684_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [0]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $and$libresoc.v:42330$1686_Y
+ connect \Y $and$libresoc.v:42289$1685_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:42332$1688
+ cell $and $and$libresoc.v:42291$1687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1460
- connect \B \$1464
- connect \Y $and$libresoc.v:42332$1688_Y
+ connect \A \wr_pick$1458
+ connect \B \$1462
+ connect \Y $and$libresoc.v:42291$1687_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
- cell $and $and$libresoc.v:42333$1689
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1460
+ connect \A \wr_pick$1458
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $and$libresoc.v:42333$1689_Y
+ connect \Y $and$libresoc.v:42292$1688_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
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connect \A \wrpick_XER_xer_ov_o [1]
connect \B \wrpick_XER_xer_ov_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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parameter \B_SIGNED 0
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parameter \Y_WIDTH 1
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connect \B \wrpick_XER_xer_ov_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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connect \A \wrpick_XER_xer_ov_o [2]
connect \B \wrpick_XER_xer_ov_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \Y_WIDTH 1
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connect \B \wrpick_XER_xer_ov_en_o
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parameter \B_SIGNED 0
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connect \A \fus_xer_ov_ok$138
connect \B \fus_cu_busy_o$32
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parameter \B_SIGNED 0
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connect \A \wrpick_XER_xer_ov_o [3]
connect \B \wrpick_XER_xer_ov_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_XER_xer_ov_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
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connect \A \fus_xer_so_ok
connect \B \fus_cu_busy_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [4]
connect \B \fu_enable [0]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$102 [3]
connect \B \fu_enable [5]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$105 [3]
connect \B \fu_enable [6]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$108 [3]
connect \B \fu_enable [7]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [0]
connect \B \wrpick_XER_xer_so_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_XER_xer_so_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$141
connect \B \fus_cu_busy_o$26
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [1]
connect \B \wrpick_XER_xer_so_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_XER_xer_so_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$142
connect \B \fus_cu_busy_o$29
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [2]
connect \B \wrpick_XER_xer_so_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1576
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1576
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connect \B \wrpick_XER_xer_so_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$143
connect \B \fus_cu_busy_o$32
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [3]
connect \B \wrpick_XER_xer_so_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1592
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1592
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connect \B \wrpick_XER_xer_so_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast1_ok
connect \B \fus_cu_busy_o$17
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$148 [0]
connect \B \fu_enable [2]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [1]
connect \B \fu_enable [3]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$102 [2]
connect \B \fu_enable [5]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$148 [1]
connect \B \fu_enable [2]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
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connect \B \fu_enable [3]
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connect \A \wrpick_FAST_fast1_o [0]
connect \B \wrpick_FAST_fast1_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_FAST_fast1_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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parameter \B_SIGNED 0
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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parameter \B_SIGNED 0
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connect \A \wrpick_FAST_fast1_o [1]
connect \B \wrpick_FAST_fast1_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_FAST_fast1_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \B_SIGNED 0
parameter \Y_WIDTH 1
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connect \B \fus_cu_busy_o$26
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [2]
connect \B \wrpick_FAST_fast1_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_FAST_fast1_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
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connect \A \fus_fast2_ok
connect \B \fus_cu_busy_o$17
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [3]
connect \B \wrpick_FAST_fast1_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1685
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_FAST_fast1_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast2_ok$152
connect \B \fus_cu_busy_o$20
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [4]
connect \B \wrpick_FAST_fast1_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \wrpick_FAST_fast1_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_nia_ok
connect \B \fus_cu_busy_o$17
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$148 [2]
connect \B \fu_enable [2]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [3]
connect \B \fu_enable [3]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_nia_o [0]
connect \B \wrpick_STATE_nia_en_o
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1745
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1745
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connect \B \wrpick_STATE_nia_en_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_nia_ok$158
connect \B \fus_cu_busy_o$20
- connect \Y $and$libresoc.v:42450$1808_Y
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_nia_o [1]
connect \B \wrpick_STATE_nia_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1761
- connect \B \$1765
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1761
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connect \B \wrpick_STATE_nia_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_msr_ok
connect \B \fus_cu_busy_o$20
- connect \Y $and$libresoc.v:42459$1818_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [4]
connect \B \fu_enable [3]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_msr_o
connect \B \wrpick_STATE_msr_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1785
- connect \B \$1789
- connect \Y $and$libresoc.v:42463$1822_Y
+ connect \A \wr_pick$1783
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1785
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connect \B \wrpick_STATE_msr_en_o
- connect \Y $and$libresoc.v:42464$1823_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_spr1_ok
connect \B \fus_cu_busy_o$26
- connect \Y $and$libresoc.v:42467$1827_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$102 [1]
connect \B \fu_enable [5]
- connect \Y $and$libresoc.v:42468$1828_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_SPR_spr1_o
connect \B \wrpick_SPR_spr1_en_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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parameter \A_SIGNED 0
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parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1805
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419"
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \Y_WIDTH 1
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connect \B \wrpick_SPR_spr1_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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connect \A \core_core_fn_unit
connect \B 2'10
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 7'1000000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 6'100000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 8'10000000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
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parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 5'10000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 11'10000000000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 10'1000000000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 9'100000000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 4'1000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 14
connect \A \core_core_fn_unit
connect \B 3'100
- connect \Y $and$libresoc.v:42492$1852_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42497$1857
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42497$1857_Y
+ connect \Y $and$libresoc.v:42456$1856_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42498$1858
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42498$1858_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42501$1861
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42501$1861_Y
+ connect \Y $and$libresoc.v:42460$1860_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $and $and$libresoc.v:42504$1864
+ cell $and $and$libresoc.v:42463$1863
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 3'100
- connect \Y $and$libresoc.v:42504$1864_Y
+ connect \Y $and$libresoc.v:42463$1863_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42511$1871
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42511$1871_Y
+ connect \Y $and$libresoc.v:42470$1870_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42512$1872
+ cell $and $and$libresoc.v:42471$1871
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42512$1872_Y
+ connect \Y $and$libresoc.v:42471$1871_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42515$1875
+ cell $and $and$libresoc.v:42474$1874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42515$1875_Y
+ connect \Y $and$libresoc.v:42474$1874_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42518$1878
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42518$1878_Y
+ connect \Y $and$libresoc.v:42477$1877_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42519$1879
+ cell $and $and$libresoc.v:42478$1878
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42519$1879_Y
+ connect \Y $and$libresoc.v:42478$1878_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42522$1882
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42522$1882_Y
+ connect \Y $and$libresoc.v:42481$1881_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $and $and$libresoc.v:42524$1884
+ cell $and $and$libresoc.v:42483$1883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42524$1884_Y
+ connect \Y $and$libresoc.v:42483$1883_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84"
- cell $and $and$libresoc.v:42525$1885
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 2'10
- connect \Y $and$libresoc.v:42525$1885_Y
+ connect \Y $and$libresoc.v:42484$1884_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $and $and$libresoc.v:42529$1889
+ cell $and $and$libresoc.v:42488$1888
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 3'100
- connect \Y $and$libresoc.v:42529$1889_Y
+ connect \Y $and$libresoc.v:42488$1888_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42533$1893
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42533$1893_Y
+ connect \Y $and$libresoc.v:42492$1892_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42534$1894
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42534$1894_Y
+ connect \Y $and$libresoc.v:42493$1893_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42537$1897
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42537$1897_Y
+ connect \Y $and$libresoc.v:42496$1896_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42540$1900
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42540$1900_Y
+ connect \Y $and$libresoc.v:42499$1899_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42541$1901
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42541$1901_Y
+ connect \Y $and$libresoc.v:42500$1900_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42544$1904
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42544$1904_Y
+ connect \Y $and$libresoc.v:42503$1903_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42547$1907
+ cell $and $and$libresoc.v:42506$1906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
- connect \Y $and$libresoc.v:42547$1907_Y
+ connect \Y $and$libresoc.v:42506$1906_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $and $and$libresoc.v:42548$1908
+ cell $and $and$libresoc.v:42507$1907
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 1'1
- connect \Y $and$libresoc.v:42548$1908_Y
+ connect \Y $and$libresoc.v:42507$1907_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $and$libresoc.v:42551$1911
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_rc
connect \B \core_core_rc_ok
- connect \Y $and$libresoc.v:42551$1911_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $and $and$libresoc.v:42554$1914
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 3'100
- connect \Y $and$libresoc.v:42554$1914_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o [0]
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connect \B \fu_enable [0]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$352
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- connect \Y $and$libresoc.v:42560$1920_Y
+ connect \B \rdflag_INT_rabc_0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$354
connect \B \$356
- connect \Y $and$libresoc.v:42562$1922_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [0]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42563$1923_Y
+ connect \A \rdpick_INT_rabc_o [0]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$40 [0]
+ connect \A \fus_cu_rd__rel_o$40 [1]
connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42565$1925_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$364
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- connect \Y $and$libresoc.v:42566$1926_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42568$1928
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42527$1927
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$366
connect \B \$368
- connect \Y $and$libresoc.v:42568$1928_Y
+ connect \Y $and$libresoc.v:42527$1927_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42569$1929
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42528$1928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [1]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42569$1929_Y
+ connect \A \rdpick_INT_rabc_o [1]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42528$1928_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42571$1931
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42530$1930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$43 [0]
+ connect \A \fus_cu_rd__rel_o$43 [1]
connect \B \fu_enable [3]
- connect \Y $and$libresoc.v:42571$1931_Y
+ connect \Y $and$libresoc.v:42530$1930_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42572$1932
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42531$1931
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$376
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42572$1932_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42531$1931_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42574$1934
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42533$1933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$378
connect \B \$380
- connect \Y $and$libresoc.v:42574$1934_Y
+ connect \Y $and$libresoc.v:42533$1933_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42575$1935
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42534$1934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [2]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42575$1935_Y
+ connect \A \rdpick_INT_rabc_o [2]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42534$1934_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42577$1937
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42536$1936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$46 [0]
+ connect \A \fus_cu_rd__rel_o$46 [1]
connect \B \fu_enable [4]
- connect \Y $and$libresoc.v:42577$1937_Y
+ connect \Y $and$libresoc.v:42536$1936_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42578$1938
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42537$1937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$388
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42578$1938_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42537$1937_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42580$1940
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42539$1939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$390
connect \B \$392
- connect \Y $and$libresoc.v:42580$1940_Y
+ connect \Y $and$libresoc.v:42539$1939_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42581$1941
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42540$1940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [3]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42581$1941_Y
+ connect \A \rdpick_INT_rabc_o [3]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42540$1940_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42583$1943
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42542$1942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$49 [0]
- connect \B \fu_enable [5]
- connect \Y $and$libresoc.v:42583$1943_Y
+ connect \A \fus_cu_rd__rel_o$49 [1]
+ connect \B \fu_enable [6]
+ connect \Y $and$libresoc.v:42542$1942_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42584$1944
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42543$1943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$400
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42584$1944_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42543$1943_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42586$1946
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42545$1945
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$402
connect \B \$404
- connect \Y $and$libresoc.v:42586$1946_Y
+ connect \Y $and$libresoc.v:42545$1945_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42587$1947
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42546$1946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [4]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42587$1947_Y
+ connect \A \rdpick_INT_rabc_o [4]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42546$1946_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42589$1949
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42548$1948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$52 [0]
- connect \B \fu_enable [6]
- connect \Y $and$libresoc.v:42589$1949_Y
+ connect \A \fus_cu_rd__rel_o$52 [1]
+ connect \B \fu_enable [7]
+ connect \Y $and$libresoc.v:42548$1948_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42590$1950
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42549$1949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$412
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42590$1950_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42549$1949_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42592$1952
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42551$1951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$414
connect \B \$416
- connect \Y $and$libresoc.v:42592$1952_Y
+ connect \Y $and$libresoc.v:42551$1951_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42593$1953
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42552$1952
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [5]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42593$1953_Y
+ connect \A \rdpick_INT_rabc_o [5]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42552$1952_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42595$1955
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42554$1954
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$55 [0]
- connect \B \fu_enable [7]
- connect \Y $and$libresoc.v:42595$1955_Y
+ connect \A \fus_cu_rd__rel_o$55 [1]
+ connect \B \fu_enable [8]
+ connect \Y $and$libresoc.v:42554$1954_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42596$1956
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42555$1955
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$424
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42596$1956_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42555$1955_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42598$1958
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42557$1957
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$426
connect \B \$428
- connect \Y $and$libresoc.v:42598$1958_Y
+ connect \Y $and$libresoc.v:42557$1957_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42599$1959
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42558$1958
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [6]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42599$1959_Y
+ connect \A \rdpick_INT_rabc_o [6]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42558$1958_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42601$1961
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42560$1960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$58 [0]
- connect \B \fu_enable [8]
- connect \Y $and$libresoc.v:42601$1961_Y
+ connect \A \fus_cu_rd__rel_o$58 [1]
+ connect \B \fu_enable [9]
+ connect \Y $and$libresoc.v:42560$1960_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42602$1962
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42561$1961
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$436
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42602$1962_Y
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $and$libresoc.v:42561$1961_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42604$1964
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42563$1963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$438
connect \B \$440
- connect \Y $and$libresoc.v:42604$1964_Y
+ connect \Y $and$libresoc.v:42563$1963_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42605$1965
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42564$1964
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [7]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42605$1965_Y
+ connect \A \rdpick_INT_rabc_o [7]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42564$1964_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42607$1967
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42566$1966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$61 [0]
- connect \B \fu_enable [9]
- connect \Y $and$libresoc.v:42607$1967_Y
+ connect \A \fus_cu_rd__rel_o$55 [2]
+ connect \B \fu_enable [8]
+ connect \Y $and$libresoc.v:42566$1966_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42608$1968
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42567$1967
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$448
- connect \B \rdflag_INT_ra_0
- connect \Y $and$libresoc.v:42608$1968_Y
+ connect \B \rdflag_INT_rabc_1
+ connect \Y $and$libresoc.v:42567$1967_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42610$1970
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42569$1969
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$450
connect \B \$452
- connect \Y $and$libresoc.v:42610$1970_Y
+ connect \Y $and$libresoc.v:42569$1969_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42611$1971
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42570$1970
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [8]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $and$libresoc.v:42611$1971_Y
+ connect \A \rdpick_INT_rabc_o [8]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42570$1970_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42622$1982
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42572$1972
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o [1]
- connect \B \fu_enable [0]
- connect \Y $and$libresoc.v:42622$1982_Y
+ connect \A \fus_cu_rd__rel_o$58 [2]
+ connect \B \fu_enable [9]
+ connect \Y $and$libresoc.v:42572$1972_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42623$1983
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42573$1973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$479
- connect \B \rdflag_INT_rb_0
- connect \Y $and$libresoc.v:42623$1983_Y
+ connect \A \$460
+ connect \B \rdflag_INT_rabc_1
+ connect \Y $and$libresoc.v:42573$1973_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $and $and$libresoc.v:42625$1985
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $and $and$libresoc.v:42575$1975
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$481
- connect \B \$483
- connect \Y $and$libresoc.v:42625$1985_Y
+ connect \A \$462
+ connect \B \$464
+ connect \Y $and$libresoc.v:42575$1975_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
- cell $and $and$libresoc.v:42626$1986
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+ cell $and $and$libresoc.v:42576$1976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [0]
- connect \B \rdpick_INT_rb_en_o
- connect \Y $and$libresoc.v:42626$1986_Y
+ connect \A \rdpick_INT_rabc_o [9]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $and$libresoc.v:42576$1976_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
- cell $and $and$libresoc.v:42628$1988
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+ cell $and $and$libresoc.v:42578$1978
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$40 [1]
- connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42628$1988_Y
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end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$493
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$43 [1]
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end
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [2]
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end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$46 [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$515
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$517
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [3]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$52 [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$527
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$529
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [4]
- connect \B \rdpick_INT_rb_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$55 [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$539
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$541
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [5]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$58 [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$551
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$553
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [6]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$61 [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$563
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$565
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rb_o [7]
- connect \B \rdpick_INT_rb_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$58 [2]
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connect \B \fu_enable [8]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$592
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$594
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rc_o [0]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$61 [2]
+ connect \A \fus_cu_rd__rel_o$58 [0]
connect \B \fu_enable [9]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$604
- connect \B \rdflag_INT_rc_0
- connect \Y $and$libresoc.v:42685$2045_Y
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$739
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ca_o [1]
connect \B \rdpick_XER_xer_ca_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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+ connect \A \fus_cu_rd__rel_o$55 [4]
connect \B \fu_enable [8]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \rdflag_XER_xer_ca_0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ca_o [2]
connect \B \rdpick_XER_xer_ca_en_o
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_oe
connect \B \core_core_oe_ok
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84"
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_xer_in
connect \B 2'10
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$49 [4]
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connect \B \fu_enable [5]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \rdflag_XER_xer_ov_0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ov_o
connect \B \rdpick_XER_xer_ov_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$40 [2]
connect \B \fu_enable [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
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connect \B \rdflag_CR_full_cr_0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$789
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+ connect \A \$787
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_full_cr_o
connect \B \rdpick_CR_full_cr_en_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$40 [3]
connect \B \fu_enable [1]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$799
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connect \B \rdflag_CR_cr_a_0
- connect \Y $and$libresoc.v:42782$2144_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$801
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- connect \Y $and$libresoc.v:42784$2146_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_cr_a_o [0]
connect \B \rdpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42785$2147_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$81 [2]
connect \B \fu_enable [2]
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$815
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connect \B \rdflag_CR_cr_a_0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$817
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- connect \Y $and$libresoc.v:42792$2154_Y
+ connect \A \$815
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_cr_a_o [1]
connect \B \rdpick_CR_cr_a_en_o
- connect \Y $and$libresoc.v:42793$2155_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$40 [4]
connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42798$2160_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$834
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connect \B \rdflag_CR_cr_b_0
- connect \Y $and$libresoc.v:42799$2161_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$836
- connect \B \$838
- connect \Y $and$libresoc.v:42801$2163_Y
+ connect \A \$834
+ connect \B \$836
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_cr_b_o
connect \B \rdpick_CR_cr_b_en_o
- connect \Y $and$libresoc.v:42802$2164_Y
+ connect \Y $and$libresoc.v:42761$2163_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$40 [5]
connect \B \fu_enable [1]
- connect \Y $and$libresoc.v:42806$2168_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$850
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connect \B \rdflag_CR_cr_c_0
- connect \Y $and$libresoc.v:42807$2169_Y
+ connect \Y $and$libresoc.v:42766$2168_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$852
- connect \B \$854
- connect \Y $and$libresoc.v:42809$2171_Y
+ connect \A \$850
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_cr_c_o
connect \B \rdpick_CR_cr_c_en_o
- connect \Y $and$libresoc.v:42810$2172_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$81 [0]
connect \B \fu_enable [2]
- connect \Y $and$libresoc.v:42814$2176_Y
+ connect \Y $and$libresoc.v:42773$2175_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$866
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connect \B \rdflag_FAST_fast1_0
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+ connect \Y $and$libresoc.v:42774$2176_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$868
- connect \B \$870
- connect \Y $and$libresoc.v:42817$2179_Y
+ connect \A \$866
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+ connect \Y $and$libresoc.v:42776$2178_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [0]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $and$libresoc.v:42818$2180_Y
+ connect \Y $and$libresoc.v:42777$2179_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$43 [2]
connect \B \fu_enable [3]
- connect \Y $and$libresoc.v:42820$2182_Y
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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connect \A { \core_cr_in1_ok \core_fast2_ok \core_fast1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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parameter \Y_WIDTH 3
connect \A { \$267 \core_reg2_ok \core_reg1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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parameter \A_SIGNED 0
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connect \A { \$297 \$289 \$281 \core_fast1_ok \core_spr1_ok \core_reg1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 3
connect \A { \$325 \core_reg2_ok \core_reg1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A { \$347 \$339 \core_reg3_ok \core_reg2_ok \core_reg1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220"
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connect \A { \core_reg3_ok \core_reg2_ok \core_reg1_ok }
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_ra_ldst0_8
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_rb_div0_4
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_rb_mul0_5
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_rb_ldst0_7
- connect \Y $not$libresoc.v:42666$2026_Y
+ connect \A \dp_INT_rabc_mul0_16
+ connect \Y $not$libresoc.v:42616$2016_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42680$2040
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42622$2022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_rc_shiftrot0_0
- connect \Y $not$libresoc.v:42680$2040_Y
+ connect \A \dp_INT_rabc_shiftrot0_17
+ connect \Y $not$libresoc.v:42622$2022_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42686$2046
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42628$2028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_INT_rc_ldst0_1
- connect \Y $not$libresoc.v:42686$2046_Y
+ connect \A \dp_INT_rabc_ldst0_18
+ connect \Y $not$libresoc.v:42628$2028_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42700$2060
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42659$2059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_alu0_0
- connect \Y $not$libresoc.v:42700$2060_Y
+ connect \Y $not$libresoc.v:42659$2059_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42706$2066
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42665$2065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_logical0_1
- connect \Y $not$libresoc.v:42706$2066_Y
+ connect \Y $not$libresoc.v:42665$2065_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42712$2072
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42671$2071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_spr0_2
- connect \Y $not$libresoc.v:42712$2072_Y
+ connect \Y $not$libresoc.v:42671$2071_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42718$2078
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42677$2077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_div0_3
- connect \Y $not$libresoc.v:42718$2078_Y
+ connect \Y $not$libresoc.v:42677$2077_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42724$2084
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42683$2083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_mul0_4
- connect \Y $not$libresoc.v:42724$2084_Y
+ connect \Y $not$libresoc.v:42683$2083_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42730$2090
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42689$2089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_so_shiftrot0_5
- connect \Y $not$libresoc.v:42730$2090_Y
+ connect \Y $not$libresoc.v:42689$2089_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42746$2107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42705$2106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_ca_alu0_0
- connect \Y $not$libresoc.v:42746$2107_Y
+ connect \Y $not$libresoc.v:42705$2106_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42752$2113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42711$2112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_ca_spr0_1
- connect \Y $not$libresoc.v:42752$2113_Y
+ connect \Y $not$libresoc.v:42711$2112_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42758$2119
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42717$2118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_ca_shiftrot0_2
- connect \Y $not$libresoc.v:42758$2119_Y
+ connect \Y $not$libresoc.v:42717$2118_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42771$2133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42730$2132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_XER_xer_ov_spr0_0
- connect \Y $not$libresoc.v:42771$2133_Y
+ connect \Y $not$libresoc.v:42730$2132_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42777$2139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42736$2138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_CR_full_cr_cr0_0
- connect \Y $not$libresoc.v:42777$2139_Y
+ connect \Y $not$libresoc.v:42736$2138_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42783$2145
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42742$2144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_CR_cr_a_cr0_0
- connect \Y $not$libresoc.v:42783$2145_Y
+ connect \Y $not$libresoc.v:42742$2144_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42791$2153
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42750$2152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_CR_cr_a_branch0_1
- connect \Y $not$libresoc.v:42791$2153_Y
+ connect \Y $not$libresoc.v:42750$2152_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42800$2162
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42759$2161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_CR_cr_b_cr0_0
- connect \Y $not$libresoc.v:42800$2162_Y
+ connect \Y $not$libresoc.v:42759$2161_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42808$2170
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42767$2169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_CR_cr_c_cr0_0
- connect \Y $not$libresoc.v:42808$2170_Y
+ connect \Y $not$libresoc.v:42767$2169_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42816$2178
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42775$2177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_FAST_fast1_branch0_0
- connect \Y $not$libresoc.v:42816$2178_Y
+ connect \Y $not$libresoc.v:42775$2177_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42822$2184
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42781$2183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_FAST_fast1_trap0_1
- connect \Y $not$libresoc.v:42822$2184_Y
+ connect \Y $not$libresoc.v:42781$2183_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42828$2190
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42787$2189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_FAST_fast1_spr0_2
- connect \Y $not$libresoc.v:42828$2190_Y
+ connect \Y $not$libresoc.v:42787$2189_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42837$2199
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42793$2195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_FAST_fast2_branch0_0
- connect \Y $not$libresoc.v:42837$2199_Y
+ connect \A \dp_FAST_fast1_branch0_3
+ connect \Y $not$libresoc.v:42793$2195_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42843$2205
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42799$2201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dp_FAST_fast2_trap0_1
- connect \Y $not$libresoc.v:42843$2205_Y
+ connect \A \dp_FAST_fast1_trap0_4
+ connect \Y $not$libresoc.v:42799$2201_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
- cell $not $not$libresoc.v:42851$2213
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286"
+ cell $not $not$libresoc.v:42810$2212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dp_SPR_spr1_spr0_0
- connect \Y $not$libresoc.v:42851$2213_Y
+ connect \Y $not$libresoc.v:42810$2212_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:42868$2230
+ cell $not $not$libresoc.v:42827$2229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_pick_dly
- connect \Y $not$libresoc.v:42868$2230_Y
+ connect \Y $not$libresoc.v:42827$2229_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:42874$2236
+ cell $not $not$libresoc.v:42833$2235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$991
- connect \Y $not$libresoc.v:42874$2236_Y
+ connect \A \wr_pick_dly$989
+ connect \Y $not$libresoc.v:42833$2235_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42201$1556
+ cell $or $or$libresoc.v:42160$1555
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o
connect \B \fus_dest1_o$115
- connect \Y $or$libresoc.v:42201$1556_Y
+ connect \Y $or$libresoc.v:42160$1555_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42202$1557
+ cell $or $or$libresoc.v:42161$1556
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$117
connect \B \fus_dest1_o$118
- connect \Y $or$libresoc.v:42202$1557_Y
+ connect \Y $or$libresoc.v:42161$1556_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42203$1558
+ cell $or $or$libresoc.v:42162$1557
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$116
- connect \B \$1162
- connect \Y $or$libresoc.v:42203$1558_Y
+ connect \B \$1160
+ connect \Y $or$libresoc.v:42162$1557_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42204$1559
+ cell $or $or$libresoc.v:42163$1558
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \$1160
- connect \B \$1164
- connect \Y $or$libresoc.v:42204$1559_Y
+ connect \A \$1158
+ connect \B \$1162
+ connect \Y $or$libresoc.v:42163$1558_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42205$1560
+ cell $or $or$libresoc.v:42164$1559
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$119
connect \B \fus_dest1_o$120
- connect \Y $or$libresoc.v:42205$1560_Y
+ connect \Y $or$libresoc.v:42164$1559_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42206$1561
+ cell $or $or$libresoc.v:42165$1560
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A { \o_ok \fus_o }
connect \B { \ea_ok \fus_ea }
- connect \Y $or$libresoc.v:42206$1561_Y
+ connect \Y $or$libresoc.v:42165$1560_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42207$1562
+ cell $or $or$libresoc.v:42166$1561
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
connect \A \fus_dest1_o$121
- connect \B \$1170
- connect \Y $or$libresoc.v:42207$1562_Y
+ connect \B \$1168
+ connect \Y $or$libresoc.v:42166$1561_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42208$1563
+ cell $or $or$libresoc.v:42167$1562
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
- connect \A \$1168
- connect \B \$1172
- connect \Y $or$libresoc.v:42208$1563_Y
+ connect \A \$1166
+ connect \B \$1170
+ connect \Y $or$libresoc.v:42167$1562_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42209$1564
+ cell $or $or$libresoc.v:42168$1563
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
- connect \A \$1166
- connect \B \$1174
- connect \Y $or$libresoc.v:42209$1564_Y
+ connect \A \$1164
+ connect \B \$1172
+ connect \Y $or$libresoc.v:42168$1563_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42210$1565
+ cell $or $or$libresoc.v:42169$1564
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
connect \A \addr_en
- connect \B \addr_en$1002
- connect \Y $or$libresoc.v:42210$1565_Y
+ connect \B \addr_en$1000
+ connect \Y $or$libresoc.v:42169$1564_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42211$1566
+ cell $or $or$libresoc.v:42170$1565
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en$1041
- connect \B \addr_en$1063
- connect \Y $or$libresoc.v:42211$1566_Y
+ connect \A \addr_en$1039
+ connect \B \addr_en$1061
+ connect \Y $or$libresoc.v:42170$1565_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42212$1567
+ cell $or $or$libresoc.v:42171$1566
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en$1023
- connect \B \$1181
- connect \Y $or$libresoc.v:42212$1567_Y
+ connect \A \addr_en$1021
+ connect \B \$1179
+ connect \Y $or$libresoc.v:42171$1566_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42213$1568
+ cell $or $or$libresoc.v:42172$1567
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$1179
- connect \B \$1183
- connect \Y $or$libresoc.v:42213$1568_Y
+ connect \A \$1177
+ connect \B \$1181
+ connect \Y $or$libresoc.v:42172$1567_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42214$1569
+ cell $or $or$libresoc.v:42173$1568
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en$1083
- connect \B \addr_en$1103
- connect \Y $or$libresoc.v:42214$1569_Y
+ connect \A \addr_en$1081
+ connect \B \addr_en$1101
+ connect \Y $or$libresoc.v:42173$1568_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42215$1570
+ cell $or $or$libresoc.v:42174$1569
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en$1140
- connect \B \addr_en$1156
- connect \Y $or$libresoc.v:42215$1570_Y
+ connect \A \addr_en$1138
+ connect \B \addr_en$1154
+ connect \Y $or$libresoc.v:42174$1569_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42216$1571
+ cell $or $or$libresoc.v:42175$1570
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en$1122
- connect \B \$1189
- connect \Y $or$libresoc.v:42216$1571_Y
+ connect \A \addr_en$1120
+ connect \B \$1187
+ connect \Y $or$libresoc.v:42175$1570_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42217$1572
+ cell $or $or$libresoc.v:42176$1571
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$1187
- connect \B \$1191
- connect \Y $or$libresoc.v:42217$1572_Y
+ connect \A \$1185
+ connect \B \$1189
+ connect \Y $or$libresoc.v:42176$1571_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42218$1573
+ cell $or $or$libresoc.v:42177$1572
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$1185
- connect \B \$1193
- connect \Y $or$libresoc.v:42218$1573_Y
+ connect \A \$1183
+ connect \B \$1191
+ connect \Y $or$libresoc.v:42177$1572_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42219$1574
+ cell $or $or$libresoc.v:42178$1573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wp
- connect \B \wp$999
- connect \Y $or$libresoc.v:42219$1574_Y
+ connect \B \wp$997
+ connect \Y $or$libresoc.v:42178$1573_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42220$1575
+ cell $or $or$libresoc.v:42179$1574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1038
- connect \B \wp$1060
- connect \Y $or$libresoc.v:42220$1575_Y
+ connect \A \wp$1036
+ connect \B \wp$1058
+ connect \Y $or$libresoc.v:42179$1574_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42221$1576
+ cell $or $or$libresoc.v:42180$1575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1020
- connect \B \$1199
- connect \Y $or$libresoc.v:42221$1576_Y
+ connect \A \wp$1018
+ connect \B \$1197
+ connect \Y $or$libresoc.v:42180$1575_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42222$1577
+ cell $or $or$libresoc.v:42181$1576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1197
- connect \B \$1201
- connect \Y $or$libresoc.v:42222$1577_Y
+ connect \A \$1195
+ connect \B \$1199
+ connect \Y $or$libresoc.v:42181$1576_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42223$1578
+ cell $or $or$libresoc.v:42182$1577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1080
- connect \B \wp$1100
- connect \Y $or$libresoc.v:42223$1578_Y
+ connect \A \wp$1078
+ connect \B \wp$1098
+ connect \Y $or$libresoc.v:42182$1577_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42224$1579
+ cell $or $or$libresoc.v:42183$1578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1137
- connect \B \wp$1153
- connect \Y $or$libresoc.v:42224$1579_Y
+ connect \A \wp$1135
+ connect \B \wp$1151
+ connect \Y $or$libresoc.v:42183$1578_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42225$1580
+ cell $or $or$libresoc.v:42184$1579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1119
- connect \B \$1207
- connect \Y $or$libresoc.v:42225$1580_Y
+ connect \A \wp$1117
+ connect \B \$1205
+ connect \Y $or$libresoc.v:42184$1579_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42226$1581
+ cell $or $or$libresoc.v:42185$1580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1205
- connect \B \$1209
- connect \Y $or$libresoc.v:42226$1581_Y
+ connect \A \$1203
+ connect \B \$1207
+ connect \Y $or$libresoc.v:42185$1580_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42227$1582
+ cell $or $or$libresoc.v:42186$1581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1203
- connect \B \$1211
- connect \Y $or$libresoc.v:42227$1582_Y
+ connect \A \$1201
+ connect \B \$1209
+ connect \Y $or$libresoc.v:42186$1581_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42289$1644
+ cell $or $or$libresoc.v:42248$1643
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \fus_dest3_o
connect \B \fus_dest2_o$128
- connect \Y $or$libresoc.v:42289$1644_Y
+ connect \Y $or$libresoc.v:42248$1643_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42290$1645
+ cell $or $or$libresoc.v:42249$1644
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$127
- connect \B \$1365
- connect \Y $or$libresoc.v:42290$1645_Y
+ connect \B \$1363
+ connect \Y $or$libresoc.v:42249$1644_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42291$1646
+ cell $or $or$libresoc.v:42250$1645
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$130
connect \B \fus_dest2_o$131
- connect \Y $or$libresoc.v:42291$1646_Y
+ connect \Y $or$libresoc.v:42250$1645_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42292$1647
+ cell $or $or$libresoc.v:42251$1646
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$129
- connect \B \$1369
- connect \Y $or$libresoc.v:42292$1647_Y
+ connect \B \$1367
+ connect \Y $or$libresoc.v:42251$1646_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42293$1648
+ cell $or $or$libresoc.v:42252$1647
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \$1367
- connect \B \$1371
- connect \Y $or$libresoc.v:42293$1648_Y
+ connect \A \$1365
+ connect \B \$1369
+ connect \Y $or$libresoc.v:42252$1647_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42294$1649
+ cell $or $or$libresoc.v:42253$1648
parameter \A_SIGNED 0
parameter \A_WIDTH 256
parameter \B_SIGNED 0
parameter \B_WIDTH 256
parameter \Y_WIDTH 256
- connect \A \addr_en$1278
- connect \B \addr_en$1298
- connect \Y $or$libresoc.v:42294$1649_Y
+ connect \A \addr_en$1276
+ connect \B \addr_en$1296
+ connect \Y $or$libresoc.v:42253$1648_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42295$1650
+ cell $or $or$libresoc.v:42254$1649
parameter \A_SIGNED 0
parameter \A_WIDTH 256
parameter \B_SIGNED 0
parameter \B_WIDTH 256
parameter \Y_WIDTH 256
- connect \A \addr_en$1258
- connect \B \$1376
- connect \Y $or$libresoc.v:42295$1650_Y
+ connect \A \addr_en$1256
+ connect \B \$1374
+ connect \Y $or$libresoc.v:42254$1649_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42296$1651
+ cell $or $or$libresoc.v:42255$1650
parameter \A_SIGNED 0
parameter \A_WIDTH 256
parameter \B_SIGNED 0
parameter \B_WIDTH 256
parameter \Y_WIDTH 256
- connect \A \addr_en$1338
- connect \B \addr_en$1358
- connect \Y $or$libresoc.v:42296$1651_Y
+ connect \A \addr_en$1336
+ connect \B \addr_en$1356
+ connect \Y $or$libresoc.v:42255$1650_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42297$1652
+ cell $or $or$libresoc.v:42256$1651
parameter \A_SIGNED 0
parameter \A_WIDTH 256
parameter \B_SIGNED 0
parameter \B_WIDTH 256
parameter \Y_WIDTH 256
- connect \A \addr_en$1318
- connect \B \$1380
- connect \Y $or$libresoc.v:42297$1652_Y
+ connect \A \addr_en$1316
+ connect \B \$1378
+ connect \Y $or$libresoc.v:42256$1651_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42298$1653
+ cell $or $or$libresoc.v:42257$1652
parameter \A_SIGNED 0
parameter \A_WIDTH 256
parameter \B_SIGNED 0
parameter \B_WIDTH 256
parameter \Y_WIDTH 256
- connect \A \$1378
- connect \B \$1382
- connect \Y $or$libresoc.v:42298$1653_Y
+ connect \A \$1376
+ connect \B \$1380
+ connect \Y $or$libresoc.v:42257$1652_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42320$1675
+ cell $or $or$libresoc.v:42279$1674
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest6_o
connect \B \fus_dest3_o$135
- connect \Y $or$libresoc.v:42320$1675_Y
+ connect \Y $or$libresoc.v:42279$1674_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42321$1676
+ cell $or $or$libresoc.v:42280$1675
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \fus_dest3_o$134
- connect \B \$1440
- connect \Y $or$libresoc.v:42321$1676_Y
+ connect \B \$1438
+ connect \Y $or$libresoc.v:42280$1675_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42322$1677
+ cell $or $or$libresoc.v:42281$1676
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \addr_en$1421
- connect \B \addr_en$1437
- connect \Y $or$libresoc.v:42322$1677_Y
+ connect \A \addr_en$1419
+ connect \B \addr_en$1435
+ connect \Y $or$libresoc.v:42281$1676_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42323$1678
+ cell $or $or$libresoc.v:42282$1677
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \addr_en$1405
- connect \B \$1445
- connect \Y $or$libresoc.v:42323$1678_Y
+ connect \A \addr_en$1403
+ connect \B \$1443
+ connect \Y $or$libresoc.v:42282$1677_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42353$1709
+ cell $or $or$libresoc.v:42312$1708
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest4_o
connect \B \fus_dest5_o
- connect \Y $or$libresoc.v:42353$1709_Y
+ connect \Y $or$libresoc.v:42312$1708_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42354$1710
+ cell $or $or$libresoc.v:42313$1709
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest3_o$139
connect \B \fus_dest3_o$140
- connect \Y $or$libresoc.v:42354$1710_Y
+ connect \Y $or$libresoc.v:42313$1709_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42355$1711
+ cell $or $or$libresoc.v:42314$1710
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \$1522
- connect \B \$1524
- connect \Y $or$libresoc.v:42355$1711_Y
+ connect \A \$1520
+ connect \B \$1522
+ connect \Y $or$libresoc.v:42314$1710_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42356$1712
+ cell $or $or$libresoc.v:42315$1711
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \addr_en$1471
- connect \B \addr_en$1487
- connect \Y $or$libresoc.v:42356$1712_Y
+ connect \A \addr_en$1469
+ connect \B \addr_en$1485
+ connect \Y $or$libresoc.v:42315$1711_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42357$1713
+ cell $or $or$libresoc.v:42316$1712
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \addr_en$1503
- connect \B \addr_en$1519
- connect \Y $or$libresoc.v:42357$1713_Y
+ connect \A \addr_en$1501
+ connect \B \addr_en$1517
+ connect \Y $or$libresoc.v:42316$1712_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42358$1714
+ cell $or $or$libresoc.v:42317$1713
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \$1528
- connect \B \$1530
- connect \Y $or$libresoc.v:42358$1714_Y
+ connect \A \$1526
+ connect \B \$1528
+ connect \Y $or$libresoc.v:42317$1713_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42387$1743
+ cell $or $or$libresoc.v:42346$1742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_dest5_o$144
connect \B \fus_dest4_o$145
- connect \Y $or$libresoc.v:42387$1743_Y
+ connect \Y $or$libresoc.v:42346$1742_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42388$1744
+ cell $or $or$libresoc.v:42347$1743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_dest4_o$146
connect \B \fus_dest4_o$147
- connect \Y $or$libresoc.v:42388$1744_Y
+ connect \Y $or$libresoc.v:42347$1743_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42389$1745
+ cell $or $or$libresoc.v:42348$1744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1607
- connect \B \$1609
- connect \Y $or$libresoc.v:42389$1745_Y
+ connect \A \$1605
+ connect \B \$1607
+ connect \Y $or$libresoc.v:42348$1744_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42391$1748
+ cell $or $or$libresoc.v:42350$1747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \addr_en$1555
- connect \B \addr_en$1571
- connect \Y $or$libresoc.v:42391$1748_Y
+ connect \A \addr_en$1553
+ connect \B \addr_en$1569
+ connect \Y $or$libresoc.v:42350$1747_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42392$1749
+ cell $or $or$libresoc.v:42351$1748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \addr_en$1587
- connect \B \addr_en$1603
- connect \Y $or$libresoc.v:42392$1749_Y
+ connect \A \addr_en$1585
+ connect \B \addr_en$1601
+ connect \Y $or$libresoc.v:42351$1748_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42393$1750
+ cell $or $or$libresoc.v:42352$1749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1615
- connect \B \$1617
- connect \Y $or$libresoc.v:42393$1750_Y
+ connect \A \$1613
+ connect \B \$1615
+ connect \Y $or$libresoc.v:42352$1749_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42430$1788
+ cell $or $or$libresoc.v:42389$1787
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$153
connect \B \fus_dest2_o$154
- connect \Y $or$libresoc.v:42430$1788_Y
+ connect \Y $or$libresoc.v:42389$1787_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42431$1789
+ cell $or $or$libresoc.v:42390$1788
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest2_o$156
connect \B \fus_dest3_o$157
- connect \Y $or$libresoc.v:42431$1789_Y
+ connect \Y $or$libresoc.v:42390$1788_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42432$1790
+ cell $or $or$libresoc.v:42391$1789
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
connect \A \fus_dest3_o$155
- connect \B \$1717
- connect \Y $or$libresoc.v:42432$1790_Y
+ connect \B \$1715
+ connect \Y $or$libresoc.v:42391$1789_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42433$1791
+ cell $or $or$libresoc.v:42392$1790
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \$1715
- connect \B \$1719
- connect \Y $or$libresoc.v:42433$1791_Y
+ connect \A \$1713
+ connect \B \$1717
+ connect \Y $or$libresoc.v:42392$1790_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42434$1792
+ cell $or $or$libresoc.v:42393$1791
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \addr_en$1648
- connect \B \addr_en$1664
- connect \Y $or$libresoc.v:42434$1792_Y
+ connect \A \addr_en$1646
+ connect \B \addr_en$1662
+ connect \Y $or$libresoc.v:42393$1791_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42435$1793
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \addr_en$1696
- connect \B \addr_en$1712
- connect \Y $or$libresoc.v:42435$1793_Y
+ connect \A \addr_en$1694
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42436$1794
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parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \addr_en$1680
- connect \B \$1725
- connect \Y $or$libresoc.v:42436$1794_Y
+ connect \A \addr_en$1678
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42437$1795
+ cell $or $or$libresoc.v:42396$1794
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \$1723
- connect \B \$1727
- connect \Y $or$libresoc.v:42437$1795_Y
+ connect \A \$1721
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+ connect \Y $or$libresoc.v:42396$1794_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42438$1796
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1645
- connect \B \wp$1661
- connect \Y $or$libresoc.v:42438$1796_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42439$1797
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1693
- connect \B \wp$1709
- connect \Y $or$libresoc.v:42439$1797_Y
+ connect \A \wp$1691
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+ connect \Y $or$libresoc.v:42398$1796_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42440$1798
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wp$1677
- connect \B \$1733
- connect \Y $or$libresoc.v:42440$1798_Y
+ connect \A \wp$1675
+ connect \B \$1731
+ connect \Y $or$libresoc.v:42399$1797_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42441$1799
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$1731
- connect \B \$1735
- connect \Y $or$libresoc.v:42441$1799_Y
+ connect \A \$1729
+ connect \B \$1733
+ connect \Y $or$libresoc.v:42400$1798_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42456$1814
+ cell $or $or$libresoc.v:42415$1813
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest3_o$159
connect \B \fus_dest4_o$160
- connect \Y $or$libresoc.v:42456$1814_Y
+ connect \Y $or$libresoc.v:42415$1813_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42457$1815
+ cell $or $or$libresoc.v:42416$1814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \addr_en$1756
- connect \B \addr_en$1772
- connect \Y $or$libresoc.v:42457$1815_Y
+ connect \A \addr_en$1754
+ connect \B \addr_en$1770
+ connect \Y $or$libresoc.v:42416$1814_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42500$1860
+ cell $or $or$libresoc.v:42459$1859
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$229
connect \B \$233
- connect \Y $or$libresoc.v:42500$1860_Y
+ connect \Y $or$libresoc.v:42459$1859_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42502$1862
+ cell $or $or$libresoc.v:42461$1861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$235
connect \B \$237
- connect \Y $or$libresoc.v:42502$1862_Y
+ connect \Y $or$libresoc.v:42461$1861_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $or $or$libresoc.v:42506$1866
+ cell $or $or$libresoc.v:42465$1865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$241
connect \B \$245
- connect \Y $or$libresoc.v:42506$1866_Y
+ connect \Y $or$libresoc.v:42465$1865_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42514$1874
+ cell $or $or$libresoc.v:42473$1873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$257
connect \B \$261
- connect \Y $or$libresoc.v:42514$1874_Y
+ connect \Y $or$libresoc.v:42473$1873_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42516$1876
+ cell $or $or$libresoc.v:42475$1875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$263
connect \B \$265
- connect \Y $or$libresoc.v:42516$1876_Y
+ connect \Y $or$libresoc.v:42475$1875_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42521$1881
+ cell $or $or$libresoc.v:42480$1880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$271
connect \B \$275
- connect \Y $or$libresoc.v:42521$1881_Y
+ connect \Y $or$libresoc.v:42480$1880_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42523$1883
+ cell $or $or$libresoc.v:42482$1882
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$277
connect \B \$279
- connect \Y $or$libresoc.v:42523$1883_Y
+ connect \Y $or$libresoc.v:42482$1882_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84"
- cell $or $or$libresoc.v:42527$1887
+ cell $or $or$libresoc.v:42486$1886
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$283
connect \B \$287
- connect \Y $or$libresoc.v:42527$1887_Y
+ connect \Y $or$libresoc.v:42486$1886_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $or $or$libresoc.v:42531$1891
+ cell $or $or$libresoc.v:42490$1890
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$291
connect \B \$295
- connect \Y $or$libresoc.v:42531$1891_Y
+ connect \Y $or$libresoc.v:42490$1890_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42536$1896
+ cell $or $or$libresoc.v:42495$1895
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$301
connect \B \$305
- connect \Y $or$libresoc.v:42536$1896_Y
+ connect \Y $or$libresoc.v:42495$1895_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42538$1898
+ cell $or $or$libresoc.v:42497$1897
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$307
connect \B \$309
- connect \Y $or$libresoc.v:42538$1898_Y
+ connect \Y $or$libresoc.v:42497$1897_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42543$1903
+ cell $or $or$libresoc.v:42502$1902
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$315
connect \B \$319
- connect \Y $or$libresoc.v:42543$1903_Y
+ connect \Y $or$libresoc.v:42502$1902_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42545$1905
+ cell $or $or$libresoc.v:42504$1904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$321
connect \B \$323
- connect \Y $or$libresoc.v:42545$1905_Y
+ connect \Y $or$libresoc.v:42504$1904_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80"
- cell $or $or$libresoc.v:42550$1910
+ cell $or $or$libresoc.v:42509$1909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$329
connect \B \$333
- connect \Y $or$libresoc.v:42550$1910_Y
+ connect \Y $or$libresoc.v:42509$1909_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $or$libresoc.v:42552$1912
+ cell $or $or$libresoc.v:42511$1911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$335
connect \B \$337
- connect \Y $or$libresoc.v:42552$1912_Y
+ connect \Y $or$libresoc.v:42511$1911_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87"
- cell $or $or$libresoc.v:42556$1916
+ cell $or $or$libresoc.v:42515$1915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$341
connect \B \$345
- connect \Y $or$libresoc.v:42556$1916_Y
+ connect \Y $or$libresoc.v:42515$1915_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42613$1973
+ cell $or $or$libresoc.v:42632$2032
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_ra_alu0_0
- connect \B \addr_en_INT_ra_cr0_1
- connect \Y $or$libresoc.v:42613$1973_Y
+ connect \A \addr_en_INT_rabc_alu0_0
+ connect \B \addr_en_INT_rabc_cr0_1
+ connect \Y $or$libresoc.v:42632$2032_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42614$1974
+ cell $or $or$libresoc.v:42633$2033
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_ra_trap0_2
- connect \B \addr_en_INT_ra_logical0_3
- connect \Y $or$libresoc.v:42614$1974_Y
+ connect \A \addr_en_INT_rabc_trap0_2
+ connect \B \addr_en_INT_rabc_logical0_3
+ connect \Y $or$libresoc.v:42633$2033_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42615$1975
+ cell $or $or$libresoc.v:42634$2034
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$461
- connect \B \$463
- connect \Y $or$libresoc.v:42615$1975_Y
+ connect \A \$581
+ connect \B \$583
+ connect \Y $or$libresoc.v:42634$2034_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42616$1976
+ cell $or $or$libresoc.v:42635$2035
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_ra_spr0_4
- connect \B \addr_en_INT_ra_div0_5
- connect \Y $or$libresoc.v:42616$1976_Y
+ connect \A \addr_en_INT_rabc_div0_4
+ connect \B \addr_en_INT_rabc_mul0_5
+ connect \Y $or$libresoc.v:42635$2035_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42617$1977
+ cell $or $or$libresoc.v:42636$2036
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_ra_shiftrot0_7
- connect \B \addr_en_INT_ra_ldst0_8
- connect \Y $or$libresoc.v:42617$1977_Y
+ connect \A \addr_en_INT_rabc_ldst0_7
+ connect \B \addr_en_INT_rabc_shiftrot0_8
+ connect \Y $or$libresoc.v:42636$2036_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42618$1978
+ cell $or $or$libresoc.v:42637$2037
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_ra_mul0_6
- connect \B \$469
- connect \Y $or$libresoc.v:42618$1978_Y
+ connect \A \addr_en_INT_rabc_shiftrot0_6
+ connect \B \$589
+ connect \Y $or$libresoc.v:42637$2037_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42619$1979
+ cell $or $or$libresoc.v:42638$2038
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$467
- connect \B \$471
- connect \Y $or$libresoc.v:42619$1979_Y
+ connect \A \$587
+ connect \B \$591
+ connect \Y $or$libresoc.v:42638$2038_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42620$1980
+ cell $or $or$libresoc.v:42639$2039
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$465
- connect \B \$473
- connect \Y $or$libresoc.v:42620$1980_Y
+ connect \A \$585
+ connect \B \$593
+ connect \Y $or$libresoc.v:42639$2039_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42670$2030
+ cell $or $or$libresoc.v:42640$2040
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_rb_alu0_0
- connect \B \addr_en_INT_rb_cr0_1
- connect \Y $or$libresoc.v:42670$2030_Y
+ connect \A \addr_en_INT_rabc_ldst0_9
+ connect \B \addr_en_INT_rabc_alu0_10
+ connect \Y $or$libresoc.v:42640$2040_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42671$2031
+ cell $or $or$libresoc.v:42641$2041
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_rb_trap0_2
- connect \B \addr_en_INT_rb_logical0_3
- connect \Y $or$libresoc.v:42671$2031_Y
+ connect \A \addr_en_INT_rabc_trap0_12
+ connect \B \addr_en_INT_rabc_logical0_13
+ connect \Y $or$libresoc.v:42641$2041_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42672$2032
+ cell $or $or$libresoc.v:42642$2042
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$576
- connect \B \$578
- connect \Y $or$libresoc.v:42672$2032_Y
+ connect \A \addr_en_INT_rabc_cr0_11
+ connect \B \$599
+ connect \Y $or$libresoc.v:42642$2042_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
+ cell $or $or$libresoc.v:42643$2043
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 7
+ connect \A \$597
+ connect \B \$601
+ connect \Y $or$libresoc.v:42643$2043_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42673$2033
+ cell $or $or$libresoc.v:42644$2044
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_rb_div0_4
- connect \B \addr_en_INT_rb_mul0_5
- connect \Y $or$libresoc.v:42673$2033_Y
+ connect \A \addr_en_INT_rabc_spr0_14
+ connect \B \addr_en_INT_rabc_div0_15
+ connect \Y $or$libresoc.v:42644$2044_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42674$2034
+ cell $or $or$libresoc.v:42645$2045
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \addr_en_INT_rb_shiftrot0_6
- connect \B \addr_en_INT_rb_ldst0_7
- connect \Y $or$libresoc.v:42674$2034_Y
+ connect \A \addr_en_INT_rabc_shiftrot0_17
+ connect \B \addr_en_INT_rabc_ldst0_18
+ connect \Y $or$libresoc.v:42645$2045_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42675$2035
+ cell $or $or$libresoc.v:42646$2046
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$582
- connect \B \$584
- connect \Y $or$libresoc.v:42675$2035_Y
+ connect \A \addr_en_INT_rabc_mul0_16
+ connect \B \$607
+ connect \Y $or$libresoc.v:42646$2046_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:42676$2036
+ cell $or $or$libresoc.v:42647$2047
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 7
- connect \A \$580
- connect \B \$586
- connect \Y $or$libresoc.v:42676$2036_Y
+ connect \A \$605
+ connect \B \$609
+ connect \Y $or$libresoc.v:42647$2047_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:42690$2050
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
+ cell $or $or$libresoc.v:42648$2048
parameter \A_SIGNED 0
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
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- connect \Y $reduce_or$libresoc.v:42848$2210_Y
+ connect \A { \rp_FAST_fast1_trap0_4 \rp_FAST_fast1_branch0_3 \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 }
+ connect \Y $reduce_or$libresoc.v:42807$2209_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316"
- cell $reduce_or $reduce_or$libresoc.v:42855$2217
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+ cell $reduce_or $reduce_or$libresoc.v:42814$2216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rp_SPR_spr1_spr0_0
- connect \Y $reduce_or$libresoc.v:42855$2217_Y
+ connect \Y $reduce_or$libresoc.v:42814$2216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42247$1602
+ cell $sshl $sshl$libresoc.v:42206$1601
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1259
- connect \Y $sshl$libresoc.v:42247$1602_Y
+ connect \B \$1257
+ connect \Y $sshl$libresoc.v:42206$1601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42255$1610
+ cell $sshl $sshl$libresoc.v:42214$1609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1279
- connect \Y $sshl$libresoc.v:42255$1610_Y
+ connect \B \$1277
+ connect \Y $sshl$libresoc.v:42214$1609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42263$1618
+ cell $sshl $sshl$libresoc.v:42222$1617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1299
- connect \Y $sshl$libresoc.v:42263$1618_Y
+ connect \B \$1297
+ connect \Y $sshl$libresoc.v:42222$1617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42271$1626
+ cell $sshl $sshl$libresoc.v:42230$1625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1319
- connect \Y $sshl$libresoc.v:42271$1626_Y
+ connect \B \$1317
+ connect \Y $sshl$libresoc.v:42230$1625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42279$1634
+ cell $sshl $sshl$libresoc.v:42238$1633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1339
- connect \Y $sshl$libresoc.v:42279$1634_Y
+ connect \B \$1337
+ connect \Y $sshl$libresoc.v:42238$1633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sshl $sshl$libresoc.v:42287$1642
+ cell $sshl $sshl$libresoc.v:42246$1641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$1359
- connect \Y $sshl$libresoc.v:42287$1642_Y
+ connect \B \$1357
+ connect \Y $sshl$libresoc.v:42246$1641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64"
- cell $sshl $sshl$libresoc.v:42787$2149
+ cell $sshl $sshl$libresoc.v:42746$2148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$809
- connect \Y $sshl$libresoc.v:42787$2149_Y
+ connect \B \$807
+ connect \Y $sshl$libresoc.v:42746$2148_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64"
- cell $sshl $sshl$libresoc.v:42795$2157
+ cell $sshl $sshl$libresoc.v:42754$2156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$825
- connect \Y $sshl$libresoc.v:42795$2157_Y
+ connect \B \$823
+ connect \Y $sshl$libresoc.v:42754$2156_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66"
- cell $sshl $sshl$libresoc.v:42804$2166
+ cell $sshl $sshl$libresoc.v:42763$2165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$844
- connect \Y $sshl$libresoc.v:42804$2166_Y
+ connect \B \$842
+ connect \Y $sshl$libresoc.v:42763$2165_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68"
- cell $sshl $sshl$libresoc.v:42812$2174
+ cell $sshl $sshl$libresoc.v:42771$2173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 256
connect \A 1'1
- connect \B \$860
- connect \Y $sshl$libresoc.v:42812$2174_Y
+ connect \B \$858
+ connect \Y $sshl$libresoc.v:42771$2173_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42246$1601
+ cell $sub $sub$libresoc.v:42205$1600
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42246$1601_Y
+ connect \Y $sub$libresoc.v:42205$1600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42254$1609
+ cell $sub $sub$libresoc.v:42213$1608
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42254$1609_Y
+ connect \Y $sub$libresoc.v:42213$1608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42262$1617
+ cell $sub $sub$libresoc.v:42221$1616
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42262$1617_Y
+ connect \Y $sub$libresoc.v:42221$1616_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42270$1625
+ cell $sub $sub$libresoc.v:42229$1624
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42270$1625_Y
+ connect \Y $sub$libresoc.v:42229$1624_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42278$1633
+ cell $sub $sub$libresoc.v:42237$1632
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42278$1633_Y
+ connect \Y $sub$libresoc.v:42237$1632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140"
- cell $sub $sub$libresoc.v:42286$1641
+ cell $sub $sub$libresoc.v:42245$1640
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_out
- connect \Y $sub$libresoc.v:42286$1641_Y
+ connect \Y $sub$libresoc.v:42245$1640_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190"
- cell $sub $sub$libresoc.v:42495$1855
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ cell $sub $sub$libresoc.v:42454$1854
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \counter
connect \B 1'1
- connect \Y $sub$libresoc.v:42495$1855_Y
+ connect \Y $sub$libresoc.v:42454$1854_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64"
- cell $sub $sub$libresoc.v:42786$2148
+ cell $sub $sub$libresoc.v:42745$2147
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_in1
- connect \Y $sub$libresoc.v:42786$2148_Y
+ connect \Y $sub$libresoc.v:42745$2147_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64"
- cell $sub $sub$libresoc.v:42794$2156
+ cell $sub $sub$libresoc.v:42753$2155
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_in1
- connect \Y $sub$libresoc.v:42794$2156_Y
+ connect \Y $sub$libresoc.v:42753$2155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66"
- cell $sub $sub$libresoc.v:42803$2165
+ cell $sub $sub$libresoc.v:42762$2164
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_in2
- connect \Y $sub$libresoc.v:42803$2165_Y
+ connect \Y $sub$libresoc.v:42762$2164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68"
- cell $sub $sub$libresoc.v:42811$2173
+ cell $sub $sub$libresoc.v:42770$2172
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 3'111
connect \B \core_cr_in2$1
- connect \Y $sub$libresoc.v:42811$2173_Y
+ connect \Y $sub$libresoc.v:42770$2172_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42152$1507
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42111$1506
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$999
- connect \Y $ternary$libresoc.v:42152$1507_Y
+ connect \S \wp$997
+ connect \Y $ternary$libresoc.v:42111$1506_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42158$1513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42117$1512
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1020
- connect \Y $ternary$libresoc.v:42158$1513_Y
+ connect \S \wp$1018
+ connect \Y $ternary$libresoc.v:42117$1512_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42164$1519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42123$1518
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1038
- connect \Y $ternary$libresoc.v:42164$1519_Y
+ connect \S \wp$1036
+ connect \Y $ternary$libresoc.v:42123$1518_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42170$1525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42129$1524
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1060
- connect \Y $ternary$libresoc.v:42170$1525_Y
+ connect \S \wp$1058
+ connect \Y $ternary$libresoc.v:42129$1524_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42176$1531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42135$1530
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1080
- connect \Y $ternary$libresoc.v:42176$1531_Y
+ connect \S \wp$1078
+ connect \Y $ternary$libresoc.v:42135$1530_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42182$1537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42141$1536
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1100
- connect \Y $ternary$libresoc.v:42182$1537_Y
+ connect \S \wp$1098
+ connect \Y $ternary$libresoc.v:42141$1536_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42188$1543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42147$1542
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1119
- connect \Y $ternary$libresoc.v:42188$1543_Y
+ connect \S \wp$1117
+ connect \Y $ternary$libresoc.v:42147$1542_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42194$1549
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42153$1548
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
- connect \S \wp$1137
- connect \Y $ternary$libresoc.v:42194$1549_Y
+ connect \S \wp$1135
+ connect \Y $ternary$libresoc.v:42153$1548_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42200$1555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42159$1554
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_ea
- connect \S \wp$1153
- connect \Y $ternary$libresoc.v:42200$1555_Y
+ connect \S \wp$1151
+ connect \Y $ternary$libresoc.v:42159$1554_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42234$1589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42193$1588
parameter \WIDTH 8
connect \A 8'00000000
connect \B \core_core_cr_wr
- connect \S \wp$1227
- connect \Y $ternary$libresoc.v:42234$1589_Y
+ connect \S \wp$1225
+ connect \Y $ternary$libresoc.v:42193$1588_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42248$1603
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42207$1602
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1261
- connect \S \wp$1255
- connect \Y $ternary$libresoc.v:42248$1603_Y
+ connect \B \$1259
+ connect \S \wp$1253
+ connect \Y $ternary$libresoc.v:42207$1602_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42256$1611
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42215$1610
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1281
- connect \S \wp$1275
- connect \Y $ternary$libresoc.v:42256$1611_Y
+ connect \B \$1279
+ connect \S \wp$1273
+ connect \Y $ternary$libresoc.v:42215$1610_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42264$1619
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42223$1618
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1301
- connect \S \wp$1295
- connect \Y $ternary$libresoc.v:42264$1619_Y
+ connect \B \$1299
+ connect \S \wp$1293
+ connect \Y $ternary$libresoc.v:42223$1618_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42272$1627
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42231$1626
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1321
- connect \S \wp$1315
- connect \Y $ternary$libresoc.v:42272$1627_Y
+ connect \B \$1319
+ connect \S \wp$1313
+ connect \Y $ternary$libresoc.v:42231$1626_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42280$1635
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42239$1634
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1341
- connect \S \wp$1335
- connect \Y $ternary$libresoc.v:42280$1635_Y
+ connect \B \$1339
+ connect \S \wp$1333
+ connect \Y $ternary$libresoc.v:42239$1634_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42288$1643
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42247$1642
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$1361
- connect \S \wp$1355
- connect \Y $ternary$libresoc.v:42288$1643_Y
+ connect \B \$1359
+ connect \S \wp$1353
+ connect \Y $ternary$libresoc.v:42247$1642_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42307$1662
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42266$1661
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S \wp$1402
- connect \Y $ternary$libresoc.v:42307$1662_Y
+ connect \S \wp$1400
+ connect \Y $ternary$libresoc.v:42266$1661_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42313$1668
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42272$1667
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S \wp$1418
- connect \Y $ternary$libresoc.v:42313$1668_Y
+ connect \S \wp$1416
+ connect \Y $ternary$libresoc.v:42272$1667_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42319$1674
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42278$1673
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S \wp$1434
- connect \Y $ternary$libresoc.v:42319$1674_Y
+ connect \S \wp$1432
+ connect \Y $ternary$libresoc.v:42278$1673_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42334$1690
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42293$1689
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S \wp$1468
- connect \Y $ternary$libresoc.v:42334$1690_Y
+ connect \S \wp$1466
+ connect \Y $ternary$libresoc.v:42293$1689_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42340$1696
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42299$1695
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S \wp$1484
- connect \Y $ternary$libresoc.v:42340$1696_Y
+ connect \S \wp$1482
+ connect \Y $ternary$libresoc.v:42299$1695_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42346$1702
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42305$1701
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S \wp$1500
- connect \Y $ternary$libresoc.v:42346$1702_Y
+ connect \S \wp$1498
+ connect \Y $ternary$libresoc.v:42305$1701_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42352$1708
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42311$1707
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S \wp$1516
- connect \Y $ternary$libresoc.v:42352$1708_Y
+ connect \S \wp$1514
+ connect \Y $ternary$libresoc.v:42311$1707_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42368$1724
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42327$1723
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1552
- connect \Y $ternary$libresoc.v:42368$1724_Y
+ connect \S \wp$1550
+ connect \Y $ternary$libresoc.v:42327$1723_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42374$1730
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42333$1729
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1568
- connect \Y $ternary$libresoc.v:42374$1730_Y
+ connect \S \wp$1566
+ connect \Y $ternary$libresoc.v:42333$1729_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42380$1736
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42339$1735
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1584
- connect \Y $ternary$libresoc.v:42380$1736_Y
+ connect \S \wp$1582
+ connect \Y $ternary$libresoc.v:42339$1735_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42386$1742
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42345$1741
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1600
- connect \Y $ternary$libresoc.v:42386$1742_Y
+ connect \S \wp$1598
+ connect \Y $ternary$libresoc.v:42345$1741_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42405$1763
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42364$1762
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fasto1
- connect \S \wp$1645
- connect \Y $ternary$libresoc.v:42405$1763_Y
+ connect \S \wp$1643
+ connect \Y $ternary$libresoc.v:42364$1762_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42411$1769
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42370$1768
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fasto1
- connect \S \wp$1661
- connect \Y $ternary$libresoc.v:42411$1769_Y
+ connect \S \wp$1659
+ connect \Y $ternary$libresoc.v:42370$1768_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42417$1775
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42376$1774
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fasto1
- connect \S \wp$1677
- connect \Y $ternary$libresoc.v:42417$1775_Y
+ connect \S \wp$1675
+ connect \Y $ternary$libresoc.v:42376$1774_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42423$1781
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42382$1780
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fasto2
- connect \S \wp$1693
- connect \Y $ternary$libresoc.v:42423$1781_Y
+ connect \S \wp$1691
+ connect \Y $ternary$libresoc.v:42382$1780_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42429$1787
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42388$1786
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fasto2
- connect \S \wp$1709
- connect \Y $ternary$libresoc.v:42429$1787_Y
+ connect \S \wp$1707
+ connect \Y $ternary$libresoc.v:42388$1786_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42449$1807
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42408$1806
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1753
- connect \Y $ternary$libresoc.v:42449$1807_Y
+ connect \S \wp$1751
+ connect \Y $ternary$libresoc.v:42408$1806_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42455$1813
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42414$1812
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S \wp$1769
- connect \Y $ternary$libresoc.v:42455$1813_Y
+ connect \S \wp$1767
+ connect \Y $ternary$libresoc.v:42414$1812_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42465$1824
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42424$1823
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S \wp$1793
- connect \Y $ternary$libresoc.v:42465$1824_Y
+ connect \S \wp$1791
+ connect \Y $ternary$libresoc.v:42424$1823_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42473$1833
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42432$1832
parameter \WIDTH 10
connect \A 10'0000000000
connect \B \core_spro
- connect \S \wp$1813
- connect \Y $ternary$libresoc.v:42473$1833_Y
+ connect \S \wp$1811
+ connect \Y $ternary$libresoc.v:42432$1832_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42564$1924
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42523$1923
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_alu0_0
- connect \Y $ternary$libresoc.v:42564$1924_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_alu0_0
+ connect \Y $ternary$libresoc.v:42523$1923_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42570$1930
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42529$1929
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_cr0_1
- connect \Y $ternary$libresoc.v:42570$1930_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_cr0_1
+ connect \Y $ternary$libresoc.v:42529$1929_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42576$1936
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42535$1935
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_trap0_2
- connect \Y $ternary$libresoc.v:42576$1936_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_trap0_2
+ connect \Y $ternary$libresoc.v:42535$1935_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42582$1942
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42541$1941
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_logical0_3
- connect \Y $ternary$libresoc.v:42582$1942_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_logical0_3
+ connect \Y $ternary$libresoc.v:42541$1941_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42588$1948
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42547$1947
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_spr0_4
- connect \Y $ternary$libresoc.v:42588$1948_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_div0_4
+ connect \Y $ternary$libresoc.v:42547$1947_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42594$1954
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42553$1953
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_div0_5
- connect \Y $ternary$libresoc.v:42594$1954_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_mul0_5
+ connect \Y $ternary$libresoc.v:42553$1953_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42600$1960
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42559$1959
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_mul0_6
- connect \Y $ternary$libresoc.v:42600$1960_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_shiftrot0_6
+ connect \Y $ternary$libresoc.v:42559$1959_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42606$1966
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42565$1965
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_shiftrot0_7
- connect \Y $ternary$libresoc.v:42606$1966_Y
+ connect \B \core_reg2
+ connect \S \rp_INT_rabc_ldst0_7
+ connect \Y $ternary$libresoc.v:42565$1965_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42612$1972
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42571$1971
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg1
- connect \S \rp_INT_ra_ldst0_8
- connect \Y $ternary$libresoc.v:42612$1972_Y
+ connect \B \core_reg3
+ connect \S \rp_INT_rabc_shiftrot0_8
+ connect \Y $ternary$libresoc.v:42571$1971_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42627$1987
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42577$1977
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_alu0_0
- connect \Y $ternary$libresoc.v:42627$1987_Y
+ connect \B \core_reg3
+ connect \S \rp_INT_rabc_ldst0_9
+ connect \Y $ternary$libresoc.v:42577$1977_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42633$1993
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42583$1983
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_cr0_1
- connect \Y $ternary$libresoc.v:42633$1993_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_alu0_10
+ connect \Y $ternary$libresoc.v:42583$1983_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42639$1999
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42589$1989
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_trap0_2
- connect \Y $ternary$libresoc.v:42639$1999_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_cr0_11
+ connect \Y $ternary$libresoc.v:42589$1989_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42645$2005
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42595$1995
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_logical0_3
- connect \Y $ternary$libresoc.v:42645$2005_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_trap0_12
+ connect \Y $ternary$libresoc.v:42595$1995_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42651$2011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42601$2001
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_div0_4
- connect \Y $ternary$libresoc.v:42651$2011_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_logical0_13
+ connect \Y $ternary$libresoc.v:42601$2001_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42657$2017
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42607$2007
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_mul0_5
- connect \Y $ternary$libresoc.v:42657$2017_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_spr0_14
+ connect \Y $ternary$libresoc.v:42607$2007_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42663$2023
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42613$2013
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_shiftrot0_6
- connect \Y $ternary$libresoc.v:42663$2023_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_div0_15
+ connect \Y $ternary$libresoc.v:42613$2013_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42669$2029
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42619$2019
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg2
- connect \S \rp_INT_rb_ldst0_7
- connect \Y $ternary$libresoc.v:42669$2029_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_mul0_16
+ connect \Y $ternary$libresoc.v:42619$2019_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42683$2043
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42625$2025
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg3
- connect \S \rp_INT_rc_shiftrot0_0
- connect \Y $ternary$libresoc.v:42683$2043_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_shiftrot0_17
+ connect \Y $ternary$libresoc.v:42625$2025_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42689$2049
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42631$2031
parameter \WIDTH 7
connect \A 7'0000000
- connect \B \core_reg3
- connect \S \rp_INT_rc_ldst0_1
- connect \Y $ternary$libresoc.v:42689$2049_Y
+ connect \B \core_reg1
+ connect \S \rp_INT_rabc_ldst0_18
+ connect \Y $ternary$libresoc.v:42631$2031_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42703$2063
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42662$2062
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_alu0_0
- connect \Y $ternary$libresoc.v:42703$2063_Y
+ connect \Y $ternary$libresoc.v:42662$2062_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42709$2069
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42668$2068
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_logical0_1
- connect \Y $ternary$libresoc.v:42709$2069_Y
+ connect \Y $ternary$libresoc.v:42668$2068_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42715$2075
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42674$2074
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_spr0_2
- connect \Y $ternary$libresoc.v:42715$2075_Y
+ connect \Y $ternary$libresoc.v:42674$2074_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42721$2081
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42680$2080
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_div0_3
- connect \Y $ternary$libresoc.v:42721$2081_Y
+ connect \Y $ternary$libresoc.v:42680$2080_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42727$2087
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42686$2086
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_mul0_4
- connect \Y $ternary$libresoc.v:42727$2087_Y
+ connect \Y $ternary$libresoc.v:42686$2086_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42733$2093
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42692$2092
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
connect \S \rp_XER_xer_so_shiftrot0_5
- connect \Y $ternary$libresoc.v:42733$2093_Y
+ connect \Y $ternary$libresoc.v:42692$2092_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42749$2110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42708$2109
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
connect \S \rp_XER_xer_ca_alu0_0
- connect \Y $ternary$libresoc.v:42749$2110_Y
+ connect \Y $ternary$libresoc.v:42708$2109_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42755$2116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42714$2115
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
connect \S \rp_XER_xer_ca_spr0_1
- connect \Y $ternary$libresoc.v:42755$2116_Y
+ connect \Y $ternary$libresoc.v:42714$2115_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42761$2122
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42720$2121
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
connect \S \rp_XER_xer_ca_shiftrot0_2
- connect \Y $ternary$libresoc.v:42761$2122_Y
+ connect \Y $ternary$libresoc.v:42720$2121_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42774$2136
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42733$2135
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
connect \S \rp_XER_xer_ov_spr0_0
- connect \Y $ternary$libresoc.v:42774$2136_Y
+ connect \Y $ternary$libresoc.v:42733$2135_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42780$2142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42739$2141
parameter \WIDTH 8
connect \A 8'00000000
connect \B \core_core_cr_rd
connect \S \rp_CR_full_cr_cr0_0
- connect \Y $ternary$libresoc.v:42780$2142_Y
+ connect \Y $ternary$libresoc.v:42739$2141_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42788$2150
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42747$2149
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$811
+ connect \B \$809
connect \S \rp_CR_cr_a_cr0_0
- connect \Y $ternary$libresoc.v:42788$2150_Y
+ connect \Y $ternary$libresoc.v:42747$2149_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42796$2158
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42755$2157
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$827
+ connect \B \$825
connect \S \rp_CR_cr_a_branch0_1
- connect \Y $ternary$libresoc.v:42796$2158_Y
+ connect \Y $ternary$libresoc.v:42755$2157_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42805$2167
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42764$2166
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$846
+ connect \B \$844
connect \S \rp_CR_cr_b_cr0_0
- connect \Y $ternary$libresoc.v:42805$2167_Y
+ connect \Y $ternary$libresoc.v:42764$2166_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42813$2175
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42772$2174
parameter \WIDTH 256
connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- connect \B \$862
+ connect \B \$860
connect \S \rp_CR_cr_c_cr0_0
- connect \Y $ternary$libresoc.v:42813$2175_Y
+ connect \Y $ternary$libresoc.v:42772$2174_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42819$2181
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42778$2180
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fast1
connect \S \rp_FAST_fast1_branch0_0
- connect \Y $ternary$libresoc.v:42819$2181_Y
+ connect \Y $ternary$libresoc.v:42778$2180_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42825$2187
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42784$2186
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fast1
connect \S \rp_FAST_fast1_trap0_1
- connect \Y $ternary$libresoc.v:42825$2187_Y
+ connect \Y $ternary$libresoc.v:42784$2186_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42831$2193
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42790$2192
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fast1
connect \S \rp_FAST_fast1_spr0_2
- connect \Y $ternary$libresoc.v:42831$2193_Y
+ connect \Y $ternary$libresoc.v:42790$2192_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42840$2202
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42796$2198
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fast2
- connect \S \rp_FAST_fast2_branch0_0
- connect \Y $ternary$libresoc.v:42840$2202_Y
+ connect \S \rp_FAST_fast1_branch0_3
+ connect \Y $ternary$libresoc.v:42796$2198_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42846$2208
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42802$2204
parameter \WIDTH 3
connect \A 3'000
connect \B \core_fast2
- connect \S \rp_FAST_fast2_trap0_1
- connect \Y $ternary$libresoc.v:42846$2208_Y
+ connect \S \rp_FAST_fast1_trap0_4
+ connect \Y $ternary$libresoc.v:42802$2204_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
- cell $mux $ternary$libresoc.v:42854$2216
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+ cell $mux $ternary$libresoc.v:42813$2215
parameter \WIDTH 10
connect \A 10'0000000000
connect \B \core_spr1
connect \S \rp_SPR_spr1_spr0_0
- connect \Y $ternary$libresoc.v:42854$2216_Y
+ connect \Y $ternary$libresoc.v:42813$2215_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420"
- cell $mux $ternary$libresoc.v:42871$2233
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425"
+ cell $mux $ternary$libresoc.v:42830$2232
parameter \WIDTH 7
connect \A 7'0000000
connect \B \core_rego
connect \S \wp
- connect \Y $ternary$libresoc.v:42871$2233_Y
+ connect \Y $ternary$libresoc.v:42830$2232_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43034.6-43051.4"
+ attribute \src "libresoc.v:42994.6-43011.4"
cell \cr \cr
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \wen \cr_wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43052.11-43074.4"
+ attribute \src "libresoc.v:43012.11-43034.4"
cell \dec_ALU \dec_ALU
connect \ALU__data_len \dec_ALU_ALU__data_len
connect \ALU__fn_unit \dec_ALU_ALU__fn_unit
connect \sv_a_nz \dec_ALU_sv_a_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43075.14-43087.4"
+ attribute \src "libresoc.v:43035.14-43047.4"
cell \dec_BRANCH \dec_BRANCH
connect \BRANCH__cia \dec_BRANCH_BRANCH__cia
connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit
connect \raw_opcode_in \dec_BRANCH_raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43088.10-43094.4"
+ attribute \src "libresoc.v:43048.10-43054.4"
cell \dec_CR \dec_CR
connect \CR__fn_unit \dec_CR_CR__fn_unit
connect \CR__insn \dec_CR_CR__insn
connect \raw_opcode_in \dec_CR_raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43095.11-43117.4"
+ attribute \src "libresoc.v:43055.11-43077.4"
cell \dec_DIV \dec_DIV
connect \DIV__data_len \dec_DIV_DIV__data_len
connect \DIV__fn_unit \dec_DIV_DIV__fn_unit
connect \sv_a_nz \dec_DIV_sv_a_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43118.12-43138.4"
+ attribute \src "libresoc.v:43078.12-43098.4"
cell \dec_LDST \dec_LDST
connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse
connect \LDST__data_len \dec_LDST_LDST__data_len
connect \sv_a_nz \dec_LDST_sv_a_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43139.15-43161.4"
+ attribute \src "libresoc.v:43099.15-43121.4"
cell \dec_LOGICAL \dec_LOGICAL
connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len
connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit
connect \sv_a_nz \dec_LOGICAL_sv_a_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43162.11-43177.4"
+ attribute \src "libresoc.v:43122.11-43137.4"
cell \dec_MUL \dec_MUL
connect \MUL__fn_unit \dec_MUL_MUL__fn_unit
connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data
connect \raw_opcode_in \dec_MUL_raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43178.17-43198.4"
+ attribute \src "libresoc.v:43138.17-43158.4"
cell \dec_SHIFT_ROT \dec_SHIFT_ROT
connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit
connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data
connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43199.11-43206.4"
+ attribute \src "libresoc.v:43159.11-43166.4"
cell \dec_SPR \dec_SPR
connect \SPR__fn_unit \dec_SPR_SPR__fn_unit
connect \SPR__insn \dec_SPR_SPR__insn
connect \raw_opcode_in \dec_SPR_raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43207.8-43225.4"
+ attribute \src "libresoc.v:43167.8-43182.4"
cell \fast \fast
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src1__addr \fast_src1__addr
connect \src1__data_o \fast_src1__data_o
connect \src1__ren \fast_src1__ren
- connect \src2__addr \fast_src2__addr
- connect \src2__data_o \fast_src2__data_o
- connect \src2__ren \fast_src2__ren
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43226.7-43557.4"
+ attribute \src "libresoc.v:43183.7-43514.4"
cell \fus \fus
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53
connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56
connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59
- connect \cu_rd__go_i$50 \fus_cu_rd__go_i$62
+ connect \cu_rd__go_i$54 \fus_cu_rd__go_i$66
connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82
connect \cu_rd__rel_o \fus_cu_rd__rel_o
connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40
connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52
connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55
connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58
- connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$61
+ connect \cu_rd__rel_o$53 \fus_cu_rd__rel_o$65
connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81
connect \cu_rdmaskn_i \fus_cu_rdmaskn_i
connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24
connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a
connect \spr1_ok \fus_spr1_ok
connect \src1_i \fus_src1_i
- connect \src1_i$30 \fus_src1_i$42
- connect \src1_i$33 \fus_src1_i$45
- connect \src1_i$36 \fus_src1_i$48
- connect \src1_i$39 \fus_src1_i$51
- connect \src1_i$42 \fus_src1_i$54
- connect \src1_i$45 \fus_src1_i$57
- connect \src1_i$48 \fus_src1_i$60
+ connect \src1_i$50 \fus_src1_i$62
connect \src1_i$51 \fus_src1_i$63
+ connect \src1_i$52 \fus_src1_i$64
+ connect \src1_i$55 \fus_src1_i$67
+ connect \src1_i$56 \fus_src1_i$68
+ connect \src1_i$57 \fus_src1_i$69
+ connect \src1_i$58 \fus_src1_i$70
+ connect \src1_i$59 \fus_src1_i$71
connect \src1_i$74 \fus_src1_i$86
connect \src2_i \fus_src2_i
- connect \src2_i$52 \fus_src2_i$64
- connect \src2_i$53 \fus_src2_i$65
- connect \src2_i$54 \fus_src2_i$66
- connect \src2_i$55 \fus_src2_i$67
- connect \src2_i$56 \fus_src2_i$68
- connect \src2_i$57 \fus_src2_i$69
- connect \src2_i$58 \fus_src2_i$70
+ connect \src2_i$30 \fus_src2_i$42
+ connect \src2_i$33 \fus_src2_i$45
+ connect \src2_i$36 \fus_src2_i$48
+ connect \src2_i$39 \fus_src2_i$51
+ connect \src2_i$42 \fus_src2_i$54
+ connect \src2_i$45 \fus_src2_i$57
+ connect \src2_i$48 \fus_src2_i$60
connect \src2_i$77 \fus_src2_i$89
connect \src2_i$79 \fus_src2_i$91
connect \src3_i \fus_src3_i
- connect \src3_i$59 \fus_src3_i$71
+ connect \src3_i$49 \fus_src3_i$61
connect \src3_i$60 \fus_src3_i$72
connect \src3_i$61 \fus_src3_i$73
connect \src3_i$62 \fus_src3_i$74
connect \xer_so_ok$131 \fus_xer_so_ok$143
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43558.9-43576.4"
+ attribute \src "libresoc.v:43515.9-43527.4"
cell \int \int
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \dmi__addr \dmi__addr
connect \dmi__data_o \dmi__data_o
connect \dmi__ren \dmi__ren
- connect \src1__addr \int_src1__addr
- connect \src1__data_o \int_src1__data_o
- connect \src1__ren \int_src1__ren
- connect \src2__addr \int_src2__addr
- connect \src2__data_o \int_src2__data_o
- connect \src2__ren \int_src2__ren
- connect \src3__addr \int_src3__addr
- connect \src3__data_o \int_src3__data_o
- connect \src3__ren \int_src3__ren
+ connect \src__addr \int_src__addr
+ connect \src__data_o \int_src__data_o
+ connect \src__ren \int_src__ren
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43577.6-43609.4"
+ attribute \src "libresoc.v:43528.6-43560.4"
cell \l0 \l0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \wb_dcache_en \wb_dcache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43610.18-43614.4"
+ attribute \src "libresoc.v:43561.18-43565.4"
cell \rdpick_CR_cr_a \rdpick_CR_cr_a
connect \en_o \rdpick_CR_cr_a_en_o
connect \i \rdpick_CR_cr_a_i
connect \o \rdpick_CR_cr_a_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43615.18-43619.4"
+ attribute \src "libresoc.v:43566.18-43570.4"
cell \rdpick_CR_cr_b \rdpick_CR_cr_b
connect \en_o \rdpick_CR_cr_b_en_o
connect \i \rdpick_CR_cr_b_i
connect \o \rdpick_CR_cr_b_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43620.18-43624.4"
+ attribute \src "libresoc.v:43571.18-43575.4"
cell \rdpick_CR_cr_c \rdpick_CR_cr_c
connect \en_o \rdpick_CR_cr_c_en_o
connect \i \rdpick_CR_cr_c_i
connect \o \rdpick_CR_cr_c_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43625.21-43629.4"
+ attribute \src "libresoc.v:43576.21-43580.4"
cell \rdpick_CR_full_cr \rdpick_CR_full_cr
connect \en_o \rdpick_CR_full_cr_en_o
connect \i \rdpick_CR_full_cr_i
connect \o \rdpick_CR_full_cr_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43630.21-43634.4"
+ attribute \src "libresoc.v:43581.21-43585.4"
cell \rdpick_FAST_fast1 \rdpick_FAST_fast1
connect \en_o \rdpick_FAST_fast1_en_o
connect \i \rdpick_FAST_fast1_i
connect \o \rdpick_FAST_fast1_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43635.21-43639.4"
- cell \rdpick_FAST_fast2 \rdpick_FAST_fast2
- connect \en_o \rdpick_FAST_fast2_en_o
- connect \i \rdpick_FAST_fast2_i
- connect \o \rdpick_FAST_fast2_o
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:43640.17-43644.4"
- cell \rdpick_INT_ra \rdpick_INT_ra
- connect \en_o \rdpick_INT_ra_en_o
- connect \i \rdpick_INT_ra_i
- connect \o \rdpick_INT_ra_o
+ attribute \src "libresoc.v:43586.19-43590.4"
+ cell \rdpick_INT_rabc \rdpick_INT_rabc
+ connect \en_o \rdpick_INT_rabc_en_o
+ connect \i \rdpick_INT_rabc_i
+ connect \o \rdpick_INT_rabc_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43645.17-43649.4"
- cell \rdpick_INT_rb \rdpick_INT_rb
- connect \en_o \rdpick_INT_rb_en_o
- connect \i \rdpick_INT_rb_i
- connect \o \rdpick_INT_rb_o
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:43650.17-43654.4"
- cell \rdpick_INT_rc \rdpick_INT_rc
- connect \en_o \rdpick_INT_rc_en_o
- connect \i \rdpick_INT_rc_i
- connect \o \rdpick_INT_rc_o
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:43655.19-43659.4"
+ attribute \src "libresoc.v:43591.19-43595.4"
cell \rdpick_SPR_spr1 \rdpick_SPR_spr1
connect \en_o \rdpick_SPR_spr1_en_o
connect \i \rdpick_SPR_spr1_i
connect \o \rdpick_SPR_spr1_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43660.21-43664.4"
+ attribute \src "libresoc.v:43596.21-43600.4"
cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
connect \en_o \rdpick_XER_xer_ca_en_o
connect \i \rdpick_XER_xer_ca_i
connect \o \rdpick_XER_xer_ca_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43665.21-43669.4"
+ attribute \src "libresoc.v:43601.21-43605.4"
cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov
connect \en_o \rdpick_XER_xer_ov_en_o
connect \i \rdpick_XER_xer_ov_i
connect \o \rdpick_XER_xer_ov_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43670.21-43674.4"
+ attribute \src "libresoc.v:43606.21-43610.4"
cell \rdpick_XER_xer_so \rdpick_XER_xer_so
connect \en_o \rdpick_XER_xer_so_en_o
connect \i \rdpick_XER_xer_so_i
connect \o \rdpick_XER_xer_so_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43675.7-43684.4"
+ attribute \src "libresoc.v:43611.7-43620.4"
cell \spr \spr
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \spr1__wen \spr_spr1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43685.9-43702.4"
+ attribute \src "libresoc.v:43621.9-43638.4"
cell \state \state
connect \cia__data_o \cia__data_o
connect \cia__ren \cia__ren
connect \wen$5 \state_wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43703.18-43707.4"
+ attribute \src "libresoc.v:43639.18-43643.4"
cell \wrpick_CR_cr_a \wrpick_CR_cr_a
connect \en_o \wrpick_CR_cr_a_en_o
connect \i \wrpick_CR_cr_a_i
connect \o \wrpick_CR_cr_a_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43708.21-43712.4"
+ attribute \src "libresoc.v:43644.21-43648.4"
cell \wrpick_CR_full_cr \wrpick_CR_full_cr
connect \en_o \wrpick_CR_full_cr_en_o
connect \i \wrpick_CR_full_cr_i
connect \o \wrpick_CR_full_cr_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43713.21-43717.4"
+ attribute \src "libresoc.v:43649.21-43653.4"
cell \wrpick_FAST_fast1 \wrpick_FAST_fast1
connect \en_o \wrpick_FAST_fast1_en_o
connect \i \wrpick_FAST_fast1_i
connect \o \wrpick_FAST_fast1_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43718.16-43722.4"
+ attribute \src "libresoc.v:43654.16-43658.4"
cell \wrpick_INT_o \wrpick_INT_o
connect \en_o \wrpick_INT_o_en_o
connect \i \wrpick_INT_o_i
connect \o \wrpick_INT_o_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43723.19-43727.4"
+ attribute \src "libresoc.v:43659.19-43663.4"
cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
connect \en_o \wrpick_SPR_spr1_en_o
connect \i \wrpick_SPR_spr1_i
connect \o \wrpick_SPR_spr1_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43728.20-43732.4"
+ attribute \src "libresoc.v:43664.20-43668.4"
cell \wrpick_STATE_msr \wrpick_STATE_msr
connect \en_o \wrpick_STATE_msr_en_o
connect \i \wrpick_STATE_msr_i
connect \o \wrpick_STATE_msr_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43733.20-43737.4"
+ attribute \src "libresoc.v:43669.20-43673.4"
cell \wrpick_STATE_nia \wrpick_STATE_nia
connect \en_o \wrpick_STATE_nia_en_o
connect \i \wrpick_STATE_nia_i
connect \o \wrpick_STATE_nia_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43738.21-43742.4"
+ attribute \src "libresoc.v:43674.21-43678.4"
cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
connect \en_o \wrpick_XER_xer_ca_en_o
connect \i \wrpick_XER_xer_ca_i
connect \o \wrpick_XER_xer_ca_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43743.21-43747.4"
+ attribute \src "libresoc.v:43679.21-43683.4"
cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
connect \en_o \wrpick_XER_xer_ov_en_o
connect \i \wrpick_XER_xer_ov_i
connect \o \wrpick_XER_xer_ov_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43748.21-43752.4"
+ attribute \src "libresoc.v:43684.21-43688.4"
cell \wrpick_XER_xer_so \wrpick_XER_xer_so
connect \en_o \wrpick_XER_xer_so_en_o
connect \i \wrpick_XER_xer_so_i
connect \o \wrpick_XER_xer_so_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43753.7-43770.4"
+ attribute \src "libresoc.v:43689.7-43706.4"
cell \xer \xer
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:38311.7-38311.30"
- process $proc$libresoc.v:38311$2901
+ attribute \src "libresoc.v:38307.7-38307.30"
+ process $proc$libresoc.v:38307$2901
assign { } { }
assign $1\core_terminate_o[0:0] 1'0
sync always
sync init
update \core_terminate_o $1\core_terminate_o[0:0]
end
- attribute \src "libresoc.v:38324.13-38324.27"
- process $proc$libresoc.v:38324$2902
+ attribute \src "libresoc.v:38320.13-38320.27"
+ process $proc$libresoc.v:38320$2902
assign { } { }
assign $1\counter[1:0] 2'00
sync always
sync init
update \counter $1\counter[1:0]
end
- attribute \src "libresoc.v:39491.7-39491.34"
- process $proc$libresoc.v:39491$2903
+ attribute \src "libresoc.v:39487.7-39487.34"
+ process $proc$libresoc.v:39487$2903
assign { } { }
assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0
sync always
sync init
update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0]
end
- attribute \src "libresoc.v:39495.7-39495.30"
- process $proc$libresoc.v:39495$2904
+ attribute \src "libresoc.v:39491.7-39491.30"
+ process $proc$libresoc.v:39491$2904
assign { } { }
assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0
sync always
sync init
update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0]
end
- attribute \src "libresoc.v:39499.7-39499.30"
- process $proc$libresoc.v:39499$2905
+ attribute \src "libresoc.v:39495.7-39495.30"
+ process $proc$libresoc.v:39495$2905
assign { } { }
assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0
sync always
sync init
update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0]
end
- attribute \src "libresoc.v:39503.7-39503.30"
- process $proc$libresoc.v:39503$2906
+ attribute \src "libresoc.v:39499.7-39499.30"
+ process $proc$libresoc.v:39499$2906
assign { } { }
assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0
sync always
sync init
update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0]
end
- attribute \src "libresoc.v:39507.7-39507.33"
- process $proc$libresoc.v:39507$2907
+ attribute \src "libresoc.v:39503.7-39503.33"
+ process $proc$libresoc.v:39503$2907
assign { } { }
assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0
sync always
sync init
update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0]
end
- attribute \src "libresoc.v:39511.7-39511.37"
- process $proc$libresoc.v:39511$2908
+ attribute \src "libresoc.v:39507.7-39507.37"
+ process $proc$libresoc.v:39507$2908
assign { } { }
assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0
sync always
sync init
update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0]
end
+ attribute \src "libresoc.v:39511.7-39511.37"
+ process $proc$libresoc.v:39511$2909
+ assign { } { }
+ assign $1\dp_FAST_fast1_branch0_3[0:0] 1'0
+ sync always
+ sync init
+ update \dp_FAST_fast1_branch0_3 $1\dp_FAST_fast1_branch0_3[0:0]
+ end
attribute \src "libresoc.v:39515.7-39515.34"
- process $proc$libresoc.v:39515$2909
+ process $proc$libresoc.v:39515$2910
assign { } { }
assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0
sync always
update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0]
end
attribute \src "libresoc.v:39519.7-39519.35"
- process $proc$libresoc.v:39519$2910
+ process $proc$libresoc.v:39519$2911
assign { } { }
assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0
sync always
sync init
update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0]
end
- attribute \src "libresoc.v:39523.7-39523.37"
- process $proc$libresoc.v:39523$2911
- assign { } { }
- assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0
- sync always
- sync init
- update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0]
- end
- attribute \src "libresoc.v:39527.7-39527.35"
- process $proc$libresoc.v:39527$2912
+ attribute \src "libresoc.v:39523.7-39523.35"
+ process $proc$libresoc.v:39523$2912
assign { } { }
- assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0
+ assign $1\dp_FAST_fast1_trap0_4[0:0] 1'0
sync always
sync init
- update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0]
+ update \dp_FAST_fast1_trap0_4 $1\dp_FAST_fast1_trap0_4[0:0]
end
- attribute \src "libresoc.v:39531.7-39531.30"
- process $proc$libresoc.v:39531$2913
+ attribute \src "libresoc.v:39527.7-39527.32"
+ process $proc$libresoc.v:39527$2913
assign { } { }
- assign $1\dp_INT_ra_alu0_0[0:0] 1'0
+ assign $1\dp_INT_rabc_alu0_0[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0]
+ update \dp_INT_rabc_alu0_0 $1\dp_INT_rabc_alu0_0[0:0]
end
- attribute \src "libresoc.v:39535.7-39535.29"
- process $proc$libresoc.v:39535$2914
+ attribute \src "libresoc.v:39531.7-39531.33"
+ process $proc$libresoc.v:39531$2914
assign { } { }
- assign $1\dp_INT_ra_cr0_1[0:0] 1'0
+ assign $1\dp_INT_rabc_alu0_10[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0]
+ update \dp_INT_rabc_alu0_10 $1\dp_INT_rabc_alu0_10[0:0]
end
- attribute \src "libresoc.v:39539.7-39539.30"
- process $proc$libresoc.v:39539$2915
+ attribute \src "libresoc.v:39535.7-39535.31"
+ process $proc$libresoc.v:39535$2915
assign { } { }
- assign $1\dp_INT_ra_div0_5[0:0] 1'0
+ assign $1\dp_INT_rabc_cr0_1[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0]
+ update \dp_INT_rabc_cr0_1 $1\dp_INT_rabc_cr0_1[0:0]
end
- attribute \src "libresoc.v:39543.7-39543.31"
- process $proc$libresoc.v:39543$2916
+ attribute \src "libresoc.v:39539.7-39539.32"
+ process $proc$libresoc.v:39539$2916
assign { } { }
- assign $1\dp_INT_ra_ldst0_8[0:0] 1'0
+ assign $1\dp_INT_rabc_cr0_11[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0]
+ update \dp_INT_rabc_cr0_11 $1\dp_INT_rabc_cr0_11[0:0]
end
- attribute \src "libresoc.v:39547.7-39547.34"
- process $proc$libresoc.v:39547$2917
+ attribute \src "libresoc.v:39543.7-39543.33"
+ process $proc$libresoc.v:39543$2917
assign { } { }
- assign $1\dp_INT_ra_logical0_3[0:0] 1'0
+ assign $1\dp_INT_rabc_div0_15[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0]
+ update \dp_INT_rabc_div0_15 $1\dp_INT_rabc_div0_15[0:0]
end
- attribute \src "libresoc.v:39551.7-39551.30"
- process $proc$libresoc.v:39551$2918
+ attribute \src "libresoc.v:39547.7-39547.32"
+ process $proc$libresoc.v:39547$2918
assign { } { }
- assign $1\dp_INT_ra_mul0_6[0:0] 1'0
+ assign $1\dp_INT_rabc_div0_4[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0]
+ update \dp_INT_rabc_div0_4 $1\dp_INT_rabc_div0_4[0:0]
end
- attribute \src "libresoc.v:39555.7-39555.35"
- process $proc$libresoc.v:39555$2919
+ attribute \src "libresoc.v:39551.7-39551.34"
+ process $proc$libresoc.v:39551$2919
assign { } { }
- assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0
+ assign $1\dp_INT_rabc_ldst0_18[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0]
+ update \dp_INT_rabc_ldst0_18 $1\dp_INT_rabc_ldst0_18[0:0]
end
- attribute \src "libresoc.v:39559.7-39559.30"
- process $proc$libresoc.v:39559$2920
+ attribute \src "libresoc.v:39555.7-39555.33"
+ process $proc$libresoc.v:39555$2920
assign { } { }
- assign $1\dp_INT_ra_spr0_4[0:0] 1'0
+ assign $1\dp_INT_rabc_ldst0_7[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0]
+ update \dp_INT_rabc_ldst0_7 $1\dp_INT_rabc_ldst0_7[0:0]
end
- attribute \src "libresoc.v:39563.7-39563.31"
- process $proc$libresoc.v:39563$2921
+ attribute \src "libresoc.v:39559.7-39559.33"
+ process $proc$libresoc.v:39559$2921
assign { } { }
- assign $1\dp_INT_ra_trap0_2[0:0] 1'0
+ assign $1\dp_INT_rabc_ldst0_9[0:0] 1'0
sync always
sync init
- update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0]
+ update \dp_INT_rabc_ldst0_9 $1\dp_INT_rabc_ldst0_9[0:0]
end
- attribute \src "libresoc.v:39567.7-39567.30"
- process $proc$libresoc.v:39567$2922
+ attribute \src "libresoc.v:39563.7-39563.37"
+ process $proc$libresoc.v:39563$2922
assign { } { }
- assign $1\dp_INT_rb_alu0_0[0:0] 1'0
+ assign $1\dp_INT_rabc_logical0_13[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0]
+ update \dp_INT_rabc_logical0_13 $1\dp_INT_rabc_logical0_13[0:0]
end
- attribute \src "libresoc.v:39571.7-39571.29"
- process $proc$libresoc.v:39571$2923
+ attribute \src "libresoc.v:39567.7-39567.36"
+ process $proc$libresoc.v:39567$2923
assign { } { }
- assign $1\dp_INT_rb_cr0_1[0:0] 1'0
+ assign $1\dp_INT_rabc_logical0_3[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0]
+ update \dp_INT_rabc_logical0_3 $1\dp_INT_rabc_logical0_3[0:0]
end
- attribute \src "libresoc.v:39575.7-39575.30"
- process $proc$libresoc.v:39575$2924
+ attribute \src "libresoc.v:39571.7-39571.33"
+ process $proc$libresoc.v:39571$2924
assign { } { }
- assign $1\dp_INT_rb_div0_4[0:0] 1'0
+ assign $1\dp_INT_rabc_mul0_16[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0]
+ update \dp_INT_rabc_mul0_16 $1\dp_INT_rabc_mul0_16[0:0]
end
- attribute \src "libresoc.v:39579.7-39579.31"
- process $proc$libresoc.v:39579$2925
+ attribute \src "libresoc.v:39575.7-39575.32"
+ process $proc$libresoc.v:39575$2925
assign { } { }
- assign $1\dp_INT_rb_ldst0_7[0:0] 1'0
+ assign $1\dp_INT_rabc_mul0_5[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0]
+ update \dp_INT_rabc_mul0_5 $1\dp_INT_rabc_mul0_5[0:0]
end
- attribute \src "libresoc.v:39583.7-39583.34"
- process $proc$libresoc.v:39583$2926
+ attribute \src "libresoc.v:39579.7-39579.38"
+ process $proc$libresoc.v:39579$2926
assign { } { }
- assign $1\dp_INT_rb_logical0_3[0:0] 1'0
+ assign $1\dp_INT_rabc_shiftrot0_17[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0]
+ update \dp_INT_rabc_shiftrot0_17 $1\dp_INT_rabc_shiftrot0_17[0:0]
end
- attribute \src "libresoc.v:39587.7-39587.30"
- process $proc$libresoc.v:39587$2927
+ attribute \src "libresoc.v:39583.7-39583.37"
+ process $proc$libresoc.v:39583$2927
assign { } { }
- assign $1\dp_INT_rb_mul0_5[0:0] 1'0
+ assign $1\dp_INT_rabc_shiftrot0_6[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0]
+ update \dp_INT_rabc_shiftrot0_6 $1\dp_INT_rabc_shiftrot0_6[0:0]
end
- attribute \src "libresoc.v:39591.7-39591.35"
- process $proc$libresoc.v:39591$2928
+ attribute \src "libresoc.v:39587.7-39587.37"
+ process $proc$libresoc.v:39587$2928
assign { } { }
- assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0
+ assign $1\dp_INT_rabc_shiftrot0_8[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0]
+ update \dp_INT_rabc_shiftrot0_8 $1\dp_INT_rabc_shiftrot0_8[0:0]
end
- attribute \src "libresoc.v:39595.7-39595.31"
- process $proc$libresoc.v:39595$2929
+ attribute \src "libresoc.v:39591.7-39591.33"
+ process $proc$libresoc.v:39591$2929
assign { } { }
- assign $1\dp_INT_rb_trap0_2[0:0] 1'0
+ assign $1\dp_INT_rabc_spr0_14[0:0] 1'0
sync always
sync init
- update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0]
+ update \dp_INT_rabc_spr0_14 $1\dp_INT_rabc_spr0_14[0:0]
end
- attribute \src "libresoc.v:39599.7-39599.31"
- process $proc$libresoc.v:39599$2930
+ attribute \src "libresoc.v:39595.7-39595.34"
+ process $proc$libresoc.v:39595$2930
assign { } { }
- assign $1\dp_INT_rc_ldst0_1[0:0] 1'0
+ assign $1\dp_INT_rabc_trap0_12[0:0] 1'0
sync always
sync init
- update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0]
+ update \dp_INT_rabc_trap0_12 $1\dp_INT_rabc_trap0_12[0:0]
end
- attribute \src "libresoc.v:39603.7-39603.35"
- process $proc$libresoc.v:39603$2931
+ attribute \src "libresoc.v:39599.7-39599.33"
+ process $proc$libresoc.v:39599$2931
assign { } { }
- assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0
+ assign $1\dp_INT_rabc_trap0_2[0:0] 1'0
sync always
sync init
- update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0]
+ update \dp_INT_rabc_trap0_2 $1\dp_INT_rabc_trap0_2[0:0]
end
- attribute \src "libresoc.v:39607.7-39607.32"
- process $proc$libresoc.v:39607$2932
+ attribute \src "libresoc.v:39603.7-39603.32"
+ process $proc$libresoc.v:39603$2932
assign { } { }
assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0
sync always
sync init
update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0]
end
- attribute \src "libresoc.v:39611.7-39611.34"
- process $proc$libresoc.v:39611$2933
+ attribute \src "libresoc.v:39607.7-39607.34"
+ process $proc$libresoc.v:39607$2933
assign { } { }
assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0
sync always
sync init
update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0]
end
- attribute \src "libresoc.v:39615.7-39615.39"
- process $proc$libresoc.v:39615$2934
+ attribute \src "libresoc.v:39611.7-39611.39"
+ process $proc$libresoc.v:39611$2934
assign { } { }
assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0
sync always
sync init
update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0]
end
- attribute \src "libresoc.v:39619.7-39619.34"
- process $proc$libresoc.v:39619$2935
+ attribute \src "libresoc.v:39615.7-39615.34"
+ process $proc$libresoc.v:39615$2935
assign { } { }
assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0
sync always
sync init
update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0]
end
- attribute \src "libresoc.v:39623.7-39623.34"
- process $proc$libresoc.v:39623$2936
+ attribute \src "libresoc.v:39619.7-39619.34"
+ process $proc$libresoc.v:39619$2936
assign { } { }
assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0
sync always
sync init
update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0]
end
- attribute \src "libresoc.v:39627.7-39627.34"
- process $proc$libresoc.v:39627$2937
+ attribute \src "libresoc.v:39623.7-39623.34"
+ process $proc$libresoc.v:39623$2937
assign { } { }
assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0]
end
- attribute \src "libresoc.v:39631.7-39631.34"
- process $proc$libresoc.v:39631$2938
+ attribute \src "libresoc.v:39627.7-39627.34"
+ process $proc$libresoc.v:39627$2938
assign { } { }
assign $1\dp_XER_xer_so_div0_3[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0]
end
- attribute \src "libresoc.v:39635.7-39635.38"
- process $proc$libresoc.v:39635$2939
+ attribute \src "libresoc.v:39631.7-39631.38"
+ process $proc$libresoc.v:39631$2939
assign { } { }
assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0]
end
- attribute \src "libresoc.v:39639.7-39639.34"
- process $proc$libresoc.v:39639$2940
+ attribute \src "libresoc.v:39635.7-39635.34"
+ process $proc$libresoc.v:39635$2940
assign { } { }
assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0]
end
- attribute \src "libresoc.v:39643.7-39643.39"
- process $proc$libresoc.v:39643$2941
+ attribute \src "libresoc.v:39639.7-39639.39"
+ process $proc$libresoc.v:39639$2941
assign { } { }
assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0]
end
- attribute \src "libresoc.v:39647.7-39647.34"
- process $proc$libresoc.v:39647$2942
+ attribute \src "libresoc.v:39643.7-39643.34"
+ process $proc$libresoc.v:39643$2942
assign { } { }
assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0
sync always
sync init
update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0]
end
- attribute \src "libresoc.v:41772.7-41772.25"
- process $proc$libresoc.v:41772$2943
+ attribute \src "libresoc.v:41732.7-41732.25"
+ process $proc$libresoc.v:41732$2943
assign { } { }
assign $1\wr_pick_dly[0:0] 1'0
sync always
sync init
update \wr_pick_dly $1\wr_pick_dly[0:0]
end
- attribute \src "libresoc.v:41774.7-41774.32"
- process $proc$libresoc.v:41774$2944
+ attribute \src "libresoc.v:41734.7-41734.32"
+ process $proc$libresoc.v:41734$2944
assign { } { }
- assign $0\wr_pick_dly$1010[0:0]$2945 1'0
+ assign $0\wr_pick_dly$1008[0:0]$2945 1'0
sync always
sync init
- update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945
+ update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2945
end
- attribute \src "libresoc.v:41778.7-41778.32"
- process $proc$libresoc.v:41778$2946
+ attribute \src "libresoc.v:41738.7-41738.32"
+ process $proc$libresoc.v:41738$2946
assign { } { }
- assign $0\wr_pick_dly$1031[0:0]$2947 1'0
+ assign $0\wr_pick_dly$1029[0:0]$2947 1'0
sync always
sync init
- update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947
+ update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2947
end
- attribute \src "libresoc.v:41782.7-41782.32"
- process $proc$libresoc.v:41782$2948
+ attribute \src "libresoc.v:41742.7-41742.32"
+ process $proc$libresoc.v:41742$2948
assign { } { }
- assign $0\wr_pick_dly$1049[0:0]$2949 1'0
+ assign $0\wr_pick_dly$1047[0:0]$2949 1'0
sync always
sync init
- update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949
+ update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2949
end
- attribute \src "libresoc.v:41786.7-41786.32"
- process $proc$libresoc.v:41786$2950
+ attribute \src "libresoc.v:41746.7-41746.32"
+ process $proc$libresoc.v:41746$2950
assign { } { }
- assign $0\wr_pick_dly$1071[0:0]$2951 1'0
+ assign $0\wr_pick_dly$1069[0:0]$2951 1'0
sync always
sync init
- update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951
+ update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2951
end
- attribute \src "libresoc.v:41790.7-41790.32"
- process $proc$libresoc.v:41790$2952
+ attribute \src "libresoc.v:41750.7-41750.32"
+ process $proc$libresoc.v:41750$2952
assign { } { }
- assign $0\wr_pick_dly$1091[0:0]$2953 1'0
+ assign $0\wr_pick_dly$1089[0:0]$2953 1'0
sync always
sync init
- update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953
+ update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2953
end
- attribute \src "libresoc.v:41794.7-41794.32"
- process $proc$libresoc.v:41794$2954
+ attribute \src "libresoc.v:41754.7-41754.32"
+ process $proc$libresoc.v:41754$2954
assign { } { }
- assign $0\wr_pick_dly$1111[0:0]$2955 1'0
+ assign $0\wr_pick_dly$1109[0:0]$2955 1'0
sync always
sync init
- update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955
+ update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2955
end
- attribute \src "libresoc.v:41798.7-41798.32"
- process $proc$libresoc.v:41798$2956
+ attribute \src "libresoc.v:41758.7-41758.32"
+ process $proc$libresoc.v:41758$2956
assign { } { }
- assign $0\wr_pick_dly$1130[0:0]$2957 1'0
+ assign $0\wr_pick_dly$1128[0:0]$2957 1'0
sync always
sync init
- update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957
+ update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2957
end
- attribute \src "libresoc.v:41802.7-41802.32"
- process $proc$libresoc.v:41802$2958
+ attribute \src "libresoc.v:41762.7-41762.32"
+ process $proc$libresoc.v:41762$2958
assign { } { }
- assign $0\wr_pick_dly$1148[0:0]$2959 1'0
+ assign $0\wr_pick_dly$1146[0:0]$2959 1'0
sync always
sync init
- update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959
+ update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2959
end
- attribute \src "libresoc.v:41806.7-41806.32"
- process $proc$libresoc.v:41806$2960
+ attribute \src "libresoc.v:41766.7-41766.32"
+ process $proc$libresoc.v:41766$2960
assign { } { }
- assign $0\wr_pick_dly$1222[0:0]$2961 1'0
+ assign $0\wr_pick_dly$1220[0:0]$2961 1'0
sync always
sync init
- update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961
+ update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2961
end
- attribute \src "libresoc.v:41810.7-41810.32"
- process $proc$libresoc.v:41810$2962
+ attribute \src "libresoc.v:41770.7-41770.32"
+ process $proc$libresoc.v:41770$2962
assign { } { }
- assign $0\wr_pick_dly$1250[0:0]$2963 1'0
+ assign $0\wr_pick_dly$1248[0:0]$2963 1'0
sync always
sync init
- update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963
+ update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2963
end
- attribute \src "libresoc.v:41814.7-41814.32"
- process $proc$libresoc.v:41814$2964
+ attribute \src "libresoc.v:41774.7-41774.32"
+ process $proc$libresoc.v:41774$2964
assign { } { }
- assign $0\wr_pick_dly$1270[0:0]$2965 1'0
+ assign $0\wr_pick_dly$1268[0:0]$2965 1'0
sync always
sync init
- update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965
+ update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2965
end
- attribute \src "libresoc.v:41818.7-41818.32"
- process $proc$libresoc.v:41818$2966
+ attribute \src "libresoc.v:41778.7-41778.32"
+ process $proc$libresoc.v:41778$2966
assign { } { }
- assign $0\wr_pick_dly$1290[0:0]$2967 1'0
+ assign $0\wr_pick_dly$1288[0:0]$2967 1'0
sync always
sync init
- update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967
+ update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2967
end
- attribute \src "libresoc.v:41822.7-41822.32"
- process $proc$libresoc.v:41822$2968
+ attribute \src "libresoc.v:41782.7-41782.32"
+ process $proc$libresoc.v:41782$2968
assign { } { }
- assign $0\wr_pick_dly$1310[0:0]$2969 1'0
+ assign $0\wr_pick_dly$1308[0:0]$2969 1'0
sync always
sync init
- update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969
+ update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2969
end
- attribute \src "libresoc.v:41826.7-41826.32"
- process $proc$libresoc.v:41826$2970
+ attribute \src "libresoc.v:41786.7-41786.32"
+ process $proc$libresoc.v:41786$2970
assign { } { }
- assign $0\wr_pick_dly$1330[0:0]$2971 1'0
+ assign $0\wr_pick_dly$1328[0:0]$2971 1'0
sync always
sync init
- update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971
+ update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2971
end
- attribute \src "libresoc.v:41830.7-41830.32"
- process $proc$libresoc.v:41830$2972
+ attribute \src "libresoc.v:41790.7-41790.32"
+ process $proc$libresoc.v:41790$2972
assign { } { }
- assign $0\wr_pick_dly$1350[0:0]$2973 1'0
+ assign $0\wr_pick_dly$1348[0:0]$2973 1'0
sync always
sync init
- update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973
+ update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2973
end
- attribute \src "libresoc.v:41834.7-41834.32"
- process $proc$libresoc.v:41834$2974
+ attribute \src "libresoc.v:41794.7-41794.32"
+ process $proc$libresoc.v:41794$2974
assign { } { }
- assign $0\wr_pick_dly$1397[0:0]$2975 1'0
+ assign $0\wr_pick_dly$1395[0:0]$2975 1'0
sync always
sync init
- update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975
+ update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2975
end
- attribute \src "libresoc.v:41838.7-41838.32"
- process $proc$libresoc.v:41838$2976
+ attribute \src "libresoc.v:41798.7-41798.32"
+ process $proc$libresoc.v:41798$2976
assign { } { }
- assign $0\wr_pick_dly$1413[0:0]$2977 1'0
+ assign $0\wr_pick_dly$1411[0:0]$2977 1'0
sync always
sync init
- update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977
+ update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2977
end
- attribute \src "libresoc.v:41842.7-41842.32"
- process $proc$libresoc.v:41842$2978
+ attribute \src "libresoc.v:41802.7-41802.32"
+ process $proc$libresoc.v:41802$2978
assign { } { }
- assign $0\wr_pick_dly$1429[0:0]$2979 1'0
+ assign $0\wr_pick_dly$1427[0:0]$2979 1'0
sync always
sync init
- update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979
+ update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2979
end
- attribute \src "libresoc.v:41846.7-41846.32"
- process $proc$libresoc.v:41846$2980
+ attribute \src "libresoc.v:41806.7-41806.32"
+ process $proc$libresoc.v:41806$2980
assign { } { }
- assign $0\wr_pick_dly$1463[0:0]$2981 1'0
+ assign $0\wr_pick_dly$1461[0:0]$2981 1'0
sync always
sync init
- update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981
+ update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2981
end
- attribute \src "libresoc.v:41850.7-41850.32"
- process $proc$libresoc.v:41850$2982
+ attribute \src "libresoc.v:41810.7-41810.32"
+ process $proc$libresoc.v:41810$2982
assign { } { }
- assign $0\wr_pick_dly$1479[0:0]$2983 1'0
+ assign $0\wr_pick_dly$1477[0:0]$2983 1'0
sync always
sync init
- update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983
+ update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2983
end
- attribute \src "libresoc.v:41854.7-41854.32"
- process $proc$libresoc.v:41854$2984
+ attribute \src "libresoc.v:41814.7-41814.32"
+ process $proc$libresoc.v:41814$2984
assign { } { }
- assign $0\wr_pick_dly$1495[0:0]$2985 1'0
+ assign $0\wr_pick_dly$1493[0:0]$2985 1'0
sync always
sync init
- update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985
+ update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2985
end
- attribute \src "libresoc.v:41858.7-41858.32"
- process $proc$libresoc.v:41858$2986
+ attribute \src "libresoc.v:41818.7-41818.32"
+ process $proc$libresoc.v:41818$2986
assign { } { }
- assign $0\wr_pick_dly$1511[0:0]$2987 1'0
+ assign $0\wr_pick_dly$1509[0:0]$2987 1'0
sync always
sync init
- update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987
+ update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2987
end
- attribute \src "libresoc.v:41862.7-41862.32"
- process $proc$libresoc.v:41862$2988
+ attribute \src "libresoc.v:41822.7-41822.32"
+ process $proc$libresoc.v:41822$2988
assign { } { }
- assign $0\wr_pick_dly$1547[0:0]$2989 1'0
+ assign $0\wr_pick_dly$1545[0:0]$2989 1'0
sync always
sync init
- update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989
+ update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2989
end
- attribute \src "libresoc.v:41866.7-41866.32"
- process $proc$libresoc.v:41866$2990
+ attribute \src "libresoc.v:41826.7-41826.32"
+ process $proc$libresoc.v:41826$2990
assign { } { }
- assign $0\wr_pick_dly$1563[0:0]$2991 1'0
+ assign $0\wr_pick_dly$1561[0:0]$2991 1'0
sync always
sync init
- update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991
+ update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2991
end
- attribute \src "libresoc.v:41870.7-41870.32"
- process $proc$libresoc.v:41870$2992
+ attribute \src "libresoc.v:41830.7-41830.32"
+ process $proc$libresoc.v:41830$2992
assign { } { }
- assign $0\wr_pick_dly$1579[0:0]$2993 1'0
+ assign $0\wr_pick_dly$1577[0:0]$2993 1'0
sync always
sync init
- update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993
+ update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2993
end
- attribute \src "libresoc.v:41874.7-41874.32"
- process $proc$libresoc.v:41874$2994
+ attribute \src "libresoc.v:41834.7-41834.32"
+ process $proc$libresoc.v:41834$2994
assign { } { }
- assign $0\wr_pick_dly$1595[0:0]$2995 1'0
+ assign $0\wr_pick_dly$1593[0:0]$2995 1'0
sync always
sync init
- update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995
+ update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2995
end
- attribute \src "libresoc.v:41878.7-41878.32"
- process $proc$libresoc.v:41878$2996
+ attribute \src "libresoc.v:41838.7-41838.32"
+ process $proc$libresoc.v:41838$2996
assign { } { }
- assign $0\wr_pick_dly$1637[0:0]$2997 1'0
+ assign $0\wr_pick_dly$1635[0:0]$2997 1'0
sync always
sync init
- update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997
+ update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2997
end
- attribute \src "libresoc.v:41882.7-41882.32"
- process $proc$libresoc.v:41882$2998
+ attribute \src "libresoc.v:41842.7-41842.32"
+ process $proc$libresoc.v:41842$2998
assign { } { }
- assign $0\wr_pick_dly$1656[0:0]$2999 1'0
+ assign $0\wr_pick_dly$1654[0:0]$2999 1'0
sync always
sync init
- update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999
+ update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2999
end
- attribute \src "libresoc.v:41886.7-41886.32"
- process $proc$libresoc.v:41886$3000
+ attribute \src "libresoc.v:41846.7-41846.32"
+ process $proc$libresoc.v:41846$3000
assign { } { }
- assign $0\wr_pick_dly$1672[0:0]$3001 1'0
+ assign $0\wr_pick_dly$1670[0:0]$3001 1'0
sync always
sync init
- update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001
+ update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$3001
end
- attribute \src "libresoc.v:41890.7-41890.32"
- process $proc$libresoc.v:41890$3002
+ attribute \src "libresoc.v:41850.7-41850.32"
+ process $proc$libresoc.v:41850$3002
assign { } { }
- assign $0\wr_pick_dly$1688[0:0]$3003 1'0
+ assign $0\wr_pick_dly$1686[0:0]$3003 1'0
sync always
sync init
- update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003
+ update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$3003
end
- attribute \src "libresoc.v:41894.7-41894.32"
- process $proc$libresoc.v:41894$3004
+ attribute \src "libresoc.v:41854.7-41854.32"
+ process $proc$libresoc.v:41854$3004
assign { } { }
- assign $0\wr_pick_dly$1704[0:0]$3005 1'0
+ assign $0\wr_pick_dly$1702[0:0]$3005 1'0
sync always
sync init
- update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005
+ update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$3005
end
- attribute \src "libresoc.v:41898.7-41898.32"
- process $proc$libresoc.v:41898$3006
+ attribute \src "libresoc.v:41858.7-41858.32"
+ process $proc$libresoc.v:41858$3006
assign { } { }
- assign $0\wr_pick_dly$1748[0:0]$3007 1'0
+ assign $0\wr_pick_dly$1746[0:0]$3007 1'0
sync always
sync init
- update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007
+ update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$3007
end
- attribute \src "libresoc.v:41902.7-41902.32"
- process $proc$libresoc.v:41902$3008
+ attribute \src "libresoc.v:41862.7-41862.32"
+ process $proc$libresoc.v:41862$3008
assign { } { }
- assign $0\wr_pick_dly$1764[0:0]$3009 1'0
+ assign $0\wr_pick_dly$1762[0:0]$3009 1'0
sync always
sync init
- update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009
+ update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$3009
end
- attribute \src "libresoc.v:41906.7-41906.32"
- process $proc$libresoc.v:41906$3010
+ attribute \src "libresoc.v:41866.7-41866.32"
+ process $proc$libresoc.v:41866$3010
assign { } { }
- assign $0\wr_pick_dly$1788[0:0]$3011 1'0
+ assign $0\wr_pick_dly$1786[0:0]$3011 1'0
sync always
sync init
- update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011
+ update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$3011
end
- attribute \src "libresoc.v:41910.7-41910.32"
- process $proc$libresoc.v:41910$3012
+ attribute \src "libresoc.v:41870.7-41870.32"
+ process $proc$libresoc.v:41870$3012
assign { } { }
- assign $0\wr_pick_dly$1808[0:0]$3013 1'0
+ assign $0\wr_pick_dly$1806[0:0]$3013 1'0
sync always
sync init
- update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013
+ update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$3013
end
- attribute \src "libresoc.v:41914.7-41914.31"
- process $proc$libresoc.v:41914$3014
+ attribute \src "libresoc.v:41874.7-41874.31"
+ process $proc$libresoc.v:41874$3014
assign { } { }
- assign $0\wr_pick_dly$991[0:0]$3015 1'0
+ assign $0\wr_pick_dly$989[0:0]$3015 1'0
sync always
sync init
- update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015
+ update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$3015
end
- attribute \src "libresoc.v:42876.3-42877.51"
- process $proc$libresoc.v:42876$2238
+ attribute \src "libresoc.v:42836.3-42837.51"
+ process $proc$libresoc.v:42836$2238
assign { } { }
- assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next
+ assign $0\wr_pick_dly$1806[0:0]$2239 \wr_pick_dly$1806$next
sync posedge \coresync_clk
- update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239
+ update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$2239
end
- attribute \src "libresoc.v:42878.3-42879.51"
- process $proc$libresoc.v:42878$2240
+ attribute \src "libresoc.v:42838.3-42839.51"
+ process $proc$libresoc.v:42838$2240
assign { } { }
- assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next
+ assign $0\wr_pick_dly$1786[0:0]$2241 \wr_pick_dly$1786$next
sync posedge \coresync_clk
- update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241
+ update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$2241
end
- attribute \src "libresoc.v:42880.3-42881.51"
- process $proc$libresoc.v:42880$2242
+ attribute \src "libresoc.v:42840.3-42841.51"
+ process $proc$libresoc.v:42840$2242
assign { } { }
- assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next
+ assign $0\wr_pick_dly$1762[0:0]$2243 \wr_pick_dly$1762$next
sync posedge \coresync_clk
- update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243
+ update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$2243
end
- attribute \src "libresoc.v:42882.3-42883.51"
- process $proc$libresoc.v:42882$2244
+ attribute \src "libresoc.v:42842.3-42843.51"
+ process $proc$libresoc.v:42842$2244
assign { } { }
- assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next
+ assign $0\wr_pick_dly$1746[0:0]$2245 \wr_pick_dly$1746$next
sync posedge \coresync_clk
- update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245
+ update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$2245
end
- attribute \src "libresoc.v:42884.3-42885.51"
- process $proc$libresoc.v:42884$2246
+ attribute \src "libresoc.v:42844.3-42845.51"
+ process $proc$libresoc.v:42844$2246
assign { } { }
- assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next
+ assign $0\wr_pick_dly$1702[0:0]$2247 \wr_pick_dly$1702$next
sync posedge \coresync_clk
- update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247
+ update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$2247
end
- attribute \src "libresoc.v:42886.3-42887.51"
- process $proc$libresoc.v:42886$2248
+ attribute \src "libresoc.v:42846.3-42847.51"
+ process $proc$libresoc.v:42846$2248
assign { } { }
- assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next
+ assign $0\wr_pick_dly$1686[0:0]$2249 \wr_pick_dly$1686$next
sync posedge \coresync_clk
- update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249
+ update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$2249
end
- attribute \src "libresoc.v:42888.3-42889.51"
- process $proc$libresoc.v:42888$2250
+ attribute \src "libresoc.v:42848.3-42849.51"
+ process $proc$libresoc.v:42848$2250
assign { } { }
- assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next
+ assign $0\wr_pick_dly$1670[0:0]$2251 \wr_pick_dly$1670$next
sync posedge \coresync_clk
- update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251
+ update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$2251
end
- attribute \src "libresoc.v:42890.3-42891.51"
- process $proc$libresoc.v:42890$2252
+ attribute \src "libresoc.v:42850.3-42851.51"
+ process $proc$libresoc.v:42850$2252
assign { } { }
- assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next
+ assign $0\wr_pick_dly$1654[0:0]$2253 \wr_pick_dly$1654$next
sync posedge \coresync_clk
- update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253
+ update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2253
end
- attribute \src "libresoc.v:42892.3-42893.51"
- process $proc$libresoc.v:42892$2254
+ attribute \src "libresoc.v:42852.3-42853.51"
+ process $proc$libresoc.v:42852$2254
assign { } { }
- assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next
+ assign $0\wr_pick_dly$1635[0:0]$2255 \wr_pick_dly$1635$next
sync posedge \coresync_clk
- update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255
+ update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2255
end
- attribute \src "libresoc.v:42894.3-42895.51"
- process $proc$libresoc.v:42894$2256
+ attribute \src "libresoc.v:42854.3-42855.51"
+ process $proc$libresoc.v:42854$2256
assign { } { }
- assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next
+ assign $0\wr_pick_dly$1593[0:0]$2257 \wr_pick_dly$1593$next
sync posedge \coresync_clk
- update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257
+ update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2257
end
- attribute \src "libresoc.v:42896.3-42897.51"
- process $proc$libresoc.v:42896$2258
+ attribute \src "libresoc.v:42856.3-42857.51"
+ process $proc$libresoc.v:42856$2258
assign { } { }
- assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next
+ assign $0\wr_pick_dly$1577[0:0]$2259 \wr_pick_dly$1577$next
sync posedge \coresync_clk
- update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259
+ update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2259
end
- attribute \src "libresoc.v:42898.3-42899.51"
- process $proc$libresoc.v:42898$2260
+ attribute \src "libresoc.v:42858.3-42859.51"
+ process $proc$libresoc.v:42858$2260
assign { } { }
- assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next
+ assign $0\wr_pick_dly$1561[0:0]$2261 \wr_pick_dly$1561$next
sync posedge \coresync_clk
- update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261
+ update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2261
end
- attribute \src "libresoc.v:42900.3-42901.51"
- process $proc$libresoc.v:42900$2262
+ attribute \src "libresoc.v:42860.3-42861.51"
+ process $proc$libresoc.v:42860$2262
assign { } { }
- assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next
+ assign $0\wr_pick_dly$1545[0:0]$2263 \wr_pick_dly$1545$next
sync posedge \coresync_clk
- update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263
+ update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2263
end
- attribute \src "libresoc.v:42902.3-42903.51"
- process $proc$libresoc.v:42902$2264
+ attribute \src "libresoc.v:42862.3-42863.51"
+ process $proc$libresoc.v:42862$2264
assign { } { }
- assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next
+ assign $0\wr_pick_dly$1509[0:0]$2265 \wr_pick_dly$1509$next
sync posedge \coresync_clk
- update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265
+ update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2265
end
- attribute \src "libresoc.v:42904.3-42905.51"
- process $proc$libresoc.v:42904$2266
+ attribute \src "libresoc.v:42864.3-42865.51"
+ process $proc$libresoc.v:42864$2266
assign { } { }
- assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next
+ assign $0\wr_pick_dly$1493[0:0]$2267 \wr_pick_dly$1493$next
sync posedge \coresync_clk
- update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267
+ update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2267
end
- attribute \src "libresoc.v:42906.3-42907.51"
- process $proc$libresoc.v:42906$2268
+ attribute \src "libresoc.v:42866.3-42867.51"
+ process $proc$libresoc.v:42866$2268
assign { } { }
- assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next
+ assign $0\wr_pick_dly$1477[0:0]$2269 \wr_pick_dly$1477$next
sync posedge \coresync_clk
- update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269
+ update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2269
end
- attribute \src "libresoc.v:42908.3-42909.51"
- process $proc$libresoc.v:42908$2270
+ attribute \src "libresoc.v:42868.3-42869.51"
+ process $proc$libresoc.v:42868$2270
assign { } { }
- assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next
+ assign $0\wr_pick_dly$1461[0:0]$2271 \wr_pick_dly$1461$next
sync posedge \coresync_clk
- update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271
+ update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2271
end
- attribute \src "libresoc.v:42910.3-42911.51"
- process $proc$libresoc.v:42910$2272
+ attribute \src "libresoc.v:42870.3-42871.51"
+ process $proc$libresoc.v:42870$2272
assign { } { }
- assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next
+ assign $0\wr_pick_dly$1427[0:0]$2273 \wr_pick_dly$1427$next
sync posedge \coresync_clk
- update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273
+ update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2273
end
- attribute \src "libresoc.v:42912.3-42913.51"
- process $proc$libresoc.v:42912$2274
+ attribute \src "libresoc.v:42872.3-42873.51"
+ process $proc$libresoc.v:42872$2274
assign { } { }
- assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next
+ assign $0\wr_pick_dly$1411[0:0]$2275 \wr_pick_dly$1411$next
sync posedge \coresync_clk
- update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275
+ update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2275
end
- attribute \src "libresoc.v:42914.3-42915.51"
- process $proc$libresoc.v:42914$2276
+ attribute \src "libresoc.v:42874.3-42875.51"
+ process $proc$libresoc.v:42874$2276
assign { } { }
- assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next
+ assign $0\wr_pick_dly$1395[0:0]$2277 \wr_pick_dly$1395$next
sync posedge \coresync_clk
- update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277
+ update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2277
end
- attribute \src "libresoc.v:42916.3-42917.51"
- process $proc$libresoc.v:42916$2278
+ attribute \src "libresoc.v:42876.3-42877.51"
+ process $proc$libresoc.v:42876$2278
assign { } { }
- assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next
+ assign $0\wr_pick_dly$1348[0:0]$2279 \wr_pick_dly$1348$next
sync posedge \coresync_clk
- update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279
+ update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2279
end
- attribute \src "libresoc.v:42918.3-42919.51"
- process $proc$libresoc.v:42918$2280
+ attribute \src "libresoc.v:42878.3-42879.51"
+ process $proc$libresoc.v:42878$2280
assign { } { }
- assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next
+ assign $0\wr_pick_dly$1328[0:0]$2281 \wr_pick_dly$1328$next
sync posedge \coresync_clk
- update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281
+ update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2281
end
- attribute \src "libresoc.v:42920.3-42921.51"
- process $proc$libresoc.v:42920$2282
+ attribute \src "libresoc.v:42880.3-42881.51"
+ process $proc$libresoc.v:42880$2282
assign { } { }
- assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next
+ assign $0\wr_pick_dly$1308[0:0]$2283 \wr_pick_dly$1308$next
sync posedge \coresync_clk
- update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283
+ update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2283
end
- attribute \src "libresoc.v:42922.3-42923.51"
- process $proc$libresoc.v:42922$2284
+ attribute \src "libresoc.v:42882.3-42883.51"
+ process $proc$libresoc.v:42882$2284
assign { } { }
- assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next
+ assign $0\wr_pick_dly$1288[0:0]$2285 \wr_pick_dly$1288$next
sync posedge \coresync_clk
- update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285
+ update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2285
end
- attribute \src "libresoc.v:42924.3-42925.51"
- process $proc$libresoc.v:42924$2286
+ attribute \src "libresoc.v:42884.3-42885.51"
+ process $proc$libresoc.v:42884$2286
assign { } { }
- assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next
+ assign $0\wr_pick_dly$1268[0:0]$2287 \wr_pick_dly$1268$next
sync posedge \coresync_clk
- update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287
+ update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2287
end
- attribute \src "libresoc.v:42926.3-42927.51"
- process $proc$libresoc.v:42926$2288
+ attribute \src "libresoc.v:42886.3-42887.51"
+ process $proc$libresoc.v:42886$2288
assign { } { }
- assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next
+ assign $0\wr_pick_dly$1248[0:0]$2289 \wr_pick_dly$1248$next
sync posedge \coresync_clk
- update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289
+ update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2289
end
- attribute \src "libresoc.v:42928.3-42929.51"
- process $proc$libresoc.v:42928$2290
+ attribute \src "libresoc.v:42888.3-42889.51"
+ process $proc$libresoc.v:42888$2290
assign { } { }
- assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next
+ assign $0\wr_pick_dly$1220[0:0]$2291 \wr_pick_dly$1220$next
sync posedge \coresync_clk
- update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291
+ update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2291
end
- attribute \src "libresoc.v:42930.3-42931.51"
- process $proc$libresoc.v:42930$2292
+ attribute \src "libresoc.v:42890.3-42891.51"
+ process $proc$libresoc.v:42890$2292
assign { } { }
- assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next
+ assign $0\wr_pick_dly$1146[0:0]$2293 \wr_pick_dly$1146$next
sync posedge \coresync_clk
- update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293
+ update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2293
end
- attribute \src "libresoc.v:42932.3-42933.51"
- process $proc$libresoc.v:42932$2294
+ attribute \src "libresoc.v:42892.3-42893.51"
+ process $proc$libresoc.v:42892$2294
assign { } { }
- assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next
+ assign $0\wr_pick_dly$1128[0:0]$2295 \wr_pick_dly$1128$next
sync posedge \coresync_clk
- update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295
+ update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2295
end
- attribute \src "libresoc.v:42934.3-42935.51"
- process $proc$libresoc.v:42934$2296
+ attribute \src "libresoc.v:42894.3-42895.51"
+ process $proc$libresoc.v:42894$2296
assign { } { }
- assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next
+ assign $0\wr_pick_dly$1109[0:0]$2297 \wr_pick_dly$1109$next
sync posedge \coresync_clk
- update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297
+ update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2297
end
- attribute \src "libresoc.v:42936.3-42937.51"
- process $proc$libresoc.v:42936$2298
+ attribute \src "libresoc.v:42896.3-42897.51"
+ process $proc$libresoc.v:42896$2298
assign { } { }
- assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next
+ assign $0\wr_pick_dly$1089[0:0]$2299 \wr_pick_dly$1089$next
sync posedge \coresync_clk
- update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299
+ update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2299
end
- attribute \src "libresoc.v:42938.3-42939.51"
- process $proc$libresoc.v:42938$2300
+ attribute \src "libresoc.v:42898.3-42899.51"
+ process $proc$libresoc.v:42898$2300
assign { } { }
- assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next
+ assign $0\wr_pick_dly$1069[0:0]$2301 \wr_pick_dly$1069$next
sync posedge \coresync_clk
- update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301
+ update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2301
end
- attribute \src "libresoc.v:42940.3-42941.51"
- process $proc$libresoc.v:42940$2302
+ attribute \src "libresoc.v:42900.3-42901.51"
+ process $proc$libresoc.v:42900$2302
assign { } { }
- assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next
+ assign $0\wr_pick_dly$1047[0:0]$2303 \wr_pick_dly$1047$next
sync posedge \coresync_clk
- update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303
+ update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2303
end
- attribute \src "libresoc.v:42942.3-42943.51"
- process $proc$libresoc.v:42942$2304
+ attribute \src "libresoc.v:42902.3-42903.51"
+ process $proc$libresoc.v:42902$2304
assign { } { }
- assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next
+ assign $0\wr_pick_dly$1029[0:0]$2305 \wr_pick_dly$1029$next
sync posedge \coresync_clk
- update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305
+ update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2305
end
- attribute \src "libresoc.v:42944.3-42945.51"
- process $proc$libresoc.v:42944$2306
+ attribute \src "libresoc.v:42904.3-42905.51"
+ process $proc$libresoc.v:42904$2306
assign { } { }
- assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next
+ assign $0\wr_pick_dly$1008[0:0]$2307 \wr_pick_dly$1008$next
sync posedge \coresync_clk
- update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307
+ update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2307
end
- attribute \src "libresoc.v:42946.3-42947.49"
- process $proc$libresoc.v:42946$2308
+ attribute \src "libresoc.v:42906.3-42907.49"
+ process $proc$libresoc.v:42906$2308
assign { } { }
- assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next
+ assign $0\wr_pick_dly$989[0:0]$2309 \wr_pick_dly$989$next
sync posedge \coresync_clk
- update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309
+ update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$2309
end
- attribute \src "libresoc.v:42948.3-42949.39"
- process $proc$libresoc.v:42948$2310
+ attribute \src "libresoc.v:42908.3-42909.39"
+ process $proc$libresoc.v:42908$2310
assign { } { }
assign $0\wr_pick_dly[0:0] \wr_pick_dly$next
sync posedge \coresync_clk
update \wr_pick_dly $0\wr_pick_dly[0:0]
end
- attribute \src "libresoc.v:42950.3-42951.53"
- process $proc$libresoc.v:42950$2311
+ attribute \src "libresoc.v:42910.3-42911.53"
+ process $proc$libresoc.v:42910$2311
assign { } { }
assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next
sync posedge \coresync_clk
update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0]
end
- attribute \src "libresoc.v:42952.3-42953.59"
- process $proc$libresoc.v:42952$2312
+ attribute \src "libresoc.v:42912.3-42913.59"
+ process $proc$libresoc.v:42912$2312
assign { } { }
- assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next
+ assign $0\dp_FAST_fast1_trap0_4[0:0] \dp_FAST_fast1_trap0_4$next
sync posedge \coresync_clk
- update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0]
+ update \dp_FAST_fast1_trap0_4 $0\dp_FAST_fast1_trap0_4[0:0]
end
- attribute \src "libresoc.v:42954.3-42955.63"
- process $proc$libresoc.v:42954$2313
+ attribute \src "libresoc.v:42914.3-42915.63"
+ process $proc$libresoc.v:42914$2313
assign { } { }
- assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next
+ assign $0\dp_FAST_fast1_branch0_3[0:0] \dp_FAST_fast1_branch0_3$next
sync posedge \coresync_clk
- update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0]
+ update \dp_FAST_fast1_branch0_3 $0\dp_FAST_fast1_branch0_3[0:0]
end
- attribute \src "libresoc.v:42956.3-42957.57"
- process $proc$libresoc.v:42956$2314
+ attribute \src "libresoc.v:42916.3-42917.57"
+ process $proc$libresoc.v:42916$2314
assign { } { }
assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next
sync posedge \coresync_clk
update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0]
end
- attribute \src "libresoc.v:42958.3-42959.59"
- process $proc$libresoc.v:42958$2315
+ attribute \src "libresoc.v:42918.3-42919.59"
+ process $proc$libresoc.v:42918$2315
assign { } { }
assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next
sync posedge \coresync_clk
update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0]
end
- attribute \src "libresoc.v:42960.3-42961.63"
- process $proc$libresoc.v:42960$2316
+ attribute \src "libresoc.v:42920.3-42921.63"
+ process $proc$libresoc.v:42920$2316
assign { } { }
assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next
sync posedge \coresync_clk
update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0]
end
- attribute \src "libresoc.v:42962.3-42963.49"
- process $proc$libresoc.v:42962$2317
+ attribute \src "libresoc.v:42922.3-42923.49"
+ process $proc$libresoc.v:42922$2317
assign { } { }
assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next
sync posedge \coresync_clk
update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0]
end
- attribute \src "libresoc.v:42964.3-42965.49"
- process $proc$libresoc.v:42964$2318
+ attribute \src "libresoc.v:42924.3-42925.49"
+ process $proc$libresoc.v:42924$2318
assign { } { }
assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next
sync posedge \coresync_clk
update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0]
end
- attribute \src "libresoc.v:42966.3-42967.57"
- process $proc$libresoc.v:42966$2319
+ attribute \src "libresoc.v:42926.3-42927.57"
+ process $proc$libresoc.v:42926$2319
assign { } { }
assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next
sync posedge \coresync_clk
update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0]
end
- attribute \src "libresoc.v:42968.3-42969.49"
- process $proc$libresoc.v:42968$2320
+ attribute \src "libresoc.v:42928.3-42929.49"
+ process $proc$libresoc.v:42928$2320
assign { } { }
assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next
sync posedge \coresync_clk
update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0]
end
- attribute \src "libresoc.v:42970.3-42971.55"
- process $proc$libresoc.v:42970$2321
+ attribute \src "libresoc.v:42930.3-42931.55"
+ process $proc$libresoc.v:42930$2321
assign { } { }
assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next
sync posedge \coresync_clk
update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0]
end
- attribute \src "libresoc.v:42972.3-42973.57"
- process $proc$libresoc.v:42972$2322
+ attribute \src "libresoc.v:42932.3-42933.57"
+ process $proc$libresoc.v:42932$2322
assign { } { }
assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next
sync posedge \coresync_clk
update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0]
end
- attribute \src "libresoc.v:42974.3-42975.67"
- process $proc$libresoc.v:42974$2323
+ attribute \src "libresoc.v:42934.3-42935.67"
+ process $proc$libresoc.v:42934$2323
assign { } { }
assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next
sync posedge \coresync_clk
update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0]
end
- attribute \src "libresoc.v:42976.3-42977.57"
- process $proc$libresoc.v:42976$2324
+ attribute \src "libresoc.v:42936.3-42937.57"
+ process $proc$libresoc.v:42936$2324
assign { } { }
assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next
sync posedge \coresync_clk
update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0]
end
- attribute \src "libresoc.v:42978.3-42979.57"
- process $proc$libresoc.v:42978$2325
+ attribute \src "libresoc.v:42938.3-42939.57"
+ process $proc$libresoc.v:42938$2325
assign { } { }
assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next
sync posedge \coresync_clk
update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0]
end
- attribute \src "libresoc.v:42980.3-42981.67"
- process $proc$libresoc.v:42980$2326
+ attribute \src "libresoc.v:42940.3-42941.67"
+ process $proc$libresoc.v:42940$2326
assign { } { }
assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next
sync posedge \coresync_clk
update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0]
end
- attribute \src "libresoc.v:42982.3-42983.57"
- process $proc$libresoc.v:42982$2327
+ attribute \src "libresoc.v:42942.3-42943.57"
+ process $proc$libresoc.v:42942$2327
assign { } { }
assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next
sync posedge \coresync_clk
update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0]
end
- attribute \src "libresoc.v:42984.3-42985.57"
- process $proc$libresoc.v:42984$2328
+ attribute \src "libresoc.v:42944.3-42945.57"
+ process $proc$libresoc.v:42944$2328
assign { } { }
assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next
sync posedge \coresync_clk
update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0]
end
- attribute \src "libresoc.v:42986.3-42987.57"
- process $proc$libresoc.v:42986$2329
+ attribute \src "libresoc.v:42946.3-42947.57"
+ process $proc$libresoc.v:42946$2329
assign { } { }
assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next
sync posedge \coresync_clk
update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0]
end
- attribute \src "libresoc.v:42988.3-42989.65"
- process $proc$libresoc.v:42988$2330
+ attribute \src "libresoc.v:42948.3-42949.65"
+ process $proc$libresoc.v:42948$2330
assign { } { }
assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next
sync posedge \coresync_clk
update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0]
end
- attribute \src "libresoc.v:42990.3-42991.57"
- process $proc$libresoc.v:42990$2331
+ attribute \src "libresoc.v:42950.3-42951.57"
+ process $proc$libresoc.v:42950$2331
assign { } { }
assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next
sync posedge \coresync_clk
update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0]
end
- attribute \src "libresoc.v:42992.3-42993.51"
- process $proc$libresoc.v:42992$2332
+ attribute \src "libresoc.v:42952.3-42953.57"
+ process $proc$libresoc.v:42952$2332
assign { } { }
- assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next
+ assign $0\dp_INT_rabc_ldst0_18[0:0] \dp_INT_rabc_ldst0_18$next
sync posedge \coresync_clk
- update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0]
+ update \dp_INT_rabc_ldst0_18 $0\dp_INT_rabc_ldst0_18[0:0]
end
- attribute \src "libresoc.v:42994.3-42995.59"
- process $proc$libresoc.v:42994$2333
+ attribute \src "libresoc.v:42954.3-42955.65"
+ process $proc$libresoc.v:42954$2333
assign { } { }
- assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next
+ assign $0\dp_INT_rabc_shiftrot0_17[0:0] \dp_INT_rabc_shiftrot0_17$next
sync posedge \coresync_clk
- update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0]
+ update \dp_INT_rabc_shiftrot0_17 $0\dp_INT_rabc_shiftrot0_17[0:0]
end
- attribute \src "libresoc.v:42996.3-42997.51"
- process $proc$libresoc.v:42996$2334
+ attribute \src "libresoc.v:42956.3-42957.55"
+ process $proc$libresoc.v:42956$2334
assign { } { }
- assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next
+ assign $0\dp_INT_rabc_mul0_16[0:0] \dp_INT_rabc_mul0_16$next
sync posedge \coresync_clk
- update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0]
+ update \dp_INT_rabc_mul0_16 $0\dp_INT_rabc_mul0_16[0:0]
end
- attribute \src "libresoc.v:42998.3-42999.59"
- process $proc$libresoc.v:42998$2335
+ attribute \src "libresoc.v:42958.3-42959.55"
+ process $proc$libresoc.v:42958$2335
assign { } { }
- assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next
+ assign $0\dp_INT_rabc_div0_15[0:0] \dp_INT_rabc_div0_15$next
sync posedge \coresync_clk
- update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0]
+ update \dp_INT_rabc_div0_15 $0\dp_INT_rabc_div0_15[0:0]
end
- attribute \src "libresoc.v:43000.3-43001.49"
- process $proc$libresoc.v:43000$2336
+ attribute \src "libresoc.v:42960.3-42961.55"
+ process $proc$libresoc.v:42960$2336
assign { } { }
- assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next
+ assign $0\dp_INT_rabc_spr0_14[0:0] \dp_INT_rabc_spr0_14$next
sync posedge \coresync_clk
- update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0]
+ update \dp_INT_rabc_spr0_14 $0\dp_INT_rabc_spr0_14[0:0]
end
- attribute \src "libresoc.v:43002.3-43003.49"
- process $proc$libresoc.v:43002$2337
+ attribute \src "libresoc.v:42962.3-42963.63"
+ process $proc$libresoc.v:42962$2337
assign { } { }
- assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next
+ assign $0\dp_INT_rabc_logical0_13[0:0] \dp_INT_rabc_logical0_13$next
sync posedge \coresync_clk
- update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0]
+ update \dp_INT_rabc_logical0_13 $0\dp_INT_rabc_logical0_13[0:0]
end
- attribute \src "libresoc.v:43004.3-43005.57"
- process $proc$libresoc.v:43004$2338
+ attribute \src "libresoc.v:42964.3-42965.57"
+ process $proc$libresoc.v:42964$2338
assign { } { }
- assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next
+ assign $0\dp_INT_rabc_trap0_12[0:0] \dp_INT_rabc_trap0_12$next
sync posedge \coresync_clk
- update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0]
+ update \dp_INT_rabc_trap0_12 $0\dp_INT_rabc_trap0_12[0:0]
end
- attribute \src "libresoc.v:43006.3-43007.51"
- process $proc$libresoc.v:43006$2339
+ attribute \src "libresoc.v:42966.3-42967.53"
+ process $proc$libresoc.v:42966$2339
assign { } { }
- assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next
+ assign $0\dp_INT_rabc_cr0_11[0:0] \dp_INT_rabc_cr0_11$next
sync posedge \coresync_clk
- update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0]
+ update \dp_INT_rabc_cr0_11 $0\dp_INT_rabc_cr0_11[0:0]
end
- attribute \src "libresoc.v:43008.3-43009.47"
- process $proc$libresoc.v:43008$2340
+ attribute \src "libresoc.v:42968.3-42969.55"
+ process $proc$libresoc.v:42968$2340
assign { } { }
- assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next
+ assign $0\dp_INT_rabc_alu0_10[0:0] \dp_INT_rabc_alu0_10$next
sync posedge \coresync_clk
- update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0]
+ update \dp_INT_rabc_alu0_10 $0\dp_INT_rabc_alu0_10[0:0]
end
- attribute \src "libresoc.v:43010.3-43011.49"
- process $proc$libresoc.v:43010$2341
+ attribute \src "libresoc.v:42970.3-42971.55"
+ process $proc$libresoc.v:42970$2341
assign { } { }
- assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next
+ assign $0\dp_INT_rabc_ldst0_9[0:0] \dp_INT_rabc_ldst0_9$next
sync posedge \coresync_clk
- update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0]
+ update \dp_INT_rabc_ldst0_9 $0\dp_INT_rabc_ldst0_9[0:0]
end
- attribute \src "libresoc.v:43012.3-43013.51"
- process $proc$libresoc.v:43012$2342
+ attribute \src "libresoc.v:42972.3-42973.63"
+ process $proc$libresoc.v:42972$2342
assign { } { }
- assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next
+ assign $0\dp_INT_rabc_shiftrot0_8[0:0] \dp_INT_rabc_shiftrot0_8$next
sync posedge \coresync_clk
- update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0]
+ update \dp_INT_rabc_shiftrot0_8 $0\dp_INT_rabc_shiftrot0_8[0:0]
end
- attribute \src "libresoc.v:43014.3-43015.59"
- process $proc$libresoc.v:43014$2343
+ attribute \src "libresoc.v:42974.3-42975.55"
+ process $proc$libresoc.v:42974$2343
assign { } { }
- assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next
+ assign $0\dp_INT_rabc_ldst0_7[0:0] \dp_INT_rabc_ldst0_7$next
sync posedge \coresync_clk
- update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0]
+ update \dp_INT_rabc_ldst0_7 $0\dp_INT_rabc_ldst0_7[0:0]
end
- attribute \src "libresoc.v:43016.3-43017.49"
- process $proc$libresoc.v:43016$2344
+ attribute \src "libresoc.v:42976.3-42977.63"
+ process $proc$libresoc.v:42976$2344
assign { } { }
- assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next
+ assign $0\dp_INT_rabc_shiftrot0_6[0:0] \dp_INT_rabc_shiftrot0_6$next
sync posedge \coresync_clk
- update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0]
+ update \dp_INT_rabc_shiftrot0_6 $0\dp_INT_rabc_shiftrot0_6[0:0]
end
- attribute \src "libresoc.v:43018.3-43019.49"
- process $proc$libresoc.v:43018$2345
+ attribute \src "libresoc.v:42978.3-42979.53"
+ process $proc$libresoc.v:42978$2345
assign { } { }
- assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next
+ assign $0\dp_INT_rabc_mul0_5[0:0] \dp_INT_rabc_mul0_5$next
sync posedge \coresync_clk
- update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0]
+ update \dp_INT_rabc_mul0_5 $0\dp_INT_rabc_mul0_5[0:0]
end
- attribute \src "libresoc.v:43020.3-43021.49"
- process $proc$libresoc.v:43020$2346
+ attribute \src "libresoc.v:42980.3-42981.53"
+ process $proc$libresoc.v:42980$2346
assign { } { }
- assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next
+ assign $0\dp_INT_rabc_div0_4[0:0] \dp_INT_rabc_div0_4$next
sync posedge \coresync_clk
- update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0]
+ update \dp_INT_rabc_div0_4 $0\dp_INT_rabc_div0_4[0:0]
end
- attribute \src "libresoc.v:43022.3-43023.57"
- process $proc$libresoc.v:43022$2347
+ attribute \src "libresoc.v:42982.3-42983.61"
+ process $proc$libresoc.v:42982$2347
assign { } { }
- assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next
+ assign $0\dp_INT_rabc_logical0_3[0:0] \dp_INT_rabc_logical0_3$next
sync posedge \coresync_clk
- update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0]
+ update \dp_INT_rabc_logical0_3 $0\dp_INT_rabc_logical0_3[0:0]
end
- attribute \src "libresoc.v:43024.3-43025.51"
- process $proc$libresoc.v:43024$2348
+ attribute \src "libresoc.v:42984.3-42985.55"
+ process $proc$libresoc.v:42984$2348
assign { } { }
- assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next
+ assign $0\dp_INT_rabc_trap0_2[0:0] \dp_INT_rabc_trap0_2$next
sync posedge \coresync_clk
- update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0]
+ update \dp_INT_rabc_trap0_2 $0\dp_INT_rabc_trap0_2[0:0]
end
- attribute \src "libresoc.v:43026.3-43027.47"
- process $proc$libresoc.v:43026$2349
+ attribute \src "libresoc.v:42986.3-42987.51"
+ process $proc$libresoc.v:42986$2349
assign { } { }
- assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next
+ assign $0\dp_INT_rabc_cr0_1[0:0] \dp_INT_rabc_cr0_1$next
sync posedge \coresync_clk
- update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0]
+ update \dp_INT_rabc_cr0_1 $0\dp_INT_rabc_cr0_1[0:0]
end
- attribute \src "libresoc.v:43028.3-43029.49"
- process $proc$libresoc.v:43028$2350
+ attribute \src "libresoc.v:42988.3-42989.53"
+ process $proc$libresoc.v:42988$2350
assign { } { }
- assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next
+ assign $0\dp_INT_rabc_alu0_0[0:0] \dp_INT_rabc_alu0_0$next
sync posedge \coresync_clk
- update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0]
+ update \dp_INT_rabc_alu0_0 $0\dp_INT_rabc_alu0_0[0:0]
end
- attribute \src "libresoc.v:43030.3-43031.49"
- process $proc$libresoc.v:43030$2351
+ attribute \src "libresoc.v:42990.3-42991.49"
+ process $proc$libresoc.v:42990$2351
assign { } { }
assign $0\core_terminate_o[0:0] \core_terminate_o$next
sync posedge \coresync_clk
update \core_terminate_o $0\core_terminate_o[0:0]
end
- attribute \src "libresoc.v:43032.3-43033.31"
- process $proc$libresoc.v:43032$2352
+ attribute \src "libresoc.v:42992.3-42993.31"
+ process $proc$libresoc.v:42992$2352
assign { } { }
assign $0\counter[1:0] \counter$next
sync posedge \coresync_clk
update \counter $0\counter[1:0]
end
- attribute \src "libresoc.v:43771.3-43799.6"
- process $proc$libresoc.v:43771$2353
+ attribute \src "libresoc.v:43707.3-43735.6"
+ process $proc$libresoc.v:43707$2353
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "libresoc.v:43772.5-43772.29"
+ attribute \src "libresoc.v:43708.5-43708.29"
switch \initial
- attribute \src "libresoc.v:43772.9-43772.17"
+ attribute \src "libresoc.v:43708.9-43708.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0]
end
- attribute \src "libresoc.v:43800.3-43828.6"
- process $proc$libresoc.v:43800$2354
+ attribute \src "libresoc.v:43736.3-43764.6"
+ process $proc$libresoc.v:43736$2354
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "libresoc.v:43801.5-43801.29"
+ attribute \src "libresoc.v:43737.5-43737.29"
switch \initial
- attribute \src "libresoc.v:43801.9-43801.17"
+ attribute \src "libresoc.v:43737.9-43737.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0]
end
- attribute \src "libresoc.v:43829.3-43857.6"
- process $proc$libresoc.v:43829$2355
+ attribute \src "libresoc.v:43765.3-43793.6"
+ process $proc$libresoc.v:43765$2355
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "libresoc.v:43830.5-43830.29"
+ attribute \src "libresoc.v:43766.5-43766.29"
switch \initial
- attribute \src "libresoc.v:43830.9-43830.17"
+ attribute \src "libresoc.v:43766.9-43766.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0]
end
- attribute \src "libresoc.v:43858.3-43886.6"
- process $proc$libresoc.v:43858$2356
+ attribute \src "libresoc.v:43794.3-43822.6"
+ process $proc$libresoc.v:43794$2356
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "libresoc.v:43859.5-43859.29"
+ attribute \src "libresoc.v:43795.5-43795.29"
switch \initial
- attribute \src "libresoc.v:43859.9-43859.17"
+ attribute \src "libresoc.v:43795.9-43795.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0]
end
- attribute \src "libresoc.v:43887.3-43915.6"
- process $proc$libresoc.v:43887$2357
+ attribute \src "libresoc.v:43823.3-43851.6"
+ process $proc$libresoc.v:43823$2357
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "libresoc.v:43888.5-43888.29"
+ attribute \src "libresoc.v:43824.5-43824.29"
switch \initial
- attribute \src "libresoc.v:43888.9-43888.17"
+ attribute \src "libresoc.v:43824.9-43824.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0]
end
- attribute \src "libresoc.v:43916.3-43944.6"
- process $proc$libresoc.v:43916$2358
+ attribute \src "libresoc.v:43852.3-43880.6"
+ process $proc$libresoc.v:43852$2358
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360
- attribute \src "libresoc.v:43917.5-43917.29"
+ attribute \src "libresoc.v:43853.5-43853.29"
switch \initial
- attribute \src "libresoc.v:43917.9-43917.17"
+ attribute \src "libresoc.v:43853.9-43853.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359
end
- attribute \src "libresoc.v:43945.3-43973.6"
- process $proc$libresoc.v:43945$2363
+ attribute \src "libresoc.v:43881.3-43909.6"
+ process $proc$libresoc.v:43881$2363
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365
- attribute \src "libresoc.v:43946.5-43946.29"
+ attribute \src "libresoc.v:43882.5-43882.29"
switch \initial
- attribute \src "libresoc.v:43946.9-43946.17"
+ attribute \src "libresoc.v:43882.9-43882.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364
end
- attribute \src "libresoc.v:43974.3-44002.6"
- process $proc$libresoc.v:43974$2368
+ attribute \src "libresoc.v:43910.3-43938.6"
+ process $proc$libresoc.v:43910$2368
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "libresoc.v:43975.5-43975.29"
+ attribute \src "libresoc.v:43911.5-43911.29"
switch \initial
- attribute \src "libresoc.v:43975.9-43975.17"
+ attribute \src "libresoc.v:43911.9-43911.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0]
end
- attribute \src "libresoc.v:44003.3-44031.6"
- process $proc$libresoc.v:44003$2369
+ attribute \src "libresoc.v:43939.3-43967.6"
+ process $proc$libresoc.v:43939$2369
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "libresoc.v:44004.5-44004.29"
+ attribute \src "libresoc.v:43940.5-43940.29"
switch \initial
- attribute \src "libresoc.v:44004.9-44004.17"
+ attribute \src "libresoc.v:43940.9-43940.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0]
end
- attribute \src "libresoc.v:44032.3-44060.6"
- process $proc$libresoc.v:44032$2370
+ attribute \src "libresoc.v:43968.3-43996.6"
+ process $proc$libresoc.v:43968$2370
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "libresoc.v:44033.5-44033.29"
+ attribute \src "libresoc.v:43969.5-43969.29"
switch \initial
- attribute \src "libresoc.v:44033.9-44033.17"
+ attribute \src "libresoc.v:43969.9-43969.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0]
end
- attribute \src "libresoc.v:44061.3-44089.6"
- process $proc$libresoc.v:44061$2371
+ attribute \src "libresoc.v:43997.3-44025.6"
+ process $proc$libresoc.v:43997$2371
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "libresoc.v:44062.5-44062.29"
+ attribute \src "libresoc.v:43998.5-43998.29"
switch \initial
- attribute \src "libresoc.v:44062.9-44062.17"
+ attribute \src "libresoc.v:43998.9-43998.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0]
end
- attribute \src "libresoc.v:44090.3-44118.6"
- process $proc$libresoc.v:44090$2372
+ attribute \src "libresoc.v:44026.3-44054.6"
+ process $proc$libresoc.v:44026$2372
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374
- attribute \src "libresoc.v:44091.5-44091.29"
+ attribute \src "libresoc.v:44027.5-44027.29"
switch \initial
- attribute \src "libresoc.v:44091.9-44091.17"
+ attribute \src "libresoc.v:44027.9-44027.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373
end
- attribute \src "libresoc.v:44119.3-44147.6"
- process $proc$libresoc.v:44119$2377
+ attribute \src "libresoc.v:44055.3-44083.6"
+ process $proc$libresoc.v:44055$2377
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379
- attribute \src "libresoc.v:44120.5-44120.29"
+ attribute \src "libresoc.v:44056.5-44056.29"
switch \initial
- attribute \src "libresoc.v:44120.9-44120.17"
+ attribute \src "libresoc.v:44056.9-44056.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378
end
- attribute \src "libresoc.v:44148.3-44176.6"
- process $proc$libresoc.v:44148$2382
+ attribute \src "libresoc.v:44084.3-44112.6"
+ process $proc$libresoc.v:44084$2382
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "libresoc.v:44149.5-44149.29"
+ attribute \src "libresoc.v:44085.5-44085.29"
switch \initial
- attribute \src "libresoc.v:44149.9-44149.17"
+ attribute \src "libresoc.v:44085.9-44085.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0]
end
- attribute \src "libresoc.v:44177.3-44205.6"
- process $proc$libresoc.v:44177$2383
+ attribute \src "libresoc.v:44113.3-44141.6"
+ process $proc$libresoc.v:44113$2383
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "libresoc.v:44178.5-44178.29"
+ attribute \src "libresoc.v:44114.5-44114.29"
switch \initial
- attribute \src "libresoc.v:44178.9-44178.17"
+ attribute \src "libresoc.v:44114.9-44114.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0]
end
- attribute \src "libresoc.v:44206.3-44235.6"
- process $proc$libresoc.v:44206$2384
+ attribute \src "libresoc.v:44142.3-44171.6"
+ process $proc$libresoc.v:44142$2384
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44207.5-44207.29"
+ attribute \src "libresoc.v:44143.5-44143.29"
switch \initial
- attribute \src "libresoc.v:44207.9-44207.17"
+ attribute \src "libresoc.v:44143.9-44143.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0]
update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:44236.3-44265.6"
- process $proc$libresoc.v:44236$2385
+ attribute \src "libresoc.v:44172.3-44201.6"
+ process $proc$libresoc.v:44172$2385
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0]
assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "libresoc.v:44237.5-44237.29"
+ attribute \src "libresoc.v:44173.5-44173.29"
switch \initial
- attribute \src "libresoc.v:44237.9-44237.17"
+ attribute \src "libresoc.v:44173.9-44173.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0]
assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0]
assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0]
update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0]
end
- attribute \src "libresoc.v:44266.3-44295.6"
- process $proc$libresoc.v:44266$2386
+ attribute \src "libresoc.v:44202.3-44231.6"
+ process $proc$libresoc.v:44202$2386
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0]
assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "libresoc.v:44267.5-44267.29"
+ attribute \src "libresoc.v:44203.5-44203.29"
switch \initial
- attribute \src "libresoc.v:44267.9-44267.17"
+ attribute \src "libresoc.v:44203.9-44203.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0]
assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0]
assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0]
update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0]
end
- attribute \src "libresoc.v:44296.3-44324.6"
- process $proc$libresoc.v:44296$2387
+ attribute \src "libresoc.v:44232.3-44260.6"
+ process $proc$libresoc.v:44232$2387
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "libresoc.v:44297.5-44297.29"
+ attribute \src "libresoc.v:44233.5-44233.29"
switch \initial
- attribute \src "libresoc.v:44297.9-44297.17"
+ attribute \src "libresoc.v:44233.9-44233.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0]
end
- attribute \src "libresoc.v:44325.3-44353.6"
- process $proc$libresoc.v:44325$2388
+ attribute \src "libresoc.v:44261.3-44289.6"
+ process $proc$libresoc.v:44261$2388
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "libresoc.v:44326.5-44326.29"
+ attribute \src "libresoc.v:44262.5-44262.29"
switch \initial
- attribute \src "libresoc.v:44326.9-44326.17"
+ attribute \src "libresoc.v:44262.9-44262.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0]
end
- attribute \src "libresoc.v:44354.3-44382.6"
- process $proc$libresoc.v:44354$2389
+ attribute \src "libresoc.v:44290.3-44318.6"
+ process $proc$libresoc.v:44290$2389
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "libresoc.v:44355.5-44355.29"
+ attribute \src "libresoc.v:44291.5-44291.29"
switch \initial
- attribute \src "libresoc.v:44355.9-44355.17"
+ attribute \src "libresoc.v:44291.9-44291.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0]
end
- attribute \src "libresoc.v:44383.3-44411.6"
- process $proc$libresoc.v:44383$2390
+ attribute \src "libresoc.v:44319.3-44347.6"
+ process $proc$libresoc.v:44319$2390
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "libresoc.v:44384.5-44384.29"
+ attribute \src "libresoc.v:44320.5-44320.29"
switch \initial
- attribute \src "libresoc.v:44384.9-44384.17"
+ attribute \src "libresoc.v:44320.9-44320.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0]
end
- attribute \src "libresoc.v:44412.3-44440.6"
- process $proc$libresoc.v:44412$2391
+ attribute \src "libresoc.v:44348.3-44376.6"
+ process $proc$libresoc.v:44348$2391
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "libresoc.v:44413.5-44413.29"
+ attribute \src "libresoc.v:44349.5-44349.29"
switch \initial
- attribute \src "libresoc.v:44413.9-44413.17"
+ attribute \src "libresoc.v:44349.9-44349.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0]
end
- attribute \src "libresoc.v:44441.3-44469.6"
- process $proc$libresoc.v:44441$2392
+ attribute \src "libresoc.v:44377.3-44405.6"
+ process $proc$libresoc.v:44377$2392
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "libresoc.v:44442.5-44442.29"
+ attribute \src "libresoc.v:44378.5-44378.29"
switch \initial
- attribute \src "libresoc.v:44442.9-44442.17"
+ attribute \src "libresoc.v:44378.9-44378.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0]
end
- attribute \src "libresoc.v:44470.3-44498.6"
- process $proc$libresoc.v:44470$2393
+ attribute \src "libresoc.v:44406.3-44434.6"
+ process $proc$libresoc.v:44406$2393
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "libresoc.v:44471.5-44471.29"
+ attribute \src "libresoc.v:44407.5-44407.29"
switch \initial
- attribute \src "libresoc.v:44471.9-44471.17"
+ attribute \src "libresoc.v:44407.9-44407.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0]
end
- attribute \src "libresoc.v:44499.3-44527.6"
- process $proc$libresoc.v:44499$2394
+ attribute \src "libresoc.v:44435.3-44463.6"
+ process $proc$libresoc.v:44435$2394
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "libresoc.v:44500.5-44500.29"
+ attribute \src "libresoc.v:44436.5-44436.29"
switch \initial
- attribute \src "libresoc.v:44500.9-44500.17"
+ attribute \src "libresoc.v:44436.9-44436.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0]
end
- attribute \src "libresoc.v:44528.3-44556.6"
- process $proc$libresoc.v:44528$2395
+ attribute \src "libresoc.v:44464.3-44492.6"
+ process $proc$libresoc.v:44464$2395
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "libresoc.v:44529.5-44529.29"
+ attribute \src "libresoc.v:44465.5-44465.29"
switch \initial
- attribute \src "libresoc.v:44529.9-44529.17"
+ attribute \src "libresoc.v:44465.9-44465.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0]
end
- attribute \src "libresoc.v:44557.3-44585.6"
- process $proc$libresoc.v:44557$2396
+ attribute \src "libresoc.v:44493.3-44521.6"
+ process $proc$libresoc.v:44493$2396
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "libresoc.v:44558.5-44558.29"
+ attribute \src "libresoc.v:44494.5-44494.29"
switch \initial
- attribute \src "libresoc.v:44558.9-44558.17"
+ attribute \src "libresoc.v:44494.9-44494.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0]
end
- attribute \src "libresoc.v:44586.3-44614.6"
- process $proc$libresoc.v:44586$2397
+ attribute \src "libresoc.v:44522.3-44550.6"
+ process $proc$libresoc.v:44522$2397
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399
- attribute \src "libresoc.v:44587.5-44587.29"
+ attribute \src "libresoc.v:44523.5-44523.29"
switch \initial
- attribute \src "libresoc.v:44587.9-44587.17"
+ attribute \src "libresoc.v:44523.9-44523.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398
end
- attribute \src "libresoc.v:44615.3-44643.6"
- process $proc$libresoc.v:44615$2402
+ attribute \src "libresoc.v:44551.3-44579.6"
+ process $proc$libresoc.v:44551$2402
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404
- attribute \src "libresoc.v:44616.5-44616.29"
+ attribute \src "libresoc.v:44552.5-44552.29"
switch \initial
- attribute \src "libresoc.v:44616.9-44616.17"
+ attribute \src "libresoc.v:44552.9-44552.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403
end
- attribute \src "libresoc.v:44644.3-44672.6"
- process $proc$libresoc.v:44644$2407
+ attribute \src "libresoc.v:44580.3-44608.6"
+ process $proc$libresoc.v:44580$2407
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "libresoc.v:44645.5-44645.29"
+ attribute \src "libresoc.v:44581.5-44581.29"
switch \initial
- attribute \src "libresoc.v:44645.9-44645.17"
+ attribute \src "libresoc.v:44581.9-44581.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0]
end
- attribute \src "libresoc.v:44673.3-44701.6"
- process $proc$libresoc.v:44673$2408
+ attribute \src "libresoc.v:44609.3-44637.6"
+ process $proc$libresoc.v:44609$2408
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "libresoc.v:44674.5-44674.29"
+ attribute \src "libresoc.v:44610.5-44610.29"
switch \initial
- attribute \src "libresoc.v:44674.9-44674.17"
+ attribute \src "libresoc.v:44610.9-44610.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0]
end
- attribute \src "libresoc.v:44702.3-44731.6"
- process $proc$libresoc.v:44702$2409
+ attribute \src "libresoc.v:44638.3-44667.6"
+ process $proc$libresoc.v:44638$2409
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "libresoc.v:44703.5-44703.29"
+ attribute \src "libresoc.v:44639.5-44639.29"
switch \initial
- attribute \src "libresoc.v:44703.9-44703.17"
+ attribute \src "libresoc.v:44639.9-44639.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0]
update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:44732.3-44761.6"
- process $proc$libresoc.v:44732$2410
+ attribute \src "libresoc.v:44668.3-44697.6"
+ process $proc$libresoc.v:44668$2410
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0]
assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "libresoc.v:44733.5-44733.29"
+ attribute \src "libresoc.v:44669.5-44669.29"
switch \initial
- attribute \src "libresoc.v:44733.9-44733.17"
+ attribute \src "libresoc.v:44669.9-44669.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0]
assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0]
assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0]
update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0]
end
- attribute \src "libresoc.v:44762.3-44791.6"
- process $proc$libresoc.v:44762$2411
+ attribute \src "libresoc.v:44698.3-44727.6"
+ process $proc$libresoc.v:44698$2411
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0]
assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "libresoc.v:44763.5-44763.29"
+ attribute \src "libresoc.v:44699.5-44699.29"
switch \initial
- attribute \src "libresoc.v:44763.9-44763.17"
+ attribute \src "libresoc.v:44699.9-44699.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0]
assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0]
assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0]
update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0]
end
- attribute \src "libresoc.v:44792.3-44820.6"
- process $proc$libresoc.v:44792$2412
+ attribute \src "libresoc.v:44728.3-44756.6"
+ process $proc$libresoc.v:44728$2412
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "libresoc.v:44793.5-44793.29"
+ attribute \src "libresoc.v:44729.5-44729.29"
switch \initial
- attribute \src "libresoc.v:44793.9-44793.17"
+ attribute \src "libresoc.v:44729.9-44729.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0]
end
- attribute \src "libresoc.v:44821.3-44849.6"
- process $proc$libresoc.v:44821$2413
+ attribute \src "libresoc.v:44757.3-44785.6"
+ process $proc$libresoc.v:44757$2413
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "libresoc.v:44822.5-44822.29"
+ attribute \src "libresoc.v:44758.5-44758.29"
switch \initial
- attribute \src "libresoc.v:44822.9-44822.17"
+ attribute \src "libresoc.v:44758.9-44758.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0]
end
- attribute \src "libresoc.v:44850.3-44878.6"
- process $proc$libresoc.v:44850$2414
+ attribute \src "libresoc.v:44786.3-44814.6"
+ process $proc$libresoc.v:44786$2414
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "libresoc.v:44851.5-44851.29"
+ attribute \src "libresoc.v:44787.5-44787.29"
switch \initial
- attribute \src "libresoc.v:44851.9-44851.17"
+ attribute \src "libresoc.v:44787.9-44787.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0]
end
- attribute \src "libresoc.v:44879.3-44907.6"
- process $proc$libresoc.v:44879$2415
+ attribute \src "libresoc.v:44815.3-44843.6"
+ process $proc$libresoc.v:44815$2415
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "libresoc.v:44880.5-44880.29"
+ attribute \src "libresoc.v:44816.5-44816.29"
switch \initial
- attribute \src "libresoc.v:44880.9-44880.17"
+ attribute \src "libresoc.v:44816.9-44816.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0]
end
- attribute \src "libresoc.v:44908.3-44936.6"
- process $proc$libresoc.v:44908$2416
+ attribute \src "libresoc.v:44844.3-44872.6"
+ process $proc$libresoc.v:44844$2416
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418
- attribute \src "libresoc.v:44909.5-44909.29"
+ attribute \src "libresoc.v:44845.5-44845.29"
switch \initial
- attribute \src "libresoc.v:44909.9-44909.17"
+ attribute \src "libresoc.v:44845.9-44845.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417
end
- attribute \src "libresoc.v:44937.3-44965.6"
- process $proc$libresoc.v:44937$2421
+ attribute \src "libresoc.v:44873.3-44901.6"
+ process $proc$libresoc.v:44873$2421
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423
- attribute \src "libresoc.v:44938.5-44938.29"
+ attribute \src "libresoc.v:44874.5-44874.29"
switch \initial
- attribute \src "libresoc.v:44938.9-44938.17"
+ attribute \src "libresoc.v:44874.9-44874.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422
end
- attribute \src "libresoc.v:44966.3-44994.6"
- process $proc$libresoc.v:44966$2426
+ attribute \src "libresoc.v:44902.3-44930.6"
+ process $proc$libresoc.v:44902$2426
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "libresoc.v:44967.5-44967.29"
+ attribute \src "libresoc.v:44903.5-44903.29"
switch \initial
- attribute \src "libresoc.v:44967.9-44967.17"
+ attribute \src "libresoc.v:44903.9-44903.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0]
end
- attribute \src "libresoc.v:44995.3-45023.6"
- process $proc$libresoc.v:44995$2427
+ attribute \src "libresoc.v:44931.3-44959.6"
+ process $proc$libresoc.v:44931$2427
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "libresoc.v:44996.5-44996.29"
+ attribute \src "libresoc.v:44932.5-44932.29"
switch \initial
- attribute \src "libresoc.v:44996.9-44996.17"
+ attribute \src "libresoc.v:44932.9-44932.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0]
end
- attribute \src "libresoc.v:45024.3-45053.6"
- process $proc$libresoc.v:45024$2428
+ attribute \src "libresoc.v:44960.3-44989.6"
+ process $proc$libresoc.v:44960$2428
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45025.5-45025.29"
+ attribute \src "libresoc.v:44961.5-44961.29"
switch \initial
- attribute \src "libresoc.v:45025.9-45025.17"
+ attribute \src "libresoc.v:44961.9-44961.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0]
update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:45054.3-45083.6"
- process $proc$libresoc.v:45054$2429
+ attribute \src "libresoc.v:44990.3-45019.6"
+ process $proc$libresoc.v:44990$2429
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "libresoc.v:45055.5-45055.29"
+ attribute \src "libresoc.v:44991.5-44991.29"
switch \initial
- attribute \src "libresoc.v:45055.9-45055.17"
+ attribute \src "libresoc.v:44991.9-44991.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0]
update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0]
end
- attribute \src "libresoc.v:45084.3-45113.6"
- process $proc$libresoc.v:45084$2430
+ attribute \src "libresoc.v:45020.3-45049.6"
+ process $proc$libresoc.v:45020$2430
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "libresoc.v:45085.5-45085.29"
+ attribute \src "libresoc.v:45021.5-45021.29"
switch \initial
- attribute \src "libresoc.v:45085.9-45085.17"
+ attribute \src "libresoc.v:45021.9-45021.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0]
update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0]
end
- attribute \src "libresoc.v:45114.3-45142.6"
- process $proc$libresoc.v:45114$2431
+ attribute \src "libresoc.v:45050.3-45078.6"
+ process $proc$libresoc.v:45050$2431
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "libresoc.v:45115.5-45115.29"
+ attribute \src "libresoc.v:45051.5-45051.29"
switch \initial
- attribute \src "libresoc.v:45115.9-45115.17"
+ attribute \src "libresoc.v:45051.9-45051.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0]
end
- attribute \src "libresoc.v:45143.3-45171.6"
- process $proc$libresoc.v:45143$2432
+ attribute \src "libresoc.v:45079.3-45107.6"
+ process $proc$libresoc.v:45079$2432
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "libresoc.v:45144.5-45144.29"
+ attribute \src "libresoc.v:45080.5-45080.29"
switch \initial
- attribute \src "libresoc.v:45144.9-45144.17"
+ attribute \src "libresoc.v:45080.9-45080.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0]
end
- attribute \src "libresoc.v:45172.3-45200.6"
- process $proc$libresoc.v:45172$2433
+ attribute \src "libresoc.v:45108.3-45136.6"
+ process $proc$libresoc.v:45108$2433
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "libresoc.v:45173.5-45173.29"
+ attribute \src "libresoc.v:45109.5-45109.29"
switch \initial
- attribute \src "libresoc.v:45173.9-45173.17"
+ attribute \src "libresoc.v:45109.9-45109.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0]
end
- attribute \src "libresoc.v:45201.3-45229.6"
- process $proc$libresoc.v:45201$2434
+ attribute \src "libresoc.v:45137.3-45165.6"
+ process $proc$libresoc.v:45137$2434
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "libresoc.v:45202.5-45202.29"
+ attribute \src "libresoc.v:45138.5-45138.29"
switch \initial
- attribute \src "libresoc.v:45202.9-45202.17"
+ attribute \src "libresoc.v:45138.9-45138.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0]
end
- attribute \src "libresoc.v:45230.3-45258.6"
- process $proc$libresoc.v:45230$2435
+ attribute \src "libresoc.v:45166.3-45194.6"
+ process $proc$libresoc.v:45166$2435
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "libresoc.v:45231.5-45231.29"
+ attribute \src "libresoc.v:45167.5-45167.29"
switch \initial
- attribute \src "libresoc.v:45231.9-45231.17"
+ attribute \src "libresoc.v:45167.9-45167.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0]
end
- attribute \src "libresoc.v:45259.3-45287.6"
- process $proc$libresoc.v:45259$2436
+ attribute \src "libresoc.v:45195.3-45223.6"
+ process $proc$libresoc.v:45195$2436
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "libresoc.v:45260.5-45260.29"
+ attribute \src "libresoc.v:45196.5-45196.29"
switch \initial
- attribute \src "libresoc.v:45260.9-45260.17"
+ attribute \src "libresoc.v:45196.9-45196.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0]
end
- attribute \src "libresoc.v:45288.3-45316.6"
- process $proc$libresoc.v:45288$2437
+ attribute \src "libresoc.v:45224.3-45252.6"
+ process $proc$libresoc.v:45224$2437
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "libresoc.v:45289.5-45289.29"
+ attribute \src "libresoc.v:45225.5-45225.29"
switch \initial
- attribute \src "libresoc.v:45289.9-45289.17"
+ attribute \src "libresoc.v:45225.9-45225.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0]
end
- attribute \src "libresoc.v:45317.3-45345.6"
- process $proc$libresoc.v:45317$2438
+ attribute \src "libresoc.v:45253.3-45281.6"
+ process $proc$libresoc.v:45253$2438
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "libresoc.v:45318.5-45318.29"
+ attribute \src "libresoc.v:45254.5-45254.29"
switch \initial
- attribute \src "libresoc.v:45318.9-45318.17"
+ attribute \src "libresoc.v:45254.9-45254.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0]
end
- attribute \src "libresoc.v:45346.3-45374.6"
- process $proc$libresoc.v:45346$2439
+ attribute \src "libresoc.v:45282.3-45310.6"
+ process $proc$libresoc.v:45282$2439
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "libresoc.v:45347.5-45347.29"
+ attribute \src "libresoc.v:45283.5-45283.29"
switch \initial
- attribute \src "libresoc.v:45347.9-45347.17"
+ attribute \src "libresoc.v:45283.9-45283.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0]
end
- attribute \src "libresoc.v:45375.3-45403.6"
- process $proc$libresoc.v:45375$2440
+ attribute \src "libresoc.v:45311.3-45339.6"
+ process $proc$libresoc.v:45311$2440
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442
- attribute \src "libresoc.v:45376.5-45376.29"
+ attribute \src "libresoc.v:45312.5-45312.29"
switch \initial
- attribute \src "libresoc.v:45376.9-45376.17"
+ attribute \src "libresoc.v:45312.9-45312.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441
end
- attribute \src "libresoc.v:45404.3-45432.6"
- process $proc$libresoc.v:45404$2445
+ attribute \src "libresoc.v:45340.3-45368.6"
+ process $proc$libresoc.v:45340$2445
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447
- attribute \src "libresoc.v:45405.5-45405.29"
+ attribute \src "libresoc.v:45341.5-45341.29"
switch \initial
- attribute \src "libresoc.v:45405.9-45405.17"
+ attribute \src "libresoc.v:45341.9-45341.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446
end
- attribute \src "libresoc.v:45433.3-45461.6"
- process $proc$libresoc.v:45433$2450
+ attribute \src "libresoc.v:45369.3-45397.6"
+ process $proc$libresoc.v:45369$2450
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "libresoc.v:45434.5-45434.29"
+ attribute \src "libresoc.v:45370.5-45370.29"
switch \initial
- attribute \src "libresoc.v:45434.9-45434.17"
+ attribute \src "libresoc.v:45370.9-45370.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0]
end
- attribute \src "libresoc.v:45462.3-45490.6"
- process $proc$libresoc.v:45462$2451
+ attribute \src "libresoc.v:45398.3-45426.6"
+ process $proc$libresoc.v:45398$2451
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "libresoc.v:45463.5-45463.29"
+ attribute \src "libresoc.v:45399.5-45399.29"
switch \initial
- attribute \src "libresoc.v:45463.9-45463.17"
+ attribute \src "libresoc.v:45399.9-45399.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0]
end
- attribute \src "libresoc.v:45491.3-45520.6"
- process $proc$libresoc.v:45491$2452
+ attribute \src "libresoc.v:45427.3-45456.6"
+ process $proc$libresoc.v:45427$2452
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "libresoc.v:45492.5-45492.29"
+ attribute \src "libresoc.v:45428.5-45428.29"
switch \initial
- attribute \src "libresoc.v:45492.9-45492.17"
+ attribute \src "libresoc.v:45428.9-45428.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0]
update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:45521.3-45549.6"
- process $proc$libresoc.v:45521$2453
+ attribute \src "libresoc.v:45457.3-45485.6"
+ process $proc$libresoc.v:45457$2453
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "libresoc.v:45522.5-45522.29"
+ attribute \src "libresoc.v:45458.5-45458.29"
switch \initial
- attribute \src "libresoc.v:45522.9-45522.17"
+ attribute \src "libresoc.v:45458.9-45458.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0]
end
- attribute \src "libresoc.v:45550.3-45579.6"
- process $proc$libresoc.v:45550$2454
+ attribute \src "libresoc.v:45486.3-45515.6"
+ process $proc$libresoc.v:45486$2454
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0]
assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "libresoc.v:45551.5-45551.29"
+ attribute \src "libresoc.v:45487.5-45487.29"
switch \initial
- attribute \src "libresoc.v:45551.9-45551.17"
+ attribute \src "libresoc.v:45487.9-45487.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0]
assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0]
assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0]
update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0]
end
- attribute \src "libresoc.v:45580.3-45609.6"
- process $proc$libresoc.v:45580$2455
+ attribute \src "libresoc.v:45516.3-45545.6"
+ process $proc$libresoc.v:45516$2455
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0]
assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "libresoc.v:45581.5-45581.29"
+ attribute \src "libresoc.v:45517.5-45517.29"
switch \initial
- attribute \src "libresoc.v:45581.9-45581.17"
+ attribute \src "libresoc.v:45517.9-45517.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0]
assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0]
assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0]
update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0]
end
- attribute \src "libresoc.v:45610.3-45638.6"
- process $proc$libresoc.v:45610$2456
+ attribute \src "libresoc.v:45546.3-45574.6"
+ process $proc$libresoc.v:45546$2456
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "libresoc.v:45611.5-45611.29"
+ attribute \src "libresoc.v:45547.5-45547.29"
switch \initial
- attribute \src "libresoc.v:45611.9-45611.17"
+ attribute \src "libresoc.v:45547.9-45547.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0]
end
- attribute \src "libresoc.v:45639.3-45667.6"
- process $proc$libresoc.v:45639$2457
+ attribute \src "libresoc.v:45575.3-45603.6"
+ process $proc$libresoc.v:45575$2457
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "libresoc.v:45640.5-45640.29"
+ attribute \src "libresoc.v:45576.5-45576.29"
switch \initial
- attribute \src "libresoc.v:45640.9-45640.17"
+ attribute \src "libresoc.v:45576.9-45576.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0]
end
- attribute \src "libresoc.v:45668.3-45696.6"
- process $proc$libresoc.v:45668$2458
+ attribute \src "libresoc.v:45604.3-45632.6"
+ process $proc$libresoc.v:45604$2458
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "libresoc.v:45669.5-45669.29"
+ attribute \src "libresoc.v:45605.5-45605.29"
switch \initial
- attribute \src "libresoc.v:45669.9-45669.17"
+ attribute \src "libresoc.v:45605.9-45605.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0]
end
- attribute \src "libresoc.v:45697.3-45725.6"
- process $proc$libresoc.v:45697$2459
+ attribute \src "libresoc.v:45633.3-45661.6"
+ process $proc$libresoc.v:45633$2459
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "libresoc.v:45698.5-45698.29"
+ attribute \src "libresoc.v:45634.5-45634.29"
switch \initial
- attribute \src "libresoc.v:45698.9-45698.17"
+ attribute \src "libresoc.v:45634.9-45634.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0]
end
- attribute \src "libresoc.v:45726.3-45754.6"
- process $proc$libresoc.v:45726$2460
+ attribute \src "libresoc.v:45662.3-45690.6"
+ process $proc$libresoc.v:45662$2460
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "libresoc.v:45727.5-45727.29"
+ attribute \src "libresoc.v:45663.5-45663.29"
switch \initial
- attribute \src "libresoc.v:45727.9-45727.17"
+ attribute \src "libresoc.v:45663.9-45663.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0]
end
- attribute \src "libresoc.v:45755.3-45783.6"
- process $proc$libresoc.v:45755$2461
+ attribute \src "libresoc.v:45691.3-45719.6"
+ process $proc$libresoc.v:45691$2461
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "libresoc.v:45756.5-45756.29"
+ attribute \src "libresoc.v:45692.5-45692.29"
switch \initial
- attribute \src "libresoc.v:45756.9-45756.17"
+ attribute \src "libresoc.v:45692.9-45692.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0]
end
- attribute \src "libresoc.v:45784.3-45812.6"
- process $proc$libresoc.v:45784$2462
+ attribute \src "libresoc.v:45720.3-45748.6"
+ process $proc$libresoc.v:45720$2462
assign { } { }
assign { } { }
assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "libresoc.v:45785.5-45785.29"
+ attribute \src "libresoc.v:45721.5-45721.29"
switch \initial
- attribute \src "libresoc.v:45785.9-45785.17"
+ attribute \src "libresoc.v:45721.9-45721.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0]
end
- attribute \src "libresoc.v:45813.3-45841.6"
- process $proc$libresoc.v:45813$2463
+ attribute \src "libresoc.v:45749.3-45777.6"
+ process $proc$libresoc.v:45749$2463
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465
- attribute \src "libresoc.v:45814.5-45814.29"
+ attribute \src "libresoc.v:45750.5-45750.29"
switch \initial
- attribute \src "libresoc.v:45814.9-45814.17"
+ attribute \src "libresoc.v:45750.9-45750.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464
end
- attribute \src "libresoc.v:45842.3-45870.6"
- process $proc$libresoc.v:45842$2468
+ attribute \src "libresoc.v:45778.3-45806.6"
+ process $proc$libresoc.v:45778$2468
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470
- attribute \src "libresoc.v:45843.5-45843.29"
+ attribute \src "libresoc.v:45779.5-45779.29"
switch \initial
- attribute \src "libresoc.v:45843.9-45843.17"
+ attribute \src "libresoc.v:45779.9-45779.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469
end
- attribute \src "libresoc.v:45871.3-45879.6"
- process $proc$libresoc.v:45871$2473
+ attribute \src "libresoc.v:45807.3-45815.6"
+ process $proc$libresoc.v:45807$2473
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475
- attribute \src "libresoc.v:45872.5-45872.29"
+ assign $0\dp_INT_rabc_alu0_0$next[0:0]$2474 $1\dp_INT_rabc_alu0_0$next[0:0]$2475
+ attribute \src "libresoc.v:45808.5-45808.29"
switch \initial
- attribute \src "libresoc.v:45872.9-45872.17"
+ attribute \src "libresoc.v:45808.9-45808.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 1'0
+ assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 1'0
case
- assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 \rp_INT_ra_alu0_0
+ assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 \rp_INT_rabc_alu0_0
end
sync always
- update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474
+ update \dp_INT_rabc_alu0_0$next $0\dp_INT_rabc_alu0_0$next[0:0]$2474
end
- attribute \src "libresoc.v:45880.3-45889.6"
- process $proc$libresoc.v:45880$2476
+ attribute \src "libresoc.v:45816.3-45825.6"
+ process $proc$libresoc.v:45816$2476
assign { } { }
assign { } { }
- assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0]
- attribute \src "libresoc.v:45881.5-45881.29"
+ assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0]
+ attribute \src "libresoc.v:45817.5-45817.29"
switch \initial
- attribute \src "libresoc.v:45881.9-45881.17"
+ attribute \src "libresoc.v:45817.9-45817.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_alu0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i[63:0] \int_src1__data_o
+ assign $1\fus_src2_i[63:0] \int_src__data_o
case
- assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i $0\fus_src1_i[63:0]
+ update \fus_src2_i $0\fus_src2_i[63:0]
end
- attribute \src "libresoc.v:45890.3-45898.6"
- process $proc$libresoc.v:45890$2477
+ attribute \src "libresoc.v:45826.3-45834.6"
+ process $proc$libresoc.v:45826$2477
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479
- attribute \src "libresoc.v:45891.5-45891.29"
+ assign $0\dp_INT_rabc_cr0_1$next[0:0]$2478 $1\dp_INT_rabc_cr0_1$next[0:0]$2479
+ attribute \src "libresoc.v:45827.5-45827.29"
switch \initial
- attribute \src "libresoc.v:45891.9-45891.17"
+ attribute \src "libresoc.v:45827.9-45827.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 1'0
+ assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 1'0
case
- assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 \rp_INT_ra_cr0_1
+ assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 \rp_INT_rabc_cr0_1
end
sync always
- update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478
+ update \dp_INT_rabc_cr0_1$next $0\dp_INT_rabc_cr0_1$next[0:0]$2478
end
- attribute \src "libresoc.v:45899.3-45908.6"
- process $proc$libresoc.v:45899$2480
+ attribute \src "libresoc.v:45835.3-45844.6"
+ process $proc$libresoc.v:45835$2480
assign { } { }
assign { } { }
- assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482
- attribute \src "libresoc.v:45900.5-45900.29"
+ assign $0\fus_src2_i$42[63:0]$2481 $1\fus_src2_i$42[63:0]$2482
+ attribute \src "libresoc.v:45836.5-45836.29"
switch \initial
- attribute \src "libresoc.v:45900.9-45900.17"
+ attribute \src "libresoc.v:45836.9-45836.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_cr0_1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$42[63:0]$2482 \int_src1__data_o
+ assign $1\fus_src2_i$42[63:0]$2482 \int_src__data_o
case
- assign $1\fus_src1_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481
+ update \fus_src2_i$42 $0\fus_src2_i$42[63:0]$2481
end
- attribute \src "libresoc.v:45909.3-45917.6"
- process $proc$libresoc.v:45909$2483
+ attribute \src "libresoc.v:45845.3-45853.6"
+ process $proc$libresoc.v:45845$2483
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485
- attribute \src "libresoc.v:45910.5-45910.29"
+ assign $0\dp_INT_rabc_trap0_2$next[0:0]$2484 $1\dp_INT_rabc_trap0_2$next[0:0]$2485
+ attribute \src "libresoc.v:45846.5-45846.29"
switch \initial
- attribute \src "libresoc.v:45910.9-45910.17"
+ attribute \src "libresoc.v:45846.9-45846.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 1'0
+ assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 1'0
case
- assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 \rp_INT_ra_trap0_2
+ assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 \rp_INT_rabc_trap0_2
end
sync always
- update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484
+ update \dp_INT_rabc_trap0_2$next $0\dp_INT_rabc_trap0_2$next[0:0]$2484
end
- attribute \src "libresoc.v:45918.3-45927.6"
- process $proc$libresoc.v:45918$2486
+ attribute \src "libresoc.v:45854.3-45863.6"
+ process $proc$libresoc.v:45854$2486
assign { } { }
assign { } { }
- assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488
- attribute \src "libresoc.v:45919.5-45919.29"
+ assign $0\fus_src2_i$45[63:0]$2487 $1\fus_src2_i$45[63:0]$2488
+ attribute \src "libresoc.v:45855.5-45855.29"
switch \initial
- attribute \src "libresoc.v:45919.9-45919.17"
+ attribute \src "libresoc.v:45855.9-45855.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_trap0_2
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$45[63:0]$2488 \int_src1__data_o
+ assign $1\fus_src2_i$45[63:0]$2488 \int_src__data_o
case
- assign $1\fus_src1_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487
+ update \fus_src2_i$45 $0\fus_src2_i$45[63:0]$2487
end
- attribute \src "libresoc.v:45928.3-45936.6"
- process $proc$libresoc.v:45928$2489
+ attribute \src "libresoc.v:45864.3-45872.6"
+ process $proc$libresoc.v:45864$2489
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491
- attribute \src "libresoc.v:45929.5-45929.29"
+ assign $0\dp_INT_rabc_logical0_3$next[0:0]$2490 $1\dp_INT_rabc_logical0_3$next[0:0]$2491
+ attribute \src "libresoc.v:45865.5-45865.29"
switch \initial
- attribute \src "libresoc.v:45929.9-45929.17"
+ attribute \src "libresoc.v:45865.9-45865.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 1'0
+ assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 1'0
case
- assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 \rp_INT_ra_logical0_3
+ assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 \rp_INT_rabc_logical0_3
end
sync always
- update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490
+ update \dp_INT_rabc_logical0_3$next $0\dp_INT_rabc_logical0_3$next[0:0]$2490
end
- attribute \src "libresoc.v:45937.3-45946.6"
- process $proc$libresoc.v:45937$2492
+ attribute \src "libresoc.v:45873.3-45882.6"
+ process $proc$libresoc.v:45873$2492
assign { } { }
assign { } { }
- assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494
- attribute \src "libresoc.v:45938.5-45938.29"
+ assign $0\fus_src2_i$48[63:0]$2493 $1\fus_src2_i$48[63:0]$2494
+ attribute \src "libresoc.v:45874.5-45874.29"
switch \initial
- attribute \src "libresoc.v:45938.9-45938.17"
+ attribute \src "libresoc.v:45874.9-45874.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_logical0_3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$48[63:0]$2494 \int_src1__data_o
+ assign $1\fus_src2_i$48[63:0]$2494 \int_src__data_o
case
- assign $1\fus_src1_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493
+ update \fus_src2_i$48 $0\fus_src2_i$48[63:0]$2493
end
- attribute \src "libresoc.v:45947.3-45955.6"
- process $proc$libresoc.v:45947$2495
+ attribute \src "libresoc.v:45883.3-45891.6"
+ process $proc$libresoc.v:45883$2495
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497
- attribute \src "libresoc.v:45948.5-45948.29"
+ assign $0\dp_INT_rabc_div0_4$next[0:0]$2496 $1\dp_INT_rabc_div0_4$next[0:0]$2497
+ attribute \src "libresoc.v:45884.5-45884.29"
switch \initial
- attribute \src "libresoc.v:45948.9-45948.17"
+ attribute \src "libresoc.v:45884.9-45884.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 1'0
+ assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 1'0
case
- assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 \rp_INT_ra_spr0_4
+ assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 \rp_INT_rabc_div0_4
end
sync always
- update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496
+ update \dp_INT_rabc_div0_4$next $0\dp_INT_rabc_div0_4$next[0:0]$2496
end
- attribute \src "libresoc.v:45956.3-45965.6"
- process $proc$libresoc.v:45956$2498
+ attribute \src "libresoc.v:45892.3-45901.6"
+ process $proc$libresoc.v:45892$2498
assign { } { }
assign { } { }
- assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500
- attribute \src "libresoc.v:45957.5-45957.29"
+ assign $0\fus_src2_i$51[63:0]$2499 $1\fus_src2_i$51[63:0]$2500
+ attribute \src "libresoc.v:45893.5-45893.29"
switch \initial
- attribute \src "libresoc.v:45957.9-45957.17"
+ attribute \src "libresoc.v:45893.9-45893.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_spr0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_div0_4
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$51[63:0]$2500 \int_src1__data_o
+ assign $1\fus_src2_i$51[63:0]$2500 \int_src__data_o
case
- assign $1\fus_src1_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499
+ update \fus_src2_i$51 $0\fus_src2_i$51[63:0]$2499
end
- attribute \src "libresoc.v:45966.3-45974.6"
- process $proc$libresoc.v:45966$2501
+ attribute \src "libresoc.v:45902.3-45910.6"
+ process $proc$libresoc.v:45902$2501
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503
- attribute \src "libresoc.v:45967.5-45967.29"
+ assign $0\dp_INT_rabc_mul0_5$next[0:0]$2502 $1\dp_INT_rabc_mul0_5$next[0:0]$2503
+ attribute \src "libresoc.v:45903.5-45903.29"
switch \initial
- attribute \src "libresoc.v:45967.9-45967.17"
+ attribute \src "libresoc.v:45903.9-45903.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_div0_5$next[0:0]$2503 1'0
+ assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 1'0
case
- assign $1\dp_INT_ra_div0_5$next[0:0]$2503 \rp_INT_ra_div0_5
+ assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 \rp_INT_rabc_mul0_5
end
sync always
- update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502
+ update \dp_INT_rabc_mul0_5$next $0\dp_INT_rabc_mul0_5$next[0:0]$2502
end
- attribute \src "libresoc.v:45975.3-45984.6"
- process $proc$libresoc.v:45975$2504
+ attribute \src "libresoc.v:45911.3-45920.6"
+ process $proc$libresoc.v:45911$2504
assign { } { }
assign { } { }
- assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506
- attribute \src "libresoc.v:45976.5-45976.29"
+ assign $0\fus_src2_i$54[63:0]$2505 $1\fus_src2_i$54[63:0]$2506
+ attribute \src "libresoc.v:45912.5-45912.29"
switch \initial
- attribute \src "libresoc.v:45976.9-45976.17"
+ attribute \src "libresoc.v:45912.9-45912.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_div0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_mul0_5
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$54[63:0]$2506 \int_src1__data_o
+ assign $1\fus_src2_i$54[63:0]$2506 \int_src__data_o
case
- assign $1\fus_src1_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505
+ update \fus_src2_i$54 $0\fus_src2_i$54[63:0]$2505
end
- attribute \src "libresoc.v:45985.3-45993.6"
- process $proc$libresoc.v:45985$2507
+ attribute \src "libresoc.v:45921.3-45929.6"
+ process $proc$libresoc.v:45921$2507
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509
- attribute \src "libresoc.v:45986.5-45986.29"
+ assign $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509
+ attribute \src "libresoc.v:45922.5-45922.29"
switch \initial
- attribute \src "libresoc.v:45986.9-45986.17"
+ attribute \src "libresoc.v:45922.9-45922.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 1'0
+ assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 1'0
case
- assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 \rp_INT_ra_mul0_6
+ assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 \rp_INT_rabc_shiftrot0_6
end
sync always
- update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508
+ update \dp_INT_rabc_shiftrot0_6$next $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508
end
- attribute \src "libresoc.v:45994.3-46003.6"
- process $proc$libresoc.v:45994$2510
+ attribute \src "libresoc.v:45930.3-45939.6"
+ process $proc$libresoc.v:45930$2510
assign { } { }
assign { } { }
- assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512
- attribute \src "libresoc.v:45995.5-45995.29"
+ assign $0\fus_src2_i$57[63:0]$2511 $1\fus_src2_i$57[63:0]$2512
+ attribute \src "libresoc.v:45931.5-45931.29"
switch \initial
- attribute \src "libresoc.v:45995.9-45995.17"
+ attribute \src "libresoc.v:45931.9-45931.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_mul0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_shiftrot0_6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$57[63:0]$2512 \int_src1__data_o
+ assign $1\fus_src2_i$57[63:0]$2512 \int_src__data_o
case
- assign $1\fus_src1_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511
+ update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2511
end
- attribute \src "libresoc.v:46004.3-46012.6"
- process $proc$libresoc.v:46004$2513
+ attribute \src "libresoc.v:45940.3-45948.6"
+ process $proc$libresoc.v:45940$2513
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515
- attribute \src "libresoc.v:46005.5-46005.29"
+ assign $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 $1\dp_INT_rabc_ldst0_7$next[0:0]$2515
+ attribute \src "libresoc.v:45941.5-45941.29"
switch \initial
- attribute \src "libresoc.v:46005.9-46005.17"
+ attribute \src "libresoc.v:45941.9-45941.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 1'0
+ assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 1'0
case
- assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 \rp_INT_ra_shiftrot0_7
+ assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 \rp_INT_rabc_ldst0_7
end
sync always
- update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514
+ update \dp_INT_rabc_ldst0_7$next $0\dp_INT_rabc_ldst0_7$next[0:0]$2514
end
- attribute \src "libresoc.v:46013.3-46022.6"
- process $proc$libresoc.v:46013$2516
+ attribute \src "libresoc.v:45949.3-45958.6"
+ process $proc$libresoc.v:45949$2516
assign { } { }
assign { } { }
- assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518
- attribute \src "libresoc.v:46014.5-46014.29"
+ assign $0\fus_src2_i$60[63:0]$2517 $1\fus_src2_i$60[63:0]$2518
+ attribute \src "libresoc.v:45950.5-45950.29"
switch \initial
- attribute \src "libresoc.v:46014.9-46014.17"
+ attribute \src "libresoc.v:45950.9-45950.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_shiftrot0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_ldst0_7
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$60[63:0]$2518 \int_src1__data_o
+ assign $1\fus_src2_i$60[63:0]$2518 \int_src__data_o
case
- assign $1\fus_src1_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517
+ update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2517
end
- attribute \src "libresoc.v:46023.3-46031.6"
- process $proc$libresoc.v:46023$2519
+ attribute \src "libresoc.v:45959.3-45967.6"
+ process $proc$libresoc.v:45959$2519
assign { } { }
assign { } { }
- assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521
- attribute \src "libresoc.v:46024.5-46024.29"
+ assign $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521
+ attribute \src "libresoc.v:45960.5-45960.29"
switch \initial
- attribute \src "libresoc.v:46024.9-46024.17"
+ attribute \src "libresoc.v:45960.9-45960.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 1'0
+ assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 1'0
case
- assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 \rp_INT_ra_ldst0_8
+ assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 \rp_INT_rabc_shiftrot0_8
end
sync always
- update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520
+ update \dp_INT_rabc_shiftrot0_8$next $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520
end
- attribute \src "libresoc.v:46032.3-46041.6"
- process $proc$libresoc.v:46032$2522
+ attribute \src "libresoc.v:45968.3-45977.6"
+ process $proc$libresoc.v:45968$2522
assign { } { }
assign { } { }
- assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524
- attribute \src "libresoc.v:46033.5-46033.29"
+ assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0]
+ attribute \src "libresoc.v:45969.5-45969.29"
switch \initial
- attribute \src "libresoc.v:46033.9-46033.17"
+ attribute \src "libresoc.v:45969.9-45969.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_ra_ldst0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_shiftrot0_8
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$63[63:0]$2524 \int_src1__data_o
+ assign $1\fus_src3_i[63:0] \int_src__data_o
case
- assign $1\fus_src1_i$63[63:0]$2524 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523
+ update \fus_src3_i $0\fus_src3_i[63:0]
end
- attribute \src "libresoc.v:46042.3-46050.6"
- process $proc$libresoc.v:46042$2525
+ attribute \src "libresoc.v:45978.3-45986.6"
+ process $proc$libresoc.v:45978$2523
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527
- attribute \src "libresoc.v:46043.5-46043.29"
+ assign $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 $1\dp_INT_rabc_ldst0_9$next[0:0]$2525
+ attribute \src "libresoc.v:45979.5-45979.29"
switch \initial
- attribute \src "libresoc.v:46043.9-46043.17"
+ attribute \src "libresoc.v:45979.9-45979.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 1'0
+ assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 1'0
case
- assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 \rp_INT_rb_alu0_0
+ assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 \rp_INT_rabc_ldst0_9
end
sync always
- update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526
+ update \dp_INT_rabc_ldst0_9$next $0\dp_INT_rabc_ldst0_9$next[0:0]$2524
end
- attribute \src "libresoc.v:46051.3-46060.6"
- process $proc$libresoc.v:46051$2528
+ attribute \src "libresoc.v:45987.3-45996.6"
+ process $proc$libresoc.v:45987$2526
assign { } { }
assign { } { }
- assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0]
- attribute \src "libresoc.v:46052.5-46052.29"
+ assign $0\fus_src3_i$61[63:0]$2527 $1\fus_src3_i$61[63:0]$2528
+ attribute \src "libresoc.v:45988.5-45988.29"
switch \initial
- attribute \src "libresoc.v:46052.9-46052.17"
+ attribute \src "libresoc.v:45988.9-45988.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_ldst0_9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i[63:0] \int_src2__data_o
+ assign $1\fus_src3_i$61[63:0]$2528 \int_src__data_o
case
- assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src3_i$61[63:0]$2528 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i $0\fus_src2_i[63:0]
+ update \fus_src3_i$61 $0\fus_src3_i$61[63:0]$2527
end
- attribute \src "libresoc.v:46061.3-46069.6"
- process $proc$libresoc.v:46061$2529
+ attribute \src "libresoc.v:45997.3-46005.6"
+ process $proc$libresoc.v:45997$2529
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531
- attribute \src "libresoc.v:46062.5-46062.29"
+ assign $0\dp_INT_rabc_alu0_10$next[0:0]$2530 $1\dp_INT_rabc_alu0_10$next[0:0]$2531
+ attribute \src "libresoc.v:45998.5-45998.29"
switch \initial
- attribute \src "libresoc.v:46062.9-46062.17"
+ attribute \src "libresoc.v:45998.9-45998.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 1'0
+ assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 1'0
case
- assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 \rp_INT_rb_cr0_1
+ assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 \rp_INT_rabc_alu0_10
end
sync always
- update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530
+ update \dp_INT_rabc_alu0_10$next $0\dp_INT_rabc_alu0_10$next[0:0]$2530
end
- attribute \src "libresoc.v:46070.3-46079.6"
- process $proc$libresoc.v:46070$2532
+ attribute \src "libresoc.v:46006.3-46015.6"
+ process $proc$libresoc.v:46006$2532
assign { } { }
assign { } { }
- assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534
- attribute \src "libresoc.v:46071.5-46071.29"
+ assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0]
+ attribute \src "libresoc.v:46007.5-46007.29"
switch \initial
- attribute \src "libresoc.v:46071.9-46071.17"
+ attribute \src "libresoc.v:46007.9-46007.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_alu0_10
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$64[63:0]$2534 \int_src2__data_o
+ assign $1\fus_src1_i[63:0] \int_src__data_o
case
- assign $1\fus_src2_i$64[63:0]$2534 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533
+ update \fus_src1_i $0\fus_src1_i[63:0]
end
- attribute \src "libresoc.v:46080.3-46088.6"
- process $proc$libresoc.v:46080$2535
+ attribute \src "libresoc.v:46016.3-46024.6"
+ process $proc$libresoc.v:46016$2533
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537
- attribute \src "libresoc.v:46081.5-46081.29"
+ assign $0\dp_INT_rabc_cr0_11$next[0:0]$2534 $1\dp_INT_rabc_cr0_11$next[0:0]$2535
+ attribute \src "libresoc.v:46017.5-46017.29"
switch \initial
- attribute \src "libresoc.v:46081.9-46081.17"
+ attribute \src "libresoc.v:46017.9-46017.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 1'0
+ assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 1'0
case
- assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 \rp_INT_rb_trap0_2
+ assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 \rp_INT_rabc_cr0_11
end
sync always
- update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536
+ update \dp_INT_rabc_cr0_11$next $0\dp_INT_rabc_cr0_11$next[0:0]$2534
end
- attribute \src "libresoc.v:46089.3-46098.6"
- process $proc$libresoc.v:46089$2538
+ attribute \src "libresoc.v:46025.3-46034.6"
+ process $proc$libresoc.v:46025$2536
assign { } { }
assign { } { }
- assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540
- attribute \src "libresoc.v:46090.5-46090.29"
+ assign $0\fus_src1_i$62[63:0]$2537 $1\fus_src1_i$62[63:0]$2538
+ attribute \src "libresoc.v:46026.5-46026.29"
switch \initial
- attribute \src "libresoc.v:46090.9-46090.17"
+ attribute \src "libresoc.v:46026.9-46026.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_cr0_11
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$65[63:0]$2540 \int_src2__data_o
+ assign $1\fus_src1_i$62[63:0]$2538 \int_src__data_o
case
- assign $1\fus_src2_i$65[63:0]$2540 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$62[63:0]$2538 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539
+ update \fus_src1_i$62 $0\fus_src1_i$62[63:0]$2537
end
- attribute \src "libresoc.v:46099.3-46107.6"
- process $proc$libresoc.v:46099$2541
+ attribute \src "libresoc.v:46035.3-46043.6"
+ process $proc$libresoc.v:46035$2539
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543
- attribute \src "libresoc.v:46100.5-46100.29"
+ assign $0\dp_INT_rabc_trap0_12$next[0:0]$2540 $1\dp_INT_rabc_trap0_12$next[0:0]$2541
+ attribute \src "libresoc.v:46036.5-46036.29"
switch \initial
- attribute \src "libresoc.v:46100.9-46100.17"
+ attribute \src "libresoc.v:46036.9-46036.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 1'0
+ assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 1'0
case
- assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 \rp_INT_rb_logical0_3
+ assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 \rp_INT_rabc_trap0_12
end
sync always
- update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542
+ update \dp_INT_rabc_trap0_12$next $0\dp_INT_rabc_trap0_12$next[0:0]$2540
end
- attribute \src "libresoc.v:46108.3-46117.6"
- process $proc$libresoc.v:46108$2544
+ attribute \src "libresoc.v:46044.3-46053.6"
+ process $proc$libresoc.v:46044$2542
assign { } { }
assign { } { }
- assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546
- attribute \src "libresoc.v:46109.5-46109.29"
+ assign $0\fus_src1_i$63[63:0]$2543 $1\fus_src1_i$63[63:0]$2544
+ attribute \src "libresoc.v:46045.5-46045.29"
switch \initial
- attribute \src "libresoc.v:46109.9-46109.17"
+ attribute \src "libresoc.v:46045.9-46045.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_trap0_12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$66[63:0]$2546 \int_src2__data_o
+ assign $1\fus_src1_i$63[63:0]$2544 \int_src__data_o
case
- assign $1\fus_src2_i$66[63:0]$2546 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$63[63:0]$2544 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545
+ update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2543
end
- attribute \src "libresoc.v:46118.3-46126.6"
- process $proc$libresoc.v:46118$2547
+ attribute \src "libresoc.v:46054.3-46062.6"
+ process $proc$libresoc.v:46054$2545
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549
- attribute \src "libresoc.v:46119.5-46119.29"
+ assign $0\dp_INT_rabc_logical0_13$next[0:0]$2546 $1\dp_INT_rabc_logical0_13$next[0:0]$2547
+ attribute \src "libresoc.v:46055.5-46055.29"
switch \initial
- attribute \src "libresoc.v:46119.9-46119.17"
+ attribute \src "libresoc.v:46055.9-46055.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_div0_4$next[0:0]$2549 1'0
+ assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 1'0
case
- assign $1\dp_INT_rb_div0_4$next[0:0]$2549 \rp_INT_rb_div0_4
+ assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 \rp_INT_rabc_logical0_13
end
sync always
- update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548
+ update \dp_INT_rabc_logical0_13$next $0\dp_INT_rabc_logical0_13$next[0:0]$2546
end
- attribute \src "libresoc.v:46127.3-46136.6"
- process $proc$libresoc.v:46127$2550
+ attribute \src "libresoc.v:46063.3-46072.6"
+ process $proc$libresoc.v:46063$2548
assign { } { }
assign { } { }
- assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552
- attribute \src "libresoc.v:46128.5-46128.29"
+ assign $0\fus_src1_i$64[63:0]$2549 $1\fus_src1_i$64[63:0]$2550
+ attribute \src "libresoc.v:46064.5-46064.29"
switch \initial
- attribute \src "libresoc.v:46128.9-46128.17"
+ attribute \src "libresoc.v:46064.9-46064.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_logical0_13
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$67[63:0]$2552 \int_src2__data_o
+ assign $1\fus_src1_i$64[63:0]$2550 \int_src__data_o
case
- assign $1\fus_src2_i$67[63:0]$2552 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$64[63:0]$2550 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551
+ update \fus_src1_i$64 $0\fus_src1_i$64[63:0]$2549
end
- attribute \src "libresoc.v:46137.3-46145.6"
- process $proc$libresoc.v:46137$2553
+ attribute \src "libresoc.v:46073.3-46081.6"
+ process $proc$libresoc.v:46073$2551
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555
- attribute \src "libresoc.v:46138.5-46138.29"
+ assign $0\dp_INT_rabc_spr0_14$next[0:0]$2552 $1\dp_INT_rabc_spr0_14$next[0:0]$2553
+ attribute \src "libresoc.v:46074.5-46074.29"
switch \initial
- attribute \src "libresoc.v:46138.9-46138.17"
+ attribute \src "libresoc.v:46074.9-46074.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 1'0
+ assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 1'0
case
- assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 \rp_INT_rb_mul0_5
+ assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 \rp_INT_rabc_spr0_14
end
sync always
- update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554
+ update \dp_INT_rabc_spr0_14$next $0\dp_INT_rabc_spr0_14$next[0:0]$2552
end
- attribute \src "libresoc.v:46146.3-46155.6"
- process $proc$libresoc.v:46146$2556
+ attribute \src "libresoc.v:46082.3-46091.6"
+ process $proc$libresoc.v:46082$2554
assign { } { }
assign { } { }
- assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558
- attribute \src "libresoc.v:46147.5-46147.29"
+ assign $0\fus_src1_i$67[63:0]$2555 $1\fus_src1_i$67[63:0]$2556
+ attribute \src "libresoc.v:46083.5-46083.29"
switch \initial
- attribute \src "libresoc.v:46147.9-46147.17"
+ attribute \src "libresoc.v:46083.9-46083.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_spr0_14
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$68[63:0]$2558 \int_src2__data_o
+ assign $1\fus_src1_i$67[63:0]$2556 \int_src__data_o
case
- assign $1\fus_src2_i$68[63:0]$2558 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$67[63:0]$2556 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557
+ update \fus_src1_i$67 $0\fus_src1_i$67[63:0]$2555
end
- attribute \src "libresoc.v:46156.3-46164.6"
- process $proc$libresoc.v:46156$2559
+ attribute \src "libresoc.v:46092.3-46100.6"
+ process $proc$libresoc.v:46092$2557
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561
- attribute \src "libresoc.v:46157.5-46157.29"
+ assign $0\dp_INT_rabc_div0_15$next[0:0]$2558 $1\dp_INT_rabc_div0_15$next[0:0]$2559
+ attribute \src "libresoc.v:46093.5-46093.29"
switch \initial
- attribute \src "libresoc.v:46157.9-46157.17"
+ attribute \src "libresoc.v:46093.9-46093.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 1'0
+ assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 1'0
case
- assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 \rp_INT_rb_shiftrot0_6
+ assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 \rp_INT_rabc_div0_15
end
sync always
- update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560
+ update \dp_INT_rabc_div0_15$next $0\dp_INT_rabc_div0_15$next[0:0]$2558
end
- attribute \src "libresoc.v:46165.3-46174.6"
- process $proc$libresoc.v:46165$2562
+ attribute \src "libresoc.v:46101.3-46110.6"
+ process $proc$libresoc.v:46101$2560
assign { } { }
assign { } { }
- assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564
- attribute \src "libresoc.v:46166.5-46166.29"
+ assign $0\fus_src1_i$68[63:0]$2561 $1\fus_src1_i$68[63:0]$2562
+ attribute \src "libresoc.v:46102.5-46102.29"
switch \initial
- attribute \src "libresoc.v:46166.9-46166.17"
+ attribute \src "libresoc.v:46102.9-46102.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_div0_15
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$69[63:0]$2564 \int_src2__data_o
+ assign $1\fus_src1_i$68[63:0]$2562 \int_src__data_o
case
- assign $1\fus_src2_i$69[63:0]$2564 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$68[63:0]$2562 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563
+ update \fus_src1_i$68 $0\fus_src1_i$68[63:0]$2561
end
- attribute \src "libresoc.v:46175.3-46183.6"
- process $proc$libresoc.v:46175$2565
+ attribute \src "libresoc.v:46111.3-46119.6"
+ process $proc$libresoc.v:46111$2563
assign { } { }
assign { } { }
- assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567
- attribute \src "libresoc.v:46176.5-46176.29"
+ assign $0\dp_INT_rabc_mul0_16$next[0:0]$2564 $1\dp_INT_rabc_mul0_16$next[0:0]$2565
+ attribute \src "libresoc.v:46112.5-46112.29"
switch \initial
- attribute \src "libresoc.v:46176.9-46176.17"
+ attribute \src "libresoc.v:46112.9-46112.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 1'0
+ assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 1'0
case
- assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 \rp_INT_rb_ldst0_7
+ assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 \rp_INT_rabc_mul0_16
end
sync always
- update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566
+ update \dp_INT_rabc_mul0_16$next $0\dp_INT_rabc_mul0_16$next[0:0]$2564
end
- attribute \src "libresoc.v:46184.3-46193.6"
- process $proc$libresoc.v:46184$2568
+ attribute \src "libresoc.v:46120.3-46129.6"
+ process $proc$libresoc.v:46120$2566
assign { } { }
assign { } { }
- assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570
- attribute \src "libresoc.v:46185.5-46185.29"
+ assign $0\fus_src1_i$69[63:0]$2567 $1\fus_src1_i$69[63:0]$2568
+ attribute \src "libresoc.v:46121.5-46121.29"
switch \initial
- attribute \src "libresoc.v:46185.9-46185.17"
+ attribute \src "libresoc.v:46121.9-46121.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rb_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_mul0_16
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$70[63:0]$2570 \int_src2__data_o
+ assign $1\fus_src1_i$69[63:0]$2568 \int_src__data_o
case
- assign $1\fus_src2_i$70[63:0]$2570 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$69[63:0]$2568 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569
+ update \fus_src1_i$69 $0\fus_src1_i$69[63:0]$2567
end
- attribute \src "libresoc.v:46194.3-46202.6"
- process $proc$libresoc.v:46194$2571
+ attribute \src "libresoc.v:46130.3-46138.6"
+ process $proc$libresoc.v:46130$2569
assign { } { }
assign { } { }
- assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573
- attribute \src "libresoc.v:46195.5-46195.29"
+ assign $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571
+ attribute \src "libresoc.v:46131.5-46131.29"
switch \initial
- attribute \src "libresoc.v:46195.9-46195.17"
+ attribute \src "libresoc.v:46131.9-46131.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 1'0
+ assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 1'0
case
- assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 \rp_INT_rc_shiftrot0_0
+ assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 \rp_INT_rabc_shiftrot0_17
end
sync always
- update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572
+ update \dp_INT_rabc_shiftrot0_17$next $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570
end
- attribute \src "libresoc.v:46203.3-46212.6"
- process $proc$libresoc.v:46203$2574
+ attribute \src "libresoc.v:46139.3-46148.6"
+ process $proc$libresoc.v:46139$2572
assign { } { }
assign { } { }
- assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0]
- attribute \src "libresoc.v:46204.5-46204.29"
+ assign $0\fus_src1_i$70[63:0]$2573 $1\fus_src1_i$70[63:0]$2574
+ attribute \src "libresoc.v:46140.5-46140.29"
switch \initial
- attribute \src "libresoc.v:46204.9-46204.17"
+ attribute \src "libresoc.v:46140.9-46140.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rc_shiftrot0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_shiftrot0_17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src3_i[63:0] \int_src3__data_o
+ assign $1\fus_src1_i$70[63:0]$2574 \int_src__data_o
case
- assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$70[63:0]$2574 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src3_i $0\fus_src3_i[63:0]
+ update \fus_src1_i$70 $0\fus_src1_i$70[63:0]$2573
end
- attribute \src "libresoc.v:46213.3-46221.6"
- process $proc$libresoc.v:46213$2575
+ attribute \src "libresoc.v:46149.3-46157.6"
+ process $proc$libresoc.v:46149$2575
assign { } { }
assign { } { }
- assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577
- attribute \src "libresoc.v:46214.5-46214.29"
+ assign $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 $1\dp_INT_rabc_ldst0_18$next[0:0]$2577
+ attribute \src "libresoc.v:46150.5-46150.29"
switch \initial
- attribute \src "libresoc.v:46214.9-46214.17"
+ attribute \src "libresoc.v:46150.9-46150.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 1'0
+ assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 1'0
case
- assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 \rp_INT_rc_ldst0_1
+ assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 \rp_INT_rabc_ldst0_18
end
sync always
- update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576
+ update \dp_INT_rabc_ldst0_18$next $0\dp_INT_rabc_ldst0_18$next[0:0]$2576
end
- attribute \src "libresoc.v:46222.3-46231.6"
- process $proc$libresoc.v:46222$2578
+ attribute \src "libresoc.v:46158.3-46167.6"
+ process $proc$libresoc.v:46158$2578
assign { } { }
assign { } { }
- assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580
- attribute \src "libresoc.v:46223.5-46223.29"
+ assign $0\fus_src1_i$71[63:0]$2579 $1\fus_src1_i$71[63:0]$2580
+ attribute \src "libresoc.v:46159.5-46159.29"
switch \initial
- attribute \src "libresoc.v:46223.9-46223.17"
+ attribute \src "libresoc.v:46159.9-46159.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_INT_rc_ldst0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_INT_rabc_ldst0_18
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src3_i$71[63:0]$2580 \int_src3__data_o
+ assign $1\fus_src1_i$71[63:0]$2580 \int_src__data_o
case
- assign $1\fus_src3_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src1_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579
+ update \fus_src1_i$71 $0\fus_src1_i$71[63:0]$2579
end
- attribute \src "libresoc.v:46232.3-46240.6"
- process $proc$libresoc.v:46232$2581
+ attribute \src "libresoc.v:46168.3-46176.6"
+ process $proc$libresoc.v:46168$2581
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583
- attribute \src "libresoc.v:46233.5-46233.29"
+ attribute \src "libresoc.v:46169.5-46169.29"
switch \initial
- attribute \src "libresoc.v:46233.9-46233.17"
+ attribute \src "libresoc.v:46169.9-46169.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582
end
- attribute \src "libresoc.v:46241.3-46250.6"
- process $proc$libresoc.v:46241$2584
+ attribute \src "libresoc.v:46177.3-46186.6"
+ process $proc$libresoc.v:46177$2584
assign { } { }
assign { } { }
assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586
- attribute \src "libresoc.v:46242.5-46242.29"
+ attribute \src "libresoc.v:46178.5-46178.29"
switch \initial
- attribute \src "libresoc.v:46242.9-46242.17"
+ attribute \src "libresoc.v:46178.9-46178.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_alu0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585
end
- attribute \src "libresoc.v:46251.3-46259.6"
- process $proc$libresoc.v:46251$2587
+ attribute \src "libresoc.v:46187.3-46195.6"
+ process $proc$libresoc.v:46187$2587
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589
- attribute \src "libresoc.v:46252.5-46252.29"
+ attribute \src "libresoc.v:46188.5-46188.29"
switch \initial
- attribute \src "libresoc.v:46252.9-46252.17"
+ attribute \src "libresoc.v:46188.9-46188.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588
end
- attribute \src "libresoc.v:46260.3-46269.6"
- process $proc$libresoc.v:46260$2590
+ attribute \src "libresoc.v:46196.3-46205.6"
+ process $proc$libresoc.v:46196$2590
assign { } { }
assign { } { }
assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592
- attribute \src "libresoc.v:46261.5-46261.29"
+ attribute \src "libresoc.v:46197.5-46197.29"
switch \initial
- attribute \src "libresoc.v:46261.9-46261.17"
+ attribute \src "libresoc.v:46197.9-46197.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_logical0_1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591
end
- attribute \src "libresoc.v:46270.3-46278.6"
- process $proc$libresoc.v:46270$2593
+ attribute \src "libresoc.v:46206.3-46214.6"
+ process $proc$libresoc.v:46206$2593
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595
- attribute \src "libresoc.v:46271.5-46271.29"
+ attribute \src "libresoc.v:46207.5-46207.29"
switch \initial
- attribute \src "libresoc.v:46271.9-46271.17"
+ attribute \src "libresoc.v:46207.9-46207.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594
end
- attribute \src "libresoc.v:46279.3-46288.6"
- process $proc$libresoc.v:46279$2596
+ attribute \src "libresoc.v:46215.3-46224.6"
+ process $proc$libresoc.v:46215$2596
assign { } { }
assign { } { }
assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0]
- attribute \src "libresoc.v:46280.5-46280.29"
+ attribute \src "libresoc.v:46216.5-46216.29"
switch \initial
- attribute \src "libresoc.v:46280.9-46280.17"
+ attribute \src "libresoc.v:46216.9-46216.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_spr0_2
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src4_i $0\fus_src4_i[0:0]
end
- attribute \src "libresoc.v:46289.3-46297.6"
- process $proc$libresoc.v:46289$2597
+ attribute \src "libresoc.v:46225.3-46233.6"
+ process $proc$libresoc.v:46225$2597
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599
- attribute \src "libresoc.v:46290.5-46290.29"
+ attribute \src "libresoc.v:46226.5-46226.29"
switch \initial
- attribute \src "libresoc.v:46290.9-46290.17"
+ attribute \src "libresoc.v:46226.9-46226.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598
end
- attribute \src "libresoc.v:46298.3-46307.6"
- process $proc$libresoc.v:46298$2600
+ attribute \src "libresoc.v:46234.3-46243.6"
+ process $proc$libresoc.v:46234$2600
assign { } { }
assign { } { }
assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602
- attribute \src "libresoc.v:46299.5-46299.29"
+ attribute \src "libresoc.v:46235.5-46235.29"
switch \initial
- attribute \src "libresoc.v:46299.9-46299.17"
+ attribute \src "libresoc.v:46235.9-46235.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_div0_3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601
end
- attribute \src "libresoc.v:46308.3-46316.6"
- process $proc$libresoc.v:46308$2603
+ attribute \src "libresoc.v:46244.3-46252.6"
+ process $proc$libresoc.v:46244$2603
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605
- attribute \src "libresoc.v:46309.5-46309.29"
+ attribute \src "libresoc.v:46245.5-46245.29"
switch \initial
- attribute \src "libresoc.v:46309.9-46309.17"
+ attribute \src "libresoc.v:46245.9-46245.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604
end
- attribute \src "libresoc.v:46317.3-46326.6"
- process $proc$libresoc.v:46317$2606
+ attribute \src "libresoc.v:46253.3-46262.6"
+ process $proc$libresoc.v:46253$2606
assign { } { }
assign { } { }
assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608
- attribute \src "libresoc.v:46318.5-46318.29"
+ attribute \src "libresoc.v:46254.5-46254.29"
switch \initial
- attribute \src "libresoc.v:46318.9-46318.17"
+ attribute \src "libresoc.v:46254.9-46254.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_mul0_4
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607
end
- attribute \src "libresoc.v:46327.3-46335.6"
- process $proc$libresoc.v:46327$2609
+ attribute \src "libresoc.v:46263.3-46271.6"
+ process $proc$libresoc.v:46263$2609
assign { } { }
assign { } { }
assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611
- attribute \src "libresoc.v:46328.5-46328.29"
+ attribute \src "libresoc.v:46264.5-46264.29"
switch \initial
- attribute \src "libresoc.v:46328.9-46328.17"
+ attribute \src "libresoc.v:46264.9-46264.17"
case 1'1
case
end
sync always
update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610
end
- attribute \src "libresoc.v:46336.3-46345.6"
- process $proc$libresoc.v:46336$2612
+ attribute \src "libresoc.v:46272.3-46281.6"
+ process $proc$libresoc.v:46272$2612
assign { } { }
assign { } { }
assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614
- attribute \src "libresoc.v:46337.5-46337.29"
+ attribute \src "libresoc.v:46273.5-46273.29"
switch \initial
- attribute \src "libresoc.v:46337.9-46337.17"
+ attribute \src "libresoc.v:46273.9-46273.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_so_shiftrot0_5
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613
end
- attribute \src "libresoc.v:46346.3-46354.6"
- process $proc$libresoc.v:46346$2615
+ attribute \src "libresoc.v:46282.3-46290.6"
+ process $proc$libresoc.v:46282$2615
assign { } { }
assign { } { }
assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617
- attribute \src "libresoc.v:46347.5-46347.29"
+ attribute \src "libresoc.v:46283.5-46283.29"
switch \initial
- attribute \src "libresoc.v:46347.9-46347.17"
+ attribute \src "libresoc.v:46283.9-46283.17"
case 1'1
case
end
sync always
update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616
end
- attribute \src "libresoc.v:46355.3-46364.6"
- process $proc$libresoc.v:46355$2618
+ attribute \src "libresoc.v:46291.3-46300.6"
+ process $proc$libresoc.v:46291$2618
assign { } { }
assign { } { }
assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620
- attribute \src "libresoc.v:46356.5-46356.29"
+ attribute \src "libresoc.v:46292.5-46292.29"
switch \initial
- attribute \src "libresoc.v:46356.9-46356.17"
+ attribute \src "libresoc.v:46292.9-46292.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_ca_alu0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619
end
- attribute \src "libresoc.v:46365.3-46373.6"
- process $proc$libresoc.v:46365$2621
+ attribute \src "libresoc.v:46301.3-46309.6"
+ process $proc$libresoc.v:46301$2621
assign { } { }
assign { } { }
assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623
- attribute \src "libresoc.v:46366.5-46366.29"
+ attribute \src "libresoc.v:46302.5-46302.29"
switch \initial
- attribute \src "libresoc.v:46366.9-46366.17"
+ attribute \src "libresoc.v:46302.9-46302.17"
case 1'1
case
end
sync always
update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622
end
- attribute \src "libresoc.v:46374.3-46383.6"
- process $proc$libresoc.v:46374$2624
+ attribute \src "libresoc.v:46310.3-46319.6"
+ process $proc$libresoc.v:46310$2624
assign { } { }
assign { } { }
assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0]
- attribute \src "libresoc.v:46375.5-46375.29"
+ attribute \src "libresoc.v:46311.5-46311.29"
switch \initial
- attribute \src "libresoc.v:46375.9-46375.17"
+ attribute \src "libresoc.v:46311.9-46311.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_ca_spr0_1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src6_i $0\fus_src6_i[1:0]
end
- attribute \src "libresoc.v:46384.3-46392.6"
- process $proc$libresoc.v:46384$2625
+ attribute \src "libresoc.v:46320.3-46328.6"
+ process $proc$libresoc.v:46320$2625
assign { } { }
assign { } { }
assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627
- attribute \src "libresoc.v:46385.5-46385.29"
+ attribute \src "libresoc.v:46321.5-46321.29"
switch \initial
- attribute \src "libresoc.v:46385.9-46385.17"
+ attribute \src "libresoc.v:46321.9-46321.17"
case 1'1
case
end
sync always
update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626
end
- attribute \src "libresoc.v:46393.3-46402.6"
- process $proc$libresoc.v:46393$2628
+ attribute \src "libresoc.v:46329.3-46338.6"
+ process $proc$libresoc.v:46329$2628
assign { } { }
assign { } { }
assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0]
- attribute \src "libresoc.v:46394.5-46394.29"
+ attribute \src "libresoc.v:46330.5-46330.29"
switch \initial
- attribute \src "libresoc.v:46394.9-46394.17"
+ attribute \src "libresoc.v:46330.9-46330.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_ca_shiftrot0_2
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src5_i $0\fus_src5_i[1:0]
end
- attribute \src "libresoc.v:46403.3-46411.6"
- process $proc$libresoc.v:46403$2629
+ attribute \src "libresoc.v:46339.3-46347.6"
+ process $proc$libresoc.v:46339$2629
assign { } { }
assign { } { }
assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631
- attribute \src "libresoc.v:46404.5-46404.29"
+ attribute \src "libresoc.v:46340.5-46340.29"
switch \initial
- attribute \src "libresoc.v:46404.9-46404.17"
+ attribute \src "libresoc.v:46340.9-46340.17"
case 1'1
case
end
sync always
update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630
end
- attribute \src "libresoc.v:46412.3-46421.6"
- process $proc$libresoc.v:46412$2632
+ attribute \src "libresoc.v:46348.3-46357.6"
+ process $proc$libresoc.v:46348$2632
assign { } { }
assign { } { }
assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634
- attribute \src "libresoc.v:46413.5-46413.29"
+ attribute \src "libresoc.v:46349.5-46349.29"
switch \initial
- attribute \src "libresoc.v:46413.9-46413.17"
+ attribute \src "libresoc.v:46349.9-46349.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_XER_xer_ov_spr0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633
end
- attribute \src "libresoc.v:46422.3-46430.6"
- process $proc$libresoc.v:46422$2635
+ attribute \src "libresoc.v:46358.3-46366.6"
+ process $proc$libresoc.v:46358$2635
assign { } { }
assign { } { }
assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637
- attribute \src "libresoc.v:46423.5-46423.29"
+ attribute \src "libresoc.v:46359.5-46359.29"
switch \initial
- attribute \src "libresoc.v:46423.9-46423.17"
+ attribute \src "libresoc.v:46359.9-46359.17"
case 1'1
case
end
sync always
update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636
end
- attribute \src "libresoc.v:46431.3-46440.6"
- process $proc$libresoc.v:46431$2638
+ attribute \src "libresoc.v:46367.3-46376.6"
+ process $proc$libresoc.v:46367$2638
assign { } { }
assign { } { }
assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640
- attribute \src "libresoc.v:46432.5-46432.29"
+ attribute \src "libresoc.v:46368.5-46368.29"
switch \initial
- attribute \src "libresoc.v:46432.9-46432.17"
+ attribute \src "libresoc.v:46368.9-46368.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_CR_full_cr_cr0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639
end
- attribute \src "libresoc.v:46441.3-46449.6"
- process $proc$libresoc.v:46441$2641
+ attribute \src "libresoc.v:46377.3-46385.6"
+ process $proc$libresoc.v:46377$2641
assign { } { }
assign { } { }
assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643
- attribute \src "libresoc.v:46442.5-46442.29"
+ attribute \src "libresoc.v:46378.5-46378.29"
switch \initial
- attribute \src "libresoc.v:46442.9-46442.17"
+ attribute \src "libresoc.v:46378.9-46378.17"
case 1'1
case
end
sync always
update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642
end
- attribute \src "libresoc.v:46450.3-46459.6"
- process $proc$libresoc.v:46450$2644
+ attribute \src "libresoc.v:46386.3-46395.6"
+ process $proc$libresoc.v:46386$2644
assign { } { }
assign { } { }
assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646
- attribute \src "libresoc.v:46451.5-46451.29"
+ attribute \src "libresoc.v:46387.5-46387.29"
switch \initial
- attribute \src "libresoc.v:46451.9-46451.17"
+ attribute \src "libresoc.v:46387.9-46387.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_CR_cr_a_cr0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645
end
- attribute \src "libresoc.v:46460.3-46468.6"
- process $proc$libresoc.v:46460$2647
+ attribute \src "libresoc.v:46396.3-46404.6"
+ process $proc$libresoc.v:46396$2647
assign { } { }
assign { } { }
assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649
- attribute \src "libresoc.v:46461.5-46461.29"
+ attribute \src "libresoc.v:46397.5-46397.29"
switch \initial
- attribute \src "libresoc.v:46461.9-46461.17"
+ attribute \src "libresoc.v:46397.9-46397.17"
case 1'1
case
end
sync always
update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648
end
- attribute \src "libresoc.v:46469.3-46478.6"
- process $proc$libresoc.v:46469$2650
+ attribute \src "libresoc.v:46405.3-46414.6"
+ process $proc$libresoc.v:46405$2650
assign { } { }
assign { } { }
assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652
- attribute \src "libresoc.v:46470.5-46470.29"
+ attribute \src "libresoc.v:46406.5-46406.29"
switch \initial
- attribute \src "libresoc.v:46470.9-46470.17"
+ attribute \src "libresoc.v:46406.9-46406.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
switch \dp_CR_cr_a_branch0_1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651
end
- attribute \src "libresoc.v:46479.3-46509.6"
- process $proc$libresoc.v:46479$2653
+ attribute \src "libresoc.v:46415.3-46423.6"
+ process $proc$libresoc.v:46415$2653
+ assign { } { }
+ assign { } { }
+ assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 $1\dp_CR_cr_b_cr0_0$next[0:0]$2655
+ attribute \src "libresoc.v:46416.5-46416.29"
+ switch \initial
+ attribute \src "libresoc.v:46416.9-46416.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 1'0
+ case
+ assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 \rp_CR_cr_b_cr0_0
+ end
+ sync always
+ update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2654
+ end
+ attribute \src "libresoc.v:46424.3-46454.6"
+ process $proc$libresoc.v:46424$2656
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658
- attribute \src "libresoc.v:46480.5-46480.29"
+ assign $0\counter$next[1:0]$2657 $4\counter$next[1:0]$2661
+ attribute \src "libresoc.v:46425.5-46425.29"
switch \initial
- attribute \src "libresoc.v:46480.9-46480.17"
+ attribute \src "libresoc.v:46425.9-46425.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
switch \$221
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\counter$next[1:0]$2655 \$223 [1:0]
+ assign $1\counter$next[1:0]$2658 \$223 [1:0]
case
- assign $1\counter$next[1:0]$2655 \counter
+ assign $1\counter$next[1:0]$2658 \counter
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\counter$next[1:0]$2656 $3\counter$next[1:0]$2657
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ assign $2\counter$next[1:0]$2659 $3\counter$next[1:0]$2660
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
- assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655
+ assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658
attribute \src "libresoc.v:0.0-0.0"
case 7'0000001
assign { } { }
- assign $3\counter$next[1:0]$2657 2'10
+ assign $3\counter$next[1:0]$2660 2'10
case
- assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655
+ assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658
end
case
- assign $2\counter$next[1:0]$2656 $1\counter$next[1:0]$2655
+ assign $2\counter$next[1:0]$2659 $1\counter$next[1:0]$2658
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\counter$next[1:0]$2658 2'00
+ assign $4\counter$next[1:0]$2661 2'00
case
- assign $4\counter$next[1:0]$2658 $2\counter$next[1:0]$2656
+ assign $4\counter$next[1:0]$2661 $2\counter$next[1:0]$2659
end
sync always
- update \counter$next $0\counter$next[1:0]$2654
+ update \counter$next $0\counter$next[1:0]$2657
end
- attribute \src "libresoc.v:46510.3-46518.6"
- process $proc$libresoc.v:46510$2659
+ attribute \src "libresoc.v:46455.3-46464.6"
+ process $proc$libresoc.v:46455$2662
assign { } { }
assign { } { }
- assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661
- attribute \src "libresoc.v:46511.5-46511.29"
+ assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664
+ attribute \src "libresoc.v:46456.5-46456.29"
+ switch \initial
+ attribute \src "libresoc.v:46456.9-46456.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_CR_cr_b_cr0_0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o
+ case
+ assign $1\fus_src5_i$84[3:0]$2664 4'0000
+ end
+ sync always
+ update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663
+ end
+ attribute \src "libresoc.v:46465.3-46473.6"
+ process $proc$libresoc.v:46465$2665
+ assign { } { }
+ assign { } { }
+ assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667
+ attribute \src "libresoc.v:46466.5-46466.29"
switch \initial
- attribute \src "libresoc.v:46511.9-46511.17"
+ attribute \src "libresoc.v:46466.9-46466.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 1'0
+ assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 1'0
case
- assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 \rp_CR_cr_b_cr0_0
+ assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 \rp_CR_cr_c_cr0_0
end
sync always
- update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660
+ update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666
end
- attribute \src "libresoc.v:46519.3-46528.6"
- process $proc$libresoc.v:46519$2662
+ attribute \src "libresoc.v:46474.3-46483.6"
+ process $proc$libresoc.v:46474$2668
assign { } { }
assign { } { }
- assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664
- attribute \src "libresoc.v:46520.5-46520.29"
+ assign $0\fus_src6_i$85[3:0]$2669 $1\fus_src6_i$85[3:0]$2670
+ attribute \src "libresoc.v:46475.5-46475.29"
switch \initial
- attribute \src "libresoc.v:46520.9-46520.17"
+ attribute \src "libresoc.v:46475.9-46475.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_CR_cr_b_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_CR_cr_c_cr0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o
+ assign $1\fus_src6_i$85[3:0]$2670 \cr_src3__data_o
case
- assign $1\fus_src5_i$84[3:0]$2664 4'0000
+ assign $1\fus_src6_i$85[3:0]$2670 4'0000
end
sync always
- update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663
+ update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2669
end
- attribute \src "libresoc.v:46529.3-46619.6"
- process $proc$libresoc.v:46529$2665
+ attribute \src "libresoc.v:46484.3-46574.6"
+ process $proc$libresoc.v:46484$2671
assign { } { }
assign { } { }
assign { } { }
assign $0\corebusy_o[0:0] $2\corebusy_o[0:0]
- attribute \src "libresoc.v:46530.5-46530.29"
+ attribute \src "libresoc.v:46485.5-46485.29"
switch \initial
- attribute \src "libresoc.v:46530.9-46530.17"
+ attribute \src "libresoc.v:46485.9-46485.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
switch \$226
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\corebusy_o[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\corebusy_o[0:0] $3\corebusy_o[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign { } { }
assign $3\corebusy_o[0:0] $13\corebusy_o[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $4\corebusy_o[0:0] $1\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $5\corebusy_o[0:0] $4\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $6\corebusy_o[0:0] $5\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $7\corebusy_o[0:0] $6\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $8\corebusy_o[0:0] $7\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [5]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $9\corebusy_o[0:0] $8\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [6]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $10\corebusy_o[0:0] $9\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [7]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $11\corebusy_o[0:0] $10\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [8]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $12\corebusy_o[0:0] $11\corebusy_o[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [9]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \corebusy_o $0\corebusy_o[0:0]
end
- attribute \src "libresoc.v:46620.3-46628.6"
- process $proc$libresoc.v:46620$2666
+ attribute \src "libresoc.v:46575.3-46583.6"
+ process $proc$libresoc.v:46575$2672
assign { } { }
assign { } { }
- assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668
- attribute \src "libresoc.v:46621.5-46621.29"
+ assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 $1\dp_FAST_fast1_branch0_0$next[0:0]$2674
+ attribute \src "libresoc.v:46576.5-46576.29"
switch \initial
- attribute \src "libresoc.v:46621.9-46621.17"
+ attribute \src "libresoc.v:46576.9-46576.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 1'0
+ assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 1'0
case
- assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 \rp_CR_cr_c_cr0_0
+ assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 \rp_FAST_fast1_branch0_0
end
sync always
- update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667
+ update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2673
end
- attribute \src "libresoc.v:46629.3-46638.6"
- process $proc$libresoc.v:46629$2669
+ attribute \src "libresoc.v:46584.3-46593.6"
+ process $proc$libresoc.v:46584$2675
assign { } { }
assign { } { }
- assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671
- attribute \src "libresoc.v:46630.5-46630.29"
+ assign $0\fus_src1_i$86[63:0]$2676 $1\fus_src1_i$86[63:0]$2677
+ attribute \src "libresoc.v:46585.5-46585.29"
switch \initial
- attribute \src "libresoc.v:46630.9-46630.17"
+ attribute \src "libresoc.v:46585.9-46585.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_CR_cr_c_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_FAST_fast1_branch0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src6_i$85[3:0]$2671 \cr_src3__data_o
+ assign $1\fus_src1_i$86[63:0]$2677 \fast_src1__data_o
case
- assign $1\fus_src6_i$85[3:0]$2671 4'0000
+ assign $1\fus_src1_i$86[63:0]$2677 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670
+ update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2676
end
- attribute \src "libresoc.v:46639.3-46659.6"
- process $proc$libresoc.v:46639$2672
+ attribute \src "libresoc.v:46594.3-46614.6"
+ process $proc$libresoc.v:46594$2678
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676
- attribute \src "libresoc.v:46640.5-46640.29"
+ assign $0\core_terminate_o$next[0:0]$2679 $3\core_terminate_o$next[0:0]$2682
+ attribute \src "libresoc.v:46595.5-46595.29"
switch \initial
- attribute \src "libresoc.v:46640.9-46640.17"
+ attribute \src "libresoc.v:46595.9-46595.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_terminate_o$next[0:0]$2674 $2\core_terminate_o$next[0:0]$2675
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ assign $1\core_terminate_o$next[0:0]$2680 $2\core_terminate_o$next[0:0]$2681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
- assign $2\core_terminate_o$next[0:0]$2675 1'1
+ assign $2\core_terminate_o$next[0:0]$2681 1'1
case
- assign $2\core_terminate_o$next[0:0]$2675 \core_terminate_o
+ assign $2\core_terminate_o$next[0:0]$2681 \core_terminate_o
end
case
- assign $1\core_terminate_o$next[0:0]$2674 \core_terminate_o
+ assign $1\core_terminate_o$next[0:0]$2680 \core_terminate_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_terminate_o$next[0:0]$2676 1'0
+ assign $3\core_terminate_o$next[0:0]$2682 1'0
case
- assign $3\core_terminate_o$next[0:0]$2676 $1\core_terminate_o$next[0:0]$2674
+ assign $3\core_terminate_o$next[0:0]$2682 $1\core_terminate_o$next[0:0]$2680
end
sync always
- update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673
+ update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2679
end
- attribute \src "libresoc.v:46660.3-46668.6"
- process $proc$libresoc.v:46660$2677
+ attribute \src "libresoc.v:46615.3-46623.6"
+ process $proc$libresoc.v:46615$2683
assign { } { }
assign { } { }
- assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679
- attribute \src "libresoc.v:46661.5-46661.29"
+ assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685
+ attribute \src "libresoc.v:46616.5-46616.29"
switch \initial
- attribute \src "libresoc.v:46661.9-46661.17"
+ attribute \src "libresoc.v:46616.9-46616.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 1'0
+ assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0
case
- assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 \rp_FAST_fast1_branch0_0
+ assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1
end
sync always
- update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678
+ update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684
end
- attribute \src "libresoc.v:46669.3-46678.6"
- process $proc$libresoc.v:46669$2680
+ attribute \src "libresoc.v:46624.3-46633.6"
+ process $proc$libresoc.v:46624$2686
assign { } { }
assign { } { }
- assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682
- attribute \src "libresoc.v:46670.5-46670.29"
+ assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688
+ attribute \src "libresoc.v:46625.5-46625.29"
switch \initial
- attribute \src "libresoc.v:46670.9-46670.17"
+ attribute \src "libresoc.v:46625.9-46625.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_FAST_fast1_branch0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_FAST_fast1_trap0_1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src1_i$86[63:0]$2682 \fast_src1__data_o
+ assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o
case
- assign $1\fus_src1_i$86[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681
+ update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687
end
- attribute \src "libresoc.v:46679.3-46687.6"
- process $proc$libresoc.v:46679$2683
+ attribute \src "libresoc.v:46634.3-46642.6"
+ process $proc$libresoc.v:46634$2689
assign { } { }
assign { } { }
- assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685
- attribute \src "libresoc.v:46680.5-46680.29"
+ assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 $1\dp_FAST_fast1_spr0_2$next[0:0]$2691
+ attribute \src "libresoc.v:46635.5-46635.29"
switch \initial
- attribute \src "libresoc.v:46680.9-46680.17"
+ attribute \src "libresoc.v:46635.9-46635.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0
+ assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 1'0
case
- assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1
+ assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 \rp_FAST_fast1_spr0_2
end
sync always
- update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684
+ update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2690
end
- attribute \src "libresoc.v:46688.3-46697.6"
- process $proc$libresoc.v:46688$2686
+ attribute \src "libresoc.v:46643.3-46652.6"
+ process $proc$libresoc.v:46643$2692
assign { } { }
assign { } { }
- assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688
- attribute \src "libresoc.v:46689.5-46689.29"
+ assign $0\fus_src3_i$88[63:0]$2693 $1\fus_src3_i$88[63:0]$2694
+ attribute \src "libresoc.v:46644.5-46644.29"
switch \initial
- attribute \src "libresoc.v:46689.9-46689.17"
+ attribute \src "libresoc.v:46644.9-46644.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_FAST_fast1_trap0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_FAST_fast1_spr0_2
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o
+ assign $1\fus_src3_i$88[63:0]$2694 \fast_src1__data_o
case
- assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src3_i$88[63:0]$2694 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687
+ update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2693
end
- attribute \src "libresoc.v:46698.3-46726.6"
- process $proc$libresoc.v:46698$2689
+ attribute \src "libresoc.v:46653.3-46681.6"
+ process $proc$libresoc.v:46653$2695
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "libresoc.v:46699.5-46699.29"
+ attribute \src "libresoc.v:46654.5-46654.29"
switch \initial
- attribute \src "libresoc.v:46699.9-46699.17"
+ attribute \src "libresoc.v:46654.9-46654.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0]
end
- attribute \src "libresoc.v:46727.3-46735.6"
- process $proc$libresoc.v:46727$2690
+ attribute \src "libresoc.v:46682.3-46690.6"
+ process $proc$libresoc.v:46682$2696
assign { } { }
assign { } { }
- assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692
- attribute \src "libresoc.v:46728.5-46728.29"
+ assign $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 $1\dp_FAST_fast1_branch0_3$next[0:0]$2698
+ attribute \src "libresoc.v:46683.5-46683.29"
switch \initial
- attribute \src "libresoc.v:46728.9-46728.17"
+ attribute \src "libresoc.v:46683.9-46683.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 1'0
+ assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 1'0
case
- assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 \rp_FAST_fast1_spr0_2
+ assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 \rp_FAST_fast1_branch0_3
end
sync always
- update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691
+ update \dp_FAST_fast1_branch0_3$next $0\dp_FAST_fast1_branch0_3$next[0:0]$2697
end
- attribute \src "libresoc.v:46736.3-46745.6"
- process $proc$libresoc.v:46736$2693
+ attribute \src "libresoc.v:46691.3-46700.6"
+ process $proc$libresoc.v:46691$2699
assign { } { }
assign { } { }
- assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695
- attribute \src "libresoc.v:46737.5-46737.29"
+ assign $0\fus_src2_i$89[63:0]$2700 $1\fus_src2_i$89[63:0]$2701
+ attribute \src "libresoc.v:46692.5-46692.29"
switch \initial
- attribute \src "libresoc.v:46737.9-46737.17"
+ attribute \src "libresoc.v:46692.9-46692.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_FAST_fast1_spr0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_FAST_fast1_branch0_3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src3_i$88[63:0]$2695 \fast_src1__data_o
+ assign $1\fus_src2_i$89[63:0]$2701 \fast_src1__data_o
case
- assign $1\fus_src3_i$88[63:0]$2695 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$89[63:0]$2701 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694
+ update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2700
end
- attribute \src "libresoc.v:46746.3-46774.6"
- process $proc$libresoc.v:46746$2696
+ attribute \src "libresoc.v:46701.3-46709.6"
+ process $proc$libresoc.v:46701$2702
assign { } { }
assign { } { }
- assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "libresoc.v:46747.5-46747.29"
+ assign $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 $1\dp_FAST_fast1_trap0_4$next[0:0]$2704
+ attribute \src "libresoc.v:46702.5-46702.29"
switch \initial
- attribute \src "libresoc.v:46747.9-46747.17"
+ attribute \src "libresoc.v:46702.9-46702.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
- switch \ivalid_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
- switch \core_core_insn_type
- attribute \src "libresoc.v:0.0-0.0"
- case 7'0000101
- assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
- attribute \src "libresoc.v:0.0-0.0"
- case 7'0000001
- assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
- switch \fu_enable [0]
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit
- case
- assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
- end
- end
+ assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 1'0
case
- assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
+ assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 \rp_FAST_fast1_trap0_4
end
sync always
- update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0]
+ update \dp_FAST_fast1_trap0_4$next $0\dp_FAST_fast1_trap0_4$next[0:0]$2703
end
- attribute \src "libresoc.v:46775.3-46783.6"
- process $proc$libresoc.v:46775$2697
+ attribute \src "libresoc.v:46710.3-46719.6"
+ process $proc$libresoc.v:46710$2705
assign { } { }
assign { } { }
- assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699
- attribute \src "libresoc.v:46776.5-46776.29"
+ assign $0\fus_src4_i$90[63:0]$2706 $1\fus_src4_i$90[63:0]$2707
+ attribute \src "libresoc.v:46711.5-46711.29"
switch \initial
- attribute \src "libresoc.v:46776.9-46776.17"
+ attribute \src "libresoc.v:46711.9-46711.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_FAST_fast1_trap0_4
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 1'0
+ assign $1\fus_src4_i$90[63:0]$2707 \fast_src1__data_o
case
- assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 \rp_FAST_fast2_branch0_0
+ assign $1\fus_src4_i$90[63:0]$2707 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698
+ update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2706
end
- attribute \src "libresoc.v:46784.3-46793.6"
- process $proc$libresoc.v:46784$2700
+ attribute \src "libresoc.v:46720.3-46748.6"
+ process $proc$libresoc.v:46720$2708
assign { } { }
assign { } { }
- assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702
- attribute \src "libresoc.v:46785.5-46785.29"
+ assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0]
+ attribute \src "libresoc.v:46721.5-46721.29"
switch \initial
- attribute \src "libresoc.v:46785.9-46785.17"
+ attribute \src "libresoc.v:46721.9-46721.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_FAST_fast2_branch0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
+ switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src2_i$89[63:0]$2702 \fast_src2__data_o
+ assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
+ switch \core_core_insn_type
+ attribute \src "libresoc.v:0.0-0.0"
+ case 7'0000101
+ assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 7'0000001
+ assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
+ switch \fu_enable [0]
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit
+ case
+ assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
+ end
+ end
case
- assign $1\fus_src2_i$89[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000
end
sync always
- update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701
+ update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0]
end
- attribute \src "libresoc.v:46794.3-46802.6"
- process $proc$libresoc.v:46794$2703
+ attribute \src "libresoc.v:46749.3-46757.6"
+ process $proc$libresoc.v:46749$2709
assign { } { }
assign { } { }
- assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705
- attribute \src "libresoc.v:46795.5-46795.29"
+ assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 $1\dp_SPR_spr1_spr0_0$next[0:0]$2711
+ attribute \src "libresoc.v:46750.5-46750.29"
switch \initial
- attribute \src "libresoc.v:46795.9-46795.17"
+ attribute \src "libresoc.v:46750.9-46750.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 1'0
+ assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 1'0
case
- assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 \rp_FAST_fast2_trap0_1
+ assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 \rp_SPR_spr1_spr0_0
end
sync always
- update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704
+ update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2710
end
- attribute \src "libresoc.v:46803.3-46812.6"
- process $proc$libresoc.v:46803$2706
+ attribute \src "libresoc.v:46758.3-46767.6"
+ process $proc$libresoc.v:46758$2712
assign { } { }
assign { } { }
- assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708
- attribute \src "libresoc.v:46804.5-46804.29"
+ assign $0\fus_src2_i$91[63:0]$2713 $1\fus_src2_i$91[63:0]$2714
+ attribute \src "libresoc.v:46759.5-46759.29"
switch \initial
- attribute \src "libresoc.v:46804.9-46804.17"
+ attribute \src "libresoc.v:46759.9-46759.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_FAST_fast2_trap0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304"
+ switch \dp_SPR_spr1_spr0_0
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_src4_i$90[63:0]$2708 \fast_src2__data_o
+ assign $1\fus_src2_i$91[63:0]$2714 \spr_spr1__data_o
case
- assign $1\fus_src4_i$90[63:0]$2708 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fus_src2_i$91[63:0]$2714 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707
+ update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2713
end
- attribute \src "libresoc.v:46813.3-46842.6"
- process $proc$libresoc.v:46813$2709
+ attribute \src "libresoc.v:46768.3-46797.6"
+ process $proc$libresoc.v:46768$2715
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "libresoc.v:46814.5-46814.29"
+ attribute \src "libresoc.v:46769.5-46769.29"
switch \initial
- attribute \src "libresoc.v:46814.9-46814.17"
+ attribute \src "libresoc.v:46769.9-46769.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0]
update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:46843.3-46851.6"
- process $proc$libresoc.v:46843$2710
+ attribute \src "libresoc.v:46798.3-46806.6"
+ process $proc$libresoc.v:46798$2716
assign { } { }
assign { } { }
- assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712
- attribute \src "libresoc.v:46844.5-46844.29"
+ assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718
+ attribute \src "libresoc.v:46799.5-46799.29"
switch \initial
- attribute \src "libresoc.v:46844.9-46844.17"
+ attribute \src "libresoc.v:46799.9-46799.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 1'0
- case
- assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 \rp_SPR_spr1_spr0_0
- end
- sync always
- update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711
- end
- attribute \src "libresoc.v:46852.3-46861.6"
- process $proc$libresoc.v:46852$2713
- assign { } { }
- assign { } { }
- assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715
- attribute \src "libresoc.v:46853.5-46853.29"
- switch \initial
- attribute \src "libresoc.v:46853.9-46853.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300"
- switch \dp_SPR_spr1_spr0_0
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\fus_src2_i$91[63:0]$2715 \spr_spr1__data_o
+ assign $1\wr_pick_dly$next[0:0]$2718 1'0
case
- assign $1\fus_src2_i$91[63:0]$2715 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick
end
sync always
- update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714
+ update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717
end
- attribute \src "libresoc.v:46862.3-46870.6"
- process $proc$libresoc.v:46862$2716
+ attribute \src "libresoc.v:46807.3-46815.6"
+ process $proc$libresoc.v:46807$2719
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718
- attribute \src "libresoc.v:46863.5-46863.29"
+ assign $0\wr_pick_dly$989$next[0:0]$2720 $1\wr_pick_dly$989$next[0:0]$2721
+ attribute \src "libresoc.v:46808.5-46808.29"
switch \initial
- attribute \src "libresoc.v:46863.9-46863.17"
+ attribute \src "libresoc.v:46808.9-46808.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$next[0:0]$2718 1'0
+ assign $1\wr_pick_dly$989$next[0:0]$2721 1'0
case
- assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick
+ assign $1\wr_pick_dly$989$next[0:0]$2721 \wr_pick$986
end
sync always
- update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717
+ update \wr_pick_dly$989$next $0\wr_pick_dly$989$next[0:0]$2720
end
- attribute \src "libresoc.v:46871.3-46879.6"
- process $proc$libresoc.v:46871$2719
+ attribute \src "libresoc.v:46816.3-46824.6"
+ process $proc$libresoc.v:46816$2722
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721
- attribute \src "libresoc.v:46872.5-46872.29"
+ assign $0\wr_pick_dly$1008$next[0:0]$2723 $1\wr_pick_dly$1008$next[0:0]$2724
+ attribute \src "libresoc.v:46817.5-46817.29"
switch \initial
- attribute \src "libresoc.v:46872.9-46872.17"
+ attribute \src "libresoc.v:46817.9-46817.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$991$next[0:0]$2721 1'0
+ assign $1\wr_pick_dly$1008$next[0:0]$2724 1'0
case
- assign $1\wr_pick_dly$991$next[0:0]$2721 \wr_pick$988
+ assign $1\wr_pick_dly$1008$next[0:0]$2724 \wr_pick$1005
end
sync always
- update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720
+ update \wr_pick_dly$1008$next $0\wr_pick_dly$1008$next[0:0]$2723
end
- attribute \src "libresoc.v:46880.3-46909.6"
- process $proc$libresoc.v:46880$2722
+ attribute \src "libresoc.v:46825.3-46854.6"
+ process $proc$libresoc.v:46825$2725
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0]
assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "libresoc.v:46881.5-46881.29"
+ attribute \src "libresoc.v:46826.5-46826.29"
switch \initial
- attribute \src "libresoc.v:46881.9-46881.17"
+ attribute \src "libresoc.v:46826.9-46826.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0]
assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0]
assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0]
update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0]
end
- attribute \src "libresoc.v:46910.3-46918.6"
- process $proc$libresoc.v:46910$2723
+ attribute \src "libresoc.v:46855.3-46863.6"
+ process $proc$libresoc.v:46855$2726
+ assign { } { }
+ assign { } { }
+ assign $0\wr_pick_dly$1029$next[0:0]$2727 $1\wr_pick_dly$1029$next[0:0]$2728
+ attribute \src "libresoc.v:46856.5-46856.29"
+ switch \initial
+ attribute \src "libresoc.v:46856.9-46856.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\wr_pick_dly$1029$next[0:0]$2728 1'0
+ case
+ assign $1\wr_pick_dly$1029$next[0:0]$2728 \wr_pick$1026
+ end
+ sync always
+ update \wr_pick_dly$1029$next $0\wr_pick_dly$1029$next[0:0]$2727
+ end
+ attribute \src "libresoc.v:46864.3-46872.6"
+ process $proc$libresoc.v:46864$2729
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725
- attribute \src "libresoc.v:46911.5-46911.29"
+ assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731
+ attribute \src "libresoc.v:46865.5-46865.29"
switch \initial
- attribute \src "libresoc.v:46911.9-46911.17"
+ attribute \src "libresoc.v:46865.9-46865.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1010$next[0:0]$2725 1'0
+ assign $1\wr_pick_dly$1047$next[0:0]$2731 1'0
case
- assign $1\wr_pick_dly$1010$next[0:0]$2725 \wr_pick$1007
+ assign $1\wr_pick_dly$1047$next[0:0]$2731 \wr_pick$1044
end
sync always
- update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724
+ update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730
end
- attribute \src "libresoc.v:46919.3-46927.6"
- process $proc$libresoc.v:46919$2726
+ attribute \src "libresoc.v:46873.3-46881.6"
+ process $proc$libresoc.v:46873$2732
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728
- attribute \src "libresoc.v:46920.5-46920.29"
+ assign $0\wr_pick_dly$1069$next[0:0]$2733 $1\wr_pick_dly$1069$next[0:0]$2734
+ attribute \src "libresoc.v:46874.5-46874.29"
switch \initial
- attribute \src "libresoc.v:46920.9-46920.17"
+ attribute \src "libresoc.v:46874.9-46874.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1031$next[0:0]$2728 1'0
+ assign $1\wr_pick_dly$1069$next[0:0]$2734 1'0
case
- assign $1\wr_pick_dly$1031$next[0:0]$2728 \wr_pick$1028
+ assign $1\wr_pick_dly$1069$next[0:0]$2734 \wr_pick$1066
end
sync always
- update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727
+ update \wr_pick_dly$1069$next $0\wr_pick_dly$1069$next[0:0]$2733
end
- attribute \src "libresoc.v:46928.3-46957.6"
- process $proc$libresoc.v:46928$2729
+ attribute \src "libresoc.v:46882.3-46911.6"
+ process $proc$libresoc.v:46882$2735
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0]
assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "libresoc.v:46929.5-46929.29"
+ attribute \src "libresoc.v:46883.5-46883.29"
switch \initial
- attribute \src "libresoc.v:46929.9-46929.17"
+ attribute \src "libresoc.v:46883.9-46883.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0]
assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0]
assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0]
update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0]
end
- attribute \src "libresoc.v:46958.3-46966.6"
- process $proc$libresoc.v:46958$2730
+ attribute \src "libresoc.v:46912.3-46920.6"
+ process $proc$libresoc.v:46912$2736
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732
- attribute \src "libresoc.v:46959.5-46959.29"
+ assign $0\wr_pick_dly$1089$next[0:0]$2737 $1\wr_pick_dly$1089$next[0:0]$2738
+ attribute \src "libresoc.v:46913.5-46913.29"
switch \initial
- attribute \src "libresoc.v:46959.9-46959.17"
+ attribute \src "libresoc.v:46913.9-46913.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1049$next[0:0]$2732 1'0
+ assign $1\wr_pick_dly$1089$next[0:0]$2738 1'0
case
- assign $1\wr_pick_dly$1049$next[0:0]$2732 \wr_pick$1046
+ assign $1\wr_pick_dly$1089$next[0:0]$2738 \wr_pick$1086
end
sync always
- update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731
+ update \wr_pick_dly$1089$next $0\wr_pick_dly$1089$next[0:0]$2737
end
- attribute \src "libresoc.v:46967.3-46975.6"
- process $proc$libresoc.v:46967$2733
+ attribute \src "libresoc.v:46921.3-46929.6"
+ process $proc$libresoc.v:46921$2739
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735
- attribute \src "libresoc.v:46968.5-46968.29"
+ assign $0\wr_pick_dly$1109$next[0:0]$2740 $1\wr_pick_dly$1109$next[0:0]$2741
+ attribute \src "libresoc.v:46922.5-46922.29"
switch \initial
- attribute \src "libresoc.v:46968.9-46968.17"
+ attribute \src "libresoc.v:46922.9-46922.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1071$next[0:0]$2735 1'0
+ assign $1\wr_pick_dly$1109$next[0:0]$2741 1'0
case
- assign $1\wr_pick_dly$1071$next[0:0]$2735 \wr_pick$1068
+ assign $1\wr_pick_dly$1109$next[0:0]$2741 \wr_pick$1106
end
sync always
- update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734
+ update \wr_pick_dly$1109$next $0\wr_pick_dly$1109$next[0:0]$2740
end
- attribute \src "libresoc.v:46976.3-46984.6"
- process $proc$libresoc.v:46976$2736
+ attribute \src "libresoc.v:46930.3-46938.6"
+ process $proc$libresoc.v:46930$2742
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738
- attribute \src "libresoc.v:46977.5-46977.29"
+ assign $0\wr_pick_dly$1128$next[0:0]$2743 $1\wr_pick_dly$1128$next[0:0]$2744
+ attribute \src "libresoc.v:46931.5-46931.29"
switch \initial
- attribute \src "libresoc.v:46977.9-46977.17"
+ attribute \src "libresoc.v:46931.9-46931.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1091$next[0:0]$2738 1'0
+ assign $1\wr_pick_dly$1128$next[0:0]$2744 1'0
case
- assign $1\wr_pick_dly$1091$next[0:0]$2738 \wr_pick$1088
+ assign $1\wr_pick_dly$1128$next[0:0]$2744 \wr_pick$1125
end
sync always
- update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737
+ update \wr_pick_dly$1128$next $0\wr_pick_dly$1128$next[0:0]$2743
end
- attribute \src "libresoc.v:46985.3-47013.6"
- process $proc$libresoc.v:46985$2739
+ attribute \src "libresoc.v:46939.3-46967.6"
+ process $proc$libresoc.v:46939$2745
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "libresoc.v:46986.5-46986.29"
+ attribute \src "libresoc.v:46940.5-46940.29"
switch \initial
- attribute \src "libresoc.v:46986.9-46986.17"
+ attribute \src "libresoc.v:46940.9-46940.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0]
end
- attribute \src "libresoc.v:47014.3-47022.6"
- process $proc$libresoc.v:47014$2740
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742
- attribute \src "libresoc.v:47015.5-47015.29"
- switch \initial
- attribute \src "libresoc.v:47015.9-47015.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1111$next[0:0]$2742 1'0
- case
- assign $1\wr_pick_dly$1111$next[0:0]$2742 \wr_pick$1108
- end
- sync always
- update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741
- end
- attribute \src "libresoc.v:47023.3-47031.6"
- process $proc$libresoc.v:47023$2743
+ attribute \src "libresoc.v:46968.3-46976.6"
+ process $proc$libresoc.v:46968$2746
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745
- attribute \src "libresoc.v:47024.5-47024.29"
+ assign $0\wr_pick_dly$1146$next[0:0]$2747 $1\wr_pick_dly$1146$next[0:0]$2748
+ attribute \src "libresoc.v:46969.5-46969.29"
switch \initial
- attribute \src "libresoc.v:47024.9-47024.17"
+ attribute \src "libresoc.v:46969.9-46969.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1130$next[0:0]$2745 1'0
+ assign $1\wr_pick_dly$1146$next[0:0]$2748 1'0
case
- assign $1\wr_pick_dly$1130$next[0:0]$2745 \wr_pick$1127
+ assign $1\wr_pick_dly$1146$next[0:0]$2748 \wr_pick$1143
end
sync always
- update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744
+ update \wr_pick_dly$1146$next $0\wr_pick_dly$1146$next[0:0]$2747
end
- attribute \src "libresoc.v:47032.3-47060.6"
- process $proc$libresoc.v:47032$2746
+ attribute \src "libresoc.v:46977.3-47005.6"
+ process $proc$libresoc.v:46977$2749
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "libresoc.v:47033.5-47033.29"
+ attribute \src "libresoc.v:46978.5-46978.29"
switch \initial
- attribute \src "libresoc.v:47033.9-47033.17"
+ attribute \src "libresoc.v:46978.9-46978.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0]
end
- attribute \src "libresoc.v:47061.3-47069.6"
- process $proc$libresoc.v:47061$2747
+ attribute \src "libresoc.v:47006.3-47014.6"
+ process $proc$libresoc.v:47006$2750
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749
- attribute \src "libresoc.v:47062.5-47062.29"
+ assign $0\wr_pick_dly$1220$next[0:0]$2751 $1\wr_pick_dly$1220$next[0:0]$2752
+ attribute \src "libresoc.v:47007.5-47007.29"
switch \initial
- attribute \src "libresoc.v:47062.9-47062.17"
+ attribute \src "libresoc.v:47007.9-47007.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1148$next[0:0]$2749 1'0
+ assign $1\wr_pick_dly$1220$next[0:0]$2752 1'0
case
- assign $1\wr_pick_dly$1148$next[0:0]$2749 \wr_pick$1145
+ assign $1\wr_pick_dly$1220$next[0:0]$2752 \wr_pick$1217
end
sync always
- update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748
+ update \wr_pick_dly$1220$next $0\wr_pick_dly$1220$next[0:0]$2751
end
- attribute \src "libresoc.v:47070.3-47098.6"
- process $proc$libresoc.v:47070$2750
+ attribute \src "libresoc.v:47015.3-47043.6"
+ process $proc$libresoc.v:47015$2753
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "libresoc.v:47071.5-47071.29"
+ attribute \src "libresoc.v:47016.5-47016.29"
switch \initial
- attribute \src "libresoc.v:47071.9-47071.17"
+ attribute \src "libresoc.v:47016.9-47016.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0]
end
- attribute \src "libresoc.v:47099.3-47107.6"
- process $proc$libresoc.v:47099$2751
+ attribute \src "libresoc.v:47044.3-47052.6"
+ process $proc$libresoc.v:47044$2754
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753
- attribute \src "libresoc.v:47100.5-47100.29"
+ assign $0\wr_pick_dly$1248$next[0:0]$2755 $1\wr_pick_dly$1248$next[0:0]$2756
+ attribute \src "libresoc.v:47045.5-47045.29"
switch \initial
- attribute \src "libresoc.v:47100.9-47100.17"
+ attribute \src "libresoc.v:47045.9-47045.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1222$next[0:0]$2753 1'0
+ assign $1\wr_pick_dly$1248$next[0:0]$2756 1'0
case
- assign $1\wr_pick_dly$1222$next[0:0]$2753 \wr_pick$1219
+ assign $1\wr_pick_dly$1248$next[0:0]$2756 \wr_pick$1245
end
sync always
- update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752
+ update \wr_pick_dly$1248$next $0\wr_pick_dly$1248$next[0:0]$2755
end
- attribute \src "libresoc.v:47108.3-47136.6"
- process $proc$libresoc.v:47108$2754
+ attribute \src "libresoc.v:47053.3-47081.6"
+ process $proc$libresoc.v:47053$2757
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "libresoc.v:47109.5-47109.29"
+ attribute \src "libresoc.v:47054.5-47054.29"
switch \initial
- attribute \src "libresoc.v:47109.9-47109.17"
+ attribute \src "libresoc.v:47054.9-47054.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0]
end
- attribute \src "libresoc.v:47137.3-47145.6"
- process $proc$libresoc.v:47137$2755
+ attribute \src "libresoc.v:47082.3-47090.6"
+ process $proc$libresoc.v:47082$2758
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757
- attribute \src "libresoc.v:47138.5-47138.29"
+ assign $0\wr_pick_dly$1268$next[0:0]$2759 $1\wr_pick_dly$1268$next[0:0]$2760
+ attribute \src "libresoc.v:47083.5-47083.29"
switch \initial
- attribute \src "libresoc.v:47138.9-47138.17"
+ attribute \src "libresoc.v:47083.9-47083.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1250$next[0:0]$2757 1'0
+ assign $1\wr_pick_dly$1268$next[0:0]$2760 1'0
case
- assign $1\wr_pick_dly$1250$next[0:0]$2757 \wr_pick$1247
+ assign $1\wr_pick_dly$1268$next[0:0]$2760 \wr_pick$1265
end
sync always
- update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756
+ update \wr_pick_dly$1268$next $0\wr_pick_dly$1268$next[0:0]$2759
end
- attribute \src "libresoc.v:47146.3-47174.6"
- process $proc$libresoc.v:47146$2758
+ attribute \src "libresoc.v:47091.3-47099.6"
+ process $proc$libresoc.v:47091$2761
+ assign { } { }
+ assign { } { }
+ assign $0\wr_pick_dly$1288$next[0:0]$2762 $1\wr_pick_dly$1288$next[0:0]$2763
+ attribute \src "libresoc.v:47092.5-47092.29"
+ switch \initial
+ attribute \src "libresoc.v:47092.9-47092.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\wr_pick_dly$1288$next[0:0]$2763 1'0
+ case
+ assign $1\wr_pick_dly$1288$next[0:0]$2763 \wr_pick$1285
+ end
+ sync always
+ update \wr_pick_dly$1288$next $0\wr_pick_dly$1288$next[0:0]$2762
+ end
+ attribute \src "libresoc.v:47100.3-47128.6"
+ process $proc$libresoc.v:47100$2764
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "libresoc.v:47147.5-47147.29"
+ attribute \src "libresoc.v:47101.5-47101.29"
switch \initial
- attribute \src "libresoc.v:47147.9-47147.17"
+ attribute \src "libresoc.v:47101.9-47101.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0]
end
- attribute \src "libresoc.v:47175.3-47183.6"
- process $proc$libresoc.v:47175$2759
+ attribute \src "libresoc.v:47129.3-47137.6"
+ process $proc$libresoc.v:47129$2765
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761
- attribute \src "libresoc.v:47176.5-47176.29"
+ assign $0\wr_pick_dly$1308$next[0:0]$2766 $1\wr_pick_dly$1308$next[0:0]$2767
+ attribute \src "libresoc.v:47130.5-47130.29"
switch \initial
- attribute \src "libresoc.v:47176.9-47176.17"
+ attribute \src "libresoc.v:47130.9-47130.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1270$next[0:0]$2761 1'0
+ assign $1\wr_pick_dly$1308$next[0:0]$2767 1'0
case
- assign $1\wr_pick_dly$1270$next[0:0]$2761 \wr_pick$1267
+ assign $1\wr_pick_dly$1308$next[0:0]$2767 \wr_pick$1305
end
sync always
- update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760
+ update \wr_pick_dly$1308$next $0\wr_pick_dly$1308$next[0:0]$2766
end
- attribute \src "libresoc.v:47184.3-47192.6"
- process $proc$libresoc.v:47184$2762
+ attribute \src "libresoc.v:47138.3-47146.6"
+ process $proc$libresoc.v:47138$2768
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764
- attribute \src "libresoc.v:47185.5-47185.29"
+ assign $0\wr_pick_dly$1328$next[0:0]$2769 $1\wr_pick_dly$1328$next[0:0]$2770
+ attribute \src "libresoc.v:47139.5-47139.29"
switch \initial
- attribute \src "libresoc.v:47185.9-47185.17"
+ attribute \src "libresoc.v:47139.9-47139.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1290$next[0:0]$2764 1'0
+ assign $1\wr_pick_dly$1328$next[0:0]$2770 1'0
case
- assign $1\wr_pick_dly$1290$next[0:0]$2764 \wr_pick$1287
+ assign $1\wr_pick_dly$1328$next[0:0]$2770 \wr_pick$1325
end
sync always
- update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763
+ update \wr_pick_dly$1328$next $0\wr_pick_dly$1328$next[0:0]$2769
end
- attribute \src "libresoc.v:47193.3-47221.6"
- process $proc$libresoc.v:47193$2765
+ attribute \src "libresoc.v:47147.3-47175.6"
+ process $proc$libresoc.v:47147$2771
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "libresoc.v:47194.5-47194.29"
+ attribute \src "libresoc.v:47148.5-47148.29"
switch \initial
- attribute \src "libresoc.v:47194.9-47194.17"
+ attribute \src "libresoc.v:47148.9-47148.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0]
end
- attribute \src "libresoc.v:47222.3-47230.6"
- process $proc$libresoc.v:47222$2766
+ attribute \src "libresoc.v:47176.3-47184.6"
+ process $proc$libresoc.v:47176$2772
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768
- attribute \src "libresoc.v:47223.5-47223.29"
+ assign $0\wr_pick_dly$1348$next[0:0]$2773 $1\wr_pick_dly$1348$next[0:0]$2774
+ attribute \src "libresoc.v:47177.5-47177.29"
switch \initial
- attribute \src "libresoc.v:47223.9-47223.17"
+ attribute \src "libresoc.v:47177.9-47177.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1310$next[0:0]$2768 1'0
+ assign $1\wr_pick_dly$1348$next[0:0]$2774 1'0
case
- assign $1\wr_pick_dly$1310$next[0:0]$2768 \wr_pick$1307
+ assign $1\wr_pick_dly$1348$next[0:0]$2774 \wr_pick$1345
end
sync always
- update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767
+ update \wr_pick_dly$1348$next $0\wr_pick_dly$1348$next[0:0]$2773
end
- attribute \src "libresoc.v:47231.3-47239.6"
- process $proc$libresoc.v:47231$2769
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771
- attribute \src "libresoc.v:47232.5-47232.29"
- switch \initial
- attribute \src "libresoc.v:47232.9-47232.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1330$next[0:0]$2771 1'0
- case
- assign $1\wr_pick_dly$1330$next[0:0]$2771 \wr_pick$1327
- end
- sync always
- update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770
- end
- attribute \src "libresoc.v:47240.3-47268.6"
- process $proc$libresoc.v:47240$2772
+ attribute \src "libresoc.v:47185.3-47213.6"
+ process $proc$libresoc.v:47185$2775
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "libresoc.v:47241.5-47241.29"
+ attribute \src "libresoc.v:47186.5-47186.29"
switch \initial
- attribute \src "libresoc.v:47241.9-47241.17"
+ attribute \src "libresoc.v:47186.9-47186.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0]
end
- attribute \src "libresoc.v:47269.3-47277.6"
- process $proc$libresoc.v:47269$2773
+ attribute \src "libresoc.v:47214.3-47222.6"
+ process $proc$libresoc.v:47214$2776
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775
- attribute \src "libresoc.v:47270.5-47270.29"
+ assign $0\wr_pick_dly$1395$next[0:0]$2777 $1\wr_pick_dly$1395$next[0:0]$2778
+ attribute \src "libresoc.v:47215.5-47215.29"
switch \initial
- attribute \src "libresoc.v:47270.9-47270.17"
+ attribute \src "libresoc.v:47215.9-47215.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1350$next[0:0]$2775 1'0
+ assign $1\wr_pick_dly$1395$next[0:0]$2778 1'0
case
- assign $1\wr_pick_dly$1350$next[0:0]$2775 \wr_pick$1347
+ assign $1\wr_pick_dly$1395$next[0:0]$2778 \wr_pick$1392
end
sync always
- update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774
+ update \wr_pick_dly$1395$next $0\wr_pick_dly$1395$next[0:0]$2777
end
- attribute \src "libresoc.v:47278.3-47306.6"
- process $proc$libresoc.v:47278$2776
+ attribute \src "libresoc.v:47223.3-47251.6"
+ process $proc$libresoc.v:47223$2779
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "libresoc.v:47279.5-47279.29"
+ attribute \src "libresoc.v:47224.5-47224.29"
switch \initial
- attribute \src "libresoc.v:47279.9-47279.17"
+ attribute \src "libresoc.v:47224.9-47224.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0]
end
- attribute \src "libresoc.v:47307.3-47315.6"
- process $proc$libresoc.v:47307$2777
+ attribute \src "libresoc.v:47252.3-47260.6"
+ process $proc$libresoc.v:47252$2780
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779
- attribute \src "libresoc.v:47308.5-47308.29"
+ assign $0\wr_pick_dly$1411$next[0:0]$2781 $1\wr_pick_dly$1411$next[0:0]$2782
+ attribute \src "libresoc.v:47253.5-47253.29"
switch \initial
- attribute \src "libresoc.v:47308.9-47308.17"
+ attribute \src "libresoc.v:47253.9-47253.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1397$next[0:0]$2779 1'0
+ assign $1\wr_pick_dly$1411$next[0:0]$2782 1'0
case
- assign $1\wr_pick_dly$1397$next[0:0]$2779 \wr_pick$1394
+ assign $1\wr_pick_dly$1411$next[0:0]$2782 \wr_pick$1408
end
sync always
- update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778
+ update \wr_pick_dly$1411$next $0\wr_pick_dly$1411$next[0:0]$2781
end
- attribute \src "libresoc.v:47316.3-47324.6"
- process $proc$libresoc.v:47316$2780
+ attribute \src "libresoc.v:47261.3-47269.6"
+ process $proc$libresoc.v:47261$2783
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782
- attribute \src "libresoc.v:47317.5-47317.29"
+ assign $0\wr_pick_dly$1427$next[0:0]$2784 $1\wr_pick_dly$1427$next[0:0]$2785
+ attribute \src "libresoc.v:47262.5-47262.29"
switch \initial
- attribute \src "libresoc.v:47317.9-47317.17"
+ attribute \src "libresoc.v:47262.9-47262.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1413$next[0:0]$2782 1'0
+ assign $1\wr_pick_dly$1427$next[0:0]$2785 1'0
case
- assign $1\wr_pick_dly$1413$next[0:0]$2782 \wr_pick$1410
+ assign $1\wr_pick_dly$1427$next[0:0]$2785 \wr_pick$1424
end
sync always
- update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781
+ update \wr_pick_dly$1427$next $0\wr_pick_dly$1427$next[0:0]$2784
end
- attribute \src "libresoc.v:47325.3-47353.6"
- process $proc$libresoc.v:47325$2783
+ attribute \src "libresoc.v:47270.3-47298.6"
+ process $proc$libresoc.v:47270$2786
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "libresoc.v:47326.5-47326.29"
+ attribute \src "libresoc.v:47271.5-47271.29"
switch \initial
- attribute \src "libresoc.v:47326.9-47326.17"
+ attribute \src "libresoc.v:47271.9-47271.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0]
end
- attribute \src "libresoc.v:47354.3-47362.6"
- process $proc$libresoc.v:47354$2784
+ attribute \src "libresoc.v:47299.3-47307.6"
+ process $proc$libresoc.v:47299$2787
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786
- attribute \src "libresoc.v:47355.5-47355.29"
+ assign $0\wr_pick_dly$1461$next[0:0]$2788 $1\wr_pick_dly$1461$next[0:0]$2789
+ attribute \src "libresoc.v:47300.5-47300.29"
switch \initial
- attribute \src "libresoc.v:47355.9-47355.17"
+ attribute \src "libresoc.v:47300.9-47300.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1429$next[0:0]$2786 1'0
+ assign $1\wr_pick_dly$1461$next[0:0]$2789 1'0
case
- assign $1\wr_pick_dly$1429$next[0:0]$2786 \wr_pick$1426
+ assign $1\wr_pick_dly$1461$next[0:0]$2789 \wr_pick$1458
end
sync always
- update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785
+ update \wr_pick_dly$1461$next $0\wr_pick_dly$1461$next[0:0]$2788
end
- attribute \src "libresoc.v:47363.3-47391.6"
- process $proc$libresoc.v:47363$2787
+ attribute \src "libresoc.v:47308.3-47336.6"
+ process $proc$libresoc.v:47308$2790
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "libresoc.v:47364.5-47364.29"
+ attribute \src "libresoc.v:47309.5-47309.29"
switch \initial
- attribute \src "libresoc.v:47364.9-47364.17"
+ attribute \src "libresoc.v:47309.9-47309.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0]
end
- attribute \src "libresoc.v:47392.3-47400.6"
- process $proc$libresoc.v:47392$2788
+ attribute \src "libresoc.v:47337.3-47345.6"
+ process $proc$libresoc.v:47337$2791
+ assign { } { }
+ assign { } { }
+ assign $0\wr_pick_dly$1477$next[0:0]$2792 $1\wr_pick_dly$1477$next[0:0]$2793
+ attribute \src "libresoc.v:47338.5-47338.29"
+ switch \initial
+ attribute \src "libresoc.v:47338.9-47338.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\wr_pick_dly$1477$next[0:0]$2793 1'0
+ case
+ assign $1\wr_pick_dly$1477$next[0:0]$2793 \wr_pick$1474
+ end
+ sync always
+ update \wr_pick_dly$1477$next $0\wr_pick_dly$1477$next[0:0]$2792
+ end
+ attribute \src "libresoc.v:47346.3-47354.6"
+ process $proc$libresoc.v:47346$2794
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790
- attribute \src "libresoc.v:47393.5-47393.29"
+ assign $0\wr_pick_dly$1493$next[0:0]$2795 $1\wr_pick_dly$1493$next[0:0]$2796
+ attribute \src "libresoc.v:47347.5-47347.29"
switch \initial
- attribute \src "libresoc.v:47393.9-47393.17"
+ attribute \src "libresoc.v:47347.9-47347.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1463$next[0:0]$2790 1'0
+ assign $1\wr_pick_dly$1493$next[0:0]$2796 1'0
case
- assign $1\wr_pick_dly$1463$next[0:0]$2790 \wr_pick$1460
+ assign $1\wr_pick_dly$1493$next[0:0]$2796 \wr_pick$1490
end
sync always
- update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789
+ update \wr_pick_dly$1493$next $0\wr_pick_dly$1493$next[0:0]$2795
end
- attribute \src "libresoc.v:47401.3-47429.6"
- process $proc$libresoc.v:47401$2791
+ attribute \src "libresoc.v:47355.3-47383.6"
+ process $proc$libresoc.v:47355$2797
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0]
- attribute \src "libresoc.v:47402.5-47402.29"
+ attribute \src "libresoc.v:47356.5-47356.29"
switch \initial
- attribute \src "libresoc.v:47402.9-47402.17"
+ attribute \src "libresoc.v:47356.9-47356.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i $0\fus_cu_issue_i[0:0]
end
- attribute \src "libresoc.v:47430.3-47438.6"
- process $proc$libresoc.v:47430$2792
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794
- attribute \src "libresoc.v:47431.5-47431.29"
- switch \initial
- attribute \src "libresoc.v:47431.9-47431.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1479$next[0:0]$2794 1'0
- case
- assign $1\wr_pick_dly$1479$next[0:0]$2794 \wr_pick$1476
- end
- sync always
- update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793
- end
- attribute \src "libresoc.v:47439.3-47447.6"
- process $proc$libresoc.v:47439$2795
+ attribute \src "libresoc.v:47384.3-47392.6"
+ process $proc$libresoc.v:47384$2798
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797
- attribute \src "libresoc.v:47440.5-47440.29"
+ assign $0\wr_pick_dly$1509$next[0:0]$2799 $1\wr_pick_dly$1509$next[0:0]$2800
+ attribute \src "libresoc.v:47385.5-47385.29"
switch \initial
- attribute \src "libresoc.v:47440.9-47440.17"
+ attribute \src "libresoc.v:47385.9-47385.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1495$next[0:0]$2797 1'0
+ assign $1\wr_pick_dly$1509$next[0:0]$2800 1'0
case
- assign $1\wr_pick_dly$1495$next[0:0]$2797 \wr_pick$1492
+ assign $1\wr_pick_dly$1509$next[0:0]$2800 \wr_pick$1506
end
sync always
- update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796
+ update \wr_pick_dly$1509$next $0\wr_pick_dly$1509$next[0:0]$2799
end
- attribute \src "libresoc.v:47448.3-47476.6"
- process $proc$libresoc.v:47448$2798
+ attribute \src "libresoc.v:47393.3-47421.6"
+ process $proc$libresoc.v:47393$2801
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0]
- attribute \src "libresoc.v:47449.5-47449.29"
+ attribute \src "libresoc.v:47394.5-47394.29"
switch \initial
- attribute \src "libresoc.v:47449.9-47449.17"
+ attribute \src "libresoc.v:47394.9-47394.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0]
end
- attribute \src "libresoc.v:47477.3-47485.6"
- process $proc$libresoc.v:47477$2799
+ attribute \src "libresoc.v:47422.3-47430.6"
+ process $proc$libresoc.v:47422$2802
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801
- attribute \src "libresoc.v:47478.5-47478.29"
+ assign $0\wr_pick_dly$1545$next[0:0]$2803 $1\wr_pick_dly$1545$next[0:0]$2804
+ attribute \src "libresoc.v:47423.5-47423.29"
switch \initial
- attribute \src "libresoc.v:47478.9-47478.17"
+ attribute \src "libresoc.v:47423.9-47423.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1511$next[0:0]$2801 1'0
+ assign $1\wr_pick_dly$1545$next[0:0]$2804 1'0
case
- assign $1\wr_pick_dly$1511$next[0:0]$2801 \wr_pick$1508
+ assign $1\wr_pick_dly$1545$next[0:0]$2804 \wr_pick$1542
end
sync always
- update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800
+ update \wr_pick_dly$1545$next $0\wr_pick_dly$1545$next[0:0]$2803
end
- attribute \src "libresoc.v:47486.3-47514.6"
- process $proc$libresoc.v:47486$2802
+ attribute \src "libresoc.v:47431.3-47439.6"
+ process $proc$libresoc.v:47431$2805
+ assign { } { }
+ assign { } { }
+ assign $0\wr_pick_dly$1561$next[0:0]$2806 $1\wr_pick_dly$1561$next[0:0]$2807
+ attribute \src "libresoc.v:47432.5-47432.29"
+ switch \initial
+ attribute \src "libresoc.v:47432.9-47432.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\wr_pick_dly$1561$next[0:0]$2807 1'0
+ case
+ assign $1\wr_pick_dly$1561$next[0:0]$2807 \wr_pick$1558
+ end
+ sync always
+ update \wr_pick_dly$1561$next $0\wr_pick_dly$1561$next[0:0]$2806
+ end
+ attribute \src "libresoc.v:47440.3-47468.6"
+ process $proc$libresoc.v:47440$2808
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "libresoc.v:47487.5-47487.29"
+ attribute \src "libresoc.v:47441.5-47441.29"
switch \initial
- attribute \src "libresoc.v:47487.9-47487.17"
+ attribute \src "libresoc.v:47441.9-47441.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0]
end
- attribute \src "libresoc.v:47515.3-47523.6"
- process $proc$libresoc.v:47515$2803
+ attribute \src "libresoc.v:47469.3-47477.6"
+ process $proc$libresoc.v:47469$2809
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805
- attribute \src "libresoc.v:47516.5-47516.29"
+ assign $0\wr_pick_dly$1577$next[0:0]$2810 $1\wr_pick_dly$1577$next[0:0]$2811
+ attribute \src "libresoc.v:47470.5-47470.29"
switch \initial
- attribute \src "libresoc.v:47516.9-47516.17"
+ attribute \src "libresoc.v:47470.9-47470.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1547$next[0:0]$2805 1'0
+ assign $1\wr_pick_dly$1577$next[0:0]$2811 1'0
case
- assign $1\wr_pick_dly$1547$next[0:0]$2805 \wr_pick$1544
+ assign $1\wr_pick_dly$1577$next[0:0]$2811 \wr_pick$1574
end
sync always
- update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804
+ update \wr_pick_dly$1577$next $0\wr_pick_dly$1577$next[0:0]$2810
end
- attribute \src "libresoc.v:47524.3-47532.6"
- process $proc$libresoc.v:47524$2806
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808
- attribute \src "libresoc.v:47525.5-47525.29"
- switch \initial
- attribute \src "libresoc.v:47525.9-47525.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1563$next[0:0]$2808 1'0
- case
- assign $1\wr_pick_dly$1563$next[0:0]$2808 \wr_pick$1560
- end
- sync always
- update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807
- end
- attribute \src "libresoc.v:47533.3-47561.6"
- process $proc$libresoc.v:47533$2809
+ attribute \src "libresoc.v:47478.3-47506.6"
+ process $proc$libresoc.v:47478$2812
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "libresoc.v:47534.5-47534.29"
+ attribute \src "libresoc.v:47479.5-47479.29"
switch \initial
- attribute \src "libresoc.v:47534.9-47534.17"
+ attribute \src "libresoc.v:47479.9-47479.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0]
end
- attribute \src "libresoc.v:47562.3-47570.6"
- process $proc$libresoc.v:47562$2810
+ attribute \src "libresoc.v:47507.3-47515.6"
+ process $proc$libresoc.v:47507$2813
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812
- attribute \src "libresoc.v:47563.5-47563.29"
+ assign $0\wr_pick_dly$1593$next[0:0]$2814 $1\wr_pick_dly$1593$next[0:0]$2815
+ attribute \src "libresoc.v:47508.5-47508.29"
switch \initial
- attribute \src "libresoc.v:47563.9-47563.17"
+ attribute \src "libresoc.v:47508.9-47508.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1579$next[0:0]$2812 1'0
+ assign $1\wr_pick_dly$1593$next[0:0]$2815 1'0
case
- assign $1\wr_pick_dly$1579$next[0:0]$2812 \wr_pick$1576
+ assign $1\wr_pick_dly$1593$next[0:0]$2815 \wr_pick$1590
end
sync always
- update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811
+ update \wr_pick_dly$1593$next $0\wr_pick_dly$1593$next[0:0]$2814
end
- attribute \src "libresoc.v:47571.3-47579.6"
- process $proc$libresoc.v:47571$2813
+ attribute \src "libresoc.v:47516.3-47524.6"
+ process $proc$libresoc.v:47516$2816
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815
- attribute \src "libresoc.v:47572.5-47572.29"
+ assign $0\wr_pick_dly$1635$next[0:0]$2817 $1\wr_pick_dly$1635$next[0:0]$2818
+ attribute \src "libresoc.v:47517.5-47517.29"
switch \initial
- attribute \src "libresoc.v:47572.9-47572.17"
+ attribute \src "libresoc.v:47517.9-47517.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1595$next[0:0]$2815 1'0
+ assign $1\wr_pick_dly$1635$next[0:0]$2818 1'0
case
- assign $1\wr_pick_dly$1595$next[0:0]$2815 \wr_pick$1592
+ assign $1\wr_pick_dly$1635$next[0:0]$2818 \wr_pick$1632
end
sync always
- update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814
+ update \wr_pick_dly$1635$next $0\wr_pick_dly$1635$next[0:0]$2817
end
- attribute \src "libresoc.v:47580.3-47608.6"
- process $proc$libresoc.v:47580$2816
+ attribute \src "libresoc.v:47525.3-47553.6"
+ process $proc$libresoc.v:47525$2819
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "libresoc.v:47581.5-47581.29"
+ attribute \src "libresoc.v:47526.5-47526.29"
switch \initial
- attribute \src "libresoc.v:47581.9-47581.17"
+ attribute \src "libresoc.v:47526.9-47526.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0]
end
- attribute \src "libresoc.v:47609.3-47617.6"
- process $proc$libresoc.v:47609$2817
+ attribute \src "libresoc.v:47554.3-47562.6"
+ process $proc$libresoc.v:47554$2820
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819
- attribute \src "libresoc.v:47610.5-47610.29"
+ assign $0\wr_pick_dly$1654$next[0:0]$2821 $1\wr_pick_dly$1654$next[0:0]$2822
+ attribute \src "libresoc.v:47555.5-47555.29"
switch \initial
- attribute \src "libresoc.v:47610.9-47610.17"
+ attribute \src "libresoc.v:47555.9-47555.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1637$next[0:0]$2819 1'0
+ assign $1\wr_pick_dly$1654$next[0:0]$2822 1'0
case
- assign $1\wr_pick_dly$1637$next[0:0]$2819 \wr_pick$1634
+ assign $1\wr_pick_dly$1654$next[0:0]$2822 \wr_pick$1651
end
sync always
- update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818
+ update \wr_pick_dly$1654$next $0\wr_pick_dly$1654$next[0:0]$2821
end
- attribute \src "libresoc.v:47618.3-47646.6"
- process $proc$libresoc.v:47618$2820
+ attribute \src "libresoc.v:47563.3-47591.6"
+ process $proc$libresoc.v:47563$2823
assign { } { }
assign { } { }
- assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822
- attribute \src "libresoc.v:47619.5-47619.29"
+ assign $0\fus_cu_issue_i$13[0:0]$2824 $1\fus_cu_issue_i$13[0:0]$2825
+ attribute \src "libresoc.v:47564.5-47564.29"
switch \initial
- attribute \src "libresoc.v:47619.9-47619.17"
+ attribute \src "libresoc.v:47564.9-47564.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_cu_issue_i$13[0:0]$2822 $2\fus_cu_issue_i$13[0:0]$2823
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ assign $1\fus_cu_issue_i$13[0:0]$2825 $2\fus_cu_issue_i$13[0:0]$2826
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
- assign $2\fus_cu_issue_i$13[0:0]$2823 1'0
+ assign $2\fus_cu_issue_i$13[0:0]$2826 1'0
attribute \src "libresoc.v:0.0-0.0"
case 7'0000001
- assign $2\fus_cu_issue_i$13[0:0]$2823 1'0
+ assign $2\fus_cu_issue_i$13[0:0]$2826 1'0
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\fus_cu_issue_i$13[0:0]$2823 $3\fus_cu_issue_i$13[0:0]$2824
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ assign $2\fus_cu_issue_i$13[0:0]$2826 $3\fus_cu_issue_i$13[0:0]$2827
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fus_cu_issue_i$13[0:0]$2824 \issue_i
+ assign $3\fus_cu_issue_i$13[0:0]$2827 \issue_i
case
- assign $3\fus_cu_issue_i$13[0:0]$2824 1'0
+ assign $3\fus_cu_issue_i$13[0:0]$2827 1'0
end
end
case
- assign $1\fus_cu_issue_i$13[0:0]$2822 1'0
+ assign $1\fus_cu_issue_i$13[0:0]$2825 1'0
end
sync always
- update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821
+ update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2824
end
- attribute \src "libresoc.v:47647.3-47655.6"
- process $proc$libresoc.v:47647$2825
+ attribute \src "libresoc.v:47592.3-47600.6"
+ process $proc$libresoc.v:47592$2828
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827
- attribute \src "libresoc.v:47648.5-47648.29"
+ assign $0\wr_pick_dly$1670$next[0:0]$2829 $1\wr_pick_dly$1670$next[0:0]$2830
+ attribute \src "libresoc.v:47593.5-47593.29"
switch \initial
- attribute \src "libresoc.v:47648.9-47648.17"
+ attribute \src "libresoc.v:47593.9-47593.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1656$next[0:0]$2827 1'0
+ assign $1\wr_pick_dly$1670$next[0:0]$2830 1'0
case
- assign $1\wr_pick_dly$1656$next[0:0]$2827 \wr_pick$1653
+ assign $1\wr_pick_dly$1670$next[0:0]$2830 \wr_pick$1667
end
sync always
- update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826
+ update \wr_pick_dly$1670$next $0\wr_pick_dly$1670$next[0:0]$2829
end
- attribute \src "libresoc.v:47656.3-47684.6"
- process $proc$libresoc.v:47656$2828
+ attribute \src "libresoc.v:47601.3-47609.6"
+ process $proc$libresoc.v:47601$2831
assign { } { }
assign { } { }
- assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830
- attribute \src "libresoc.v:47657.5-47657.29"
+ assign $0\wr_pick_dly$1686$next[0:0]$2832 $1\wr_pick_dly$1686$next[0:0]$2833
+ attribute \src "libresoc.v:47602.5-47602.29"
switch \initial
- attribute \src "libresoc.v:47657.9-47657.17"
+ attribute \src "libresoc.v:47602.9-47602.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\wr_pick_dly$1686$next[0:0]$2833 1'0
+ case
+ assign $1\wr_pick_dly$1686$next[0:0]$2833 \wr_pick$1683
+ end
+ sync always
+ update \wr_pick_dly$1686$next $0\wr_pick_dly$1686$next[0:0]$2832
+ end
+ attribute \src "libresoc.v:47610.3-47638.6"
+ process $proc$libresoc.v:47610$2834
+ assign { } { }
+ assign { } { }
+ assign $0\fus_cu_rdmaskn_i$15[5:0]$2835 $1\fus_cu_rdmaskn_i$15[5:0]$2836
+ attribute \src "libresoc.v:47611.5-47611.29"
+ switch \initial
+ attribute \src "libresoc.v:47611.9-47611.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 $2\fus_cu_rdmaskn_i$15[5:0]$2831
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 $2\fus_cu_rdmaskn_i$15[5:0]$2837
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
- assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000
+ assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000
attribute \src "libresoc.v:0.0-0.0"
case 7'0000001
- assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000
+ assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 $3\fus_cu_rdmaskn_i$15[5:0]$2832
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 $3\fus_cu_rdmaskn_i$15[5:0]$2838
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 \$250
+ assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 \$250
case
- assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 6'000000
+ assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 6'000000
end
end
case
- assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 6'000000
- end
- sync always
- update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829
- end
- attribute \src "libresoc.v:47685.3-47693.6"
- process $proc$libresoc.v:47685$2833
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835
- attribute \src "libresoc.v:47686.5-47686.29"
- switch \initial
- attribute \src "libresoc.v:47686.9-47686.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1672$next[0:0]$2835 1'0
- case
- assign $1\wr_pick_dly$1672$next[0:0]$2835 \wr_pick$1669
+ assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 6'000000
end
sync always
- update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834
+ update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2835
end
- attribute \src "libresoc.v:47694.3-47702.6"
- process $proc$libresoc.v:47694$2836
+ attribute \src "libresoc.v:47639.3-47647.6"
+ process $proc$libresoc.v:47639$2839
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838
- attribute \src "libresoc.v:47695.5-47695.29"
+ assign $0\wr_pick_dly$1702$next[0:0]$2840 $1\wr_pick_dly$1702$next[0:0]$2841
+ attribute \src "libresoc.v:47640.5-47640.29"
switch \initial
- attribute \src "libresoc.v:47695.9-47695.17"
+ attribute \src "libresoc.v:47640.9-47640.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1688$next[0:0]$2838 1'0
+ assign $1\wr_pick_dly$1702$next[0:0]$2841 1'0
case
- assign $1\wr_pick_dly$1688$next[0:0]$2838 \wr_pick$1685
+ assign $1\wr_pick_dly$1702$next[0:0]$2841 \wr_pick$1699
end
sync always
- update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837
+ update \wr_pick_dly$1702$next $0\wr_pick_dly$1702$next[0:0]$2840
end
- attribute \src "libresoc.v:47703.3-47731.6"
- process $proc$libresoc.v:47703$2839
+ attribute \src "libresoc.v:47648.3-47676.6"
+ process $proc$libresoc.v:47648$2842
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "libresoc.v:47704.5-47704.29"
+ attribute \src "libresoc.v:47649.5-47649.29"
switch \initial
- attribute \src "libresoc.v:47704.9-47704.17"
+ attribute \src "libresoc.v:47649.9-47649.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0]
end
- attribute \src "libresoc.v:47732.3-47740.6"
- process $proc$libresoc.v:47732$2840
+ attribute \src "libresoc.v:47677.3-47685.6"
+ process $proc$libresoc.v:47677$2843
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842
- attribute \src "libresoc.v:47733.5-47733.29"
+ assign $0\wr_pick_dly$1746$next[0:0]$2844 $1\wr_pick_dly$1746$next[0:0]$2845
+ attribute \src "libresoc.v:47678.5-47678.29"
switch \initial
- attribute \src "libresoc.v:47733.9-47733.17"
+ attribute \src "libresoc.v:47678.9-47678.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1704$next[0:0]$2842 1'0
+ assign $1\wr_pick_dly$1746$next[0:0]$2845 1'0
case
- assign $1\wr_pick_dly$1704$next[0:0]$2842 \wr_pick$1701
+ assign $1\wr_pick_dly$1746$next[0:0]$2845 \wr_pick$1743
end
sync always
- update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841
+ update \wr_pick_dly$1746$next $0\wr_pick_dly$1746$next[0:0]$2844
end
- attribute \src "libresoc.v:47741.3-47769.6"
- process $proc$libresoc.v:47741$2843
+ attribute \src "libresoc.v:47686.3-47714.6"
+ process $proc$libresoc.v:47686$2846
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "libresoc.v:47742.5-47742.29"
+ attribute \src "libresoc.v:47687.5-47687.29"
switch \initial
- attribute \src "libresoc.v:47742.9-47742.17"
+ attribute \src "libresoc.v:47687.9-47687.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0]
end
- attribute \src "libresoc.v:47770.3-47778.6"
- process $proc$libresoc.v:47770$2844
+ attribute \src "libresoc.v:47715.3-47723.6"
+ process $proc$libresoc.v:47715$2847
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846
- attribute \src "libresoc.v:47771.5-47771.29"
+ assign $0\wr_pick_dly$1762$next[0:0]$2848 $1\wr_pick_dly$1762$next[0:0]$2849
+ attribute \src "libresoc.v:47716.5-47716.29"
switch \initial
- attribute \src "libresoc.v:47771.9-47771.17"
+ attribute \src "libresoc.v:47716.9-47716.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1748$next[0:0]$2846 1'0
+ assign $1\wr_pick_dly$1762$next[0:0]$2849 1'0
case
- assign $1\wr_pick_dly$1748$next[0:0]$2846 \wr_pick$1745
+ assign $1\wr_pick_dly$1762$next[0:0]$2849 \wr_pick$1759
end
sync always
- update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845
+ update \wr_pick_dly$1762$next $0\wr_pick_dly$1762$next[0:0]$2848
end
- attribute \src "libresoc.v:47779.3-47787.6"
- process $proc$libresoc.v:47779$2847
+ attribute \src "libresoc.v:47724.3-47732.6"
+ process $proc$libresoc.v:47724$2850
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849
- attribute \src "libresoc.v:47780.5-47780.29"
+ assign $0\wr_pick_dly$1786$next[0:0]$2851 $1\wr_pick_dly$1786$next[0:0]$2852
+ attribute \src "libresoc.v:47725.5-47725.29"
switch \initial
- attribute \src "libresoc.v:47780.9-47780.17"
+ attribute \src "libresoc.v:47725.9-47725.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1764$next[0:0]$2849 1'0
+ assign $1\wr_pick_dly$1786$next[0:0]$2852 1'0
case
- assign $1\wr_pick_dly$1764$next[0:0]$2849 \wr_pick$1761
+ assign $1\wr_pick_dly$1786$next[0:0]$2852 \wr_pick$1783
end
sync always
- update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848
+ update \wr_pick_dly$1786$next $0\wr_pick_dly$1786$next[0:0]$2851
end
- attribute \src "libresoc.v:47788.3-47816.6"
- process $proc$libresoc.v:47788$2850
+ attribute \src "libresoc.v:47733.3-47761.6"
+ process $proc$libresoc.v:47733$2853
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "libresoc.v:47789.5-47789.29"
+ attribute \src "libresoc.v:47734.5-47734.29"
switch \initial
- attribute \src "libresoc.v:47789.9-47789.17"
+ attribute \src "libresoc.v:47734.9-47734.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0]
end
- attribute \src "libresoc.v:47817.3-47825.6"
- process $proc$libresoc.v:47817$2851
+ attribute \src "libresoc.v:47762.3-47770.6"
+ process $proc$libresoc.v:47762$2854
assign { } { }
assign { } { }
- assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853
- attribute \src "libresoc.v:47818.5-47818.29"
+ assign $0\wr_pick_dly$1806$next[0:0]$2855 $1\wr_pick_dly$1806$next[0:0]$2856
+ attribute \src "libresoc.v:47763.5-47763.29"
switch \initial
- attribute \src "libresoc.v:47818.9-47818.17"
+ attribute \src "libresoc.v:47763.9-47763.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wr_pick_dly$1788$next[0:0]$2853 1'0
+ assign $1\wr_pick_dly$1806$next[0:0]$2856 1'0
case
- assign $1\wr_pick_dly$1788$next[0:0]$2853 \wr_pick$1785
+ assign $1\wr_pick_dly$1806$next[0:0]$2856 \wr_pick$1803
end
sync always
- update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852
+ update \wr_pick_dly$1806$next $0\wr_pick_dly$1806$next[0:0]$2855
end
- attribute \src "libresoc.v:47826.3-47854.6"
- process $proc$libresoc.v:47826$2854
+ attribute \src "libresoc.v:47771.3-47799.6"
+ process $proc$libresoc.v:47771$2857
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "libresoc.v:47827.5-47827.29"
+ attribute \src "libresoc.v:47772.5-47772.29"
switch \initial
- attribute \src "libresoc.v:47827.9-47827.17"
+ attribute \src "libresoc.v:47772.9-47772.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0]
end
- attribute \src "libresoc.v:47855.3-47863.6"
- process $proc$libresoc.v:47855$2855
- assign { } { }
- assign { } { }
- assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857
- attribute \src "libresoc.v:47856.5-47856.29"
- switch \initial
- attribute \src "libresoc.v:47856.9-47856.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wr_pick_dly$1808$next[0:0]$2857 1'0
- case
- assign $1\wr_pick_dly$1808$next[0:0]$2857 \wr_pick$1805
- end
- sync always
- update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856
- end
- attribute \src "libresoc.v:47864.3-47893.6"
- process $proc$libresoc.v:47864$2858
+ attribute \src "libresoc.v:47800.3-47829.6"
+ process $proc$libresoc.v:47800$2858
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "libresoc.v:47865.5-47865.29"
+ attribute \src "libresoc.v:47801.5-47801.29"
switch \initial
- attribute \src "libresoc.v:47865.9-47865.17"
+ attribute \src "libresoc.v:47801.9-47801.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0]
update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:47894.3-47922.6"
- process $proc$libresoc.v:47894$2859
+ attribute \src "libresoc.v:47830.3-47858.6"
+ process $proc$libresoc.v:47830$2859
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "libresoc.v:47895.5-47895.29"
+ attribute \src "libresoc.v:47831.5-47831.29"
switch \initial
- attribute \src "libresoc.v:47895.9-47895.17"
+ attribute \src "libresoc.v:47831.9-47831.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0]
end
- attribute \src "libresoc.v:47923.3-47951.6"
- process $proc$libresoc.v:47923$2860
+ attribute \src "libresoc.v:47859.3-47887.6"
+ process $proc$libresoc.v:47859$2860
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "libresoc.v:47924.5-47924.29"
+ attribute \src "libresoc.v:47860.5-47860.29"
switch \initial
- attribute \src "libresoc.v:47924.9-47924.17"
+ attribute \src "libresoc.v:47860.9-47860.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0]
end
- attribute \src "libresoc.v:47952.3-47980.6"
- process $proc$libresoc.v:47952$2861
+ attribute \src "libresoc.v:47888.3-47916.6"
+ process $proc$libresoc.v:47888$2861
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863
- attribute \src "libresoc.v:47953.5-47953.29"
+ attribute \src "libresoc.v:47889.5-47889.29"
switch \initial
- attribute \src "libresoc.v:47953.9-47953.17"
+ attribute \src "libresoc.v:47889.9-47889.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862
end
- attribute \src "libresoc.v:47981.3-48009.6"
- process $proc$libresoc.v:47981$2866
+ attribute \src "libresoc.v:47917.3-47945.6"
+ process $proc$libresoc.v:47917$2866
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868
- attribute \src "libresoc.v:47982.5-47982.29"
+ attribute \src "libresoc.v:47918.5-47918.29"
switch \initial
- attribute \src "libresoc.v:47982.9-47982.17"
+ attribute \src "libresoc.v:47918.9-47918.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867
end
- attribute \src "libresoc.v:48010.3-48038.6"
- process $proc$libresoc.v:48010$2871
+ attribute \src "libresoc.v:47946.3-47974.6"
+ process $proc$libresoc.v:47946$2871
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "libresoc.v:48011.5-48011.29"
+ attribute \src "libresoc.v:47947.5-47947.29"
switch \initial
- attribute \src "libresoc.v:48011.9-48011.17"
+ attribute \src "libresoc.v:47947.9-47947.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0]
end
- attribute \src "libresoc.v:48039.3-48067.6"
- process $proc$libresoc.v:48039$2872
+ attribute \src "libresoc.v:47975.3-48003.6"
+ process $proc$libresoc.v:47975$2872
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "libresoc.v:48040.5-48040.29"
+ attribute \src "libresoc.v:47976.5-47976.29"
switch \initial
- attribute \src "libresoc.v:48040.9-48040.17"
+ attribute \src "libresoc.v:47976.9-47976.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0]
end
- attribute \src "libresoc.v:48068.3-48096.6"
- process $proc$libresoc.v:48068$2873
+ attribute \src "libresoc.v:48004.3-48032.6"
+ process $proc$libresoc.v:48004$2873
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "libresoc.v:48069.5-48069.29"
+ attribute \src "libresoc.v:48005.5-48005.29"
switch \initial
- attribute \src "libresoc.v:48069.9-48069.17"
+ attribute \src "libresoc.v:48005.9-48005.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0]
end
- attribute \src "libresoc.v:48097.3-48125.6"
- process $proc$libresoc.v:48097$2874
+ attribute \src "libresoc.v:48033.3-48061.6"
+ process $proc$libresoc.v:48033$2874
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "libresoc.v:48098.5-48098.29"
+ attribute \src "libresoc.v:48034.5-48034.29"
switch \initial
- attribute \src "libresoc.v:48098.9-48098.17"
+ attribute \src "libresoc.v:48034.9-48034.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0]
end
- attribute \src "libresoc.v:48126.3-48154.6"
- process $proc$libresoc.v:48126$2875
+ attribute \src "libresoc.v:48062.3-48090.6"
+ process $proc$libresoc.v:48062$2875
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "libresoc.v:48127.5-48127.29"
+ attribute \src "libresoc.v:48063.5-48063.29"
switch \initial
- attribute \src "libresoc.v:48127.9-48127.17"
+ attribute \src "libresoc.v:48063.9-48063.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0]
end
- attribute \src "libresoc.v:48155.3-48183.6"
- process $proc$libresoc.v:48155$2876
+ attribute \src "libresoc.v:48091.3-48119.6"
+ process $proc$libresoc.v:48091$2876
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "libresoc.v:48156.5-48156.29"
+ attribute \src "libresoc.v:48092.5-48092.29"
switch \initial
- attribute \src "libresoc.v:48156.9-48156.17"
+ attribute \src "libresoc.v:48092.9-48092.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0]
end
- attribute \src "libresoc.v:48184.3-48212.6"
- process $proc$libresoc.v:48184$2877
+ attribute \src "libresoc.v:48120.3-48148.6"
+ process $proc$libresoc.v:48120$2877
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "libresoc.v:48185.5-48185.29"
+ attribute \src "libresoc.v:48121.5-48121.29"
switch \initial
- attribute \src "libresoc.v:48185.9-48185.17"
+ attribute \src "libresoc.v:48121.9-48121.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0]
end
- attribute \src "libresoc.v:48213.3-48241.6"
- process $proc$libresoc.v:48213$2878
+ attribute \src "libresoc.v:48149.3-48177.6"
+ process $proc$libresoc.v:48149$2878
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "libresoc.v:48214.5-48214.29"
+ attribute \src "libresoc.v:48150.5-48150.29"
switch \initial
- attribute \src "libresoc.v:48214.9-48214.17"
+ attribute \src "libresoc.v:48150.9-48150.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0]
end
- attribute \src "libresoc.v:48242.3-48270.6"
- process $proc$libresoc.v:48242$2879
+ attribute \src "libresoc.v:48178.3-48206.6"
+ process $proc$libresoc.v:48178$2879
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "libresoc.v:48243.5-48243.29"
+ attribute \src "libresoc.v:48179.5-48179.29"
switch \initial
- attribute \src "libresoc.v:48243.9-48243.17"
+ attribute \src "libresoc.v:48179.9-48179.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0]
end
- attribute \src "libresoc.v:48271.3-48299.6"
- process $proc$libresoc.v:48271$2880
+ attribute \src "libresoc.v:48207.3-48235.6"
+ process $proc$libresoc.v:48207$2880
assign { } { }
assign { } { }
assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882
- attribute \src "libresoc.v:48272.5-48272.29"
+ attribute \src "libresoc.v:48208.5-48208.29"
switch \initial
- attribute \src "libresoc.v:48272.9-48272.17"
+ attribute \src "libresoc.v:48208.9-48208.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881
end
- attribute \src "libresoc.v:48300.3-48328.6"
- process $proc$libresoc.v:48300$2885
+ attribute \src "libresoc.v:48236.3-48264.6"
+ process $proc$libresoc.v:48236$2885
assign { } { }
assign { } { }
assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887
- attribute \src "libresoc.v:48301.5-48301.29"
+ attribute \src "libresoc.v:48237.5-48237.29"
switch \initial
- attribute \src "libresoc.v:48301.9-48301.17"
+ attribute \src "libresoc.v:48237.9-48237.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886
end
- attribute \src "libresoc.v:48329.3-48357.6"
- process $proc$libresoc.v:48329$2890
+ attribute \src "libresoc.v:48265.3-48293.6"
+ process $proc$libresoc.v:48265$2890
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "libresoc.v:48330.5-48330.29"
+ attribute \src "libresoc.v:48266.5-48266.29"
switch \initial
- attribute \src "libresoc.v:48330.9-48330.17"
+ attribute \src "libresoc.v:48266.9-48266.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0]
end
- attribute \src "libresoc.v:48358.3-48386.6"
- process $proc$libresoc.v:48358$2891
+ attribute \src "libresoc.v:48294.3-48322.6"
+ process $proc$libresoc.v:48294$2891
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "libresoc.v:48359.5-48359.29"
+ attribute \src "libresoc.v:48295.5-48295.29"
switch \initial
- attribute \src "libresoc.v:48359.9-48359.17"
+ attribute \src "libresoc.v:48295.9-48295.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0]
end
- attribute \src "libresoc.v:48387.3-48416.6"
- process $proc$libresoc.v:48387$2892
+ attribute \src "libresoc.v:48323.3-48352.6"
+ process $proc$libresoc.v:48323$2892
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0]
assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "libresoc.v:48388.5-48388.29"
+ attribute \src "libresoc.v:48324.5-48324.29"
switch \initial
- attribute \src "libresoc.v:48388.9-48388.17"
+ attribute \src "libresoc.v:48324.9-48324.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0]
assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0]
assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0]
update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:48417.3-48446.6"
- process $proc$libresoc.v:48417$2893
+ attribute \src "libresoc.v:48353.3-48382.6"
+ process $proc$libresoc.v:48353$2893
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0]
assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "libresoc.v:48418.5-48418.29"
+ attribute \src "libresoc.v:48354.5-48354.29"
switch \initial
- attribute \src "libresoc.v:48418.9-48418.17"
+ attribute \src "libresoc.v:48354.9-48354.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0]
assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0]
assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0]
update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0]
end
- attribute \src "libresoc.v:48447.3-48476.6"
- process $proc$libresoc.v:48447$2894
+ attribute \src "libresoc.v:48383.3-48412.6"
+ process $proc$libresoc.v:48383$2894
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0]
assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "libresoc.v:48448.5-48448.29"
+ attribute \src "libresoc.v:48384.5-48384.29"
switch \initial
- attribute \src "libresoc.v:48448.9-48448.17"
+ attribute \src "libresoc.v:48384.9-48384.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0]
assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
assign { } { }
assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0]
assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0]
update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0]
end
- attribute \src "libresoc.v:48477.3-48505.6"
- process $proc$libresoc.v:48477$2895
+ attribute \src "libresoc.v:48413.3-48441.6"
+ process $proc$libresoc.v:48413$2895
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "libresoc.v:48478.5-48478.29"
+ attribute \src "libresoc.v:48414.5-48414.29"
switch \initial
- attribute \src "libresoc.v:48478.9-48478.17"
+ attribute \src "libresoc.v:48414.9-48414.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0]
end
- attribute \src "libresoc.v:48506.3-48534.6"
- process $proc$libresoc.v:48506$2896
+ attribute \src "libresoc.v:48442.3-48470.6"
+ process $proc$libresoc.v:48442$2896
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "libresoc.v:48507.5-48507.29"
+ attribute \src "libresoc.v:48443.5-48443.29"
switch \initial
- attribute \src "libresoc.v:48507.9-48507.17"
+ attribute \src "libresoc.v:48443.9-48443.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0]
end
- attribute \src "libresoc.v:48535.3-48563.6"
- process $proc$libresoc.v:48535$2897
+ attribute \src "libresoc.v:48471.3-48499.6"
+ process $proc$libresoc.v:48471$2897
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "libresoc.v:48536.5-48536.29"
+ attribute \src "libresoc.v:48472.5-48472.29"
switch \initial
- attribute \src "libresoc.v:48536.9-48536.17"
+ attribute \src "libresoc.v:48472.9-48472.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0]
end
- attribute \src "libresoc.v:48564.3-48592.6"
- process $proc$libresoc.v:48564$2898
+ attribute \src "libresoc.v:48500.3-48528.6"
+ process $proc$libresoc.v:48500$2898
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "libresoc.v:48565.5-48565.29"
+ attribute \src "libresoc.v:48501.5-48501.29"
switch \initial
- attribute \src "libresoc.v:48565.9-48565.17"
+ attribute \src "libresoc.v:48501.9-48501.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0]
end
- attribute \src "libresoc.v:48593.3-48621.6"
- process $proc$libresoc.v:48593$2899
+ attribute \src "libresoc.v:48529.3-48557.6"
+ process $proc$libresoc.v:48529$2899
assign { } { }
assign { } { }
assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "libresoc.v:48594.5-48594.29"
+ attribute \src "libresoc.v:48530.5-48530.29"
switch \initial
- attribute \src "libresoc.v:48594.9-48594.17"
+ attribute \src "libresoc.v:48530.9-48530.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197"
switch \ivalid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198"
switch \core_core_insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101
case
assign { } { }
assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215"
switch \fu_enable [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0]
end
- connect \$1000 $and$libresoc.v:42151$1506_Y
- connect \$1003 $ternary$libresoc.v:42152$1507_Y
- connect \$1005 $and$libresoc.v:42153$1508_Y
- connect \$1008 $and$libresoc.v:42154$1509_Y
- connect \$1012 $not$libresoc.v:42155$1510_Y
- connect \$1014 $and$libresoc.v:42156$1511_Y
- connect \$1021 $and$libresoc.v:42157$1512_Y
- connect \$1024 $ternary$libresoc.v:42158$1513_Y
- connect \$1026 $and$libresoc.v:42159$1514_Y
- connect \$1029 $and$libresoc.v:42160$1515_Y
- connect \$1033 $not$libresoc.v:42161$1516_Y
- connect \$1035 $and$libresoc.v:42162$1517_Y
- connect \$1039 $and$libresoc.v:42163$1518_Y
- connect \$1042 $ternary$libresoc.v:42164$1519_Y
- connect \$1044 $and$libresoc.v:42165$1520_Y
- connect \$1047 $and$libresoc.v:42166$1521_Y
- connect \$1051 $not$libresoc.v:42167$1522_Y
- connect \$1053 $and$libresoc.v:42168$1523_Y
- connect \$1061 $and$libresoc.v:42169$1524_Y
- connect \$1064 $ternary$libresoc.v:42170$1525_Y
- connect \$1066 $and$libresoc.v:42171$1526_Y
- connect \$1069 $and$libresoc.v:42172$1527_Y
- connect \$1073 $not$libresoc.v:42173$1528_Y
- connect \$1075 $and$libresoc.v:42174$1529_Y
- connect \$1081 $and$libresoc.v:42175$1530_Y
- connect \$1084 $ternary$libresoc.v:42176$1531_Y
- connect \$1086 $and$libresoc.v:42177$1532_Y
- connect \$1089 $and$libresoc.v:42178$1533_Y
- connect \$1093 $not$libresoc.v:42179$1534_Y
- connect \$1095 $and$libresoc.v:42180$1535_Y
- connect \$1101 $and$libresoc.v:42181$1536_Y
- connect \$1104 $ternary$libresoc.v:42182$1537_Y
- connect \$1106 $and$libresoc.v:42183$1538_Y
- connect \$1109 $and$libresoc.v:42184$1539_Y
- connect \$1113 $not$libresoc.v:42185$1540_Y
- connect \$1115 $and$libresoc.v:42186$1541_Y
- connect \$1120 $and$libresoc.v:42187$1542_Y
- connect \$1123 $ternary$libresoc.v:42188$1543_Y
- connect \$1125 $and$libresoc.v:42189$1544_Y
- connect \$1128 $and$libresoc.v:42190$1545_Y
- connect \$1132 $not$libresoc.v:42191$1546_Y
- connect \$1134 $and$libresoc.v:42192$1547_Y
- connect \$1138 $and$libresoc.v:42193$1548_Y
- connect \$1141 $ternary$libresoc.v:42194$1549_Y
- connect \$1143 $and$libresoc.v:42195$1550_Y
- connect \$1146 $and$libresoc.v:42196$1551_Y
- connect \$1149 $not$libresoc.v:42197$1552_Y
- connect \$1151 $and$libresoc.v:42198$1553_Y
- connect \$1154 $and$libresoc.v:42199$1554_Y
- connect \$1157 $ternary$libresoc.v:42200$1555_Y
- connect \$1160 $or$libresoc.v:42201$1556_Y
- connect \$1162 $or$libresoc.v:42202$1557_Y
- connect \$1164 $or$libresoc.v:42203$1558_Y
- connect \$1166 $or$libresoc.v:42204$1559_Y
- connect \$1168 $or$libresoc.v:42205$1560_Y
- connect \$1170 $or$libresoc.v:42206$1561_Y
- connect \$1172 $or$libresoc.v:42207$1562_Y
- connect \$1174 $or$libresoc.v:42208$1563_Y
- connect \$1176 $or$libresoc.v:42209$1564_Y
- connect \$1179 $or$libresoc.v:42210$1565_Y
- connect \$1181 $or$libresoc.v:42211$1566_Y
- connect \$1183 $or$libresoc.v:42212$1567_Y
- connect \$1185 $or$libresoc.v:42213$1568_Y
- connect \$1187 $or$libresoc.v:42214$1569_Y
- connect \$1189 $or$libresoc.v:42215$1570_Y
- connect \$1191 $or$libresoc.v:42216$1571_Y
- connect \$1193 $or$libresoc.v:42217$1572_Y
- connect \$1195 $or$libresoc.v:42218$1573_Y
- connect \$1197 $or$libresoc.v:42219$1574_Y
- connect \$1199 $or$libresoc.v:42220$1575_Y
- connect \$1201 $or$libresoc.v:42221$1576_Y
- connect \$1203 $or$libresoc.v:42222$1577_Y
- connect \$1205 $or$libresoc.v:42223$1578_Y
- connect \$1207 $or$libresoc.v:42224$1579_Y
- connect \$1209 $or$libresoc.v:42225$1580_Y
- connect \$1211 $or$libresoc.v:42226$1581_Y
- connect \$1213 $or$libresoc.v:42227$1582_Y
- connect \$1215 $and$libresoc.v:42228$1583_Y
- connect \$1217 $and$libresoc.v:42229$1584_Y
- connect \$1220 $and$libresoc.v:42230$1585_Y
- connect \$1223 $not$libresoc.v:42231$1586_Y
- connect \$1225 $and$libresoc.v:42232$1587_Y
- connect \$1228 $and$libresoc.v:42233$1588_Y
- connect \$1231 $ternary$libresoc.v:42234$1589_Y
- connect \$1233 $and$libresoc.v:42235$1590_Y
- connect \$1235 $and$libresoc.v:42236$1591_Y
- connect \$1237 $and$libresoc.v:42237$1592_Y
- connect \$1239 $and$libresoc.v:42238$1593_Y
- connect \$1241 $and$libresoc.v:42239$1594_Y
- connect \$1243 $and$libresoc.v:42240$1595_Y
- connect \$1245 $and$libresoc.v:42241$1596_Y
- connect \$1248 $and$libresoc.v:42242$1597_Y
- connect \$1251 $not$libresoc.v:42243$1598_Y
- connect \$1253 $and$libresoc.v:42244$1599_Y
- connect \$1256 $and$libresoc.v:42245$1600_Y
- connect \$1259 $sub$libresoc.v:42246$1601_Y
- connect \$1261 $sshl$libresoc.v:42247$1602_Y
- connect \$1263 $ternary$libresoc.v:42248$1603_Y
- connect \$1265 $and$libresoc.v:42249$1604_Y
- connect \$1268 $and$libresoc.v:42250$1605_Y
- connect \$1271 $not$libresoc.v:42251$1606_Y
- connect \$1273 $and$libresoc.v:42252$1607_Y
- connect \$1276 $and$libresoc.v:42253$1608_Y
- connect \$1279 $sub$libresoc.v:42254$1609_Y
- connect \$1281 $sshl$libresoc.v:42255$1610_Y
- connect \$1283 $ternary$libresoc.v:42256$1611_Y
- connect \$1285 $and$libresoc.v:42257$1612_Y
- connect \$1288 $and$libresoc.v:42258$1613_Y
- connect \$1291 $not$libresoc.v:42259$1614_Y
- connect \$1293 $and$libresoc.v:42260$1615_Y
- connect \$1296 $and$libresoc.v:42261$1616_Y
- connect \$1299 $sub$libresoc.v:42262$1617_Y
- connect \$1301 $sshl$libresoc.v:42263$1618_Y
- connect \$1303 $ternary$libresoc.v:42264$1619_Y
- connect \$1305 $and$libresoc.v:42265$1620_Y
- connect \$1308 $and$libresoc.v:42266$1621_Y
- connect \$1311 $not$libresoc.v:42267$1622_Y
- connect \$1313 $and$libresoc.v:42268$1623_Y
- connect \$1316 $and$libresoc.v:42269$1624_Y
- connect \$1319 $sub$libresoc.v:42270$1625_Y
- connect \$1321 $sshl$libresoc.v:42271$1626_Y
- connect \$1323 $ternary$libresoc.v:42272$1627_Y
- connect \$1325 $and$libresoc.v:42273$1628_Y
- connect \$1328 $and$libresoc.v:42274$1629_Y
- connect \$1331 $not$libresoc.v:42275$1630_Y
- connect \$1333 $and$libresoc.v:42276$1631_Y
- connect \$1336 $and$libresoc.v:42277$1632_Y
- connect \$1339 $sub$libresoc.v:42278$1633_Y
- connect \$1341 $sshl$libresoc.v:42279$1634_Y
- connect \$1343 $ternary$libresoc.v:42280$1635_Y
- connect \$1345 $and$libresoc.v:42281$1636_Y
- connect \$1348 $and$libresoc.v:42282$1637_Y
- connect \$1351 $not$libresoc.v:42283$1638_Y
- connect \$1353 $and$libresoc.v:42284$1639_Y
- connect \$1356 $and$libresoc.v:42285$1640_Y
- connect \$1359 $sub$libresoc.v:42286$1641_Y
- connect \$1361 $sshl$libresoc.v:42287$1642_Y
- connect \$1363 $ternary$libresoc.v:42288$1643_Y
- connect \$1365 $or$libresoc.v:42289$1644_Y
- connect \$1367 $or$libresoc.v:42290$1645_Y
- connect \$1369 $or$libresoc.v:42291$1646_Y
- connect \$1371 $or$libresoc.v:42292$1647_Y
- connect \$1373 $or$libresoc.v:42293$1648_Y
- connect \$1376 $or$libresoc.v:42294$1649_Y
- connect \$1378 $or$libresoc.v:42295$1650_Y
- connect \$1380 $or$libresoc.v:42296$1651_Y
- connect \$1382 $or$libresoc.v:42297$1652_Y
- connect \$1384 $or$libresoc.v:42298$1653_Y
- connect \$1386 $and$libresoc.v:42299$1654_Y
- connect \$1388 $and$libresoc.v:42300$1655_Y
- connect \$1390 $and$libresoc.v:42301$1656_Y
- connect \$1392 $and$libresoc.v:42302$1657_Y
- connect \$1395 $and$libresoc.v:42303$1658_Y
- connect \$1398 $not$libresoc.v:42304$1659_Y
- connect \$1400 $and$libresoc.v:42305$1660_Y
- connect \$1403 $and$libresoc.v:42306$1661_Y
- connect \$1406 $ternary$libresoc.v:42307$1662_Y
- connect \$1408 $and$libresoc.v:42308$1663_Y
- connect \$1411 $and$libresoc.v:42309$1664_Y
- connect \$1414 $not$libresoc.v:42310$1665_Y
- connect \$1416 $and$libresoc.v:42311$1666_Y
- connect \$1419 $and$libresoc.v:42312$1667_Y
- connect \$1422 $ternary$libresoc.v:42313$1668_Y
- connect \$1424 $and$libresoc.v:42314$1669_Y
- connect \$1427 $and$libresoc.v:42315$1670_Y
- connect \$1430 $not$libresoc.v:42316$1671_Y
- connect \$1432 $and$libresoc.v:42317$1672_Y
- connect \$1435 $and$libresoc.v:42318$1673_Y
- connect \$1438 $ternary$libresoc.v:42319$1674_Y
- connect \$1440 $or$libresoc.v:42320$1675_Y
- connect \$1442 $or$libresoc.v:42321$1676_Y
- connect \$1445 $or$libresoc.v:42322$1677_Y
- connect \$1447 $or$libresoc.v:42323$1678_Y
- connect \$1444 $pos$libresoc.v:42324$1680_Y
- connect \$1450 $and$libresoc.v:42325$1681_Y
- connect \$1452 $and$libresoc.v:42326$1682_Y
- connect \$1454 $and$libresoc.v:42327$1683_Y
- connect \$1456 $and$libresoc.v:42328$1684_Y
- connect \$1458 $and$libresoc.v:42329$1685_Y
- connect \$1461 $and$libresoc.v:42330$1686_Y
- connect \$1464 $not$libresoc.v:42331$1687_Y
- connect \$1466 $and$libresoc.v:42332$1688_Y
- connect \$1469 $and$libresoc.v:42333$1689_Y
- connect \$1472 $ternary$libresoc.v:42334$1690_Y
- connect \$1474 $and$libresoc.v:42335$1691_Y
- connect \$1477 $and$libresoc.v:42336$1692_Y
- connect \$1480 $not$libresoc.v:42337$1693_Y
- connect \$1482 $and$libresoc.v:42338$1694_Y
- connect \$1485 $and$libresoc.v:42339$1695_Y
- connect \$1488 $ternary$libresoc.v:42340$1696_Y
- connect \$1490 $and$libresoc.v:42341$1697_Y
- connect \$1493 $and$libresoc.v:42342$1698_Y
- connect \$1496 $not$libresoc.v:42343$1699_Y
- connect \$1498 $and$libresoc.v:42344$1700_Y
- connect \$1501 $and$libresoc.v:42345$1701_Y
- connect \$1504 $ternary$libresoc.v:42346$1702_Y
- connect \$1506 $and$libresoc.v:42347$1703_Y
- connect \$1509 $and$libresoc.v:42348$1704_Y
- connect \$1512 $not$libresoc.v:42349$1705_Y
- connect \$1514 $and$libresoc.v:42350$1706_Y
- connect \$1517 $and$libresoc.v:42351$1707_Y
- connect \$1520 $ternary$libresoc.v:42352$1708_Y
- connect \$1522 $or$libresoc.v:42353$1709_Y
- connect \$1524 $or$libresoc.v:42354$1710_Y
- connect \$1526 $or$libresoc.v:42355$1711_Y
- connect \$1528 $or$libresoc.v:42356$1712_Y
- connect \$1530 $or$libresoc.v:42357$1713_Y
- connect \$1532 $or$libresoc.v:42358$1714_Y
- connect \$1534 $and$libresoc.v:42359$1715_Y
- connect \$1536 $and$libresoc.v:42360$1716_Y
- connect \$1538 $and$libresoc.v:42361$1717_Y
- connect \$1540 $and$libresoc.v:42362$1718_Y
- connect \$1542 $and$libresoc.v:42363$1719_Y
- connect \$1545 $and$libresoc.v:42364$1720_Y
- connect \$1548 $not$libresoc.v:42365$1721_Y
- connect \$1550 $and$libresoc.v:42366$1722_Y
- connect \$1553 $and$libresoc.v:42367$1723_Y
- connect \$1556 $ternary$libresoc.v:42368$1724_Y
- connect \$1558 $and$libresoc.v:42369$1725_Y
- connect \$1561 $and$libresoc.v:42370$1726_Y
- connect \$1564 $not$libresoc.v:42371$1727_Y
- connect \$1566 $and$libresoc.v:42372$1728_Y
- connect \$1569 $and$libresoc.v:42373$1729_Y
- connect \$1572 $ternary$libresoc.v:42374$1730_Y
- connect \$1574 $and$libresoc.v:42375$1731_Y
- connect \$1577 $and$libresoc.v:42376$1732_Y
- connect \$1580 $not$libresoc.v:42377$1733_Y
- connect \$1582 $and$libresoc.v:42378$1734_Y
- connect \$1585 $and$libresoc.v:42379$1735_Y
- connect \$1588 $ternary$libresoc.v:42380$1736_Y
- connect \$1590 $and$libresoc.v:42381$1737_Y
- connect \$1593 $and$libresoc.v:42382$1738_Y
- connect \$1596 $not$libresoc.v:42383$1739_Y
- connect \$1598 $and$libresoc.v:42384$1740_Y
- connect \$1601 $and$libresoc.v:42385$1741_Y
- connect \$1604 $ternary$libresoc.v:42386$1742_Y
- connect \$1607 $or$libresoc.v:42387$1743_Y
- connect \$1609 $or$libresoc.v:42388$1744_Y
- connect \$1611 $or$libresoc.v:42389$1745_Y
- connect \$1606 $pos$libresoc.v:42390$1747_Y
- connect \$1615 $or$libresoc.v:42391$1748_Y
- connect \$1617 $or$libresoc.v:42392$1749_Y
- connect \$1619 $or$libresoc.v:42393$1750_Y
- connect \$1614 $pos$libresoc.v:42394$1752_Y
- connect \$1622 $and$libresoc.v:42395$1753_Y
- connect \$1624 $and$libresoc.v:42396$1754_Y
- connect \$1626 $and$libresoc.v:42397$1755_Y
- connect \$1628 $and$libresoc.v:42398$1756_Y
- connect \$1630 $and$libresoc.v:42399$1757_Y
- connect \$1632 $and$libresoc.v:42400$1758_Y
- connect \$1635 $and$libresoc.v:42401$1759_Y
- connect \$1639 $not$libresoc.v:42402$1760_Y
- connect \$1641 $and$libresoc.v:42403$1761_Y
- connect \$1646 $and$libresoc.v:42404$1762_Y
- connect \$1649 $ternary$libresoc.v:42405$1763_Y
- connect \$1651 $and$libresoc.v:42406$1764_Y
- connect \$1654 $and$libresoc.v:42407$1765_Y
- connect \$1657 $not$libresoc.v:42408$1766_Y
- connect \$1659 $and$libresoc.v:42409$1767_Y
- connect \$1662 $and$libresoc.v:42410$1768_Y
- connect \$1665 $ternary$libresoc.v:42411$1769_Y
- connect \$1667 $and$libresoc.v:42412$1770_Y
- connect \$1670 $and$libresoc.v:42413$1771_Y
- connect \$1673 $not$libresoc.v:42414$1772_Y
- connect \$1675 $and$libresoc.v:42415$1773_Y
- connect \$1678 $and$libresoc.v:42416$1774_Y
- connect \$1681 $ternary$libresoc.v:42417$1775_Y
- connect \$1683 $and$libresoc.v:42418$1776_Y
- connect \$1686 $and$libresoc.v:42419$1777_Y
- connect \$1689 $not$libresoc.v:42420$1778_Y
- connect \$1691 $and$libresoc.v:42421$1779_Y
- connect \$1694 $and$libresoc.v:42422$1780_Y
- connect \$1697 $ternary$libresoc.v:42423$1781_Y
- connect \$1699 $and$libresoc.v:42424$1782_Y
- connect \$1702 $and$libresoc.v:42425$1783_Y
- connect \$1705 $not$libresoc.v:42426$1784_Y
- connect \$1707 $and$libresoc.v:42427$1785_Y
- connect \$1710 $and$libresoc.v:42428$1786_Y
- connect \$1713 $ternary$libresoc.v:42429$1787_Y
- connect \$1715 $or$libresoc.v:42430$1788_Y
- connect \$1717 $or$libresoc.v:42431$1789_Y
- connect \$1719 $or$libresoc.v:42432$1790_Y
- connect \$1721 $or$libresoc.v:42433$1791_Y
- connect \$1723 $or$libresoc.v:42434$1792_Y
- connect \$1725 $or$libresoc.v:42435$1793_Y
- connect \$1727 $or$libresoc.v:42436$1794_Y
- connect \$1729 $or$libresoc.v:42437$1795_Y
- connect \$1731 $or$libresoc.v:42438$1796_Y
- connect \$1733 $or$libresoc.v:42439$1797_Y
- connect \$1735 $or$libresoc.v:42440$1798_Y
- connect \$1737 $or$libresoc.v:42441$1799_Y
- connect \$1739 $and$libresoc.v:42442$1800_Y
- connect \$1741 $and$libresoc.v:42443$1801_Y
- connect \$1743 $and$libresoc.v:42444$1802_Y
- connect \$1746 $and$libresoc.v:42445$1803_Y
- connect \$1749 $not$libresoc.v:42446$1804_Y
- connect \$1751 $and$libresoc.v:42447$1805_Y
- connect \$1754 $and$libresoc.v:42448$1806_Y
- connect \$1757 $ternary$libresoc.v:42449$1807_Y
- connect \$1759 $and$libresoc.v:42450$1808_Y
- connect \$1762 $and$libresoc.v:42451$1809_Y
- connect \$1765 $not$libresoc.v:42452$1810_Y
- connect \$1767 $and$libresoc.v:42453$1811_Y
- connect \$1770 $and$libresoc.v:42454$1812_Y
- connect \$1773 $ternary$libresoc.v:42455$1813_Y
- connect \$1775 $or$libresoc.v:42456$1814_Y
- connect \$1778 $or$libresoc.v:42457$1815_Y
- connect \$1777 $pos$libresoc.v:42458$1817_Y
- connect \$1781 $and$libresoc.v:42459$1818_Y
- connect \$1783 $and$libresoc.v:42460$1819_Y
- connect \$1786 $and$libresoc.v:42461$1820_Y
- connect \$1789 $not$libresoc.v:42462$1821_Y
- connect \$1791 $and$libresoc.v:42463$1822_Y
- connect \$1794 $and$libresoc.v:42464$1823_Y
- connect \$1797 $ternary$libresoc.v:42465$1824_Y
- connect \$1799 $pos$libresoc.v:42466$1826_Y
- connect \$1801 $and$libresoc.v:42467$1827_Y
- connect \$1803 $and$libresoc.v:42468$1828_Y
- connect \$1806 $and$libresoc.v:42469$1829_Y
- connect \$1809 $not$libresoc.v:42470$1830_Y
- connect \$1811 $and$libresoc.v:42471$1831_Y
- connect \$1814 $and$libresoc.v:42472$1832_Y
- connect \$1817 $ternary$libresoc.v:42473$1833_Y
- connect \$182 $and$libresoc.v:42474$1834_Y
- connect \$181 $reduce_or$libresoc.v:42475$1835_Y
- connect \$186 $and$libresoc.v:42476$1836_Y
- connect \$185 $reduce_or$libresoc.v:42477$1837_Y
- connect \$190 $and$libresoc.v:42478$1838_Y
- connect \$189 $reduce_or$libresoc.v:42479$1839_Y
- connect \$194 $and$libresoc.v:42480$1840_Y
- connect \$193 $reduce_or$libresoc.v:42481$1841_Y
- connect \$198 $and$libresoc.v:42482$1842_Y
- connect \$197 $reduce_or$libresoc.v:42483$1843_Y
- connect \$202 $and$libresoc.v:42484$1844_Y
- connect \$201 $reduce_or$libresoc.v:42485$1845_Y
- connect \$206 $and$libresoc.v:42486$1846_Y
- connect \$205 $reduce_or$libresoc.v:42487$1847_Y
- connect \$210 $and$libresoc.v:42488$1848_Y
- connect \$209 $reduce_or$libresoc.v:42489$1849_Y
- connect \$214 $and$libresoc.v:42490$1850_Y
- connect \$213 $reduce_or$libresoc.v:42491$1851_Y
- connect \$218 $and$libresoc.v:42492$1852_Y
- connect \$217 $reduce_or$libresoc.v:42493$1853_Y
- connect \$221 $ne$libresoc.v:42494$1854_Y
- connect \$224 $sub$libresoc.v:42495$1855_Y
- connect \$226 $ne$libresoc.v:42496$1856_Y
- connect \$229 $and$libresoc.v:42497$1857_Y
- connect \$231 $and$libresoc.v:42498$1858_Y
- connect \$233 $eq$libresoc.v:42499$1859_Y
- connect \$235 $or$libresoc.v:42500$1860_Y
- connect \$237 $and$libresoc.v:42501$1861_Y
- connect \$239 $or$libresoc.v:42502$1862_Y
- connect \$241 $eq$libresoc.v:42503$1863_Y
- connect \$243 $and$libresoc.v:42504$1864_Y
- connect \$245 $eq$libresoc.v:42505$1865_Y
- connect \$247 $or$libresoc.v:42506$1866_Y
- connect \$228 $not$libresoc.v:42507$1867_Y
- connect \$250 $not$libresoc.v:42508$1868_Y
- connect \$252 $not$libresoc.v:42509$1869_Y
- connect \$254 $not$libresoc.v:42510$1870_Y
- connect \$257 $and$libresoc.v:42511$1871_Y
- connect \$259 $and$libresoc.v:42512$1872_Y
- connect \$261 $eq$libresoc.v:42513$1873_Y
- connect \$263 $or$libresoc.v:42514$1874_Y
- connect \$265 $and$libresoc.v:42515$1875_Y
- connect \$267 $or$libresoc.v:42516$1876_Y
- connect \$256 $not$libresoc.v:42517$1877_Y
- connect \$271 $and$libresoc.v:42518$1878_Y
- connect \$273 $and$libresoc.v:42519$1879_Y
- connect \$275 $eq$libresoc.v:42520$1880_Y
- connect \$277 $or$libresoc.v:42521$1881_Y
- connect \$279 $and$libresoc.v:42522$1882_Y
- connect \$281 $or$libresoc.v:42523$1883_Y
- connect \$283 $and$libresoc.v:42524$1884_Y
- connect \$285 $and$libresoc.v:42525$1885_Y
- connect \$287 $eq$libresoc.v:42526$1886_Y
- connect \$289 $or$libresoc.v:42527$1887_Y
- connect \$291 $eq$libresoc.v:42528$1888_Y
- connect \$293 $and$libresoc.v:42529$1889_Y
- connect \$295 $eq$libresoc.v:42530$1890_Y
- connect \$297 $or$libresoc.v:42531$1891_Y
- connect \$270 $not$libresoc.v:42532$1892_Y
- connect \$301 $and$libresoc.v:42533$1893_Y
- connect \$303 $and$libresoc.v:42534$1894_Y
- connect \$305 $eq$libresoc.v:42535$1895_Y
- connect \$307 $or$libresoc.v:42536$1896_Y
- connect \$309 $and$libresoc.v:42537$1897_Y
- connect \$311 $or$libresoc.v:42538$1898_Y
- connect \$300 $not$libresoc.v:42539$1899_Y
- connect \$315 $and$libresoc.v:42540$1900_Y
- connect \$317 $and$libresoc.v:42541$1901_Y
- connect \$319 $eq$libresoc.v:42542$1902_Y
- connect \$321 $or$libresoc.v:42543$1903_Y
- connect \$323 $and$libresoc.v:42544$1904_Y
- connect \$325 $or$libresoc.v:42545$1905_Y
- connect \$314 $not$libresoc.v:42546$1906_Y
- connect \$329 $and$libresoc.v:42547$1907_Y
- connect \$331 $and$libresoc.v:42548$1908_Y
- connect \$333 $eq$libresoc.v:42549$1909_Y
- connect \$335 $or$libresoc.v:42550$1910_Y
- connect \$337 $and$libresoc.v:42551$1911_Y
- connect \$339 $or$libresoc.v:42552$1912_Y
- connect \$341 $eq$libresoc.v:42553$1913_Y
- connect \$343 $and$libresoc.v:42554$1914_Y
- connect \$345 $eq$libresoc.v:42555$1915_Y
- connect \$347 $or$libresoc.v:42556$1916_Y
- connect \$328 $not$libresoc.v:42557$1917_Y
- connect \$350 $not$libresoc.v:42558$1918_Y
- connect \$352 $and$libresoc.v:42559$1919_Y
- connect \$354 $and$libresoc.v:42560$1920_Y
- connect \$356 $not$libresoc.v:42561$1921_Y
- connect \$358 $and$libresoc.v:42562$1922_Y
- connect \$360 $and$libresoc.v:42563$1923_Y
- connect \$362 $ternary$libresoc.v:42564$1924_Y
- connect \$364 $and$libresoc.v:42565$1925_Y
- connect \$366 $and$libresoc.v:42566$1926_Y
- connect \$368 $not$libresoc.v:42567$1927_Y
- connect \$370 $and$libresoc.v:42568$1928_Y
- connect \$372 $and$libresoc.v:42569$1929_Y
- connect \$374 $ternary$libresoc.v:42570$1930_Y
- connect \$376 $and$libresoc.v:42571$1931_Y
- connect \$378 $and$libresoc.v:42572$1932_Y
- connect \$380 $not$libresoc.v:42573$1933_Y
- connect \$382 $and$libresoc.v:42574$1934_Y
- connect \$384 $and$libresoc.v:42575$1935_Y
- connect \$386 $ternary$libresoc.v:42576$1936_Y
- connect \$388 $and$libresoc.v:42577$1937_Y
- connect \$390 $and$libresoc.v:42578$1938_Y
- connect \$392 $not$libresoc.v:42579$1939_Y
- connect \$394 $and$libresoc.v:42580$1940_Y
- connect \$396 $and$libresoc.v:42581$1941_Y
- connect \$398 $ternary$libresoc.v:42582$1942_Y
- connect \$400 $and$libresoc.v:42583$1943_Y
- connect \$402 $and$libresoc.v:42584$1944_Y
- connect \$404 $not$libresoc.v:42585$1945_Y
- connect \$406 $and$libresoc.v:42586$1946_Y
- connect \$408 $and$libresoc.v:42587$1947_Y
- connect \$410 $ternary$libresoc.v:42588$1948_Y
- connect \$412 $and$libresoc.v:42589$1949_Y
- connect \$414 $and$libresoc.v:42590$1950_Y
- connect \$416 $not$libresoc.v:42591$1951_Y
- connect \$418 $and$libresoc.v:42592$1952_Y
- connect \$420 $and$libresoc.v:42593$1953_Y
- connect \$422 $ternary$libresoc.v:42594$1954_Y
- connect \$424 $and$libresoc.v:42595$1955_Y
- connect \$426 $and$libresoc.v:42596$1956_Y
- connect \$428 $not$libresoc.v:42597$1957_Y
- connect \$430 $and$libresoc.v:42598$1958_Y
- connect \$432 $and$libresoc.v:42599$1959_Y
- connect \$434 $ternary$libresoc.v:42600$1960_Y
- connect \$436 $and$libresoc.v:42601$1961_Y
- connect \$438 $and$libresoc.v:42602$1962_Y
- connect \$440 $not$libresoc.v:42603$1963_Y
- connect \$442 $and$libresoc.v:42604$1964_Y
- connect \$444 $and$libresoc.v:42605$1965_Y
- connect \$446 $ternary$libresoc.v:42606$1966_Y
- connect \$448 $and$libresoc.v:42607$1967_Y
- connect \$450 $and$libresoc.v:42608$1968_Y
- connect \$452 $not$libresoc.v:42609$1969_Y
- connect \$454 $and$libresoc.v:42610$1970_Y
- connect \$456 $and$libresoc.v:42611$1971_Y
- connect \$458 $ternary$libresoc.v:42612$1972_Y
- connect \$461 $or$libresoc.v:42613$1973_Y
- connect \$463 $or$libresoc.v:42614$1974_Y
- connect \$465 $or$libresoc.v:42615$1975_Y
- connect \$467 $or$libresoc.v:42616$1976_Y
- connect \$469 $or$libresoc.v:42617$1977_Y
- connect \$471 $or$libresoc.v:42618$1978_Y
- connect \$473 $or$libresoc.v:42619$1979_Y
- connect \$475 $or$libresoc.v:42620$1980_Y
- connect \$477 $reduce_or$libresoc.v:42621$1981_Y
- connect \$479 $and$libresoc.v:42622$1982_Y
- connect \$481 $and$libresoc.v:42623$1983_Y
- connect \$483 $not$libresoc.v:42624$1984_Y
- connect \$485 $and$libresoc.v:42625$1985_Y
- connect \$487 $and$libresoc.v:42626$1986_Y
- connect \$489 $ternary$libresoc.v:42627$1987_Y
- connect \$491 $and$libresoc.v:42628$1988_Y
- connect \$493 $and$libresoc.v:42629$1989_Y
- connect \$495 $not$libresoc.v:42630$1990_Y
- connect \$497 $and$libresoc.v:42631$1991_Y
- connect \$499 $and$libresoc.v:42632$1992_Y
- connect \$501 $ternary$libresoc.v:42633$1993_Y
- connect \$503 $and$libresoc.v:42634$1994_Y
- connect \$505 $and$libresoc.v:42635$1995_Y
- connect \$507 $not$libresoc.v:42636$1996_Y
- connect \$509 $and$libresoc.v:42637$1997_Y
- connect \$511 $and$libresoc.v:42638$1998_Y
- connect \$513 $ternary$libresoc.v:42639$1999_Y
- connect \$515 $and$libresoc.v:42640$2000_Y
- connect \$517 $and$libresoc.v:42641$2001_Y
- connect \$519 $not$libresoc.v:42642$2002_Y
- connect \$521 $and$libresoc.v:42643$2003_Y
- connect \$523 $and$libresoc.v:42644$2004_Y
- connect \$525 $ternary$libresoc.v:42645$2005_Y
- connect \$527 $and$libresoc.v:42646$2006_Y
- connect \$529 $and$libresoc.v:42647$2007_Y
- connect \$531 $not$libresoc.v:42648$2008_Y
- connect \$533 $and$libresoc.v:42649$2009_Y
- connect \$535 $and$libresoc.v:42650$2010_Y
- connect \$537 $ternary$libresoc.v:42651$2011_Y
- connect \$539 $and$libresoc.v:42652$2012_Y
- connect \$541 $and$libresoc.v:42653$2013_Y
- connect \$543 $not$libresoc.v:42654$2014_Y
- connect \$545 $and$libresoc.v:42655$2015_Y
- connect \$547 $and$libresoc.v:42656$2016_Y
- connect \$549 $ternary$libresoc.v:42657$2017_Y
- connect \$551 $and$libresoc.v:42658$2018_Y
- connect \$553 $and$libresoc.v:42659$2019_Y
- connect \$555 $not$libresoc.v:42660$2020_Y
- connect \$557 $and$libresoc.v:42661$2021_Y
- connect \$559 $and$libresoc.v:42662$2022_Y
- connect \$561 $ternary$libresoc.v:42663$2023_Y
- connect \$563 $and$libresoc.v:42664$2024_Y
- connect \$565 $and$libresoc.v:42665$2025_Y
- connect \$567 $not$libresoc.v:42666$2026_Y
- connect \$569 $and$libresoc.v:42667$2027_Y
- connect \$571 $and$libresoc.v:42668$2028_Y
- connect \$573 $ternary$libresoc.v:42669$2029_Y
- connect \$576 $or$libresoc.v:42670$2030_Y
- connect \$578 $or$libresoc.v:42671$2031_Y
- connect \$580 $or$libresoc.v:42672$2032_Y
- connect \$582 $or$libresoc.v:42673$2033_Y
- connect \$584 $or$libresoc.v:42674$2034_Y
- connect \$586 $or$libresoc.v:42675$2035_Y
- connect \$588 $or$libresoc.v:42676$2036_Y
- connect \$590 $reduce_or$libresoc.v:42677$2037_Y
- connect \$592 $and$libresoc.v:42678$2038_Y
- connect \$594 $and$libresoc.v:42679$2039_Y
- connect \$596 $not$libresoc.v:42680$2040_Y
- connect \$598 $and$libresoc.v:42681$2041_Y
- connect \$600 $and$libresoc.v:42682$2042_Y
- connect \$602 $ternary$libresoc.v:42683$2043_Y
- connect \$604 $and$libresoc.v:42684$2044_Y
- connect \$606 $and$libresoc.v:42685$2045_Y
- connect \$608 $not$libresoc.v:42686$2046_Y
- connect \$610 $and$libresoc.v:42687$2047_Y
- connect \$612 $and$libresoc.v:42688$2048_Y
- connect \$614 $ternary$libresoc.v:42689$2049_Y
- connect \$617 $or$libresoc.v:42690$2050_Y
- connect \$619 $reduce_or$libresoc.v:42691$2051_Y
- connect \$621 $and$libresoc.v:42692$2052_Y
- connect \$623 $and$libresoc.v:42693$2053_Y
- connect \$625 $eq$libresoc.v:42694$2054_Y
- connect \$627 $or$libresoc.v:42695$2055_Y
- connect \$629 $and$libresoc.v:42696$2056_Y
- connect \$631 $or$libresoc.v:42697$2057_Y
- connect \$633 $and$libresoc.v:42698$2058_Y
- connect \$635 $and$libresoc.v:42699$2059_Y
- connect \$637 $not$libresoc.v:42700$2060_Y
- connect \$639 $and$libresoc.v:42701$2061_Y
- connect \$641 $and$libresoc.v:42702$2062_Y
- connect \$643 $ternary$libresoc.v:42703$2063_Y
- connect \$645 $and$libresoc.v:42704$2064_Y
- connect \$647 $and$libresoc.v:42705$2065_Y
- connect \$649 $not$libresoc.v:42706$2066_Y
- connect \$651 $and$libresoc.v:42707$2067_Y
- connect \$653 $and$libresoc.v:42708$2068_Y
- connect \$655 $ternary$libresoc.v:42709$2069_Y
- connect \$657 $and$libresoc.v:42710$2070_Y
- connect \$659 $and$libresoc.v:42711$2071_Y
- connect \$661 $not$libresoc.v:42712$2072_Y
- connect \$663 $and$libresoc.v:42713$2073_Y
- connect \$665 $and$libresoc.v:42714$2074_Y
- connect \$667 $ternary$libresoc.v:42715$2075_Y
- connect \$669 $and$libresoc.v:42716$2076_Y
- connect \$671 $and$libresoc.v:42717$2077_Y
- connect \$673 $not$libresoc.v:42718$2078_Y
- connect \$675 $and$libresoc.v:42719$2079_Y
- connect \$677 $and$libresoc.v:42720$2080_Y
- connect \$679 $ternary$libresoc.v:42721$2081_Y
- connect \$681 $and$libresoc.v:42722$2082_Y
- connect \$683 $and$libresoc.v:42723$2083_Y
- connect \$685 $not$libresoc.v:42724$2084_Y
- connect \$687 $and$libresoc.v:42725$2085_Y
- connect \$689 $and$libresoc.v:42726$2086_Y
- connect \$691 $ternary$libresoc.v:42727$2087_Y
- connect \$693 $and$libresoc.v:42728$2088_Y
- connect \$695 $and$libresoc.v:42729$2089_Y
- connect \$697 $not$libresoc.v:42730$2090_Y
- connect \$699 $and$libresoc.v:42731$2091_Y
- connect \$701 $and$libresoc.v:42732$2092_Y
- connect \$703 $ternary$libresoc.v:42733$2093_Y
- connect \$706 $or$libresoc.v:42734$2094_Y
- connect \$708 $or$libresoc.v:42735$2095_Y
- connect \$710 $or$libresoc.v:42736$2096_Y
- connect \$712 $or$libresoc.v:42737$2097_Y
- connect \$714 $or$libresoc.v:42738$2098_Y
- connect \$705 $pos$libresoc.v:42739$2100_Y
- connect \$717 $eq$libresoc.v:42740$2101_Y
- connect \$719 $and$libresoc.v:42741$2102_Y
- connect \$721 $eq$libresoc.v:42742$2103_Y
- connect \$723 $or$libresoc.v:42743$2104_Y
- connect \$725 $and$libresoc.v:42744$2105_Y
- connect \$727 $and$libresoc.v:42745$2106_Y
- connect \$729 $not$libresoc.v:42746$2107_Y
- connect \$731 $and$libresoc.v:42747$2108_Y
- connect \$733 $and$libresoc.v:42748$2109_Y
- connect \$735 $ternary$libresoc.v:42749$2110_Y
- connect \$737 $and$libresoc.v:42750$2111_Y
- connect \$739 $and$libresoc.v:42751$2112_Y
- connect \$741 $not$libresoc.v:42752$2113_Y
- connect \$743 $and$libresoc.v:42753$2114_Y
- connect \$745 $and$libresoc.v:42754$2115_Y
- connect \$747 $ternary$libresoc.v:42755$2116_Y
- connect \$749 $and$libresoc.v:42756$2117_Y
- connect \$751 $and$libresoc.v:42757$2118_Y
- connect \$753 $not$libresoc.v:42758$2119_Y
- connect \$755 $and$libresoc.v:42759$2120_Y
- connect \$757 $and$libresoc.v:42760$2121_Y
- connect \$759 $ternary$libresoc.v:42761$2122_Y
- connect \$762 $or$libresoc.v:42762$2123_Y
- connect \$764 $or$libresoc.v:42763$2124_Y
- connect \$761 $pos$libresoc.v:42764$2126_Y
- connect \$767 $and$libresoc.v:42765$2127_Y
- connect \$769 $and$libresoc.v:42766$2128_Y
- connect \$771 $eq$libresoc.v:42767$2129_Y
- connect \$773 $or$libresoc.v:42768$2130_Y
- connect \$775 $and$libresoc.v:42769$2131_Y
- connect \$777 $and$libresoc.v:42770$2132_Y
- connect \$779 $not$libresoc.v:42771$2133_Y
- connect \$781 $and$libresoc.v:42772$2134_Y
- connect \$783 $and$libresoc.v:42773$2135_Y
- connect \$785 $ternary$libresoc.v:42774$2136_Y
- connect \$787 $and$libresoc.v:42775$2137_Y
- connect \$789 $and$libresoc.v:42776$2138_Y
- connect \$791 $not$libresoc.v:42777$2139_Y
- connect \$793 $and$libresoc.v:42778$2140_Y
- connect \$795 $and$libresoc.v:42779$2141_Y
- connect \$797 $ternary$libresoc.v:42780$2142_Y
- connect \$799 $and$libresoc.v:42781$2143_Y
- connect \$801 $and$libresoc.v:42782$2144_Y
- connect \$803 $not$libresoc.v:42783$2145_Y
- connect \$805 $and$libresoc.v:42784$2146_Y
- connect \$807 $and$libresoc.v:42785$2147_Y
- connect \$809 $sub$libresoc.v:42786$2148_Y
- connect \$811 $sshl$libresoc.v:42787$2149_Y
- connect \$813 $ternary$libresoc.v:42788$2150_Y
- connect \$815 $and$libresoc.v:42789$2151_Y
- connect \$817 $and$libresoc.v:42790$2152_Y
- connect \$819 $not$libresoc.v:42791$2153_Y
- connect \$821 $and$libresoc.v:42792$2154_Y
- connect \$823 $and$libresoc.v:42793$2155_Y
- connect \$825 $sub$libresoc.v:42794$2156_Y
- connect \$827 $sshl$libresoc.v:42795$2157_Y
- connect \$829 $ternary$libresoc.v:42796$2158_Y
- connect \$832 $or$libresoc.v:42797$2159_Y
- connect \$834 $and$libresoc.v:42798$2160_Y
- connect \$836 $and$libresoc.v:42799$2161_Y
- connect \$838 $not$libresoc.v:42800$2162_Y
- connect \$840 $and$libresoc.v:42801$2163_Y
- connect \$842 $and$libresoc.v:42802$2164_Y
- connect \$844 $sub$libresoc.v:42803$2165_Y
- connect \$846 $sshl$libresoc.v:42804$2166_Y
- connect \$848 $ternary$libresoc.v:42805$2167_Y
- connect \$850 $and$libresoc.v:42806$2168_Y
- connect \$852 $and$libresoc.v:42807$2169_Y
- connect \$854 $not$libresoc.v:42808$2170_Y
- connect \$856 $and$libresoc.v:42809$2171_Y
- connect \$858 $and$libresoc.v:42810$2172_Y
- connect \$860 $sub$libresoc.v:42811$2173_Y
- connect \$862 $sshl$libresoc.v:42812$2174_Y
- connect \$864 $ternary$libresoc.v:42813$2175_Y
- connect \$866 $and$libresoc.v:42814$2176_Y
- connect \$868 $and$libresoc.v:42815$2177_Y
- connect \$870 $not$libresoc.v:42816$2178_Y
- connect \$872 $and$libresoc.v:42817$2179_Y
- connect \$874 $and$libresoc.v:42818$2180_Y
- connect \$876 $ternary$libresoc.v:42819$2181_Y
- connect \$878 $and$libresoc.v:42820$2182_Y
- connect \$880 $and$libresoc.v:42821$2183_Y
- connect \$882 $not$libresoc.v:42822$2184_Y
- connect \$884 $and$libresoc.v:42823$2185_Y
- connect \$886 $and$libresoc.v:42824$2186_Y
- connect \$888 $ternary$libresoc.v:42825$2187_Y
- connect \$890 $and$libresoc.v:42826$2188_Y
- connect \$892 $and$libresoc.v:42827$2189_Y
- connect \$894 $not$libresoc.v:42828$2190_Y
- connect \$896 $and$libresoc.v:42829$2191_Y
- connect \$898 $and$libresoc.v:42830$2192_Y
- connect \$900 $ternary$libresoc.v:42831$2193_Y
- connect \$902 $or$libresoc.v:42832$2194_Y
- connect \$904 $or$libresoc.v:42833$2195_Y
- connect \$906 $reduce_or$libresoc.v:42834$2196_Y
- connect \$908 $and$libresoc.v:42835$2197_Y
- connect \$910 $and$libresoc.v:42836$2198_Y
- connect \$912 $not$libresoc.v:42837$2199_Y
- connect \$914 $and$libresoc.v:42838$2200_Y
- connect \$916 $and$libresoc.v:42839$2201_Y
- connect \$918 $ternary$libresoc.v:42840$2202_Y
- connect \$920 $and$libresoc.v:42841$2203_Y
- connect \$922 $and$libresoc.v:42842$2204_Y
- connect \$924 $not$libresoc.v:42843$2205_Y
- connect \$926 $and$libresoc.v:42844$2206_Y
- connect \$928 $and$libresoc.v:42845$2207_Y
- connect \$930 $ternary$libresoc.v:42846$2208_Y
- connect \$932 $or$libresoc.v:42847$2209_Y
- connect \$934 $reduce_or$libresoc.v:42848$2210_Y
- connect \$936 $and$libresoc.v:42849$2211_Y
- connect \$938 $and$libresoc.v:42850$2212_Y
- connect \$940 $not$libresoc.v:42851$2213_Y
- connect \$942 $and$libresoc.v:42852$2214_Y
- connect \$944 $and$libresoc.v:42853$2215_Y
- connect \$946 $ternary$libresoc.v:42854$2216_Y
- connect \$948 $reduce_or$libresoc.v:42855$2217_Y
- connect \$950 $and$libresoc.v:42856$2218_Y
- connect \$952 $and$libresoc.v:42857$2219_Y
- connect \$954 $and$libresoc.v:42858$2220_Y
- connect \$956 $and$libresoc.v:42859$2221_Y
- connect \$958 $and$libresoc.v:42860$2222_Y
- connect \$960 $and$libresoc.v:42861$2223_Y
- connect \$962 $and$libresoc.v:42862$2224_Y
- connect \$964 $and$libresoc.v:42863$2225_Y
- connect \$966 $and$libresoc.v:42864$2226_Y
- connect \$968 $and$libresoc.v:42865$2227_Y
- connect \$970 $and$libresoc.v:42866$2228_Y
- connect \$972 $and$libresoc.v:42867$2229_Y
- connect \$974 $not$libresoc.v:42868$2230_Y
- connect \$976 $and$libresoc.v:42869$2231_Y
- connect \$982 $and$libresoc.v:42870$2232_Y
- connect \$984 $ternary$libresoc.v:42871$2233_Y
- connect \$986 $and$libresoc.v:42872$2234_Y
- connect \$989 $and$libresoc.v:42873$2235_Y
- connect \$993 $not$libresoc.v:42874$2236_Y
- connect \$995 $and$libresoc.v:42875$2237_Y
+ connect \$1001 $ternary$libresoc.v:42111$1506_Y
+ connect \$1003 $and$libresoc.v:42112$1507_Y
+ connect \$1006 $and$libresoc.v:42113$1508_Y
+ connect \$1010 $not$libresoc.v:42114$1509_Y
+ connect \$1012 $and$libresoc.v:42115$1510_Y
+ connect \$1019 $and$libresoc.v:42116$1511_Y
+ connect \$1022 $ternary$libresoc.v:42117$1512_Y
+ connect \$1024 $and$libresoc.v:42118$1513_Y
+ connect \$1027 $and$libresoc.v:42119$1514_Y
+ connect \$1031 $not$libresoc.v:42120$1515_Y
+ connect \$1033 $and$libresoc.v:42121$1516_Y
+ connect \$1037 $and$libresoc.v:42122$1517_Y
+ connect \$1040 $ternary$libresoc.v:42123$1518_Y
+ connect \$1042 $and$libresoc.v:42124$1519_Y
+ connect \$1045 $and$libresoc.v:42125$1520_Y
+ connect \$1049 $not$libresoc.v:42126$1521_Y
+ connect \$1051 $and$libresoc.v:42127$1522_Y
+ connect \$1059 $and$libresoc.v:42128$1523_Y
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+ connect \$1064 $and$libresoc.v:42130$1525_Y
+ connect \$1067 $and$libresoc.v:42131$1526_Y
+ connect \$1071 $not$libresoc.v:42132$1527_Y
+ connect \$1073 $and$libresoc.v:42133$1528_Y
+ connect \$1079 $and$libresoc.v:42134$1529_Y
+ connect \$1082 $ternary$libresoc.v:42135$1530_Y
+ connect \$1084 $and$libresoc.v:42136$1531_Y
+ connect \$1087 $and$libresoc.v:42137$1532_Y
+ connect \$1091 $not$libresoc.v:42138$1533_Y
+ connect \$1093 $and$libresoc.v:42139$1534_Y
+ connect \$1099 $and$libresoc.v:42140$1535_Y
+ connect \$1102 $ternary$libresoc.v:42141$1536_Y
+ connect \$1104 $and$libresoc.v:42142$1537_Y
+ connect \$1107 $and$libresoc.v:42143$1538_Y
+ connect \$1111 $not$libresoc.v:42144$1539_Y
+ connect \$1113 $and$libresoc.v:42145$1540_Y
+ connect \$1118 $and$libresoc.v:42146$1541_Y
+ connect \$1121 $ternary$libresoc.v:42147$1542_Y
+ connect \$1123 $and$libresoc.v:42148$1543_Y
+ connect \$1126 $and$libresoc.v:42149$1544_Y
+ connect \$1130 $not$libresoc.v:42150$1545_Y
+ connect \$1132 $and$libresoc.v:42151$1546_Y
+ connect \$1136 $and$libresoc.v:42152$1547_Y
+ connect \$1139 $ternary$libresoc.v:42153$1548_Y
+ connect \$1141 $and$libresoc.v:42154$1549_Y
+ connect \$1144 $and$libresoc.v:42155$1550_Y
+ connect \$1147 $not$libresoc.v:42156$1551_Y
+ connect \$1149 $and$libresoc.v:42157$1552_Y
+ connect \$1152 $and$libresoc.v:42158$1553_Y
+ connect \$1155 $ternary$libresoc.v:42159$1554_Y
+ connect \$1158 $or$libresoc.v:42160$1555_Y
+ connect \$1160 $or$libresoc.v:42161$1556_Y
+ connect \$1162 $or$libresoc.v:42162$1557_Y
+ connect \$1164 $or$libresoc.v:42163$1558_Y
+ connect \$1166 $or$libresoc.v:42164$1559_Y
+ connect \$1168 $or$libresoc.v:42165$1560_Y
+ connect \$1170 $or$libresoc.v:42166$1561_Y
+ connect \$1172 $or$libresoc.v:42167$1562_Y
+ connect \$1174 $or$libresoc.v:42168$1563_Y
+ connect \$1177 $or$libresoc.v:42169$1564_Y
+ connect \$1179 $or$libresoc.v:42170$1565_Y
+ connect \$1181 $or$libresoc.v:42171$1566_Y
+ connect \$1183 $or$libresoc.v:42172$1567_Y
+ connect \$1185 $or$libresoc.v:42173$1568_Y
+ connect \$1187 $or$libresoc.v:42174$1569_Y
+ connect \$1189 $or$libresoc.v:42175$1570_Y
+ connect \$1191 $or$libresoc.v:42176$1571_Y
+ connect \$1193 $or$libresoc.v:42177$1572_Y
+ connect \$1195 $or$libresoc.v:42178$1573_Y
+ connect \$1197 $or$libresoc.v:42179$1574_Y
+ connect \$1199 $or$libresoc.v:42180$1575_Y
+ connect \$1201 $or$libresoc.v:42181$1576_Y
+ connect \$1203 $or$libresoc.v:42182$1577_Y
+ connect \$1205 $or$libresoc.v:42183$1578_Y
+ connect \$1207 $or$libresoc.v:42184$1579_Y
+ connect \$1209 $or$libresoc.v:42185$1580_Y
+ connect \$1211 $or$libresoc.v:42186$1581_Y
+ connect \$1213 $and$libresoc.v:42187$1582_Y
+ connect \$1215 $and$libresoc.v:42188$1583_Y
+ connect \$1218 $and$libresoc.v:42189$1584_Y
+ connect \$1221 $not$libresoc.v:42190$1585_Y
+ connect \$1223 $and$libresoc.v:42191$1586_Y
+ connect \$1226 $and$libresoc.v:42192$1587_Y
+ connect \$1229 $ternary$libresoc.v:42193$1588_Y
+ connect \$1231 $and$libresoc.v:42194$1589_Y
+ connect \$1233 $and$libresoc.v:42195$1590_Y
+ connect \$1235 $and$libresoc.v:42196$1591_Y
+ connect \$1237 $and$libresoc.v:42197$1592_Y
+ connect \$1239 $and$libresoc.v:42198$1593_Y
+ connect \$1241 $and$libresoc.v:42199$1594_Y
+ connect \$1243 $and$libresoc.v:42200$1595_Y
+ connect \$1246 $and$libresoc.v:42201$1596_Y
+ connect \$1249 $not$libresoc.v:42202$1597_Y
+ connect \$1251 $and$libresoc.v:42203$1598_Y
+ connect \$1254 $and$libresoc.v:42204$1599_Y
+ connect \$1257 $sub$libresoc.v:42205$1600_Y
+ connect \$1259 $sshl$libresoc.v:42206$1601_Y
+ connect \$1261 $ternary$libresoc.v:42207$1602_Y
+ connect \$1263 $and$libresoc.v:42208$1603_Y
+ connect \$1266 $and$libresoc.v:42209$1604_Y
+ connect \$1269 $not$libresoc.v:42210$1605_Y
+ connect \$1271 $and$libresoc.v:42211$1606_Y
+ connect \$1274 $and$libresoc.v:42212$1607_Y
+ connect \$1277 $sub$libresoc.v:42213$1608_Y
+ connect \$1279 $sshl$libresoc.v:42214$1609_Y
+ connect \$1281 $ternary$libresoc.v:42215$1610_Y
+ connect \$1283 $and$libresoc.v:42216$1611_Y
+ connect \$1286 $and$libresoc.v:42217$1612_Y
+ connect \$1289 $not$libresoc.v:42218$1613_Y
+ connect \$1291 $and$libresoc.v:42219$1614_Y
+ connect \$1294 $and$libresoc.v:42220$1615_Y
+ connect \$1297 $sub$libresoc.v:42221$1616_Y
+ connect \$1299 $sshl$libresoc.v:42222$1617_Y
+ connect \$1301 $ternary$libresoc.v:42223$1618_Y
+ connect \$1303 $and$libresoc.v:42224$1619_Y
+ connect \$1306 $and$libresoc.v:42225$1620_Y
+ connect \$1309 $not$libresoc.v:42226$1621_Y
+ connect \$1311 $and$libresoc.v:42227$1622_Y
+ connect \$1314 $and$libresoc.v:42228$1623_Y
+ connect \$1317 $sub$libresoc.v:42229$1624_Y
+ connect \$1319 $sshl$libresoc.v:42230$1625_Y
+ connect \$1321 $ternary$libresoc.v:42231$1626_Y
+ connect \$1323 $and$libresoc.v:42232$1627_Y
+ connect \$1326 $and$libresoc.v:42233$1628_Y
+ connect \$1329 $not$libresoc.v:42234$1629_Y
+ connect \$1331 $and$libresoc.v:42235$1630_Y
+ connect \$1334 $and$libresoc.v:42236$1631_Y
+ connect \$1337 $sub$libresoc.v:42237$1632_Y
+ connect \$1339 $sshl$libresoc.v:42238$1633_Y
+ connect \$1341 $ternary$libresoc.v:42239$1634_Y
+ connect \$1343 $and$libresoc.v:42240$1635_Y
+ connect \$1346 $and$libresoc.v:42241$1636_Y
+ connect \$1349 $not$libresoc.v:42242$1637_Y
+ connect \$1351 $and$libresoc.v:42243$1638_Y
+ connect \$1354 $and$libresoc.v:42244$1639_Y
+ connect \$1357 $sub$libresoc.v:42245$1640_Y
+ connect \$1359 $sshl$libresoc.v:42246$1641_Y
+ connect \$1361 $ternary$libresoc.v:42247$1642_Y
+ connect \$1363 $or$libresoc.v:42248$1643_Y
+ connect \$1365 $or$libresoc.v:42249$1644_Y
+ connect \$1367 $or$libresoc.v:42250$1645_Y
+ connect \$1369 $or$libresoc.v:42251$1646_Y
+ connect \$1371 $or$libresoc.v:42252$1647_Y
+ connect \$1374 $or$libresoc.v:42253$1648_Y
+ connect \$1376 $or$libresoc.v:42254$1649_Y
+ connect \$1378 $or$libresoc.v:42255$1650_Y
+ connect \$1380 $or$libresoc.v:42256$1651_Y
+ connect \$1382 $or$libresoc.v:42257$1652_Y
+ connect \$1384 $and$libresoc.v:42258$1653_Y
+ connect \$1386 $and$libresoc.v:42259$1654_Y
+ connect \$1388 $and$libresoc.v:42260$1655_Y
+ connect \$1390 $and$libresoc.v:42261$1656_Y
+ connect \$1393 $and$libresoc.v:42262$1657_Y
+ connect \$1396 $not$libresoc.v:42263$1658_Y
+ connect \$1398 $and$libresoc.v:42264$1659_Y
+ connect \$1401 $and$libresoc.v:42265$1660_Y
+ connect \$1404 $ternary$libresoc.v:42266$1661_Y
+ connect \$1406 $and$libresoc.v:42267$1662_Y
+ connect \$1409 $and$libresoc.v:42268$1663_Y
+ connect \$1412 $not$libresoc.v:42269$1664_Y
+ connect \$1414 $and$libresoc.v:42270$1665_Y
+ connect \$1417 $and$libresoc.v:42271$1666_Y
+ connect \$1420 $ternary$libresoc.v:42272$1667_Y
+ connect \$1422 $and$libresoc.v:42273$1668_Y
+ connect \$1425 $and$libresoc.v:42274$1669_Y
+ connect \$1428 $not$libresoc.v:42275$1670_Y
+ connect \$1430 $and$libresoc.v:42276$1671_Y
+ connect \$1433 $and$libresoc.v:42277$1672_Y
+ connect \$1436 $ternary$libresoc.v:42278$1673_Y
+ connect \$1438 $or$libresoc.v:42279$1674_Y
+ connect \$1440 $or$libresoc.v:42280$1675_Y
+ connect \$1443 $or$libresoc.v:42281$1676_Y
+ connect \$1445 $or$libresoc.v:42282$1677_Y
+ connect \$1442 $pos$libresoc.v:42283$1679_Y
+ connect \$1448 $and$libresoc.v:42284$1680_Y
+ connect \$1450 $and$libresoc.v:42285$1681_Y
+ connect \$1452 $and$libresoc.v:42286$1682_Y
+ connect \$1454 $and$libresoc.v:42287$1683_Y
+ connect \$1456 $and$libresoc.v:42288$1684_Y
+ connect \$1459 $and$libresoc.v:42289$1685_Y
+ connect \$1462 $not$libresoc.v:42290$1686_Y
+ connect \$1464 $and$libresoc.v:42291$1687_Y
+ connect \$1467 $and$libresoc.v:42292$1688_Y
+ connect \$1470 $ternary$libresoc.v:42293$1689_Y
+ connect \$1472 $and$libresoc.v:42294$1690_Y
+ connect \$1475 $and$libresoc.v:42295$1691_Y
+ connect \$1478 $not$libresoc.v:42296$1692_Y
+ connect \$1480 $and$libresoc.v:42297$1693_Y
+ connect \$1483 $and$libresoc.v:42298$1694_Y
+ connect \$1486 $ternary$libresoc.v:42299$1695_Y
+ connect \$1488 $and$libresoc.v:42300$1696_Y
+ connect \$1491 $and$libresoc.v:42301$1697_Y
+ connect \$1494 $not$libresoc.v:42302$1698_Y
+ connect \$1496 $and$libresoc.v:42303$1699_Y
+ connect \$1499 $and$libresoc.v:42304$1700_Y
+ connect \$1502 $ternary$libresoc.v:42305$1701_Y
+ connect \$1504 $and$libresoc.v:42306$1702_Y
+ connect \$1507 $and$libresoc.v:42307$1703_Y
+ connect \$1510 $not$libresoc.v:42308$1704_Y
+ connect \$1512 $and$libresoc.v:42309$1705_Y
+ connect \$1515 $and$libresoc.v:42310$1706_Y
+ connect \$1518 $ternary$libresoc.v:42311$1707_Y
+ connect \$1520 $or$libresoc.v:42312$1708_Y
+ connect \$1522 $or$libresoc.v:42313$1709_Y
+ connect \$1524 $or$libresoc.v:42314$1710_Y
+ connect \$1526 $or$libresoc.v:42315$1711_Y
+ connect \$1528 $or$libresoc.v:42316$1712_Y
+ connect \$1530 $or$libresoc.v:42317$1713_Y
+ connect \$1532 $and$libresoc.v:42318$1714_Y
+ connect \$1534 $and$libresoc.v:42319$1715_Y
+ connect \$1536 $and$libresoc.v:42320$1716_Y
+ connect \$1538 $and$libresoc.v:42321$1717_Y
+ connect \$1540 $and$libresoc.v:42322$1718_Y
+ connect \$1543 $and$libresoc.v:42323$1719_Y
+ connect \$1546 $not$libresoc.v:42324$1720_Y
+ connect \$1548 $and$libresoc.v:42325$1721_Y
+ connect \$1551 $and$libresoc.v:42326$1722_Y
+ connect \$1554 $ternary$libresoc.v:42327$1723_Y
+ connect \$1556 $and$libresoc.v:42328$1724_Y
+ connect \$1559 $and$libresoc.v:42329$1725_Y
+ connect \$1562 $not$libresoc.v:42330$1726_Y
+ connect \$1564 $and$libresoc.v:42331$1727_Y
+ connect \$1567 $and$libresoc.v:42332$1728_Y
+ connect \$1570 $ternary$libresoc.v:42333$1729_Y
+ connect \$1572 $and$libresoc.v:42334$1730_Y
+ connect \$1575 $and$libresoc.v:42335$1731_Y
+ connect \$1578 $not$libresoc.v:42336$1732_Y
+ connect \$1580 $and$libresoc.v:42337$1733_Y
+ connect \$1583 $and$libresoc.v:42338$1734_Y
+ connect \$1586 $ternary$libresoc.v:42339$1735_Y
+ connect \$1588 $and$libresoc.v:42340$1736_Y
+ connect \$1591 $and$libresoc.v:42341$1737_Y
+ connect \$1594 $not$libresoc.v:42342$1738_Y
+ connect \$1596 $and$libresoc.v:42343$1739_Y
+ connect \$1599 $and$libresoc.v:42344$1740_Y
+ connect \$1602 $ternary$libresoc.v:42345$1741_Y
+ connect \$1605 $or$libresoc.v:42346$1742_Y
+ connect \$1607 $or$libresoc.v:42347$1743_Y
+ connect \$1609 $or$libresoc.v:42348$1744_Y
+ connect \$1604 $pos$libresoc.v:42349$1746_Y
+ connect \$1613 $or$libresoc.v:42350$1747_Y
+ connect \$1615 $or$libresoc.v:42351$1748_Y
+ connect \$1617 $or$libresoc.v:42352$1749_Y
+ connect \$1612 $pos$libresoc.v:42353$1751_Y
+ connect \$1620 $and$libresoc.v:42354$1752_Y
+ connect \$1622 $and$libresoc.v:42355$1753_Y
+ connect \$1624 $and$libresoc.v:42356$1754_Y
+ connect \$1626 $and$libresoc.v:42357$1755_Y
+ connect \$1628 $and$libresoc.v:42358$1756_Y
+ connect \$1630 $and$libresoc.v:42359$1757_Y
+ connect \$1633 $and$libresoc.v:42360$1758_Y
+ connect \$1637 $not$libresoc.v:42361$1759_Y
+ connect \$1639 $and$libresoc.v:42362$1760_Y
+ connect \$1644 $and$libresoc.v:42363$1761_Y
+ connect \$1647 $ternary$libresoc.v:42364$1762_Y
+ connect \$1649 $and$libresoc.v:42365$1763_Y
+ connect \$1652 $and$libresoc.v:42366$1764_Y
+ connect \$1655 $not$libresoc.v:42367$1765_Y
+ connect \$1657 $and$libresoc.v:42368$1766_Y
+ connect \$1660 $and$libresoc.v:42369$1767_Y
+ connect \$1663 $ternary$libresoc.v:42370$1768_Y
+ connect \$1665 $and$libresoc.v:42371$1769_Y
+ connect \$1668 $and$libresoc.v:42372$1770_Y
+ connect \$1671 $not$libresoc.v:42373$1771_Y
+ connect \$1673 $and$libresoc.v:42374$1772_Y
+ connect \$1676 $and$libresoc.v:42375$1773_Y
+ connect \$1679 $ternary$libresoc.v:42376$1774_Y
+ connect \$1681 $and$libresoc.v:42377$1775_Y
+ connect \$1684 $and$libresoc.v:42378$1776_Y
+ connect \$1687 $not$libresoc.v:42379$1777_Y
+ connect \$1689 $and$libresoc.v:42380$1778_Y
+ connect \$1692 $and$libresoc.v:42381$1779_Y
+ connect \$1695 $ternary$libresoc.v:42382$1780_Y
+ connect \$1697 $and$libresoc.v:42383$1781_Y
+ connect \$1700 $and$libresoc.v:42384$1782_Y
+ connect \$1703 $not$libresoc.v:42385$1783_Y
+ connect \$1705 $and$libresoc.v:42386$1784_Y
+ connect \$1708 $and$libresoc.v:42387$1785_Y
+ connect \$1711 $ternary$libresoc.v:42388$1786_Y
+ connect \$1713 $or$libresoc.v:42389$1787_Y
+ connect \$1715 $or$libresoc.v:42390$1788_Y
+ connect \$1717 $or$libresoc.v:42391$1789_Y
+ connect \$1719 $or$libresoc.v:42392$1790_Y
+ connect \$1721 $or$libresoc.v:42393$1791_Y
+ connect \$1723 $or$libresoc.v:42394$1792_Y
+ connect \$1725 $or$libresoc.v:42395$1793_Y
+ connect \$1727 $or$libresoc.v:42396$1794_Y
+ connect \$1729 $or$libresoc.v:42397$1795_Y
+ connect \$1731 $or$libresoc.v:42398$1796_Y
+ connect \$1733 $or$libresoc.v:42399$1797_Y
+ connect \$1735 $or$libresoc.v:42400$1798_Y
+ connect \$1737 $and$libresoc.v:42401$1799_Y
+ connect \$1739 $and$libresoc.v:42402$1800_Y
+ connect \$1741 $and$libresoc.v:42403$1801_Y
+ connect \$1744 $and$libresoc.v:42404$1802_Y
+ connect \$1747 $not$libresoc.v:42405$1803_Y
+ connect \$1749 $and$libresoc.v:42406$1804_Y
+ connect \$1752 $and$libresoc.v:42407$1805_Y
+ connect \$1755 $ternary$libresoc.v:42408$1806_Y
+ connect \$1757 $and$libresoc.v:42409$1807_Y
+ connect \$1760 $and$libresoc.v:42410$1808_Y
+ connect \$1763 $not$libresoc.v:42411$1809_Y
+ connect \$1765 $and$libresoc.v:42412$1810_Y
+ connect \$1768 $and$libresoc.v:42413$1811_Y
+ connect \$1771 $ternary$libresoc.v:42414$1812_Y
+ connect \$1773 $or$libresoc.v:42415$1813_Y
+ connect \$1776 $or$libresoc.v:42416$1814_Y
+ connect \$1775 $pos$libresoc.v:42417$1816_Y
+ connect \$1779 $and$libresoc.v:42418$1817_Y
+ connect \$1781 $and$libresoc.v:42419$1818_Y
+ connect \$1784 $and$libresoc.v:42420$1819_Y
+ connect \$1787 $not$libresoc.v:42421$1820_Y
+ connect \$1789 $and$libresoc.v:42422$1821_Y
+ connect \$1792 $and$libresoc.v:42423$1822_Y
+ connect \$1795 $ternary$libresoc.v:42424$1823_Y
+ connect \$1797 $pos$libresoc.v:42425$1825_Y
+ connect \$1799 $and$libresoc.v:42426$1826_Y
+ connect \$1801 $and$libresoc.v:42427$1827_Y
+ connect \$1804 $and$libresoc.v:42428$1828_Y
+ connect \$1807 $not$libresoc.v:42429$1829_Y
+ connect \$1809 $and$libresoc.v:42430$1830_Y
+ connect \$1812 $and$libresoc.v:42431$1831_Y
+ connect \$1815 $ternary$libresoc.v:42432$1832_Y
+ connect \$182 $and$libresoc.v:42433$1833_Y
+ connect \$181 $reduce_or$libresoc.v:42434$1834_Y
+ connect \$186 $and$libresoc.v:42435$1835_Y
+ connect \$185 $reduce_or$libresoc.v:42436$1836_Y
+ connect \$190 $and$libresoc.v:42437$1837_Y
+ connect \$189 $reduce_or$libresoc.v:42438$1838_Y
+ connect \$194 $and$libresoc.v:42439$1839_Y
+ connect \$193 $reduce_or$libresoc.v:42440$1840_Y
+ connect \$198 $and$libresoc.v:42441$1841_Y
+ connect \$197 $reduce_or$libresoc.v:42442$1842_Y
+ connect \$202 $and$libresoc.v:42443$1843_Y
+ connect \$201 $reduce_or$libresoc.v:42444$1844_Y
+ connect \$206 $and$libresoc.v:42445$1845_Y
+ connect \$205 $reduce_or$libresoc.v:42446$1846_Y
+ connect \$210 $and$libresoc.v:42447$1847_Y
+ connect \$209 $reduce_or$libresoc.v:42448$1848_Y
+ connect \$214 $and$libresoc.v:42449$1849_Y
+ connect \$213 $reduce_or$libresoc.v:42450$1850_Y
+ connect \$218 $and$libresoc.v:42451$1851_Y
+ connect \$217 $reduce_or$libresoc.v:42452$1852_Y
+ connect \$221 $ne$libresoc.v:42453$1853_Y
+ connect \$224 $sub$libresoc.v:42454$1854_Y
+ connect \$226 $ne$libresoc.v:42455$1855_Y
+ connect \$229 $and$libresoc.v:42456$1856_Y
+ connect \$231 $and$libresoc.v:42457$1857_Y
+ connect \$233 $eq$libresoc.v:42458$1858_Y
+ connect \$235 $or$libresoc.v:42459$1859_Y
+ connect \$237 $and$libresoc.v:42460$1860_Y
+ connect \$239 $or$libresoc.v:42461$1861_Y
+ connect \$241 $eq$libresoc.v:42462$1862_Y
+ connect \$243 $and$libresoc.v:42463$1863_Y
+ connect \$245 $eq$libresoc.v:42464$1864_Y
+ connect \$247 $or$libresoc.v:42465$1865_Y
+ connect \$228 $not$libresoc.v:42466$1866_Y
+ connect \$250 $not$libresoc.v:42467$1867_Y
+ connect \$252 $not$libresoc.v:42468$1868_Y
+ connect \$254 $not$libresoc.v:42469$1869_Y
+ connect \$257 $and$libresoc.v:42470$1870_Y
+ connect \$259 $and$libresoc.v:42471$1871_Y
+ connect \$261 $eq$libresoc.v:42472$1872_Y
+ connect \$263 $or$libresoc.v:42473$1873_Y
+ connect \$265 $and$libresoc.v:42474$1874_Y
+ connect \$267 $or$libresoc.v:42475$1875_Y
+ connect \$256 $not$libresoc.v:42476$1876_Y
+ connect \$271 $and$libresoc.v:42477$1877_Y
+ connect \$273 $and$libresoc.v:42478$1878_Y
+ connect \$275 $eq$libresoc.v:42479$1879_Y
+ connect \$277 $or$libresoc.v:42480$1880_Y
+ connect \$279 $and$libresoc.v:42481$1881_Y
+ connect \$281 $or$libresoc.v:42482$1882_Y
+ connect \$283 $and$libresoc.v:42483$1883_Y
+ connect \$285 $and$libresoc.v:42484$1884_Y
+ connect \$287 $eq$libresoc.v:42485$1885_Y
+ connect \$289 $or$libresoc.v:42486$1886_Y
+ connect \$291 $eq$libresoc.v:42487$1887_Y
+ connect \$293 $and$libresoc.v:42488$1888_Y
+ connect \$295 $eq$libresoc.v:42489$1889_Y
+ connect \$297 $or$libresoc.v:42490$1890_Y
+ connect \$270 $not$libresoc.v:42491$1891_Y
+ connect \$301 $and$libresoc.v:42492$1892_Y
+ connect \$303 $and$libresoc.v:42493$1893_Y
+ connect \$305 $eq$libresoc.v:42494$1894_Y
+ connect \$307 $or$libresoc.v:42495$1895_Y
+ connect \$309 $and$libresoc.v:42496$1896_Y
+ connect \$311 $or$libresoc.v:42497$1897_Y
+ connect \$300 $not$libresoc.v:42498$1898_Y
+ connect \$315 $and$libresoc.v:42499$1899_Y
+ connect \$317 $and$libresoc.v:42500$1900_Y
+ connect \$319 $eq$libresoc.v:42501$1901_Y
+ connect \$321 $or$libresoc.v:42502$1902_Y
+ connect \$323 $and$libresoc.v:42503$1903_Y
+ connect \$325 $or$libresoc.v:42504$1904_Y
+ connect \$314 $not$libresoc.v:42505$1905_Y
+ connect \$329 $and$libresoc.v:42506$1906_Y
+ connect \$331 $and$libresoc.v:42507$1907_Y
+ connect \$333 $eq$libresoc.v:42508$1908_Y
+ connect \$335 $or$libresoc.v:42509$1909_Y
+ connect \$337 $and$libresoc.v:42510$1910_Y
+ connect \$339 $or$libresoc.v:42511$1911_Y
+ connect \$341 $eq$libresoc.v:42512$1912_Y
+ connect \$343 $and$libresoc.v:42513$1913_Y
+ connect \$345 $eq$libresoc.v:42514$1914_Y
+ connect \$347 $or$libresoc.v:42515$1915_Y
+ connect \$328 $not$libresoc.v:42516$1916_Y
+ connect \$350 $not$libresoc.v:42517$1917_Y
+ connect \$352 $and$libresoc.v:42518$1918_Y
+ connect \$354 $and$libresoc.v:42519$1919_Y
+ connect \$356 $not$libresoc.v:42520$1920_Y
+ connect \$358 $and$libresoc.v:42521$1921_Y
+ connect \$360 $and$libresoc.v:42522$1922_Y
+ connect \$362 $ternary$libresoc.v:42523$1923_Y
+ connect \$364 $and$libresoc.v:42524$1924_Y
+ connect \$366 $and$libresoc.v:42525$1925_Y
+ connect \$368 $not$libresoc.v:42526$1926_Y
+ connect \$370 $and$libresoc.v:42527$1927_Y
+ connect \$372 $and$libresoc.v:42528$1928_Y
+ connect \$374 $ternary$libresoc.v:42529$1929_Y
+ connect \$376 $and$libresoc.v:42530$1930_Y
+ connect \$378 $and$libresoc.v:42531$1931_Y
+ connect \$380 $not$libresoc.v:42532$1932_Y
+ connect \$382 $and$libresoc.v:42533$1933_Y
+ connect \$384 $and$libresoc.v:42534$1934_Y
+ connect \$386 $ternary$libresoc.v:42535$1935_Y
+ connect \$388 $and$libresoc.v:42536$1936_Y
+ connect \$390 $and$libresoc.v:42537$1937_Y
+ connect \$392 $not$libresoc.v:42538$1938_Y
+ connect \$394 $and$libresoc.v:42539$1939_Y
+ connect \$396 $and$libresoc.v:42540$1940_Y
+ connect \$398 $ternary$libresoc.v:42541$1941_Y
+ connect \$400 $and$libresoc.v:42542$1942_Y
+ connect \$402 $and$libresoc.v:42543$1943_Y
+ connect \$404 $not$libresoc.v:42544$1944_Y
+ connect \$406 $and$libresoc.v:42545$1945_Y
+ connect \$408 $and$libresoc.v:42546$1946_Y
+ connect \$410 $ternary$libresoc.v:42547$1947_Y
+ connect \$412 $and$libresoc.v:42548$1948_Y
+ connect \$414 $and$libresoc.v:42549$1949_Y
+ connect \$416 $not$libresoc.v:42550$1950_Y
+ connect \$418 $and$libresoc.v:42551$1951_Y
+ connect \$420 $and$libresoc.v:42552$1952_Y
+ connect \$422 $ternary$libresoc.v:42553$1953_Y
+ connect \$424 $and$libresoc.v:42554$1954_Y
+ connect \$426 $and$libresoc.v:42555$1955_Y
+ connect \$428 $not$libresoc.v:42556$1956_Y
+ connect \$430 $and$libresoc.v:42557$1957_Y
+ connect \$432 $and$libresoc.v:42558$1958_Y
+ connect \$434 $ternary$libresoc.v:42559$1959_Y
+ connect \$436 $and$libresoc.v:42560$1960_Y
+ connect \$438 $and$libresoc.v:42561$1961_Y
+ connect \$440 $not$libresoc.v:42562$1962_Y
+ connect \$442 $and$libresoc.v:42563$1963_Y
+ connect \$444 $and$libresoc.v:42564$1964_Y
+ connect \$446 $ternary$libresoc.v:42565$1965_Y
+ connect \$448 $and$libresoc.v:42566$1966_Y
+ connect \$450 $and$libresoc.v:42567$1967_Y
+ connect \$452 $not$libresoc.v:42568$1968_Y
+ connect \$454 $and$libresoc.v:42569$1969_Y
+ connect \$456 $and$libresoc.v:42570$1970_Y
+ connect \$458 $ternary$libresoc.v:42571$1971_Y
+ connect \$460 $and$libresoc.v:42572$1972_Y
+ connect \$462 $and$libresoc.v:42573$1973_Y
+ connect \$464 $not$libresoc.v:42574$1974_Y
+ connect \$466 $and$libresoc.v:42575$1975_Y
+ connect \$468 $and$libresoc.v:42576$1976_Y
+ connect \$470 $ternary$libresoc.v:42577$1977_Y
+ connect \$472 $and$libresoc.v:42578$1978_Y
+ connect \$474 $and$libresoc.v:42579$1979_Y
+ connect \$476 $not$libresoc.v:42580$1980_Y
+ connect \$478 $and$libresoc.v:42581$1981_Y
+ connect \$480 $and$libresoc.v:42582$1982_Y
+ connect \$482 $ternary$libresoc.v:42583$1983_Y
+ connect \$484 $and$libresoc.v:42584$1984_Y
+ connect \$486 $and$libresoc.v:42585$1985_Y
+ connect \$488 $not$libresoc.v:42586$1986_Y
+ connect \$490 $and$libresoc.v:42587$1987_Y
+ connect \$492 $and$libresoc.v:42588$1988_Y
+ connect \$494 $ternary$libresoc.v:42589$1989_Y
+ connect \$496 $and$libresoc.v:42590$1990_Y
+ connect \$498 $and$libresoc.v:42591$1991_Y
+ connect \$500 $not$libresoc.v:42592$1992_Y
+ connect \$502 $and$libresoc.v:42593$1993_Y
+ connect \$504 $and$libresoc.v:42594$1994_Y
+ connect \$506 $ternary$libresoc.v:42595$1995_Y
+ connect \$508 $and$libresoc.v:42596$1996_Y
+ connect \$510 $and$libresoc.v:42597$1997_Y
+ connect \$512 $not$libresoc.v:42598$1998_Y
+ connect \$514 $and$libresoc.v:42599$1999_Y
+ connect \$516 $and$libresoc.v:42600$2000_Y
+ connect \$518 $ternary$libresoc.v:42601$2001_Y
+ connect \$520 $and$libresoc.v:42602$2002_Y
+ connect \$522 $and$libresoc.v:42603$2003_Y
+ connect \$524 $not$libresoc.v:42604$2004_Y
+ connect \$526 $and$libresoc.v:42605$2005_Y
+ connect \$528 $and$libresoc.v:42606$2006_Y
+ connect \$530 $ternary$libresoc.v:42607$2007_Y
+ connect \$532 $and$libresoc.v:42608$2008_Y
+ connect \$534 $and$libresoc.v:42609$2009_Y
+ connect \$536 $not$libresoc.v:42610$2010_Y
+ connect \$538 $and$libresoc.v:42611$2011_Y
+ connect \$540 $and$libresoc.v:42612$2012_Y
+ connect \$542 $ternary$libresoc.v:42613$2013_Y
+ connect \$544 $and$libresoc.v:42614$2014_Y
+ connect \$546 $and$libresoc.v:42615$2015_Y
+ connect \$548 $not$libresoc.v:42616$2016_Y
+ connect \$550 $and$libresoc.v:42617$2017_Y
+ connect \$552 $and$libresoc.v:42618$2018_Y
+ connect \$554 $ternary$libresoc.v:42619$2019_Y
+ connect \$556 $and$libresoc.v:42620$2020_Y
+ connect \$558 $and$libresoc.v:42621$2021_Y
+ connect \$560 $not$libresoc.v:42622$2022_Y
+ connect \$562 $and$libresoc.v:42623$2023_Y
+ connect \$564 $and$libresoc.v:42624$2024_Y
+ connect \$566 $ternary$libresoc.v:42625$2025_Y
+ connect \$568 $and$libresoc.v:42626$2026_Y
+ connect \$570 $and$libresoc.v:42627$2027_Y
+ connect \$572 $not$libresoc.v:42628$2028_Y
+ connect \$574 $and$libresoc.v:42629$2029_Y
+ connect \$576 $and$libresoc.v:42630$2030_Y
+ connect \$578 $ternary$libresoc.v:42631$2031_Y
+ connect \$581 $or$libresoc.v:42632$2032_Y
+ connect \$583 $or$libresoc.v:42633$2033_Y
+ connect \$585 $or$libresoc.v:42634$2034_Y
+ connect \$587 $or$libresoc.v:42635$2035_Y
+ connect \$589 $or$libresoc.v:42636$2036_Y
+ connect \$591 $or$libresoc.v:42637$2037_Y
+ connect \$593 $or$libresoc.v:42638$2038_Y
+ connect \$595 $or$libresoc.v:42639$2039_Y
+ connect \$597 $or$libresoc.v:42640$2040_Y
+ connect \$599 $or$libresoc.v:42641$2041_Y
+ connect \$601 $or$libresoc.v:42642$2042_Y
+ connect \$603 $or$libresoc.v:42643$2043_Y
+ connect \$605 $or$libresoc.v:42644$2044_Y
+ connect \$607 $or$libresoc.v:42645$2045_Y
+ connect \$609 $or$libresoc.v:42646$2046_Y
+ connect \$611 $or$libresoc.v:42647$2047_Y
+ connect \$613 $or$libresoc.v:42648$2048_Y
+ connect \$615 $or$libresoc.v:42649$2049_Y
+ connect \$617 $reduce_or$libresoc.v:42650$2050_Y
+ connect \$619 $and$libresoc.v:42651$2051_Y
+ connect \$621 $and$libresoc.v:42652$2052_Y
+ connect \$623 $eq$libresoc.v:42653$2053_Y
+ connect \$625 $or$libresoc.v:42654$2054_Y
+ connect \$627 $and$libresoc.v:42655$2055_Y
+ connect \$629 $or$libresoc.v:42656$2056_Y
+ connect \$631 $and$libresoc.v:42657$2057_Y
+ connect \$633 $and$libresoc.v:42658$2058_Y
+ connect \$635 $not$libresoc.v:42659$2059_Y
+ connect \$637 $and$libresoc.v:42660$2060_Y
+ connect \$639 $and$libresoc.v:42661$2061_Y
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+ connect \$643 $and$libresoc.v:42663$2063_Y
+ connect \$645 $and$libresoc.v:42664$2064_Y
+ connect \$647 $not$libresoc.v:42665$2065_Y
+ connect \$649 $and$libresoc.v:42666$2066_Y
+ connect \$651 $and$libresoc.v:42667$2067_Y
+ connect \$653 $ternary$libresoc.v:42668$2068_Y
+ connect \$655 $and$libresoc.v:42669$2069_Y
+ connect \$657 $and$libresoc.v:42670$2070_Y
+ connect \$659 $not$libresoc.v:42671$2071_Y
+ connect \$661 $and$libresoc.v:42672$2072_Y
+ connect \$663 $and$libresoc.v:42673$2073_Y
+ connect \$665 $ternary$libresoc.v:42674$2074_Y
+ connect \$667 $and$libresoc.v:42675$2075_Y
+ connect \$669 $and$libresoc.v:42676$2076_Y
+ connect \$671 $not$libresoc.v:42677$2077_Y
+ connect \$673 $and$libresoc.v:42678$2078_Y
+ connect \$675 $and$libresoc.v:42679$2079_Y
+ connect \$677 $ternary$libresoc.v:42680$2080_Y
+ connect \$679 $and$libresoc.v:42681$2081_Y
+ connect \$681 $and$libresoc.v:42682$2082_Y
+ connect \$683 $not$libresoc.v:42683$2083_Y
+ connect \$685 $and$libresoc.v:42684$2084_Y
+ connect \$687 $and$libresoc.v:42685$2085_Y
+ connect \$689 $ternary$libresoc.v:42686$2086_Y
+ connect \$691 $and$libresoc.v:42687$2087_Y
+ connect \$693 $and$libresoc.v:42688$2088_Y
+ connect \$695 $not$libresoc.v:42689$2089_Y
+ connect \$697 $and$libresoc.v:42690$2090_Y
+ connect \$699 $and$libresoc.v:42691$2091_Y
+ connect \$701 $ternary$libresoc.v:42692$2092_Y
+ connect \$704 $or$libresoc.v:42693$2093_Y
+ connect \$706 $or$libresoc.v:42694$2094_Y
+ connect \$708 $or$libresoc.v:42695$2095_Y
+ connect \$710 $or$libresoc.v:42696$2096_Y
+ connect \$712 $or$libresoc.v:42697$2097_Y
+ connect \$703 $pos$libresoc.v:42698$2099_Y
+ connect \$715 $eq$libresoc.v:42699$2100_Y
+ connect \$717 $and$libresoc.v:42700$2101_Y
+ connect \$719 $eq$libresoc.v:42701$2102_Y
+ connect \$721 $or$libresoc.v:42702$2103_Y
+ connect \$723 $and$libresoc.v:42703$2104_Y
+ connect \$725 $and$libresoc.v:42704$2105_Y
+ connect \$727 $not$libresoc.v:42705$2106_Y
+ connect \$729 $and$libresoc.v:42706$2107_Y
+ connect \$731 $and$libresoc.v:42707$2108_Y
+ connect \$733 $ternary$libresoc.v:42708$2109_Y
+ connect \$735 $and$libresoc.v:42709$2110_Y
+ connect \$737 $and$libresoc.v:42710$2111_Y
+ connect \$739 $not$libresoc.v:42711$2112_Y
+ connect \$741 $and$libresoc.v:42712$2113_Y
+ connect \$743 $and$libresoc.v:42713$2114_Y
+ connect \$745 $ternary$libresoc.v:42714$2115_Y
+ connect \$747 $and$libresoc.v:42715$2116_Y
+ connect \$749 $and$libresoc.v:42716$2117_Y
+ connect \$751 $not$libresoc.v:42717$2118_Y
+ connect \$753 $and$libresoc.v:42718$2119_Y
+ connect \$755 $and$libresoc.v:42719$2120_Y
+ connect \$757 $ternary$libresoc.v:42720$2121_Y
+ connect \$760 $or$libresoc.v:42721$2122_Y
+ connect \$762 $or$libresoc.v:42722$2123_Y
+ connect \$759 $pos$libresoc.v:42723$2125_Y
+ connect \$765 $and$libresoc.v:42724$2126_Y
+ connect \$767 $and$libresoc.v:42725$2127_Y
+ connect \$769 $eq$libresoc.v:42726$2128_Y
+ connect \$771 $or$libresoc.v:42727$2129_Y
+ connect \$773 $and$libresoc.v:42728$2130_Y
+ connect \$775 $and$libresoc.v:42729$2131_Y
+ connect \$777 $not$libresoc.v:42730$2132_Y
+ connect \$779 $and$libresoc.v:42731$2133_Y
+ connect \$781 $and$libresoc.v:42732$2134_Y
+ connect \$783 $ternary$libresoc.v:42733$2135_Y
+ connect \$785 $and$libresoc.v:42734$2136_Y
+ connect \$787 $and$libresoc.v:42735$2137_Y
+ connect \$789 $not$libresoc.v:42736$2138_Y
+ connect \$791 $and$libresoc.v:42737$2139_Y
+ connect \$793 $and$libresoc.v:42738$2140_Y
+ connect \$795 $ternary$libresoc.v:42739$2141_Y
+ connect \$797 $and$libresoc.v:42740$2142_Y
+ connect \$799 $and$libresoc.v:42741$2143_Y
+ connect \$801 $not$libresoc.v:42742$2144_Y
+ connect \$803 $and$libresoc.v:42743$2145_Y
+ connect \$805 $and$libresoc.v:42744$2146_Y
+ connect \$807 $sub$libresoc.v:42745$2147_Y
+ connect \$809 $sshl$libresoc.v:42746$2148_Y
+ connect \$811 $ternary$libresoc.v:42747$2149_Y
+ connect \$813 $and$libresoc.v:42748$2150_Y
+ connect \$815 $and$libresoc.v:42749$2151_Y
+ connect \$817 $not$libresoc.v:42750$2152_Y
+ connect \$819 $and$libresoc.v:42751$2153_Y
+ connect \$821 $and$libresoc.v:42752$2154_Y
+ connect \$823 $sub$libresoc.v:42753$2155_Y
+ connect \$825 $sshl$libresoc.v:42754$2156_Y
+ connect \$827 $ternary$libresoc.v:42755$2157_Y
+ connect \$830 $or$libresoc.v:42756$2158_Y
+ connect \$832 $and$libresoc.v:42757$2159_Y
+ connect \$834 $and$libresoc.v:42758$2160_Y
+ connect \$836 $not$libresoc.v:42759$2161_Y
+ connect \$838 $and$libresoc.v:42760$2162_Y
+ connect \$840 $and$libresoc.v:42761$2163_Y
+ connect \$842 $sub$libresoc.v:42762$2164_Y
+ connect \$844 $sshl$libresoc.v:42763$2165_Y
+ connect \$846 $ternary$libresoc.v:42764$2166_Y
+ connect \$848 $and$libresoc.v:42765$2167_Y
+ connect \$850 $and$libresoc.v:42766$2168_Y
+ connect \$852 $not$libresoc.v:42767$2169_Y
+ connect \$854 $and$libresoc.v:42768$2170_Y
+ connect \$856 $and$libresoc.v:42769$2171_Y
+ connect \$858 $sub$libresoc.v:42770$2172_Y
+ connect \$860 $sshl$libresoc.v:42771$2173_Y
+ connect \$862 $ternary$libresoc.v:42772$2174_Y
+ connect \$864 $and$libresoc.v:42773$2175_Y
+ connect \$866 $and$libresoc.v:42774$2176_Y
+ connect \$868 $not$libresoc.v:42775$2177_Y
+ connect \$870 $and$libresoc.v:42776$2178_Y
+ connect \$872 $and$libresoc.v:42777$2179_Y
+ connect \$874 $ternary$libresoc.v:42778$2180_Y
+ connect \$876 $and$libresoc.v:42779$2181_Y
+ connect \$878 $and$libresoc.v:42780$2182_Y
+ connect \$880 $not$libresoc.v:42781$2183_Y
+ connect \$882 $and$libresoc.v:42782$2184_Y
+ connect \$884 $and$libresoc.v:42783$2185_Y
+ connect \$886 $ternary$libresoc.v:42784$2186_Y
+ connect \$888 $and$libresoc.v:42785$2187_Y
+ connect \$890 $and$libresoc.v:42786$2188_Y
+ connect \$892 $not$libresoc.v:42787$2189_Y
+ connect \$894 $and$libresoc.v:42788$2190_Y
+ connect \$896 $and$libresoc.v:42789$2191_Y
+ connect \$898 $ternary$libresoc.v:42790$2192_Y
+ connect \$900 $and$libresoc.v:42791$2193_Y
+ connect \$902 $and$libresoc.v:42792$2194_Y
+ connect \$904 $not$libresoc.v:42793$2195_Y
+ connect \$906 $and$libresoc.v:42794$2196_Y
+ connect \$908 $and$libresoc.v:42795$2197_Y
+ connect \$910 $ternary$libresoc.v:42796$2198_Y
+ connect \$912 $and$libresoc.v:42797$2199_Y
+ connect \$914 $and$libresoc.v:42798$2200_Y
+ connect \$916 $not$libresoc.v:42799$2201_Y
+ connect \$918 $and$libresoc.v:42800$2202_Y
+ connect \$920 $and$libresoc.v:42801$2203_Y
+ connect \$922 $ternary$libresoc.v:42802$2204_Y
+ connect \$924 $or$libresoc.v:42803$2205_Y
+ connect \$926 $or$libresoc.v:42804$2206_Y
+ connect \$928 $or$libresoc.v:42805$2207_Y
+ connect \$930 $or$libresoc.v:42806$2208_Y
+ connect \$932 $reduce_or$libresoc.v:42807$2209_Y
+ connect \$934 $and$libresoc.v:42808$2210_Y
+ connect \$936 $and$libresoc.v:42809$2211_Y
+ connect \$938 $not$libresoc.v:42810$2212_Y
+ connect \$940 $and$libresoc.v:42811$2213_Y
+ connect \$942 $and$libresoc.v:42812$2214_Y
+ connect \$944 $ternary$libresoc.v:42813$2215_Y
+ connect \$946 $reduce_or$libresoc.v:42814$2216_Y
+ connect \$948 $and$libresoc.v:42815$2217_Y
+ connect \$950 $and$libresoc.v:42816$2218_Y
+ connect \$952 $and$libresoc.v:42817$2219_Y
+ connect \$954 $and$libresoc.v:42818$2220_Y
+ connect \$956 $and$libresoc.v:42819$2221_Y
+ connect \$958 $and$libresoc.v:42820$2222_Y
+ connect \$960 $and$libresoc.v:42821$2223_Y
+ connect \$962 $and$libresoc.v:42822$2224_Y
+ connect \$964 $and$libresoc.v:42823$2225_Y
+ connect \$966 $and$libresoc.v:42824$2226_Y
+ connect \$968 $and$libresoc.v:42825$2227_Y
+ connect \$970 $and$libresoc.v:42826$2228_Y
+ connect \$972 $not$libresoc.v:42827$2229_Y
+ connect \$974 $and$libresoc.v:42828$2230_Y
+ connect \$980 $and$libresoc.v:42829$2231_Y
+ connect \$982 $ternary$libresoc.v:42830$2232_Y
+ connect \$984 $and$libresoc.v:42831$2233_Y
+ connect \$987 $and$libresoc.v:42832$2234_Y
+ connect \$991 $not$libresoc.v:42833$2235_Y
+ connect \$993 $and$libresoc.v:42834$2236_Y
+ connect \$998 $and$libresoc.v:42835$2237_Y
connect \$223 \$224
- connect \$460 \$475
- connect \$575 \$588
- connect \$616 \$617
- connect \$831 \$832
- connect \$1159 \$1176
- connect \$1178 \$1195
- connect \$1375 \$1384
+ connect \$580 \$615
+ connect \$829 \$830
+ connect \$1157 \$1174
+ connect \$1176 \$1193
+ connect \$1373 \$1382
connect \o_ok 1'0
connect \ea_ok 1'0
- connect \spr_spr1__wen \wp$1813
- connect \spr_spr1__addr$175 \addr_en$1816 [6:0]
+ connect \spr_spr1__wen \wp$1811
+ connect \spr_spr1__addr$175 \addr_en$1814 [6:0]
connect \spr_spr1__data_i \fus_dest2_o$162
- connect \addr_en$1816 \$1817
- connect \wp$1813 \$1814
- connect \wr_pick_rise$1059 \$1811
- connect \wr_pick$1805 \$1806
- connect \wrpick_SPR_spr1_i \$1803
- connect \wrflag_spr0_spr1_1 \$1801
- connect \state_wen \$1799
+ connect \addr_en$1814 \$1815
+ connect \wp$1811 \$1812
+ connect \wr_pick_rise$1057 \$1809
+ connect \wr_pick$1803 \$1804
+ connect \wrpick_SPR_spr1_i \$1801
+ connect \wrflag_spr0_spr1_1 \$1799
+ connect \state_wen \$1797
connect \state_data_i$174 \fus_dest5_o$161
- connect \addr_en$1796 \$1797
- connect \wp$1793 \$1794
- connect \wr_pick_rise$1019 \$1791
- connect \wr_pick$1785 \$1786
- connect \wrpick_STATE_msr_i \$1783
- connect \wrflag_trap0_msr_4 \$1781
- connect \state_nia_wen \$1777
- connect \state_data_i \$1775
- connect \addr_en$1772 \$1773
- connect \wp$1769 \$1770
- connect \wr_pick_rise$1018 \$1767
- connect \wr_pick$1761 \$1762
- connect \wrflag_trap0_nia_3 \$1759
- connect \addr_en$1756 \$1757
- connect \wp$1753 \$1754
- connect \wr_pick_rise$1644 \$1751
- connect \wr_pick$1745 \$1746
- connect \wrpick_STATE_nia_i [1] \$1743
- connect \wrpick_STATE_nia_i [0] \$1741
- connect \wrflag_branch0_nia_2 \$1739
- connect \fast_dest1__wen \$1737
- connect \fast_dest1__addr \$1729
- connect \fast_dest1__data_i \$1721
- connect \addr_en$1712 \$1713
- connect \wp$1709 \$1710
- connect \wr_pick_rise$1017 \$1707
- connect \wr_pick$1701 \$1702
- connect \wrflag_trap0_fast1_2 \$1699
- connect \addr_en$1696 \$1697
- connect \wp$1693 \$1694
- connect \wr_pick_rise$1643 \$1691
- connect \wr_pick$1685 \$1686
- connect \wrflag_branch0_fast1_1 \$1683
- connect \addr_en$1680 \$1681
- connect \wp$1677 \$1678
- connect \wr_pick_rise$1058 \$1675
- connect \wr_pick$1669 \$1670
- connect \wrflag_spr0_fast1_2 \$1667
- connect \addr_en$1664 \$1665
- connect \wp$1661 \$1662
- connect \wr_pick_rise$1016 \$1659
- connect \wr_pick$1653 \$1654
- connect \wrflag_trap0_fast1_1 \$1651
- connect \addr_en$1648 \$1649
- connect \wp$1645 \$1646
- connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1644
- connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1643
- connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1638
- connect \wr_pick_rise$1638 \$1641
- connect \wr_pick$1634 \$1635
- connect \wrpick_FAST_fast1_i [4] \$1632
- connect \wrpick_FAST_fast1_i [3] \$1630
- connect \wrpick_FAST_fast1_i [2] \$1628
- connect \wrpick_FAST_fast1_i [1] \$1626
- connect \wrpick_FAST_fast1_i [0] \$1624
- connect \wrflag_branch0_fast1_0 \$1622
- connect \xer_wen$173 \$1614
- connect \xer_data_i$172 \$1606
- connect \addr_en$1603 \$1604
- connect \wp$1600 \$1601
- connect \wr_pick_rise$1099 \$1598
- connect \wr_pick$1592 \$1593
- connect \wrflag_mul0_xer_so_3 \$1590
- connect \addr_en$1587 \$1588
- connect \wp$1584 \$1585
- connect \wr_pick_rise$1079 \$1582
- connect \wr_pick$1576 \$1577
- connect \wrflag_div0_xer_so_3 \$1574
- connect \addr_en$1571 \$1572
- connect \wp$1568 \$1569
- connect \wr_pick_rise$1057 \$1566
- connect \wr_pick$1560 \$1561
- connect \wrflag_spr0_xer_so_3 \$1558
- connect \addr_en$1555 \$1556
- connect \wp$1552 \$1553
- connect \wr_pick_rise$981 \$1550
- connect \wr_pick$1544 \$1545
- connect \wrpick_XER_xer_so_i [3] \$1542
- connect \wrpick_XER_xer_so_i [2] \$1540
- connect \wrpick_XER_xer_so_i [1] \$1538
- connect \wrpick_XER_xer_so_i [0] \$1536
- connect \wrflag_alu0_xer_so_4 \$1534
- connect \xer_wen$171 \$1532
- connect \xer_data_i$170 \$1526
- connect \addr_en$1519 \$1520
- connect \wp$1516 \$1517
- connect \wr_pick_rise$1098 \$1514
- connect \wr_pick$1508 \$1509
- connect \wrflag_mul0_xer_ov_2 \$1506
- connect \addr_en$1503 \$1504
- connect \wp$1500 \$1501
- connect \wr_pick_rise$1078 \$1498
- connect \wr_pick$1492 \$1493
- connect \wrflag_div0_xer_ov_2 \$1490
- connect \addr_en$1487 \$1488
- connect \wp$1484 \$1485
- connect \wr_pick_rise$1056 \$1482
- connect \wr_pick$1476 \$1477
- connect \wrflag_spr0_xer_ov_4 \$1474
- connect \addr_en$1471 \$1472
- connect \wp$1468 \$1469
- connect \wr_pick_rise$980 \$1466
- connect \wr_pick$1460 \$1461
- connect \wrpick_XER_xer_ov_i [3] \$1458
- connect \wrpick_XER_xer_ov_i [2] \$1456
- connect \wrpick_XER_xer_ov_i [1] \$1454
- connect \wrpick_XER_xer_ov_i [0] \$1452
- connect \wrflag_alu0_xer_ov_3 \$1450
- connect \xer_wen \$1444
- connect \xer_data_i \$1442
- connect \addr_en$1437 \$1438
- connect \wp$1434 \$1435
- connect \wr_pick_rise$1118 \$1432
- connect \wr_pick$1426 \$1427
- connect \wrflag_shiftrot0_xer_ca_2 \$1424
- connect \addr_en$1421 \$1422
- connect \wp$1418 \$1419
- connect \wr_pick_rise$1055 \$1416
- connect \wr_pick$1410 \$1411
- connect \wrflag_spr0_xer_ca_5 \$1408
- connect \addr_en$1405 \$1406
- connect \wp$1402 \$1403
- connect \wr_pick_rise$979 \$1400
- connect \wr_pick$1394 \$1395
- connect \wrpick_XER_xer_ca_i [2] \$1392
- connect \wrpick_XER_xer_ca_i [1] \$1390
- connect \wrpick_XER_xer_ca_i [0] \$1388
- connect \wrflag_alu0_xer_ca_2 \$1386
- connect \cr_wen \$1384 [7:0]
- connect \cr_data_i \$1373
- connect \addr_en$1358 \$1363
- connect \wp$1355 \$1356
- connect \wr_pick_rise$1117 \$1353
- connect \wr_pick$1347 \$1348
- connect \wrflag_shiftrot0_cr_a_1 \$1345
- connect \addr_en$1338 \$1343
- connect \wp$1335 \$1336
- connect \wr_pick_rise$1097 \$1333
- connect \wr_pick$1327 \$1328
- connect \wrflag_mul0_cr_a_1 \$1325
- connect \addr_en$1318 \$1323
- connect \wp$1315 \$1316
- connect \wr_pick_rise$1077 \$1313
- connect \wr_pick$1307 \$1308
- connect \wrflag_div0_cr_a_1 \$1305
- connect \addr_en$1298 \$1303
- connect \wp$1295 \$1296
- connect \wr_pick_rise$1037 \$1293
- connect \wr_pick$1287 \$1288
- connect \wrflag_logical0_cr_a_1 \$1285
- connect \addr_en$1278 \$1283
- connect \wp$1275 \$1276
- connect \wr_pick_rise$998 \$1273
- connect \wr_pick$1267 \$1268
- connect \wrflag_cr0_cr_a_2 \$1265
- connect \addr_en$1258 \$1263
- connect \wp$1255 \$1256
- connect \wr_pick_rise$978 \$1253
- connect \wr_pick$1247 \$1248
- connect \wrpick_CR_cr_a_i [5] \$1245
- connect \wrpick_CR_cr_a_i [4] \$1243
- connect \wrpick_CR_cr_a_i [3] \$1241
- connect \wrpick_CR_cr_a_i [2] \$1239
- connect \wrpick_CR_cr_a_i [1] \$1237
- connect \wrpick_CR_cr_a_i [0] \$1235
- connect \wrflag_alu0_cr_a_1 \$1233
- connect \cr_full_wr__wen \addr_en$1230
+ connect \addr_en$1794 \$1795
+ connect \wp$1791 \$1792
+ connect \wr_pick_rise$1017 \$1789
+ connect \wr_pick$1783 \$1784
+ connect \wrpick_STATE_msr_i \$1781
+ connect \wrflag_trap0_msr_4 \$1779
+ connect \state_nia_wen \$1775
+ connect \state_data_i \$1773
+ connect \addr_en$1770 \$1771
+ connect \wp$1767 \$1768
+ connect \wr_pick_rise$1016 \$1765
+ connect \wr_pick$1759 \$1760
+ connect \wrflag_trap0_nia_3 \$1757
+ connect \addr_en$1754 \$1755
+ connect \wp$1751 \$1752
+ connect \wr_pick_rise$1642 \$1749
+ connect \wr_pick$1743 \$1744
+ connect \wrpick_STATE_nia_i [1] \$1741
+ connect \wrpick_STATE_nia_i [0] \$1739
+ connect \wrflag_branch0_nia_2 \$1737
+ connect \fast_dest1__wen \$1735
+ connect \fast_dest1__addr \$1727
+ connect \fast_dest1__data_i \$1719
+ connect \addr_en$1710 \$1711
+ connect \wp$1707 \$1708
+ connect \wr_pick_rise$1015 \$1705
+ connect \wr_pick$1699 \$1700
+ connect \wrflag_trap0_fast1_2 \$1697
+ connect \addr_en$1694 \$1695
+ connect \wp$1691 \$1692
+ connect \wr_pick_rise$1641 \$1689
+ connect \wr_pick$1683 \$1684
+ connect \wrflag_branch0_fast1_1 \$1681
+ connect \addr_en$1678 \$1679
+ connect \wp$1675 \$1676
+ connect \wr_pick_rise$1056 \$1673
+ connect \wr_pick$1667 \$1668
+ connect \wrflag_spr0_fast1_2 \$1665
+ connect \addr_en$1662 \$1663
+ connect \wp$1659 \$1660
+ connect \wr_pick_rise$1014 \$1657
+ connect \wr_pick$1651 \$1652
+ connect \wrflag_trap0_fast1_1 \$1649
+ connect \addr_en$1646 \$1647
+ connect \wp$1643 \$1644
+ connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1642
+ connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1641
+ connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1636
+ connect \wr_pick_rise$1636 \$1639
+ connect \wr_pick$1632 \$1633
+ connect \wrpick_FAST_fast1_i [4] \$1630
+ connect \wrpick_FAST_fast1_i [3] \$1628
+ connect \wrpick_FAST_fast1_i [2] \$1626
+ connect \wrpick_FAST_fast1_i [1] \$1624
+ connect \wrpick_FAST_fast1_i [0] \$1622
+ connect \wrflag_branch0_fast1_0 \$1620
+ connect \xer_wen$173 \$1612
+ connect \xer_data_i$172 \$1604
+ connect \addr_en$1601 \$1602
+ connect \wp$1598 \$1599
+ connect \wr_pick_rise$1097 \$1596
+ connect \wr_pick$1590 \$1591
+ connect \wrflag_mul0_xer_so_3 \$1588
+ connect \addr_en$1585 \$1586
+ connect \wp$1582 \$1583
+ connect \wr_pick_rise$1077 \$1580
+ connect \wr_pick$1574 \$1575
+ connect \wrflag_div0_xer_so_3 \$1572
+ connect \addr_en$1569 \$1570
+ connect \wp$1566 \$1567
+ connect \wr_pick_rise$1055 \$1564
+ connect \wr_pick$1558 \$1559
+ connect \wrflag_spr0_xer_so_3 \$1556
+ connect \addr_en$1553 \$1554
+ connect \wp$1550 \$1551
+ connect \wr_pick_rise$979 \$1548
+ connect \wr_pick$1542 \$1543
+ connect \wrpick_XER_xer_so_i [3] \$1540
+ connect \wrpick_XER_xer_so_i [2] \$1538
+ connect \wrpick_XER_xer_so_i [1] \$1536
+ connect \wrpick_XER_xer_so_i [0] \$1534
+ connect \wrflag_alu0_xer_so_4 \$1532
+ connect \xer_wen$171 \$1530
+ connect \xer_data_i$170 \$1524
+ connect \addr_en$1517 \$1518
+ connect \wp$1514 \$1515
+ connect \wr_pick_rise$1096 \$1512
+ connect \wr_pick$1506 \$1507
+ connect \wrflag_mul0_xer_ov_2 \$1504
+ connect \addr_en$1501 \$1502
+ connect \wp$1498 \$1499
+ connect \wr_pick_rise$1076 \$1496
+ connect \wr_pick$1490 \$1491
+ connect \wrflag_div0_xer_ov_2 \$1488
+ connect \addr_en$1485 \$1486
+ connect \wp$1482 \$1483
+ connect \wr_pick_rise$1054 \$1480
+ connect \wr_pick$1474 \$1475
+ connect \wrflag_spr0_xer_ov_4 \$1472
+ connect \addr_en$1469 \$1470
+ connect \wp$1466 \$1467
+ connect \wr_pick_rise$978 \$1464
+ connect \wr_pick$1458 \$1459
+ connect \wrpick_XER_xer_ov_i [3] \$1456
+ connect \wrpick_XER_xer_ov_i [2] \$1454
+ connect \wrpick_XER_xer_ov_i [1] \$1452
+ connect \wrpick_XER_xer_ov_i [0] \$1450
+ connect \wrflag_alu0_xer_ov_3 \$1448
+ connect \xer_wen \$1442
+ connect \xer_data_i \$1440
+ connect \addr_en$1435 \$1436
+ connect \wp$1432 \$1433
+ connect \wr_pick_rise$1116 \$1430
+ connect \wr_pick$1424 \$1425
+ connect \wrflag_shiftrot0_xer_ca_2 \$1422
+ connect \addr_en$1419 \$1420
+ connect \wp$1416 \$1417
+ connect \wr_pick_rise$1053 \$1414
+ connect \wr_pick$1408 \$1409
+ connect \wrflag_spr0_xer_ca_5 \$1406
+ connect \addr_en$1403 \$1404
+ connect \wp$1400 \$1401
+ connect \wr_pick_rise$977 \$1398
+ connect \wr_pick$1392 \$1393
+ connect \wrpick_XER_xer_ca_i [2] \$1390
+ connect \wrpick_XER_xer_ca_i [1] \$1388
+ connect \wrpick_XER_xer_ca_i [0] \$1386
+ connect \wrflag_alu0_xer_ca_2 \$1384
+ connect \cr_wen \$1382 [7:0]
+ connect \cr_data_i \$1371
+ connect \addr_en$1356 \$1361
+ connect \wp$1353 \$1354
+ connect \wr_pick_rise$1115 \$1351
+ connect \wr_pick$1345 \$1346
+ connect \wrflag_shiftrot0_cr_a_1 \$1343
+ connect \addr_en$1336 \$1341
+ connect \wp$1333 \$1334
+ connect \wr_pick_rise$1095 \$1331
+ connect \wr_pick$1325 \$1326
+ connect \wrflag_mul0_cr_a_1 \$1323
+ connect \addr_en$1316 \$1321
+ connect \wp$1313 \$1314
+ connect \wr_pick_rise$1075 \$1311
+ connect \wr_pick$1305 \$1306
+ connect \wrflag_div0_cr_a_1 \$1303
+ connect \addr_en$1296 \$1301
+ connect \wp$1293 \$1294
+ connect \wr_pick_rise$1035 \$1291
+ connect \wr_pick$1285 \$1286
+ connect \wrflag_logical0_cr_a_1 \$1283
+ connect \addr_en$1276 \$1281
+ connect \wp$1273 \$1274
+ connect \wr_pick_rise$996 \$1271
+ connect \wr_pick$1265 \$1266
+ connect \wrflag_cr0_cr_a_2 \$1263
+ connect \addr_en$1256 \$1261
+ connect \wp$1253 \$1254
+ connect \wr_pick_rise$976 \$1251
+ connect \wr_pick$1245 \$1246
+ connect \wrpick_CR_cr_a_i [5] \$1243
+ connect \wrpick_CR_cr_a_i [4] \$1241
+ connect \wrpick_CR_cr_a_i [3] \$1239
+ connect \wrpick_CR_cr_a_i [2] \$1237
+ connect \wrpick_CR_cr_a_i [1] \$1235
+ connect \wrpick_CR_cr_a_i [0] \$1233
+ connect \wrflag_alu0_cr_a_1 \$1231
+ connect \cr_full_wr__wen \addr_en$1228
connect \cr_full_wr__data_i \fus_dest2_o
- connect \addr_en$1230 \$1231
- connect \wp$1227 \$1228
- connect \wr_pick_rise$997 \$1225
- connect \wr_pick$1219 \$1220
- connect \wrpick_CR_full_cr_i \$1217
- connect \wrflag_cr0_full_cr_1 \$1215
- connect \int_dest1__wen \$1213
- connect \int_dest1__addr \$1195 [4:0]
- connect \int_dest1__data_i \$1176 [63:0]
- connect \addr_en$1156 \$1157
- connect \wp$1153 \$1154
- connect \wr_pick_rise$1136 \$1151
- connect \wr_pick$1145 \$1146
- connect \wrflag_ldst0_o_1 \$1143
- connect \addr_en$1140 \$1141
- connect \wp$1137 \$1138
- connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1136
- connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1131
- connect \wr_pick_rise$1131 \$1134
- connect \wr_pick$1127 \$1128
- connect \wrflag_ldst0_o_0 \$1125
- connect \addr_en$1122 \$1123
- connect \wp$1119 \$1120
- connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1118
- connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1117
- connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1112
- connect \wr_pick_rise$1112 \$1115
- connect \wr_pick$1108 \$1109
- connect \wrflag_shiftrot0_o_0 \$1106
- connect \addr_en$1103 \$1104
- connect \wp$1100 \$1101
- connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1099
- connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1098
- connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1097
- connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1092
- connect \wr_pick_rise$1092 \$1095
- connect \wr_pick$1088 \$1089
- connect \wrflag_mul0_o_0 \$1086
- connect \addr_en$1083 \$1084
- connect \wp$1080 \$1081
- connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1079
- connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1078
- connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1077
- connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1072
- connect \wr_pick_rise$1072 \$1075
- connect \wr_pick$1068 \$1069
- connect \wrflag_div0_o_0 \$1066
- connect \addr_en$1063 \$1064
- connect \wp$1060 \$1061
- connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1059
- connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1058
- connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1057
- connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1056
- connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1055
- connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1050
- connect \wr_pick_rise$1050 \$1053
- connect \wr_pick$1046 \$1047
- connect \wrflag_spr0_o_0 \$1044
- connect \addr_en$1041 \$1042
- connect \wp$1038 \$1039
- connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1037
- connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1032
- connect \wr_pick_rise$1032 \$1035
- connect \wr_pick$1028 \$1029
- connect \wrflag_logical0_o_0 \$1026
- connect \addr_en$1023 \$1024
- connect \wp$1020 \$1021
- connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1019
- connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1018
- connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1017
- connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1016
- connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1011
- connect \wr_pick_rise$1011 \$1014
- connect \wr_pick$1007 \$1008
- connect \wrflag_trap0_o_0 \$1005
- connect \addr_en$1002 \$1003
- connect \wp$999 \$1000
- connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$998
- connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$997
- connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$992
- connect \wr_pick_rise$992 \$995
- connect \wr_pick$988 \$989
- connect \wrflag_cr0_o_0 \$986
- connect \addr_en \$984
- connect \wp \$982
- connect \fus_cu_wr__go_i [4] \wr_pick_rise$981
- connect \fus_cu_wr__go_i [3] \wr_pick_rise$980
- connect \fus_cu_wr__go_i [2] \wr_pick_rise$979
- connect \fus_cu_wr__go_i [1] \wr_pick_rise$978
+ connect \addr_en$1228 \$1229
+ connect \wp$1225 \$1226
+ connect \wr_pick_rise$995 \$1223
+ connect \wr_pick$1217 \$1218
+ connect \wrpick_CR_full_cr_i \$1215
+ connect \wrflag_cr0_full_cr_1 \$1213
+ connect \int_dest1__wen \$1211
+ connect \int_dest1__addr \$1193 [4:0]
+ connect \int_dest1__data_i \$1174 [63:0]
+ connect \addr_en$1154 \$1155
+ connect \wp$1151 \$1152
+ connect \wr_pick_rise$1134 \$1149
+ connect \wr_pick$1143 \$1144
+ connect \wrflag_ldst0_o_1 \$1141
+ connect \addr_en$1138 \$1139
+ connect \wp$1135 \$1136
+ connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1134
+ connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1129
+ connect \wr_pick_rise$1129 \$1132
+ connect \wr_pick$1125 \$1126
+ connect \wrflag_ldst0_o_0 \$1123
+ connect \addr_en$1120 \$1121
+ connect \wp$1117 \$1118
+ connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1116
+ connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1115
+ connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1110
+ connect \wr_pick_rise$1110 \$1113
+ connect \wr_pick$1106 \$1107
+ connect \wrflag_shiftrot0_o_0 \$1104
+ connect \addr_en$1101 \$1102
+ connect \wp$1098 \$1099
+ connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1097
+ connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1096
+ connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1095
+ connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1090
+ connect \wr_pick_rise$1090 \$1093
+ connect \wr_pick$1086 \$1087
+ connect \wrflag_mul0_o_0 \$1084
+ connect \addr_en$1081 \$1082
+ connect \wp$1078 \$1079
+ connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1077
+ connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1076
+ connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1075
+ connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1070
+ connect \wr_pick_rise$1070 \$1073
+ connect \wr_pick$1066 \$1067
+ connect \wrflag_div0_o_0 \$1064
+ connect \addr_en$1061 \$1062
+ connect \wp$1058 \$1059
+ connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1057
+ connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1056
+ connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1055
+ connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1054
+ connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1053
+ connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1048
+ connect \wr_pick_rise$1048 \$1051
+ connect \wr_pick$1044 \$1045
+ connect \wrflag_spr0_o_0 \$1042
+ connect \addr_en$1039 \$1040
+ connect \wp$1036 \$1037
+ connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1035
+ connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1030
+ connect \wr_pick_rise$1030 \$1033
+ connect \wr_pick$1026 \$1027
+ connect \wrflag_logical0_o_0 \$1024
+ connect \addr_en$1021 \$1022
+ connect \wp$1018 \$1019
+ connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1017
+ connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1016
+ connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1015
+ connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1014
+ connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1009
+ connect \wr_pick_rise$1009 \$1012
+ connect \wr_pick$1005 \$1006
+ connect \wrflag_trap0_o_0 \$1003
+ connect \addr_en$1000 \$1001
+ connect \wp$997 \$998
+ connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$996
+ connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$995
+ connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$990
+ connect \wr_pick_rise$990 \$993
+ connect \wr_pick$986 \$987
+ connect \wrflag_cr0_o_0 \$984
+ connect \addr_en \$982
+ connect \wp \$980
+ connect \fus_cu_wr__go_i [4] \wr_pick_rise$979
+ connect \fus_cu_wr__go_i [3] \wr_pick_rise$978
+ connect \fus_cu_wr__go_i [2] \wr_pick_rise$977
+ connect \fus_cu_wr__go_i [1] \wr_pick_rise$976
connect \fus_cu_wr__go_i [0] \wr_pick_rise
- connect \wr_pick_rise \$976
- connect \wr_pick \$972
- connect \wrpick_INT_o_i [9] \$970
- connect \wrpick_INT_o_i [8] \$968
- connect \wrpick_INT_o_i [7] \$966
- connect \wrpick_INT_o_i [6] \$964
- connect \wrpick_INT_o_i [5] \$962
- connect \wrpick_INT_o_i [4] \$960
- connect \wrpick_INT_o_i [3] \$958
- connect \wrpick_INT_o_i [2] \$956
- connect \wrpick_INT_o_i [1] \$954
- connect \wrpick_INT_o_i [0] \$952
- connect \wrflag_alu0_o_0 \$950
- connect \spr_spr1__ren \$948
+ connect \wr_pick_rise \$974
+ connect \wr_pick \$970
+ connect \wrpick_INT_o_i [9] \$968
+ connect \wrpick_INT_o_i [8] \$966
+ connect \wrpick_INT_o_i [7] \$964
+ connect \wrpick_INT_o_i [6] \$962
+ connect \wrpick_INT_o_i [5] \$960
+ connect \wrpick_INT_o_i [4] \$958
+ connect \wrpick_INT_o_i [3] \$956
+ connect \wrpick_INT_o_i [2] \$954
+ connect \wrpick_INT_o_i [1] \$952
+ connect \wrpick_INT_o_i [0] \$950
+ connect \wrflag_alu0_o_0 \$948
+ connect \spr_spr1__ren \$946
connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0]
- connect \addr_en_SPR_spr1_spr0_0 \$946
- connect \rp_SPR_spr1_spr0_0 \$944
+ connect \addr_en_SPR_spr1_spr0_0 \$944
+ connect \rp_SPR_spr1_spr0_0 \$942
connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0
- connect \pick_SPR_spr1_spr0_0 \$942
+ connect \pick_SPR_spr1_spr0_0 \$940
connect \rdflag_SPR_spr1_0 \core_spr1_ok
- connect \fast_src2__ren \$934
- connect \fast_src2__addr \$932
- connect \addr_en_FAST_fast2_trap0_1 \$930
- connect \rp_FAST_fast2_trap0_1 \$928
- connect \pick_FAST_fast2_trap0_1 \$926
- connect \addr_en_FAST_fast2_branch0_0 \$918
- connect \rp_FAST_fast2_branch0_0 \$916
- connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1
- connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0
- connect \pick_FAST_fast2_branch0_0 \$914
- connect \rdflag_FAST_fast2_0 \core_fast2_ok
- connect \fast_src1__ren \$906
- connect \fast_src1__addr \$904
- connect \addr_en_FAST_fast1_spr0_2 \$900
- connect \rp_FAST_fast1_spr0_2 \$898
- connect \pick_FAST_fast1_spr0_2 \$896
- connect \addr_en_FAST_fast1_trap0_1 \$888
- connect \rp_FAST_fast1_trap0_1 \$886
- connect \pick_FAST_fast1_trap0_1 \$884
- connect \addr_en_FAST_fast1_branch0_0 \$876
- connect \rp_FAST_fast1_branch0_0 \$874
+ connect \fast_src1__ren \$932
+ connect \fast_src1__addr \$930
+ connect \addr_en_FAST_fast1_trap0_4 \$922
+ connect \rp_FAST_fast1_trap0_4 \$920
+ connect \pick_FAST_fast1_trap0_4 \$918
+ connect \addr_en_FAST_fast1_branch0_3 \$910
+ connect \rp_FAST_fast1_branch0_3 \$908
+ connect \pick_FAST_fast1_branch0_3 \$906
+ connect \addr_en_FAST_fast1_spr0_2 \$898
+ connect \rp_FAST_fast1_spr0_2 \$896
+ connect \pick_FAST_fast1_spr0_2 \$894
+ connect \addr_en_FAST_fast1_trap0_1 \$886
+ connect \rp_FAST_fast1_trap0_1 \$884
+ connect \pick_FAST_fast1_trap0_1 \$882
+ connect \addr_en_FAST_fast1_branch0_0 \$874
+ connect \rp_FAST_fast1_branch0_0 \$872
+ connect \rdpick_FAST_fast1_i [4] \pick_FAST_fast1_trap0_4
+ connect \rdpick_FAST_fast1_i [3] \pick_FAST_fast1_branch0_3
connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2
connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1
connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0
- connect \pick_FAST_fast1_branch0_0 \$872
+ connect \pick_FAST_fast1_branch0_0 \$870
+ connect \rdflag_FAST_fast1_1 \core_fast2_ok
connect \rdflag_FAST_fast1_0 \core_fast1_ok
connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0]
- connect \addr_en_CR_cr_c_cr0_0 \$864
- connect \rp_CR_cr_c_cr0_0 \$858
+ connect \addr_en_CR_cr_c_cr0_0 \$862
+ connect \rp_CR_cr_c_cr0_0 \$856
connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0
- connect \pick_CR_cr_c_cr0_0 \$856
+ connect \pick_CR_cr_c_cr0_0 \$854
connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2
connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0]
- connect \addr_en_CR_cr_b_cr0_0 \$848
- connect \rp_CR_cr_b_cr0_0 \$842
+ connect \addr_en_CR_cr_b_cr0_0 \$846
+ connect \rp_CR_cr_b_cr0_0 \$840
connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0
- connect \pick_CR_cr_b_cr0_0 \$840
+ connect \pick_CR_cr_b_cr0_0 \$838
connect \rdflag_CR_cr_b_0 \core_cr_in2_ok
- connect \cr_src1__ren \$832 [7:0]
- connect \addr_en_CR_cr_a_branch0_1 \$829
- connect \rp_CR_cr_a_branch0_1 \$823
- connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0
+ connect \cr_src1__ren \$830 [7:0]
+ connect \addr_en_CR_cr_a_branch0_1 \$827
+ connect \rp_CR_cr_a_branch0_1 \$821
+ connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast1_branch0_3
connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0
connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1
- connect \pick_CR_cr_a_branch0_1 \$821
- connect \addr_en_CR_cr_a_cr0_0 \$813
- connect \rp_CR_cr_a_cr0_0 \$807
+ connect \pick_CR_cr_a_branch0_1 \$819
+ connect \addr_en_CR_cr_a_cr0_0 \$811
+ connect \rp_CR_cr_a_cr0_0 \$805
connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1
connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0
- connect \pick_CR_cr_a_cr0_0 \$805
+ connect \pick_CR_cr_a_cr0_0 \$803
connect \rdflag_CR_cr_a_0 \core_cr_in1_ok
connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0
- connect \addr_en_CR_full_cr_cr0_0 \$797
- connect \rp_CR_full_cr_cr0_0 \$795
+ connect \addr_en_CR_full_cr_cr0_0 \$795
+ connect \rp_CR_full_cr_cr0_0 \$793
connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0
- connect \pick_CR_full_cr_cr0_0 \$793
+ connect \pick_CR_full_cr_cr0_0 \$791
connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok
connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0
- connect \addr_en_XER_xer_ov_spr0_0 \$785
- connect \rp_XER_xer_ov_spr0_0 \$783
+ connect \addr_en_XER_xer_ov_spr0_0 \$783
+ connect \rp_XER_xer_ov_spr0_0 \$781
connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0
- connect \pick_XER_xer_ov_spr0_0 \$781
- connect \rdflag_XER_xer_ov_0 \$773
- connect \xer_src2__ren \$761
- connect \addr_en_XER_xer_ca_shiftrot0_2 \$759
- connect \rp_XER_xer_ca_shiftrot0_2 \$757
- connect \pick_XER_xer_ca_shiftrot0_2 \$755
- connect \addr_en_XER_xer_ca_spr0_1 \$747
- connect \rp_XER_xer_ca_spr0_1 \$745
- connect \pick_XER_xer_ca_spr0_1 \$743
- connect \addr_en_XER_xer_ca_alu0_0 \$735
- connect \rp_XER_xer_ca_alu0_0 \$733
+ connect \pick_XER_xer_ov_spr0_0 \$779
+ connect \rdflag_XER_xer_ov_0 \$771
+ connect \xer_src2__ren \$759
+ connect \addr_en_XER_xer_ca_shiftrot0_2 \$757
+ connect \rp_XER_xer_ca_shiftrot0_2 \$755
+ connect \pick_XER_xer_ca_shiftrot0_2 \$753
+ connect \addr_en_XER_xer_ca_spr0_1 \$745
+ connect \rp_XER_xer_ca_spr0_1 \$743
+ connect \pick_XER_xer_ca_spr0_1 \$741
+ connect \addr_en_XER_xer_ca_alu0_0 \$733
+ connect \rp_XER_xer_ca_alu0_0 \$731
connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2
connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1
connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0
- connect \pick_XER_xer_ca_alu0_0 \$731
- connect \rdflag_XER_xer_ca_0 \$723
- connect \xer_src1__ren \$705
- connect \addr_en_XER_xer_so_shiftrot0_5 \$703
- connect \rp_XER_xer_so_shiftrot0_5 \$701
- connect \pick_XER_xer_so_shiftrot0_5 \$699
- connect \addr_en_XER_xer_so_mul0_4 \$691
- connect \rp_XER_xer_so_mul0_4 \$689
- connect \pick_XER_xer_so_mul0_4 \$687
- connect \addr_en_XER_xer_so_div0_3 \$679
- connect \rp_XER_xer_so_div0_3 \$677
- connect \pick_XER_xer_so_div0_3 \$675
- connect \addr_en_XER_xer_so_spr0_2 \$667
- connect \rp_XER_xer_so_spr0_2 \$665
- connect \pick_XER_xer_so_spr0_2 \$663
- connect \addr_en_XER_xer_so_logical0_1 \$655
- connect \rp_XER_xer_so_logical0_1 \$653
- connect \pick_XER_xer_so_logical0_1 \$651
- connect \addr_en_XER_xer_so_alu0_0 \$643
- connect \rp_XER_xer_so_alu0_0 \$641
+ connect \pick_XER_xer_ca_alu0_0 \$729
+ connect \rdflag_XER_xer_ca_0 \$721
+ connect \xer_src1__ren \$703
+ connect \addr_en_XER_xer_so_shiftrot0_5 \$701
+ connect \rp_XER_xer_so_shiftrot0_5 \$699
+ connect \pick_XER_xer_so_shiftrot0_5 \$697
+ connect \addr_en_XER_xer_so_mul0_4 \$689
+ connect \rp_XER_xer_so_mul0_4 \$687
+ connect \pick_XER_xer_so_mul0_4 \$685
+ connect \addr_en_XER_xer_so_div0_3 \$677
+ connect \rp_XER_xer_so_div0_3 \$675
+ connect \pick_XER_xer_so_div0_3 \$673
+ connect \addr_en_XER_xer_so_spr0_2 \$665
+ connect \rp_XER_xer_so_spr0_2 \$663
+ connect \pick_XER_xer_so_spr0_2 \$661
+ connect \addr_en_XER_xer_so_logical0_1 \$653
+ connect \rp_XER_xer_so_logical0_1 \$651
+ connect \pick_XER_xer_so_logical0_1 \$649
+ connect \addr_en_XER_xer_so_alu0_0 \$641
+ connect \rp_XER_xer_so_alu0_0 \$639
connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5
connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4
connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3
connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2
connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1
connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0
- connect \pick_XER_xer_so_alu0_0 \$639
- connect \rdflag_XER_xer_so_0 \$631
- connect \int_src3__ren \$619
- connect \int_src3__addr \$617 [4:0]
- connect \addr_en_INT_rc_ldst0_1 \$614
- connect \rp_INT_rc_ldst0_1 \$612
- connect \pick_INT_rc_ldst0_1 \$610
- connect \addr_en_INT_rc_shiftrot0_0 \$602
- connect \rp_INT_rc_shiftrot0_0 \$600
- connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1
- connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0
- connect \pick_INT_rc_shiftrot0_0 \$598
- connect \rdflag_INT_rc_0 \core_reg3_ok
- connect \int_src2__ren \$590
- connect \int_src2__addr \$588 [4:0]
- connect \addr_en_INT_rb_ldst0_7 \$573
- connect \rp_INT_rb_ldst0_7 \$571
- connect \pick_INT_rb_ldst0_7 \$569
- connect \addr_en_INT_rb_shiftrot0_6 \$561
- connect \rp_INT_rb_shiftrot0_6 \$559
- connect \pick_INT_rb_shiftrot0_6 \$557
- connect \addr_en_INT_rb_mul0_5 \$549
- connect \rp_INT_rb_mul0_5 \$547
- connect \pick_INT_rb_mul0_5 \$545
- connect \addr_en_INT_rb_div0_4 \$537
- connect \rp_INT_rb_div0_4 \$535
- connect \pick_INT_rb_div0_4 \$533
- connect \addr_en_INT_rb_logical0_3 \$525
- connect \rp_INT_rb_logical0_3 \$523
- connect \pick_INT_rb_logical0_3 \$521
- connect \addr_en_INT_rb_trap0_2 \$513
- connect \rp_INT_rb_trap0_2 \$511
- connect \pick_INT_rb_trap0_2 \$509
- connect \addr_en_INT_rb_cr0_1 \$501
- connect \rp_INT_rb_cr0_1 \$499
- connect \pick_INT_rb_cr0_1 \$497
- connect \addr_en_INT_rb_alu0_0 \$489
- connect \rp_INT_rb_alu0_0 \$487
- connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7
- connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6
- connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5
- connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4
- connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3
- connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2
- connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1
- connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0
- connect \pick_INT_rb_alu0_0 \$485
- connect \rdflag_INT_rb_0 \core_reg2_ok
- connect \int_src1__ren \$477
- connect \int_src1__addr \$475 [4:0]
- connect \addr_en_INT_ra_ldst0_8 \$458
- connect \rp_INT_ra_ldst0_8 \$456
- connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1
- connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7
- connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8
- connect \pick_INT_ra_ldst0_8 \$454
- connect \addr_en_INT_ra_shiftrot0_7 \$446
- connect \rp_INT_ra_shiftrot0_7 \$444
- connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2
- connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5
- connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0
- connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6
- connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7
- connect \pick_INT_ra_shiftrot0_7 \$442
- connect \addr_en_INT_ra_mul0_6 \$434
- connect \rp_INT_ra_mul0_6 \$432
- connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4
- connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5
- connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6
- connect \pick_INT_ra_mul0_6 \$430
- connect \addr_en_INT_ra_div0_5 \$422
- connect \rp_INT_ra_div0_5 \$420
- connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3
- connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4
- connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5
- connect \pick_INT_ra_div0_5 \$418
- connect \addr_en_INT_ra_spr0_4 \$410
- connect \rp_INT_ra_spr0_4 \$408
- connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0
- connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2
- connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0
- connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1
- connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2
- connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4
- connect \pick_INT_ra_spr0_4 \$406
- connect \addr_en_INT_ra_logical0_3 \$398
- connect \rp_INT_ra_logical0_3 \$396
+ connect \pick_XER_xer_so_alu0_0 \$637
+ connect \rdflag_XER_xer_so_0 \$629
+ connect \int_src__ren \$617
+ connect \int_src__addr \$615 [4:0]
+ connect \addr_en_INT_rabc_ldst0_18 \$578
+ connect \rp_INT_rabc_ldst0_18 \$576
+ connect \pick_INT_rabc_ldst0_18 \$574
+ connect \addr_en_INT_rabc_shiftrot0_17 \$566
+ connect \rp_INT_rabc_shiftrot0_17 \$564
+ connect \pick_INT_rabc_shiftrot0_17 \$562
+ connect \addr_en_INT_rabc_mul0_16 \$554
+ connect \rp_INT_rabc_mul0_16 \$552
+ connect \pick_INT_rabc_mul0_16 \$550
+ connect \addr_en_INT_rabc_div0_15 \$542
+ connect \rp_INT_rabc_div0_15 \$540
+ connect \pick_INT_rabc_div0_15 \$538
+ connect \addr_en_INT_rabc_spr0_14 \$530
+ connect \rp_INT_rabc_spr0_14 \$528
+ connect \fus_cu_rd__go_i$66 [1] \dp_SPR_spr1_spr0_0
+ connect \fus_cu_rd__go_i$66 [2] \dp_FAST_fast1_spr0_2
+ connect \fus_cu_rd__go_i$66 [4] \dp_XER_xer_ov_spr0_0
+ connect \fus_cu_rd__go_i$66 [5] \dp_XER_xer_ca_spr0_1
+ connect \fus_cu_rd__go_i$66 [3] \dp_XER_xer_so_spr0_2
+ connect \fus_cu_rd__go_i$66 [0] \dp_INT_rabc_spr0_14
+ connect \pick_INT_rabc_spr0_14 \$526
+ connect \addr_en_INT_rabc_logical0_13 \$518
+ connect \rp_INT_rabc_logical0_13 \$516
+ connect \pick_INT_rabc_logical0_13 \$514
+ connect \addr_en_INT_rabc_trap0_12 \$506
+ connect \rp_INT_rabc_trap0_12 \$504
+ connect \pick_INT_rabc_trap0_12 \$502
+ connect \addr_en_INT_rabc_cr0_11 \$494
+ connect \rp_INT_rabc_cr0_11 \$492
+ connect \pick_INT_rabc_cr0_11 \$490
+ connect \addr_en_INT_rabc_alu0_10 \$482
+ connect \rp_INT_rabc_alu0_10 \$480
+ connect \pick_INT_rabc_alu0_10 \$478
+ connect \addr_en_INT_rabc_ldst0_9 \$470
+ connect \rp_INT_rabc_ldst0_9 \$468
+ connect \pick_INT_rabc_ldst0_9 \$466
+ connect \addr_en_INT_rabc_shiftrot0_8 \$458
+ connect \rp_INT_rabc_shiftrot0_8 \$456
+ connect \pick_INT_rabc_shiftrot0_8 \$454
+ connect \addr_en_INT_rabc_ldst0_7 \$446
+ connect \rp_INT_rabc_ldst0_7 \$444
+ connect \fus_cu_rd__go_i$59 [0] \dp_INT_rabc_ldst0_18
+ connect \fus_cu_rd__go_i$59 [2] \dp_INT_rabc_ldst0_9
+ connect \fus_cu_rd__go_i$59 [1] \dp_INT_rabc_ldst0_7
+ connect \pick_INT_rabc_ldst0_7 \$442
+ connect \addr_en_INT_rabc_shiftrot0_6 \$434
+ connect \rp_INT_rabc_shiftrot0_6 \$432
+ connect \fus_cu_rd__go_i$56 [4] \dp_XER_xer_ca_shiftrot0_2
+ connect \fus_cu_rd__go_i$56 [3] \dp_XER_xer_so_shiftrot0_5
+ connect \fus_cu_rd__go_i$56 [0] \dp_INT_rabc_shiftrot0_17
+ connect \fus_cu_rd__go_i$56 [2] \dp_INT_rabc_shiftrot0_8
+ connect \fus_cu_rd__go_i$56 [1] \dp_INT_rabc_shiftrot0_6
+ connect \pick_INT_rabc_shiftrot0_6 \$430
+ connect \addr_en_INT_rabc_mul0_5 \$422
+ connect \rp_INT_rabc_mul0_5 \$420
+ connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_mul0_4
+ connect \fus_cu_rd__go_i$53 [0] \dp_INT_rabc_mul0_16
+ connect \fus_cu_rd__go_i$53 [1] \dp_INT_rabc_mul0_5
+ connect \pick_INT_rabc_mul0_5 \$418
+ connect \addr_en_INT_rabc_div0_4 \$410
+ connect \rp_INT_rabc_div0_4 \$408
+ connect \fus_cu_rd__go_i$50 [2] \dp_XER_xer_so_div0_3
+ connect \fus_cu_rd__go_i$50 [0] \dp_INT_rabc_div0_15
+ connect \fus_cu_rd__go_i$50 [1] \dp_INT_rabc_div0_4
+ connect \pick_INT_rabc_div0_4 \$406
+ connect \addr_en_INT_rabc_logical0_3 \$398
+ connect \rp_INT_rabc_logical0_3 \$396
connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1
- connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3
- connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3
- connect \pick_INT_ra_logical0_3 \$394
- connect \addr_en_INT_ra_trap0_2 \$386
- connect \rp_INT_ra_trap0_2 \$384
- connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1
+ connect \fus_cu_rd__go_i$47 [0] \dp_INT_rabc_logical0_13
+ connect \fus_cu_rd__go_i$47 [1] \dp_INT_rabc_logical0_3
+ connect \pick_INT_rabc_logical0_3 \$394
+ connect \addr_en_INT_rabc_trap0_2 \$386
+ connect \rp_INT_rabc_trap0_2 \$384
+ connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast1_trap0_4
connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1
- connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2
- connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2
- connect \pick_INT_ra_trap0_2 \$382
- connect \addr_en_INT_ra_cr0_1 \$374
- connect \rp_INT_ra_cr0_1 \$372
+ connect \fus_cu_rd__go_i$44 [0] \dp_INT_rabc_trap0_12
+ connect \fus_cu_rd__go_i$44 [1] \dp_INT_rabc_trap0_2
+ connect \pick_INT_rabc_trap0_2 \$382
+ connect \addr_en_INT_rabc_cr0_1 \$374
+ connect \rp_INT_rabc_cr0_1 \$372
connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0
connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0
connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0
connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0
- connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1
- connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1
- connect \pick_INT_ra_cr0_1 \$370
- connect \addr_en_INT_ra_alu0_0 \$362
- connect \rp_INT_ra_alu0_0 \$360
+ connect \fus_cu_rd__go_i$41 [0] \dp_INT_rabc_cr0_11
+ connect \fus_cu_rd__go_i$41 [1] \dp_INT_rabc_cr0_1
+ connect \pick_INT_rabc_cr0_1 \$370
+ connect \addr_en_INT_rabc_alu0_0 \$362
+ connect \rp_INT_rabc_alu0_0 \$360
connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0
connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0
- connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0
- connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0
- connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8
- connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7
- connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6
- connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5
- connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4
- connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3
- connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2
- connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1
- connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0
- connect \pick_INT_ra_alu0_0 \$358
- connect \rdflag_INT_ra_0 \core_reg1_ok
+ connect \fus_cu_rd__go_i [0] \dp_INT_rabc_alu0_10
+ connect \fus_cu_rd__go_i [1] \dp_INT_rabc_alu0_0
+ connect \rdpick_INT_rabc_i [18] \pick_INT_rabc_ldst0_18
+ connect \rdpick_INT_rabc_i [17] \pick_INT_rabc_shiftrot0_17
+ connect \rdpick_INT_rabc_i [16] \pick_INT_rabc_mul0_16
+ connect \rdpick_INT_rabc_i [15] \pick_INT_rabc_div0_15
+ connect \rdpick_INT_rabc_i [14] \pick_INT_rabc_spr0_14
+ connect \rdpick_INT_rabc_i [13] \pick_INT_rabc_logical0_13
+ connect \rdpick_INT_rabc_i [12] \pick_INT_rabc_trap0_12
+ connect \rdpick_INT_rabc_i [11] \pick_INT_rabc_cr0_11
+ connect \rdpick_INT_rabc_i [10] \pick_INT_rabc_alu0_10
+ connect \rdpick_INT_rabc_i [9] \pick_INT_rabc_ldst0_9
+ connect \rdpick_INT_rabc_i [8] \pick_INT_rabc_shiftrot0_8
+ connect \rdpick_INT_rabc_i [7] \pick_INT_rabc_ldst0_7
+ connect \rdpick_INT_rabc_i [6] \pick_INT_rabc_shiftrot0_6
+ connect \rdpick_INT_rabc_i [5] \pick_INT_rabc_mul0_5
+ connect \rdpick_INT_rabc_i [4] \pick_INT_rabc_div0_4
+ connect \rdpick_INT_rabc_i [3] \pick_INT_rabc_logical0_3
+ connect \rdpick_INT_rabc_i [2] \pick_INT_rabc_trap0_2
+ connect \rdpick_INT_rabc_i [1] \pick_INT_rabc_cr0_1
+ connect \rdpick_INT_rabc_i [0] \pick_INT_rabc_alu0_0
+ connect \pick_INT_rabc_alu0_0 \$358
+ connect \rdflag_INT_rabc_2 \core_reg1_ok
+ connect \rdflag_INT_rabc_1 \core_reg3_ok
+ connect \rdflag_INT_rabc_0 \core_reg2_ok
connect \en_ldst0 \$217
connect \en_shiftrot0 \$213
connect \en_mul0 \$209
connect \dec_ALU_bigendian \bigendian_i
connect \dec_ALU_raw_opcode_in \raw_insn_i
end
-attribute \src "libresoc.v:49197.1-49933.10"
+attribute \src "libresoc.v:49125.1-49758.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr"
attribute \generator "nMigen"
module \cr
- attribute \src "libresoc.v:49892.3-49901.6"
- wire width 4 $0\cr_pred__data_o[3:0]
- attribute \src "libresoc.v:49198.7-49198.20"
+ attribute \src "libresoc.v:49126.7-49126.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:49826.3-49834.6"
- wire width 8 $0\ren_delay$17$next[7:0]$3056
- attribute \src "libresoc.v:49646.3-49647.43"
- wire width 8 $0\ren_delay$17[7:0]$3053
- attribute \src "libresoc.v:49578.13-49578.35"
- wire width 8 $0\ren_delay$17[7:0]$3074
- attribute \src "libresoc.v:49845.3-49853.6"
- wire width 8 $0\ren_delay$34$next[7:0]$3060
- attribute \src "libresoc.v:49644.3-49645.43"
- wire width 8 $0\ren_delay$34[7:0]$3051
- attribute \src "libresoc.v:49582.13-49582.35"
- wire width 8 $0\ren_delay$34[7:0]$3076
- attribute \src "libresoc.v:49864.3-49872.6"
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- attribute \src "libresoc.v:49642.3-49643.43"
- wire width 8 $0\ren_delay$51[7:0]$3049
- attribute \src "libresoc.v:49586.13-49586.35"
- wire width 8 $0\ren_delay$51[7:0]$3078
- attribute \src "libresoc.v:49883.3-49891.6"
- wire width 8 $0\ren_delay$next[7:0]$3068
- attribute \src "libresoc.v:49648.3-49649.35"
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+ attribute \src "libresoc.v:49508.3-49509.43"
+ wire width 8 $0\ren_delay$17[7:0]$3043
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wire width 8 $0\ren_delay[7:0]
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wire width 4 $0\src1__data_o[3:0]
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+ attribute \src "libresoc.v:49681.3-49690.6"
wire width 4 $0\src2__data_o[3:0]
- attribute \src "libresoc.v:49873.3-49882.6"
+ attribute \src "libresoc.v:49700.3-49709.6"
wire width 4 $0\src3__data_o[3:0]
- attribute \src "libresoc.v:49892.3-49901.6"
- wire width 4 $1\cr_pred__data_o[3:0]
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- wire width 8 $1\ren_delay$51$next[7:0]$3065
- attribute \src "libresoc.v:49883.3-49891.6"
- wire width 8 $1\ren_delay$next[7:0]$3069
- attribute \src "libresoc.v:49576.13-49576.30"
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wire width 8 $1\ren_delay[7:0]
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wire width 4 $1\src1__data_o[3:0]
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wire width 4 $1\src2__data_o[3:0]
- attribute \src "libresoc.v:49873.3-49882.6"
+ attribute \src "libresoc.v:49700.3-49709.6"
wire width 4 $1\src3__data_o[3:0]
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- wire width 4 $or$libresoc.v:49610$3016_Y
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- wire width 4 $or$libresoc.v:49611$3017_Y
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- wire width 4 $or$libresoc.v:49617$3023_Y
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- wire width 4 $or$libresoc.v:49618$3024_Y
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- wire width 4 $or$libresoc.v:49619$3025_Y
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- wire width 4 $or$libresoc.v:49620$3026_Y
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- wire width 4 $or$libresoc.v:49621$3027_Y
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- wire width 4 $or$libresoc.v:49622$3028_Y
- attribute \src "libresoc.v:49624.18-49624.126"
- wire width 4 $or$libresoc.v:49624$3030_Y
- attribute \src "libresoc.v:49625.17-49625.131"
- wire width 4 $or$libresoc.v:49625$3031_Y
- attribute \src "libresoc.v:49626.18-49626.126"
- wire width 4 $or$libresoc.v:49626$3032_Y
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- wire width 4 $or$libresoc.v:49627$3033_Y
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- wire width 4 $or$libresoc.v:49628$3034_Y
- attribute \src "libresoc.v:49629.18-49629.126"
- wire width 4 $or$libresoc.v:49629$3035_Y
- attribute \src "libresoc.v:49630.18-49630.97"
- wire width 4 $or$libresoc.v:49630$3036_Y
- attribute \src "libresoc.v:49631.18-49631.97"
- wire width 4 $or$libresoc.v:49631$3037_Y
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- wire width 4 $or$libresoc.v:49633$3039_Y
- attribute \src "libresoc.v:49634.18-49634.126"
- wire width 4 $or$libresoc.v:49634$3040_Y
- attribute \src "libresoc.v:49635.18-49635.97"
- wire width 4 $or$libresoc.v:49635$3041_Y
- attribute \src "libresoc.v:49636.17-49636.131"
- wire width 4 $or$libresoc.v:49636$3042_Y
- attribute \src "libresoc.v:49637.18-49637.126"
- wire width 4 $or$libresoc.v:49637$3043_Y
- attribute \src "libresoc.v:49638.18-49638.126"
- wire width 4 $or$libresoc.v:49638$3044_Y
- attribute \src "libresoc.v:49639.18-49639.97"
- wire width 4 $or$libresoc.v:49639$3045_Y
- attribute \src "libresoc.v:49640.18-49640.97"
- wire width 4 $or$libresoc.v:49640$3046_Y
- attribute \src "libresoc.v:49641.17-49641.94"
- wire width 4 $or$libresoc.v:49641$3047_Y
- attribute \src "libresoc.v:49614.18-49614.100"
- wire $reduce_or$libresoc.v:49614$3020_Y
- attribute \src "libresoc.v:49615.17-49615.95"
- wire $reduce_or$libresoc.v:49615$3021_Y
- attribute \src "libresoc.v:49623.18-49623.100"
- wire $reduce_or$libresoc.v:49623$3029_Y
- attribute \src "libresoc.v:49632.18-49632.100"
- wire $reduce_or$libresoc.v:49632$3038_Y
+ attribute \src "libresoc.v:49482.17-49482.125"
+ wire width 4 $or$libresoc.v:49482$3016_Y
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+ wire width 4 $or$libresoc.v:49483$3017_Y
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+ wire width 4 $or$libresoc.v:49484$3018_Y
+ attribute \src "libresoc.v:49485.18-49485.96"
+ wire width 4 $or$libresoc.v:49485$3019_Y
+ attribute \src "libresoc.v:49488.18-49488.126"
+ wire width 4 $or$libresoc.v:49488$3022_Y
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+ wire width 4 $or$libresoc.v:49489$3023_Y
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+ wire width 4 $or$libresoc.v:49490$3024_Y
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+ wire width 4 $or$libresoc.v:49491$3025_Y
+ attribute \src "libresoc.v:49492.18-49492.126"
+ wire width 4 $or$libresoc.v:49492$3026_Y
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+ wire width 4 $or$libresoc.v:49493$3027_Y
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+ wire width 4 $or$libresoc.v:49494$3028_Y
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+ wire width 4 $or$libresoc.v:49496$3030_Y
+ attribute \src "libresoc.v:49497.17-49497.125"
+ wire width 4 $or$libresoc.v:49497$3031_Y
+ attribute \src "libresoc.v:49498.18-49498.126"
+ wire width 4 $or$libresoc.v:49498$3032_Y
+ attribute \src "libresoc.v:49499.18-49499.97"
+ wire width 4 $or$libresoc.v:49499$3033_Y
+ attribute \src "libresoc.v:49500.18-49500.126"
+ wire width 4 $or$libresoc.v:49500$3034_Y
+ attribute \src "libresoc.v:49501.18-49501.126"
+ wire width 4 $or$libresoc.v:49501$3035_Y
+ attribute \src "libresoc.v:49502.18-49502.97"
+ wire width 4 $or$libresoc.v:49502$3036_Y
+ attribute \src "libresoc.v:49503.18-49503.97"
+ wire width 4 $or$libresoc.v:49503$3037_Y
+ attribute \src "libresoc.v:49504.17-49504.125"
+ wire width 4 $or$libresoc.v:49504$3038_Y
+ attribute \src "libresoc.v:49505.17-49505.94"
+ wire width 4 $or$libresoc.v:49505$3039_Y
+ attribute \src "libresoc.v:49486.18-49486.100"
+ wire $reduce_or$libresoc.v:49486$3020_Y
+ attribute \src "libresoc.v:49487.17-49487.95"
+ wire $reduce_or$libresoc.v:49487$3021_Y
+ attribute \src "libresoc.v:49495.18-49495.100"
+ wire $reduce_or$libresoc.v:49495$3029_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 4 \$49
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 4 \$5
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- wire \$52
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- wire width 4 \$54
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- wire width 4 \$56
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- wire width 4 \$58
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- wire width 4 \$60
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- wire width 4 \$62
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- wire width 4 \$64
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- wire width 4 \$66
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 8 \cr_pred__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 14 \data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \data_i$69
+ wire width 4 \data_i$52
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 32 output 3 \full_rd2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 32 input 12 \full_wr__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 8 input 13 \full_wr__wen
- attribute \src "libresoc.v:49198.7-49198.15"
+ attribute \src "libresoc.v:49126.7-49126.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_0_cr_pred0__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_0_cr_pred0__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_0_dest10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_0_dest10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_0_w0__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_1_cr_pred1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_1_cr_pred1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_1_dest11__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_1_dest11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_1_w1__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_2_cr_pred2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_2_cr_pred2__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_2_dest12__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_2_dest12__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_2_w2__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_3_cr_pred3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_3_cr_pred3__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_3_dest13__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_3_dest13__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_3_w3__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_4_cr_pred4__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_4_cr_pred4__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_4_dest14__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_4_dest14__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_4_w4__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_5_cr_pred5__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_5_cr_pred5__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_5_dest15__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_5_dest15__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_5_w5__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_6_cr_pred6__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_6_cr_pred6__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_6_dest16__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_6_dest16__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_6_w6__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \reg_7_cr_pred7__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \reg_7_cr_pred7__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \reg_7_dest17__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \reg_7_dest17__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170"
wire width 8 \ren_delay$34$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170"
- wire width 8 \ren_delay$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170"
- wire width 8 \ren_delay$51$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170"
wire width 8 \ren_delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 6 \src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 8 input 15 \wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 8 \wen$68
+ wire width 8 \wen$51
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49610$3016
+ cell $or $or$libresoc.v:49482$3016
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_4_cr_pred4__data_o
- connect \B \reg_5_cr_pred5__data_o
- connect \Y $or$libresoc.v:49610$3016_Y
+ connect \A \reg_4_src14__data_o
+ connect \B \reg_5_src15__data_o
+ connect \Y $or$libresoc.v:49482$3016_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49611$3017
+ cell $or $or$libresoc.v:49483$3017
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_6_cr_pred6__data_o
- connect \B \reg_7_cr_pred7__data_o
- connect \Y $or$libresoc.v:49611$3017_Y
+ connect \A \reg_6_src16__data_o
+ connect \B \reg_7_src17__data_o
+ connect \Y $or$libresoc.v:49483$3017_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49612$3018
+ cell $or $or$libresoc.v:49484$3018
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \$11
- connect \Y $or$libresoc.v:49612$3018_Y
+ connect \Y $or$libresoc.v:49484$3018_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49613$3019
+ cell $or $or$libresoc.v:49485$3019
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$7
connect \B \$13
- connect \Y $or$libresoc.v:49613$3019_Y
+ connect \Y $or$libresoc.v:49485$3019_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49616$3022
+ cell $or $or$libresoc.v:49488$3022
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_0_src10__data_o
- connect \B \reg_1_src11__data_o
- connect \Y $or$libresoc.v:49616$3022_Y
+ connect \A \reg_0_src20__data_o
+ connect \B \reg_1_src21__data_o
+ connect \Y $or$libresoc.v:49488$3022_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49617$3023
+ cell $or $or$libresoc.v:49489$3023
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_2_src12__data_o
- connect \B \reg_3_src13__data_o
- connect \Y $or$libresoc.v:49617$3023_Y
+ connect \A \reg_2_src22__data_o
+ connect \B \reg_3_src23__data_o
+ connect \Y $or$libresoc.v:49489$3023_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49618$3024
+ cell $or $or$libresoc.v:49490$3024
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$20
connect \B \$22
- connect \Y $or$libresoc.v:49618$3024_Y
+ connect \Y $or$libresoc.v:49490$3024_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49619$3025
+ cell $or $or$libresoc.v:49491$3025
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_4_src14__data_o
- connect \B \reg_5_src15__data_o
- connect \Y $or$libresoc.v:49619$3025_Y
+ connect \A \reg_4_src24__data_o
+ connect \B \reg_5_src25__data_o
+ connect \Y $or$libresoc.v:49491$3025_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49620$3026
+ cell $or $or$libresoc.v:49492$3026
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_6_src16__data_o
- connect \B \reg_7_src17__data_o
- connect \Y $or$libresoc.v:49620$3026_Y
+ connect \A \reg_6_src26__data_o
+ connect \B \reg_7_src27__data_o
+ connect \Y $or$libresoc.v:49492$3026_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49621$3027
+ cell $or $or$libresoc.v:49493$3027
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:49621$3027_Y
+ connect \Y $or$libresoc.v:49493$3027_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49622$3028
+ cell $or $or$libresoc.v:49494$3028
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$24
connect \B \$30
- connect \Y $or$libresoc.v:49622$3028_Y
+ connect \Y $or$libresoc.v:49494$3028_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49624$3030
+ cell $or $or$libresoc.v:49496$3030
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_0_src20__data_o
- connect \B \reg_1_src21__data_o
- connect \Y $or$libresoc.v:49624$3030_Y
+ connect \A \reg_0_src30__data_o
+ connect \B \reg_1_src31__data_o
+ connect \Y $or$libresoc.v:49496$3030_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49625$3031
+ cell $or $or$libresoc.v:49497$3031
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_0_cr_pred0__data_o
- connect \B \reg_1_cr_pred1__data_o
- connect \Y $or$libresoc.v:49625$3031_Y
+ connect \A \reg_0_src10__data_o
+ connect \B \reg_1_src11__data_o
+ connect \Y $or$libresoc.v:49497$3031_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49626$3032
+ cell $or $or$libresoc.v:49498$3032
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_2_src22__data_o
- connect \B \reg_3_src23__data_o
- connect \Y $or$libresoc.v:49626$3032_Y
+ connect \A \reg_2_src32__data_o
+ connect \B \reg_3_src33__data_o
+ connect \Y $or$libresoc.v:49498$3032_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49627$3033
+ cell $or $or$libresoc.v:49499$3033
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$37
connect \B \$39
- connect \Y $or$libresoc.v:49627$3033_Y
+ connect \Y $or$libresoc.v:49499$3033_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49628$3034
+ cell $or $or$libresoc.v:49500$3034
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_4_src24__data_o
- connect \B \reg_5_src25__data_o
- connect \Y $or$libresoc.v:49628$3034_Y
+ connect \A \reg_4_src34__data_o
+ connect \B \reg_5_src35__data_o
+ connect \Y $or$libresoc.v:49500$3034_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49629$3035
+ cell $or $or$libresoc.v:49501$3035
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \reg_6_src26__data_o
- connect \B \reg_7_src27__data_o
- connect \Y $or$libresoc.v:49629$3035_Y
+ connect \A \reg_6_src36__data_o
+ connect \B \reg_7_src37__data_o
+ connect \Y $or$libresoc.v:49501$3035_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49630$3036
+ cell $or $or$libresoc.v:49502$3036
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$43
connect \B \$45
- connect \Y $or$libresoc.v:49630$3036_Y
+ connect \Y $or$libresoc.v:49502$3036_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49631$3037
+ cell $or $or$libresoc.v:49503$3037
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$41
connect \B \$47
- connect \Y $or$libresoc.v:49631$3037_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49633$3039
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \reg_0_src30__data_o
- connect \B \reg_1_src31__data_o
- connect \Y $or$libresoc.v:49633$3039_Y
+ connect \Y $or$libresoc.v:49503$3037_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49634$3040
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \reg_2_src32__data_o
- connect \B \reg_3_src33__data_o
- connect \Y $or$libresoc.v:49634$3040_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49635$3041
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \$54
- connect \B \$56
- connect \Y $or$libresoc.v:49635$3041_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49636$3042
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \reg_2_cr_pred2__data_o
- connect \B \reg_3_cr_pred3__data_o
- connect \Y $or$libresoc.v:49636$3042_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49637$3043
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \reg_4_src34__data_o
- connect \B \reg_5_src35__data_o
- connect \Y $or$libresoc.v:49637$3043_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:49638$3044
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \reg_6_src36__data_o
- connect \B \reg_7_src37__data_o
- connect \Y $or$libresoc.v:49638$3044_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49639$3045
+ cell $or $or$libresoc.v:49504$3038
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \$60
- connect \B \$62
- connect \Y $or$libresoc.v:49639$3045_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49640$3046
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \$58
- connect \B \$64
- connect \Y $or$libresoc.v:49640$3046_Y
+ connect \A \reg_2_src12__data_o
+ connect \B \reg_3_src13__data_o
+ connect \Y $or$libresoc.v:49504$3038_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:49641$3047
+ cell $or $or$libresoc.v:49505$3039
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \$5
- connect \Y $or$libresoc.v:49641$3047_Y
+ connect \Y $or$libresoc.v:49505$3039_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:49614$3020
+ cell $reduce_or $reduce_or$libresoc.v:49486$3020
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \ren_delay$17
- connect \Y $reduce_or$libresoc.v:49614$3020_Y
+ connect \Y $reduce_or$libresoc.v:49486$3020_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:49615$3021
+ cell $reduce_or $reduce_or$libresoc.v:49487$3021
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:49615$3021_Y
+ connect \Y $reduce_or$libresoc.v:49487$3021_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:49623$3029
+ cell $reduce_or $reduce_or$libresoc.v:49495$3029
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \ren_delay$34
- connect \Y $reduce_or$libresoc.v:49623$3029_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:49632$3038
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \Y_WIDTH 1
- connect \A \ren_delay$51
- connect \Y $reduce_or$libresoc.v:49632$3038_Y
+ connect \Y $reduce_or$libresoc.v:49495$3029_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49650.9-49671.4"
+ attribute \src "libresoc.v:49512.9-49531.4"
cell \reg_0 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred0__data_o \reg_0_cr_pred0__data_o
- connect \cr_pred0__ren \reg_0_cr_pred0__ren
connect \dest10__data_i \reg_0_dest10__data_i
connect \dest10__wen \reg_0_dest10__wen
connect \dest20__data_i \reg_0_dest20__data_i
connect \w0__wen \reg_0_w0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49672.9-49693.4"
+ attribute \src "libresoc.v:49532.9-49551.4"
cell \reg_1 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred1__data_o \reg_1_cr_pred1__data_o
- connect \cr_pred1__ren \reg_1_cr_pred1__ren
connect \dest11__data_i \reg_1_dest11__data_i
connect \dest11__wen \reg_1_dest11__wen
connect \dest21__data_i \reg_1_dest21__data_i
connect \w1__wen \reg_1_w1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49694.9-49715.4"
+ attribute \src "libresoc.v:49552.9-49571.4"
cell \reg_2 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred2__data_o \reg_2_cr_pred2__data_o
- connect \cr_pred2__ren \reg_2_cr_pred2__ren
connect \dest12__data_i \reg_2_dest12__data_i
connect \dest12__wen \reg_2_dest12__wen
connect \dest22__data_i \reg_2_dest22__data_i
connect \w2__wen \reg_2_w2__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49716.9-49737.4"
+ attribute \src "libresoc.v:49572.9-49591.4"
cell \reg_3 \reg_3
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred3__data_o \reg_3_cr_pred3__data_o
- connect \cr_pred3__ren \reg_3_cr_pred3__ren
connect \dest13__data_i \reg_3_dest13__data_i
connect \dest13__wen \reg_3_dest13__wen
connect \dest23__data_i \reg_3_dest23__data_i
connect \w3__wen \reg_3_w3__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49738.9-49759.4"
+ attribute \src "libresoc.v:49592.9-49611.4"
cell \reg_4 \reg_4
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred4__data_o \reg_4_cr_pred4__data_o
- connect \cr_pred4__ren \reg_4_cr_pred4__ren
connect \dest14__data_i \reg_4_dest14__data_i
connect \dest14__wen \reg_4_dest14__wen
connect \dest24__data_i \reg_4_dest24__data_i
connect \w4__wen \reg_4_w4__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49760.9-49781.4"
+ attribute \src "libresoc.v:49612.9-49631.4"
cell \reg_5 \reg_5
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred5__data_o \reg_5_cr_pred5__data_o
- connect \cr_pred5__ren \reg_5_cr_pred5__ren
connect \dest15__data_i \reg_5_dest15__data_i
connect \dest15__wen \reg_5_dest15__wen
connect \dest25__data_i \reg_5_dest25__data_i
connect \w5__wen \reg_5_w5__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49782.9-49803.4"
+ attribute \src "libresoc.v:49632.9-49651.4"
cell \reg_6 \reg_6
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred6__data_o \reg_6_cr_pred6__data_o
- connect \cr_pred6__ren \reg_6_cr_pred6__ren
connect \dest16__data_i \reg_6_dest16__data_i
connect \dest16__wen \reg_6_dest16__wen
connect \dest26__data_i \reg_6_dest26__data_i
connect \w6__wen \reg_6_w6__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:49804.9-49825.4"
+ attribute \src "libresoc.v:49652.9-49671.4"
cell \reg_7 \reg_7
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
- connect \cr_pred7__data_o \reg_7_cr_pred7__data_o
- connect \cr_pred7__ren \reg_7_cr_pred7__ren
connect \dest17__data_i \reg_7_dest17__data_i
connect \dest17__wen \reg_7_dest17__wen
connect \dest27__data_i \reg_7_dest27__data_i
connect \w7__data_i \reg_7_w7__data_i
connect \w7__wen \reg_7_w7__wen
end
- attribute \src "libresoc.v:49198.7-49198.20"
- process $proc$libresoc.v:49198$3071
+ attribute \src "libresoc.v:49126.7-49126.20"
+ process $proc$libresoc.v:49126$3057
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:49576.13-49576.30"
- process $proc$libresoc.v:49576$3072
+ attribute \src "libresoc.v:49452.13-49452.30"
+ process $proc$libresoc.v:49452$3058
assign { } { }
assign $1\ren_delay[7:0] 8'00000000
sync always
sync init
update \ren_delay $1\ren_delay[7:0]
end
- attribute \src "libresoc.v:49578.13-49578.35"
- process $proc$libresoc.v:49578$3073
- assign { } { }
- assign $0\ren_delay$17[7:0]$3074 8'00000000
- sync always
- sync init
- update \ren_delay$17 $0\ren_delay$17[7:0]$3074
- end
- attribute \src "libresoc.v:49582.13-49582.35"
- process $proc$libresoc.v:49582$3075
+ attribute \src "libresoc.v:49454.13-49454.35"
+ process $proc$libresoc.v:49454$3059
assign { } { }
- assign $0\ren_delay$34[7:0]$3076 8'00000000
+ assign $0\ren_delay$17[7:0]$3060 8'00000000
sync always
sync init
- update \ren_delay$34 $0\ren_delay$34[7:0]$3076
+ update \ren_delay$17 $0\ren_delay$17[7:0]$3060
end
- attribute \src "libresoc.v:49586.13-49586.35"
- process $proc$libresoc.v:49586$3077
+ attribute \src "libresoc.v:49458.13-49458.35"
+ process $proc$libresoc.v:49458$3061
assign { } { }
- assign $0\ren_delay$51[7:0]$3078 8'00000000
+ assign $0\ren_delay$34[7:0]$3062 8'00000000
sync always
sync init
- update \ren_delay$51 $0\ren_delay$51[7:0]$3078
- end
- attribute \src "libresoc.v:49642.3-49643.43"
- process $proc$libresoc.v:49642$3048
- assign { } { }
- assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next
- sync posedge \coresync_clk
- update \ren_delay$51 $0\ren_delay$51[7:0]$3049
+ update \ren_delay$34 $0\ren_delay$34[7:0]$3062
end
- attribute \src "libresoc.v:49644.3-49645.43"
- process $proc$libresoc.v:49644$3050
+ attribute \src "libresoc.v:49506.3-49507.43"
+ process $proc$libresoc.v:49506$3040
assign { } { }
- assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next
+ assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next
sync posedge \coresync_clk
- update \ren_delay$34 $0\ren_delay$34[7:0]$3051
+ update \ren_delay$34 $0\ren_delay$34[7:0]$3041
end
- attribute \src "libresoc.v:49646.3-49647.43"
- process $proc$libresoc.v:49646$3052
+ attribute \src "libresoc.v:49508.3-49509.43"
+ process $proc$libresoc.v:49508$3042
assign { } { }
- assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next
+ assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next
sync posedge \coresync_clk
- update \ren_delay$17 $0\ren_delay$17[7:0]$3053
+ update \ren_delay$17 $0\ren_delay$17[7:0]$3043
end
- attribute \src "libresoc.v:49648.3-49649.35"
- process $proc$libresoc.v:49648$3054
+ attribute \src "libresoc.v:49510.3-49511.35"
+ process $proc$libresoc.v:49510$3044
assign { } { }
assign $0\ren_delay[7:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[7:0]
end
- attribute \src "libresoc.v:49826.3-49834.6"
- process $proc$libresoc.v:49826$3055
+ attribute \src "libresoc.v:49672.3-49680.6"
+ process $proc$libresoc.v:49672$3045
assign { } { }
assign { } { }
- assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057
- attribute \src "libresoc.v:49827.5-49827.29"
+ assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047
+ attribute \src "libresoc.v:49673.5-49673.29"
switch \initial
- attribute \src "libresoc.v:49827.9-49827.17"
+ attribute \src "libresoc.v:49673.9-49673.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$17$next[7:0]$3057 8'00000000
+ assign $1\ren_delay$17$next[7:0]$3047 8'00000000
case
- assign $1\ren_delay$17$next[7:0]$3057 \src1__ren
+ assign $1\ren_delay$17$next[7:0]$3047 \src2__ren
end
sync always
- update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056
+ update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046
end
- attribute \src "libresoc.v:49835.3-49844.6"
- process $proc$libresoc.v:49835$3058
- assign { } { }
- assign { } { }
- assign $0\src1__data_o[3:0] $1\src1__data_o[3:0]
- attribute \src "libresoc.v:49836.5-49836.29"
- switch \initial
- attribute \src "libresoc.v:49836.9-49836.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172"
- switch \$18
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\src1__data_o[3:0] \$32
- case
- assign $1\src1__data_o[3:0] 4'0000
- end
- sync always
- update \src1__data_o $0\src1__data_o[3:0]
- end
- attribute \src "libresoc.v:49845.3-49853.6"
- process $proc$libresoc.v:49845$3059
- assign { } { }
- assign { } { }
- assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061
- attribute \src "libresoc.v:49846.5-49846.29"
- switch \initial
- attribute \src "libresoc.v:49846.9-49846.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ren_delay$34$next[7:0]$3061 8'00000000
- case
- assign $1\ren_delay$34$next[7:0]$3061 \src2__ren
- end
- sync always
- update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060
- end
- attribute \src "libresoc.v:49854.3-49863.6"
- process $proc$libresoc.v:49854$3062
+ attribute \src "libresoc.v:49681.3-49690.6"
+ process $proc$libresoc.v:49681$3048
assign { } { }
assign { } { }
assign $0\src2__data_o[3:0] $1\src2__data_o[3:0]
- attribute \src "libresoc.v:49855.5-49855.29"
+ attribute \src "libresoc.v:49682.5-49682.29"
switch \initial
- attribute \src "libresoc.v:49855.9-49855.17"
+ attribute \src "libresoc.v:49682.9-49682.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172"
- switch \$35
+ switch \$18
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src2__data_o[3:0] \$49
+ assign $1\src2__data_o[3:0] \$32
case
assign $1\src2__data_o[3:0] 4'0000
end
sync always
update \src2__data_o $0\src2__data_o[3:0]
end
- attribute \src "libresoc.v:49864.3-49872.6"
- process $proc$libresoc.v:49864$3063
+ attribute \src "libresoc.v:49691.3-49699.6"
+ process $proc$libresoc.v:49691$3049
assign { } { }
assign { } { }
- assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065
- attribute \src "libresoc.v:49865.5-49865.29"
+ assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051
+ attribute \src "libresoc.v:49692.5-49692.29"
switch \initial
- attribute \src "libresoc.v:49865.9-49865.17"
+ attribute \src "libresoc.v:49692.9-49692.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$51$next[7:0]$3065 8'00000000
+ assign $1\ren_delay$34$next[7:0]$3051 8'00000000
case
- assign $1\ren_delay$51$next[7:0]$3065 \src3__ren
+ assign $1\ren_delay$34$next[7:0]$3051 \src3__ren
end
sync always
- update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064
+ update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050
end
- attribute \src "libresoc.v:49873.3-49882.6"
- process $proc$libresoc.v:49873$3066
+ attribute \src "libresoc.v:49700.3-49709.6"
+ process $proc$libresoc.v:49700$3052
assign { } { }
assign { } { }
assign $0\src3__data_o[3:0] $1\src3__data_o[3:0]
- attribute \src "libresoc.v:49874.5-49874.29"
+ attribute \src "libresoc.v:49701.5-49701.29"
switch \initial
- attribute \src "libresoc.v:49874.9-49874.17"
+ attribute \src "libresoc.v:49701.9-49701.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172"
- switch \$52
+ switch \$35
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src3__data_o[3:0] \$66
+ assign $1\src3__data_o[3:0] \$49
case
assign $1\src3__data_o[3:0] 4'0000
end
sync always
update \src3__data_o $0\src3__data_o[3:0]
end
- attribute \src "libresoc.v:49883.3-49891.6"
- process $proc$libresoc.v:49883$3067
+ attribute \src "libresoc.v:49710.3-49718.6"
+ process $proc$libresoc.v:49710$3053
assign { } { }
assign { } { }
- assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069
- attribute \src "libresoc.v:49884.5-49884.29"
+ assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055
+ attribute \src "libresoc.v:49711.5-49711.29"
switch \initial
- attribute \src "libresoc.v:49884.9-49884.17"
+ attribute \src "libresoc.v:49711.9-49711.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[7:0]$3069 8'00000000
+ assign $1\ren_delay$next[7:0]$3055 8'00000000
case
- assign $1\ren_delay$next[7:0]$3069 \cr_pred__ren
+ assign $1\ren_delay$next[7:0]$3055 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[7:0]$3068
+ update \ren_delay$next $0\ren_delay$next[7:0]$3054
end
- attribute \src "libresoc.v:49892.3-49901.6"
- process $proc$libresoc.v:49892$3070
+ attribute \src "libresoc.v:49719.3-49728.6"
+ process $proc$libresoc.v:49719$3056
assign { } { }
assign { } { }
- assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0]
- attribute \src "libresoc.v:49893.5-49893.29"
+ assign $0\src1__data_o[3:0] $1\src1__data_o[3:0]
+ attribute \src "libresoc.v:49720.5-49720.29"
switch \initial
- attribute \src "libresoc.v:49893.9-49893.17"
+ attribute \src "libresoc.v:49720.9-49720.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\cr_pred__data_o[3:0] \$15
- case
- assign $1\cr_pred__data_o[3:0] 4'0000
- end
- sync always
- update \cr_pred__data_o $0\cr_pred__data_o[3:0]
- end
- connect \$9 $or$libresoc.v:49610$3016_Y
- connect \$11 $or$libresoc.v:49611$3017_Y
- connect \$13 $or$libresoc.v:49612$3018_Y
- connect \$15 $or$libresoc.v:49613$3019_Y
- connect \$18 $reduce_or$libresoc.v:49614$3020_Y
- connect \$1 $reduce_or$libresoc.v:49615$3021_Y
- connect \$20 $or$libresoc.v:49616$3022_Y
- connect \$22 $or$libresoc.v:49617$3023_Y
- connect \$24 $or$libresoc.v:49618$3024_Y
- connect \$26 $or$libresoc.v:49619$3025_Y
- connect \$28 $or$libresoc.v:49620$3026_Y
- connect \$30 $or$libresoc.v:49621$3027_Y
- connect \$32 $or$libresoc.v:49622$3028_Y
- connect \$35 $reduce_or$libresoc.v:49623$3029_Y
- connect \$37 $or$libresoc.v:49624$3030_Y
- connect \$3 $or$libresoc.v:49625$3031_Y
- connect \$39 $or$libresoc.v:49626$3032_Y
- connect \$41 $or$libresoc.v:49627$3033_Y
- connect \$43 $or$libresoc.v:49628$3034_Y
- connect \$45 $or$libresoc.v:49629$3035_Y
- connect \$47 $or$libresoc.v:49630$3036_Y
- connect \$49 $or$libresoc.v:49631$3037_Y
- connect \$52 $reduce_or$libresoc.v:49632$3038_Y
- connect \$54 $or$libresoc.v:49633$3039_Y
- connect \$56 $or$libresoc.v:49634$3040_Y
- connect \$58 $or$libresoc.v:49635$3041_Y
- connect \$5 $or$libresoc.v:49636$3042_Y
- connect \$60 $or$libresoc.v:49637$3043_Y
- connect \$62 $or$libresoc.v:49638$3044_Y
- connect \$64 $or$libresoc.v:49639$3045_Y
- connect \$66 $or$libresoc.v:49640$3046_Y
- connect \$7 $or$libresoc.v:49641$3047_Y
- connect \cr_pred__ren 8'00000000
- connect \wen$68 8'00000000
- connect \data_i$69 4'0000
+ assign $1\src1__data_o[3:0] \$15
+ case
+ assign $1\src1__data_o[3:0] 4'0000
+ end
+ sync always
+ update \src1__data_o $0\src1__data_o[3:0]
+ end
+ connect \$9 $or$libresoc.v:49482$3016_Y
+ connect \$11 $or$libresoc.v:49483$3017_Y
+ connect \$13 $or$libresoc.v:49484$3018_Y
+ connect \$15 $or$libresoc.v:49485$3019_Y
+ connect \$18 $reduce_or$libresoc.v:49486$3020_Y
+ connect \$1 $reduce_or$libresoc.v:49487$3021_Y
+ connect \$20 $or$libresoc.v:49488$3022_Y
+ connect \$22 $or$libresoc.v:49489$3023_Y
+ connect \$24 $or$libresoc.v:49490$3024_Y
+ connect \$26 $or$libresoc.v:49491$3025_Y
+ connect \$28 $or$libresoc.v:49492$3026_Y
+ connect \$30 $or$libresoc.v:49493$3027_Y
+ connect \$32 $or$libresoc.v:49494$3028_Y
+ connect \$35 $reduce_or$libresoc.v:49495$3029_Y
+ connect \$37 $or$libresoc.v:49496$3030_Y
+ connect \$3 $or$libresoc.v:49497$3031_Y
+ connect \$39 $or$libresoc.v:49498$3032_Y
+ connect \$41 $or$libresoc.v:49499$3033_Y
+ connect \$43 $or$libresoc.v:49500$3034_Y
+ connect \$45 $or$libresoc.v:49501$3035_Y
+ connect \$47 $or$libresoc.v:49502$3036_Y
+ connect \$49 $or$libresoc.v:49503$3037_Y
+ connect \$5 $or$libresoc.v:49504$3038_Y
+ connect \$7 $or$libresoc.v:49505$3039_Y
+ connect \wen$51 8'00000000
+ connect \data_i$52 4'0000
connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen
connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i
connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren
connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
- connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000
end
-attribute \src "libresoc.v:49937.1-50994.10"
+attribute \src "libresoc.v:49762.1-50819.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0"
attribute \generator "nMigen"
module \cr0
- attribute \src "libresoc.v:50595.3-50596.25"
+ attribute \src "libresoc.v:50420.3-50421.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198
- attribute \src "libresoc.v:50567.3-50568.61"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182
+ attribute \src "libresoc.v:50392.3-50393.61"
wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199
- attribute \src "libresoc.v:50569.3-50570.55"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183
+ attribute \src "libresoc.v:50394.3-50395.55"
wire width 32 $0\alu_cr0_cr_op__insn[31:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200
- attribute \src "libresoc.v:50565.3-50566.65"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184
+ attribute \src "libresoc.v:50390.3-50391.65"
wire width 7 $0\alu_cr0_cr_op__insn_type[6:0]
- attribute \src "libresoc.v:50593.3-50594.39"
+ attribute \src "libresoc.v:50418.3-50419.39"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:50915.3-50923.6"
- wire $0\alu_l_r_alu$next[0:0]$3250
- attribute \src "libresoc.v:50537.3-50538.39"
+ attribute \src "libresoc.v:50740.3-50748.6"
+ wire $0\alu_l_r_alu$next[0:0]$3234
+ attribute \src "libresoc.v:50362.3-50363.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:50906.3-50914.6"
- wire $0\alui_l_r_alui$next[0:0]$3247
- attribute \src "libresoc.v:50539.3-50540.43"
+ attribute \src "libresoc.v:50731.3-50739.6"
+ wire $0\alui_l_r_alui$next[0:0]$3231
+ attribute \src "libresoc.v:50364.3-50365.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:50780.3-50801.6"
- wire width 64 $0\data_r0__o$next[63:0]$3205
- attribute \src "libresoc.v:50561.3-50562.37"
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire width 64 $0\data_r0__o$next[63:0]$3189
+ attribute \src "libresoc.v:50386.3-50387.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:50780.3-50801.6"
- wire $0\data_r0__o_ok$next[0:0]$3206
- attribute \src "libresoc.v:50563.3-50564.43"
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire $0\data_r0__o_ok$next[0:0]$3190
+ attribute \src "libresoc.v:50388.3-50389.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:50802.3-50823.6"
- wire width 32 $0\data_r1__full_cr$next[31:0]$3213
- attribute \src "libresoc.v:50557.3-50558.49"
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire width 32 $0\data_r1__full_cr$next[31:0]$3197
+ attribute \src "libresoc.v:50382.3-50383.49"
wire width 32 $0\data_r1__full_cr[31:0]
- attribute \src "libresoc.v:50802.3-50823.6"
- wire $0\data_r1__full_cr_ok$next[0:0]$3214
- attribute \src "libresoc.v:50559.3-50560.55"
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire $0\data_r1__full_cr_ok$next[0:0]$3198
+ attribute \src "libresoc.v:50384.3-50385.55"
wire $0\data_r1__full_cr_ok[0:0]
- attribute \src "libresoc.v:50824.3-50845.6"
- wire width 4 $0\data_r2__cr_a$next[3:0]$3221
- attribute \src "libresoc.v:50553.3-50554.43"
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire width 4 $0\data_r2__cr_a$next[3:0]$3205
+ attribute \src "libresoc.v:50378.3-50379.43"
wire width 4 $0\data_r2__cr_a[3:0]
- attribute \src "libresoc.v:50824.3-50845.6"
- wire $0\data_r2__cr_a_ok$next[0:0]$3222
- attribute \src "libresoc.v:50555.3-50556.49"
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire $0\data_r2__cr_a_ok$next[0:0]$3206
+ attribute \src "libresoc.v:50380.3-50381.49"
wire $0\data_r2__cr_a_ok[0:0]
- attribute \src "libresoc.v:50924.3-50933.6"
+ attribute \src "libresoc.v:50749.3-50758.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:50934.3-50943.6"
+ attribute \src "libresoc.v:50759.3-50768.6"
wire width 32 $0\dest2_o[31:0]
- attribute \src "libresoc.v:50944.3-50953.6"
+ attribute \src "libresoc.v:50769.3-50778.6"
wire width 4 $0\dest3_o[3:0]
- attribute \src "libresoc.v:49938.7-49938.20"
+ attribute \src "libresoc.v:49763.7-49763.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:50723.3-50731.6"
- wire $0\opc_l_r_opc$next[0:0]$3183
- attribute \src "libresoc.v:50579.3-50580.39"
+ attribute \src "libresoc.v:50548.3-50556.6"
+ wire $0\opc_l_r_opc$next[0:0]$3167
+ attribute \src "libresoc.v:50404.3-50405.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:50714.3-50722.6"
- wire $0\opc_l_s_opc$next[0:0]$3180
- attribute \src "libresoc.v:50581.3-50582.39"
+ attribute \src "libresoc.v:50539.3-50547.6"
+ wire $0\opc_l_s_opc$next[0:0]$3164
+ attribute \src "libresoc.v:50406.3-50407.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:50954.3-50962.6"
- wire width 3 $0\prev_wr_go$next[2:0]$3256
- attribute \src "libresoc.v:50591.3-50592.37"
+ attribute \src "libresoc.v:50779.3-50787.6"
+ wire width 3 $0\prev_wr_go$next[2:0]$3240
+ attribute \src "libresoc.v:50416.3-50417.37"
wire width 3 $0\prev_wr_go[2:0]
- attribute \src "libresoc.v:50668.3-50677.6"
+ attribute \src "libresoc.v:50493.3-50502.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:50759.3-50767.6"
- wire width 3 $0\req_l_r_req$next[2:0]$3195
- attribute \src "libresoc.v:50571.3-50572.39"
+ attribute \src "libresoc.v:50584.3-50592.6"
+ wire width 3 $0\req_l_r_req$next[2:0]$3179
+ attribute \src "libresoc.v:50396.3-50397.39"
wire width 3 $0\req_l_r_req[2:0]
- attribute \src "libresoc.v:50750.3-50758.6"
- wire width 3 $0\req_l_s_req$next[2:0]$3192
- attribute \src "libresoc.v:50573.3-50574.39"
+ attribute \src "libresoc.v:50575.3-50583.6"
+ wire width 3 $0\req_l_s_req$next[2:0]$3176
+ attribute \src "libresoc.v:50398.3-50399.39"
wire width 3 $0\req_l_s_req[2:0]
- attribute \src "libresoc.v:50687.3-50695.6"
- wire $0\rok_l_r_rdok$next[0:0]$3171
- attribute \src "libresoc.v:50587.3-50588.41"
+ attribute \src "libresoc.v:50512.3-50520.6"
+ wire $0\rok_l_r_rdok$next[0:0]$3155
+ attribute \src "libresoc.v:50412.3-50413.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:50678.3-50686.6"
- wire $0\rok_l_s_rdok$next[0:0]$3168
- attribute \src "libresoc.v:50589.3-50590.41"
+ attribute \src "libresoc.v:50503.3-50511.6"
+ wire $0\rok_l_s_rdok$next[0:0]$3152
+ attribute \src "libresoc.v:50414.3-50415.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:50705.3-50713.6"
- wire $0\rst_l_r_rst$next[0:0]$3177
- attribute \src "libresoc.v:50583.3-50584.39"
+ attribute \src "libresoc.v:50530.3-50538.6"
+ wire $0\rst_l_r_rst$next[0:0]$3161
+ attribute \src "libresoc.v:50408.3-50409.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:50696.3-50704.6"
- wire $0\rst_l_s_rst$next[0:0]$3174
- attribute \src "libresoc.v:50585.3-50586.39"
+ attribute \src "libresoc.v:50521.3-50529.6"
+ wire $0\rst_l_s_rst$next[0:0]$3158
+ attribute \src "libresoc.v:50410.3-50411.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:50741.3-50749.6"
- wire width 6 $0\src_l_r_src$next[5:0]$3189
- attribute \src "libresoc.v:50575.3-50576.39"
+ attribute \src "libresoc.v:50566.3-50574.6"
+ wire width 6 $0\src_l_r_src$next[5:0]$3173
+ attribute \src "libresoc.v:50400.3-50401.39"
wire width 6 $0\src_l_r_src[5:0]
- attribute \src "libresoc.v:50732.3-50740.6"
- wire width 6 $0\src_l_s_src$next[5:0]$3186
- attribute \src "libresoc.v:50577.3-50578.39"
+ attribute \src "libresoc.v:50557.3-50565.6"
+ wire width 6 $0\src_l_s_src$next[5:0]$3170
+ attribute \src "libresoc.v:50402.3-50403.39"
wire width 6 $0\src_l_s_src[5:0]
- attribute \src "libresoc.v:50846.3-50855.6"
- wire width 64 $0\src_r0$next[63:0]$3229
- attribute \src "libresoc.v:50551.3-50552.29"
+ attribute \src "libresoc.v:50671.3-50680.6"
+ wire width 64 $0\src_r0$next[63:0]$3213
+ attribute \src "libresoc.v:50376.3-50377.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:50856.3-50865.6"
- wire width 64 $0\src_r1$next[63:0]$3232
- attribute \src "libresoc.v:50549.3-50550.29"
+ attribute \src "libresoc.v:50681.3-50690.6"
+ wire width 64 $0\src_r1$next[63:0]$3216
+ attribute \src "libresoc.v:50374.3-50375.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:50866.3-50875.6"
- wire width 32 $0\src_r2$next[31:0]$3235
- attribute \src "libresoc.v:50547.3-50548.29"
+ attribute \src "libresoc.v:50691.3-50700.6"
+ wire width 32 $0\src_r2$next[31:0]$3219
+ attribute \src "libresoc.v:50372.3-50373.29"
wire width 32 $0\src_r2[31:0]
- attribute \src "libresoc.v:50876.3-50885.6"
- wire width 4 $0\src_r3$next[3:0]$3238
- attribute \src "libresoc.v:50545.3-50546.29"
+ attribute \src "libresoc.v:50701.3-50710.6"
+ wire width 4 $0\src_r3$next[3:0]$3222
+ attribute \src "libresoc.v:50370.3-50371.29"
wire width 4 $0\src_r3[3:0]
- attribute \src "libresoc.v:50886.3-50895.6"
- wire width 4 $0\src_r4$next[3:0]$3241
- attribute \src "libresoc.v:50543.3-50544.29"
+ attribute \src "libresoc.v:50711.3-50720.6"
+ wire width 4 $0\src_r4$next[3:0]$3225
+ attribute \src "libresoc.v:50368.3-50369.29"
wire width 4 $0\src_r4[3:0]
- attribute \src "libresoc.v:50896.3-50905.6"
- wire width 4 $0\src_r5$next[3:0]$3244
- attribute \src "libresoc.v:50541.3-50542.29"
+ attribute \src "libresoc.v:50721.3-50730.6"
+ wire width 4 $0\src_r5$next[3:0]$3228
+ attribute \src "libresoc.v:50366.3-50367.29"
wire width 4 $0\src_r5[3:0]
- attribute \src "libresoc.v:50056.7-50056.24"
+ attribute \src "libresoc.v:49881.7-49881.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201
- attribute \src "libresoc.v:50087.14-50087.47"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185
+ attribute \src "libresoc.v:49912.14-49912.47"
wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202
- attribute \src "libresoc.v:50091.14-50091.41"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186
+ attribute \src "libresoc.v:49916.14-49916.41"
wire width 32 $1\alu_cr0_cr_op__insn[31:0]
- attribute \src "libresoc.v:50768.3-50779.6"
- wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203
- attribute \src "libresoc.v:50170.13-50170.45"
+ attribute \src "libresoc.v:50593.3-50604.6"
+ wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187
+ attribute \src "libresoc.v:49995.13-49995.45"
wire width 7 $1\alu_cr0_cr_op__insn_type[6:0]
- attribute \src "libresoc.v:50194.7-50194.26"
+ attribute \src "libresoc.v:50019.7-50019.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:50915.3-50923.6"
- wire $1\alu_l_r_alu$next[0:0]$3251
- attribute \src "libresoc.v:50202.7-50202.25"
+ attribute \src "libresoc.v:50740.3-50748.6"
+ wire $1\alu_l_r_alu$next[0:0]$3235
+ attribute \src "libresoc.v:50027.7-50027.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:50906.3-50914.6"
- wire $1\alui_l_r_alui$next[0:0]$3248
- attribute \src "libresoc.v:50214.7-50214.27"
+ attribute \src "libresoc.v:50731.3-50739.6"
+ wire $1\alui_l_r_alui$next[0:0]$3232
+ attribute \src "libresoc.v:50039.7-50039.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:50780.3-50801.6"
- wire width 64 $1\data_r0__o$next[63:0]$3207
- attribute \src "libresoc.v:50248.14-50248.47"
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire width 64 $1\data_r0__o$next[63:0]$3191
+ attribute \src "libresoc.v:50073.14-50073.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:50780.3-50801.6"
- wire $1\data_r0__o_ok$next[0:0]$3208
- attribute \src "libresoc.v:50252.7-50252.27"
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire $1\data_r0__o_ok$next[0:0]$3192
+ attribute \src "libresoc.v:50077.7-50077.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:50802.3-50823.6"
- wire width 32 $1\data_r1__full_cr$next[31:0]$3215
- attribute \src "libresoc.v:50256.14-50256.38"
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire width 32 $1\data_r1__full_cr$next[31:0]$3199
+ attribute \src "libresoc.v:50081.14-50081.38"
wire width 32 $1\data_r1__full_cr[31:0]
- attribute \src "libresoc.v:50802.3-50823.6"
- wire $1\data_r1__full_cr_ok$next[0:0]$3216
- attribute \src "libresoc.v:50260.7-50260.33"
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire $1\data_r1__full_cr_ok$next[0:0]$3200
+ attribute \src "libresoc.v:50085.7-50085.33"
wire $1\data_r1__full_cr_ok[0:0]
- attribute \src "libresoc.v:50824.3-50845.6"
- wire width 4 $1\data_r2__cr_a$next[3:0]$3223
- attribute \src "libresoc.v:50264.13-50264.33"
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire width 4 $1\data_r2__cr_a$next[3:0]$3207
+ attribute \src "libresoc.v:50089.13-50089.33"
wire width 4 $1\data_r2__cr_a[3:0]
- attribute \src "libresoc.v:50824.3-50845.6"
- wire $1\data_r2__cr_a_ok$next[0:0]$3224
- attribute \src "libresoc.v:50268.7-50268.30"
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire $1\data_r2__cr_a_ok$next[0:0]$3208
+ attribute \src "libresoc.v:50093.7-50093.30"
wire $1\data_r2__cr_a_ok[0:0]
- attribute \src "libresoc.v:50924.3-50933.6"
+ attribute \src "libresoc.v:50749.3-50758.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:50934.3-50943.6"
+ attribute \src "libresoc.v:50759.3-50768.6"
wire width 32 $1\dest2_o[31:0]
- attribute \src "libresoc.v:50944.3-50953.6"
+ attribute \src "libresoc.v:50769.3-50778.6"
wire width 4 $1\dest3_o[3:0]
- attribute \src "libresoc.v:50723.3-50731.6"
- wire $1\opc_l_r_opc$next[0:0]$3184
- attribute \src "libresoc.v:50287.7-50287.25"
+ attribute \src "libresoc.v:50548.3-50556.6"
+ wire $1\opc_l_r_opc$next[0:0]$3168
+ attribute \src "libresoc.v:50112.7-50112.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:50714.3-50722.6"
- wire $1\opc_l_s_opc$next[0:0]$3181
- attribute \src "libresoc.v:50291.7-50291.25"
+ attribute \src "libresoc.v:50539.3-50547.6"
+ wire $1\opc_l_s_opc$next[0:0]$3165
+ attribute \src "libresoc.v:50116.7-50116.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:50954.3-50962.6"
- wire width 3 $1\prev_wr_go$next[2:0]$3257
- attribute \src "libresoc.v:50391.13-50391.30"
+ attribute \src "libresoc.v:50779.3-50787.6"
+ wire width 3 $1\prev_wr_go$next[2:0]$3241
+ attribute \src "libresoc.v:50216.13-50216.30"
wire width 3 $1\prev_wr_go[2:0]
- attribute \src "libresoc.v:50668.3-50677.6"
+ attribute \src "libresoc.v:50493.3-50502.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:50759.3-50767.6"
- wire width 3 $1\req_l_r_req$next[2:0]$3196
- attribute \src "libresoc.v:50399.13-50399.31"
+ attribute \src "libresoc.v:50584.3-50592.6"
+ wire width 3 $1\req_l_r_req$next[2:0]$3180
+ attribute \src "libresoc.v:50224.13-50224.31"
wire width 3 $1\req_l_r_req[2:0]
- attribute \src "libresoc.v:50750.3-50758.6"
- wire width 3 $1\req_l_s_req$next[2:0]$3193
- attribute \src "libresoc.v:50403.13-50403.31"
+ attribute \src "libresoc.v:50575.3-50583.6"
+ wire width 3 $1\req_l_s_req$next[2:0]$3177
+ attribute \src "libresoc.v:50228.13-50228.31"
wire width 3 $1\req_l_s_req[2:0]
- attribute \src "libresoc.v:50687.3-50695.6"
- wire $1\rok_l_r_rdok$next[0:0]$3172
- attribute \src "libresoc.v:50415.7-50415.26"
+ attribute \src "libresoc.v:50512.3-50520.6"
+ wire $1\rok_l_r_rdok$next[0:0]$3156
+ attribute \src "libresoc.v:50240.7-50240.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:50678.3-50686.6"
- wire $1\rok_l_s_rdok$next[0:0]$3169
- attribute \src "libresoc.v:50419.7-50419.26"
+ attribute \src "libresoc.v:50503.3-50511.6"
+ wire $1\rok_l_s_rdok$next[0:0]$3153
+ attribute \src "libresoc.v:50244.7-50244.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:50705.3-50713.6"
- wire $1\rst_l_r_rst$next[0:0]$3178
- attribute \src "libresoc.v:50423.7-50423.25"
+ attribute \src "libresoc.v:50530.3-50538.6"
+ wire $1\rst_l_r_rst$next[0:0]$3162
+ attribute \src "libresoc.v:50248.7-50248.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:50696.3-50704.6"
- wire $1\rst_l_s_rst$next[0:0]$3175
- attribute \src "libresoc.v:50427.7-50427.25"
+ attribute \src "libresoc.v:50521.3-50529.6"
+ wire $1\rst_l_s_rst$next[0:0]$3159
+ attribute \src "libresoc.v:50252.7-50252.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:50741.3-50749.6"
- wire width 6 $1\src_l_r_src$next[5:0]$3190
- attribute \src "libresoc.v:50447.13-50447.32"
+ attribute \src "libresoc.v:50566.3-50574.6"
+ wire width 6 $1\src_l_r_src$next[5:0]$3174
+ attribute \src "libresoc.v:50272.13-50272.32"
wire width 6 $1\src_l_r_src[5:0]
- attribute \src "libresoc.v:50732.3-50740.6"
- wire width 6 $1\src_l_s_src$next[5:0]$3187
- attribute \src "libresoc.v:50451.13-50451.32"
+ attribute \src "libresoc.v:50557.3-50565.6"
+ wire width 6 $1\src_l_s_src$next[5:0]$3171
+ attribute \src "libresoc.v:50276.13-50276.32"
wire width 6 $1\src_l_s_src[5:0]
- attribute \src "libresoc.v:50846.3-50855.6"
- wire width 64 $1\src_r0$next[63:0]$3230
- attribute \src "libresoc.v:50455.14-50455.43"
+ attribute \src "libresoc.v:50671.3-50680.6"
+ wire width 64 $1\src_r0$next[63:0]$3214
+ attribute \src "libresoc.v:50280.14-50280.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:50856.3-50865.6"
- wire width 64 $1\src_r1$next[63:0]$3233
- attribute \src "libresoc.v:50459.14-50459.43"
+ attribute \src "libresoc.v:50681.3-50690.6"
+ wire width 64 $1\src_r1$next[63:0]$3217
+ attribute \src "libresoc.v:50284.14-50284.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:50866.3-50875.6"
- wire width 32 $1\src_r2$next[31:0]$3236
- attribute \src "libresoc.v:50463.14-50463.28"
+ attribute \src "libresoc.v:50691.3-50700.6"
+ wire width 32 $1\src_r2$next[31:0]$3220
+ attribute \src "libresoc.v:50288.14-50288.28"
wire width 32 $1\src_r2[31:0]
- attribute \src "libresoc.v:50876.3-50885.6"
- wire width 4 $1\src_r3$next[3:0]$3239
- attribute \src "libresoc.v:50467.13-50467.26"
+ attribute \src "libresoc.v:50701.3-50710.6"
+ wire width 4 $1\src_r3$next[3:0]$3223
+ attribute \src "libresoc.v:50292.13-50292.26"
wire width 4 $1\src_r3[3:0]
- attribute \src "libresoc.v:50886.3-50895.6"
- wire width 4 $1\src_r4$next[3:0]$3242
- attribute \src "libresoc.v:50471.13-50471.26"
+ attribute \src "libresoc.v:50711.3-50720.6"
+ wire width 4 $1\src_r4$next[3:0]$3226
+ attribute \src "libresoc.v:50296.13-50296.26"
wire width 4 $1\src_r4[3:0]
- attribute \src "libresoc.v:50896.3-50905.6"
- wire width 4 $1\src_r5$next[3:0]$3245
- attribute \src "libresoc.v:50475.13-50475.26"
+ attribute \src "libresoc.v:50721.3-50730.6"
+ wire width 4 $1\src_r5$next[3:0]$3229
+ attribute \src "libresoc.v:50300.13-50300.26"
wire width 4 $1\src_r5[3:0]
- attribute \src "libresoc.v:50780.3-50801.6"
- wire width 64 $2\data_r0__o$next[63:0]$3209
- attribute \src "libresoc.v:50780.3-50801.6"
- wire $2\data_r0__o_ok$next[0:0]$3210
- attribute \src "libresoc.v:50802.3-50823.6"
- wire width 32 $2\data_r1__full_cr$next[31:0]$3217
- attribute \src "libresoc.v:50802.3-50823.6"
- wire $2\data_r1__full_cr_ok$next[0:0]$3218
- attribute \src "libresoc.v:50824.3-50845.6"
- wire width 4 $2\data_r2__cr_a$next[3:0]$3225
- attribute \src "libresoc.v:50824.3-50845.6"
- wire $2\data_r2__cr_a_ok$next[0:0]$3226
- attribute \src "libresoc.v:50780.3-50801.6"
- wire $3\data_r0__o_ok$next[0:0]$3211
- attribute \src "libresoc.v:50802.3-50823.6"
- wire $3\data_r1__full_cr_ok$next[0:0]$3219
- attribute \src "libresoc.v:50824.3-50845.6"
- wire $3\data_r2__cr_a_ok$next[0:0]$3227
- attribute \src "libresoc.v:50481.18-50481.112"
- wire width 6 $and$libresoc.v:50481$3080_Y
- attribute \src "libresoc.v:50482.19-50482.125"
- wire $and$libresoc.v:50482$3081_Y
- attribute \src "libresoc.v:50483.19-50483.125"
- wire $and$libresoc.v:50483$3082_Y
- attribute \src "libresoc.v:50484.19-50484.125"
- wire $and$libresoc.v:50484$3083_Y
- attribute \src "libresoc.v:50485.19-50485.141"
- wire width 3 $and$libresoc.v:50485$3084_Y
- attribute \src "libresoc.v:50486.19-50486.121"
- wire width 3 $and$libresoc.v:50486$3085_Y
- attribute \src "libresoc.v:50487.19-50487.127"
- wire $and$libresoc.v:50487$3086_Y
- attribute \src "libresoc.v:50488.19-50488.127"
- wire $and$libresoc.v:50488$3087_Y
- attribute \src "libresoc.v:50489.19-50489.127"
- wire $and$libresoc.v:50489$3088_Y
- attribute \src "libresoc.v:50490.18-50490.110"
- wire $and$libresoc.v:50490$3089_Y
- attribute \src "libresoc.v:50492.18-50492.98"
- wire $and$libresoc.v:50492$3091_Y
- attribute \src "libresoc.v:50494.18-50494.100"
- wire $and$libresoc.v:50494$3093_Y
- attribute \src "libresoc.v:50495.18-50495.149"
- wire width 3 $and$libresoc.v:50495$3094_Y
- attribute \src "libresoc.v:50497.18-50497.119"
- wire width 3 $and$libresoc.v:50497$3096_Y
- attribute \src "libresoc.v:50500.18-50500.116"
- wire $and$libresoc.v:50500$3099_Y
- attribute \src "libresoc.v:50504.17-50504.123"
- wire $and$libresoc.v:50504$3103_Y
- attribute \src "libresoc.v:50506.18-50506.113"
- wire $and$libresoc.v:50506$3105_Y
- attribute \src "libresoc.v:50507.18-50507.125"
- wire width 3 $and$libresoc.v:50507$3106_Y
- attribute \src "libresoc.v:50509.18-50509.112"
- wire $and$libresoc.v:50509$3108_Y
- attribute \src "libresoc.v:50511.18-50511.125"
- wire $and$libresoc.v:50511$3110_Y
- attribute \src "libresoc.v:50512.18-50512.125"
- wire $and$libresoc.v:50512$3111_Y
- attribute \src "libresoc.v:50513.18-50513.117"
- wire $and$libresoc.v:50513$3112_Y
- attribute \src "libresoc.v:50518.18-50518.129"
- wire $and$libresoc.v:50518$3117_Y
- attribute \src "libresoc.v:50519.18-50519.124"
- wire width 3 $and$libresoc.v:50519$3118_Y
- attribute \src "libresoc.v:50522.18-50522.116"
- wire $and$libresoc.v:50522$3121_Y
- attribute \src "libresoc.v:50523.18-50523.122"
- wire $and$libresoc.v:50523$3122_Y
- attribute \src "libresoc.v:50524.18-50524.119"
- wire $and$libresoc.v:50524$3123_Y
- attribute \src "libresoc.v:50532.18-50532.133"
- wire $and$libresoc.v:50532$3131_Y
- attribute \src "libresoc.v:50533.18-50533.131"
- wire $and$libresoc.v:50533$3132_Y
- attribute \src "libresoc.v:50534.18-50534.182"
- wire width 6 $and$libresoc.v:50534$3133_Y
- attribute \src "libresoc.v:50535.18-50535.113"
- wire width 6 $and$libresoc.v:50535$3134_Y
- attribute \src "libresoc.v:50508.18-50508.113"
- wire $eq$libresoc.v:50508$3107_Y
- attribute \src "libresoc.v:50510.18-50510.119"
- wire $eq$libresoc.v:50510$3109_Y
- attribute \src "libresoc.v:50491.18-50491.97"
- wire $not$libresoc.v:50491$3090_Y
- attribute \src "libresoc.v:50493.18-50493.99"
- wire $not$libresoc.v:50493$3092_Y
- attribute \src "libresoc.v:50496.18-50496.113"
- wire width 3 $not$libresoc.v:50496$3095_Y
- attribute \src "libresoc.v:50499.18-50499.106"
- wire $not$libresoc.v:50499$3098_Y
- attribute \src "libresoc.v:50505.18-50505.119"
- wire $not$libresoc.v:50505$3104_Y
- attribute \src "libresoc.v:50520.17-50520.113"
- wire width 6 $not$libresoc.v:50520$3119_Y
- attribute \src "libresoc.v:50536.18-50536.114"
- wire width 6 $not$libresoc.v:50536$3135_Y
- attribute \src "libresoc.v:50503.18-50503.112"
- wire $or$libresoc.v:50503$3102_Y
- attribute \src "libresoc.v:50514.18-50514.122"
- wire $or$libresoc.v:50514$3113_Y
- attribute \src "libresoc.v:50515.18-50515.124"
- wire $or$libresoc.v:50515$3114_Y
- attribute \src "libresoc.v:50516.18-50516.155"
- wire width 3 $or$libresoc.v:50516$3115_Y
- attribute \src "libresoc.v:50517.18-50517.194"
- wire width 6 $or$libresoc.v:50517$3116_Y
- attribute \src "libresoc.v:50521.18-50521.120"
- wire width 3 $or$libresoc.v:50521$3120_Y
- attribute \src "libresoc.v:50531.17-50531.117"
- wire width 6 $or$libresoc.v:50531$3130_Y
- attribute \src "libresoc.v:50480.17-50480.104"
- wire $reduce_and$libresoc.v:50480$3079_Y
- attribute \src "libresoc.v:50498.18-50498.106"
- wire $reduce_or$libresoc.v:50498$3097_Y
- attribute \src "libresoc.v:50501.18-50501.113"
- wire $reduce_or$libresoc.v:50501$3100_Y
- attribute \src "libresoc.v:50502.18-50502.112"
- wire $reduce_or$libresoc.v:50502$3101_Y
- attribute \src "libresoc.v:50525.18-50525.118"
- wire width 64 $ternary$libresoc.v:50525$3124_Y
- attribute \src "libresoc.v:50526.18-50526.118"
- wire width 64 $ternary$libresoc.v:50526$3125_Y
- attribute \src "libresoc.v:50527.18-50527.118"
- wire width 32 $ternary$libresoc.v:50527$3126_Y
- attribute \src "libresoc.v:50528.18-50528.118"
- wire width 4 $ternary$libresoc.v:50528$3127_Y
- attribute \src "libresoc.v:50529.18-50529.118"
- wire width 4 $ternary$libresoc.v:50529$3128_Y
- attribute \src "libresoc.v:50530.18-50530.118"
- wire width 4 $ternary$libresoc.v:50530$3129_Y
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire width 64 $2\data_r0__o$next[63:0]$3193
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire $2\data_r0__o_ok$next[0:0]$3194
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire width 32 $2\data_r1__full_cr$next[31:0]$3201
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire $2\data_r1__full_cr_ok$next[0:0]$3202
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire width 4 $2\data_r2__cr_a$next[3:0]$3209
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire $2\data_r2__cr_a_ok$next[0:0]$3210
+ attribute \src "libresoc.v:50605.3-50626.6"
+ wire $3\data_r0__o_ok$next[0:0]$3195
+ attribute \src "libresoc.v:50627.3-50648.6"
+ wire $3\data_r1__full_cr_ok$next[0:0]$3203
+ attribute \src "libresoc.v:50649.3-50670.6"
+ wire $3\data_r2__cr_a_ok$next[0:0]$3211
+ attribute \src "libresoc.v:50306.18-50306.112"
+ wire width 6 $and$libresoc.v:50306$3064_Y
+ attribute \src "libresoc.v:50307.19-50307.125"
+ wire $and$libresoc.v:50307$3065_Y
+ attribute \src "libresoc.v:50308.19-50308.125"
+ wire $and$libresoc.v:50308$3066_Y
+ attribute \src "libresoc.v:50309.19-50309.125"
+ wire $and$libresoc.v:50309$3067_Y
+ attribute \src "libresoc.v:50310.19-50310.141"
+ wire width 3 $and$libresoc.v:50310$3068_Y
+ attribute \src "libresoc.v:50311.19-50311.121"
+ wire width 3 $and$libresoc.v:50311$3069_Y
+ attribute \src "libresoc.v:50312.19-50312.127"
+ wire $and$libresoc.v:50312$3070_Y
+ attribute \src "libresoc.v:50313.19-50313.127"
+ wire $and$libresoc.v:50313$3071_Y
+ attribute \src "libresoc.v:50314.19-50314.127"
+ wire $and$libresoc.v:50314$3072_Y
+ attribute \src "libresoc.v:50315.18-50315.110"
+ wire $and$libresoc.v:50315$3073_Y
+ attribute \src "libresoc.v:50317.18-50317.98"
+ wire $and$libresoc.v:50317$3075_Y
+ attribute \src "libresoc.v:50319.18-50319.100"
+ wire $and$libresoc.v:50319$3077_Y
+ attribute \src "libresoc.v:50320.18-50320.149"
+ wire width 3 $and$libresoc.v:50320$3078_Y
+ attribute \src "libresoc.v:50322.18-50322.119"
+ wire width 3 $and$libresoc.v:50322$3080_Y
+ attribute \src "libresoc.v:50325.18-50325.116"
+ wire $and$libresoc.v:50325$3083_Y
+ attribute \src "libresoc.v:50329.17-50329.123"
+ wire $and$libresoc.v:50329$3087_Y
+ attribute \src "libresoc.v:50331.18-50331.113"
+ wire $and$libresoc.v:50331$3089_Y
+ attribute \src "libresoc.v:50332.18-50332.125"
+ wire width 3 $and$libresoc.v:50332$3090_Y
+ attribute \src "libresoc.v:50334.18-50334.112"
+ wire $and$libresoc.v:50334$3092_Y
+ attribute \src "libresoc.v:50336.18-50336.125"
+ wire $and$libresoc.v:50336$3094_Y
+ attribute \src "libresoc.v:50337.18-50337.125"
+ wire $and$libresoc.v:50337$3095_Y
+ attribute \src "libresoc.v:50338.18-50338.117"
+ wire $and$libresoc.v:50338$3096_Y
+ attribute \src "libresoc.v:50343.18-50343.129"
+ wire $and$libresoc.v:50343$3101_Y
+ attribute \src "libresoc.v:50344.18-50344.124"
+ wire width 3 $and$libresoc.v:50344$3102_Y
+ attribute \src "libresoc.v:50347.18-50347.116"
+ wire $and$libresoc.v:50347$3105_Y
+ attribute \src "libresoc.v:50348.18-50348.122"
+ wire $and$libresoc.v:50348$3106_Y
+ attribute \src "libresoc.v:50349.18-50349.119"
+ wire $and$libresoc.v:50349$3107_Y
+ attribute \src "libresoc.v:50357.18-50357.133"
+ wire $and$libresoc.v:50357$3115_Y
+ attribute \src "libresoc.v:50358.18-50358.131"
+ wire $and$libresoc.v:50358$3116_Y
+ attribute \src "libresoc.v:50359.18-50359.182"
+ wire width 6 $and$libresoc.v:50359$3117_Y
+ attribute \src "libresoc.v:50360.18-50360.113"
+ wire width 6 $and$libresoc.v:50360$3118_Y
+ attribute \src "libresoc.v:50333.18-50333.113"
+ wire $eq$libresoc.v:50333$3091_Y
+ attribute \src "libresoc.v:50335.18-50335.119"
+ wire $eq$libresoc.v:50335$3093_Y
+ attribute \src "libresoc.v:50316.18-50316.97"
+ wire $not$libresoc.v:50316$3074_Y
+ attribute \src "libresoc.v:50318.18-50318.99"
+ wire $not$libresoc.v:50318$3076_Y
+ attribute \src "libresoc.v:50321.18-50321.113"
+ wire width 3 $not$libresoc.v:50321$3079_Y
+ attribute \src "libresoc.v:50324.18-50324.106"
+ wire $not$libresoc.v:50324$3082_Y
+ attribute \src "libresoc.v:50330.18-50330.119"
+ wire $not$libresoc.v:50330$3088_Y
+ attribute \src "libresoc.v:50345.17-50345.113"
+ wire width 6 $not$libresoc.v:50345$3103_Y
+ attribute \src "libresoc.v:50361.18-50361.114"
+ wire width 6 $not$libresoc.v:50361$3119_Y
+ attribute \src "libresoc.v:50328.18-50328.112"
+ wire $or$libresoc.v:50328$3086_Y
+ attribute \src "libresoc.v:50339.18-50339.122"
+ wire $or$libresoc.v:50339$3097_Y
+ attribute \src "libresoc.v:50340.18-50340.124"
+ wire $or$libresoc.v:50340$3098_Y
+ attribute \src "libresoc.v:50341.18-50341.155"
+ wire width 3 $or$libresoc.v:50341$3099_Y
+ attribute \src "libresoc.v:50342.18-50342.194"
+ wire width 6 $or$libresoc.v:50342$3100_Y
+ attribute \src "libresoc.v:50346.18-50346.120"
+ wire width 3 $or$libresoc.v:50346$3104_Y
+ attribute \src "libresoc.v:50356.17-50356.117"
+ wire width 6 $or$libresoc.v:50356$3114_Y
+ attribute \src "libresoc.v:50305.17-50305.104"
+ wire $reduce_and$libresoc.v:50305$3063_Y
+ attribute \src "libresoc.v:50323.18-50323.106"
+ wire $reduce_or$libresoc.v:50323$3081_Y
+ attribute \src "libresoc.v:50326.18-50326.113"
+ wire $reduce_or$libresoc.v:50326$3084_Y
+ attribute \src "libresoc.v:50327.18-50327.112"
+ wire $reduce_or$libresoc.v:50327$3085_Y
+ attribute \src "libresoc.v:50350.18-50350.118"
+ wire width 64 $ternary$libresoc.v:50350$3108_Y
+ attribute \src "libresoc.v:50351.18-50351.118"
+ wire width 64 $ternary$libresoc.v:50351$3109_Y
+ attribute \src "libresoc.v:50352.18-50352.118"
+ wire width 32 $ternary$libresoc.v:50352$3110_Y
+ attribute \src "libresoc.v:50353.18-50353.118"
+ wire width 4 $ternary$libresoc.v:50353$3111_Y
+ attribute \src "libresoc.v:50354.18-50354.118"
+ wire width 4 $ternary$libresoc.v:50354$3112_Y
+ attribute \src "libresoc.v:50355.18-50355.118"
+ wire width 4 $ternary$libresoc.v:50355$3113_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 24 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 22 \cr_a_ok
wire width 4 output 23 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 20 \full_cr_ok
- attribute \src "libresoc.v:49938.7-49938.15"
+ attribute \src "libresoc.v:49763.7-49763.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 16 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 10 \src1_i
+ wire width 64 input 11 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 11 \src2_i
+ wire width 64 input 10 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 32 input 12 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:50481$3080
+ cell $and $and$libresoc.v:50306$3064
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:50481$3080_Y
+ connect \Y $and$libresoc.v:50306$3064_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:50482$3081
+ cell $and $and$libresoc.v:50307$3065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:50482$3081_Y
+ connect \Y $and$libresoc.v:50307$3065_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:50483$3082
+ cell $and $and$libresoc.v:50308$3066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:50483$3082_Y
+ connect \Y $and$libresoc.v:50308$3066_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:50484$3083
+ cell $and $and$libresoc.v:50309$3067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:50484$3083_Y
+ connect \Y $and$libresoc.v:50309$3067_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:50485$3084
+ cell $and $and$libresoc.v:50310$3068
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B { \$101 \$103 \$105 }
- connect \Y $and$libresoc.v:50485$3084_Y
+ connect \Y $and$libresoc.v:50310$3068_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:50486$3085
+ cell $and $and$libresoc.v:50311$3069
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$107
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:50486$3085_Y
+ connect \Y $and$libresoc.v:50311$3069_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:50487$3086
+ cell $and $and$libresoc.v:50312$3070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50487$3086_Y
+ connect \Y $and$libresoc.v:50312$3070_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:50488$3087
+ cell $and $and$libresoc.v:50313$3071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50488$3087_Y
+ connect \Y $and$libresoc.v:50313$3071_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:50489$3088
+ cell $and $and$libresoc.v:50314$3072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50489$3088_Y
+ connect \Y $and$libresoc.v:50314$3072_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:50490$3089
+ cell $and $and$libresoc.v:50315$3073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:50490$3089_Y
+ connect \Y $and$libresoc.v:50315$3073_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:50492$3091
+ cell $and $and$libresoc.v:50317$3075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$13
- connect \Y $and$libresoc.v:50492$3091_Y
+ connect \Y $and$libresoc.v:50317$3075_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:50494$3093
+ cell $and $and$libresoc.v:50319$3077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$17
- connect \Y $and$libresoc.v:50494$3093_Y
+ connect \Y $and$libresoc.v:50319$3077_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:50495$3094
+ cell $and $and$libresoc.v:50320$3078
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:50495$3094_Y
+ connect \Y $and$libresoc.v:50320$3078_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:50497$3096
+ cell $and $and$libresoc.v:50322$3080
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__rel_o
connect \B \$25
- connect \Y $and$libresoc.v:50497$3096_Y
+ connect \Y $and$libresoc.v:50322$3080_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:50500$3099
+ cell $and $and$libresoc.v:50325$3083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$23
- connect \Y $and$libresoc.v:50500$3099_Y
+ connect \Y $and$libresoc.v:50325$3083_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:50504$3103
+ cell $and $and$libresoc.v:50329$3087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:50504$3103_Y
+ connect \Y $and$libresoc.v:50329$3087_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:50506$3105
+ cell $and $and$libresoc.v:50331$3089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$39
- connect \Y $and$libresoc.v:50506$3105_Y
+ connect \Y $and$libresoc.v:50331$3089_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:50507$3106
+ cell $and $and$libresoc.v:50332$3090
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:50507$3106_Y
+ connect \Y $and$libresoc.v:50332$3090_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:50509$3108
+ cell $and $and$libresoc.v:50334$3092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B \$45
- connect \Y $and$libresoc.v:50509$3108_Y
+ connect \Y $and$libresoc.v:50334$3092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:50511$3110
+ cell $and $and$libresoc.v:50336$3094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_cr0_n_ready_i
- connect \Y $and$libresoc.v:50511$3110_Y
+ connect \Y $and$libresoc.v:50336$3094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:50512$3111
+ cell $and $and$libresoc.v:50337$3095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \alu_cr0_n_valid_o
- connect \Y $and$libresoc.v:50512$3111_Y
+ connect \Y $and$libresoc.v:50337$3095_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:50513$3112
+ cell $and $and$libresoc.v:50338$3096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50513$3112_Y
+ connect \Y $and$libresoc.v:50338$3096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:50518$3117
+ cell $and $and$libresoc.v:50343$3101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50518$3117_Y
+ connect \Y $and$libresoc.v:50343$3101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:50519$3118
+ cell $and $and$libresoc.v:50344$3102
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:50519$3118_Y
+ connect \Y $and$libresoc.v:50344$3102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:50522$3121
+ cell $and $and$libresoc.v:50347$3105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50522$3121_Y
+ connect \Y $and$libresoc.v:50347$3105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:50523$3122
+ cell $and $and$libresoc.v:50348$3106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \full_cr_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50523$3122_Y
+ connect \Y $and$libresoc.v:50348$3106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:50524$3123
+ cell $and $and$libresoc.v:50349$3107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:50524$3123_Y
+ connect \Y $and$libresoc.v:50349$3107_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:50532$3131
+ cell $and $and$libresoc.v:50357$3115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:50532$3131_Y
+ connect \Y $and$libresoc.v:50357$3115_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:50533$3132
+ cell $and $and$libresoc.v:50358$3116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:50533$3132_Y
+ connect \Y $and$libresoc.v:50358$3116_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:50534$3133
+ cell $and $and$libresoc.v:50359$3117
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:50534$3133_Y
+ connect \Y $and$libresoc.v:50359$3117_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:50535$3134
+ cell $and $and$libresoc.v:50360$3118
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$93
connect \B 6'111111
- connect \Y $and$libresoc.v:50535$3134_Y
+ connect \Y $and$libresoc.v:50360$3118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:50508$3107
+ cell $eq $eq$libresoc.v:50333$3091
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B 1'0
- connect \Y $eq$libresoc.v:50508$3107_Y
+ connect \Y $eq$libresoc.v:50333$3091_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:50510$3109
+ cell $eq $eq$libresoc.v:50335$3093
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:50510$3109_Y
+ connect \Y $eq$libresoc.v:50335$3093_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:50491$3090
+ cell $not $not$libresoc.v:50316$3074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:50491$3090_Y
+ connect \Y $not$libresoc.v:50316$3074_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:50493$3092
+ cell $not $not$libresoc.v:50318$3076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:50493$3092_Y
+ connect \Y $not$libresoc.v:50318$3076_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:50496$3095
+ cell $not $not$libresoc.v:50321$3079
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:50496$3095_Y
+ connect \Y $not$libresoc.v:50321$3079_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:50499$3098
+ cell $not $not$libresoc.v:50324$3082
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:50499$3098_Y
+ connect \Y $not$libresoc.v:50324$3082_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:50505$3104
+ cell $not $not$libresoc.v:50330$3088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_ready_i
- connect \Y $not$libresoc.v:50505$3104_Y
+ connect \Y $not$libresoc.v:50330$3088_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:50520$3119
+ cell $not $not$libresoc.v:50345$3103
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:50520$3119_Y
+ connect \Y $not$libresoc.v:50345$3103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:50536$3135
+ cell $not $not$libresoc.v:50361$3119
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:50536$3135_Y
+ connect \Y $not$libresoc.v:50361$3119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:50503$3102
+ cell $or $or$libresoc.v:50328$3086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:50503$3102_Y
+ connect \Y $or$libresoc.v:50328$3086_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:50514$3113
+ cell $or $or$libresoc.v:50339$3097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:50514$3113_Y
+ connect \Y $or$libresoc.v:50339$3097_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:50515$3114
+ cell $or $or$libresoc.v:50340$3098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:50515$3114_Y
+ connect \Y $or$libresoc.v:50340$3098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:50516$3115
+ cell $or $or$libresoc.v:50341$3099
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:50516$3115_Y
+ connect \Y $or$libresoc.v:50341$3099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:50517$3116
+ cell $or $or$libresoc.v:50342$3100
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:50517$3116_Y
+ connect \Y $or$libresoc.v:50342$3100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:50521$3120
+ cell $or $or$libresoc.v:50346$3104
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:50521$3120_Y
+ connect \Y $or$libresoc.v:50346$3104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:50531$3130
+ cell $or $or$libresoc.v:50356$3114
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$6
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:50531$3130_Y
+ connect \Y $or$libresoc.v:50356$3114_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:50480$3079
+ cell $reduce_and $reduce_and$libresoc.v:50305$3063
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $reduce_and$libresoc.v:50480$3079_Y
+ connect \Y $reduce_and$libresoc.v:50305$3063_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:50498$3097
+ cell $reduce_or $reduce_or$libresoc.v:50323$3081
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $reduce_or$libresoc.v:50498$3097_Y
+ connect \Y $reduce_or$libresoc.v:50323$3081_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:50501$3100
+ cell $reduce_or $reduce_or$libresoc.v:50326$3084
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:50501$3100_Y
+ connect \Y $reduce_or$libresoc.v:50326$3084_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:50502$3101
+ cell $reduce_or $reduce_or$libresoc.v:50327$3085
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:50502$3101_Y
+ connect \Y $reduce_or$libresoc.v:50327$3085_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50525$3124
+ cell $mux $ternary$libresoc.v:50350$3108
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:50525$3124_Y
+ connect \Y $ternary$libresoc.v:50350$3108_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50526$3125
+ cell $mux $ternary$libresoc.v:50351$3109
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:50526$3125_Y
+ connect \Y $ternary$libresoc.v:50351$3109_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50527$3126
+ cell $mux $ternary$libresoc.v:50352$3110
parameter \WIDTH 32
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:50527$3126_Y
+ connect \Y $ternary$libresoc.v:50352$3110_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50528$3127
+ cell $mux $ternary$libresoc.v:50353$3111
parameter \WIDTH 4
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:50528$3127_Y
+ connect \Y $ternary$libresoc.v:50353$3111_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50529$3128
+ cell $mux $ternary$libresoc.v:50354$3112
parameter \WIDTH 4
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:50529$3128_Y
+ connect \Y $ternary$libresoc.v:50354$3112_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:50530$3129
+ cell $mux $ternary$libresoc.v:50355$3113
parameter \WIDTH 4
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $ternary$libresoc.v:50530$3129_Y
+ connect \Y $ternary$libresoc.v:50355$3113_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50597.11-50619.4"
+ attribute \src "libresoc.v:50422.11-50444.4"
cell \alu_cr0 \alu_cr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \rb \alu_cr0_rb
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50620.14-50626.4"
+ attribute \src "libresoc.v:50445.14-50451.4"
cell \alu_l$16 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50627.15-50633.4"
+ attribute \src "libresoc.v:50452.15-50458.4"
cell \alui_l$15 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50634.14-50640.4"
+ attribute \src "libresoc.v:50459.14-50465.4"
cell \opc_l$11 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50641.14-50647.4"
+ attribute \src "libresoc.v:50466.14-50472.4"
cell \req_l$12 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50648.14-50654.4"
+ attribute \src "libresoc.v:50473.14-50479.4"
cell \rok_l$14 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50655.14-50660.4"
+ attribute \src "libresoc.v:50480.14-50485.4"
cell \rst_l$13 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:50661.14-50667.4"
+ attribute \src "libresoc.v:50486.14-50492.4"
cell \src_l$10 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:49938.7-49938.20"
- process $proc$libresoc.v:49938$3258
+ attribute \src "libresoc.v:49763.7-49763.20"
+ process $proc$libresoc.v:49763$3242
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:50056.7-50056.24"
- process $proc$libresoc.v:50056$3259
+ attribute \src "libresoc.v:49881.7-49881.24"
+ process $proc$libresoc.v:49881$3243
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:50087.14-50087.47"
- process $proc$libresoc.v:50087$3260
+ attribute \src "libresoc.v:49912.14-49912.47"
+ process $proc$libresoc.v:49912$3244
assign { } { }
assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:50091.14-50091.41"
- process $proc$libresoc.v:50091$3261
+ attribute \src "libresoc.v:49916.14-49916.41"
+ process $proc$libresoc.v:49916$3245
assign { } { }
assign $1\alu_cr0_cr_op__insn[31:0] 0
sync always
sync init
update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0]
end
- attribute \src "libresoc.v:50170.13-50170.45"
- process $proc$libresoc.v:50170$3262
+ attribute \src "libresoc.v:49995.13-49995.45"
+ process $proc$libresoc.v:49995$3246
assign { } { }
assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:50194.7-50194.26"
- process $proc$libresoc.v:50194$3263
+ attribute \src "libresoc.v:50019.7-50019.26"
+ process $proc$libresoc.v:50019$3247
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:50202.7-50202.25"
- process $proc$libresoc.v:50202$3264
+ attribute \src "libresoc.v:50027.7-50027.25"
+ process $proc$libresoc.v:50027$3248
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:50214.7-50214.27"
- process $proc$libresoc.v:50214$3265
+ attribute \src "libresoc.v:50039.7-50039.27"
+ process $proc$libresoc.v:50039$3249
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:50248.14-50248.47"
- process $proc$libresoc.v:50248$3266
+ attribute \src "libresoc.v:50073.14-50073.47"
+ process $proc$libresoc.v:50073$3250
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:50252.7-50252.27"
- process $proc$libresoc.v:50252$3267
+ attribute \src "libresoc.v:50077.7-50077.27"
+ process $proc$libresoc.v:50077$3251
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:50256.14-50256.38"
- process $proc$libresoc.v:50256$3268
+ attribute \src "libresoc.v:50081.14-50081.38"
+ process $proc$libresoc.v:50081$3252
assign { } { }
assign $1\data_r1__full_cr[31:0] 0
sync always
sync init
update \data_r1__full_cr $1\data_r1__full_cr[31:0]
end
- attribute \src "libresoc.v:50260.7-50260.33"
- process $proc$libresoc.v:50260$3269
+ attribute \src "libresoc.v:50085.7-50085.33"
+ process $proc$libresoc.v:50085$3253
assign { } { }
assign $1\data_r1__full_cr_ok[0:0] 1'0
sync always
sync init
update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0]
end
- attribute \src "libresoc.v:50264.13-50264.33"
- process $proc$libresoc.v:50264$3270
+ attribute \src "libresoc.v:50089.13-50089.33"
+ process $proc$libresoc.v:50089$3254
assign { } { }
assign $1\data_r2__cr_a[3:0] 4'0000
sync always
sync init
update \data_r2__cr_a $1\data_r2__cr_a[3:0]
end
- attribute \src "libresoc.v:50268.7-50268.30"
- process $proc$libresoc.v:50268$3271
+ attribute \src "libresoc.v:50093.7-50093.30"
+ process $proc$libresoc.v:50093$3255
assign { } { }
assign $1\data_r2__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:50287.7-50287.25"
- process $proc$libresoc.v:50287$3272
+ attribute \src "libresoc.v:50112.7-50112.25"
+ process $proc$libresoc.v:50112$3256
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:50291.7-50291.25"
- process $proc$libresoc.v:50291$3273
+ attribute \src "libresoc.v:50116.7-50116.25"
+ process $proc$libresoc.v:50116$3257
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:50391.13-50391.30"
- process $proc$libresoc.v:50391$3274
+ attribute \src "libresoc.v:50216.13-50216.30"
+ process $proc$libresoc.v:50216$3258
assign { } { }
assign $1\prev_wr_go[2:0] 3'000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:50399.13-50399.31"
- process $proc$libresoc.v:50399$3275
+ attribute \src "libresoc.v:50224.13-50224.31"
+ process $proc$libresoc.v:50224$3259
assign { } { }
assign $1\req_l_r_req[2:0] 3'111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:50403.13-50403.31"
- process $proc$libresoc.v:50403$3276
+ attribute \src "libresoc.v:50228.13-50228.31"
+ process $proc$libresoc.v:50228$3260
assign { } { }
assign $1\req_l_s_req[2:0] 3'000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:50415.7-50415.26"
- process $proc$libresoc.v:50415$3277
+ attribute \src "libresoc.v:50240.7-50240.26"
+ process $proc$libresoc.v:50240$3261
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:50419.7-50419.26"
- process $proc$libresoc.v:50419$3278
+ attribute \src "libresoc.v:50244.7-50244.26"
+ process $proc$libresoc.v:50244$3262
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:50423.7-50423.25"
- process $proc$libresoc.v:50423$3279
+ attribute \src "libresoc.v:50248.7-50248.25"
+ process $proc$libresoc.v:50248$3263
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:50427.7-50427.25"
- process $proc$libresoc.v:50427$3280
+ attribute \src "libresoc.v:50252.7-50252.25"
+ process $proc$libresoc.v:50252$3264
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:50447.13-50447.32"
- process $proc$libresoc.v:50447$3281
+ attribute \src "libresoc.v:50272.13-50272.32"
+ process $proc$libresoc.v:50272$3265
assign { } { }
assign $1\src_l_r_src[5:0] 6'111111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:50451.13-50451.32"
- process $proc$libresoc.v:50451$3282
+ attribute \src "libresoc.v:50276.13-50276.32"
+ process $proc$libresoc.v:50276$3266
assign { } { }
assign $1\src_l_s_src[5:0] 6'000000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:50455.14-50455.43"
- process $proc$libresoc.v:50455$3283
+ attribute \src "libresoc.v:50280.14-50280.43"
+ process $proc$libresoc.v:50280$3267
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:50459.14-50459.43"
- process $proc$libresoc.v:50459$3284
+ attribute \src "libresoc.v:50284.14-50284.43"
+ process $proc$libresoc.v:50284$3268
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:50463.14-50463.28"
- process $proc$libresoc.v:50463$3285
+ attribute \src "libresoc.v:50288.14-50288.28"
+ process $proc$libresoc.v:50288$3269
assign { } { }
assign $1\src_r2[31:0] 0
sync always
sync init
update \src_r2 $1\src_r2[31:0]
end
- attribute \src "libresoc.v:50467.13-50467.26"
- process $proc$libresoc.v:50467$3286
+ attribute \src "libresoc.v:50292.13-50292.26"
+ process $proc$libresoc.v:50292$3270
assign { } { }
assign $1\src_r3[3:0] 4'0000
sync always
sync init
update \src_r3 $1\src_r3[3:0]
end
- attribute \src "libresoc.v:50471.13-50471.26"
- process $proc$libresoc.v:50471$3287
+ attribute \src "libresoc.v:50296.13-50296.26"
+ process $proc$libresoc.v:50296$3271
assign { } { }
assign $1\src_r4[3:0] 4'0000
sync always
sync init
update \src_r4 $1\src_r4[3:0]
end
- attribute \src "libresoc.v:50475.13-50475.26"
- process $proc$libresoc.v:50475$3288
+ attribute \src "libresoc.v:50300.13-50300.26"
+ process $proc$libresoc.v:50300$3272
assign { } { }
assign $1\src_r5[3:0] 4'0000
sync always
sync init
update \src_r5 $1\src_r5[3:0]
end
- attribute \src "libresoc.v:50537.3-50538.39"
- process $proc$libresoc.v:50537$3136
+ attribute \src "libresoc.v:50362.3-50363.39"
+ process $proc$libresoc.v:50362$3120
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:50539.3-50540.43"
- process $proc$libresoc.v:50539$3137
+ attribute \src "libresoc.v:50364.3-50365.43"
+ process $proc$libresoc.v:50364$3121
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:50541.3-50542.29"
- process $proc$libresoc.v:50541$3138
+ attribute \src "libresoc.v:50366.3-50367.29"
+ process $proc$libresoc.v:50366$3122
assign { } { }
assign $0\src_r5[3:0] \src_r5$next
sync posedge \coresync_clk
update \src_r5 $0\src_r5[3:0]
end
- attribute \src "libresoc.v:50543.3-50544.29"
- process $proc$libresoc.v:50543$3139
+ attribute \src "libresoc.v:50368.3-50369.29"
+ process $proc$libresoc.v:50368$3123
assign { } { }
assign $0\src_r4[3:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[3:0]
end
- attribute \src "libresoc.v:50545.3-50546.29"
- process $proc$libresoc.v:50545$3140
+ attribute \src "libresoc.v:50370.3-50371.29"
+ process $proc$libresoc.v:50370$3124
assign { } { }
assign $0\src_r3[3:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[3:0]
end
- attribute \src "libresoc.v:50547.3-50548.29"
- process $proc$libresoc.v:50547$3141
+ attribute \src "libresoc.v:50372.3-50373.29"
+ process $proc$libresoc.v:50372$3125
assign { } { }
assign $0\src_r2[31:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[31:0]
end
- attribute \src "libresoc.v:50549.3-50550.29"
- process $proc$libresoc.v:50549$3142
+ attribute \src "libresoc.v:50374.3-50375.29"
+ process $proc$libresoc.v:50374$3126
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:50551.3-50552.29"
- process $proc$libresoc.v:50551$3143
+ attribute \src "libresoc.v:50376.3-50377.29"
+ process $proc$libresoc.v:50376$3127
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:50553.3-50554.43"
- process $proc$libresoc.v:50553$3144
+ attribute \src "libresoc.v:50378.3-50379.43"
+ process $proc$libresoc.v:50378$3128
assign { } { }
assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next
sync posedge \coresync_clk
update \data_r2__cr_a $0\data_r2__cr_a[3:0]
end
- attribute \src "libresoc.v:50555.3-50556.49"
- process $proc$libresoc.v:50555$3145
+ attribute \src "libresoc.v:50380.3-50381.49"
+ process $proc$libresoc.v:50380$3129
assign { } { }
assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next
sync posedge \coresync_clk
update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:50557.3-50558.49"
- process $proc$libresoc.v:50557$3146
+ attribute \src "libresoc.v:50382.3-50383.49"
+ process $proc$libresoc.v:50382$3130
assign { } { }
assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next
sync posedge \coresync_clk
update \data_r1__full_cr $0\data_r1__full_cr[31:0]
end
- attribute \src "libresoc.v:50559.3-50560.55"
- process $proc$libresoc.v:50559$3147
+ attribute \src "libresoc.v:50384.3-50385.55"
+ process $proc$libresoc.v:50384$3131
assign { } { }
assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next
sync posedge \coresync_clk
update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0]
end
- attribute \src "libresoc.v:50561.3-50562.37"
- process $proc$libresoc.v:50561$3148
+ attribute \src "libresoc.v:50386.3-50387.37"
+ process $proc$libresoc.v:50386$3132
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:50563.3-50564.43"
- process $proc$libresoc.v:50563$3149
+ attribute \src "libresoc.v:50388.3-50389.43"
+ process $proc$libresoc.v:50388$3133
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:50565.3-50566.65"
- process $proc$libresoc.v:50565$3150
+ attribute \src "libresoc.v:50390.3-50391.65"
+ process $proc$libresoc.v:50390$3134
assign { } { }
assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next
sync posedge \coresync_clk
update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:50567.3-50568.61"
- process $proc$libresoc.v:50567$3151
+ attribute \src "libresoc.v:50392.3-50393.61"
+ process $proc$libresoc.v:50392$3135
assign { } { }
assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:50569.3-50570.55"
- process $proc$libresoc.v:50569$3152
+ attribute \src "libresoc.v:50394.3-50395.55"
+ process $proc$libresoc.v:50394$3136
assign { } { }
assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next
sync posedge \coresync_clk
update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0]
end
- attribute \src "libresoc.v:50571.3-50572.39"
- process $proc$libresoc.v:50571$3153
+ attribute \src "libresoc.v:50396.3-50397.39"
+ process $proc$libresoc.v:50396$3137
assign { } { }
assign $0\req_l_r_req[2:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:50573.3-50574.39"
- process $proc$libresoc.v:50573$3154
+ attribute \src "libresoc.v:50398.3-50399.39"
+ process $proc$libresoc.v:50398$3138
assign { } { }
assign $0\req_l_s_req[2:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:50575.3-50576.39"
- process $proc$libresoc.v:50575$3155
+ attribute \src "libresoc.v:50400.3-50401.39"
+ process $proc$libresoc.v:50400$3139
assign { } { }
assign $0\src_l_r_src[5:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:50577.3-50578.39"
- process $proc$libresoc.v:50577$3156
+ attribute \src "libresoc.v:50402.3-50403.39"
+ process $proc$libresoc.v:50402$3140
assign { } { }
assign $0\src_l_s_src[5:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:50579.3-50580.39"
- process $proc$libresoc.v:50579$3157
+ attribute \src "libresoc.v:50404.3-50405.39"
+ process $proc$libresoc.v:50404$3141
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:50581.3-50582.39"
- process $proc$libresoc.v:50581$3158
+ attribute \src "libresoc.v:50406.3-50407.39"
+ process $proc$libresoc.v:50406$3142
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:50583.3-50584.39"
- process $proc$libresoc.v:50583$3159
+ attribute \src "libresoc.v:50408.3-50409.39"
+ process $proc$libresoc.v:50408$3143
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:50585.3-50586.39"
- process $proc$libresoc.v:50585$3160
+ attribute \src "libresoc.v:50410.3-50411.39"
+ process $proc$libresoc.v:50410$3144
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:50587.3-50588.41"
- process $proc$libresoc.v:50587$3161
+ attribute \src "libresoc.v:50412.3-50413.41"
+ process $proc$libresoc.v:50412$3145
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:50589.3-50590.41"
- process $proc$libresoc.v:50589$3162
+ attribute \src "libresoc.v:50414.3-50415.41"
+ process $proc$libresoc.v:50414$3146
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:50591.3-50592.37"
- process $proc$libresoc.v:50591$3163
+ attribute \src "libresoc.v:50416.3-50417.37"
+ process $proc$libresoc.v:50416$3147
assign { } { }
assign $0\prev_wr_go[2:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:50593.3-50594.39"
- process $proc$libresoc.v:50593$3164
+ attribute \src "libresoc.v:50418.3-50419.39"
+ process $proc$libresoc.v:50418$3148
assign { } { }
assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:50595.3-50596.25"
- process $proc$libresoc.v:50595$3165
+ attribute \src "libresoc.v:50420.3-50421.25"
+ process $proc$libresoc.v:50420$3149
assign { } { }
assign $0\all_rd_dly[0:0] \$11
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:50668.3-50677.6"
- process $proc$libresoc.v:50668$3166
+ attribute \src "libresoc.v:50493.3-50502.6"
+ process $proc$libresoc.v:50493$3150
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:50669.5-50669.29"
+ attribute \src "libresoc.v:50494.5-50494.29"
switch \initial
- attribute \src "libresoc.v:50669.9-50669.17"
+ attribute \src "libresoc.v:50494.9-50494.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:50678.3-50686.6"
- process $proc$libresoc.v:50678$3167
+ attribute \src "libresoc.v:50503.3-50511.6"
+ process $proc$libresoc.v:50503$3151
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169
- attribute \src "libresoc.v:50679.5-50679.29"
+ assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153
+ attribute \src "libresoc.v:50504.5-50504.29"
switch \initial
- attribute \src "libresoc.v:50679.9-50679.17"
+ attribute \src "libresoc.v:50504.9-50504.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$3169 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$3153 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$3169 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152
end
- attribute \src "libresoc.v:50687.3-50695.6"
- process $proc$libresoc.v:50687$3170
+ attribute \src "libresoc.v:50512.3-50520.6"
+ process $proc$libresoc.v:50512$3154
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172
- attribute \src "libresoc.v:50688.5-50688.29"
+ assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156
+ attribute \src "libresoc.v:50513.5-50513.29"
switch \initial
- attribute \src "libresoc.v:50688.9-50688.17"
+ attribute \src "libresoc.v:50513.9-50513.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$3172 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$3156 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$3172 \$65
+ assign $1\rok_l_r_rdok$next[0:0]$3156 \$65
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155
end
- attribute \src "libresoc.v:50696.3-50704.6"
- process $proc$libresoc.v:50696$3173
+ attribute \src "libresoc.v:50521.3-50529.6"
+ process $proc$libresoc.v:50521$3157
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175
- attribute \src "libresoc.v:50697.5-50697.29"
+ assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159
+ attribute \src "libresoc.v:50522.5-50522.29"
switch \initial
- attribute \src "libresoc.v:50697.9-50697.17"
+ attribute \src "libresoc.v:50522.9-50522.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$3175 1'0
+ assign $1\rst_l_s_rst$next[0:0]$3159 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$3175 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158
end
- attribute \src "libresoc.v:50705.3-50713.6"
- process $proc$libresoc.v:50705$3176
+ attribute \src "libresoc.v:50530.3-50538.6"
+ process $proc$libresoc.v:50530$3160
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178
- attribute \src "libresoc.v:50706.5-50706.29"
+ assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162
+ attribute \src "libresoc.v:50531.5-50531.29"
switch \initial
- attribute \src "libresoc.v:50706.9-50706.17"
+ attribute \src "libresoc.v:50531.9-50531.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$3178 1'1
+ assign $1\rst_l_r_rst$next[0:0]$3162 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$3178 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161
end
- attribute \src "libresoc.v:50714.3-50722.6"
- process $proc$libresoc.v:50714$3179
+ attribute \src "libresoc.v:50539.3-50547.6"
+ process $proc$libresoc.v:50539$3163
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181
- attribute \src "libresoc.v:50715.5-50715.29"
+ assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165
+ attribute \src "libresoc.v:50540.5-50540.29"
switch \initial
- attribute \src "libresoc.v:50715.9-50715.17"
+ attribute \src "libresoc.v:50540.9-50540.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$3181 1'0
+ assign $1\opc_l_s_opc$next[0:0]$3165 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$3181 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164
end
- attribute \src "libresoc.v:50723.3-50731.6"
- process $proc$libresoc.v:50723$3182
+ attribute \src "libresoc.v:50548.3-50556.6"
+ process $proc$libresoc.v:50548$3166
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184
- attribute \src "libresoc.v:50724.5-50724.29"
+ assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168
+ attribute \src "libresoc.v:50549.5-50549.29"
switch \initial
- attribute \src "libresoc.v:50724.9-50724.17"
+ attribute \src "libresoc.v:50549.9-50549.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$3184 1'1
+ assign $1\opc_l_r_opc$next[0:0]$3168 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$3184 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$3168 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167
end
- attribute \src "libresoc.v:50732.3-50740.6"
- process $proc$libresoc.v:50732$3185
+ attribute \src "libresoc.v:50557.3-50565.6"
+ process $proc$libresoc.v:50557$3169
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187
- attribute \src "libresoc.v:50733.5-50733.29"
+ assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171
+ attribute \src "libresoc.v:50558.5-50558.29"
switch \initial
- attribute \src "libresoc.v:50733.9-50733.17"
+ attribute \src "libresoc.v:50558.9-50558.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[5:0]$3187 6'000000
+ assign $1\src_l_s_src$next[5:0]$3171 6'000000
case
- assign $1\src_l_s_src$next[5:0]$3187 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186
+ update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170
end
- attribute \src "libresoc.v:50741.3-50749.6"
- process $proc$libresoc.v:50741$3188
+ attribute \src "libresoc.v:50566.3-50574.6"
+ process $proc$libresoc.v:50566$3172
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190
- attribute \src "libresoc.v:50742.5-50742.29"
+ assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174
+ attribute \src "libresoc.v:50567.5-50567.29"
switch \initial
- attribute \src "libresoc.v:50742.9-50742.17"
+ attribute \src "libresoc.v:50567.9-50567.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[5:0]$3190 6'111111
+ assign $1\src_l_r_src$next[5:0]$3174 6'111111
case
- assign $1\src_l_r_src$next[5:0]$3190 \reset_r
+ assign $1\src_l_r_src$next[5:0]$3174 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189
+ update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173
end
- attribute \src "libresoc.v:50750.3-50758.6"
- process $proc$libresoc.v:50750$3191
+ attribute \src "libresoc.v:50575.3-50583.6"
+ process $proc$libresoc.v:50575$3175
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193
- attribute \src "libresoc.v:50751.5-50751.29"
+ assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177
+ attribute \src "libresoc.v:50576.5-50576.29"
switch \initial
- attribute \src "libresoc.v:50751.9-50751.17"
+ attribute \src "libresoc.v:50576.9-50576.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[2:0]$3193 3'000
+ assign $1\req_l_s_req$next[2:0]$3177 3'000
case
- assign $1\req_l_s_req$next[2:0]$3193 \$67
+ assign $1\req_l_s_req$next[2:0]$3177 \$67
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192
+ update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176
end
- attribute \src "libresoc.v:50759.3-50767.6"
- process $proc$libresoc.v:50759$3194
+ attribute \src "libresoc.v:50584.3-50592.6"
+ process $proc$libresoc.v:50584$3178
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196
- attribute \src "libresoc.v:50760.5-50760.29"
+ assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180
+ attribute \src "libresoc.v:50585.5-50585.29"
switch \initial
- attribute \src "libresoc.v:50760.9-50760.17"
+ attribute \src "libresoc.v:50585.9-50585.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[2:0]$3196 3'111
+ assign $1\req_l_r_req$next[2:0]$3180 3'111
case
- assign $1\req_l_r_req$next[2:0]$3196 \$69
+ assign $1\req_l_r_req$next[2:0]$3180 \$69
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195
+ update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179
end
- attribute \src "libresoc.v:50768.3-50779.6"
- process $proc$libresoc.v:50768$3197
+ attribute \src "libresoc.v:50593.3-50604.6"
+ process $proc$libresoc.v:50593$3181
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201
- assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202
- assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203
- attribute \src "libresoc.v:50769.5-50769.29"
+ assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185
+ assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186
+ assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187
+ attribute \src "libresoc.v:50594.5-50594.29"
switch \initial
- attribute \src "libresoc.v:50769.9-50769.17"
+ attribute \src "libresoc.v:50594.9-50594.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_cr0_cr_op__insn$next[31:0]$3202 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type }
+ assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type }
case
- assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 \alu_cr0_cr_op__fn_unit
- assign $1\alu_cr0_cr_op__insn$next[31:0]$3202 \alu_cr0_cr_op__insn
- assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 \alu_cr0_cr_op__insn_type
+ assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit
+ assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn
+ assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type
end
sync always
- update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198
- update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199
- update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200
+ update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182
+ update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183
+ update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184
end
- attribute \src "libresoc.v:50780.3-50801.6"
- process $proc$libresoc.v:50780$3204
+ attribute \src "libresoc.v:50605.3-50626.6"
+ process $proc$libresoc.v:50605$3188
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209
+ assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211
- attribute \src "libresoc.v:50781.5-50781.29"
+ assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195
+ attribute \src "libresoc.v:50606.5-50606.29"
switch \initial
- attribute \src "libresoc.v:50781.9-50781.17"
+ attribute \src "libresoc.v:50606.9-50606.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$3208 $1\data_r0__o$next[63:0]$3207 } { \o_ok \alu_cr0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o }
case
- assign $1\data_r0__o$next[63:0]$3207 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$3208 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$3191 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$3210 $2\data_r0__o$next[63:0]$3209 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$3209 $1\data_r0__o$next[63:0]$3207
- assign $2\data_r0__o_ok$next[0:0]$3210 $1\data_r0__o_ok$next[0:0]$3208
+ assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191
+ assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$3211 1'0
+ assign $3\data_r0__o_ok$next[0:0]$3195 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$3211 $2\data_r0__o_ok$next[0:0]$3210
+ assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$3205
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$3189
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190
end
- attribute \src "libresoc.v:50802.3-50823.6"
- process $proc$libresoc.v:50802$3212
+ attribute \src "libresoc.v:50627.3-50648.6"
+ process $proc$libresoc.v:50627$3196
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217
+ assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201
assign { } { }
- assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219
- attribute \src "libresoc.v:50803.5-50803.29"
+ assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203
+ attribute \src "libresoc.v:50628.5-50628.29"
switch \initial
- attribute \src "libresoc.v:50803.9-50803.17"
+ attribute \src "libresoc.v:50628.9-50628.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__full_cr_ok$next[0:0]$3216 $1\data_r1__full_cr$next[31:0]$3215 } { \full_cr_ok \alu_cr0_full_cr }
+ assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr }
case
- assign $1\data_r1__full_cr$next[31:0]$3215 \data_r1__full_cr
- assign $1\data_r1__full_cr_ok$next[0:0]$3216 \data_r1__full_cr_ok
+ assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr
+ assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__full_cr_ok$next[0:0]$3218 $2\data_r1__full_cr$next[31:0]$3217 } 33'000000000000000000000000000000000
+ assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000
case
- assign $2\data_r1__full_cr$next[31:0]$3217 $1\data_r1__full_cr$next[31:0]$3215
- assign $2\data_r1__full_cr_ok$next[0:0]$3218 $1\data_r1__full_cr_ok$next[0:0]$3216
+ assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199
+ assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__full_cr_ok$next[0:0]$3219 1'0
+ assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0
case
- assign $3\data_r1__full_cr_ok$next[0:0]$3219 $2\data_r1__full_cr_ok$next[0:0]$3218
+ assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202
end
sync always
- update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213
- update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214
+ update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197
+ update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198
end
- attribute \src "libresoc.v:50824.3-50845.6"
- process $proc$libresoc.v:50824$3220
+ attribute \src "libresoc.v:50649.3-50670.6"
+ process $proc$libresoc.v:50649$3204
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225
+ assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209
assign { } { }
- assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227
- attribute \src "libresoc.v:50825.5-50825.29"
+ assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211
+ attribute \src "libresoc.v:50650.5-50650.29"
switch \initial
- attribute \src "libresoc.v:50825.9-50825.17"
+ attribute \src "libresoc.v:50650.9-50650.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__cr_a_ok$next[0:0]$3224 $1\data_r2__cr_a$next[3:0]$3223 } { \cr_a_ok \alu_cr0_cr_a }
+ assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a }
case
- assign $1\data_r2__cr_a$next[3:0]$3223 \data_r2__cr_a
- assign $1\data_r2__cr_a_ok$next[0:0]$3224 \data_r2__cr_a_ok
+ assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a
+ assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__cr_a_ok$next[0:0]$3226 $2\data_r2__cr_a$next[3:0]$3225 } 5'00000
+ assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000
case
- assign $2\data_r2__cr_a$next[3:0]$3225 $1\data_r2__cr_a$next[3:0]$3223
- assign $2\data_r2__cr_a_ok$next[0:0]$3226 $1\data_r2__cr_a_ok$next[0:0]$3224
+ assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207
+ assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__cr_a_ok$next[0:0]$3227 1'0
+ assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0
case
- assign $3\data_r2__cr_a_ok$next[0:0]$3227 $2\data_r2__cr_a_ok$next[0:0]$3226
+ assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210
end
sync always
- update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221
- update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222
+ update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205
+ update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206
end
- attribute \src "libresoc.v:50846.3-50855.6"
- process $proc$libresoc.v:50846$3228
+ attribute \src "libresoc.v:50671.3-50680.6"
+ process $proc$libresoc.v:50671$3212
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230
- attribute \src "libresoc.v:50847.5-50847.29"
+ assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214
+ attribute \src "libresoc.v:50672.5-50672.29"
switch \initial
- attribute \src "libresoc.v:50847.9-50847.17"
+ attribute \src "libresoc.v:50672.9-50672.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$3230 \src1_i
+ assign $1\src_r0$next[63:0]$3214 \src1_i
case
- assign $1\src_r0$next[63:0]$3230 \src_r0
+ assign $1\src_r0$next[63:0]$3214 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$3229
+ update \src_r0$next $0\src_r0$next[63:0]$3213
end
- attribute \src "libresoc.v:50856.3-50865.6"
- process $proc$libresoc.v:50856$3231
+ attribute \src "libresoc.v:50681.3-50690.6"
+ process $proc$libresoc.v:50681$3215
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233
- attribute \src "libresoc.v:50857.5-50857.29"
+ assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217
+ attribute \src "libresoc.v:50682.5-50682.29"
switch \initial
- attribute \src "libresoc.v:50857.9-50857.17"
+ attribute \src "libresoc.v:50682.9-50682.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$3233 \src2_i
+ assign $1\src_r1$next[63:0]$3217 \src2_i
case
- assign $1\src_r1$next[63:0]$3233 \src_r1
+ assign $1\src_r1$next[63:0]$3217 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$3232
+ update \src_r1$next $0\src_r1$next[63:0]$3216
end
- attribute \src "libresoc.v:50866.3-50875.6"
- process $proc$libresoc.v:50866$3234
+ attribute \src "libresoc.v:50691.3-50700.6"
+ process $proc$libresoc.v:50691$3218
assign { } { }
assign { } { }
- assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236
- attribute \src "libresoc.v:50867.5-50867.29"
+ assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220
+ attribute \src "libresoc.v:50692.5-50692.29"
switch \initial
- attribute \src "libresoc.v:50867.9-50867.17"
+ attribute \src "libresoc.v:50692.9-50692.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[31:0]$3236 \src3_i
+ assign $1\src_r2$next[31:0]$3220 \src3_i
case
- assign $1\src_r2$next[31:0]$3236 \src_r2
+ assign $1\src_r2$next[31:0]$3220 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[31:0]$3235
+ update \src_r2$next $0\src_r2$next[31:0]$3219
end
- attribute \src "libresoc.v:50876.3-50885.6"
- process $proc$libresoc.v:50876$3237
+ attribute \src "libresoc.v:50701.3-50710.6"
+ process $proc$libresoc.v:50701$3221
assign { } { }
assign { } { }
- assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239
- attribute \src "libresoc.v:50877.5-50877.29"
+ assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223
+ attribute \src "libresoc.v:50702.5-50702.29"
switch \initial
- attribute \src "libresoc.v:50877.9-50877.17"
+ attribute \src "libresoc.v:50702.9-50702.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[3:0]$3239 \src4_i
+ assign $1\src_r3$next[3:0]$3223 \src4_i
case
- assign $1\src_r3$next[3:0]$3239 \src_r3
+ assign $1\src_r3$next[3:0]$3223 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[3:0]$3238
+ update \src_r3$next $0\src_r3$next[3:0]$3222
end
- attribute \src "libresoc.v:50886.3-50895.6"
- process $proc$libresoc.v:50886$3240
+ attribute \src "libresoc.v:50711.3-50720.6"
+ process $proc$libresoc.v:50711$3224
assign { } { }
assign { } { }
- assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242
- attribute \src "libresoc.v:50887.5-50887.29"
+ assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226
+ attribute \src "libresoc.v:50712.5-50712.29"
switch \initial
- attribute \src "libresoc.v:50887.9-50887.17"
+ attribute \src "libresoc.v:50712.9-50712.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[3:0]$3242 \src5_i
+ assign $1\src_r4$next[3:0]$3226 \src5_i
case
- assign $1\src_r4$next[3:0]$3242 \src_r4
+ assign $1\src_r4$next[3:0]$3226 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[3:0]$3241
+ update \src_r4$next $0\src_r4$next[3:0]$3225
end
- attribute \src "libresoc.v:50896.3-50905.6"
- process $proc$libresoc.v:50896$3243
+ attribute \src "libresoc.v:50721.3-50730.6"
+ process $proc$libresoc.v:50721$3227
assign { } { }
assign { } { }
- assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245
- attribute \src "libresoc.v:50897.5-50897.29"
+ assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229
+ attribute \src "libresoc.v:50722.5-50722.29"
switch \initial
- attribute \src "libresoc.v:50897.9-50897.17"
+ attribute \src "libresoc.v:50722.9-50722.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r5$next[3:0]$3245 \src6_i
+ assign $1\src_r5$next[3:0]$3229 \src6_i
case
- assign $1\src_r5$next[3:0]$3245 \src_r5
+ assign $1\src_r5$next[3:0]$3229 \src_r5
end
sync always
- update \src_r5$next $0\src_r5$next[3:0]$3244
+ update \src_r5$next $0\src_r5$next[3:0]$3228
end
- attribute \src "libresoc.v:50906.3-50914.6"
- process $proc$libresoc.v:50906$3246
+ attribute \src "libresoc.v:50731.3-50739.6"
+ process $proc$libresoc.v:50731$3230
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248
- attribute \src "libresoc.v:50907.5-50907.29"
+ assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232
+ attribute \src "libresoc.v:50732.5-50732.29"
switch \initial
- attribute \src "libresoc.v:50907.9-50907.17"
+ attribute \src "libresoc.v:50732.9-50732.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$3248 1'1
+ assign $1\alui_l_r_alui$next[0:0]$3232 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$3248 \$89
+ assign $1\alui_l_r_alui$next[0:0]$3232 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231
end
- attribute \src "libresoc.v:50915.3-50923.6"
- process $proc$libresoc.v:50915$3249
+ attribute \src "libresoc.v:50740.3-50748.6"
+ process $proc$libresoc.v:50740$3233
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251
- attribute \src "libresoc.v:50916.5-50916.29"
+ assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235
+ attribute \src "libresoc.v:50741.5-50741.29"
switch \initial
- attribute \src "libresoc.v:50916.9-50916.17"
+ attribute \src "libresoc.v:50741.9-50741.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$3251 1'1
+ assign $1\alu_l_r_alu$next[0:0]$3235 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$3251 \$91
+ assign $1\alu_l_r_alu$next[0:0]$3235 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234
end
- attribute \src "libresoc.v:50924.3-50933.6"
- process $proc$libresoc.v:50924$3252
+ attribute \src "libresoc.v:50749.3-50758.6"
+ process $proc$libresoc.v:50749$3236
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:50925.5-50925.29"
+ attribute \src "libresoc.v:50750.5-50750.29"
switch \initial
- attribute \src "libresoc.v:50925.9-50925.17"
+ attribute \src "libresoc.v:50750.9-50750.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:50934.3-50943.6"
- process $proc$libresoc.v:50934$3253
+ attribute \src "libresoc.v:50759.3-50768.6"
+ process $proc$libresoc.v:50759$3237
assign { } { }
assign { } { }
assign $0\dest2_o[31:0] $1\dest2_o[31:0]
- attribute \src "libresoc.v:50935.5-50935.29"
+ attribute \src "libresoc.v:50760.5-50760.29"
switch \initial
- attribute \src "libresoc.v:50935.9-50935.17"
+ attribute \src "libresoc.v:50760.9-50760.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[31:0]
end
- attribute \src "libresoc.v:50944.3-50953.6"
- process $proc$libresoc.v:50944$3254
+ attribute \src "libresoc.v:50769.3-50778.6"
+ process $proc$libresoc.v:50769$3238
assign { } { }
assign { } { }
assign $0\dest3_o[3:0] $1\dest3_o[3:0]
- attribute \src "libresoc.v:50945.5-50945.29"
+ attribute \src "libresoc.v:50770.5-50770.29"
switch \initial
- attribute \src "libresoc.v:50945.9-50945.17"
+ attribute \src "libresoc.v:50770.9-50770.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[3:0]
end
- attribute \src "libresoc.v:50954.3-50962.6"
- process $proc$libresoc.v:50954$3255
+ attribute \src "libresoc.v:50779.3-50787.6"
+ process $proc$libresoc.v:50779$3239
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257
- attribute \src "libresoc.v:50955.5-50955.29"
+ assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241
+ attribute \src "libresoc.v:50780.5-50780.29"
switch \initial
- attribute \src "libresoc.v:50955.9-50955.17"
+ attribute \src "libresoc.v:50780.9-50780.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[2:0]$3257 3'000
- case
- assign $1\prev_wr_go$next[2:0]$3257 \$21
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256
- end
- connect \$5 $reduce_and$libresoc.v:50480$3079_Y
- connect \$99 $and$libresoc.v:50481$3080_Y
- connect \$101 $and$libresoc.v:50482$3081_Y
- connect \$103 $and$libresoc.v:50483$3082_Y
- connect \$105 $and$libresoc.v:50484$3083_Y
- connect \$107 $and$libresoc.v:50485$3084_Y
- connect \$109 $and$libresoc.v:50486$3085_Y
- connect \$111 $and$libresoc.v:50487$3086_Y
- connect \$113 $and$libresoc.v:50488$3087_Y
- connect \$115 $and$libresoc.v:50489$3088_Y
- connect \$11 $and$libresoc.v:50490$3089_Y
- connect \$13 $not$libresoc.v:50491$3090_Y
- connect \$15 $and$libresoc.v:50492$3091_Y
- connect \$17 $not$libresoc.v:50493$3092_Y
- connect \$19 $and$libresoc.v:50494$3093_Y
- connect \$21 $and$libresoc.v:50495$3094_Y
- connect \$25 $not$libresoc.v:50496$3095_Y
- connect \$27 $and$libresoc.v:50497$3096_Y
- connect \$24 $reduce_or$libresoc.v:50498$3097_Y
- connect \$23 $not$libresoc.v:50499$3098_Y
- connect \$31 $and$libresoc.v:50500$3099_Y
- connect \$33 $reduce_or$libresoc.v:50501$3100_Y
- connect \$35 $reduce_or$libresoc.v:50502$3101_Y
- connect \$37 $or$libresoc.v:50503$3102_Y
- connect \$3 $and$libresoc.v:50504$3103_Y
- connect \$39 $not$libresoc.v:50505$3104_Y
- connect \$41 $and$libresoc.v:50506$3105_Y
- connect \$43 $and$libresoc.v:50507$3106_Y
- connect \$45 $eq$libresoc.v:50508$3107_Y
- connect \$47 $and$libresoc.v:50509$3108_Y
- connect \$49 $eq$libresoc.v:50510$3109_Y
- connect \$51 $and$libresoc.v:50511$3110_Y
- connect \$53 $and$libresoc.v:50512$3111_Y
- connect \$55 $and$libresoc.v:50513$3112_Y
- connect \$57 $or$libresoc.v:50514$3113_Y
- connect \$59 $or$libresoc.v:50515$3114_Y
- connect \$61 $or$libresoc.v:50516$3115_Y
- connect \$63 $or$libresoc.v:50517$3116_Y
- connect \$65 $and$libresoc.v:50518$3117_Y
- connect \$67 $and$libresoc.v:50519$3118_Y
- connect \$6 $not$libresoc.v:50520$3119_Y
- connect \$69 $or$libresoc.v:50521$3120_Y
- connect \$71 $and$libresoc.v:50522$3121_Y
- connect \$73 $and$libresoc.v:50523$3122_Y
- connect \$75 $and$libresoc.v:50524$3123_Y
- connect \$77 $ternary$libresoc.v:50525$3124_Y
- connect \$79 $ternary$libresoc.v:50526$3125_Y
- connect \$81 $ternary$libresoc.v:50527$3126_Y
- connect \$83 $ternary$libresoc.v:50528$3127_Y
- connect \$85 $ternary$libresoc.v:50529$3128_Y
- connect \$87 $ternary$libresoc.v:50530$3129_Y
- connect \$8 $or$libresoc.v:50531$3130_Y
- connect \$89 $and$libresoc.v:50532$3131_Y
- connect \$91 $and$libresoc.v:50533$3132_Y
- connect \$93 $and$libresoc.v:50534$3133_Y
- connect \$95 $and$libresoc.v:50535$3134_Y
- connect \$97 $not$libresoc.v:50536$3135_Y
+ assign $1\prev_wr_go$next[2:0]$3241 3'000
+ case
+ assign $1\prev_wr_go$next[2:0]$3241 \$21
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240
+ end
+ connect \$5 $reduce_and$libresoc.v:50305$3063_Y
+ connect \$99 $and$libresoc.v:50306$3064_Y
+ connect \$101 $and$libresoc.v:50307$3065_Y
+ connect \$103 $and$libresoc.v:50308$3066_Y
+ connect \$105 $and$libresoc.v:50309$3067_Y
+ connect \$107 $and$libresoc.v:50310$3068_Y
+ connect \$109 $and$libresoc.v:50311$3069_Y
+ connect \$111 $and$libresoc.v:50312$3070_Y
+ connect \$113 $and$libresoc.v:50313$3071_Y
+ connect \$115 $and$libresoc.v:50314$3072_Y
+ connect \$11 $and$libresoc.v:50315$3073_Y
+ connect \$13 $not$libresoc.v:50316$3074_Y
+ connect \$15 $and$libresoc.v:50317$3075_Y
+ connect \$17 $not$libresoc.v:50318$3076_Y
+ connect \$19 $and$libresoc.v:50319$3077_Y
+ connect \$21 $and$libresoc.v:50320$3078_Y
+ connect \$25 $not$libresoc.v:50321$3079_Y
+ connect \$27 $and$libresoc.v:50322$3080_Y
+ connect \$24 $reduce_or$libresoc.v:50323$3081_Y
+ connect \$23 $not$libresoc.v:50324$3082_Y
+ connect \$31 $and$libresoc.v:50325$3083_Y
+ connect \$33 $reduce_or$libresoc.v:50326$3084_Y
+ connect \$35 $reduce_or$libresoc.v:50327$3085_Y
+ connect \$37 $or$libresoc.v:50328$3086_Y
+ connect \$3 $and$libresoc.v:50329$3087_Y
+ connect \$39 $not$libresoc.v:50330$3088_Y
+ connect \$41 $and$libresoc.v:50331$3089_Y
+ connect \$43 $and$libresoc.v:50332$3090_Y
+ connect \$45 $eq$libresoc.v:50333$3091_Y
+ connect \$47 $and$libresoc.v:50334$3092_Y
+ connect \$49 $eq$libresoc.v:50335$3093_Y
+ connect \$51 $and$libresoc.v:50336$3094_Y
+ connect \$53 $and$libresoc.v:50337$3095_Y
+ connect \$55 $and$libresoc.v:50338$3096_Y
+ connect \$57 $or$libresoc.v:50339$3097_Y
+ connect \$59 $or$libresoc.v:50340$3098_Y
+ connect \$61 $or$libresoc.v:50341$3099_Y
+ connect \$63 $or$libresoc.v:50342$3100_Y
+ connect \$65 $and$libresoc.v:50343$3101_Y
+ connect \$67 $and$libresoc.v:50344$3102_Y
+ connect \$6 $not$libresoc.v:50345$3103_Y
+ connect \$69 $or$libresoc.v:50346$3104_Y
+ connect \$71 $and$libresoc.v:50347$3105_Y
+ connect \$73 $and$libresoc.v:50348$3106_Y
+ connect \$75 $and$libresoc.v:50349$3107_Y
+ connect \$77 $ternary$libresoc.v:50350$3108_Y
+ connect \$79 $ternary$libresoc.v:50351$3109_Y
+ connect \$81 $ternary$libresoc.v:50352$3110_Y
+ connect \$83 $ternary$libresoc.v:50353$3111_Y
+ connect \$85 $ternary$libresoc.v:50354$3112_Y
+ connect \$87 $ternary$libresoc.v:50355$3113_Y
+ connect \$8 $or$libresoc.v:50356$3114_Y
+ connect \$89 $and$libresoc.v:50357$3115_Y
+ connect \$91 $and$libresoc.v:50358$3116_Y
+ connect \$93 $and$libresoc.v:50359$3117_Y
+ connect \$95 $and$libresoc.v:50360$3118_Y
+ connect \$97 $not$libresoc.v:50361$3119_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$109
connect \all_rd_dly$next \all_rd
connect \all_rd \$11
end
-attribute \src "libresoc.v:50998.1-51047.10"
+attribute \src "libresoc.v:50823.1-50872.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l"
attribute \generator "nMigen"
module \cyc_l
- attribute \src "libresoc.v:50999.7-50999.20"
+ attribute \src "libresoc.v:50824.7-50824.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51035.3-51043.6"
- wire $0\q_int$next[0:0]$3296
- attribute \src "libresoc.v:51033.3-51034.27"
+ attribute \src "libresoc.v:50860.3-50868.6"
+ wire $0\q_int$next[0:0]$3280
+ attribute \src "libresoc.v:50858.3-50859.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:51035.3-51043.6"
- wire $1\q_int$next[0:0]$3297
- attribute \src "libresoc.v:51017.7-51017.19"
+ attribute \src "libresoc.v:50860.3-50868.6"
+ wire $1\q_int$next[0:0]$3281
+ attribute \src "libresoc.v:50842.7-50842.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:51030.17-51030.96"
- wire $and$libresoc.v:51030$3291_Y
- attribute \src "libresoc.v:51029.17-51029.92"
- wire $not$libresoc.v:51029$3290_Y
- attribute \src "libresoc.v:51032.17-51032.92"
- wire $not$libresoc.v:51032$3293_Y
- attribute \src "libresoc.v:51028.17-51028.98"
- wire $or$libresoc.v:51028$3289_Y
- attribute \src "libresoc.v:51031.17-51031.97"
- wire $or$libresoc.v:51031$3292_Y
+ attribute \src "libresoc.v:50855.17-50855.96"
+ wire $and$libresoc.v:50855$3275_Y
+ attribute \src "libresoc.v:50854.17-50854.92"
+ wire $not$libresoc.v:50854$3274_Y
+ attribute \src "libresoc.v:50857.17-50857.92"
+ wire $not$libresoc.v:50857$3277_Y
+ attribute \src "libresoc.v:50853.17-50853.98"
+ wire $or$libresoc.v:50853$3273_Y
+ attribute \src "libresoc.v:50856.17-50856.97"
+ wire $or$libresoc.v:50856$3276_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:50999.7-50999.15"
+ attribute \src "libresoc.v:50824.7-50824.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire output 4 \q_cyc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_cyc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:51030$3291
+ cell $and $and$libresoc.v:50855$3275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:51030$3291_Y
+ connect \Y $and$libresoc.v:50855$3275_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:51029$3290
+ cell $not $not$libresoc.v:50854$3274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_cyc
- connect \Y $not$libresoc.v:51029$3290_Y
+ connect \Y $not$libresoc.v:50854$3274_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:51032$3293
+ cell $not $not$libresoc.v:50857$3277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_cyc
- connect \Y $not$libresoc.v:51032$3293_Y
+ connect \Y $not$libresoc.v:50857$3277_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:51028$3289
+ cell $or $or$libresoc.v:50853$3273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_cyc
connect \B \q_int
- connect \Y $or$libresoc.v:51028$3289_Y
+ connect \Y $or$libresoc.v:50853$3273_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:51031$3292
+ cell $or $or$libresoc.v:50856$3276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_cyc
- connect \Y $or$libresoc.v:51031$3292_Y
+ connect \Y $or$libresoc.v:50856$3276_Y
end
- attribute \src "libresoc.v:50999.7-50999.20"
- process $proc$libresoc.v:50999$3298
+ attribute \src "libresoc.v:50824.7-50824.20"
+ process $proc$libresoc.v:50824$3282
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:51017.7-51017.19"
- process $proc$libresoc.v:51017$3299
+ attribute \src "libresoc.v:50842.7-50842.19"
+ process $proc$libresoc.v:50842$3283
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:51033.3-51034.27"
- process $proc$libresoc.v:51033$3294
+ attribute \src "libresoc.v:50858.3-50859.27"
+ process $proc$libresoc.v:50858$3278
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:51035.3-51043.6"
- process $proc$libresoc.v:51035$3295
+ attribute \src "libresoc.v:50860.3-50868.6"
+ process $proc$libresoc.v:50860$3279
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297
- attribute \src "libresoc.v:51036.5-51036.29"
+ assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281
+ attribute \src "libresoc.v:50861.5-50861.29"
switch \initial
- attribute \src "libresoc.v:51036.9-51036.17"
+ attribute \src "libresoc.v:50861.9-50861.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$3297 1'0
+ assign $1\q_int$next[0:0]$3281 1'0
case
- assign $1\q_int$next[0:0]$3297 \$5
+ assign $1\q_int$next[0:0]$3281 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$3296
+ update \q_int$next $0\q_int$next[0:0]$3280
end
- connect \$9 $or$libresoc.v:51028$3289_Y
- connect \$1 $not$libresoc.v:51029$3290_Y
- connect \$3 $and$libresoc.v:51030$3291_Y
- connect \$5 $or$libresoc.v:51031$3292_Y
- connect \$7 $not$libresoc.v:51032$3293_Y
+ connect \$9 $or$libresoc.v:50853$3273_Y
+ connect \$1 $not$libresoc.v:50854$3274_Y
+ connect \$3 $and$libresoc.v:50855$3275_Y
+ connect \$5 $or$libresoc.v:50856$3276_Y
+ connect \$7 $not$libresoc.v:50857$3277_Y
connect \qlq_cyc \$9
connect \qn_cyc \$7
connect \q_cyc \q_int
end
-attribute \src "libresoc.v:51051.1-51792.10"
+attribute \src "libresoc.v:50876.1-51617.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dbg"
attribute \generator "nMigen"
module \dbg
- attribute \src "libresoc.v:51596.3-51608.6"
+ attribute \src "libresoc.v:51421.3-51433.6"
wire $0\d_cr_req[0:0]
- attribute \src "libresoc.v:51403.3-51412.6"
+ attribute \src "libresoc.v:51228.3-51237.6"
wire $0\d_gpr_req[0:0]
- attribute \src "libresoc.v:51609.3-51624.6"
+ attribute \src "libresoc.v:51434.3-51449.6"
wire $0\d_xer_req[0:0]
- attribute \src "libresoc.v:51385.3-51402.6"
+ attribute \src "libresoc.v:51210.3-51227.6"
wire $0\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51625.3-51658.6"
+ attribute \src "libresoc.v:51450.3-51483.6"
wire width 64 $0\dmi_dout[63:0]
- attribute \src "libresoc.v:51587.3-51595.6"
- wire $0\dmi_read_log_data$next[0:0]$3414
- attribute \src "libresoc.v:51363.3-51364.51"
+ attribute \src "libresoc.v:51412.3-51420.6"
+ wire $0\dmi_read_log_data$next[0:0]$3398
+ attribute \src "libresoc.v:51188.3-51189.51"
wire $0\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:51578.3-51586.6"
- wire $0\dmi_read_log_data_1$next[0:0]$3411
- attribute \src "libresoc.v:51365.3-51366.55"
+ attribute \src "libresoc.v:51403.3-51411.6"
+ wire $0\dmi_read_log_data_1$next[0:0]$3395
+ attribute \src "libresoc.v:51190.3-51191.55"
wire $0\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:51413.3-51421.6"
- wire $0\dmi_req_i_1$next[0:0]$3377
- attribute \src "libresoc.v:51375.3-51376.39"
+ attribute \src "libresoc.v:51238.3-51246.6"
+ wire $0\dmi_req_i_1$next[0:0]$3361
+ attribute \src "libresoc.v:51200.3-51201.39"
wire $0\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:51749.3-51782.6"
- wire $0\do_dmi_log_rd$next[0:0]$3441
- attribute \src "libresoc.v:51377.3-51378.43"
+ attribute \src "libresoc.v:51574.3-51607.6"
+ wire $0\do_dmi_log_rd$next[0:0]$3425
+ attribute \src "libresoc.v:51202.3-51203.43"
wire $0\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $0\do_icreset$next[0:0]$3434
- attribute \src "libresoc.v:51379.3-51380.37"
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $0\do_icreset$next[0:0]$3418
+ attribute \src "libresoc.v:51204.3-51205.37"
wire $0\do_icreset[0:0]
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $0\do_reset$next[0:0]$3427
- attribute \src "libresoc.v:51381.3-51382.33"
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $0\do_reset$next[0:0]$3411
+ attribute \src "libresoc.v:51206.3-51207.33"
wire $0\do_reset[0:0]
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $0\do_step$next[0:0]$3420
- attribute \src "libresoc.v:51383.3-51384.31"
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $0\do_step$next[0:0]$3404
+ attribute \src "libresoc.v:51208.3-51209.31"
wire $0\do_step[0:0]
- attribute \src "libresoc.v:51516.3-51543.6"
- wire width 7 $0\gspr_index$next[6:0]$3399
- attribute \src "libresoc.v:51369.3-51370.37"
+ attribute \src "libresoc.v:51341.3-51368.6"
+ wire width 7 $0\gspr_index$next[6:0]$3383
+ attribute \src "libresoc.v:51194.3-51195.37"
wire width 7 $0\gspr_index[6:0]
- attribute \src "libresoc.v:51052.7-51052.20"
+ attribute \src "libresoc.v:50877.7-50877.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51544.3-51577.6"
- wire width 32 $0\log_dmi_addr$next[31:0]$3405
- attribute \src "libresoc.v:51367.3-51368.41"
+ attribute \src "libresoc.v:51369.3-51402.6"
+ wire width 32 $0\log_dmi_addr$next[31:0]$3389
+ attribute \src "libresoc.v:51192.3-51193.41"
wire width 32 $0\log_dmi_addr[31:0]
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $0\stopping$next[0:0]$3390
- attribute \src "libresoc.v:51371.3-51372.33"
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $0\stopping$next[0:0]$3374
+ attribute \src "libresoc.v:51196.3-51197.33"
wire $0\stopping[0:0]
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $0\terminated$next[0:0]$3380
- attribute \src "libresoc.v:51373.3-51374.37"
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $0\terminated$next[0:0]$3364
+ attribute \src "libresoc.v:51198.3-51199.37"
wire $0\terminated[0:0]
- attribute \src "libresoc.v:51596.3-51608.6"
+ attribute \src "libresoc.v:51421.3-51433.6"
wire $1\d_cr_req[0:0]
- attribute \src "libresoc.v:51403.3-51412.6"
+ attribute \src "libresoc.v:51228.3-51237.6"
wire $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:51609.3-51624.6"
+ attribute \src "libresoc.v:51434.3-51449.6"
wire $1\d_xer_req[0:0]
- attribute \src "libresoc.v:51385.3-51402.6"
+ attribute \src "libresoc.v:51210.3-51227.6"
wire $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51625.3-51658.6"
+ attribute \src "libresoc.v:51450.3-51483.6"
wire width 64 $1\dmi_dout[63:0]
- attribute \src "libresoc.v:51587.3-51595.6"
- wire $1\dmi_read_log_data$next[0:0]$3415
- attribute \src "libresoc.v:51239.7-51239.31"
+ attribute \src "libresoc.v:51412.3-51420.6"
+ wire $1\dmi_read_log_data$next[0:0]$3399
+ attribute \src "libresoc.v:51064.7-51064.31"
wire $1\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:51578.3-51586.6"
- wire $1\dmi_read_log_data_1$next[0:0]$3412
- attribute \src "libresoc.v:51243.7-51243.33"
+ attribute \src "libresoc.v:51403.3-51411.6"
+ wire $1\dmi_read_log_data_1$next[0:0]$3396
+ attribute \src "libresoc.v:51068.7-51068.33"
wire $1\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:51413.3-51421.6"
- wire $1\dmi_req_i_1$next[0:0]$3378
- attribute \src "libresoc.v:51249.7-51249.25"
+ attribute \src "libresoc.v:51238.3-51246.6"
+ wire $1\dmi_req_i_1$next[0:0]$3362
+ attribute \src "libresoc.v:51074.7-51074.25"
wire $1\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:51749.3-51782.6"
- wire $1\do_dmi_log_rd$next[0:0]$3442
- attribute \src "libresoc.v:51255.7-51255.27"
+ attribute \src "libresoc.v:51574.3-51607.6"
+ wire $1\do_dmi_log_rd$next[0:0]$3426
+ attribute \src "libresoc.v:51080.7-51080.27"
wire $1\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $1\do_icreset$next[0:0]$3435
- attribute \src "libresoc.v:51259.7-51259.24"
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $1\do_icreset$next[0:0]$3419
+ attribute \src "libresoc.v:51084.7-51084.24"
wire $1\do_icreset[0:0]
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $1\do_reset$next[0:0]$3428
- attribute \src "libresoc.v:51263.7-51263.22"
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $1\do_reset$next[0:0]$3412
+ attribute \src "libresoc.v:51088.7-51088.22"
wire $1\do_reset[0:0]
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $1\do_step$next[0:0]$3421
- attribute \src "libresoc.v:51267.7-51267.21"
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $1\do_step$next[0:0]$3405
+ attribute \src "libresoc.v:51092.7-51092.21"
wire $1\do_step[0:0]
- attribute \src "libresoc.v:51516.3-51543.6"
- wire width 7 $1\gspr_index$next[6:0]$3400
- attribute \src "libresoc.v:51271.13-51271.31"
+ attribute \src "libresoc.v:51341.3-51368.6"
+ wire width 7 $1\gspr_index$next[6:0]$3384
+ attribute \src "libresoc.v:51096.13-51096.31"
wire width 7 $1\gspr_index[6:0]
- attribute \src "libresoc.v:51544.3-51577.6"
- wire width 32 $1\log_dmi_addr$next[31:0]$3406
- attribute \src "libresoc.v:51277.14-51277.34"
+ attribute \src "libresoc.v:51369.3-51402.6"
+ wire width 32 $1\log_dmi_addr$next[31:0]$3390
+ attribute \src "libresoc.v:51102.14-51102.34"
wire width 32 $1\log_dmi_addr[31:0]
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $1\stopping$next[0:0]$3391
- attribute \src "libresoc.v:51289.7-51289.22"
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $1\stopping$next[0:0]$3375
+ attribute \src "libresoc.v:51114.7-51114.22"
wire $1\stopping[0:0]
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $1\terminated$next[0:0]$3381
- attribute \src "libresoc.v:51295.7-51295.24"
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $1\terminated$next[0:0]$3365
+ attribute \src "libresoc.v:51120.7-51120.24"
wire $1\terminated[0:0]
- attribute \src "libresoc.v:51749.3-51782.6"
- wire $2\do_dmi_log_rd$next[0:0]$3443
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $2\do_icreset$next[0:0]$3436
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $2\do_reset$next[0:0]$3429
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $2\do_step$next[0:0]$3422
- attribute \src "libresoc.v:51516.3-51543.6"
- wire width 7 $2\gspr_index$next[6:0]$3401
- attribute \src "libresoc.v:51544.3-51577.6"
- wire width 32 $2\log_dmi_addr$next[31:0]$3407
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $2\stopping$next[0:0]$3392
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $2\terminated$next[0:0]$3382
- attribute \src "libresoc.v:51749.3-51782.6"
- wire $3\do_dmi_log_rd$next[0:0]$3444
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $3\do_icreset$next[0:0]$3437
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $3\do_reset$next[0:0]$3430
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $3\do_step$next[0:0]$3423
- attribute \src "libresoc.v:51516.3-51543.6"
- wire width 7 $3\gspr_index$next[6:0]$3402
- attribute \src "libresoc.v:51544.3-51577.6"
- wire width 32 $3\log_dmi_addr$next[31:0]$3408
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $3\stopping$next[0:0]$3393
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $3\terminated$next[0:0]$3383
- attribute \src "libresoc.v:51749.3-51782.6"
- wire $4\do_dmi_log_rd$next[0:0]$3445
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $4\do_icreset$next[0:0]$3438
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $4\do_reset$next[0:0]$3431
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $4\do_step$next[0:0]$3424
- attribute \src "libresoc.v:51516.3-51543.6"
- wire width 7 $4\gspr_index$next[6:0]$3403
- attribute \src "libresoc.v:51544.3-51577.6"
- wire width 32 $4\log_dmi_addr$next[31:0]$3409
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $4\stopping$next[0:0]$3394
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $4\terminated$next[0:0]$3384
- attribute \src "libresoc.v:51719.3-51748.6"
- wire $5\do_icreset$next[0:0]$3439
- attribute \src "libresoc.v:51689.3-51718.6"
- wire $5\do_reset$next[0:0]$3432
- attribute \src "libresoc.v:51659.3-51688.6"
- wire $5\do_step$next[0:0]$3425
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $5\stopping$next[0:0]$3395
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $5\terminated$next[0:0]$3385
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $6\stopping$next[0:0]$3396
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $6\terminated$next[0:0]$3386
- attribute \src "libresoc.v:51472.3-51515.6"
- wire $7\stopping$next[0:0]$3397
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $7\terminated$next[0:0]$3387
- attribute \src "libresoc.v:51422.3-51471.6"
- wire $8\terminated$next[0:0]$3388
- attribute \src "libresoc.v:51310.19-51310.110"
- wire width 3 $add$libresoc.v:51310$3310_Y
- attribute \src "libresoc.v:51304.19-51304.103"
- wire $and$libresoc.v:51304$3304_Y
- attribute \src "libresoc.v:51306.19-51306.113"
- wire $and$libresoc.v:51306$3306_Y
- attribute \src "libresoc.v:51311.18-51311.110"
- wire $and$libresoc.v:51311$3311_Y
- attribute \src "libresoc.v:51313.19-51313.103"
- wire $and$libresoc.v:51313$3313_Y
- attribute \src "libresoc.v:51315.19-51315.102"
- wire $and$libresoc.v:51315$3315_Y
- attribute \src "libresoc.v:51321.18-51321.101"
- wire $and$libresoc.v:51321$3321_Y
- attribute \src "libresoc.v:51323.18-51323.111"
- wire $and$libresoc.v:51323$3323_Y
- attribute \src "libresoc.v:51328.18-51328.101"
- wire $and$libresoc.v:51328$3328_Y
- attribute \src "libresoc.v:51331.18-51331.111"
- wire $and$libresoc.v:51331$3331_Y
- attribute \src "libresoc.v:51336.18-51336.101"
- wire $and$libresoc.v:51336$3336_Y
- attribute \src "libresoc.v:51338.18-51338.111"
- wire $and$libresoc.v:51338$3338_Y
- attribute \src "libresoc.v:51344.18-51344.101"
- wire $and$libresoc.v:51344$3344_Y
- attribute \src "libresoc.v:51346.18-51346.111"
- wire $and$libresoc.v:51346$3346_Y
- attribute \src "libresoc.v:51351.18-51351.101"
- wire $and$libresoc.v:51351$3351_Y
- attribute \src "libresoc.v:51352.17-51352.99"
- wire $and$libresoc.v:51352$3352_Y
- attribute \src "libresoc.v:51354.18-51354.111"
- wire $and$libresoc.v:51354$3354_Y
- attribute \src "libresoc.v:51359.18-51359.101"
- wire $and$libresoc.v:51359$3359_Y
- attribute \src "libresoc.v:51361.18-51361.111"
- wire $and$libresoc.v:51361$3361_Y
- attribute \src "libresoc.v:51301.18-51301.103"
- wire $eq$libresoc.v:51301$3301_Y
- attribute \src "libresoc.v:51302.19-51302.104"
- wire $eq$libresoc.v:51302$3302_Y
- attribute \src "libresoc.v:51307.19-51307.104"
- wire $eq$libresoc.v:51307$3307_Y
- attribute \src "libresoc.v:51308.19-51308.104"
- wire $eq$libresoc.v:51308$3308_Y
- attribute \src "libresoc.v:51309.19-51309.104"
- wire $eq$libresoc.v:51309$3309_Y
- attribute \src "libresoc.v:51312.19-51312.104"
- wire $eq$libresoc.v:51312$3312_Y
- attribute \src "libresoc.v:51316.18-51316.103"
- wire $eq$libresoc.v:51316$3316_Y
- attribute \src "libresoc.v:51317.18-51317.103"
- wire $eq$libresoc.v:51317$3317_Y
- attribute \src "libresoc.v:51318.18-51318.103"
- wire $eq$libresoc.v:51318$3318_Y
- attribute \src "libresoc.v:51324.18-51324.103"
- wire $eq$libresoc.v:51324$3324_Y
- attribute \src "libresoc.v:51325.18-51325.103"
- wire $eq$libresoc.v:51325$3325_Y
- attribute \src "libresoc.v:51326.18-51326.103"
- wire $eq$libresoc.v:51326$3326_Y
- attribute \src "libresoc.v:51332.18-51332.103"
- wire $eq$libresoc.v:51332$3332_Y
- attribute \src "libresoc.v:51333.18-51333.103"
- wire $eq$libresoc.v:51333$3333_Y
- attribute \src "libresoc.v:51334.18-51334.103"
- wire $eq$libresoc.v:51334$3334_Y
- attribute \src "libresoc.v:51339.18-51339.103"
- wire $eq$libresoc.v:51339$3339_Y
- attribute \src "libresoc.v:51340.18-51340.103"
- wire $eq$libresoc.v:51340$3340_Y
- attribute \src "libresoc.v:51342.18-51342.103"
- wire $eq$libresoc.v:51342$3342_Y
- attribute \src "libresoc.v:51347.18-51347.103"
- wire $eq$libresoc.v:51347$3347_Y
- attribute \src "libresoc.v:51348.18-51348.103"
- wire $eq$libresoc.v:51348$3348_Y
- attribute \src "libresoc.v:51349.18-51349.103"
- wire $eq$libresoc.v:51349$3349_Y
- attribute \src "libresoc.v:51355.18-51355.103"
- wire $eq$libresoc.v:51355$3355_Y
- attribute \src "libresoc.v:51356.18-51356.103"
- wire $eq$libresoc.v:51356$3356_Y
- attribute \src "libresoc.v:51357.18-51357.103"
- wire $eq$libresoc.v:51357$3357_Y
- attribute \src "libresoc.v:51362.18-51362.103"
- wire $eq$libresoc.v:51362$3362_Y
- attribute \src "libresoc.v:51300.17-51300.103"
- wire $not$libresoc.v:51300$3300_Y
- attribute \src "libresoc.v:51303.19-51303.99"
- wire $not$libresoc.v:51303$3303_Y
- attribute \src "libresoc.v:51305.19-51305.105"
- wire $not$libresoc.v:51305$3305_Y
- attribute \src "libresoc.v:51314.19-51314.95"
- wire $not$libresoc.v:51314$3314_Y
- attribute \src "libresoc.v:51320.18-51320.98"
- wire $not$libresoc.v:51320$3320_Y
- attribute \src "libresoc.v:51322.18-51322.104"
- wire $not$libresoc.v:51322$3322_Y
- attribute \src "libresoc.v:51327.18-51327.98"
- wire $not$libresoc.v:51327$3327_Y
- attribute \src "libresoc.v:51329.18-51329.104"
- wire $not$libresoc.v:51329$3329_Y
- attribute \src "libresoc.v:51335.18-51335.98"
- wire $not$libresoc.v:51335$3335_Y
- attribute \src "libresoc.v:51337.18-51337.104"
- wire $not$libresoc.v:51337$3337_Y
- attribute \src "libresoc.v:51341.17-51341.97"
- wire $not$libresoc.v:51341$3341_Y
- attribute \src "libresoc.v:51343.18-51343.98"
- wire $not$libresoc.v:51343$3343_Y
- attribute \src "libresoc.v:51345.18-51345.104"
- wire $not$libresoc.v:51345$3345_Y
- attribute \src "libresoc.v:51350.18-51350.98"
- wire $not$libresoc.v:51350$3350_Y
- attribute \src "libresoc.v:51353.18-51353.104"
- wire $not$libresoc.v:51353$3353_Y
- attribute \src "libresoc.v:51358.18-51358.98"
- wire $not$libresoc.v:51358$3358_Y
- attribute \src "libresoc.v:51360.18-51360.104"
- wire $not$libresoc.v:51360$3360_Y
- attribute \src "libresoc.v:51319.17-51319.126"
- wire width 64 $pos$libresoc.v:51319$3319_Y
- attribute \src "libresoc.v:51330.17-51330.245"
- wire width 64 $pos$libresoc.v:51330$3330_Y
+ attribute \src "libresoc.v:51574.3-51607.6"
+ wire $2\do_dmi_log_rd$next[0:0]$3427
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $2\do_icreset$next[0:0]$3420
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $2\do_reset$next[0:0]$3413
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $2\do_step$next[0:0]$3406
+ attribute \src "libresoc.v:51341.3-51368.6"
+ wire width 7 $2\gspr_index$next[6:0]$3385
+ attribute \src "libresoc.v:51369.3-51402.6"
+ wire width 32 $2\log_dmi_addr$next[31:0]$3391
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $2\stopping$next[0:0]$3376
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $2\terminated$next[0:0]$3366
+ attribute \src "libresoc.v:51574.3-51607.6"
+ wire $3\do_dmi_log_rd$next[0:0]$3428
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $3\do_icreset$next[0:0]$3421
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $3\do_reset$next[0:0]$3414
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $3\do_step$next[0:0]$3407
+ attribute \src "libresoc.v:51341.3-51368.6"
+ wire width 7 $3\gspr_index$next[6:0]$3386
+ attribute \src "libresoc.v:51369.3-51402.6"
+ wire width 32 $3\log_dmi_addr$next[31:0]$3392
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $3\stopping$next[0:0]$3377
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $3\terminated$next[0:0]$3367
+ attribute \src "libresoc.v:51574.3-51607.6"
+ wire $4\do_dmi_log_rd$next[0:0]$3429
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $4\do_icreset$next[0:0]$3422
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $4\do_reset$next[0:0]$3415
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $4\do_step$next[0:0]$3408
+ attribute \src "libresoc.v:51341.3-51368.6"
+ wire width 7 $4\gspr_index$next[6:0]$3387
+ attribute \src "libresoc.v:51369.3-51402.6"
+ wire width 32 $4\log_dmi_addr$next[31:0]$3393
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $4\stopping$next[0:0]$3378
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $4\terminated$next[0:0]$3368
+ attribute \src "libresoc.v:51544.3-51573.6"
+ wire $5\do_icreset$next[0:0]$3423
+ attribute \src "libresoc.v:51514.3-51543.6"
+ wire $5\do_reset$next[0:0]$3416
+ attribute \src "libresoc.v:51484.3-51513.6"
+ wire $5\do_step$next[0:0]$3409
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $5\stopping$next[0:0]$3379
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $5\terminated$next[0:0]$3369
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $6\stopping$next[0:0]$3380
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $6\terminated$next[0:0]$3370
+ attribute \src "libresoc.v:51297.3-51340.6"
+ wire $7\stopping$next[0:0]$3381
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $7\terminated$next[0:0]$3371
+ attribute \src "libresoc.v:51247.3-51296.6"
+ wire $8\terminated$next[0:0]$3372
+ attribute \src "libresoc.v:51135.19-51135.110"
+ wire width 3 $add$libresoc.v:51135$3294_Y
+ attribute \src "libresoc.v:51129.19-51129.103"
+ wire $and$libresoc.v:51129$3288_Y
+ attribute \src "libresoc.v:51131.19-51131.113"
+ wire $and$libresoc.v:51131$3290_Y
+ attribute \src "libresoc.v:51136.18-51136.110"
+ wire $and$libresoc.v:51136$3295_Y
+ attribute \src "libresoc.v:51138.19-51138.103"
+ wire $and$libresoc.v:51138$3297_Y
+ attribute \src "libresoc.v:51140.19-51140.102"
+ wire $and$libresoc.v:51140$3299_Y
+ attribute \src "libresoc.v:51146.18-51146.101"
+ wire $and$libresoc.v:51146$3305_Y
+ attribute \src "libresoc.v:51148.18-51148.111"
+ wire $and$libresoc.v:51148$3307_Y
+ attribute \src "libresoc.v:51153.18-51153.101"
+ wire $and$libresoc.v:51153$3312_Y
+ attribute \src "libresoc.v:51156.18-51156.111"
+ wire $and$libresoc.v:51156$3315_Y
+ attribute \src "libresoc.v:51161.18-51161.101"
+ wire $and$libresoc.v:51161$3320_Y
+ attribute \src "libresoc.v:51163.18-51163.111"
+ wire $and$libresoc.v:51163$3322_Y
+ attribute \src "libresoc.v:51169.18-51169.101"
+ wire $and$libresoc.v:51169$3328_Y
+ attribute \src "libresoc.v:51171.18-51171.111"
+ wire $and$libresoc.v:51171$3330_Y
+ attribute \src "libresoc.v:51176.18-51176.101"
+ wire $and$libresoc.v:51176$3335_Y
+ attribute \src "libresoc.v:51177.17-51177.99"
+ wire $and$libresoc.v:51177$3336_Y
+ attribute \src "libresoc.v:51179.18-51179.111"
+ wire $and$libresoc.v:51179$3338_Y
+ attribute \src "libresoc.v:51184.18-51184.101"
+ wire $and$libresoc.v:51184$3343_Y
+ attribute \src "libresoc.v:51186.18-51186.111"
+ wire $and$libresoc.v:51186$3345_Y
+ attribute \src "libresoc.v:51126.18-51126.103"
+ wire $eq$libresoc.v:51126$3285_Y
+ attribute \src "libresoc.v:51127.19-51127.104"
+ wire $eq$libresoc.v:51127$3286_Y
+ attribute \src "libresoc.v:51132.19-51132.104"
+ wire $eq$libresoc.v:51132$3291_Y
+ attribute \src "libresoc.v:51133.19-51133.104"
+ wire $eq$libresoc.v:51133$3292_Y
+ attribute \src "libresoc.v:51134.19-51134.104"
+ wire $eq$libresoc.v:51134$3293_Y
+ attribute \src "libresoc.v:51137.19-51137.104"
+ wire $eq$libresoc.v:51137$3296_Y
+ attribute \src "libresoc.v:51141.18-51141.103"
+ wire $eq$libresoc.v:51141$3300_Y
+ attribute \src "libresoc.v:51142.18-51142.103"
+ wire $eq$libresoc.v:51142$3301_Y
+ attribute \src "libresoc.v:51143.18-51143.103"
+ wire $eq$libresoc.v:51143$3302_Y
+ attribute \src "libresoc.v:51149.18-51149.103"
+ wire $eq$libresoc.v:51149$3308_Y
+ attribute \src "libresoc.v:51150.18-51150.103"
+ wire $eq$libresoc.v:51150$3309_Y
+ attribute \src "libresoc.v:51151.18-51151.103"
+ wire $eq$libresoc.v:51151$3310_Y
+ attribute \src "libresoc.v:51157.18-51157.103"
+ wire $eq$libresoc.v:51157$3316_Y
+ attribute \src "libresoc.v:51158.18-51158.103"
+ wire $eq$libresoc.v:51158$3317_Y
+ attribute \src "libresoc.v:51159.18-51159.103"
+ wire $eq$libresoc.v:51159$3318_Y
+ attribute \src "libresoc.v:51164.18-51164.103"
+ wire $eq$libresoc.v:51164$3323_Y
+ attribute \src "libresoc.v:51165.18-51165.103"
+ wire $eq$libresoc.v:51165$3324_Y
+ attribute \src "libresoc.v:51167.18-51167.103"
+ wire $eq$libresoc.v:51167$3326_Y
+ attribute \src "libresoc.v:51172.18-51172.103"
+ wire $eq$libresoc.v:51172$3331_Y
+ attribute \src "libresoc.v:51173.18-51173.103"
+ wire $eq$libresoc.v:51173$3332_Y
+ attribute \src "libresoc.v:51174.18-51174.103"
+ wire $eq$libresoc.v:51174$3333_Y
+ attribute \src "libresoc.v:51180.18-51180.103"
+ wire $eq$libresoc.v:51180$3339_Y
+ attribute \src "libresoc.v:51181.18-51181.103"
+ wire $eq$libresoc.v:51181$3340_Y
+ attribute \src "libresoc.v:51182.18-51182.103"
+ wire $eq$libresoc.v:51182$3341_Y
+ attribute \src "libresoc.v:51187.18-51187.103"
+ wire $eq$libresoc.v:51187$3346_Y
+ attribute \src "libresoc.v:51125.17-51125.103"
+ wire $not$libresoc.v:51125$3284_Y
+ attribute \src "libresoc.v:51128.19-51128.99"
+ wire $not$libresoc.v:51128$3287_Y
+ attribute \src "libresoc.v:51130.19-51130.105"
+ wire $not$libresoc.v:51130$3289_Y
+ attribute \src "libresoc.v:51139.19-51139.95"
+ wire $not$libresoc.v:51139$3298_Y
+ attribute \src "libresoc.v:51145.18-51145.98"
+ wire $not$libresoc.v:51145$3304_Y
+ attribute \src "libresoc.v:51147.18-51147.104"
+ wire $not$libresoc.v:51147$3306_Y
+ attribute \src "libresoc.v:51152.18-51152.98"
+ wire $not$libresoc.v:51152$3311_Y
+ attribute \src "libresoc.v:51154.18-51154.104"
+ wire $not$libresoc.v:51154$3313_Y
+ attribute \src "libresoc.v:51160.18-51160.98"
+ wire $not$libresoc.v:51160$3319_Y
+ attribute \src "libresoc.v:51162.18-51162.104"
+ wire $not$libresoc.v:51162$3321_Y
+ attribute \src "libresoc.v:51166.17-51166.97"
+ wire $not$libresoc.v:51166$3325_Y
+ attribute \src "libresoc.v:51168.18-51168.98"
+ wire $not$libresoc.v:51168$3327_Y
+ attribute \src "libresoc.v:51170.18-51170.104"
+ wire $not$libresoc.v:51170$3329_Y
+ attribute \src "libresoc.v:51175.18-51175.98"
+ wire $not$libresoc.v:51175$3334_Y
+ attribute \src "libresoc.v:51178.18-51178.104"
+ wire $not$libresoc.v:51178$3337_Y
+ attribute \src "libresoc.v:51183.18-51183.98"
+ wire $not$libresoc.v:51183$3342_Y
+ attribute \src "libresoc.v:51185.18-51185.104"
+ wire $not$libresoc.v:51185$3344_Y
+ attribute \src "libresoc.v:51144.17-51144.126"
+ wire width 64 $pos$libresoc.v:51144$3303_Y
+ attribute \src "libresoc.v:51155.17-51155.245"
+ wire width 64 $pos$libresoc.v:51155$3314_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 30 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 input 13 \core_dbg_core_dbg_dststep
wire width 7 \gspr_index$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100"
wire \icache_rst_o
- attribute \src "libresoc.v:51052.7-51052.15"
+ attribute \src "libresoc.v:50877.7-50877.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146"
wire width 32 \log_dmi_addr
wire width 64 \log_dmi_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120"
wire width 32 \log_write_addr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135"
wire width 64 \stat_reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123"
wire \terminated_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240"
- cell $add $add$libresoc.v:51310$3310
+ cell $add $add$libresoc.v:51135$3294
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \log_dmi_addr [1:0]
connect \B 1'1
- connect \Y $add$libresoc.v:51310$3310_Y
+ connect \Y $add$libresoc.v:51135$3294_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51304$3304
+ cell $and $and$libresoc.v:51129$3288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$103
- connect \Y $and$libresoc.v:51304$3304_Y
+ connect \Y $and$libresoc.v:51129$3288_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51306$3306
+ cell $and $and$libresoc.v:51131$3290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$107
- connect \Y $and$libresoc.v:51306$3306_Y
+ connect \Y $and$libresoc.v:51131$3290_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51311$3311
+ cell $and $and$libresoc.v:51136$3295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$9
- connect \Y $and$libresoc.v:51311$3311_Y
+ connect \Y $and$libresoc.v:51136$3295_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
- cell $and $and$libresoc.v:51313$3313
+ cell $and $and$libresoc.v:51138$3297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$120
- connect \Y $and$libresoc.v:51313$3313_Y
+ connect \Y $and$libresoc.v:51138$3297_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
- cell $and $and$libresoc.v:51315$3315
+ cell $and $and$libresoc.v:51140$3299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \stopping
connect \B \$124
- connect \Y $and$libresoc.v:51315$3315_Y
+ connect \Y $and$libresoc.v:51140$3299_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51321$3321
+ cell $and $and$libresoc.v:51146$3305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$19
- connect \Y $and$libresoc.v:51321$3321_Y
+ connect \Y $and$libresoc.v:51146$3305_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51323$3323
+ cell $and $and$libresoc.v:51148$3307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$23
- connect \Y $and$libresoc.v:51323$3323_Y
+ connect \Y $and$libresoc.v:51148$3307_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51328$3328
+ cell $and $and$libresoc.v:51153$3312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$33
- connect \Y $and$libresoc.v:51328$3328_Y
+ connect \Y $and$libresoc.v:51153$3312_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51331$3331
+ cell $and $and$libresoc.v:51156$3315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$37
- connect \Y $and$libresoc.v:51331$3331_Y
+ connect \Y $and$libresoc.v:51156$3315_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51336$3336
+ cell $and $and$libresoc.v:51161$3320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$47
- connect \Y $and$libresoc.v:51336$3336_Y
+ connect \Y $and$libresoc.v:51161$3320_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51338$3338
+ cell $and $and$libresoc.v:51163$3322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$51
- connect \Y $and$libresoc.v:51338$3338_Y
+ connect \Y $and$libresoc.v:51163$3322_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51344$3344
+ cell $and $and$libresoc.v:51169$3328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$61
- connect \Y $and$libresoc.v:51344$3344_Y
+ connect \Y $and$libresoc.v:51169$3328_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51346$3346
+ cell $and $and$libresoc.v:51171$3330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$65
- connect \Y $and$libresoc.v:51346$3346_Y
+ connect \Y $and$libresoc.v:51171$3330_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51351$3351
+ cell $and $and$libresoc.v:51176$3335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$75
- connect \Y $and$libresoc.v:51351$3351_Y
+ connect \Y $and$libresoc.v:51176$3335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51352$3352
+ cell $and $and$libresoc.v:51177$3336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$5
- connect \Y $and$libresoc.v:51352$3352_Y
+ connect \Y $and$libresoc.v:51177$3336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51354$3354
+ cell $and $and$libresoc.v:51179$3338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$79
- connect \Y $and$libresoc.v:51354$3354_Y
+ connect \Y $and$libresoc.v:51179$3338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $and $and$libresoc.v:51359$3359
+ cell $and $and$libresoc.v:51184$3343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$89
- connect \Y $and$libresoc.v:51359$3359_Y
+ connect \Y $and$libresoc.v:51184$3343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $and $and$libresoc.v:51361$3361
+ cell $and $and$libresoc.v:51186$3345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$93
- connect \Y $and$libresoc.v:51361$3361_Y
+ connect \Y $and$libresoc.v:51186$3345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51301$3301
+ cell $eq $eq$libresoc.v:51126$3285
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51301$3301_Y
+ connect \Y $eq$libresoc.v:51126$3285_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51302$3302
+ cell $eq $eq$libresoc.v:51127$3286
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51302$3302_Y
+ connect \Y $eq$libresoc.v:51127$3286_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51307$3307
+ cell $eq $eq$libresoc.v:51132$3291
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51307$3307_Y
+ connect \Y $eq$libresoc.v:51132$3291_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51308$3308
+ cell $eq $eq$libresoc.v:51133$3292
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51308$3308_Y
+ connect \Y $eq$libresoc.v:51133$3292_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51309$3309
+ cell $eq $eq$libresoc.v:51134$3293
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51309$3309_Y
+ connect \Y $eq$libresoc.v:51134$3293_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
- cell $eq $eq$libresoc.v:51312$3312
+ cell $eq $eq$libresoc.v:51137$3296
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'111
- connect \Y $eq$libresoc.v:51312$3312_Y
+ connect \Y $eq$libresoc.v:51137$3296_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51316$3316
+ cell $eq $eq$libresoc.v:51141$3300
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51316$3316_Y
+ connect \Y $eq$libresoc.v:51141$3300_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51317$3317
+ cell $eq $eq$libresoc.v:51142$3301
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51317$3317_Y
+ connect \Y $eq$libresoc.v:51142$3301_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51318$3318
+ cell $eq $eq$libresoc.v:51143$3302
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51318$3318_Y
+ connect \Y $eq$libresoc.v:51143$3302_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51324$3324
+ cell $eq $eq$libresoc.v:51149$3308
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51324$3324_Y
+ connect \Y $eq$libresoc.v:51149$3308_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51325$3325
+ cell $eq $eq$libresoc.v:51150$3309
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51325$3325_Y
+ connect \Y $eq$libresoc.v:51150$3309_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51326$3326
+ cell $eq $eq$libresoc.v:51151$3310
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51326$3326_Y
+ connect \Y $eq$libresoc.v:51151$3310_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51332$3332
+ cell $eq $eq$libresoc.v:51157$3316
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51332$3332_Y
+ connect \Y $eq$libresoc.v:51157$3316_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51333$3333
+ cell $eq $eq$libresoc.v:51158$3317
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51333$3333_Y
+ connect \Y $eq$libresoc.v:51158$3317_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51334$3334
+ cell $eq $eq$libresoc.v:51159$3318
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51334$3334_Y
+ connect \Y $eq$libresoc.v:51159$3318_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51339$3339
+ cell $eq $eq$libresoc.v:51164$3323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51339$3339_Y
+ connect \Y $eq$libresoc.v:51164$3323_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51340$3340
+ cell $eq $eq$libresoc.v:51165$3324
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51340$3340_Y
+ connect \Y $eq$libresoc.v:51165$3324_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51342$3342
+ cell $eq $eq$libresoc.v:51167$3326
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51342$3342_Y
+ connect \Y $eq$libresoc.v:51167$3326_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51347$3347
+ cell $eq $eq$libresoc.v:51172$3331
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51347$3347_Y
+ connect \Y $eq$libresoc.v:51172$3331_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51348$3348
+ cell $eq $eq$libresoc.v:51173$3332
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51348$3348_Y
+ connect \Y $eq$libresoc.v:51173$3332_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51349$3349
+ cell $eq $eq$libresoc.v:51174$3333
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51349$3349_Y
+ connect \Y $eq$libresoc.v:51174$3333_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51355$3355
+ cell $eq $eq$libresoc.v:51180$3339
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51355$3355_Y
+ connect \Y $eq$libresoc.v:51180$3339_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
- cell $eq $eq$libresoc.v:51356$3356
+ cell $eq $eq$libresoc.v:51181$3340
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51356$3356_Y
+ connect \Y $eq$libresoc.v:51181$3340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
- cell $eq $eq$libresoc.v:51357$3357
+ cell $eq $eq$libresoc.v:51182$3341
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51357$3357_Y
+ connect \Y $eq$libresoc.v:51182$3341_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
- cell $eq $eq$libresoc.v:51362$3362
+ cell $eq $eq$libresoc.v:51187$3346
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51362$3362_Y
+ connect \Y $eq$libresoc.v:51187$3346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51300$3300
+ cell $not $not$libresoc.v:51125$3284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51300$3300_Y
+ connect \Y $not$libresoc.v:51125$3284_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51303$3303
+ cell $not $not$libresoc.v:51128$3287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51303$3303_Y
+ connect \Y $not$libresoc.v:51128$3287_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51305$3305
+ cell $not $not$libresoc.v:51130$3289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51305$3305_Y
+ connect \Y $not$libresoc.v:51130$3289_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
- cell $not $not$libresoc.v:51314$3314
+ cell $not $not$libresoc.v:51139$3298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \do_step
- connect \Y $not$libresoc.v:51314$3314_Y
+ connect \Y $not$libresoc.v:51139$3298_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51320$3320
+ cell $not $not$libresoc.v:51145$3304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51320$3320_Y
+ connect \Y $not$libresoc.v:51145$3304_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51322$3322
+ cell $not $not$libresoc.v:51147$3306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51322$3322_Y
+ connect \Y $not$libresoc.v:51147$3306_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51327$3327
+ cell $not $not$libresoc.v:51152$3311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51327$3327_Y
+ connect \Y $not$libresoc.v:51152$3311_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51329$3329
+ cell $not $not$libresoc.v:51154$3313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51329$3329_Y
+ connect \Y $not$libresoc.v:51154$3313_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51335$3335
+ cell $not $not$libresoc.v:51160$3319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51335$3335_Y
+ connect \Y $not$libresoc.v:51160$3319_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51337$3337
+ cell $not $not$libresoc.v:51162$3321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51337$3337_Y
+ connect \Y $not$libresoc.v:51162$3321_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51341$3341
+ cell $not $not$libresoc.v:51166$3325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51341$3341_Y
+ connect \Y $not$libresoc.v:51166$3325_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51343$3343
+ cell $not $not$libresoc.v:51168$3327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51343$3343_Y
+ connect \Y $not$libresoc.v:51168$3327_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51345$3345
+ cell $not $not$libresoc.v:51170$3329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51345$3345_Y
+ connect \Y $not$libresoc.v:51170$3329_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51350$3350
+ cell $not $not$libresoc.v:51175$3334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51350$3350_Y
+ connect \Y $not$libresoc.v:51175$3334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51353$3353
+ cell $not $not$libresoc.v:51178$3337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51353$3353_Y
+ connect \Y $not$libresoc.v:51178$3337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
- cell $not $not$libresoc.v:51358$3358
+ cell $not $not$libresoc.v:51183$3342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51358$3358_Y
+ connect \Y $not$libresoc.v:51183$3342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $not $not$libresoc.v:51360$3360
+ cell $not $not$libresoc.v:51185$3344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51360$3360_Y
+ connect \Y $not$libresoc.v:51185$3344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
- cell $pos $pos$libresoc.v:51319$3319
+ cell $pos $pos$libresoc.v:51144$3303
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping }
- connect \Y $pos$libresoc.v:51319$3319_Y
+ connect \Y $pos$libresoc.v:51144$3303_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:51330$3330
+ cell $pos $pos$libresoc.v:51155$3314
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep }
- connect \Y $pos$libresoc.v:51330$3330_Y
+ connect \Y $pos$libresoc.v:51155$3314_Y
end
- attribute \src "libresoc.v:51052.7-51052.20"
- process $proc$libresoc.v:51052$3446
+ attribute \src "libresoc.v:50877.7-50877.20"
+ process $proc$libresoc.v:50877$3430
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:51239.7-51239.31"
- process $proc$libresoc.v:51239$3447
+ attribute \src "libresoc.v:51064.7-51064.31"
+ process $proc$libresoc.v:51064$3431
assign { } { }
assign $1\dmi_read_log_data[0:0] 1'0
sync always
sync init
update \dmi_read_log_data $1\dmi_read_log_data[0:0]
end
- attribute \src "libresoc.v:51243.7-51243.33"
- process $proc$libresoc.v:51243$3448
+ attribute \src "libresoc.v:51068.7-51068.33"
+ process $proc$libresoc.v:51068$3432
assign { } { }
assign $1\dmi_read_log_data_1[0:0] 1'0
sync always
sync init
update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0]
end
- attribute \src "libresoc.v:51249.7-51249.25"
- process $proc$libresoc.v:51249$3449
+ attribute \src "libresoc.v:51074.7-51074.25"
+ process $proc$libresoc.v:51074$3433
assign { } { }
assign $1\dmi_req_i_1[0:0] 1'0
sync always
sync init
update \dmi_req_i_1 $1\dmi_req_i_1[0:0]
end
- attribute \src "libresoc.v:51255.7-51255.27"
- process $proc$libresoc.v:51255$3450
+ attribute \src "libresoc.v:51080.7-51080.27"
+ process $proc$libresoc.v:51080$3434
assign { } { }
assign $1\do_dmi_log_rd[0:0] 1'0
sync always
sync init
update \do_dmi_log_rd $1\do_dmi_log_rd[0:0]
end
- attribute \src "libresoc.v:51259.7-51259.24"
- process $proc$libresoc.v:51259$3451
+ attribute \src "libresoc.v:51084.7-51084.24"
+ process $proc$libresoc.v:51084$3435
assign { } { }
assign $1\do_icreset[0:0] 1'0
sync always
sync init
update \do_icreset $1\do_icreset[0:0]
end
- attribute \src "libresoc.v:51263.7-51263.22"
- process $proc$libresoc.v:51263$3452
+ attribute \src "libresoc.v:51088.7-51088.22"
+ process $proc$libresoc.v:51088$3436
assign { } { }
assign $1\do_reset[0:0] 1'0
sync always
sync init
update \do_reset $1\do_reset[0:0]
end
- attribute \src "libresoc.v:51267.7-51267.21"
- process $proc$libresoc.v:51267$3453
+ attribute \src "libresoc.v:51092.7-51092.21"
+ process $proc$libresoc.v:51092$3437
assign { } { }
assign $1\do_step[0:0] 1'0
sync always
sync init
update \do_step $1\do_step[0:0]
end
- attribute \src "libresoc.v:51271.13-51271.31"
- process $proc$libresoc.v:51271$3454
+ attribute \src "libresoc.v:51096.13-51096.31"
+ process $proc$libresoc.v:51096$3438
assign { } { }
assign $1\gspr_index[6:0] 7'0000000
sync always
sync init
update \gspr_index $1\gspr_index[6:0]
end
- attribute \src "libresoc.v:51277.14-51277.34"
- process $proc$libresoc.v:51277$3455
+ attribute \src "libresoc.v:51102.14-51102.34"
+ process $proc$libresoc.v:51102$3439
assign { } { }
assign $1\log_dmi_addr[31:0] 0
sync always
sync init
update \log_dmi_addr $1\log_dmi_addr[31:0]
end
- attribute \src "libresoc.v:51289.7-51289.22"
- process $proc$libresoc.v:51289$3456
+ attribute \src "libresoc.v:51114.7-51114.22"
+ process $proc$libresoc.v:51114$3440
assign { } { }
assign $1\stopping[0:0] 1'0
sync always
sync init
update \stopping $1\stopping[0:0]
end
- attribute \src "libresoc.v:51295.7-51295.24"
- process $proc$libresoc.v:51295$3457
+ attribute \src "libresoc.v:51120.7-51120.24"
+ process $proc$libresoc.v:51120$3441
assign { } { }
assign $1\terminated[0:0] 1'0
sync always
sync init
update \terminated $1\terminated[0:0]
end
- attribute \src "libresoc.v:51363.3-51364.51"
- process $proc$libresoc.v:51363$3363
+ attribute \src "libresoc.v:51188.3-51189.51"
+ process $proc$libresoc.v:51188$3347
assign { } { }
assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next
sync posedge \clk
update \dmi_read_log_data $0\dmi_read_log_data[0:0]
end
- attribute \src "libresoc.v:51365.3-51366.55"
- process $proc$libresoc.v:51365$3364
+ attribute \src "libresoc.v:51190.3-51191.55"
+ process $proc$libresoc.v:51190$3348
assign { } { }
assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next
sync posedge \clk
update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0]
end
- attribute \src "libresoc.v:51367.3-51368.41"
- process $proc$libresoc.v:51367$3365
+ attribute \src "libresoc.v:51192.3-51193.41"
+ process $proc$libresoc.v:51192$3349
assign { } { }
assign $0\log_dmi_addr[31:0] \log_dmi_addr$next
sync posedge \clk
update \log_dmi_addr $0\log_dmi_addr[31:0]
end
- attribute \src "libresoc.v:51369.3-51370.37"
- process $proc$libresoc.v:51369$3366
+ attribute \src "libresoc.v:51194.3-51195.37"
+ process $proc$libresoc.v:51194$3350
assign { } { }
assign $0\gspr_index[6:0] \gspr_index$next
sync posedge \clk
update \gspr_index $0\gspr_index[6:0]
end
- attribute \src "libresoc.v:51371.3-51372.33"
- process $proc$libresoc.v:51371$3367
+ attribute \src "libresoc.v:51196.3-51197.33"
+ process $proc$libresoc.v:51196$3351
assign { } { }
assign $0\stopping[0:0] \stopping$next
sync posedge \clk
update \stopping $0\stopping[0:0]
end
- attribute \src "libresoc.v:51373.3-51374.37"
- process $proc$libresoc.v:51373$3368
+ attribute \src "libresoc.v:51198.3-51199.37"
+ process $proc$libresoc.v:51198$3352
assign { } { }
assign $0\terminated[0:0] \terminated$next
sync posedge \clk
update \terminated $0\terminated[0:0]
end
- attribute \src "libresoc.v:51375.3-51376.39"
- process $proc$libresoc.v:51375$3369
+ attribute \src "libresoc.v:51200.3-51201.39"
+ process $proc$libresoc.v:51200$3353
assign { } { }
assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next
sync posedge \clk
update \dmi_req_i_1 $0\dmi_req_i_1[0:0]
end
- attribute \src "libresoc.v:51377.3-51378.43"
- process $proc$libresoc.v:51377$3370
+ attribute \src "libresoc.v:51202.3-51203.43"
+ process $proc$libresoc.v:51202$3354
assign { } { }
assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next
sync posedge \clk
update \do_dmi_log_rd $0\do_dmi_log_rd[0:0]
end
- attribute \src "libresoc.v:51379.3-51380.37"
- process $proc$libresoc.v:51379$3371
+ attribute \src "libresoc.v:51204.3-51205.37"
+ process $proc$libresoc.v:51204$3355
assign { } { }
assign $0\do_icreset[0:0] \do_icreset$next
sync posedge \clk
update \do_icreset $0\do_icreset[0:0]
end
- attribute \src "libresoc.v:51381.3-51382.33"
- process $proc$libresoc.v:51381$3372
+ attribute \src "libresoc.v:51206.3-51207.33"
+ process $proc$libresoc.v:51206$3356
assign { } { }
assign $0\do_reset[0:0] \do_reset$next
sync posedge \clk
update \do_reset $0\do_reset[0:0]
end
- attribute \src "libresoc.v:51383.3-51384.31"
- process $proc$libresoc.v:51383$3373
+ attribute \src "libresoc.v:51208.3-51209.31"
+ process $proc$libresoc.v:51208$3357
assign { } { }
assign $0\do_step[0:0] \do_step$next
sync posedge \clk
update \do_step $0\do_step[0:0]
end
- attribute \src "libresoc.v:51385.3-51402.6"
- process $proc$libresoc.v:51385$3374
+ attribute \src "libresoc.v:51210.3-51227.6"
+ process $proc$libresoc.v:51210$3358
assign { } { }
assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51386.5-51386.29"
+ attribute \src "libresoc.v:51211.5-51211.29"
switch \initial
- attribute \src "libresoc.v:51386.9-51386.17"
+ attribute \src "libresoc.v:51211.9-51211.17"
case 1'1
case
end
sync always
update \dmi_ack_o $0\dmi_ack_o[0:0]
end
- attribute \src "libresoc.v:51403.3-51412.6"
- process $proc$libresoc.v:51403$3375
+ attribute \src "libresoc.v:51228.3-51237.6"
+ process $proc$libresoc.v:51228$3359
assign { } { }
assign { } { }
assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:51404.5-51404.29"
+ attribute \src "libresoc.v:51229.5-51229.29"
switch \initial
- attribute \src "libresoc.v:51404.9-51404.17"
+ attribute \src "libresoc.v:51229.9-51229.17"
case 1'1
case
end
sync always
update \d_gpr_req $0\d_gpr_req[0:0]
end
- attribute \src "libresoc.v:51413.3-51421.6"
- process $proc$libresoc.v:51413$3376
+ attribute \src "libresoc.v:51238.3-51246.6"
+ process $proc$libresoc.v:51238$3360
assign { } { }
assign { } { }
- assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378
- attribute \src "libresoc.v:51414.5-51414.29"
+ assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362
+ attribute \src "libresoc.v:51239.5-51239.29"
switch \initial
- attribute \src "libresoc.v:51414.9-51414.17"
+ attribute \src "libresoc.v:51239.9-51239.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_req_i_1$next[0:0]$3378 1'0
+ assign $1\dmi_req_i_1$next[0:0]$3362 1'0
case
- assign $1\dmi_req_i_1$next[0:0]$3378 \dmi_req_i
+ assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i
end
sync always
- update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377
+ update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361
end
- attribute \src "libresoc.v:51422.3-51471.6"
- process $proc$libresoc.v:51422$3379
+ attribute \src "libresoc.v:51247.3-51296.6"
+ process $proc$libresoc.v:51247$3363
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388
- attribute \src "libresoc.v:51423.5-51423.29"
+ assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372
+ attribute \src "libresoc.v:51248.5-51248.29"
switch \initial
- attribute \src "libresoc.v:51423.9-51423.17"
+ attribute \src "libresoc.v:51248.9-51248.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\terminated$next[0:0]$3381 $2\terminated$next[0:0]$3382
+ assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\terminated$next[0:0]$3382 $3\terminated$next[0:0]$3383
+ assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$73 \$71 \$69 }
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $3\terminated$next[0:0]$3383 $6\terminated$next[0:0]$3386
+ assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
switch \dmi_din [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\terminated$next[0:0]$3384 1'0
+ assign $4\terminated$next[0:0]$3368 1'0
case
- assign $4\terminated$next[0:0]$3384 \terminated
+ assign $4\terminated$next[0:0]$3368 \terminated
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\terminated$next[0:0]$3385 1'0
+ assign $5\terminated$next[0:0]$3369 1'0
case
- assign $5\terminated$next[0:0]$3385 $4\terminated$next[0:0]$3384
+ assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221"
switch \dmi_din [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\terminated$next[0:0]$3386 1'0
+ assign $6\terminated$next[0:0]$3370 1'0
case
- assign $6\terminated$next[0:0]$3386 $5\terminated$next[0:0]$3385
+ assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369
end
case
- assign $3\terminated$next[0:0]$3383 \terminated
+ assign $3\terminated$next[0:0]$3367 \terminated
end
case
- assign $2\terminated$next[0:0]$3382 \terminated
+ assign $2\terminated$next[0:0]$3366 \terminated
end
case
- assign $1\terminated$next[0:0]$3381 \terminated
+ assign $1\terminated$next[0:0]$3365 \terminated
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250"
switch \terminate_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\terminated$next[0:0]$3387 1'1
+ assign $7\terminated$next[0:0]$3371 1'1
case
- assign $7\terminated$next[0:0]$3387 $1\terminated$next[0:0]$3381
+ assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\terminated$next[0:0]$3388 1'0
+ assign $8\terminated$next[0:0]$3372 1'0
case
- assign $8\terminated$next[0:0]$3388 $7\terminated$next[0:0]$3387
+ assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371
end
sync always
- update \terminated$next $0\terminated$next[0:0]$3380
+ update \terminated$next $0\terminated$next[0:0]$3364
end
- attribute \src "libresoc.v:51472.3-51515.6"
- process $proc$libresoc.v:51472$3389
+ attribute \src "libresoc.v:51297.3-51340.6"
+ process $proc$libresoc.v:51297$3373
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397
- attribute \src "libresoc.v:51473.5-51473.29"
+ assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381
+ attribute \src "libresoc.v:51298.5-51298.29"
switch \initial
- attribute \src "libresoc.v:51473.9-51473.17"
+ attribute \src "libresoc.v:51298.9-51298.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\stopping$next[0:0]$3391 $2\stopping$next[0:0]$3392
+ assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\stopping$next[0:0]$3392 $3\stopping$next[0:0]$3393
+ assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$87 \$85 \$83 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
assign { } { }
- assign $3\stopping$next[0:0]$3393 $5\stopping$next[0:0]$3395
+ assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214"
switch \dmi_din [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\stopping$next[0:0]$3394 1'1
+ assign $4\stopping$next[0:0]$3378 1'1
case
- assign $4\stopping$next[0:0]$3394 \stopping
+ assign $4\stopping$next[0:0]$3378 \stopping
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221"
switch \dmi_din [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\stopping$next[0:0]$3395 1'0
+ assign $5\stopping$next[0:0]$3379 1'0
case
- assign $5\stopping$next[0:0]$3395 $4\stopping$next[0:0]$3394
+ assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378
end
case
- assign $3\stopping$next[0:0]$3393 \stopping
+ assign $3\stopping$next[0:0]$3377 \stopping
end
case
- assign $2\stopping$next[0:0]$3392 \stopping
+ assign $2\stopping$next[0:0]$3376 \stopping
end
case
- assign $1\stopping$next[0:0]$3391 \stopping
+ assign $1\stopping$next[0:0]$3375 \stopping
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250"
switch \terminate_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\stopping$next[0:0]$3396 1'1
+ assign $6\stopping$next[0:0]$3380 1'1
case
- assign $6\stopping$next[0:0]$3396 $1\stopping$next[0:0]$3391
+ assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\stopping$next[0:0]$3397 1'0
+ assign $7\stopping$next[0:0]$3381 1'0
case
- assign $7\stopping$next[0:0]$3397 $6\stopping$next[0:0]$3396
+ assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380
end
sync always
- update \stopping$next $0\stopping$next[0:0]$3390
+ update \stopping$next $0\stopping$next[0:0]$3374
end
- attribute \src "libresoc.v:51516.3-51543.6"
- process $proc$libresoc.v:51516$3398
+ attribute \src "libresoc.v:51341.3-51368.6"
+ process $proc$libresoc.v:51341$3382
assign { } { }
assign { } { }
assign { } { }
- assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403
- attribute \src "libresoc.v:51517.5-51517.29"
+ assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387
+ attribute \src "libresoc.v:51342.5-51342.29"
switch \initial
- attribute \src "libresoc.v:51517.9-51517.17"
+ attribute \src "libresoc.v:51342.9-51342.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\gspr_index$next[6:0]$3400 $2\gspr_index$next[6:0]$3401
+ assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\gspr_index$next[6:0]$3401 $3\gspr_index$next[6:0]$3402
+ assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$101 \$99 \$97 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\gspr_index$next[6:0]$3402 \gspr_index
+ assign $3\gspr_index$next[6:0]$3386 \gspr_index
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $3\gspr_index$next[6:0]$3402 \dmi_din [6:0]
+ assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0]
case
- assign $3\gspr_index$next[6:0]$3402 \gspr_index
+ assign $3\gspr_index$next[6:0]$3386 \gspr_index
end
case
- assign $2\gspr_index$next[6:0]$3401 \gspr_index
+ assign $2\gspr_index$next[6:0]$3385 \gspr_index
end
case
- assign $1\gspr_index$next[6:0]$3400 \gspr_index
+ assign $1\gspr_index$next[6:0]$3384 \gspr_index
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\gspr_index$next[6:0]$3403 7'0000000
+ assign $4\gspr_index$next[6:0]$3387 7'0000000
case
- assign $4\gspr_index$next[6:0]$3403 $1\gspr_index$next[6:0]$3400
+ assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384
end
sync always
- update \gspr_index$next $0\gspr_index$next[6:0]$3399
+ update \gspr_index$next $0\gspr_index$next[6:0]$3383
end
- attribute \src "libresoc.v:51544.3-51577.6"
- process $proc$libresoc.v:51544$3404
+ attribute \src "libresoc.v:51369.3-51402.6"
+ process $proc$libresoc.v:51369$3388
assign { } { }
assign { } { }
assign { } { }
- assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409
- attribute \src "libresoc.v:51545.5-51545.29"
+ assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393
+ attribute \src "libresoc.v:51370.5-51370.29"
switch \initial
- attribute \src "libresoc.v:51545.9-51545.17"
+ attribute \src "libresoc.v:51370.9-51370.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\log_dmi_addr$next[31:0]$3406 $2\log_dmi_addr$next[31:0]$3407
+ assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\log_dmi_addr$next[31:0]$3407 $3\log_dmi_addr$next[31:0]$3408
+ assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$115 \$113 \$111 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\log_dmi_addr$next[31:0]$3408 \dmi_din [31:0]
+ assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0]
case
- assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
end
case
- assign $2\log_dmi_addr$next[31:0]$3407 \log_dmi_addr
+ assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
- assign $1\log_dmi_addr$next[31:0]$3406 [31:2] \log_dmi_addr [31:2]
- assign $1\log_dmi_addr$next[31:0]$3406 [1:0] \$117 [1:0]
+ assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2]
+ assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0]
case
- assign $1\log_dmi_addr$next[31:0]$3406 \log_dmi_addr
+ assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\log_dmi_addr$next[31:0]$3409 0
+ assign $4\log_dmi_addr$next[31:0]$3393 0
case
- assign $4\log_dmi_addr$next[31:0]$3409 $1\log_dmi_addr$next[31:0]$3406
+ assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390
end
sync always
- update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405
+ update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389
end
- attribute \src "libresoc.v:51578.3-51586.6"
- process $proc$libresoc.v:51578$3410
+ attribute \src "libresoc.v:51403.3-51411.6"
+ process $proc$libresoc.v:51403$3394
assign { } { }
assign { } { }
- assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412
- attribute \src "libresoc.v:51579.5-51579.29"
+ assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396
+ attribute \src "libresoc.v:51404.5-51404.29"
switch \initial
- attribute \src "libresoc.v:51579.9-51579.17"
+ attribute \src "libresoc.v:51404.9-51404.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_read_log_data_1$next[0:0]$3412 1'0
+ assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0
case
- assign $1\dmi_read_log_data_1$next[0:0]$3412 \dmi_read_log_data
+ assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data
end
sync always
- update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411
+ update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395
end
- attribute \src "libresoc.v:51587.3-51595.6"
- process $proc$libresoc.v:51587$3413
+ attribute \src "libresoc.v:51412.3-51420.6"
+ process $proc$libresoc.v:51412$3397
assign { } { }
assign { } { }
- assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415
- attribute \src "libresoc.v:51588.5-51588.29"
+ assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399
+ attribute \src "libresoc.v:51413.5-51413.29"
switch \initial
- attribute \src "libresoc.v:51588.9-51588.17"
+ attribute \src "libresoc.v:51413.9-51413.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_read_log_data$next[0:0]$3415 1'0
+ assign $1\dmi_read_log_data$next[0:0]$3399 1'0
case
- assign $1\dmi_read_log_data$next[0:0]$3415 \$122
+ assign $1\dmi_read_log_data$next[0:0]$3399 \$122
end
sync always
- update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414
+ update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398
end
- attribute \src "libresoc.v:51596.3-51608.6"
- process $proc$libresoc.v:51596$3416
+ attribute \src "libresoc.v:51421.3-51433.6"
+ process $proc$libresoc.v:51421$3400
assign { } { }
assign { } { }
assign $0\d_cr_req[0:0] $1\d_cr_req[0:0]
- attribute \src "libresoc.v:51597.5-51597.29"
+ attribute \src "libresoc.v:51422.5-51422.29"
switch \initial
- attribute \src "libresoc.v:51597.9-51597.17"
+ attribute \src "libresoc.v:51422.9-51422.17"
case 1'1
case
end
sync always
update \d_cr_req $0\d_cr_req[0:0]
end
- attribute \src "libresoc.v:51609.3-51624.6"
- process $proc$libresoc.v:51609$3417
+ attribute \src "libresoc.v:51434.3-51449.6"
+ process $proc$libresoc.v:51434$3401
assign { } { }
assign { } { }
assign $0\d_xer_req[0:0] $1\d_xer_req[0:0]
- attribute \src "libresoc.v:51610.5-51610.29"
+ attribute \src "libresoc.v:51435.5-51435.29"
switch \initial
- attribute \src "libresoc.v:51610.9-51610.17"
+ attribute \src "libresoc.v:51435.9-51435.17"
case 1'1
case
end
sync always
update \d_xer_req $0\d_xer_req[0:0]
end
- attribute \src "libresoc.v:51625.3-51658.6"
- process $proc$libresoc.v:51625$3418
+ attribute \src "libresoc.v:51450.3-51483.6"
+ process $proc$libresoc.v:51450$3402
assign { } { }
assign { } { }
assign $0\dmi_dout[63:0] $1\dmi_dout[63:0]
- attribute \src "libresoc.v:51626.5-51626.29"
+ attribute \src "libresoc.v:51451.5-51451.29"
switch \initial
- attribute \src "libresoc.v:51626.9-51626.17"
+ attribute \src "libresoc.v:51451.9-51451.17"
case 1'1
case
end
sync always
update \dmi_dout $0\dmi_dout[63:0]
end
- attribute \src "libresoc.v:51659.3-51688.6"
- process $proc$libresoc.v:51659$3419
+ attribute \src "libresoc.v:51484.3-51513.6"
+ process $proc$libresoc.v:51484$3403
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425
- attribute \src "libresoc.v:51660.5-51660.29"
+ assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409
+ attribute \src "libresoc.v:51485.5-51485.29"
switch \initial
- attribute \src "libresoc.v:51660.9-51660.17"
+ attribute \src "libresoc.v:51485.9-51485.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_step$next[0:0]$3421 $2\do_step$next[0:0]$3422
+ assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_step$next[0:0]$3422 $3\do_step$next[0:0]$3423
+ assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$17 \$15 \$13 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_step$next[0:0]$3423 $4\do_step$next[0:0]$3424
+ assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_step$next[0:0]$3424 1'1
+ assign $4\do_step$next[0:0]$3408 1'1
case
- assign $4\do_step$next[0:0]$3424 1'0
+ assign $4\do_step$next[0:0]$3408 1'0
end
case
- assign $3\do_step$next[0:0]$3423 1'0
+ assign $3\do_step$next[0:0]$3407 1'0
end
case
- assign $2\do_step$next[0:0]$3422 1'0
+ assign $2\do_step$next[0:0]$3406 1'0
end
case
- assign $1\do_step$next[0:0]$3421 1'0
+ assign $1\do_step$next[0:0]$3405 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_step$next[0:0]$3425 1'0
+ assign $5\do_step$next[0:0]$3409 1'0
case
- assign $5\do_step$next[0:0]$3425 $1\do_step$next[0:0]$3421
+ assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405
end
sync always
- update \do_step$next $0\do_step$next[0:0]$3420
+ update \do_step$next $0\do_step$next[0:0]$3404
end
- attribute \src "libresoc.v:51689.3-51718.6"
- process $proc$libresoc.v:51689$3426
+ attribute \src "libresoc.v:51514.3-51543.6"
+ process $proc$libresoc.v:51514$3410
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432
- attribute \src "libresoc.v:51690.5-51690.29"
+ assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416
+ attribute \src "libresoc.v:51515.5-51515.29"
switch \initial
- attribute \src "libresoc.v:51690.9-51690.17"
+ attribute \src "libresoc.v:51515.9-51515.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_reset$next[0:0]$3428 $2\do_reset$next[0:0]$3429
+ assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_reset$next[0:0]$3429 $3\do_reset$next[0:0]$3430
+ assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$31 \$29 \$27 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_reset$next[0:0]$3430 $4\do_reset$next[0:0]$3431
+ assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
switch \dmi_din [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_reset$next[0:0]$3431 1'1
+ assign $4\do_reset$next[0:0]$3415 1'1
case
- assign $4\do_reset$next[0:0]$3431 1'0
+ assign $4\do_reset$next[0:0]$3415 1'0
end
case
- assign $3\do_reset$next[0:0]$3430 1'0
+ assign $3\do_reset$next[0:0]$3414 1'0
end
case
- assign $2\do_reset$next[0:0]$3429 1'0
+ assign $2\do_reset$next[0:0]$3413 1'0
end
case
- assign $1\do_reset$next[0:0]$3428 1'0
+ assign $1\do_reset$next[0:0]$3412 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_reset$next[0:0]$3432 1'0
+ assign $5\do_reset$next[0:0]$3416 1'0
case
- assign $5\do_reset$next[0:0]$3432 $1\do_reset$next[0:0]$3428
+ assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412
end
sync always
- update \do_reset$next $0\do_reset$next[0:0]$3427
+ update \do_reset$next $0\do_reset$next[0:0]$3411
end
- attribute \src "libresoc.v:51719.3-51748.6"
- process $proc$libresoc.v:51719$3433
+ attribute \src "libresoc.v:51544.3-51573.6"
+ process $proc$libresoc.v:51544$3417
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_icreset$next[0:0]$3434 $5\do_icreset$next[0:0]$3439
- attribute \src "libresoc.v:51720.5-51720.29"
+ assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423
+ attribute \src "libresoc.v:51545.5-51545.29"
switch \initial
- attribute \src "libresoc.v:51720.9-51720.17"
+ attribute \src "libresoc.v:51545.9-51545.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_icreset$next[0:0]$3435 $2\do_icreset$next[0:0]$3436
+ assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_icreset$next[0:0]$3436 $3\do_icreset$next[0:0]$3437
+ assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$45 \$43 \$41 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_icreset$next[0:0]$3437 $4\do_icreset$next[0:0]$3438
+ assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219"
switch \dmi_din [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_icreset$next[0:0]$3438 1'1
+ assign $4\do_icreset$next[0:0]$3422 1'1
case
- assign $4\do_icreset$next[0:0]$3438 1'0
+ assign $4\do_icreset$next[0:0]$3422 1'0
end
case
- assign $3\do_icreset$next[0:0]$3437 1'0
+ assign $3\do_icreset$next[0:0]$3421 1'0
end
case
- assign $2\do_icreset$next[0:0]$3436 1'0
+ assign $2\do_icreset$next[0:0]$3420 1'0
end
case
- assign $1\do_icreset$next[0:0]$3435 1'0
+ assign $1\do_icreset$next[0:0]$3419 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_icreset$next[0:0]$3439 1'0
+ assign $5\do_icreset$next[0:0]$3423 1'0
case
- assign $5\do_icreset$next[0:0]$3439 $1\do_icreset$next[0:0]$3435
+ assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419
end
sync always
- update \do_icreset$next $0\do_icreset$next[0:0]$3434
+ update \do_icreset$next $0\do_icreset$next[0:0]$3418
end
- attribute \src "libresoc.v:51749.3-51782.6"
- process $proc$libresoc.v:51749$3440
+ attribute \src "libresoc.v:51574.3-51607.6"
+ process $proc$libresoc.v:51574$3424
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_dmi_log_rd$next[0:0]$3441 $4\do_dmi_log_rd$next[0:0]$3445
- attribute \src "libresoc.v:51750.5-51750.29"
+ assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429
+ attribute \src "libresoc.v:51575.5-51575.29"
switch \initial
- attribute \src "libresoc.v:51750.9-51750.17"
+ attribute \src "libresoc.v:51575.9-51575.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$3442 $2\do_dmi_log_rd$next[0:0]$3443
+ assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_dmi_log_rd$next[0:0]$3443 $3\do_dmi_log_rd$next[0:0]$3444
+ assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
switch { \$59 \$57 \$55 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\do_dmi_log_rd$next[0:0]$3444 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\do_dmi_log_rd$next[0:0]$3444 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\do_dmi_log_rd$next[0:0]$3444 1'1
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'1
case
- assign $3\do_dmi_log_rd$next[0:0]$3444 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
end
case
- assign $2\do_dmi_log_rd$next[0:0]$3443 1'0
+ assign $2\do_dmi_log_rd$next[0:0]$3427 1'0
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$3442 1'1
+ assign $1\do_dmi_log_rd$next[0:0]$3426 1'1
case
- assign $1\do_dmi_log_rd$next[0:0]$3442 1'0
+ assign $1\do_dmi_log_rd$next[0:0]$3426 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_dmi_log_rd$next[0:0]$3445 1'0
- case
- assign $4\do_dmi_log_rd$next[0:0]$3445 $1\do_dmi_log_rd$next[0:0]$3442
- end
- sync always
- update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3441
- end
- connect \$9 $not$libresoc.v:51300$3300_Y
- connect \$99 $eq$libresoc.v:51301$3301_Y
- connect \$101 $eq$libresoc.v:51302$3302_Y
- connect \$103 $not$libresoc.v:51303$3303_Y
- connect \$105 $and$libresoc.v:51304$3304_Y
- connect \$107 $not$libresoc.v:51305$3305_Y
- connect \$109 $and$libresoc.v:51306$3306_Y
- connect \$111 $eq$libresoc.v:51307$3307_Y
- connect \$113 $eq$libresoc.v:51308$3308_Y
- connect \$115 $eq$libresoc.v:51309$3309_Y
- connect \$118 $add$libresoc.v:51310$3310_Y
- connect \$11 $and$libresoc.v:51311$3311_Y
- connect \$120 $eq$libresoc.v:51312$3312_Y
- connect \$122 $and$libresoc.v:51313$3313_Y
- connect \$124 $not$libresoc.v:51314$3314_Y
- connect \$126 $and$libresoc.v:51315$3315_Y
- connect \$13 $eq$libresoc.v:51316$3316_Y
- connect \$15 $eq$libresoc.v:51317$3317_Y
- connect \$17 $eq$libresoc.v:51318$3318_Y
- connect \$1 $pos$libresoc.v:51319$3319_Y
- connect \$19 $not$libresoc.v:51320$3320_Y
- connect \$21 $and$libresoc.v:51321$3321_Y
- connect \$23 $not$libresoc.v:51322$3322_Y
- connect \$25 $and$libresoc.v:51323$3323_Y
- connect \$27 $eq$libresoc.v:51324$3324_Y
- connect \$29 $eq$libresoc.v:51325$3325_Y
- connect \$31 $eq$libresoc.v:51326$3326_Y
- connect \$33 $not$libresoc.v:51327$3327_Y
- connect \$35 $and$libresoc.v:51328$3328_Y
- connect \$37 $not$libresoc.v:51329$3329_Y
- connect \$3 $pos$libresoc.v:51330$3330_Y
- connect \$39 $and$libresoc.v:51331$3331_Y
- connect \$41 $eq$libresoc.v:51332$3332_Y
- connect \$43 $eq$libresoc.v:51333$3333_Y
- connect \$45 $eq$libresoc.v:51334$3334_Y
- connect \$47 $not$libresoc.v:51335$3335_Y
- connect \$49 $and$libresoc.v:51336$3336_Y
- connect \$51 $not$libresoc.v:51337$3337_Y
- connect \$53 $and$libresoc.v:51338$3338_Y
- connect \$55 $eq$libresoc.v:51339$3339_Y
- connect \$57 $eq$libresoc.v:51340$3340_Y
- connect \$5 $not$libresoc.v:51341$3341_Y
- connect \$59 $eq$libresoc.v:51342$3342_Y
- connect \$61 $not$libresoc.v:51343$3343_Y
- connect \$63 $and$libresoc.v:51344$3344_Y
- connect \$65 $not$libresoc.v:51345$3345_Y
- connect \$67 $and$libresoc.v:51346$3346_Y
- connect \$69 $eq$libresoc.v:51347$3347_Y
- connect \$71 $eq$libresoc.v:51348$3348_Y
- connect \$73 $eq$libresoc.v:51349$3349_Y
- connect \$75 $not$libresoc.v:51350$3350_Y
- connect \$77 $and$libresoc.v:51351$3351_Y
- connect \$7 $and$libresoc.v:51352$3352_Y
- connect \$79 $not$libresoc.v:51353$3353_Y
- connect \$81 $and$libresoc.v:51354$3354_Y
- connect \$83 $eq$libresoc.v:51355$3355_Y
- connect \$85 $eq$libresoc.v:51356$3356_Y
- connect \$87 $eq$libresoc.v:51357$3357_Y
- connect \$89 $not$libresoc.v:51358$3358_Y
- connect \$91 $and$libresoc.v:51359$3359_Y
- connect \$93 $not$libresoc.v:51360$3360_Y
- connect \$95 $and$libresoc.v:51361$3361_Y
- connect \$97 $eq$libresoc.v:51362$3362_Y
+ assign $4\do_dmi_log_rd$next[0:0]$3429 1'0
+ case
+ assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426
+ end
+ sync always
+ update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425
+ end
+ connect \$9 $not$libresoc.v:51125$3284_Y
+ connect \$99 $eq$libresoc.v:51126$3285_Y
+ connect \$101 $eq$libresoc.v:51127$3286_Y
+ connect \$103 $not$libresoc.v:51128$3287_Y
+ connect \$105 $and$libresoc.v:51129$3288_Y
+ connect \$107 $not$libresoc.v:51130$3289_Y
+ connect \$109 $and$libresoc.v:51131$3290_Y
+ connect \$111 $eq$libresoc.v:51132$3291_Y
+ connect \$113 $eq$libresoc.v:51133$3292_Y
+ connect \$115 $eq$libresoc.v:51134$3293_Y
+ connect \$118 $add$libresoc.v:51135$3294_Y
+ connect \$11 $and$libresoc.v:51136$3295_Y
+ connect \$120 $eq$libresoc.v:51137$3296_Y
+ connect \$122 $and$libresoc.v:51138$3297_Y
+ connect \$124 $not$libresoc.v:51139$3298_Y
+ connect \$126 $and$libresoc.v:51140$3299_Y
+ connect \$13 $eq$libresoc.v:51141$3300_Y
+ connect \$15 $eq$libresoc.v:51142$3301_Y
+ connect \$17 $eq$libresoc.v:51143$3302_Y
+ connect \$1 $pos$libresoc.v:51144$3303_Y
+ connect \$19 $not$libresoc.v:51145$3304_Y
+ connect \$21 $and$libresoc.v:51146$3305_Y
+ connect \$23 $not$libresoc.v:51147$3306_Y
+ connect \$25 $and$libresoc.v:51148$3307_Y
+ connect \$27 $eq$libresoc.v:51149$3308_Y
+ connect \$29 $eq$libresoc.v:51150$3309_Y
+ connect \$31 $eq$libresoc.v:51151$3310_Y
+ connect \$33 $not$libresoc.v:51152$3311_Y
+ connect \$35 $and$libresoc.v:51153$3312_Y
+ connect \$37 $not$libresoc.v:51154$3313_Y
+ connect \$3 $pos$libresoc.v:51155$3314_Y
+ connect \$39 $and$libresoc.v:51156$3315_Y
+ connect \$41 $eq$libresoc.v:51157$3316_Y
+ connect \$43 $eq$libresoc.v:51158$3317_Y
+ connect \$45 $eq$libresoc.v:51159$3318_Y
+ connect \$47 $not$libresoc.v:51160$3319_Y
+ connect \$49 $and$libresoc.v:51161$3320_Y
+ connect \$51 $not$libresoc.v:51162$3321_Y
+ connect \$53 $and$libresoc.v:51163$3322_Y
+ connect \$55 $eq$libresoc.v:51164$3323_Y
+ connect \$57 $eq$libresoc.v:51165$3324_Y
+ connect \$5 $not$libresoc.v:51166$3325_Y
+ connect \$59 $eq$libresoc.v:51167$3326_Y
+ connect \$61 $not$libresoc.v:51168$3327_Y
+ connect \$63 $and$libresoc.v:51169$3328_Y
+ connect \$65 $not$libresoc.v:51170$3329_Y
+ connect \$67 $and$libresoc.v:51171$3330_Y
+ connect \$69 $eq$libresoc.v:51172$3331_Y
+ connect \$71 $eq$libresoc.v:51173$3332_Y
+ connect \$73 $eq$libresoc.v:51174$3333_Y
+ connect \$75 $not$libresoc.v:51175$3334_Y
+ connect \$77 $and$libresoc.v:51176$3335_Y
+ connect \$7 $and$libresoc.v:51177$3336_Y
+ connect \$79 $not$libresoc.v:51178$3337_Y
+ connect \$81 $and$libresoc.v:51179$3338_Y
+ connect \$83 $eq$libresoc.v:51180$3339_Y
+ connect \$85 $eq$libresoc.v:51181$3340_Y
+ connect \$87 $eq$libresoc.v:51182$3341_Y
+ connect \$89 $not$libresoc.v:51183$3342_Y
+ connect \$91 $and$libresoc.v:51184$3343_Y
+ connect \$93 $not$libresoc.v:51185$3344_Y
+ connect \$95 $and$libresoc.v:51186$3345_Y
+ connect \$97 $eq$libresoc.v:51187$3346_Y
connect \$117 \$118
connect \log_write_addr_o 0
connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000
connect \d_gpr_addr \gspr_index
connect \stat_reg \$1
end
-attribute \src "libresoc.v:51796.1-53846.10"
+attribute \src "libresoc.v:51621.1-53671.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec"
attribute \generator "nMigen"
module \dec
- attribute \src "libresoc.v:53407.3-53440.6"
+ attribute \src "libresoc.v:53232.3-53265.6"
wire width 3 $0\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53441.3-53474.6"
+ attribute \src "libresoc.v:53266.3-53299.6"
wire width 3 $0\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53067.3-53100.6"
+ attribute \src "libresoc.v:52892.3-52925.6"
wire width 2 $0\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53169.3-53202.6"
+ attribute \src "libresoc.v:52994.3-53027.6"
wire $0\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53271.3-53304.6"
+ attribute \src "libresoc.v:53096.3-53129.6"
wire width 14 $0\ALU_function_unit[13:0]
- attribute \src "libresoc.v:53339.3-53372.6"
+ attribute \src "libresoc.v:53164.3-53197.6"
wire width 3 $0\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53373.3-53406.6"
+ attribute \src "libresoc.v:53198.3-53231.6"
wire width 4 $0\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53305.3-53338.6"
+ attribute \src "libresoc.v:53130.3-53163.6"
wire width 7 $0\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53101.3-53134.6"
+ attribute \src "libresoc.v:52926.3-52959.6"
wire $0\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53135.3-53168.6"
+ attribute \src "libresoc.v:52960.3-52993.6"
wire $0\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53203.3-53236.6"
+ attribute \src "libresoc.v:53028.3-53061.6"
wire $0\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53475.3-53508.6"
+ attribute \src "libresoc.v:53300.3-53333.6"
wire width 4 $0\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53033.3-53066.6"
+ attribute \src "libresoc.v:52858.3-52891.6"
wire width 2 $0\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53237.3-53270.6"
+ attribute \src "libresoc.v:53062.3-53095.6"
wire $0\ALU_sgn[0:0]
- attribute \src "libresoc.v:51797.7-51797.20"
+ attribute \src "libresoc.v:51622.7-51622.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:53407.3-53440.6"
+ attribute \src "libresoc.v:53232.3-53265.6"
wire width 3 $1\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53441.3-53474.6"
+ attribute \src "libresoc.v:53266.3-53299.6"
wire width 3 $1\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53067.3-53100.6"
+ attribute \src "libresoc.v:52892.3-52925.6"
wire width 2 $1\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53169.3-53202.6"
+ attribute \src "libresoc.v:52994.3-53027.6"
wire $1\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53271.3-53304.6"
+ attribute \src "libresoc.v:53096.3-53129.6"
wire width 14 $1\ALU_function_unit[13:0]
- attribute \src "libresoc.v:53339.3-53372.6"
+ attribute \src "libresoc.v:53164.3-53197.6"
wire width 3 $1\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53373.3-53406.6"
+ attribute \src "libresoc.v:53198.3-53231.6"
wire width 4 $1\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53305.3-53338.6"
+ attribute \src "libresoc.v:53130.3-53163.6"
wire width 7 $1\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53101.3-53134.6"
+ attribute \src "libresoc.v:52926.3-52959.6"
wire $1\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53135.3-53168.6"
+ attribute \src "libresoc.v:52960.3-52993.6"
wire $1\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53203.3-53236.6"
+ attribute \src "libresoc.v:53028.3-53061.6"
wire $1\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53475.3-53508.6"
+ attribute \src "libresoc.v:53300.3-53333.6"
wire width 4 $1\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53033.3-53066.6"
+ attribute \src "libresoc.v:52858.3-52891.6"
wire width 2 $1\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53237.3-53270.6"
+ attribute \src "libresoc.v:53062.3-53095.6"
wire $1\ALU_sgn[0:0]
- attribute \src "libresoc.v:52998.17-52998.211"
- wire width 32 $ternary$libresoc.v:52998$3458_Y
+ attribute \src "libresoc.v:52823.17-52823.211"
+ wire width 32 $ternary$libresoc.v:52823$3442_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:51797.7-51797.15"
+ attribute \src "libresoc.v:51622.7-51622.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:52998$3458
+ cell $mux $ternary$libresoc.v:52823$3442
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:52998$3458_Y
+ connect \Y $ternary$libresoc.v:52823$3442_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:52999.13-53015.4"
+ attribute \src "libresoc.v:52824.13-52840.4"
cell \ALU_dec19 \ALU_dec19
connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in
connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out
connect \opcode_in \ALU_dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:53016.13-53032.4"
+ attribute \src "libresoc.v:52841.13-52857.4"
cell \ALU_dec31 \ALU_dec31
connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in
connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out
connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn
connect \opcode_in \ALU_dec31_opcode_in
end
- attribute \src "libresoc.v:51797.7-51797.20"
- process $proc$libresoc.v:51797$3473
+ attribute \src "libresoc.v:51622.7-51622.20"
+ process $proc$libresoc.v:51622$3457
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:53033.3-53066.6"
- process $proc$libresoc.v:53033$3459
+ attribute \src "libresoc.v:52858.3-52891.6"
+ process $proc$libresoc.v:52858$3443
assign { } { }
assign { } { }
assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53034.5-53034.29"
+ attribute \src "libresoc.v:52859.5-52859.29"
switch \initial
- attribute \src "libresoc.v:53034.9-53034.17"
+ attribute \src "libresoc.v:52859.9-52859.17"
case 1'1
case
end
sync always
update \ALU_rc_sel $0\ALU_rc_sel[1:0]
end
- attribute \src "libresoc.v:53067.3-53100.6"
- process $proc$libresoc.v:53067$3460
+ attribute \src "libresoc.v:52892.3-52925.6"
+ process $proc$libresoc.v:52892$3444
assign { } { }
assign { } { }
assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53068.5-53068.29"
+ attribute \src "libresoc.v:52893.5-52893.29"
switch \initial
- attribute \src "libresoc.v:53068.9-53068.17"
+ attribute \src "libresoc.v:52893.9-52893.17"
case 1'1
case
end
sync always
update \ALU_cry_in $0\ALU_cry_in[1:0]
end
- attribute \src "libresoc.v:53101.3-53134.6"
- process $proc$libresoc.v:53101$3461
+ attribute \src "libresoc.v:52926.3-52959.6"
+ process $proc$libresoc.v:52926$3445
assign { } { }
assign { } { }
assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53102.5-53102.29"
+ attribute \src "libresoc.v:52927.5-52927.29"
switch \initial
- attribute \src "libresoc.v:53102.9-53102.17"
+ attribute \src "libresoc.v:52927.9-52927.17"
case 1'1
case
end
sync always
update \ALU_inv_a $0\ALU_inv_a[0:0]
end
- attribute \src "libresoc.v:53135.3-53168.6"
- process $proc$libresoc.v:53135$3462
+ attribute \src "libresoc.v:52960.3-52993.6"
+ process $proc$libresoc.v:52960$3446
assign { } { }
assign { } { }
assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53136.5-53136.29"
+ attribute \src "libresoc.v:52961.5-52961.29"
switch \initial
- attribute \src "libresoc.v:53136.9-53136.17"
+ attribute \src "libresoc.v:52961.9-52961.17"
case 1'1
case
end
sync always
update \ALU_inv_out $0\ALU_inv_out[0:0]
end
- attribute \src "libresoc.v:53169.3-53202.6"
- process $proc$libresoc.v:53169$3463
+ attribute \src "libresoc.v:52994.3-53027.6"
+ process $proc$libresoc.v:52994$3447
assign { } { }
assign { } { }
assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53170.5-53170.29"
+ attribute \src "libresoc.v:52995.5-52995.29"
switch \initial
- attribute \src "libresoc.v:53170.9-53170.17"
+ attribute \src "libresoc.v:52995.9-52995.17"
case 1'1
case
end
sync always
update \ALU_cry_out $0\ALU_cry_out[0:0]
end
- attribute \src "libresoc.v:53203.3-53236.6"
- process $proc$libresoc.v:53203$3464
+ attribute \src "libresoc.v:53028.3-53061.6"
+ process $proc$libresoc.v:53028$3448
assign { } { }
assign { } { }
assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53204.5-53204.29"
+ attribute \src "libresoc.v:53029.5-53029.29"
switch \initial
- attribute \src "libresoc.v:53204.9-53204.17"
+ attribute \src "libresoc.v:53029.9-53029.17"
case 1'1
case
end
sync always
update \ALU_is_32b $0\ALU_is_32b[0:0]
end
- attribute \src "libresoc.v:53237.3-53270.6"
- process $proc$libresoc.v:53237$3465
+ attribute \src "libresoc.v:53062.3-53095.6"
+ process $proc$libresoc.v:53062$3449
assign { } { }
assign { } { }
assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0]
- attribute \src "libresoc.v:53238.5-53238.29"
+ attribute \src "libresoc.v:53063.5-53063.29"
switch \initial
- attribute \src "libresoc.v:53238.9-53238.17"
+ attribute \src "libresoc.v:53063.9-53063.17"
case 1'1
case
end
sync always
update \ALU_sgn $0\ALU_sgn[0:0]
end
- attribute \src "libresoc.v:53271.3-53304.6"
- process $proc$libresoc.v:53271$3466
+ attribute \src "libresoc.v:53096.3-53129.6"
+ process $proc$libresoc.v:53096$3450
assign { } { }
assign { } { }
assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0]
- attribute \src "libresoc.v:53272.5-53272.29"
+ attribute \src "libresoc.v:53097.5-53097.29"
switch \initial
- attribute \src "libresoc.v:53272.9-53272.17"
+ attribute \src "libresoc.v:53097.9-53097.17"
case 1'1
case
end
sync always
update \ALU_function_unit $0\ALU_function_unit[13:0]
end
- attribute \src "libresoc.v:53305.3-53338.6"
- process $proc$libresoc.v:53305$3467
+ attribute \src "libresoc.v:53130.3-53163.6"
+ process $proc$libresoc.v:53130$3451
assign { } { }
assign { } { }
assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53306.5-53306.29"
+ attribute \src "libresoc.v:53131.5-53131.29"
switch \initial
- attribute \src "libresoc.v:53306.9-53306.17"
+ attribute \src "libresoc.v:53131.9-53131.17"
case 1'1
case
end
sync always
update \ALU_internal_op $0\ALU_internal_op[6:0]
end
- attribute \src "libresoc.v:53339.3-53372.6"
- process $proc$libresoc.v:53339$3468
+ attribute \src "libresoc.v:53164.3-53197.6"
+ process $proc$libresoc.v:53164$3452
assign { } { }
assign { } { }
assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53340.5-53340.29"
+ attribute \src "libresoc.v:53165.5-53165.29"
switch \initial
- attribute \src "libresoc.v:53340.9-53340.17"
+ attribute \src "libresoc.v:53165.9-53165.17"
case 1'1
case
end
sync always
update \ALU_in1_sel $0\ALU_in1_sel[2:0]
end
- attribute \src "libresoc.v:53373.3-53406.6"
- process $proc$libresoc.v:53373$3469
+ attribute \src "libresoc.v:53198.3-53231.6"
+ process $proc$libresoc.v:53198$3453
assign { } { }
assign { } { }
assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53374.5-53374.29"
+ attribute \src "libresoc.v:53199.5-53199.29"
switch \initial
- attribute \src "libresoc.v:53374.9-53374.17"
+ attribute \src "libresoc.v:53199.9-53199.17"
case 1'1
case
end
sync always
update \ALU_in2_sel $0\ALU_in2_sel[3:0]
end
- attribute \src "libresoc.v:53407.3-53440.6"
- process $proc$libresoc.v:53407$3470
+ attribute \src "libresoc.v:53232.3-53265.6"
+ process $proc$libresoc.v:53232$3454
assign { } { }
assign { } { }
assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53408.5-53408.29"
+ attribute \src "libresoc.v:53233.5-53233.29"
switch \initial
- attribute \src "libresoc.v:53408.9-53408.17"
+ attribute \src "libresoc.v:53233.9-53233.17"
case 1'1
case
end
sync always
update \ALU_cr_in $0\ALU_cr_in[2:0]
end
- attribute \src "libresoc.v:53441.3-53474.6"
- process $proc$libresoc.v:53441$3471
+ attribute \src "libresoc.v:53266.3-53299.6"
+ process $proc$libresoc.v:53266$3455
assign { } { }
assign { } { }
assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53442.5-53442.29"
+ attribute \src "libresoc.v:53267.5-53267.29"
switch \initial
- attribute \src "libresoc.v:53442.9-53442.17"
+ attribute \src "libresoc.v:53267.9-53267.17"
case 1'1
case
end
sync always
update \ALU_cr_out $0\ALU_cr_out[2:0]
end
- attribute \src "libresoc.v:53475.3-53508.6"
- process $proc$libresoc.v:53475$3472
+ attribute \src "libresoc.v:53300.3-53333.6"
+ process $proc$libresoc.v:53300$3456
assign { } { }
assign { } { }
assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53476.5-53476.29"
+ attribute \src "libresoc.v:53301.5-53301.29"
switch \initial
- attribute \src "libresoc.v:53476.9-53476.17"
+ attribute \src "libresoc.v:53301.9-53301.17"
case 1'1
case
end
sync always
update \ALU_ldst_len $0\ALU_ldst_len[3:0]
end
- connect \$1 $ternary$libresoc.v:52998$3458_Y
+ connect \$1 $ternary$libresoc.v:52823$3442_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \ALU_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:53850.1-55315.10"
+attribute \src "libresoc.v:53675.1-55140.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec"
attribute \generator "nMigen"
module \dec$138
- attribute \src "libresoc.v:54939.3-54951.6"
+ attribute \src "libresoc.v:54764.3-54776.6"
wire width 3 $0\CR_cr_in[2:0]
- attribute \src "libresoc.v:54952.3-54964.6"
+ attribute \src "libresoc.v:54777.3-54789.6"
wire width 3 $0\CR_cr_out[2:0]
- attribute \src "libresoc.v:54913.3-54925.6"
+ attribute \src "libresoc.v:54738.3-54750.6"
wire width 14 $0\CR_function_unit[13:0]
- attribute \src "libresoc.v:54926.3-54938.6"
+ attribute \src "libresoc.v:54751.3-54763.6"
wire width 7 $0\CR_internal_op[6:0]
- attribute \src "libresoc.v:54965.3-54977.6"
+ attribute \src "libresoc.v:54790.3-54802.6"
wire width 2 $0\CR_rc_sel[1:0]
- attribute \src "libresoc.v:53851.7-53851.20"
+ attribute \src "libresoc.v:53676.7-53676.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:54939.3-54951.6"
+ attribute \src "libresoc.v:54764.3-54776.6"
wire width 3 $1\CR_cr_in[2:0]
- attribute \src "libresoc.v:54952.3-54964.6"
+ attribute \src "libresoc.v:54777.3-54789.6"
wire width 3 $1\CR_cr_out[2:0]
- attribute \src "libresoc.v:54913.3-54925.6"
+ attribute \src "libresoc.v:54738.3-54750.6"
wire width 14 $1\CR_function_unit[13:0]
- attribute \src "libresoc.v:54926.3-54938.6"
+ attribute \src "libresoc.v:54751.3-54763.6"
wire width 7 $1\CR_internal_op[6:0]
- attribute \src "libresoc.v:54965.3-54977.6"
+ attribute \src "libresoc.v:54790.3-54802.6"
wire width 2 $1\CR_rc_sel[1:0]
- attribute \src "libresoc.v:54896.17-54896.211"
- wire width 32 $ternary$libresoc.v:54896$3474_Y
+ attribute \src "libresoc.v:54721.17-54721.211"
+ wire width 32 $ternary$libresoc.v:54721$3458_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:53851.7-53851.15"
+ attribute \src "libresoc.v:53676.7-53676.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 10 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:54896$3474
+ cell $mux $ternary$libresoc.v:54721$3458
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:54896$3474_Y
+ connect \Y $ternary$libresoc.v:54721$3458_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:54897.12-54904.4"
+ attribute \src "libresoc.v:54722.12-54729.4"
cell \CR_dec19 \CR_dec19
connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in
connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out
connect \opcode_in \CR_dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:54905.12-54912.4"
+ attribute \src "libresoc.v:54730.12-54737.4"
cell \CR_dec31 \CR_dec31
connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in
connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out
connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel
connect \opcode_in \CR_dec31_opcode_in
end
- attribute \src "libresoc.v:53851.7-53851.20"
- process $proc$libresoc.v:53851$3480
+ attribute \src "libresoc.v:53676.7-53676.20"
+ process $proc$libresoc.v:53676$3464
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:54913.3-54925.6"
- process $proc$libresoc.v:54913$3475
+ attribute \src "libresoc.v:54738.3-54750.6"
+ process $proc$libresoc.v:54738$3459
assign { } { }
assign { } { }
assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0]
- attribute \src "libresoc.v:54914.5-54914.29"
+ attribute \src "libresoc.v:54739.5-54739.29"
switch \initial
- attribute \src "libresoc.v:54914.9-54914.17"
+ attribute \src "libresoc.v:54739.9-54739.17"
case 1'1
case
end
sync always
update \CR_function_unit $0\CR_function_unit[13:0]
end
- attribute \src "libresoc.v:54926.3-54938.6"
- process $proc$libresoc.v:54926$3476
+ attribute \src "libresoc.v:54751.3-54763.6"
+ process $proc$libresoc.v:54751$3460
assign { } { }
assign { } { }
assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0]
- attribute \src "libresoc.v:54927.5-54927.29"
+ attribute \src "libresoc.v:54752.5-54752.29"
switch \initial
- attribute \src "libresoc.v:54927.9-54927.17"
+ attribute \src "libresoc.v:54752.9-54752.17"
case 1'1
case
end
sync always
update \CR_internal_op $0\CR_internal_op[6:0]
end
- attribute \src "libresoc.v:54939.3-54951.6"
- process $proc$libresoc.v:54939$3477
+ attribute \src "libresoc.v:54764.3-54776.6"
+ process $proc$libresoc.v:54764$3461
assign { } { }
assign { } { }
assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0]
- attribute \src "libresoc.v:54940.5-54940.29"
+ attribute \src "libresoc.v:54765.5-54765.29"
switch \initial
- attribute \src "libresoc.v:54940.9-54940.17"
+ attribute \src "libresoc.v:54765.9-54765.17"
case 1'1
case
end
sync always
update \CR_cr_in $0\CR_cr_in[2:0]
end
- attribute \src "libresoc.v:54952.3-54964.6"
- process $proc$libresoc.v:54952$3478
+ attribute \src "libresoc.v:54777.3-54789.6"
+ process $proc$libresoc.v:54777$3462
assign { } { }
assign { } { }
assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0]
- attribute \src "libresoc.v:54953.5-54953.29"
+ attribute \src "libresoc.v:54778.5-54778.29"
switch \initial
- attribute \src "libresoc.v:54953.9-54953.17"
+ attribute \src "libresoc.v:54778.9-54778.17"
case 1'1
case
end
sync always
update \CR_cr_out $0\CR_cr_out[2:0]
end
- attribute \src "libresoc.v:54965.3-54977.6"
- process $proc$libresoc.v:54965$3479
+ attribute \src "libresoc.v:54790.3-54802.6"
+ process $proc$libresoc.v:54790$3463
assign { } { }
assign { } { }
assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0]
- attribute \src "libresoc.v:54966.5-54966.29"
+ attribute \src "libresoc.v:54791.5-54791.29"
switch \initial
- attribute \src "libresoc.v:54966.9-54966.17"
+ attribute \src "libresoc.v:54791.9-54791.17"
case 1'1
case
end
sync always
update \CR_rc_sel $0\CR_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:54896$3474_Y
+ connect \$1 $ternary$libresoc.v:54721$3458_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \CR_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:55319.1-56764.10"
+attribute \src "libresoc.v:55144.1-56589.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec"
attribute \generator "nMigen"
module \dec$141
- attribute \src "libresoc.v:56348.3-56363.6"
+ attribute \src "libresoc.v:56173.3-56188.6"
wire width 3 $0\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56364.3-56379.6"
+ attribute \src "libresoc.v:56189.3-56204.6"
wire width 3 $0\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56300.3-56315.6"
+ attribute \src "libresoc.v:56125.3-56140.6"
wire width 14 $0\BRANCH_function_unit[13:0]
- attribute \src "libresoc.v:56332.3-56347.6"
+ attribute \src "libresoc.v:56157.3-56172.6"
wire width 4 $0\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56316.3-56331.6"
+ attribute \src "libresoc.v:56141.3-56156.6"
wire width 7 $0\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56396.3-56411.6"
+ attribute \src "libresoc.v:56221.3-56236.6"
wire $0\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56412.3-56427.6"
+ attribute \src "libresoc.v:56237.3-56252.6"
wire $0\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56380.3-56395.6"
+ attribute \src "libresoc.v:56205.3-56220.6"
wire width 2 $0\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:55320.7-55320.20"
+ attribute \src "libresoc.v:55145.7-55145.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:56348.3-56363.6"
+ attribute \src "libresoc.v:56173.3-56188.6"
wire width 3 $1\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56364.3-56379.6"
+ attribute \src "libresoc.v:56189.3-56204.6"
wire width 3 $1\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56300.3-56315.6"
+ attribute \src "libresoc.v:56125.3-56140.6"
wire width 14 $1\BRANCH_function_unit[13:0]
- attribute \src "libresoc.v:56332.3-56347.6"
+ attribute \src "libresoc.v:56157.3-56172.6"
wire width 4 $1\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56316.3-56331.6"
+ attribute \src "libresoc.v:56141.3-56156.6"
wire width 7 $1\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56396.3-56411.6"
+ attribute \src "libresoc.v:56221.3-56236.6"
wire $1\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56412.3-56427.6"
+ attribute \src "libresoc.v:56237.3-56252.6"
wire $1\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56380.3-56395.6"
+ attribute \src "libresoc.v:56205.3-56220.6"
wire width 2 $1\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:56288.17-56288.211"
- wire width 32 $ternary$libresoc.v:56288$3481_Y
+ attribute \src "libresoc.v:56113.17-56113.211"
+ wire width 32 $ternary$libresoc.v:56113$3465_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:55320.7-55320.15"
+ attribute \src "libresoc.v:55145.7-55145.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 21 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:56288$3481
+ cell $mux $ternary$libresoc.v:56113$3465
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:56288$3481_Y
+ connect \Y $ternary$libresoc.v:56113$3465_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:56289.16-56299.4"
+ attribute \src "libresoc.v:56114.16-56124.4"
cell \BRANCH_dec19 \BRANCH_dec19
connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in
connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out
connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel
connect \opcode_in \BRANCH_dec19_opcode_in
end
- attribute \src "libresoc.v:55320.7-55320.20"
- process $proc$libresoc.v:55320$3490
+ attribute \src "libresoc.v:55145.7-55145.20"
+ process $proc$libresoc.v:55145$3474
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:56300.3-56315.6"
- process $proc$libresoc.v:56300$3482
+ attribute \src "libresoc.v:56125.3-56140.6"
+ process $proc$libresoc.v:56125$3466
assign { } { }
assign { } { }
assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0]
- attribute \src "libresoc.v:56301.5-56301.29"
+ attribute \src "libresoc.v:56126.5-56126.29"
switch \initial
- attribute \src "libresoc.v:56301.9-56301.17"
+ attribute \src "libresoc.v:56126.9-56126.17"
case 1'1
case
end
sync always
update \BRANCH_function_unit $0\BRANCH_function_unit[13:0]
end
- attribute \src "libresoc.v:56316.3-56331.6"
- process $proc$libresoc.v:56316$3483
+ attribute \src "libresoc.v:56141.3-56156.6"
+ process $proc$libresoc.v:56141$3467
assign { } { }
assign { } { }
assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56317.5-56317.29"
+ attribute \src "libresoc.v:56142.5-56142.29"
switch \initial
- attribute \src "libresoc.v:56317.9-56317.17"
+ attribute \src "libresoc.v:56142.9-56142.17"
case 1'1
case
end
sync always
update \BRANCH_internal_op $0\BRANCH_internal_op[6:0]
end
- attribute \src "libresoc.v:56332.3-56347.6"
- process $proc$libresoc.v:56332$3484
+ attribute \src "libresoc.v:56157.3-56172.6"
+ process $proc$libresoc.v:56157$3468
assign { } { }
assign { } { }
assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56333.5-56333.29"
+ attribute \src "libresoc.v:56158.5-56158.29"
switch \initial
- attribute \src "libresoc.v:56333.9-56333.17"
+ attribute \src "libresoc.v:56158.9-56158.17"
case 1'1
case
end
sync always
update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0]
end
- attribute \src "libresoc.v:56348.3-56363.6"
- process $proc$libresoc.v:56348$3485
+ attribute \src "libresoc.v:56173.3-56188.6"
+ process $proc$libresoc.v:56173$3469
assign { } { }
assign { } { }
assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56349.5-56349.29"
+ attribute \src "libresoc.v:56174.5-56174.29"
switch \initial
- attribute \src "libresoc.v:56349.9-56349.17"
+ attribute \src "libresoc.v:56174.9-56174.17"
case 1'1
case
end
sync always
update \BRANCH_cr_in $0\BRANCH_cr_in[2:0]
end
- attribute \src "libresoc.v:56364.3-56379.6"
- process $proc$libresoc.v:56364$3486
+ attribute \src "libresoc.v:56189.3-56204.6"
+ process $proc$libresoc.v:56189$3470
assign { } { }
assign { } { }
assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56365.5-56365.29"
+ attribute \src "libresoc.v:56190.5-56190.29"
switch \initial
- attribute \src "libresoc.v:56365.9-56365.17"
+ attribute \src "libresoc.v:56190.9-56190.17"
case 1'1
case
end
sync always
update \BRANCH_cr_out $0\BRANCH_cr_out[2:0]
end
- attribute \src "libresoc.v:56380.3-56395.6"
- process $proc$libresoc.v:56380$3487
+ attribute \src "libresoc.v:56205.3-56220.6"
+ process $proc$libresoc.v:56205$3471
assign { } { }
assign { } { }
assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:56381.5-56381.29"
+ attribute \src "libresoc.v:56206.5-56206.29"
switch \initial
- attribute \src "libresoc.v:56381.9-56381.17"
+ attribute \src "libresoc.v:56206.9-56206.17"
case 1'1
case
end
sync always
update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0]
end
- attribute \src "libresoc.v:56396.3-56411.6"
- process $proc$libresoc.v:56396$3488
+ attribute \src "libresoc.v:56221.3-56236.6"
+ process $proc$libresoc.v:56221$3472
assign { } { }
assign { } { }
assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56397.5-56397.29"
+ attribute \src "libresoc.v:56222.5-56222.29"
switch \initial
- attribute \src "libresoc.v:56397.9-56397.17"
+ attribute \src "libresoc.v:56222.9-56222.17"
case 1'1
case
end
sync always
update \BRANCH_is_32b $0\BRANCH_is_32b[0:0]
end
- attribute \src "libresoc.v:56412.3-56427.6"
- process $proc$libresoc.v:56412$3489
+ attribute \src "libresoc.v:56237.3-56252.6"
+ process $proc$libresoc.v:56237$3473
assign { } { }
assign { } { }
assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56413.5-56413.29"
+ attribute \src "libresoc.v:56238.5-56238.29"
switch \initial
- attribute \src "libresoc.v:56413.9-56413.17"
+ attribute \src "libresoc.v:56238.9-56238.17"
case 1'1
case
end
sync always
update \BRANCH_lk $0\BRANCH_lk[0:0]
end
- connect \$1 $ternary$libresoc.v:56288$3481_Y
+ connect \$1 $ternary$libresoc.v:56113$3465_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \BRANCH_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:56768.1-58545.10"
+attribute \src "libresoc.v:56593.1-58370.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec"
attribute \generator "nMigen"
module \dec$145
- attribute \src "libresoc.v:58097.3-58124.6"
+ attribute \src "libresoc.v:57922.3-57949.6"
wire width 3 $0\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58125.3-58152.6"
+ attribute \src "libresoc.v:57950.3-57977.6"
wire width 3 $0\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:57817.3-57844.6"
+ attribute \src "libresoc.v:57642.3-57669.6"
wire width 2 $0\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:57901.3-57928.6"
+ attribute \src "libresoc.v:57726.3-57753.6"
wire $0\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:57985.3-58012.6"
+ attribute \src "libresoc.v:57810.3-57837.6"
wire width 14 $0\LOGICAL_function_unit[13:0]
- attribute \src "libresoc.v:58041.3-58068.6"
+ attribute \src "libresoc.v:57866.3-57893.6"
wire width 3 $0\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58069.3-58096.6"
+ attribute \src "libresoc.v:57894.3-57921.6"
wire width 4 $0\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58013.3-58040.6"
+ attribute \src "libresoc.v:57838.3-57865.6"
wire width 7 $0\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:57845.3-57872.6"
+ attribute \src "libresoc.v:57670.3-57697.6"
wire $0\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:57873.3-57900.6"
+ attribute \src "libresoc.v:57698.3-57725.6"
wire $0\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:57929.3-57956.6"
+ attribute \src "libresoc.v:57754.3-57781.6"
wire $0\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:58153.3-58180.6"
+ attribute \src "libresoc.v:57978.3-58005.6"
wire width 4 $0\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58181.3-58208.6"
+ attribute \src "libresoc.v:58006.3-58033.6"
wire width 2 $0\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:57957.3-57984.6"
+ attribute \src "libresoc.v:57782.3-57809.6"
wire $0\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:56769.7-56769.20"
+ attribute \src "libresoc.v:56594.7-56594.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:58097.3-58124.6"
+ attribute \src "libresoc.v:57922.3-57949.6"
wire width 3 $1\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58125.3-58152.6"
+ attribute \src "libresoc.v:57950.3-57977.6"
wire width 3 $1\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:57817.3-57844.6"
+ attribute \src "libresoc.v:57642.3-57669.6"
wire width 2 $1\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:57901.3-57928.6"
+ attribute \src "libresoc.v:57726.3-57753.6"
wire $1\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:57985.3-58012.6"
+ attribute \src "libresoc.v:57810.3-57837.6"
wire width 14 $1\LOGICAL_function_unit[13:0]
- attribute \src "libresoc.v:58041.3-58068.6"
+ attribute \src "libresoc.v:57866.3-57893.6"
wire width 3 $1\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58069.3-58096.6"
+ attribute \src "libresoc.v:57894.3-57921.6"
wire width 4 $1\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58013.3-58040.6"
+ attribute \src "libresoc.v:57838.3-57865.6"
wire width 7 $1\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:57845.3-57872.6"
+ attribute \src "libresoc.v:57670.3-57697.6"
wire $1\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:57873.3-57900.6"
+ attribute \src "libresoc.v:57698.3-57725.6"
wire $1\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:57929.3-57956.6"
+ attribute \src "libresoc.v:57754.3-57781.6"
wire $1\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:58153.3-58180.6"
+ attribute \src "libresoc.v:57978.3-58005.6"
wire width 4 $1\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58181.3-58208.6"
+ attribute \src "libresoc.v:58006.3-58033.6"
wire width 2 $1\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:57957.3-57984.6"
+ attribute \src "libresoc.v:57782.3-57809.6"
wire $1\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:57799.17-57799.211"
- wire width 32 $ternary$libresoc.v:57799$3491_Y
+ attribute \src "libresoc.v:57624.17-57624.211"
+ wire width 32 $ternary$libresoc.v:57624$3475_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:56769.7-56769.15"
+ attribute \src "libresoc.v:56594.7-56594.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:57799$3491
+ cell $mux $ternary$libresoc.v:57624$3475
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:57799$3491_Y
+ connect \Y $ternary$libresoc.v:57624$3475_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:57800.17-57816.4"
+ attribute \src "libresoc.v:57625.17-57641.4"
cell \LOGICAL_dec31 \LOGICAL_dec31
connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in
connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out
connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn
connect \opcode_in \LOGICAL_dec31_opcode_in
end
- attribute \src "libresoc.v:56769.7-56769.20"
- process $proc$libresoc.v:56769$3506
+ attribute \src "libresoc.v:56594.7-56594.20"
+ process $proc$libresoc.v:56594$3490
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:57817.3-57844.6"
- process $proc$libresoc.v:57817$3492
+ attribute \src "libresoc.v:57642.3-57669.6"
+ process $proc$libresoc.v:57642$3476
assign { } { }
assign { } { }
assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:57818.5-57818.29"
+ attribute \src "libresoc.v:57643.5-57643.29"
switch \initial
- attribute \src "libresoc.v:57818.9-57818.17"
+ attribute \src "libresoc.v:57643.9-57643.17"
case 1'1
case
end
sync always
update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0]
end
- attribute \src "libresoc.v:57845.3-57872.6"
- process $proc$libresoc.v:57845$3493
+ attribute \src "libresoc.v:57670.3-57697.6"
+ process $proc$libresoc.v:57670$3477
assign { } { }
assign { } { }
assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:57846.5-57846.29"
+ attribute \src "libresoc.v:57671.5-57671.29"
switch \initial
- attribute \src "libresoc.v:57846.9-57846.17"
+ attribute \src "libresoc.v:57671.9-57671.17"
case 1'1
case
end
sync always
update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0]
end
- attribute \src "libresoc.v:57873.3-57900.6"
- process $proc$libresoc.v:57873$3494
+ attribute \src "libresoc.v:57698.3-57725.6"
+ process $proc$libresoc.v:57698$3478
assign { } { }
assign { } { }
assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:57874.5-57874.29"
+ attribute \src "libresoc.v:57699.5-57699.29"
switch \initial
- attribute \src "libresoc.v:57874.9-57874.17"
+ attribute \src "libresoc.v:57699.9-57699.17"
case 1'1
case
end
sync always
update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0]
end
- attribute \src "libresoc.v:57901.3-57928.6"
- process $proc$libresoc.v:57901$3495
+ attribute \src "libresoc.v:57726.3-57753.6"
+ process $proc$libresoc.v:57726$3479
assign { } { }
assign { } { }
assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:57902.5-57902.29"
+ attribute \src "libresoc.v:57727.5-57727.29"
switch \initial
- attribute \src "libresoc.v:57902.9-57902.17"
+ attribute \src "libresoc.v:57727.9-57727.17"
case 1'1
case
end
sync always
update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0]
end
- attribute \src "libresoc.v:57929.3-57956.6"
- process $proc$libresoc.v:57929$3496
+ attribute \src "libresoc.v:57754.3-57781.6"
+ process $proc$libresoc.v:57754$3480
assign { } { }
assign { } { }
assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:57930.5-57930.29"
+ attribute \src "libresoc.v:57755.5-57755.29"
switch \initial
- attribute \src "libresoc.v:57930.9-57930.17"
+ attribute \src "libresoc.v:57755.9-57755.17"
case 1'1
case
end
sync always
update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0]
end
- attribute \src "libresoc.v:57957.3-57984.6"
- process $proc$libresoc.v:57957$3497
+ attribute \src "libresoc.v:57782.3-57809.6"
+ process $proc$libresoc.v:57782$3481
assign { } { }
assign { } { }
assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:57958.5-57958.29"
+ attribute \src "libresoc.v:57783.5-57783.29"
switch \initial
- attribute \src "libresoc.v:57958.9-57958.17"
+ attribute \src "libresoc.v:57783.9-57783.17"
case 1'1
case
end
sync always
update \LOGICAL_sgn $0\LOGICAL_sgn[0:0]
end
- attribute \src "libresoc.v:57985.3-58012.6"
- process $proc$libresoc.v:57985$3498
+ attribute \src "libresoc.v:57810.3-57837.6"
+ process $proc$libresoc.v:57810$3482
assign { } { }
assign { } { }
assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0]
- attribute \src "libresoc.v:57986.5-57986.29"
+ attribute \src "libresoc.v:57811.5-57811.29"
switch \initial
- attribute \src "libresoc.v:57986.9-57986.17"
+ attribute \src "libresoc.v:57811.9-57811.17"
case 1'1
case
end
sync always
update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0]
end
- attribute \src "libresoc.v:58013.3-58040.6"
- process $proc$libresoc.v:58013$3499
+ attribute \src "libresoc.v:57838.3-57865.6"
+ process $proc$libresoc.v:57838$3483
assign { } { }
assign { } { }
assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:58014.5-58014.29"
+ attribute \src "libresoc.v:57839.5-57839.29"
switch \initial
- attribute \src "libresoc.v:58014.9-58014.17"
+ attribute \src "libresoc.v:57839.9-57839.17"
case 1'1
case
end
sync always
update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0]
end
- attribute \src "libresoc.v:58041.3-58068.6"
- process $proc$libresoc.v:58041$3500
+ attribute \src "libresoc.v:57866.3-57893.6"
+ process $proc$libresoc.v:57866$3484
assign { } { }
assign { } { }
assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58042.5-58042.29"
+ attribute \src "libresoc.v:57867.5-57867.29"
switch \initial
- attribute \src "libresoc.v:58042.9-58042.17"
+ attribute \src "libresoc.v:57867.9-57867.17"
case 1'1
case
end
sync always
update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0]
end
- attribute \src "libresoc.v:58069.3-58096.6"
- process $proc$libresoc.v:58069$3501
+ attribute \src "libresoc.v:57894.3-57921.6"
+ process $proc$libresoc.v:57894$3485
assign { } { }
assign { } { }
assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58070.5-58070.29"
+ attribute \src "libresoc.v:57895.5-57895.29"
switch \initial
- attribute \src "libresoc.v:58070.9-58070.17"
+ attribute \src "libresoc.v:57895.9-57895.17"
case 1'1
case
end
sync always
update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0]
end
- attribute \src "libresoc.v:58097.3-58124.6"
- process $proc$libresoc.v:58097$3502
+ attribute \src "libresoc.v:57922.3-57949.6"
+ process $proc$libresoc.v:57922$3486
assign { } { }
assign { } { }
assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58098.5-58098.29"
+ attribute \src "libresoc.v:57923.5-57923.29"
switch \initial
- attribute \src "libresoc.v:58098.9-58098.17"
+ attribute \src "libresoc.v:57923.9-57923.17"
case 1'1
case
end
sync always
update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0]
end
- attribute \src "libresoc.v:58125.3-58152.6"
- process $proc$libresoc.v:58125$3503
+ attribute \src "libresoc.v:57950.3-57977.6"
+ process $proc$libresoc.v:57950$3487
assign { } { }
assign { } { }
assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:58126.5-58126.29"
+ attribute \src "libresoc.v:57951.5-57951.29"
switch \initial
- attribute \src "libresoc.v:58126.9-58126.17"
+ attribute \src "libresoc.v:57951.9-57951.17"
case 1'1
case
end
sync always
update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0]
end
- attribute \src "libresoc.v:58153.3-58180.6"
- process $proc$libresoc.v:58153$3504
+ attribute \src "libresoc.v:57978.3-58005.6"
+ process $proc$libresoc.v:57978$3488
assign { } { }
assign { } { }
assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58154.5-58154.29"
+ attribute \src "libresoc.v:57979.5-57979.29"
switch \initial
- attribute \src "libresoc.v:58154.9-58154.17"
+ attribute \src "libresoc.v:57979.9-57979.17"
case 1'1
case
end
sync always
update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0]
end
- attribute \src "libresoc.v:58181.3-58208.6"
- process $proc$libresoc.v:58181$3505
+ attribute \src "libresoc.v:58006.3-58033.6"
+ process $proc$libresoc.v:58006$3489
assign { } { }
assign { } { }
assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:58182.5-58182.29"
+ attribute \src "libresoc.v:58007.5-58007.29"
switch \initial
- attribute \src "libresoc.v:58182.9-58182.17"
+ attribute \src "libresoc.v:58007.9-58007.17"
case 1'1
case
end
sync always
update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:57799$3491_Y
+ connect \$1 $ternary$libresoc.v:57624$3475_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \LOGICAL_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:58549.1-59884.10"
+attribute \src "libresoc.v:58374.1-59709.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec"
attribute \generator "nMigen"
module \dec$150
- attribute \src "libresoc.v:59508.3-59517.6"
+ attribute \src "libresoc.v:59333.3-59342.6"
wire width 3 $0\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59518.3-59527.6"
+ attribute \src "libresoc.v:59343.3-59352.6"
wire width 3 $0\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59488.3-59497.6"
+ attribute \src "libresoc.v:59313.3-59322.6"
wire width 14 $0\SPR_function_unit[13:0]
- attribute \src "libresoc.v:59498.3-59507.6"
+ attribute \src "libresoc.v:59323.3-59332.6"
wire width 7 $0\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59538.3-59547.6"
+ attribute \src "libresoc.v:59363.3-59372.6"
wire $0\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59528.3-59537.6"
+ attribute \src "libresoc.v:59353.3-59362.6"
wire width 2 $0\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:58550.7-58550.20"
+ attribute \src "libresoc.v:58375.7-58375.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:59508.3-59517.6"
+ attribute \src "libresoc.v:59333.3-59342.6"
wire width 3 $1\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59518.3-59527.6"
+ attribute \src "libresoc.v:59343.3-59352.6"
wire width 3 $1\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59488.3-59497.6"
+ attribute \src "libresoc.v:59313.3-59322.6"
wire width 14 $1\SPR_function_unit[13:0]
- attribute \src "libresoc.v:59498.3-59507.6"
+ attribute \src "libresoc.v:59323.3-59332.6"
wire width 7 $1\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59538.3-59547.6"
+ attribute \src "libresoc.v:59363.3-59372.6"
wire $1\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59528.3-59537.6"
+ attribute \src "libresoc.v:59353.3-59362.6"
wire width 2 $1\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:59478.17-59478.211"
- wire width 32 $ternary$libresoc.v:59478$3507_Y
+ attribute \src "libresoc.v:59303.17-59303.211"
+ wire width 32 $ternary$libresoc.v:59303$3491_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:58550.7-58550.15"
+ attribute \src "libresoc.v:58375.7-58375.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 11 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:59478$3507
+ cell $mux $ternary$libresoc.v:59303$3491
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:59478$3507_Y
+ connect \Y $ternary$libresoc.v:59303$3491_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:59479.13-59487.4"
+ attribute \src "libresoc.v:59304.13-59312.4"
cell \SPR_dec31 \SPR_dec31
connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in
connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out
connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel
connect \opcode_in \SPR_dec31_opcode_in
end
- attribute \src "libresoc.v:58550.7-58550.20"
- process $proc$libresoc.v:58550$3514
+ attribute \src "libresoc.v:58375.7-58375.20"
+ process $proc$libresoc.v:58375$3498
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:59488.3-59497.6"
- process $proc$libresoc.v:59488$3508
+ attribute \src "libresoc.v:59313.3-59322.6"
+ process $proc$libresoc.v:59313$3492
assign { } { }
assign { } { }
assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0]
- attribute \src "libresoc.v:59489.5-59489.29"
+ attribute \src "libresoc.v:59314.5-59314.29"
switch \initial
- attribute \src "libresoc.v:59489.9-59489.17"
+ attribute \src "libresoc.v:59314.9-59314.17"
case 1'1
case
end
sync always
update \SPR_function_unit $0\SPR_function_unit[13:0]
end
- attribute \src "libresoc.v:59498.3-59507.6"
- process $proc$libresoc.v:59498$3509
+ attribute \src "libresoc.v:59323.3-59332.6"
+ process $proc$libresoc.v:59323$3493
assign { } { }
assign { } { }
assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59499.5-59499.29"
+ attribute \src "libresoc.v:59324.5-59324.29"
switch \initial
- attribute \src "libresoc.v:59499.9-59499.17"
+ attribute \src "libresoc.v:59324.9-59324.17"
case 1'1
case
end
sync always
update \SPR_internal_op $0\SPR_internal_op[6:0]
end
- attribute \src "libresoc.v:59508.3-59517.6"
- process $proc$libresoc.v:59508$3510
+ attribute \src "libresoc.v:59333.3-59342.6"
+ process $proc$libresoc.v:59333$3494
assign { } { }
assign { } { }
assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59509.5-59509.29"
+ attribute \src "libresoc.v:59334.5-59334.29"
switch \initial
- attribute \src "libresoc.v:59509.9-59509.17"
+ attribute \src "libresoc.v:59334.9-59334.17"
case 1'1
case
end
sync always
update \SPR_cr_in $0\SPR_cr_in[2:0]
end
- attribute \src "libresoc.v:59518.3-59527.6"
- process $proc$libresoc.v:59518$3511
+ attribute \src "libresoc.v:59343.3-59352.6"
+ process $proc$libresoc.v:59343$3495
assign { } { }
assign { } { }
assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59519.5-59519.29"
+ attribute \src "libresoc.v:59344.5-59344.29"
switch \initial
- attribute \src "libresoc.v:59519.9-59519.17"
+ attribute \src "libresoc.v:59344.9-59344.17"
case 1'1
case
end
sync always
update \SPR_cr_out $0\SPR_cr_out[2:0]
end
- attribute \src "libresoc.v:59528.3-59537.6"
- process $proc$libresoc.v:59528$3512
+ attribute \src "libresoc.v:59353.3-59362.6"
+ process $proc$libresoc.v:59353$3496
assign { } { }
assign { } { }
assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:59529.5-59529.29"
+ attribute \src "libresoc.v:59354.5-59354.29"
switch \initial
- attribute \src "libresoc.v:59529.9-59529.17"
+ attribute \src "libresoc.v:59354.9-59354.17"
case 1'1
case
end
sync always
update \SPR_rc_sel $0\SPR_rc_sel[1:0]
end
- attribute \src "libresoc.v:59538.3-59547.6"
- process $proc$libresoc.v:59538$3513
+ attribute \src "libresoc.v:59363.3-59372.6"
+ process $proc$libresoc.v:59363$3497
assign { } { }
assign { } { }
assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59539.5-59539.29"
+ attribute \src "libresoc.v:59364.5-59364.29"
switch \initial
- attribute \src "libresoc.v:59539.9-59539.17"
+ attribute \src "libresoc.v:59364.9-59364.17"
case 1'1
case
end
sync always
update \SPR_is_32b $0\SPR_is_32b[0:0]
end
- connect \$1 $ternary$libresoc.v:59478$3507_Y
+ connect \$1 $ternary$libresoc.v:59303$3491_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \SPR_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:59888.1-61413.10"
+attribute \src "libresoc.v:59713.1-61238.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec"
attribute \generator "nMigen"
module \dec$153
- attribute \src "libresoc.v:61037.3-61046.6"
+ attribute \src "libresoc.v:60862.3-60871.6"
wire width 3 $0\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61047.3-61056.6"
+ attribute \src "libresoc.v:60872.3-60881.6"
wire width 3 $0\DIV_cr_out[2:0]
- attribute \src "libresoc.v:60937.3-60946.6"
+ attribute \src "libresoc.v:60762.3-60771.6"
wire width 2 $0\DIV_cry_in[1:0]
- attribute \src "libresoc.v:60967.3-60976.6"
+ attribute \src "libresoc.v:60792.3-60801.6"
wire $0\DIV_cry_out[0:0]
- attribute \src "libresoc.v:60997.3-61006.6"
+ attribute \src "libresoc.v:60822.3-60831.6"
wire width 14 $0\DIV_function_unit[13:0]
- attribute \src "libresoc.v:61017.3-61026.6"
+ attribute \src "libresoc.v:60842.3-60851.6"
wire width 3 $0\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61027.3-61036.6"
+ attribute \src "libresoc.v:60852.3-60861.6"
wire width 4 $0\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61007.3-61016.6"
+ attribute \src "libresoc.v:60832.3-60841.6"
wire width 7 $0\DIV_internal_op[6:0]
- attribute \src "libresoc.v:60947.3-60956.6"
+ attribute \src "libresoc.v:60772.3-60781.6"
wire $0\DIV_inv_a[0:0]
- attribute \src "libresoc.v:60957.3-60966.6"
+ attribute \src "libresoc.v:60782.3-60791.6"
wire $0\DIV_inv_out[0:0]
- attribute \src "libresoc.v:60977.3-60986.6"
+ attribute \src "libresoc.v:60802.3-60811.6"
wire $0\DIV_is_32b[0:0]
- attribute \src "libresoc.v:61057.3-61066.6"
+ attribute \src "libresoc.v:60882.3-60891.6"
wire width 4 $0\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61067.3-61076.6"
+ attribute \src "libresoc.v:60892.3-60901.6"
wire width 2 $0\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:60987.3-60996.6"
+ attribute \src "libresoc.v:60812.3-60821.6"
wire $0\DIV_sgn[0:0]
- attribute \src "libresoc.v:59889.7-59889.20"
+ attribute \src "libresoc.v:59714.7-59714.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:61037.3-61046.6"
+ attribute \src "libresoc.v:60862.3-60871.6"
wire width 3 $1\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61047.3-61056.6"
+ attribute \src "libresoc.v:60872.3-60881.6"
wire width 3 $1\DIV_cr_out[2:0]
- attribute \src "libresoc.v:60937.3-60946.6"
+ attribute \src "libresoc.v:60762.3-60771.6"
wire width 2 $1\DIV_cry_in[1:0]
- attribute \src "libresoc.v:60967.3-60976.6"
+ attribute \src "libresoc.v:60792.3-60801.6"
wire $1\DIV_cry_out[0:0]
- attribute \src "libresoc.v:60997.3-61006.6"
+ attribute \src "libresoc.v:60822.3-60831.6"
wire width 14 $1\DIV_function_unit[13:0]
- attribute \src "libresoc.v:61017.3-61026.6"
+ attribute \src "libresoc.v:60842.3-60851.6"
wire width 3 $1\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61027.3-61036.6"
+ attribute \src "libresoc.v:60852.3-60861.6"
wire width 4 $1\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61007.3-61016.6"
+ attribute \src "libresoc.v:60832.3-60841.6"
wire width 7 $1\DIV_internal_op[6:0]
- attribute \src "libresoc.v:60947.3-60956.6"
+ attribute \src "libresoc.v:60772.3-60781.6"
wire $1\DIV_inv_a[0:0]
- attribute \src "libresoc.v:60957.3-60966.6"
+ attribute \src "libresoc.v:60782.3-60791.6"
wire $1\DIV_inv_out[0:0]
- attribute \src "libresoc.v:60977.3-60986.6"
+ attribute \src "libresoc.v:60802.3-60811.6"
wire $1\DIV_is_32b[0:0]
- attribute \src "libresoc.v:61057.3-61066.6"
+ attribute \src "libresoc.v:60882.3-60891.6"
wire width 4 $1\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61067.3-61076.6"
+ attribute \src "libresoc.v:60892.3-60901.6"
wire width 2 $1\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:60987.3-60996.6"
+ attribute \src "libresoc.v:60812.3-60821.6"
wire $1\DIV_sgn[0:0]
- attribute \src "libresoc.v:60919.17-60919.211"
- wire width 32 $ternary$libresoc.v:60919$3515_Y
+ attribute \src "libresoc.v:60744.17-60744.211"
+ wire width 32 $ternary$libresoc.v:60744$3499_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:59889.7-59889.15"
+ attribute \src "libresoc.v:59714.7-59714.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:60919$3515
+ cell $mux $ternary$libresoc.v:60744$3499
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:60919$3515_Y
+ connect \Y $ternary$libresoc.v:60744$3499_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:60920.13-60936.4"
+ attribute \src "libresoc.v:60745.13-60761.4"
cell \DIV_dec31 \DIV_dec31
connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in
connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out
connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn
connect \opcode_in \DIV_dec31_opcode_in
end
- attribute \src "libresoc.v:59889.7-59889.20"
- process $proc$libresoc.v:59889$3530
+ attribute \src "libresoc.v:59714.7-59714.20"
+ process $proc$libresoc.v:59714$3514
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:60937.3-60946.6"
- process $proc$libresoc.v:60937$3516
+ attribute \src "libresoc.v:60762.3-60771.6"
+ process $proc$libresoc.v:60762$3500
assign { } { }
assign { } { }
assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0]
- attribute \src "libresoc.v:60938.5-60938.29"
+ attribute \src "libresoc.v:60763.5-60763.29"
switch \initial
- attribute \src "libresoc.v:60938.9-60938.17"
+ attribute \src "libresoc.v:60763.9-60763.17"
case 1'1
case
end
sync always
update \DIV_cry_in $0\DIV_cry_in[1:0]
end
- attribute \src "libresoc.v:60947.3-60956.6"
- process $proc$libresoc.v:60947$3517
+ attribute \src "libresoc.v:60772.3-60781.6"
+ process $proc$libresoc.v:60772$3501
assign { } { }
assign { } { }
assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0]
- attribute \src "libresoc.v:60948.5-60948.29"
+ attribute \src "libresoc.v:60773.5-60773.29"
switch \initial
- attribute \src "libresoc.v:60948.9-60948.17"
+ attribute \src "libresoc.v:60773.9-60773.17"
case 1'1
case
end
sync always
update \DIV_inv_a $0\DIV_inv_a[0:0]
end
- attribute \src "libresoc.v:60957.3-60966.6"
- process $proc$libresoc.v:60957$3518
+ attribute \src "libresoc.v:60782.3-60791.6"
+ process $proc$libresoc.v:60782$3502
assign { } { }
assign { } { }
assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0]
- attribute \src "libresoc.v:60958.5-60958.29"
+ attribute \src "libresoc.v:60783.5-60783.29"
switch \initial
- attribute \src "libresoc.v:60958.9-60958.17"
+ attribute \src "libresoc.v:60783.9-60783.17"
case 1'1
case
end
sync always
update \DIV_inv_out $0\DIV_inv_out[0:0]
end
- attribute \src "libresoc.v:60967.3-60976.6"
- process $proc$libresoc.v:60967$3519
+ attribute \src "libresoc.v:60792.3-60801.6"
+ process $proc$libresoc.v:60792$3503
assign { } { }
assign { } { }
assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0]
- attribute \src "libresoc.v:60968.5-60968.29"
+ attribute \src "libresoc.v:60793.5-60793.29"
switch \initial
- attribute \src "libresoc.v:60968.9-60968.17"
+ attribute \src "libresoc.v:60793.9-60793.17"
case 1'1
case
end
sync always
update \DIV_cry_out $0\DIV_cry_out[0:0]
end
- attribute \src "libresoc.v:60977.3-60986.6"
- process $proc$libresoc.v:60977$3520
+ attribute \src "libresoc.v:60802.3-60811.6"
+ process $proc$libresoc.v:60802$3504
assign { } { }
assign { } { }
assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0]
- attribute \src "libresoc.v:60978.5-60978.29"
+ attribute \src "libresoc.v:60803.5-60803.29"
switch \initial
- attribute \src "libresoc.v:60978.9-60978.17"
+ attribute \src "libresoc.v:60803.9-60803.17"
case 1'1
case
end
sync always
update \DIV_is_32b $0\DIV_is_32b[0:0]
end
- attribute \src "libresoc.v:60987.3-60996.6"
- process $proc$libresoc.v:60987$3521
+ attribute \src "libresoc.v:60812.3-60821.6"
+ process $proc$libresoc.v:60812$3505
assign { } { }
assign { } { }
assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0]
- attribute \src "libresoc.v:60988.5-60988.29"
+ attribute \src "libresoc.v:60813.5-60813.29"
switch \initial
- attribute \src "libresoc.v:60988.9-60988.17"
+ attribute \src "libresoc.v:60813.9-60813.17"
case 1'1
case
end
sync always
update \DIV_sgn $0\DIV_sgn[0:0]
end
- attribute \src "libresoc.v:60997.3-61006.6"
- process $proc$libresoc.v:60997$3522
+ attribute \src "libresoc.v:60822.3-60831.6"
+ process $proc$libresoc.v:60822$3506
assign { } { }
assign { } { }
assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0]
- attribute \src "libresoc.v:60998.5-60998.29"
+ attribute \src "libresoc.v:60823.5-60823.29"
switch \initial
- attribute \src "libresoc.v:60998.9-60998.17"
+ attribute \src "libresoc.v:60823.9-60823.17"
case 1'1
case
end
sync always
update \DIV_function_unit $0\DIV_function_unit[13:0]
end
- attribute \src "libresoc.v:61007.3-61016.6"
- process $proc$libresoc.v:61007$3523
+ attribute \src "libresoc.v:60832.3-60841.6"
+ process $proc$libresoc.v:60832$3507
assign { } { }
assign { } { }
assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0]
- attribute \src "libresoc.v:61008.5-61008.29"
+ attribute \src "libresoc.v:60833.5-60833.29"
switch \initial
- attribute \src "libresoc.v:61008.9-61008.17"
+ attribute \src "libresoc.v:60833.9-60833.17"
case 1'1
case
end
sync always
update \DIV_internal_op $0\DIV_internal_op[6:0]
end
- attribute \src "libresoc.v:61017.3-61026.6"
- process $proc$libresoc.v:61017$3524
+ attribute \src "libresoc.v:60842.3-60851.6"
+ process $proc$libresoc.v:60842$3508
assign { } { }
assign { } { }
assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61018.5-61018.29"
+ attribute \src "libresoc.v:60843.5-60843.29"
switch \initial
- attribute \src "libresoc.v:61018.9-61018.17"
+ attribute \src "libresoc.v:60843.9-60843.17"
case 1'1
case
end
sync always
update \DIV_in1_sel $0\DIV_in1_sel[2:0]
end
- attribute \src "libresoc.v:61027.3-61036.6"
- process $proc$libresoc.v:61027$3525
+ attribute \src "libresoc.v:60852.3-60861.6"
+ process $proc$libresoc.v:60852$3509
assign { } { }
assign { } { }
assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61028.5-61028.29"
+ attribute \src "libresoc.v:60853.5-60853.29"
switch \initial
- attribute \src "libresoc.v:61028.9-61028.17"
+ attribute \src "libresoc.v:60853.9-60853.17"
case 1'1
case
end
sync always
update \DIV_in2_sel $0\DIV_in2_sel[3:0]
end
- attribute \src "libresoc.v:61037.3-61046.6"
- process $proc$libresoc.v:61037$3526
+ attribute \src "libresoc.v:60862.3-60871.6"
+ process $proc$libresoc.v:60862$3510
assign { } { }
assign { } { }
assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61038.5-61038.29"
+ attribute \src "libresoc.v:60863.5-60863.29"
switch \initial
- attribute \src "libresoc.v:61038.9-61038.17"
+ attribute \src "libresoc.v:60863.9-60863.17"
case 1'1
case
end
sync always
update \DIV_cr_in $0\DIV_cr_in[2:0]
end
- attribute \src "libresoc.v:61047.3-61056.6"
- process $proc$libresoc.v:61047$3527
+ attribute \src "libresoc.v:60872.3-60881.6"
+ process $proc$libresoc.v:60872$3511
assign { } { }
assign { } { }
assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0]
- attribute \src "libresoc.v:61048.5-61048.29"
+ attribute \src "libresoc.v:60873.5-60873.29"
switch \initial
- attribute \src "libresoc.v:61048.9-61048.17"
+ attribute \src "libresoc.v:60873.9-60873.17"
case 1'1
case
end
sync always
update \DIV_cr_out $0\DIV_cr_out[2:0]
end
- attribute \src "libresoc.v:61057.3-61066.6"
- process $proc$libresoc.v:61057$3528
+ attribute \src "libresoc.v:60882.3-60891.6"
+ process $proc$libresoc.v:60882$3512
assign { } { }
assign { } { }
assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61058.5-61058.29"
+ attribute \src "libresoc.v:60883.5-60883.29"
switch \initial
- attribute \src "libresoc.v:61058.9-61058.17"
+ attribute \src "libresoc.v:60883.9-60883.17"
case 1'1
case
end
sync always
update \DIV_ldst_len $0\DIV_ldst_len[3:0]
end
- attribute \src "libresoc.v:61067.3-61076.6"
- process $proc$libresoc.v:61067$3529
+ attribute \src "libresoc.v:60892.3-60901.6"
+ process $proc$libresoc.v:60892$3513
assign { } { }
assign { } { }
assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:61068.5-61068.29"
+ attribute \src "libresoc.v:60893.5-60893.29"
switch \initial
- attribute \src "libresoc.v:61068.9-61068.17"
+ attribute \src "libresoc.v:60893.9-60893.17"
case 1'1
case
end
sync always
update \DIV_rc_sel $0\DIV_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:60919$3515_Y
+ connect \$1 $ternary$libresoc.v:60744$3499_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \DIV_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:61417.1-62838.10"
+attribute \src "libresoc.v:61242.1-62663.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec"
attribute \generator "nMigen"
module \dec$158
- attribute \src "libresoc.v:62437.3-62449.6"
+ attribute \src "libresoc.v:62262.3-62274.6"
wire width 3 $0\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62450.3-62462.6"
+ attribute \src "libresoc.v:62275.3-62287.6"
wire width 3 $0\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62398.3-62410.6"
+ attribute \src "libresoc.v:62223.3-62235.6"
wire width 14 $0\MUL_function_unit[13:0]
- attribute \src "libresoc.v:62424.3-62436.6"
+ attribute \src "libresoc.v:62249.3-62261.6"
wire width 4 $0\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62411.3-62423.6"
+ attribute \src "libresoc.v:62236.3-62248.6"
wire width 7 $0\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62476.3-62488.6"
+ attribute \src "libresoc.v:62301.3-62313.6"
wire $0\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62463.3-62475.6"
+ attribute \src "libresoc.v:62288.3-62300.6"
wire width 2 $0\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62489.3-62501.6"
+ attribute \src "libresoc.v:62314.3-62326.6"
wire $0\MUL_sgn[0:0]
- attribute \src "libresoc.v:61418.7-61418.20"
+ attribute \src "libresoc.v:61243.7-61243.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:62437.3-62449.6"
+ attribute \src "libresoc.v:62262.3-62274.6"
wire width 3 $1\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62450.3-62462.6"
+ attribute \src "libresoc.v:62275.3-62287.6"
wire width 3 $1\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62398.3-62410.6"
+ attribute \src "libresoc.v:62223.3-62235.6"
wire width 14 $1\MUL_function_unit[13:0]
- attribute \src "libresoc.v:62424.3-62436.6"
+ attribute \src "libresoc.v:62249.3-62261.6"
wire width 4 $1\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62411.3-62423.6"
+ attribute \src "libresoc.v:62236.3-62248.6"
wire width 7 $1\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62476.3-62488.6"
+ attribute \src "libresoc.v:62301.3-62313.6"
wire $1\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62463.3-62475.6"
+ attribute \src "libresoc.v:62288.3-62300.6"
wire width 2 $1\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62489.3-62501.6"
+ attribute \src "libresoc.v:62314.3-62326.6"
wire $1\MUL_sgn[0:0]
- attribute \src "libresoc.v:62386.17-62386.211"
- wire width 32 $ternary$libresoc.v:62386$3531_Y
+ attribute \src "libresoc.v:62211.17-62211.211"
+ wire width 32 $ternary$libresoc.v:62211$3515_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:61418.7-61418.15"
+ attribute \src "libresoc.v:61243.7-61243.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 20 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:62386$3531
+ cell $mux $ternary$libresoc.v:62211$3515
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:62386$3531_Y
+ connect \Y $ternary$libresoc.v:62211$3515_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:62387.13-62397.4"
+ attribute \src "libresoc.v:62212.13-62222.4"
cell \MUL_dec31 \MUL_dec31
connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in
connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out
connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn
connect \opcode_in \MUL_dec31_opcode_in
end
- attribute \src "libresoc.v:61418.7-61418.20"
- process $proc$libresoc.v:61418$3540
+ attribute \src "libresoc.v:61243.7-61243.20"
+ process $proc$libresoc.v:61243$3524
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:62398.3-62410.6"
- process $proc$libresoc.v:62398$3532
+ attribute \src "libresoc.v:62223.3-62235.6"
+ process $proc$libresoc.v:62223$3516
assign { } { }
assign { } { }
assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0]
- attribute \src "libresoc.v:62399.5-62399.29"
+ attribute \src "libresoc.v:62224.5-62224.29"
switch \initial
- attribute \src "libresoc.v:62399.9-62399.17"
+ attribute \src "libresoc.v:62224.9-62224.17"
case 1'1
case
end
sync always
update \MUL_function_unit $0\MUL_function_unit[13:0]
end
- attribute \src "libresoc.v:62411.3-62423.6"
- process $proc$libresoc.v:62411$3533
+ attribute \src "libresoc.v:62236.3-62248.6"
+ process $proc$libresoc.v:62236$3517
assign { } { }
assign { } { }
assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62412.5-62412.29"
+ attribute \src "libresoc.v:62237.5-62237.29"
switch \initial
- attribute \src "libresoc.v:62412.9-62412.17"
+ attribute \src "libresoc.v:62237.9-62237.17"
case 1'1
case
end
sync always
update \MUL_internal_op $0\MUL_internal_op[6:0]
end
- attribute \src "libresoc.v:62424.3-62436.6"
- process $proc$libresoc.v:62424$3534
+ attribute \src "libresoc.v:62249.3-62261.6"
+ process $proc$libresoc.v:62249$3518
assign { } { }
assign { } { }
assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62425.5-62425.29"
+ attribute \src "libresoc.v:62250.5-62250.29"
switch \initial
- attribute \src "libresoc.v:62425.9-62425.17"
+ attribute \src "libresoc.v:62250.9-62250.17"
case 1'1
case
end
sync always
update \MUL_in2_sel $0\MUL_in2_sel[3:0]
end
- attribute \src "libresoc.v:62437.3-62449.6"
- process $proc$libresoc.v:62437$3535
+ attribute \src "libresoc.v:62262.3-62274.6"
+ process $proc$libresoc.v:62262$3519
assign { } { }
assign { } { }
assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62438.5-62438.29"
+ attribute \src "libresoc.v:62263.5-62263.29"
switch \initial
- attribute \src "libresoc.v:62438.9-62438.17"
+ attribute \src "libresoc.v:62263.9-62263.17"
case 1'1
case
end
sync always
update \MUL_cr_in $0\MUL_cr_in[2:0]
end
- attribute \src "libresoc.v:62450.3-62462.6"
- process $proc$libresoc.v:62450$3536
+ attribute \src "libresoc.v:62275.3-62287.6"
+ process $proc$libresoc.v:62275$3520
assign { } { }
assign { } { }
assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62451.5-62451.29"
+ attribute \src "libresoc.v:62276.5-62276.29"
switch \initial
- attribute \src "libresoc.v:62451.9-62451.17"
+ attribute \src "libresoc.v:62276.9-62276.17"
case 1'1
case
end
sync always
update \MUL_cr_out $0\MUL_cr_out[2:0]
end
- attribute \src "libresoc.v:62463.3-62475.6"
- process $proc$libresoc.v:62463$3537
+ attribute \src "libresoc.v:62288.3-62300.6"
+ process $proc$libresoc.v:62288$3521
assign { } { }
assign { } { }
assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62464.5-62464.29"
+ attribute \src "libresoc.v:62289.5-62289.29"
switch \initial
- attribute \src "libresoc.v:62464.9-62464.17"
+ attribute \src "libresoc.v:62289.9-62289.17"
case 1'1
case
end
sync always
update \MUL_rc_sel $0\MUL_rc_sel[1:0]
end
- attribute \src "libresoc.v:62476.3-62488.6"
- process $proc$libresoc.v:62476$3538
+ attribute \src "libresoc.v:62301.3-62313.6"
+ process $proc$libresoc.v:62301$3522
assign { } { }
assign { } { }
assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62477.5-62477.29"
+ attribute \src "libresoc.v:62302.5-62302.29"
switch \initial
- attribute \src "libresoc.v:62477.9-62477.17"
+ attribute \src "libresoc.v:62302.9-62302.17"
case 1'1
case
end
sync always
update \MUL_is_32b $0\MUL_is_32b[0:0]
end
- attribute \src "libresoc.v:62489.3-62501.6"
- process $proc$libresoc.v:62489$3539
+ attribute \src "libresoc.v:62314.3-62326.6"
+ process $proc$libresoc.v:62314$3523
assign { } { }
assign { } { }
assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0]
- attribute \src "libresoc.v:62490.5-62490.29"
+ attribute \src "libresoc.v:62315.5-62315.29"
switch \initial
- attribute \src "libresoc.v:62490.9-62490.17"
+ attribute \src "libresoc.v:62315.9-62315.17"
case 1'1
case
end
sync always
update \MUL_sgn $0\MUL_sgn[0:0]
end
- connect \$1 $ternary$libresoc.v:62386$3531_Y
+ connect \$1 $ternary$libresoc.v:62211$3515_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \MUL_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:62842.1-64596.10"
+attribute \src "libresoc.v:62667.1-64421.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec"
attribute \generator "nMigen"
module \dec$162
- attribute \src "libresoc.v:64171.3-64192.6"
+ attribute \src "libresoc.v:63996.3-64017.6"
wire width 3 $0\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64193.3-64214.6"
+ attribute \src "libresoc.v:64018.3-64039.6"
wire width 3 $0\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64237.3-64258.6"
+ attribute \src "libresoc.v:64062.3-64083.6"
wire width 2 $0\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64039.3-64060.6"
+ attribute \src "libresoc.v:63864.3-63885.6"
wire $0\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64105.3-64126.6"
+ attribute \src "libresoc.v:63930.3-63951.6"
wire width 14 $0\SHIFT_ROT_function_unit[13:0]
- attribute \src "libresoc.v:64149.3-64170.6"
+ attribute \src "libresoc.v:63974.3-63995.6"
wire width 4 $0\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64127.3-64148.6"
+ attribute \src "libresoc.v:63952.3-63973.6"
wire width 7 $0\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64017.3-64038.6"
+ attribute \src "libresoc.v:63842.3-63863.6"
wire $0\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64061.3-64082.6"
+ attribute \src "libresoc.v:63886.3-63907.6"
wire $0\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64215.3-64236.6"
+ attribute \src "libresoc.v:64040.3-64061.6"
wire width 2 $0\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64083.3-64104.6"
+ attribute \src "libresoc.v:63908.3-63929.6"
wire $0\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:62843.7-62843.20"
+ attribute \src "libresoc.v:62668.7-62668.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:64171.3-64192.6"
+ attribute \src "libresoc.v:63996.3-64017.6"
wire width 3 $1\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64193.3-64214.6"
+ attribute \src "libresoc.v:64018.3-64039.6"
wire width 3 $1\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64237.3-64258.6"
+ attribute \src "libresoc.v:64062.3-64083.6"
wire width 2 $1\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64039.3-64060.6"
+ attribute \src "libresoc.v:63864.3-63885.6"
wire $1\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64105.3-64126.6"
+ attribute \src "libresoc.v:63930.3-63951.6"
wire width 14 $1\SHIFT_ROT_function_unit[13:0]
- attribute \src "libresoc.v:64149.3-64170.6"
+ attribute \src "libresoc.v:63974.3-63995.6"
wire width 4 $1\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64127.3-64148.6"
+ attribute \src "libresoc.v:63952.3-63973.6"
wire width 7 $1\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64017.3-64038.6"
+ attribute \src "libresoc.v:63842.3-63863.6"
wire $1\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64061.3-64082.6"
+ attribute \src "libresoc.v:63886.3-63907.6"
wire $1\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64215.3-64236.6"
+ attribute \src "libresoc.v:64040.3-64061.6"
wire width 2 $1\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64083.3-64104.6"
+ attribute \src "libresoc.v:63908.3-63929.6"
wire $1\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:63988.17-63988.211"
- wire width 32 $ternary$libresoc.v:63988$3541_Y
+ attribute \src "libresoc.v:63813.17-63813.211"
+ wire width 32 $ternary$libresoc.v:63813$3525_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:62843.7-62843.15"
+ attribute \src "libresoc.v:62668.7-62668.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 24 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:63988$3541
+ cell $mux $ternary$libresoc.v:63813$3525
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:63988$3541_Y
+ connect \Y $ternary$libresoc.v:63813$3525_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:63989.19-64002.4"
+ attribute \src "libresoc.v:63814.19-63827.4"
cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30
connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in
connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out
connect \opcode_in \SHIFT_ROT_dec30_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:64003.19-64016.4"
+ attribute \src "libresoc.v:63828.19-63841.4"
cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31
connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in
connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out
connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn
connect \opcode_in \SHIFT_ROT_dec31_opcode_in
end
- attribute \src "libresoc.v:62843.7-62843.20"
- process $proc$libresoc.v:62843$3553
+ attribute \src "libresoc.v:62668.7-62668.20"
+ process $proc$libresoc.v:62668$3537
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:64017.3-64038.6"
- process $proc$libresoc.v:64017$3542
+ attribute \src "libresoc.v:63842.3-63863.6"
+ process $proc$libresoc.v:63842$3526
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64018.5-64018.29"
+ attribute \src "libresoc.v:63843.5-63843.29"
switch \initial
- attribute \src "libresoc.v:64018.9-64018.17"
+ attribute \src "libresoc.v:63843.9-63843.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0]
end
- attribute \src "libresoc.v:64039.3-64060.6"
- process $proc$libresoc.v:64039$3543
+ attribute \src "libresoc.v:63864.3-63885.6"
+ process $proc$libresoc.v:63864$3527
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64040.5-64040.29"
+ attribute \src "libresoc.v:63865.5-63865.29"
switch \initial
- attribute \src "libresoc.v:64040.9-64040.17"
+ attribute \src "libresoc.v:63865.9-63865.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0]
end
- attribute \src "libresoc.v:64061.3-64082.6"
- process $proc$libresoc.v:64061$3544
+ attribute \src "libresoc.v:63886.3-63907.6"
+ process $proc$libresoc.v:63886$3528
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64062.5-64062.29"
+ attribute \src "libresoc.v:63887.5-63887.29"
switch \initial
- attribute \src "libresoc.v:64062.9-64062.17"
+ attribute \src "libresoc.v:63887.9-63887.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0]
end
- attribute \src "libresoc.v:64083.3-64104.6"
- process $proc$libresoc.v:64083$3545
+ attribute \src "libresoc.v:63908.3-63929.6"
+ process $proc$libresoc.v:63908$3529
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:64084.5-64084.29"
+ attribute \src "libresoc.v:63909.5-63909.29"
switch \initial
- attribute \src "libresoc.v:64084.9-64084.17"
+ attribute \src "libresoc.v:63909.9-63909.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0]
end
- attribute \src "libresoc.v:64105.3-64126.6"
- process $proc$libresoc.v:64105$3546
+ attribute \src "libresoc.v:63930.3-63951.6"
+ process $proc$libresoc.v:63930$3530
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0]
- attribute \src "libresoc.v:64106.5-64106.29"
+ attribute \src "libresoc.v:63931.5-63931.29"
switch \initial
- attribute \src "libresoc.v:64106.9-64106.17"
+ attribute \src "libresoc.v:63931.9-63931.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0]
end
- attribute \src "libresoc.v:64127.3-64148.6"
- process $proc$libresoc.v:64127$3547
+ attribute \src "libresoc.v:63952.3-63973.6"
+ process $proc$libresoc.v:63952$3531
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64128.5-64128.29"
+ attribute \src "libresoc.v:63953.5-63953.29"
switch \initial
- attribute \src "libresoc.v:64128.9-64128.17"
+ attribute \src "libresoc.v:63953.9-63953.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0]
end
- attribute \src "libresoc.v:64149.3-64170.6"
- process $proc$libresoc.v:64149$3548
+ attribute \src "libresoc.v:63974.3-63995.6"
+ process $proc$libresoc.v:63974$3532
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64150.5-64150.29"
+ attribute \src "libresoc.v:63975.5-63975.29"
switch \initial
- attribute \src "libresoc.v:64150.9-64150.17"
+ attribute \src "libresoc.v:63975.9-63975.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0]
end
- attribute \src "libresoc.v:64171.3-64192.6"
- process $proc$libresoc.v:64171$3549
+ attribute \src "libresoc.v:63996.3-64017.6"
+ process $proc$libresoc.v:63996$3533
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64172.5-64172.29"
+ attribute \src "libresoc.v:63997.5-63997.29"
switch \initial
- attribute \src "libresoc.v:64172.9-64172.17"
+ attribute \src "libresoc.v:63997.9-63997.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0]
end
- attribute \src "libresoc.v:64193.3-64214.6"
- process $proc$libresoc.v:64193$3550
+ attribute \src "libresoc.v:64018.3-64039.6"
+ process $proc$libresoc.v:64018$3534
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64194.5-64194.29"
+ attribute \src "libresoc.v:64019.5-64019.29"
switch \initial
- attribute \src "libresoc.v:64194.9-64194.17"
+ attribute \src "libresoc.v:64019.9-64019.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0]
end
- attribute \src "libresoc.v:64215.3-64236.6"
- process $proc$libresoc.v:64215$3551
+ attribute \src "libresoc.v:64040.3-64061.6"
+ process $proc$libresoc.v:64040$3535
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64216.5-64216.29"
+ attribute \src "libresoc.v:64041.5-64041.29"
switch \initial
- attribute \src "libresoc.v:64216.9-64216.17"
+ attribute \src "libresoc.v:64041.9-64041.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0]
end
- attribute \src "libresoc.v:64237.3-64258.6"
- process $proc$libresoc.v:64237$3552
+ attribute \src "libresoc.v:64062.3-64083.6"
+ process $proc$libresoc.v:64062$3536
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64238.5-64238.29"
+ attribute \src "libresoc.v:64063.5-64063.29"
switch \initial
- attribute \src "libresoc.v:64238.9-64238.17"
+ attribute \src "libresoc.v:64063.9-64063.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0]
end
- connect \$1 $ternary$libresoc.v:63988$3541_Y
+ connect \$1 $ternary$libresoc.v:63813$3525_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \SHIFT_ROT_dec30_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:64600.1-67109.10"
+attribute \src "libresoc.v:64425.1-66934.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec"
attribute \generator "nMigen"
module \dec$166
- attribute \src "libresoc.v:66191.3-66248.6"
+ attribute \src "libresoc.v:66016.3-66073.6"
wire $0\LDST_br[0:0]
- attribute \src "libresoc.v:66655.3-66712.6"
+ attribute \src "libresoc.v:66480.3-66537.6"
wire width 3 $0\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66713.3-66770.6"
+ attribute \src "libresoc.v:66538.3-66595.6"
wire width 3 $0\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66423.3-66480.6"
+ attribute \src "libresoc.v:66248.3-66305.6"
wire width 14 $0\LDST_function_unit[13:0]
- attribute \src "libresoc.v:66539.3-66596.6"
+ attribute \src "libresoc.v:66364.3-66421.6"
wire width 3 $0\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66597.3-66654.6"
+ attribute \src "libresoc.v:66422.3-66479.6"
wire width 4 $0\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66481.3-66538.6"
+ attribute \src "libresoc.v:66306.3-66363.6"
wire width 7 $0\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66307.3-66364.6"
+ attribute \src "libresoc.v:66132.3-66189.6"
wire $0\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66017.3-66074.6"
+ attribute \src "libresoc.v:65842.3-65899.6"
wire width 4 $0\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66133.3-66190.6"
+ attribute \src "libresoc.v:65958.3-66015.6"
wire width 2 $0\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66365.3-66422.6"
+ attribute \src "libresoc.v:66190.3-66247.6"
wire $0\LDST_sgn[0:0]
- attribute \src "libresoc.v:66249.3-66306.6"
+ attribute \src "libresoc.v:66074.3-66131.6"
wire $0\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66075.3-66132.6"
+ attribute \src "libresoc.v:65900.3-65957.6"
wire width 2 $0\LDST_upd[1:0]
- attribute \src "libresoc.v:64601.7-64601.20"
+ attribute \src "libresoc.v:64426.7-64426.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:66191.3-66248.6"
+ attribute \src "libresoc.v:66016.3-66073.6"
wire $1\LDST_br[0:0]
- attribute \src "libresoc.v:66655.3-66712.6"
+ attribute \src "libresoc.v:66480.3-66537.6"
wire width 3 $1\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66713.3-66770.6"
+ attribute \src "libresoc.v:66538.3-66595.6"
wire width 3 $1\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66423.3-66480.6"
+ attribute \src "libresoc.v:66248.3-66305.6"
wire width 14 $1\LDST_function_unit[13:0]
- attribute \src "libresoc.v:66539.3-66596.6"
+ attribute \src "libresoc.v:66364.3-66421.6"
wire width 3 $1\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66597.3-66654.6"
+ attribute \src "libresoc.v:66422.3-66479.6"
wire width 4 $1\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66481.3-66538.6"
+ attribute \src "libresoc.v:66306.3-66363.6"
wire width 7 $1\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66307.3-66364.6"
+ attribute \src "libresoc.v:66132.3-66189.6"
wire $1\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66017.3-66074.6"
+ attribute \src "libresoc.v:65842.3-65899.6"
wire width 4 $1\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66133.3-66190.6"
+ attribute \src "libresoc.v:65958.3-66015.6"
wire width 2 $1\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66365.3-66422.6"
+ attribute \src "libresoc.v:66190.3-66247.6"
wire $1\LDST_sgn[0:0]
- attribute \src "libresoc.v:66249.3-66306.6"
+ attribute \src "libresoc.v:66074.3-66131.6"
wire $1\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66075.3-66132.6"
+ attribute \src "libresoc.v:65900.3-65957.6"
wire width 2 $1\LDST_upd[1:0]
- attribute \src "libresoc.v:65968.17-65968.211"
- wire width 32 $ternary$libresoc.v:65968$3554_Y
+ attribute \src "libresoc.v:65793.17-65793.211"
+ wire width 32 $ternary$libresoc.v:65793$3538_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "libresoc.v:64601.7-64601.15"
+ attribute \src "libresoc.v:64426.7-64426.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 26 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:65968$3554
+ cell $mux $ternary$libresoc.v:65793$3538
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:65968$3554_Y
+ connect \Y $ternary$libresoc.v:65793$3538_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:65969.14-65984.4"
+ attribute \src "libresoc.v:65794.14-65809.4"
cell \LDST_dec31 \LDST_dec31
connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br
connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in
connect \opcode_in \LDST_dec31_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:65985.14-66000.4"
+ attribute \src "libresoc.v:65810.14-65825.4"
cell \LDST_dec58 \LDST_dec58
connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br
connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in
connect \opcode_in \LDST_dec58_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:66001.14-66016.4"
+ attribute \src "libresoc.v:65826.14-65841.4"
cell \LDST_dec62 \LDST_dec62
connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br
connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in
connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd
connect \opcode_in \LDST_dec62_opcode_in
end
- attribute \src "libresoc.v:64601.7-64601.20"
- process $proc$libresoc.v:64601$3568
+ attribute \src "libresoc.v:64426.7-64426.20"
+ process $proc$libresoc.v:64426$3552
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:66017.3-66074.6"
- process $proc$libresoc.v:66017$3555
+ attribute \src "libresoc.v:65842.3-65899.6"
+ process $proc$libresoc.v:65842$3539
assign { } { }
assign { } { }
assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66018.5-66018.29"
+ attribute \src "libresoc.v:65843.5-65843.29"
switch \initial
- attribute \src "libresoc.v:66018.9-66018.17"
+ attribute \src "libresoc.v:65843.9-65843.17"
case 1'1
case
end
sync always
update \LDST_ldst_len $0\LDST_ldst_len[3:0]
end
- attribute \src "libresoc.v:66075.3-66132.6"
- process $proc$libresoc.v:66075$3556
+ attribute \src "libresoc.v:65900.3-65957.6"
+ process $proc$libresoc.v:65900$3540
assign { } { }
assign { } { }
assign $0\LDST_upd[1:0] $1\LDST_upd[1:0]
- attribute \src "libresoc.v:66076.5-66076.29"
+ attribute \src "libresoc.v:65901.5-65901.29"
switch \initial
- attribute \src "libresoc.v:66076.9-66076.17"
+ attribute \src "libresoc.v:65901.9-65901.17"
case 1'1
case
end
sync always
update \LDST_upd $0\LDST_upd[1:0]
end
- attribute \src "libresoc.v:66133.3-66190.6"
- process $proc$libresoc.v:66133$3557
+ attribute \src "libresoc.v:65958.3-66015.6"
+ process $proc$libresoc.v:65958$3541
assign { } { }
assign { } { }
assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66134.5-66134.29"
+ attribute \src "libresoc.v:65959.5-65959.29"
switch \initial
- attribute \src "libresoc.v:66134.9-66134.17"
+ attribute \src "libresoc.v:65959.9-65959.17"
case 1'1
case
end
sync always
update \LDST_rc_sel $0\LDST_rc_sel[1:0]
end
- attribute \src "libresoc.v:66191.3-66248.6"
- process $proc$libresoc.v:66191$3558
+ attribute \src "libresoc.v:66016.3-66073.6"
+ process $proc$libresoc.v:66016$3542
assign { } { }
assign { } { }
assign $0\LDST_br[0:0] $1\LDST_br[0:0]
- attribute \src "libresoc.v:66192.5-66192.29"
+ attribute \src "libresoc.v:66017.5-66017.29"
switch \initial
- attribute \src "libresoc.v:66192.9-66192.17"
+ attribute \src "libresoc.v:66017.9-66017.17"
case 1'1
case
end
sync always
update \LDST_br $0\LDST_br[0:0]
end
- attribute \src "libresoc.v:66249.3-66306.6"
- process $proc$libresoc.v:66249$3559
+ attribute \src "libresoc.v:66074.3-66131.6"
+ process $proc$libresoc.v:66074$3543
assign { } { }
assign { } { }
assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66250.5-66250.29"
+ attribute \src "libresoc.v:66075.5-66075.29"
switch \initial
- attribute \src "libresoc.v:66250.9-66250.17"
+ attribute \src "libresoc.v:66075.9-66075.17"
case 1'1
case
end
sync always
update \LDST_sgn_ext $0\LDST_sgn_ext[0:0]
end
- attribute \src "libresoc.v:66307.3-66364.6"
- process $proc$libresoc.v:66307$3560
+ attribute \src "libresoc.v:66132.3-66189.6"
+ process $proc$libresoc.v:66132$3544
assign { } { }
assign { } { }
assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66308.5-66308.29"
+ attribute \src "libresoc.v:66133.5-66133.29"
switch \initial
- attribute \src "libresoc.v:66308.9-66308.17"
+ attribute \src "libresoc.v:66133.9-66133.17"
case 1'1
case
end
sync always
update \LDST_is_32b $0\LDST_is_32b[0:0]
end
- attribute \src "libresoc.v:66365.3-66422.6"
- process $proc$libresoc.v:66365$3561
+ attribute \src "libresoc.v:66190.3-66247.6"
+ process $proc$libresoc.v:66190$3545
assign { } { }
assign { } { }
assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0]
- attribute \src "libresoc.v:66366.5-66366.29"
+ attribute \src "libresoc.v:66191.5-66191.29"
switch \initial
- attribute \src "libresoc.v:66366.9-66366.17"
+ attribute \src "libresoc.v:66191.9-66191.17"
case 1'1
case
end
sync always
update \LDST_sgn $0\LDST_sgn[0:0]
end
- attribute \src "libresoc.v:66423.3-66480.6"
- process $proc$libresoc.v:66423$3562
+ attribute \src "libresoc.v:66248.3-66305.6"
+ process $proc$libresoc.v:66248$3546
assign { } { }
assign { } { }
assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0]
- attribute \src "libresoc.v:66424.5-66424.29"
+ attribute \src "libresoc.v:66249.5-66249.29"
switch \initial
- attribute \src "libresoc.v:66424.9-66424.17"
+ attribute \src "libresoc.v:66249.9-66249.17"
case 1'1
case
end
sync always
update \LDST_function_unit $0\LDST_function_unit[13:0]
end
- attribute \src "libresoc.v:66481.3-66538.6"
- process $proc$libresoc.v:66481$3563
+ attribute \src "libresoc.v:66306.3-66363.6"
+ process $proc$libresoc.v:66306$3547
assign { } { }
assign { } { }
assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66482.5-66482.29"
+ attribute \src "libresoc.v:66307.5-66307.29"
switch \initial
- attribute \src "libresoc.v:66482.9-66482.17"
+ attribute \src "libresoc.v:66307.9-66307.17"
case 1'1
case
end
sync always
update \LDST_internal_op $0\LDST_internal_op[6:0]
end
- attribute \src "libresoc.v:66539.3-66596.6"
- process $proc$libresoc.v:66539$3564
+ attribute \src "libresoc.v:66364.3-66421.6"
+ process $proc$libresoc.v:66364$3548
assign { } { }
assign { } { }
assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66540.5-66540.29"
+ attribute \src "libresoc.v:66365.5-66365.29"
switch \initial
- attribute \src "libresoc.v:66540.9-66540.17"
+ attribute \src "libresoc.v:66365.9-66365.17"
case 1'1
case
end
sync always
update \LDST_in1_sel $0\LDST_in1_sel[2:0]
end
- attribute \src "libresoc.v:66597.3-66654.6"
- process $proc$libresoc.v:66597$3565
+ attribute \src "libresoc.v:66422.3-66479.6"
+ process $proc$libresoc.v:66422$3549
assign { } { }
assign { } { }
assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66598.5-66598.29"
+ attribute \src "libresoc.v:66423.5-66423.29"
switch \initial
- attribute \src "libresoc.v:66598.9-66598.17"
+ attribute \src "libresoc.v:66423.9-66423.17"
case 1'1
case
end
sync always
update \LDST_in2_sel $0\LDST_in2_sel[3:0]
end
- attribute \src "libresoc.v:66655.3-66712.6"
- process $proc$libresoc.v:66655$3566
+ attribute \src "libresoc.v:66480.3-66537.6"
+ process $proc$libresoc.v:66480$3550
assign { } { }
assign { } { }
assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66656.5-66656.29"
+ attribute \src "libresoc.v:66481.5-66481.29"
switch \initial
- attribute \src "libresoc.v:66656.9-66656.17"
+ attribute \src "libresoc.v:66481.9-66481.17"
case 1'1
case
end
sync always
update \LDST_cr_in $0\LDST_cr_in[2:0]
end
- attribute \src "libresoc.v:66713.3-66770.6"
- process $proc$libresoc.v:66713$3567
+ attribute \src "libresoc.v:66538.3-66595.6"
+ process $proc$libresoc.v:66538$3551
assign { } { }
assign { } { }
assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66714.5-66714.29"
+ attribute \src "libresoc.v:66539.5-66539.29"
switch \initial
- attribute \src "libresoc.v:66714.9-66714.17"
+ attribute \src "libresoc.v:66539.9-66539.17"
case 1'1
case
end
sync always
update \LDST_cr_out $0\LDST_cr_out[2:0]
end
- connect \$1 $ternary$libresoc.v:65968$3554_Y
+ connect \$1 $ternary$libresoc.v:65793$3538_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \LDST_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:67113.1-75333.10"
+attribute \src "libresoc.v:66938.1-75158.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec"
attribute \generator "nMigen"
module \dec$171
- attribute \src "libresoc.v:70496.3-70640.6"
+ attribute \src "libresoc.v:70321.3-70465.6"
wire width 2 $0\SV_Etype[1:0]
- attribute \src "libresoc.v:70641.3-70785.6"
+ attribute \src "libresoc.v:70466.3-70610.6"
wire width 2 $0\SV_Ptype[1:0]
- attribute \src "libresoc.v:70351.3-70495.6"
+ attribute \src "libresoc.v:70176.3-70320.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:73686.3-73830.6"
+ attribute \src "libresoc.v:73511.3-73655.6"
wire $0\br[0:0]
- attribute \src "libresoc.v:71366.3-71510.6"
+ attribute \src "libresoc.v:71191.3-71335.6"
wire width 3 $0\cr_in[2:0]
- attribute \src "libresoc.v:71511.3-71655.6"
+ attribute \src "libresoc.v:71336.3-71480.6"
wire width 3 $0\cr_out[2:0]
- attribute \src "libresoc.v:73106.3-73250.6"
+ attribute \src "libresoc.v:72931.3-73075.6"
wire width 2 $0\cry_in[1:0]
- attribute \src "libresoc.v:73541.3-73685.6"
+ attribute \src "libresoc.v:73366.3-73510.6"
wire $0\cry_out[0:0]
- attribute \src "libresoc.v:70206.3-70350.6"
+ attribute \src "libresoc.v:70031.3-70175.6"
wire width 5 $0\form[4:0]
- attribute \src "libresoc.v:74701.3-74845.6"
+ attribute \src "libresoc.v:74526.3-74670.6"
wire width 14 $0\function_unit[13:0]
- attribute \src "libresoc.v:70786.3-70930.6"
+ attribute \src "libresoc.v:70611.3-70755.6"
wire width 3 $0\in1_sel[2:0]
- attribute \src "libresoc.v:70931.3-71075.6"
+ attribute \src "libresoc.v:70756.3-70900.6"
wire width 4 $0\in2_sel[3:0]
- attribute \src "libresoc.v:71076.3-71220.6"
+ attribute \src "libresoc.v:70901.3-71045.6"
wire width 2 $0\in3_sel[1:0]
- attribute \src "libresoc.v:67114.7-67114.20"
+ attribute \src "libresoc.v:66939.7-66939.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:74846.3-74990.6"
+ attribute \src "libresoc.v:74671.3-74815.6"
wire width 7 $0\internal_op[6:0]
- attribute \src "libresoc.v:73251.3-73395.6"
+ attribute \src "libresoc.v:73076.3-73220.6"
wire $0\inv_a[0:0]
- attribute \src "libresoc.v:73396.3-73540.6"
+ attribute \src "libresoc.v:73221.3-73365.6"
wire $0\inv_out[0:0]
- attribute \src "libresoc.v:74121.3-74265.6"
+ attribute \src "libresoc.v:73946.3-74090.6"
wire $0\is_32b[0:0]
- attribute \src "libresoc.v:72671.3-72815.6"
+ attribute \src "libresoc.v:72496.3-72640.6"
wire width 4 $0\ldst_len[3:0]
- attribute \src "libresoc.v:74411.3-74555.6"
+ attribute \src "libresoc.v:74236.3-74380.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:71221.3-71365.6"
+ attribute \src "libresoc.v:71046.3-71190.6"
wire width 3 $0\out_sel[2:0]
- attribute \src "libresoc.v:72961.3-73105.6"
+ attribute \src "libresoc.v:72786.3-72930.6"
wire width 2 $0\rc_sel[1:0]
- attribute \src "libresoc.v:73976.3-74120.6"
+ attribute \src "libresoc.v:73801.3-73945.6"
wire $0\rsrv[0:0]
- attribute \src "libresoc.v:74556.3-74700.6"
+ attribute \src "libresoc.v:74381.3-74525.6"
wire $0\sgl_pipe[0:0]
- attribute \src "libresoc.v:74266.3-74410.6"
+ attribute \src "libresoc.v:74091.3-74235.6"
wire $0\sgn[0:0]
- attribute \src "libresoc.v:73831.3-73975.6"
+ attribute \src "libresoc.v:73656.3-73800.6"
wire $0\sgn_ext[0:0]
- attribute \src "libresoc.v:72381.3-72525.6"
+ attribute \src "libresoc.v:72206.3-72350.6"
wire width 3 $0\sv_cr_in[2:0]
- attribute \src "libresoc.v:72526.3-72670.6"
+ attribute \src "libresoc.v:72351.3-72495.6"
wire width 3 $0\sv_cr_out[2:0]
- attribute \src "libresoc.v:71656.3-71800.6"
+ attribute \src "libresoc.v:71481.3-71625.6"
wire width 3 $0\sv_in1[2:0]
- attribute \src "libresoc.v:71801.3-71945.6"
+ attribute \src "libresoc.v:71626.3-71770.6"
wire width 3 $0\sv_in2[2:0]
- attribute \src "libresoc.v:71946.3-72090.6"
+ attribute \src "libresoc.v:71771.3-71915.6"
wire width 3 $0\sv_in3[2:0]
- attribute \src "libresoc.v:72236.3-72380.6"
+ attribute \src "libresoc.v:72061.3-72205.6"
wire width 3 $0\sv_out2[2:0]
- attribute \src "libresoc.v:72091.3-72235.6"
+ attribute \src "libresoc.v:71916.3-72060.6"
wire width 3 $0\sv_out[2:0]
- attribute \src "libresoc.v:72816.3-72960.6"
+ attribute \src "libresoc.v:72641.3-72785.6"
wire width 2 $0\upd[1:0]
- attribute \src "libresoc.v:70496.3-70640.6"
+ attribute \src "libresoc.v:70321.3-70465.6"
wire width 2 $1\SV_Etype[1:0]
- attribute \src "libresoc.v:70641.3-70785.6"
+ attribute \src "libresoc.v:70466.3-70610.6"
wire width 2 $1\SV_Ptype[1:0]
- attribute \src "libresoc.v:70351.3-70495.6"
+ attribute \src "libresoc.v:70176.3-70320.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:73686.3-73830.6"
+ attribute \src "libresoc.v:73511.3-73655.6"
wire $1\br[0:0]
- attribute \src "libresoc.v:71366.3-71510.6"
+ attribute \src "libresoc.v:71191.3-71335.6"
wire width 3 $1\cr_in[2:0]
- attribute \src "libresoc.v:71511.3-71655.6"
+ attribute \src "libresoc.v:71336.3-71480.6"
wire width 3 $1\cr_out[2:0]
- attribute \src "libresoc.v:73106.3-73250.6"
+ attribute \src "libresoc.v:72931.3-73075.6"
wire width 2 $1\cry_in[1:0]
- attribute \src "libresoc.v:73541.3-73685.6"
+ attribute \src "libresoc.v:73366.3-73510.6"
wire $1\cry_out[0:0]
- attribute \src "libresoc.v:70206.3-70350.6"
+ attribute \src "libresoc.v:70031.3-70175.6"
wire width 5 $1\form[4:0]
- attribute \src "libresoc.v:74701.3-74845.6"
+ attribute \src "libresoc.v:74526.3-74670.6"
wire width 14 $1\function_unit[13:0]
- attribute \src "libresoc.v:70786.3-70930.6"
+ attribute \src "libresoc.v:70611.3-70755.6"
wire width 3 $1\in1_sel[2:0]
- attribute \src "libresoc.v:70931.3-71075.6"
+ attribute \src "libresoc.v:70756.3-70900.6"
wire width 4 $1\in2_sel[3:0]
- attribute \src "libresoc.v:71076.3-71220.6"
+ attribute \src "libresoc.v:70901.3-71045.6"
wire width 2 $1\in3_sel[1:0]
- attribute \src "libresoc.v:74846.3-74990.6"
+ attribute \src "libresoc.v:74671.3-74815.6"
wire width 7 $1\internal_op[6:0]
- attribute \src "libresoc.v:73251.3-73395.6"
+ attribute \src "libresoc.v:73076.3-73220.6"
wire $1\inv_a[0:0]
- attribute \src "libresoc.v:73396.3-73540.6"
+ attribute \src "libresoc.v:73221.3-73365.6"
wire $1\inv_out[0:0]
- attribute \src "libresoc.v:74121.3-74265.6"
+ attribute \src "libresoc.v:73946.3-74090.6"
wire $1\is_32b[0:0]
- attribute \src "libresoc.v:72671.3-72815.6"
+ attribute \src "libresoc.v:72496.3-72640.6"
wire width 4 $1\ldst_len[3:0]
- attribute \src "libresoc.v:74411.3-74555.6"
+ attribute \src "libresoc.v:74236.3-74380.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:71221.3-71365.6"
+ attribute \src "libresoc.v:71046.3-71190.6"
wire width 3 $1\out_sel[2:0]
- attribute \src "libresoc.v:72961.3-73105.6"
+ attribute \src "libresoc.v:72786.3-72930.6"
wire width 2 $1\rc_sel[1:0]
- attribute \src "libresoc.v:73976.3-74120.6"
+ attribute \src "libresoc.v:73801.3-73945.6"
wire $1\rsrv[0:0]
- attribute \src "libresoc.v:74556.3-74700.6"
+ attribute \src "libresoc.v:74381.3-74525.6"
wire $1\sgl_pipe[0:0]
- attribute \src "libresoc.v:74266.3-74410.6"
+ attribute \src "libresoc.v:74091.3-74235.6"
wire $1\sgn[0:0]
- attribute \src "libresoc.v:73831.3-73975.6"
+ attribute \src "libresoc.v:73656.3-73800.6"
wire $1\sgn_ext[0:0]
- attribute \src "libresoc.v:72381.3-72525.6"
+ attribute \src "libresoc.v:72206.3-72350.6"
wire width 3 $1\sv_cr_in[2:0]
- attribute \src "libresoc.v:72526.3-72670.6"
+ attribute \src "libresoc.v:72351.3-72495.6"
wire width 3 $1\sv_cr_out[2:0]
- attribute \src "libresoc.v:71656.3-71800.6"
+ attribute \src "libresoc.v:71481.3-71625.6"
wire width 3 $1\sv_in1[2:0]
- attribute \src "libresoc.v:71801.3-71945.6"
+ attribute \src "libresoc.v:71626.3-71770.6"
wire width 3 $1\sv_in2[2:0]
- attribute \src "libresoc.v:71946.3-72090.6"
+ attribute \src "libresoc.v:71771.3-71915.6"
wire width 3 $1\sv_in3[2:0]
- attribute \src "libresoc.v:72236.3-72380.6"
+ attribute \src "libresoc.v:72061.3-72205.6"
wire width 3 $1\sv_out2[2:0]
- attribute \src "libresoc.v:72091.3-72235.6"
+ attribute \src "libresoc.v:71916.3-72060.6"
wire width 3 $1\sv_out[2:0]
- attribute \src "libresoc.v:72816.3-72960.6"
+ attribute \src "libresoc.v:72641.3-72785.6"
wire width 2 $1\upd[1:0]
- attribute \src "libresoc.v:70496.3-70640.6"
+ attribute \src "libresoc.v:70321.3-70465.6"
wire width 2 $2\SV_Etype[1:0]
- attribute \src "libresoc.v:70641.3-70785.6"
+ attribute \src "libresoc.v:70466.3-70610.6"
wire width 2 $2\SV_Ptype[1:0]
- attribute \src "libresoc.v:70351.3-70495.6"
+ attribute \src "libresoc.v:70176.3-70320.6"
wire width 8 $2\asmcode[7:0]
- attribute \src "libresoc.v:73686.3-73830.6"
+ attribute \src "libresoc.v:73511.3-73655.6"
wire $2\br[0:0]
- attribute \src "libresoc.v:71366.3-71510.6"
+ attribute \src "libresoc.v:71191.3-71335.6"
wire width 3 $2\cr_in[2:0]
- attribute \src "libresoc.v:71511.3-71655.6"
+ attribute \src "libresoc.v:71336.3-71480.6"
wire width 3 $2\cr_out[2:0]
- attribute \src "libresoc.v:73106.3-73250.6"
+ attribute \src "libresoc.v:72931.3-73075.6"
wire width 2 $2\cry_in[1:0]
- attribute \src "libresoc.v:73541.3-73685.6"
+ attribute \src "libresoc.v:73366.3-73510.6"
wire $2\cry_out[0:0]
- attribute \src "libresoc.v:70206.3-70350.6"
+ attribute \src "libresoc.v:70031.3-70175.6"
wire width 5 $2\form[4:0]
- attribute \src "libresoc.v:74701.3-74845.6"
+ attribute \src "libresoc.v:74526.3-74670.6"
wire width 14 $2\function_unit[13:0]
- attribute \src "libresoc.v:70786.3-70930.6"
+ attribute \src "libresoc.v:70611.3-70755.6"
wire width 3 $2\in1_sel[2:0]
- attribute \src "libresoc.v:70931.3-71075.6"
+ attribute \src "libresoc.v:70756.3-70900.6"
wire width 4 $2\in2_sel[3:0]
- attribute \src "libresoc.v:71076.3-71220.6"
+ attribute \src "libresoc.v:70901.3-71045.6"
wire width 2 $2\in3_sel[1:0]
- attribute \src "libresoc.v:74846.3-74990.6"
+ attribute \src "libresoc.v:74671.3-74815.6"
wire width 7 $2\internal_op[6:0]
- attribute \src "libresoc.v:73251.3-73395.6"
+ attribute \src "libresoc.v:73076.3-73220.6"
wire $2\inv_a[0:0]
- attribute \src "libresoc.v:73396.3-73540.6"
+ attribute \src "libresoc.v:73221.3-73365.6"
wire $2\inv_out[0:0]
- attribute \src "libresoc.v:74121.3-74265.6"
+ attribute \src "libresoc.v:73946.3-74090.6"
wire $2\is_32b[0:0]
- attribute \src "libresoc.v:72671.3-72815.6"
+ attribute \src "libresoc.v:72496.3-72640.6"
wire width 4 $2\ldst_len[3:0]
- attribute \src "libresoc.v:74411.3-74555.6"
+ attribute \src "libresoc.v:74236.3-74380.6"
wire $2\lk[0:0]
- attribute \src "libresoc.v:71221.3-71365.6"
+ attribute \src "libresoc.v:71046.3-71190.6"
wire width 3 $2\out_sel[2:0]
- attribute \src "libresoc.v:72961.3-73105.6"
+ attribute \src "libresoc.v:72786.3-72930.6"
wire width 2 $2\rc_sel[1:0]
- attribute \src "libresoc.v:73976.3-74120.6"
+ attribute \src "libresoc.v:73801.3-73945.6"
wire $2\rsrv[0:0]
- attribute \src "libresoc.v:74556.3-74700.6"
+ attribute \src "libresoc.v:74381.3-74525.6"
wire $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:74266.3-74410.6"
+ attribute \src "libresoc.v:74091.3-74235.6"
wire $2\sgn[0:0]
- attribute \src "libresoc.v:73831.3-73975.6"
+ attribute \src "libresoc.v:73656.3-73800.6"
wire $2\sgn_ext[0:0]
- attribute \src "libresoc.v:72381.3-72525.6"
+ attribute \src "libresoc.v:72206.3-72350.6"
wire width 3 $2\sv_cr_in[2:0]
- attribute \src "libresoc.v:72526.3-72670.6"
+ attribute \src "libresoc.v:72351.3-72495.6"
wire width 3 $2\sv_cr_out[2:0]
- attribute \src "libresoc.v:71656.3-71800.6"
+ attribute \src "libresoc.v:71481.3-71625.6"
wire width 3 $2\sv_in1[2:0]
- attribute \src "libresoc.v:71801.3-71945.6"
+ attribute \src "libresoc.v:71626.3-71770.6"
wire width 3 $2\sv_in2[2:0]
- attribute \src "libresoc.v:71946.3-72090.6"
+ attribute \src "libresoc.v:71771.3-71915.6"
wire width 3 $2\sv_in3[2:0]
- attribute \src "libresoc.v:72236.3-72380.6"
+ attribute \src "libresoc.v:72061.3-72205.6"
wire width 3 $2\sv_out2[2:0]
- attribute \src "libresoc.v:72091.3-72235.6"
+ attribute \src "libresoc.v:71916.3-72060.6"
wire width 3 $2\sv_out[2:0]
- attribute \src "libresoc.v:72816.3-72960.6"
+ attribute \src "libresoc.v:72641.3-72785.6"
wire width 2 $2\upd[1:0]
- attribute \src "libresoc.v:69989.17-69989.211"
- wire width 32 $ternary$libresoc.v:69989$3569_Y
+ attribute \src "libresoc.v:69814.17-69814.211"
+ wire width 32 $ternary$libresoc.v:69814$3553_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
wire width 32 \$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 15 \in3_sel
- attribute \src "libresoc.v:67114.7-67114.15"
+ attribute \src "libresoc.v:66939.7-66939.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 18 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506"
- cell $mux $ternary$libresoc.v:69989$3569
+ cell $mux $ternary$libresoc.v:69814$3553
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:69989$3569_Y
+ connect \Y $ternary$libresoc.v:69814$3553_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69990.9-70025.4"
+ attribute \src "libresoc.v:69815.9-69850.4"
cell \dec19 \dec19
connect \dec19_SV_Etype \dec19_dec19_SV_Etype
connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype
connect \opcode_in \dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:70026.9-70061.4"
+ attribute \src "libresoc.v:69851.9-69886.4"
cell \dec22 \dec22
connect \dec22_SV_Etype \dec22_dec22_SV_Etype
connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype
connect \opcode_in \dec22_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:70062.9-70097.4"
+ attribute \src "libresoc.v:69887.9-69922.4"
cell \dec30 \dec30
connect \dec30_SV_Etype \dec30_dec30_SV_Etype
connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype
connect \opcode_in \dec30_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:70098.9-70133.4"
+ attribute \src "libresoc.v:69923.9-69958.4"
cell \dec31 \dec31
connect \dec31_SV_Etype \dec31_dec31_SV_Etype
connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype
connect \opcode_in \dec31_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:70134.9-70169.4"
+ attribute \src "libresoc.v:69959.9-69994.4"
cell \dec58 \dec58
connect \dec58_SV_Etype \dec58_dec58_SV_Etype
connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype
connect \opcode_in \dec58_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:70170.9-70205.4"
+ attribute \src "libresoc.v:69995.9-70030.4"
cell \dec62 \dec62
connect \dec62_SV_Etype \dec62_dec62_SV_Etype
connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype
connect \dec62_upd \dec62_dec62_upd
connect \opcode_in \dec62_opcode_in
end
- attribute \src "libresoc.v:67114.7-67114.20"
- process $proc$libresoc.v:67114$3603
+ attribute \src "libresoc.v:66939.7-66939.20"
+ process $proc$libresoc.v:66939$3587
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:70206.3-70350.6"
- process $proc$libresoc.v:70206$3570
+ attribute \src "libresoc.v:70031.3-70175.6"
+ process $proc$libresoc.v:70031$3554
assign { } { }
assign { } { }
assign { } { }
assign $0\form[4:0] $2\form[4:0]
- attribute \src "libresoc.v:70207.5-70207.29"
+ attribute \src "libresoc.v:70032.5-70032.29"
switch \initial
- attribute \src "libresoc.v:70207.9-70207.17"
+ attribute \src "libresoc.v:70032.9-70032.17"
case 1'1
case
end
sync always
update \form $0\form[4:0]
end
- attribute \src "libresoc.v:70351.3-70495.6"
- process $proc$libresoc.v:70351$3571
+ attribute \src "libresoc.v:70176.3-70320.6"
+ process $proc$libresoc.v:70176$3555
assign { } { }
assign { } { }
assign { } { }
assign $0\asmcode[7:0] $2\asmcode[7:0]
- attribute \src "libresoc.v:70352.5-70352.29"
+ attribute \src "libresoc.v:70177.5-70177.29"
switch \initial
- attribute \src "libresoc.v:70352.9-70352.17"
+ attribute \src "libresoc.v:70177.9-70177.17"
case 1'1
case
end
sync always
update \asmcode $0\asmcode[7:0]
end
- attribute \src "libresoc.v:70496.3-70640.6"
- process $proc$libresoc.v:70496$3572
+ attribute \src "libresoc.v:70321.3-70465.6"
+ process $proc$libresoc.v:70321$3556
assign { } { }
assign { } { }
assign { } { }
assign $0\SV_Etype[1:0] $2\SV_Etype[1:0]
- attribute \src "libresoc.v:70497.5-70497.29"
+ attribute \src "libresoc.v:70322.5-70322.29"
switch \initial
- attribute \src "libresoc.v:70497.9-70497.17"
+ attribute \src "libresoc.v:70322.9-70322.17"
case 1'1
case
end
sync always
update \SV_Etype $0\SV_Etype[1:0]
end
- attribute \src "libresoc.v:70641.3-70785.6"
- process $proc$libresoc.v:70641$3573
+ attribute \src "libresoc.v:70466.3-70610.6"
+ process $proc$libresoc.v:70466$3557
assign { } { }
assign { } { }
assign { } { }
assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0]
- attribute \src "libresoc.v:70642.5-70642.29"
+ attribute \src "libresoc.v:70467.5-70467.29"
switch \initial
- attribute \src "libresoc.v:70642.9-70642.17"
+ attribute \src "libresoc.v:70467.9-70467.17"
case 1'1
case
end
sync always
update \SV_Ptype $0\SV_Ptype[1:0]
end
- attribute \src "libresoc.v:70786.3-70930.6"
- process $proc$libresoc.v:70786$3574
+ attribute \src "libresoc.v:70611.3-70755.6"
+ process $proc$libresoc.v:70611$3558
assign { } { }
assign { } { }
assign { } { }
assign $0\in1_sel[2:0] $2\in1_sel[2:0]
- attribute \src "libresoc.v:70787.5-70787.29"
+ attribute \src "libresoc.v:70612.5-70612.29"
switch \initial
- attribute \src "libresoc.v:70787.9-70787.17"
+ attribute \src "libresoc.v:70612.9-70612.17"
case 1'1
case
end
sync always
update \in1_sel $0\in1_sel[2:0]
end
- attribute \src "libresoc.v:70931.3-71075.6"
- process $proc$libresoc.v:70931$3575
+ attribute \src "libresoc.v:70756.3-70900.6"
+ process $proc$libresoc.v:70756$3559
assign { } { }
assign { } { }
assign { } { }
assign $0\in2_sel[3:0] $2\in2_sel[3:0]
- attribute \src "libresoc.v:70932.5-70932.29"
+ attribute \src "libresoc.v:70757.5-70757.29"
switch \initial
- attribute \src "libresoc.v:70932.9-70932.17"
+ attribute \src "libresoc.v:70757.9-70757.17"
case 1'1
case
end
sync always
update \in2_sel $0\in2_sel[3:0]
end
- attribute \src "libresoc.v:71076.3-71220.6"
- process $proc$libresoc.v:71076$3576
+ attribute \src "libresoc.v:70901.3-71045.6"
+ process $proc$libresoc.v:70901$3560
assign { } { }
assign { } { }
assign { } { }
assign $0\in3_sel[1:0] $2\in3_sel[1:0]
- attribute \src "libresoc.v:71077.5-71077.29"
+ attribute \src "libresoc.v:70902.5-70902.29"
switch \initial
- attribute \src "libresoc.v:71077.9-71077.17"
+ attribute \src "libresoc.v:70902.9-70902.17"
case 1'1
case
end
sync always
update \in3_sel $0\in3_sel[1:0]
end
- attribute \src "libresoc.v:71221.3-71365.6"
- process $proc$libresoc.v:71221$3577
+ attribute \src "libresoc.v:71046.3-71190.6"
+ process $proc$libresoc.v:71046$3561
assign { } { }
assign { } { }
assign { } { }
assign $0\out_sel[2:0] $2\out_sel[2:0]
- attribute \src "libresoc.v:71222.5-71222.29"
+ attribute \src "libresoc.v:71047.5-71047.29"
switch \initial
- attribute \src "libresoc.v:71222.9-71222.17"
+ attribute \src "libresoc.v:71047.9-71047.17"
case 1'1
case
end
sync always
update \out_sel $0\out_sel[2:0]
end
- attribute \src "libresoc.v:71366.3-71510.6"
- process $proc$libresoc.v:71366$3578
+ attribute \src "libresoc.v:71191.3-71335.6"
+ process $proc$libresoc.v:71191$3562
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_in[2:0] $2\cr_in[2:0]
- attribute \src "libresoc.v:71367.5-71367.29"
+ attribute \src "libresoc.v:71192.5-71192.29"
switch \initial
- attribute \src "libresoc.v:71367.9-71367.17"
+ attribute \src "libresoc.v:71192.9-71192.17"
case 1'1
case
end
sync always
update \cr_in $0\cr_in[2:0]
end
- attribute \src "libresoc.v:71511.3-71655.6"
- process $proc$libresoc.v:71511$3579
+ attribute \src "libresoc.v:71336.3-71480.6"
+ process $proc$libresoc.v:71336$3563
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_out[2:0] $2\cr_out[2:0]
- attribute \src "libresoc.v:71512.5-71512.29"
+ attribute \src "libresoc.v:71337.5-71337.29"
switch \initial
- attribute \src "libresoc.v:71512.9-71512.17"
+ attribute \src "libresoc.v:71337.9-71337.17"
case 1'1
case
end
sync always
update \cr_out $0\cr_out[2:0]
end
- attribute \src "libresoc.v:71656.3-71800.6"
- process $proc$libresoc.v:71656$3580
+ attribute \src "libresoc.v:71481.3-71625.6"
+ process $proc$libresoc.v:71481$3564
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in1[2:0] $2\sv_in1[2:0]
- attribute \src "libresoc.v:71657.5-71657.29"
+ attribute \src "libresoc.v:71482.5-71482.29"
switch \initial
- attribute \src "libresoc.v:71657.9-71657.17"
+ attribute \src "libresoc.v:71482.9-71482.17"
case 1'1
case
end
sync always
update \sv_in1 $0\sv_in1[2:0]
end
- attribute \src "libresoc.v:71801.3-71945.6"
- process $proc$libresoc.v:71801$3581
+ attribute \src "libresoc.v:71626.3-71770.6"
+ process $proc$libresoc.v:71626$3565
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in2[2:0] $2\sv_in2[2:0]
- attribute \src "libresoc.v:71802.5-71802.29"
+ attribute \src "libresoc.v:71627.5-71627.29"
switch \initial
- attribute \src "libresoc.v:71802.9-71802.17"
+ attribute \src "libresoc.v:71627.9-71627.17"
case 1'1
case
end
sync always
update \sv_in2 $0\sv_in2[2:0]
end
- attribute \src "libresoc.v:71946.3-72090.6"
- process $proc$libresoc.v:71946$3582
+ attribute \src "libresoc.v:71771.3-71915.6"
+ process $proc$libresoc.v:71771$3566
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in3[2:0] $2\sv_in3[2:0]
- attribute \src "libresoc.v:71947.5-71947.29"
+ attribute \src "libresoc.v:71772.5-71772.29"
switch \initial
- attribute \src "libresoc.v:71947.9-71947.17"
+ attribute \src "libresoc.v:71772.9-71772.17"
case 1'1
case
end
sync always
update \sv_in3 $0\sv_in3[2:0]
end
- attribute \src "libresoc.v:72091.3-72235.6"
- process $proc$libresoc.v:72091$3583
+ attribute \src "libresoc.v:71916.3-72060.6"
+ process $proc$libresoc.v:71916$3567
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_out[2:0] $2\sv_out[2:0]
- attribute \src "libresoc.v:72092.5-72092.29"
+ attribute \src "libresoc.v:71917.5-71917.29"
switch \initial
- attribute \src "libresoc.v:72092.9-72092.17"
+ attribute \src "libresoc.v:71917.9-71917.17"
case 1'1
case
end
sync always
update \sv_out $0\sv_out[2:0]
end
- attribute \src "libresoc.v:72236.3-72380.6"
- process $proc$libresoc.v:72236$3584
+ attribute \src "libresoc.v:72061.3-72205.6"
+ process $proc$libresoc.v:72061$3568
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_out2[2:0] $2\sv_out2[2:0]
- attribute \src "libresoc.v:72237.5-72237.29"
+ attribute \src "libresoc.v:72062.5-72062.29"
switch \initial
- attribute \src "libresoc.v:72237.9-72237.17"
+ attribute \src "libresoc.v:72062.9-72062.17"
case 1'1
case
end
sync always
update \sv_out2 $0\sv_out2[2:0]
end
- attribute \src "libresoc.v:72381.3-72525.6"
- process $proc$libresoc.v:72381$3585
+ attribute \src "libresoc.v:72206.3-72350.6"
+ process $proc$libresoc.v:72206$3569
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0]
- attribute \src "libresoc.v:72382.5-72382.29"
+ attribute \src "libresoc.v:72207.5-72207.29"
switch \initial
- attribute \src "libresoc.v:72382.9-72382.17"
+ attribute \src "libresoc.v:72207.9-72207.17"
case 1'1
case
end
sync always
update \sv_cr_in $0\sv_cr_in[2:0]
end
- attribute \src "libresoc.v:72526.3-72670.6"
- process $proc$libresoc.v:72526$3586
+ attribute \src "libresoc.v:72351.3-72495.6"
+ process $proc$libresoc.v:72351$3570
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0]
- attribute \src "libresoc.v:72527.5-72527.29"
+ attribute \src "libresoc.v:72352.5-72352.29"
switch \initial
- attribute \src "libresoc.v:72527.9-72527.17"
+ attribute \src "libresoc.v:72352.9-72352.17"
case 1'1
case
end
sync always
update \sv_cr_out $0\sv_cr_out[2:0]
end
- attribute \src "libresoc.v:72671.3-72815.6"
- process $proc$libresoc.v:72671$3587
+ attribute \src "libresoc.v:72496.3-72640.6"
+ process $proc$libresoc.v:72496$3571
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_len[3:0] $2\ldst_len[3:0]
- attribute \src "libresoc.v:72672.5-72672.29"
+ attribute \src "libresoc.v:72497.5-72497.29"
switch \initial
- attribute \src "libresoc.v:72672.9-72672.17"
+ attribute \src "libresoc.v:72497.9-72497.17"
case 1'1
case
end
sync always
update \ldst_len $0\ldst_len[3:0]
end
- attribute \src "libresoc.v:72816.3-72960.6"
- process $proc$libresoc.v:72816$3588
+ attribute \src "libresoc.v:72641.3-72785.6"
+ process $proc$libresoc.v:72641$3572
assign { } { }
assign { } { }
assign { } { }
assign $0\upd[1:0] $2\upd[1:0]
- attribute \src "libresoc.v:72817.5-72817.29"
+ attribute \src "libresoc.v:72642.5-72642.29"
switch \initial
- attribute \src "libresoc.v:72817.9-72817.17"
+ attribute \src "libresoc.v:72642.9-72642.17"
case 1'1
case
end
sync always
update \upd $0\upd[1:0]
end
- attribute \src "libresoc.v:72961.3-73105.6"
- process $proc$libresoc.v:72961$3589
+ attribute \src "libresoc.v:72786.3-72930.6"
+ process $proc$libresoc.v:72786$3573
assign { } { }
assign { } { }
assign { } { }
assign $0\rc_sel[1:0] $2\rc_sel[1:0]
- attribute \src "libresoc.v:72962.5-72962.29"
+ attribute \src "libresoc.v:72787.5-72787.29"
switch \initial
- attribute \src "libresoc.v:72962.9-72962.17"
+ attribute \src "libresoc.v:72787.9-72787.17"
case 1'1
case
end
sync always
update \rc_sel $0\rc_sel[1:0]
end
- attribute \src "libresoc.v:73106.3-73250.6"
- process $proc$libresoc.v:73106$3590
+ attribute \src "libresoc.v:72931.3-73075.6"
+ process $proc$libresoc.v:72931$3574
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_in[1:0] $2\cry_in[1:0]
- attribute \src "libresoc.v:73107.5-73107.29"
+ attribute \src "libresoc.v:72932.5-72932.29"
switch \initial
- attribute \src "libresoc.v:73107.9-73107.17"
+ attribute \src "libresoc.v:72932.9-72932.17"
case 1'1
case
end
sync always
update \cry_in $0\cry_in[1:0]
end
- attribute \src "libresoc.v:73251.3-73395.6"
- process $proc$libresoc.v:73251$3591
+ attribute \src "libresoc.v:73076.3-73220.6"
+ process $proc$libresoc.v:73076$3575
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_a[0:0] $2\inv_a[0:0]
- attribute \src "libresoc.v:73252.5-73252.29"
+ attribute \src "libresoc.v:73077.5-73077.29"
switch \initial
- attribute \src "libresoc.v:73252.9-73252.17"
+ attribute \src "libresoc.v:73077.9-73077.17"
case 1'1
case
end
sync always
update \inv_a $0\inv_a[0:0]
end
- attribute \src "libresoc.v:73396.3-73540.6"
- process $proc$libresoc.v:73396$3592
+ attribute \src "libresoc.v:73221.3-73365.6"
+ process $proc$libresoc.v:73221$3576
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_out[0:0] $2\inv_out[0:0]
- attribute \src "libresoc.v:73397.5-73397.29"
+ attribute \src "libresoc.v:73222.5-73222.29"
switch \initial
- attribute \src "libresoc.v:73397.9-73397.17"
+ attribute \src "libresoc.v:73222.9-73222.17"
case 1'1
case
end
sync always
update \inv_out $0\inv_out[0:0]
end
- attribute \src "libresoc.v:73541.3-73685.6"
- process $proc$libresoc.v:73541$3593
+ attribute \src "libresoc.v:73366.3-73510.6"
+ process $proc$libresoc.v:73366$3577
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_out[0:0] $2\cry_out[0:0]
- attribute \src "libresoc.v:73542.5-73542.29"
+ attribute \src "libresoc.v:73367.5-73367.29"
switch \initial
- attribute \src "libresoc.v:73542.9-73542.17"
+ attribute \src "libresoc.v:73367.9-73367.17"
case 1'1
case
end
sync always
update \cry_out $0\cry_out[0:0]
end
- attribute \src "libresoc.v:73686.3-73830.6"
- process $proc$libresoc.v:73686$3594
+ attribute \src "libresoc.v:73511.3-73655.6"
+ process $proc$libresoc.v:73511$3578
assign { } { }
assign { } { }
assign { } { }
assign $0\br[0:0] $2\br[0:0]
- attribute \src "libresoc.v:73687.5-73687.29"
+ attribute \src "libresoc.v:73512.5-73512.29"
switch \initial
- attribute \src "libresoc.v:73687.9-73687.17"
+ attribute \src "libresoc.v:73512.9-73512.17"
case 1'1
case
end
sync always
update \br $0\br[0:0]
end
- attribute \src "libresoc.v:73831.3-73975.6"
- process $proc$libresoc.v:73831$3595
+ attribute \src "libresoc.v:73656.3-73800.6"
+ process $proc$libresoc.v:73656$3579
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn_ext[0:0] $2\sgn_ext[0:0]
- attribute \src "libresoc.v:73832.5-73832.29"
+ attribute \src "libresoc.v:73657.5-73657.29"
switch \initial
- attribute \src "libresoc.v:73832.9-73832.17"
+ attribute \src "libresoc.v:73657.9-73657.17"
case 1'1
case
end
sync always
update \sgn_ext $0\sgn_ext[0:0]
end
- attribute \src "libresoc.v:73976.3-74120.6"
- process $proc$libresoc.v:73976$3596
+ attribute \src "libresoc.v:73801.3-73945.6"
+ process $proc$libresoc.v:73801$3580
assign { } { }
assign { } { }
assign { } { }
assign $0\rsrv[0:0] $2\rsrv[0:0]
- attribute \src "libresoc.v:73977.5-73977.29"
+ attribute \src "libresoc.v:73802.5-73802.29"
switch \initial
- attribute \src "libresoc.v:73977.9-73977.17"
+ attribute \src "libresoc.v:73802.9-73802.17"
case 1'1
case
end
sync always
update \rsrv $0\rsrv[0:0]
end
- attribute \src "libresoc.v:74121.3-74265.6"
- process $proc$libresoc.v:74121$3597
+ attribute \src "libresoc.v:73946.3-74090.6"
+ process $proc$libresoc.v:73946$3581
assign { } { }
assign { } { }
assign { } { }
assign $0\is_32b[0:0] $2\is_32b[0:0]
- attribute \src "libresoc.v:74122.5-74122.29"
+ attribute \src "libresoc.v:73947.5-73947.29"
switch \initial
- attribute \src "libresoc.v:74122.9-74122.17"
+ attribute \src "libresoc.v:73947.9-73947.17"
case 1'1
case
end
sync always
update \is_32b $0\is_32b[0:0]
end
- attribute \src "libresoc.v:74266.3-74410.6"
- process $proc$libresoc.v:74266$3598
+ attribute \src "libresoc.v:74091.3-74235.6"
+ process $proc$libresoc.v:74091$3582
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn[0:0] $2\sgn[0:0]
- attribute \src "libresoc.v:74267.5-74267.29"
+ attribute \src "libresoc.v:74092.5-74092.29"
switch \initial
- attribute \src "libresoc.v:74267.9-74267.17"
+ attribute \src "libresoc.v:74092.9-74092.17"
case 1'1
case
end
sync always
update \sgn $0\sgn[0:0]
end
- attribute \src "libresoc.v:74411.3-74555.6"
- process $proc$libresoc.v:74411$3599
+ attribute \src "libresoc.v:74236.3-74380.6"
+ process $proc$libresoc.v:74236$3583
assign { } { }
assign { } { }
assign { } { }
assign $0\lk[0:0] $2\lk[0:0]
- attribute \src "libresoc.v:74412.5-74412.29"
+ attribute \src "libresoc.v:74237.5-74237.29"
switch \initial
- attribute \src "libresoc.v:74412.9-74412.17"
+ attribute \src "libresoc.v:74237.9-74237.17"
case 1'1
case
end
sync always
update \lk $0\lk[0:0]
end
- attribute \src "libresoc.v:74556.3-74700.6"
- process $proc$libresoc.v:74556$3600
+ attribute \src "libresoc.v:74381.3-74525.6"
+ process $proc$libresoc.v:74381$3584
assign { } { }
assign { } { }
assign { } { }
assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:74557.5-74557.29"
+ attribute \src "libresoc.v:74382.5-74382.29"
switch \initial
- attribute \src "libresoc.v:74557.9-74557.17"
+ attribute \src "libresoc.v:74382.9-74382.17"
case 1'1
case
end
sync always
update \sgl_pipe $0\sgl_pipe[0:0]
end
- attribute \src "libresoc.v:74701.3-74845.6"
- process $proc$libresoc.v:74701$3601
+ attribute \src "libresoc.v:74526.3-74670.6"
+ process $proc$libresoc.v:74526$3585
assign { } { }
assign { } { }
assign { } { }
assign $0\function_unit[13:0] $2\function_unit[13:0]
- attribute \src "libresoc.v:74702.5-74702.29"
+ attribute \src "libresoc.v:74527.5-74527.29"
switch \initial
- attribute \src "libresoc.v:74702.9-74702.17"
+ attribute \src "libresoc.v:74527.9-74527.17"
case 1'1
case
end
sync always
update \function_unit $0\function_unit[13:0]
end
- attribute \src "libresoc.v:74846.3-74990.6"
- process $proc$libresoc.v:74846$3602
+ attribute \src "libresoc.v:74671.3-74815.6"
+ process $proc$libresoc.v:74671$3586
assign { } { }
assign { } { }
assign { } { }
assign $0\internal_op[6:0] $2\internal_op[6:0]
- attribute \src "libresoc.v:74847.5-74847.29"
+ attribute \src "libresoc.v:74672.5-74672.29"
switch \initial
- attribute \src "libresoc.v:74847.9-74847.17"
+ attribute \src "libresoc.v:74672.9-74672.17"
case 1'1
case
end
sync always
update \internal_op $0\internal_op[6:0]
end
- connect \$2 $ternary$libresoc.v:69989$3569_Y
+ connect \$2 $ternary$libresoc.v:69814$3553_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:75337.1-77403.10"
+attribute \src "libresoc.v:75162.1-77228.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19"
attribute \generator "nMigen"
module \dec19
- attribute \src "libresoc.v:77090.3-77141.6"
+ attribute \src "libresoc.v:76915.3-76966.6"
wire width 2 $0\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:77142.3-77193.6"
+ attribute \src "libresoc.v:76967.3-77018.6"
wire width 2 $0\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:76466.3-76517.6"
+ attribute \src "libresoc.v:76291.3-76342.6"
wire width 8 $0\dec19_asmcode[7:0]
- attribute \src "libresoc.v:76674.3-76725.6"
+ attribute \src "libresoc.v:76499.3-76550.6"
wire $0\dec19_br[0:0]
- attribute \src "libresoc.v:75738.3-75789.6"
+ attribute \src "libresoc.v:75563.3-75614.6"
wire width 3 $0\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75790.3-75841.6"
+ attribute \src "libresoc.v:75615.3-75666.6"
wire width 3 $0\dec19_cr_out[2:0]
- attribute \src "libresoc.v:76414.3-76465.6"
+ attribute \src "libresoc.v:76239.3-76290.6"
wire width 2 $0\dec19_cry_in[1:0]
- attribute \src "libresoc.v:76622.3-76673.6"
+ attribute \src "libresoc.v:76447.3-76498.6"
wire $0\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76830.3-76881.6"
+ attribute \src "libresoc.v:76655.3-76706.6"
wire width 5 $0\dec19_form[4:0]
- attribute \src "libresoc.v:75686.3-75737.6"
+ attribute \src "libresoc.v:75511.3-75562.6"
wire width 14 $0\dec19_function_unit[13:0]
- attribute \src "libresoc.v:77194.3-77245.6"
+ attribute \src "libresoc.v:77019.3-77070.6"
wire width 3 $0\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:77246.3-77297.6"
+ attribute \src "libresoc.v:77071.3-77122.6"
wire width 4 $0\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:77298.3-77349.6"
+ attribute \src "libresoc.v:77123.3-77174.6"
wire width 2 $0\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:76258.3-76309.6"
+ attribute \src "libresoc.v:76083.3-76134.6"
wire width 7 $0\dec19_internal_op[6:0]
- attribute \src "libresoc.v:76518.3-76569.6"
+ attribute \src "libresoc.v:76343.3-76394.6"
wire $0\dec19_inv_a[0:0]
- attribute \src "libresoc.v:76570.3-76621.6"
+ attribute \src "libresoc.v:76395.3-76446.6"
wire $0\dec19_inv_out[0:0]
- attribute \src "libresoc.v:76882.3-76933.6"
+ attribute \src "libresoc.v:76707.3-76758.6"
wire $0\dec19_is_32b[0:0]
- attribute \src "libresoc.v:76206.3-76257.6"
+ attribute \src "libresoc.v:76031.3-76082.6"
wire width 4 $0\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:76986.3-77037.6"
+ attribute \src "libresoc.v:76811.3-76862.6"
wire $0\dec19_lk[0:0]
- attribute \src "libresoc.v:77350.3-77401.6"
+ attribute \src "libresoc.v:77175.3-77226.6"
wire width 3 $0\dec19_out_sel[2:0]
- attribute \src "libresoc.v:76362.3-76413.6"
+ attribute \src "libresoc.v:76187.3-76238.6"
wire width 2 $0\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:76778.3-76829.6"
+ attribute \src "libresoc.v:76603.3-76654.6"
wire $0\dec19_rsrv[0:0]
- attribute \src "libresoc.v:77038.3-77089.6"
+ attribute \src "libresoc.v:76863.3-76914.6"
wire $0\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:76934.3-76985.6"
+ attribute \src "libresoc.v:76759.3-76810.6"
wire $0\dec19_sgn[0:0]
- attribute \src "libresoc.v:76726.3-76777.6"
+ attribute \src "libresoc.v:76551.3-76602.6"
wire $0\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:76102.3-76153.6"
+ attribute \src "libresoc.v:75927.3-75978.6"
wire width 3 $0\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:76154.3-76205.6"
+ attribute \src "libresoc.v:75979.3-76030.6"
wire width 3 $0\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:75842.3-75893.6"
+ attribute \src "libresoc.v:75667.3-75718.6"
wire width 3 $0\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75894.3-75945.6"
+ attribute \src "libresoc.v:75719.3-75770.6"
wire width 3 $0\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75946.3-75997.6"
+ attribute \src "libresoc.v:75771.3-75822.6"
wire width 3 $0\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:76050.3-76101.6"
+ attribute \src "libresoc.v:75875.3-75926.6"
wire width 3 $0\dec19_sv_out2[2:0]
- attribute \src "libresoc.v:75998.3-76049.6"
+ attribute \src "libresoc.v:75823.3-75874.6"
wire width 3 $0\dec19_sv_out[2:0]
- attribute \src "libresoc.v:76310.3-76361.6"
+ attribute \src "libresoc.v:76135.3-76186.6"
wire width 2 $0\dec19_upd[1:0]
- attribute \src "libresoc.v:75338.7-75338.20"
+ attribute \src "libresoc.v:75163.7-75163.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:77090.3-77141.6"
+ attribute \src "libresoc.v:76915.3-76966.6"
wire width 2 $1\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:77142.3-77193.6"
+ attribute \src "libresoc.v:76967.3-77018.6"
wire width 2 $1\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:76466.3-76517.6"
+ attribute \src "libresoc.v:76291.3-76342.6"
wire width 8 $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:76674.3-76725.6"
+ attribute \src "libresoc.v:76499.3-76550.6"
wire $1\dec19_br[0:0]
- attribute \src "libresoc.v:75738.3-75789.6"
+ attribute \src "libresoc.v:75563.3-75614.6"
wire width 3 $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75790.3-75841.6"
+ attribute \src "libresoc.v:75615.3-75666.6"
wire width 3 $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:76414.3-76465.6"
+ attribute \src "libresoc.v:76239.3-76290.6"
wire width 2 $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:76622.3-76673.6"
+ attribute \src "libresoc.v:76447.3-76498.6"
wire $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76830.3-76881.6"
+ attribute \src "libresoc.v:76655.3-76706.6"
wire width 5 $1\dec19_form[4:0]
- attribute \src "libresoc.v:75686.3-75737.6"
+ attribute \src "libresoc.v:75511.3-75562.6"
wire width 14 $1\dec19_function_unit[13:0]
- attribute \src "libresoc.v:77194.3-77245.6"
+ attribute \src "libresoc.v:77019.3-77070.6"
wire width 3 $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:77246.3-77297.6"
+ attribute \src "libresoc.v:77071.3-77122.6"
wire width 4 $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:77298.3-77349.6"
+ attribute \src "libresoc.v:77123.3-77174.6"
wire width 2 $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:76258.3-76309.6"
+ attribute \src "libresoc.v:76083.3-76134.6"
wire width 7 $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:76518.3-76569.6"
+ attribute \src "libresoc.v:76343.3-76394.6"
wire $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:76570.3-76621.6"
+ attribute \src "libresoc.v:76395.3-76446.6"
wire $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:76882.3-76933.6"
+ attribute \src "libresoc.v:76707.3-76758.6"
wire $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:76206.3-76257.6"
+ attribute \src "libresoc.v:76031.3-76082.6"
wire width 4 $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:76986.3-77037.6"
+ attribute \src "libresoc.v:76811.3-76862.6"
wire $1\dec19_lk[0:0]
- attribute \src "libresoc.v:77350.3-77401.6"
+ attribute \src "libresoc.v:77175.3-77226.6"
wire width 3 $1\dec19_out_sel[2:0]
- attribute \src "libresoc.v:76362.3-76413.6"
+ attribute \src "libresoc.v:76187.3-76238.6"
wire width 2 $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:76778.3-76829.6"
+ attribute \src "libresoc.v:76603.3-76654.6"
wire $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:77038.3-77089.6"
+ attribute \src "libresoc.v:76863.3-76914.6"
wire $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:76934.3-76985.6"
+ attribute \src "libresoc.v:76759.3-76810.6"
wire $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:76726.3-76777.6"
+ attribute \src "libresoc.v:76551.3-76602.6"
wire $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:76102.3-76153.6"
+ attribute \src "libresoc.v:75927.3-75978.6"
wire width 3 $1\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:76154.3-76205.6"
+ attribute \src "libresoc.v:75979.3-76030.6"
wire width 3 $1\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:75842.3-75893.6"
+ attribute \src "libresoc.v:75667.3-75718.6"
wire width 3 $1\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75894.3-75945.6"
+ attribute \src "libresoc.v:75719.3-75770.6"
wire width 3 $1\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75946.3-75997.6"
+ attribute \src "libresoc.v:75771.3-75822.6"
wire width 3 $1\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:76050.3-76101.6"
+ attribute \src "libresoc.v:75875.3-75926.6"
wire width 3 $1\dec19_sv_out2[2:0]
- attribute \src "libresoc.v:75998.3-76049.6"
+ attribute \src "libresoc.v:75823.3-75874.6"
wire width 3 $1\dec19_sv_out[2:0]
- attribute \src "libresoc.v:76310.3-76361.6"
+ attribute \src "libresoc.v:76135.3-76186.6"
wire width 2 $1\dec19_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec19_upd
- attribute \src "libresoc.v:75338.7-75338.15"
+ attribute \src "libresoc.v:75163.7-75163.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 10 \opcode_switch
- attribute \src "libresoc.v:75338.7-75338.20"
- process $proc$libresoc.v:75338$3637
+ attribute \src "libresoc.v:75163.7-75163.20"
+ process $proc$libresoc.v:75163$3621
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:75686.3-75737.6"
- process $proc$libresoc.v:75686$3604
+ attribute \src "libresoc.v:75511.3-75562.6"
+ process $proc$libresoc.v:75511$3588
assign { } { }
assign { } { }
assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0]
- attribute \src "libresoc.v:75687.5-75687.29"
+ attribute \src "libresoc.v:75512.5-75512.29"
switch \initial
- attribute \src "libresoc.v:75687.9-75687.17"
+ attribute \src "libresoc.v:75512.9-75512.17"
case 1'1
case
end
sync always
update \dec19_function_unit $0\dec19_function_unit[13:0]
end
- attribute \src "libresoc.v:75738.3-75789.6"
- process $proc$libresoc.v:75738$3605
+ attribute \src "libresoc.v:75563.3-75614.6"
+ process $proc$libresoc.v:75563$3589
assign { } { }
assign { } { }
assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75739.5-75739.29"
+ attribute \src "libresoc.v:75564.5-75564.29"
switch \initial
- attribute \src "libresoc.v:75739.9-75739.17"
+ attribute \src "libresoc.v:75564.9-75564.17"
case 1'1
case
end
sync always
update \dec19_cr_in $0\dec19_cr_in[2:0]
end
- attribute \src "libresoc.v:75790.3-75841.6"
- process $proc$libresoc.v:75790$3606
+ attribute \src "libresoc.v:75615.3-75666.6"
+ process $proc$libresoc.v:75615$3590
assign { } { }
assign { } { }
assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:75791.5-75791.29"
+ attribute \src "libresoc.v:75616.5-75616.29"
switch \initial
- attribute \src "libresoc.v:75791.9-75791.17"
+ attribute \src "libresoc.v:75616.9-75616.17"
case 1'1
case
end
sync always
update \dec19_cr_out $0\dec19_cr_out[2:0]
end
- attribute \src "libresoc.v:75842.3-75893.6"
- process $proc$libresoc.v:75842$3607
+ attribute \src "libresoc.v:75667.3-75718.6"
+ process $proc$libresoc.v:75667$3591
assign { } { }
assign { } { }
assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75843.5-75843.29"
+ attribute \src "libresoc.v:75668.5-75668.29"
switch \initial
- attribute \src "libresoc.v:75843.9-75843.17"
+ attribute \src "libresoc.v:75668.9-75668.17"
case 1'1
case
end
sync always
update \dec19_sv_in1 $0\dec19_sv_in1[2:0]
end
- attribute \src "libresoc.v:75894.3-75945.6"
- process $proc$libresoc.v:75894$3608
+ attribute \src "libresoc.v:75719.3-75770.6"
+ process $proc$libresoc.v:75719$3592
assign { } { }
assign { } { }
assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75895.5-75895.29"
+ attribute \src "libresoc.v:75720.5-75720.29"
switch \initial
- attribute \src "libresoc.v:75895.9-75895.17"
+ attribute \src "libresoc.v:75720.9-75720.17"
case 1'1
case
end
sync always
update \dec19_sv_in2 $0\dec19_sv_in2[2:0]
end
- attribute \src "libresoc.v:75946.3-75997.6"
- process $proc$libresoc.v:75946$3609
+ attribute \src "libresoc.v:75771.3-75822.6"
+ process $proc$libresoc.v:75771$3593
assign { } { }
assign { } { }
assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:75947.5-75947.29"
+ attribute \src "libresoc.v:75772.5-75772.29"
switch \initial
- attribute \src "libresoc.v:75947.9-75947.17"
+ attribute \src "libresoc.v:75772.9-75772.17"
case 1'1
case
end
sync always
update \dec19_sv_in3 $0\dec19_sv_in3[2:0]
end
- attribute \src "libresoc.v:75998.3-76049.6"
- process $proc$libresoc.v:75998$3610
+ attribute \src "libresoc.v:75823.3-75874.6"
+ process $proc$libresoc.v:75823$3594
assign { } { }
assign { } { }
assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0]
- attribute \src "libresoc.v:75999.5-75999.29"
+ attribute \src "libresoc.v:75824.5-75824.29"
switch \initial
- attribute \src "libresoc.v:75999.9-75999.17"
+ attribute \src "libresoc.v:75824.9-75824.17"
case 1'1
case
end
sync always
update \dec19_sv_out $0\dec19_sv_out[2:0]
end
- attribute \src "libresoc.v:76050.3-76101.6"
- process $proc$libresoc.v:76050$3611
+ attribute \src "libresoc.v:75875.3-75926.6"
+ process $proc$libresoc.v:75875$3595
assign { } { }
assign { } { }
assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0]
- attribute \src "libresoc.v:76051.5-76051.29"
+ attribute \src "libresoc.v:75876.5-75876.29"
switch \initial
- attribute \src "libresoc.v:76051.9-76051.17"
+ attribute \src "libresoc.v:75876.9-75876.17"
case 1'1
case
end
sync always
update \dec19_sv_out2 $0\dec19_sv_out2[2:0]
end
- attribute \src "libresoc.v:76102.3-76153.6"
- process $proc$libresoc.v:76102$3612
+ attribute \src "libresoc.v:75927.3-75978.6"
+ process $proc$libresoc.v:75927$3596
assign { } { }
assign { } { }
assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:76103.5-76103.29"
+ attribute \src "libresoc.v:75928.5-75928.29"
switch \initial
- attribute \src "libresoc.v:76103.9-76103.17"
+ attribute \src "libresoc.v:75928.9-75928.17"
case 1'1
case
end
sync always
update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:76154.3-76205.6"
- process $proc$libresoc.v:76154$3613
+ attribute \src "libresoc.v:75979.3-76030.6"
+ process $proc$libresoc.v:75979$3597
assign { } { }
assign { } { }
assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:76155.5-76155.29"
+ attribute \src "libresoc.v:75980.5-75980.29"
switch \initial
- attribute \src "libresoc.v:76155.9-76155.17"
+ attribute \src "libresoc.v:75980.9-75980.17"
case 1'1
case
end
sync always
update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:76206.3-76257.6"
- process $proc$libresoc.v:76206$3614
+ attribute \src "libresoc.v:76031.3-76082.6"
+ process $proc$libresoc.v:76031$3598
assign { } { }
assign { } { }
assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:76207.5-76207.29"
+ attribute \src "libresoc.v:76032.5-76032.29"
switch \initial
- attribute \src "libresoc.v:76207.9-76207.17"
+ attribute \src "libresoc.v:76032.9-76032.17"
case 1'1
case
end
sync always
update \dec19_ldst_len $0\dec19_ldst_len[3:0]
end
- attribute \src "libresoc.v:76258.3-76309.6"
- process $proc$libresoc.v:76258$3615
+ attribute \src "libresoc.v:76083.3-76134.6"
+ process $proc$libresoc.v:76083$3599
assign { } { }
assign { } { }
assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:76259.5-76259.29"
+ attribute \src "libresoc.v:76084.5-76084.29"
switch \initial
- attribute \src "libresoc.v:76259.9-76259.17"
+ attribute \src "libresoc.v:76084.9-76084.17"
case 1'1
case
end
sync always
update \dec19_internal_op $0\dec19_internal_op[6:0]
end
- attribute \src "libresoc.v:76310.3-76361.6"
- process $proc$libresoc.v:76310$3616
+ attribute \src "libresoc.v:76135.3-76186.6"
+ process $proc$libresoc.v:76135$3600
assign { } { }
assign { } { }
assign $0\dec19_upd[1:0] $1\dec19_upd[1:0]
- attribute \src "libresoc.v:76311.5-76311.29"
+ attribute \src "libresoc.v:76136.5-76136.29"
switch \initial
- attribute \src "libresoc.v:76311.9-76311.17"
+ attribute \src "libresoc.v:76136.9-76136.17"
case 1'1
case
end
sync always
update \dec19_upd $0\dec19_upd[1:0]
end
- attribute \src "libresoc.v:76362.3-76413.6"
- process $proc$libresoc.v:76362$3617
+ attribute \src "libresoc.v:76187.3-76238.6"
+ process $proc$libresoc.v:76187$3601
assign { } { }
assign { } { }
assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:76363.5-76363.29"
+ attribute \src "libresoc.v:76188.5-76188.29"
switch \initial
- attribute \src "libresoc.v:76363.9-76363.17"
+ attribute \src "libresoc.v:76188.9-76188.17"
case 1'1
case
end
sync always
update \dec19_rc_sel $0\dec19_rc_sel[1:0]
end
- attribute \src "libresoc.v:76414.3-76465.6"
- process $proc$libresoc.v:76414$3618
+ attribute \src "libresoc.v:76239.3-76290.6"
+ process $proc$libresoc.v:76239$3602
assign { } { }
assign { } { }
assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:76415.5-76415.29"
+ attribute \src "libresoc.v:76240.5-76240.29"
switch \initial
- attribute \src "libresoc.v:76415.9-76415.17"
+ attribute \src "libresoc.v:76240.9-76240.17"
case 1'1
case
end
sync always
update \dec19_cry_in $0\dec19_cry_in[1:0]
end
- attribute \src "libresoc.v:76466.3-76517.6"
- process $proc$libresoc.v:76466$3619
+ attribute \src "libresoc.v:76291.3-76342.6"
+ process $proc$libresoc.v:76291$3603
assign { } { }
assign { } { }
assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:76467.5-76467.29"
+ attribute \src "libresoc.v:76292.5-76292.29"
switch \initial
- attribute \src "libresoc.v:76467.9-76467.17"
+ attribute \src "libresoc.v:76292.9-76292.17"
case 1'1
case
end
sync always
update \dec19_asmcode $0\dec19_asmcode[7:0]
end
- attribute \src "libresoc.v:76518.3-76569.6"
- process $proc$libresoc.v:76518$3620
+ attribute \src "libresoc.v:76343.3-76394.6"
+ process $proc$libresoc.v:76343$3604
assign { } { }
assign { } { }
assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:76519.5-76519.29"
+ attribute \src "libresoc.v:76344.5-76344.29"
switch \initial
- attribute \src "libresoc.v:76519.9-76519.17"
+ attribute \src "libresoc.v:76344.9-76344.17"
case 1'1
case
end
sync always
update \dec19_inv_a $0\dec19_inv_a[0:0]
end
- attribute \src "libresoc.v:76570.3-76621.6"
- process $proc$libresoc.v:76570$3621
+ attribute \src "libresoc.v:76395.3-76446.6"
+ process $proc$libresoc.v:76395$3605
assign { } { }
assign { } { }
assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:76571.5-76571.29"
+ attribute \src "libresoc.v:76396.5-76396.29"
switch \initial
- attribute \src "libresoc.v:76571.9-76571.17"
+ attribute \src "libresoc.v:76396.9-76396.17"
case 1'1
case
end
sync always
update \dec19_inv_out $0\dec19_inv_out[0:0]
end
- attribute \src "libresoc.v:76622.3-76673.6"
- process $proc$libresoc.v:76622$3622
+ attribute \src "libresoc.v:76447.3-76498.6"
+ process $proc$libresoc.v:76447$3606
assign { } { }
assign { } { }
assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76623.5-76623.29"
+ attribute \src "libresoc.v:76448.5-76448.29"
switch \initial
- attribute \src "libresoc.v:76623.9-76623.17"
+ attribute \src "libresoc.v:76448.9-76448.17"
case 1'1
case
end
sync always
update \dec19_cry_out $0\dec19_cry_out[0:0]
end
- attribute \src "libresoc.v:76674.3-76725.6"
- process $proc$libresoc.v:76674$3623
+ attribute \src "libresoc.v:76499.3-76550.6"
+ process $proc$libresoc.v:76499$3607
assign { } { }
assign { } { }
assign $0\dec19_br[0:0] $1\dec19_br[0:0]
- attribute \src "libresoc.v:76675.5-76675.29"
+ attribute \src "libresoc.v:76500.5-76500.29"
switch \initial
- attribute \src "libresoc.v:76675.9-76675.17"
+ attribute \src "libresoc.v:76500.9-76500.17"
case 1'1
case
end
sync always
update \dec19_br $0\dec19_br[0:0]
end
- attribute \src "libresoc.v:76726.3-76777.6"
- process $proc$libresoc.v:76726$3624
+ attribute \src "libresoc.v:76551.3-76602.6"
+ process $proc$libresoc.v:76551$3608
assign { } { }
assign { } { }
assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:76727.5-76727.29"
+ attribute \src "libresoc.v:76552.5-76552.29"
switch \initial
- attribute \src "libresoc.v:76727.9-76727.17"
+ attribute \src "libresoc.v:76552.9-76552.17"
case 1'1
case
end
sync always
update \dec19_sgn_ext $0\dec19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:76778.3-76829.6"
- process $proc$libresoc.v:76778$3625
+ attribute \src "libresoc.v:76603.3-76654.6"
+ process $proc$libresoc.v:76603$3609
assign { } { }
assign { } { }
assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:76779.5-76779.29"
+ attribute \src "libresoc.v:76604.5-76604.29"
switch \initial
- attribute \src "libresoc.v:76779.9-76779.17"
+ attribute \src "libresoc.v:76604.9-76604.17"
case 1'1
case
end
sync always
update \dec19_rsrv $0\dec19_rsrv[0:0]
end
- attribute \src "libresoc.v:76830.3-76881.6"
- process $proc$libresoc.v:76830$3626
+ attribute \src "libresoc.v:76655.3-76706.6"
+ process $proc$libresoc.v:76655$3610
assign { } { }
assign { } { }
assign $0\dec19_form[4:0] $1\dec19_form[4:0]
- attribute \src "libresoc.v:76831.5-76831.29"
+ attribute \src "libresoc.v:76656.5-76656.29"
switch \initial
- attribute \src "libresoc.v:76831.9-76831.17"
+ attribute \src "libresoc.v:76656.9-76656.17"
case 1'1
case
end
sync always
update \dec19_form $0\dec19_form[4:0]
end
- attribute \src "libresoc.v:76882.3-76933.6"
- process $proc$libresoc.v:76882$3627
+ attribute \src "libresoc.v:76707.3-76758.6"
+ process $proc$libresoc.v:76707$3611
assign { } { }
assign { } { }
assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:76883.5-76883.29"
+ attribute \src "libresoc.v:76708.5-76708.29"
switch \initial
- attribute \src "libresoc.v:76883.9-76883.17"
+ attribute \src "libresoc.v:76708.9-76708.17"
case 1'1
case
end
sync always
update \dec19_is_32b $0\dec19_is_32b[0:0]
end
- attribute \src "libresoc.v:76934.3-76985.6"
- process $proc$libresoc.v:76934$3628
+ attribute \src "libresoc.v:76759.3-76810.6"
+ process $proc$libresoc.v:76759$3612
assign { } { }
assign { } { }
assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:76935.5-76935.29"
+ attribute \src "libresoc.v:76760.5-76760.29"
switch \initial
- attribute \src "libresoc.v:76935.9-76935.17"
+ attribute \src "libresoc.v:76760.9-76760.17"
case 1'1
case
end
sync always
update \dec19_sgn $0\dec19_sgn[0:0]
end
- attribute \src "libresoc.v:76986.3-77037.6"
- process $proc$libresoc.v:76986$3629
+ attribute \src "libresoc.v:76811.3-76862.6"
+ process $proc$libresoc.v:76811$3613
assign { } { }
assign { } { }
assign $0\dec19_lk[0:0] $1\dec19_lk[0:0]
- attribute \src "libresoc.v:76987.5-76987.29"
+ attribute \src "libresoc.v:76812.5-76812.29"
switch \initial
- attribute \src "libresoc.v:76987.9-76987.17"
+ attribute \src "libresoc.v:76812.9-76812.17"
case 1'1
case
end
sync always
update \dec19_lk $0\dec19_lk[0:0]
end
- attribute \src "libresoc.v:77038.3-77089.6"
- process $proc$libresoc.v:77038$3630
+ attribute \src "libresoc.v:76863.3-76914.6"
+ process $proc$libresoc.v:76863$3614
assign { } { }
assign { } { }
assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:77039.5-77039.29"
+ attribute \src "libresoc.v:76864.5-76864.29"
switch \initial
- attribute \src "libresoc.v:77039.9-77039.17"
+ attribute \src "libresoc.v:76864.9-76864.17"
case 1'1
case
end
sync always
update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:77090.3-77141.6"
- process $proc$libresoc.v:77090$3631
+ attribute \src "libresoc.v:76915.3-76966.6"
+ process $proc$libresoc.v:76915$3615
assign { } { }
assign { } { }
assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:77091.5-77091.29"
+ attribute \src "libresoc.v:76916.5-76916.29"
switch \initial
- attribute \src "libresoc.v:77091.9-77091.17"
+ attribute \src "libresoc.v:76916.9-76916.17"
case 1'1
case
end
sync always
update \dec19_SV_Etype $0\dec19_SV_Etype[1:0]
end
- attribute \src "libresoc.v:77142.3-77193.6"
- process $proc$libresoc.v:77142$3632
+ attribute \src "libresoc.v:76967.3-77018.6"
+ process $proc$libresoc.v:76967$3616
assign { } { }
assign { } { }
assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:77143.5-77143.29"
+ attribute \src "libresoc.v:76968.5-76968.29"
switch \initial
- attribute \src "libresoc.v:77143.9-77143.17"
+ attribute \src "libresoc.v:76968.9-76968.17"
case 1'1
case
end
sync always
update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:77194.3-77245.6"
- process $proc$libresoc.v:77194$3633
+ attribute \src "libresoc.v:77019.3-77070.6"
+ process $proc$libresoc.v:77019$3617
assign { } { }
assign { } { }
assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:77195.5-77195.29"
+ attribute \src "libresoc.v:77020.5-77020.29"
switch \initial
- attribute \src "libresoc.v:77195.9-77195.17"
+ attribute \src "libresoc.v:77020.9-77020.17"
case 1'1
case
end
sync always
update \dec19_in1_sel $0\dec19_in1_sel[2:0]
end
- attribute \src "libresoc.v:77246.3-77297.6"
- process $proc$libresoc.v:77246$3634
+ attribute \src "libresoc.v:77071.3-77122.6"
+ process $proc$libresoc.v:77071$3618
assign { } { }
assign { } { }
assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:77247.5-77247.29"
+ attribute \src "libresoc.v:77072.5-77072.29"
switch \initial
- attribute \src "libresoc.v:77247.9-77247.17"
+ attribute \src "libresoc.v:77072.9-77072.17"
case 1'1
case
end
sync always
update \dec19_in2_sel $0\dec19_in2_sel[3:0]
end
- attribute \src "libresoc.v:77298.3-77349.6"
- process $proc$libresoc.v:77298$3635
+ attribute \src "libresoc.v:77123.3-77174.6"
+ process $proc$libresoc.v:77123$3619
assign { } { }
assign { } { }
assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:77299.5-77299.29"
+ attribute \src "libresoc.v:77124.5-77124.29"
switch \initial
- attribute \src "libresoc.v:77299.9-77299.17"
+ attribute \src "libresoc.v:77124.9-77124.17"
case 1'1
case
end
sync always
update \dec19_in3_sel $0\dec19_in3_sel[1:0]
end
- attribute \src "libresoc.v:77350.3-77401.6"
- process $proc$libresoc.v:77350$3636
+ attribute \src "libresoc.v:77175.3-77226.6"
+ process $proc$libresoc.v:77175$3620
assign { } { }
assign { } { }
assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0]
- attribute \src "libresoc.v:77351.5-77351.29"
+ attribute \src "libresoc.v:77176.5-77176.29"
switch \initial
- attribute \src "libresoc.v:77351.9-77351.17"
+ attribute \src "libresoc.v:77176.9-77176.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:77407.1-79628.10"
+attribute \src "libresoc.v:77232.1-79453.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2"
attribute \generator "nMigen"
module \dec2
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $0\cia[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\cr_in1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire width 7 $0\cr_in2$1[6:0]$3698
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire width 7 $0\cr_in2$1[6:0]$3682
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\cr_in2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\cr_in2_ok$2[0:0]$3699
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\cr_in2_ok$2[0:0]$3683
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\cr_out_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $0\cr_rd[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $0\cr_wr[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\ea[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\ea_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$3[0:0]$3701
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$4[0:0]$3702
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$5[0:0]$3703
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$6[0:0]$3704
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$7[0:0]$3705
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$8[0:0]$3706
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal$9[0:0]$3707
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $0\exc_$signal[0:0]$3700
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$3[0:0]$3685
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$4[0:0]$3686
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$5[0:0]$3687
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$6[0:0]$3688
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$7[0:0]$3689
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$8[0:0]$3690
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal$9[0:0]$3691
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $0\exc_$signal[0:0]$3684
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $0\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $0\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $0\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $0\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\fasto2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 14 $0\fn_unit[13:0]
- attribute \src "libresoc.v:77408.7-77408.20"
+ attribute \src "libresoc.v:77233.7-77233.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 2 $0\input_carry[1:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 32 $0\insn[31:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\insn_type[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\is_32bit[0:0]
- attribute \src "libresoc.v:79367.3-79390.6"
+ attribute \src "libresoc.v:79192.3-79215.6"
wire $0\is_priv_insn[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\reg1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\reg1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\reg2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\reg2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\reg3[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\reg3_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $0\rego[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\rego_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $0\spr1[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $0\spro[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\spro_ok[0:0]
- attribute \src "libresoc.v:79293.3-79307.6"
+ attribute \src "libresoc.v:79118.3-79132.6"
wire width 14 $0\tmp_tmp_fn_unit[13:0]
- attribute \src "libresoc.v:79318.3-79330.6"
+ attribute \src "libresoc.v:79143.3-79155.6"
wire width 7 $0\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79308.3-79317.6"
+ attribute \src "libresoc.v:79133.3-79142.6"
wire $0\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79357.3-79366.6"
+ attribute \src "libresoc.v:79182.3-79191.6"
wire width 13 $0\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79331.3-79346.6"
+ attribute \src "libresoc.v:79156.3-79171.6"
wire width 3 $0\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79347.3-79356.6"
+ attribute \src "libresoc.v:79172.3-79181.6"
wire $0\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 13 $0\trapaddr[12:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $0\traptype[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $0\xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $0\xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $1\cia[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\cr_in1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire width 7 $1\cr_in2$1[6:0]$3708
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire width 7 $1\cr_in2$1[6:0]$3692
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\cr_in2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\cr_in2_ok$2[0:0]$3709
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\cr_in2_ok$2[0:0]$3693
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\cr_out_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $1\cr_rd[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $1\cr_wr[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\ea[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\ea_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$3[0:0]$3711
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$4[0:0]$3712
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$5[0:0]$3713
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$6[0:0]$3714
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$7[0:0]$3715
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$8[0:0]$3716
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal$9[0:0]$3717
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $1\exc_$signal[0:0]$3710
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$3[0:0]$3695
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$4[0:0]$3696
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$5[0:0]$3697
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$6[0:0]$3698
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$7[0:0]$3699
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$8[0:0]$3700
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal$9[0:0]$3701
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $1\exc_$signal[0:0]$3694
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $1\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $1\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $1\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $1\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\fasto2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 14 $1\fn_unit[13:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 2 $1\input_carry[1:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 32 $1\insn[31:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\insn_type[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\is_32bit[0:0]
- attribute \src "libresoc.v:79367.3-79390.6"
+ attribute \src "libresoc.v:79192.3-79215.6"
wire $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\rc_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\reg1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\reg1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\reg2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\reg2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\reg3[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\reg3_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $1\rego[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\rego_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $1\spr1[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $1\spro[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\spro_ok[0:0]
- attribute \src "libresoc.v:79293.3-79307.6"
+ attribute \src "libresoc.v:79118.3-79132.6"
wire width 14 $1\tmp_tmp_fn_unit[13:0]
- attribute \src "libresoc.v:79318.3-79330.6"
+ attribute \src "libresoc.v:79143.3-79155.6"
wire width 7 $1\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79308.3-79317.6"
+ attribute \src "libresoc.v:79133.3-79142.6"
wire $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79357.3-79366.6"
+ attribute \src "libresoc.v:79182.3-79191.6"
wire width 13 $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79331.3-79346.6"
+ attribute \src "libresoc.v:79156.3-79171.6"
wire width 3 $1\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79347.3-79356.6"
+ attribute \src "libresoc.v:79172.3-79181.6"
wire $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 13 $1\trapaddr[12:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $1\traptype[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $1\xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $1\xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $2\asmcode[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $2\cia[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\cr_in1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire width 7 $2\cr_in2$1[6:0]$3718
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire width 7 $2\cr_in2$1[6:0]$3702
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\cr_in2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\cr_in2_ok$2[0:0]$3719
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\cr_in2_ok$2[0:0]$3703
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\cr_out[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\cr_out_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $2\cr_rd[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $2\cr_wr[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\ea[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\ea_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$3[0:0]$3721
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$4[0:0]$3722
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$5[0:0]$3723
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$6[0:0]$3724
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$7[0:0]$3725
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$8[0:0]$3726
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal$9[0:0]$3727
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $2\exc_$signal[0:0]$3720
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$3[0:0]$3705
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$4[0:0]$3706
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$5[0:0]$3707
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$6[0:0]$3708
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$7[0:0]$3709
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$8[0:0]$3710
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal$9[0:0]$3711
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $2\exc_$signal[0:0]$3704
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $2\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $2\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $2\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $2\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\fasto2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 14 $2\fn_unit[13:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 2 $2\input_carry[1:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 32 $2\insn[31:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\insn_type[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\is_32bit[0:0]
- attribute \src "libresoc.v:79367.3-79390.6"
+ attribute \src "libresoc.v:79192.3-79215.6"
wire $2\is_priv_insn[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\lk[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $2\msr[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\oe_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\rc[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\rc_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\reg1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\reg1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\reg2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\reg2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\reg3[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\reg3_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $2\rego[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\rego_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $2\spr1[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\spr1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $2\spro[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\spro_ok[0:0]
- attribute \src "libresoc.v:79331.3-79346.6"
+ attribute \src "libresoc.v:79156.3-79171.6"
wire width 3 $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 13 $2\trapaddr[12:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $2\traptype[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $2\xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $2\xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $3\asmcode[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $3\cia[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\cr_in1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire width 7 $3\cr_in2$1[6:0]$3728
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire width 7 $3\cr_in2$1[6:0]$3712
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\cr_in2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\cr_in2_ok$2[0:0]$3729
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\cr_in2_ok$2[0:0]$3713
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\cr_out[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\cr_out_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $3\cr_rd[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $3\cr_wr[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\ea[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\ea_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$3[0:0]$3731
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$4[0:0]$3732
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$5[0:0]$3733
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$6[0:0]$3734
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$7[0:0]$3735
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$8[0:0]$3736
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal$9[0:0]$3737
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $3\exc_$signal[0:0]$3730
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$3[0:0]$3715
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$4[0:0]$3716
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$5[0:0]$3717
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$6[0:0]$3718
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$7[0:0]$3719
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$8[0:0]$3720
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal$9[0:0]$3721
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $3\exc_$signal[0:0]$3714
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $3\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $3\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $3\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $3\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\fasto2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 14 $3\fn_unit[13:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 2 $3\input_carry[1:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 32 $3\insn[31:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\insn_type[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\is_32bit[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\lk[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $3\msr[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\oe[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\oe_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\rc[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\rc_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\reg1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\reg1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\reg2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\reg2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\reg3[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\reg3_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $3\rego[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\rego_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $3\spr1[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\spr1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $3\spro[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\spro_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 13 $3\trapaddr[12:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $3\traptype[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $3\xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $3\xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $4\asmcode[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $4\cia[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\cr_in1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire width 7 $4\cr_in2$1[6:0]$3738
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire width 7 $4\cr_in2$1[6:0]$3722
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\cr_in2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\cr_in2_ok$2[0:0]$3739
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\cr_in2_ok$2[0:0]$3723
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\cr_out[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\cr_out_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $4\cr_rd[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $4\cr_wr[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\ea[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\ea_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$3[0:0]$3741
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$4[0:0]$3742
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$5[0:0]$3743
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$6[0:0]$3744
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$7[0:0]$3745
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$8[0:0]$3746
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal$9[0:0]$3747
- attribute \src "libresoc.v:79391.3-79548.6"
- wire $4\exc_$signal[0:0]$3740
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$3[0:0]$3725
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$4[0:0]$3726
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$5[0:0]$3727
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$6[0:0]$3728
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$7[0:0]$3729
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$8[0:0]$3730
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal$9[0:0]$3731
+ attribute \src "libresoc.v:79216.3-79373.6"
+ wire $4\exc_$signal[0:0]$3724
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $4\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $4\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $4\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $4\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\fasto2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 14 $4\fn_unit[13:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 2 $4\input_carry[1:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 32 $4\insn[31:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\insn_type[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\is_32bit[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\lk[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 64 $4\msr[63:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\oe[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\oe_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\rc[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\rc_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\reg1[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\reg1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\reg2[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\reg2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\reg3[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\reg3_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 7 $4\rego[6:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\rego_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $4\spr1[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\spr1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 10 $4\spro[9:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\spro_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 13 $4\trapaddr[12:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 8 $4\traptype[7:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $4\xer_in[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $4\xer_out[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $5\fast1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $5\fast1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $5\fast2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $5\fast2_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $5\fasto1[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $5\fasto1_ok[0:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire width 3 $5\fasto2[2:0]
- attribute \src "libresoc.v:79391.3-79548.6"
+ attribute \src "libresoc.v:79216.3-79373.6"
wire $5\fasto2_ok[0:0]
- attribute \src "libresoc.v:79114.19-79114.122"
- wire $and$libresoc.v:79114$3648_Y
- attribute \src "libresoc.v:79115.19-79115.125"
- wire $and$libresoc.v:79115$3649_Y
- attribute \src "libresoc.v:79116.19-79116.126"
- wire $and$libresoc.v:79116$3650_Y
- attribute \src "libresoc.v:79123.18-79123.114"
- wire $and$libresoc.v:79123$3657_Y
- attribute \src "libresoc.v:79124.18-79124.116"
- wire $and$libresoc.v:79124$3658_Y
- attribute \src "libresoc.v:79126.18-79126.114"
- wire $and$libresoc.v:79126$3660_Y
- attribute \src "libresoc.v:79128.18-79128.110"
- wire $and$libresoc.v:79128$3662_Y
- attribute \src "libresoc.v:79140.18-79140.114"
- wire $and$libresoc.v:79140$3674_Y
- attribute \src "libresoc.v:79141.18-79141.116"
- wire $and$libresoc.v:79141$3675_Y
- attribute \src "libresoc.v:79143.18-79143.114"
- wire $and$libresoc.v:79143$3677_Y
- attribute \src "libresoc.v:79145.18-79145.110"
- wire $and$libresoc.v:79145$3679_Y
- attribute \src "libresoc.v:79110.19-79110.124"
- wire $eq$libresoc.v:79110$3644_Y
- attribute \src "libresoc.v:79111.19-79111.124"
- wire $eq$libresoc.v:79111$3645_Y
- attribute \src "libresoc.v:79112.19-79112.124"
- wire $eq$libresoc.v:79112$3646_Y
- attribute \src "libresoc.v:79113.19-79113.124"
- wire $eq$libresoc.v:79113$3647_Y
- attribute \src "libresoc.v:79117.19-79117.124"
- wire $eq$libresoc.v:79117$3651_Y
- attribute \src "libresoc.v:79118.18-79118.117"
- wire $eq$libresoc.v:79118$3652_Y
- attribute \src "libresoc.v:79119.18-79119.117"
- wire $eq$libresoc.v:79119$3653_Y
- attribute \src "libresoc.v:79121.18-79121.117"
- wire $eq$libresoc.v:79121$3655_Y
- attribute \src "libresoc.v:79122.18-79122.127"
- wire $eq$libresoc.v:79122$3656_Y
- attribute \src "libresoc.v:79125.18-79125.127"
- wire $eq$libresoc.v:79125$3659_Y
- attribute \src "libresoc.v:79129.18-79129.122"
- wire $eq$libresoc.v:79129$3663_Y
- attribute \src "libresoc.v:79130.18-79130.122"
- wire $eq$libresoc.v:79130$3664_Y
- attribute \src "libresoc.v:79132.18-79132.110"
- wire $eq$libresoc.v:79132$3666_Y
- attribute \src "libresoc.v:79133.18-79133.110"
- wire $eq$libresoc.v:79133$3667_Y
- attribute \src "libresoc.v:79135.18-79135.112"
- wire $eq$libresoc.v:79135$3669_Y
- attribute \src "libresoc.v:79137.18-79137.110"
- wire $eq$libresoc.v:79137$3671_Y
- attribute \src "libresoc.v:79139.18-79139.127"
- wire $eq$libresoc.v:79139$3673_Y
- attribute \src "libresoc.v:79142.18-79142.127"
- wire $eq$libresoc.v:79142$3676_Y
- attribute \src "libresoc.v:79107.19-79107.124"
- wire width 7 $extend$libresoc.v:79107$3638_Y
- attribute \src "libresoc.v:79108.19-79108.124"
- wire width 7 $extend$libresoc.v:79108$3640_Y
- attribute \src "libresoc.v:79109.19-79109.123"
- wire width 7 $extend$libresoc.v:79109$3642_Y
- attribute \src "libresoc.v:79146.18-79146.111"
- wire width 7 $extend$libresoc.v:79146$3680_Y
- attribute \src "libresoc.v:79147.18-79147.111"
- wire width 7 $extend$libresoc.v:79147$3682_Y
- attribute \src "libresoc.v:79148.18-79148.111"
- wire width 7 $extend$libresoc.v:79148$3684_Y
- attribute \src "libresoc.v:79149.18-79149.113"
- wire width 7 $extend$libresoc.v:79149$3686_Y
- attribute \src "libresoc.v:79150.18-79150.121"
- wire width 7 $extend$libresoc.v:79150$3688_Y
- attribute \src "libresoc.v:79127.18-79127.110"
- wire $not$libresoc.v:79127$3661_Y
- attribute \src "libresoc.v:79144.18-79144.110"
- wire $not$libresoc.v:79144$3678_Y
- attribute \src "libresoc.v:79120.18-79120.111"
- wire $or$libresoc.v:79120$3654_Y
- attribute \src "libresoc.v:79131.18-79131.110"
- wire $or$libresoc.v:79131$3665_Y
- attribute \src "libresoc.v:79134.18-79134.110"
- wire $or$libresoc.v:79134$3668_Y
- attribute \src "libresoc.v:79136.18-79136.110"
- wire $or$libresoc.v:79136$3670_Y
- attribute \src "libresoc.v:79138.18-79138.110"
- wire $or$libresoc.v:79138$3672_Y
- attribute \src "libresoc.v:79107.19-79107.124"
- wire width 7 $pos$libresoc.v:79107$3639_Y
- attribute \src "libresoc.v:79108.19-79108.124"
- wire width 7 $pos$libresoc.v:79108$3641_Y
- attribute \src "libresoc.v:79109.19-79109.123"
- wire width 7 $pos$libresoc.v:79109$3643_Y
- attribute \src "libresoc.v:79146.18-79146.111"
- wire width 7 $pos$libresoc.v:79146$3681_Y
- attribute \src "libresoc.v:79147.18-79147.111"
- wire width 7 $pos$libresoc.v:79147$3683_Y
- attribute \src "libresoc.v:79148.18-79148.111"
- wire width 7 $pos$libresoc.v:79148$3685_Y
- attribute \src "libresoc.v:79149.18-79149.113"
- wire width 7 $pos$libresoc.v:79149$3687_Y
- attribute \src "libresoc.v:79150.18-79150.121"
- wire width 7 $pos$libresoc.v:79150$3689_Y
+ attribute \src "libresoc.v:78939.19-78939.122"
+ wire $and$libresoc.v:78939$3632_Y
+ attribute \src "libresoc.v:78940.19-78940.125"
+ wire $and$libresoc.v:78940$3633_Y
+ attribute \src "libresoc.v:78941.19-78941.126"
+ wire $and$libresoc.v:78941$3634_Y
+ attribute \src "libresoc.v:78948.18-78948.114"
+ wire $and$libresoc.v:78948$3641_Y
+ attribute \src "libresoc.v:78949.18-78949.116"
+ wire $and$libresoc.v:78949$3642_Y
+ attribute \src "libresoc.v:78951.18-78951.114"
+ wire $and$libresoc.v:78951$3644_Y
+ attribute \src "libresoc.v:78953.18-78953.110"
+ wire $and$libresoc.v:78953$3646_Y
+ attribute \src "libresoc.v:78965.18-78965.114"
+ wire $and$libresoc.v:78965$3658_Y
+ attribute \src "libresoc.v:78966.18-78966.116"
+ wire $and$libresoc.v:78966$3659_Y
+ attribute \src "libresoc.v:78968.18-78968.114"
+ wire $and$libresoc.v:78968$3661_Y
+ attribute \src "libresoc.v:78970.18-78970.110"
+ wire $and$libresoc.v:78970$3663_Y
+ attribute \src "libresoc.v:78935.19-78935.124"
+ wire $eq$libresoc.v:78935$3628_Y
+ attribute \src "libresoc.v:78936.19-78936.124"
+ wire $eq$libresoc.v:78936$3629_Y
+ attribute \src "libresoc.v:78937.19-78937.124"
+ wire $eq$libresoc.v:78937$3630_Y
+ attribute \src "libresoc.v:78938.19-78938.124"
+ wire $eq$libresoc.v:78938$3631_Y
+ attribute \src "libresoc.v:78942.19-78942.124"
+ wire $eq$libresoc.v:78942$3635_Y
+ attribute \src "libresoc.v:78943.18-78943.117"
+ wire $eq$libresoc.v:78943$3636_Y
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+ wire $eq$libresoc.v:78958$3651_Y
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+ wire $eq$libresoc.v:78960$3653_Y
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+ wire $eq$libresoc.v:78967$3660_Y
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+ wire width 7 $extend$libresoc.v:78932$3622_Y
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+ wire width 7 $extend$libresoc.v:78933$3624_Y
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+ wire width 7 $extend$libresoc.v:78972$3666_Y
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+ wire width 7 $extend$libresoc.v:78974$3670_Y
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+ wire width 7 $extend$libresoc.v:78975$3672_Y
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+ wire width 7 $pos$libresoc.v:78932$3623_Y
+ attribute \src "libresoc.v:78933.19-78933.124"
+ wire width 7 $pos$libresoc.v:78933$3625_Y
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+ wire width 7 $pos$libresoc.v:78934$3627_Y
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+ wire width 7 $pos$libresoc.v:78971$3665_Y
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+ wire width 7 $pos$libresoc.v:78972$3667_Y
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+ attribute \src "libresoc.v:78974.18-78974.113"
+ wire width 7 $pos$libresoc.v:78974$3671_Y
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+ wire width 7 $pos$libresoc.v:78975$3673_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 7 \$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 14 output 42 \fn_unit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217"
wire \illeg_ok
- attribute \src "libresoc.v:77408.7-77408.15"
+ attribute \src "libresoc.v:77233.7-77233.15"
wire \initial
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire output 21 \xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
- cell $and $and$libresoc.v:79114$3648
+ cell $and $and$libresoc.v:78939$3632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_eint
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:79114$3648_Y
+ connect \Y $and$libresoc.v:78939$3632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221"
- cell $and $and$libresoc.v:79115$3649
+ cell $and $and$libresoc.v:78940$3633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_dec [63]
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:79115$3649_Y
+ connect \Y $and$libresoc.v:78940$3633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
- cell $and $and$libresoc.v:79116$3650
+ cell $and $and$libresoc.v:78941$3634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_priv_insn
connect \B \cur_msr [14]
- connect \Y $and$libresoc.v:79116$3650_Y
+ connect \Y $and$libresoc.v:78941$3634_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:79123$3657
+ cell $and $and$libresoc.v:78948$3641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$37
- connect \Y $and$libresoc.v:79123$3657_Y
+ connect \Y $and$libresoc.v:78948$3641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:79124$3658
+ cell $and $and$libresoc.v:78949$3642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:79124$3658_Y
+ connect \Y $and$libresoc.v:78949$3642_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:79126$3660
+ cell $and $and$libresoc.v:78951$3644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$43
- connect \Y $and$libresoc.v:79126$3660_Y
+ connect \Y $and$libresoc.v:78951$3644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:79128$3662
+ cell $and $and$libresoc.v:78953$3646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$45
connect \B \$47
- connect \Y $and$libresoc.v:79128$3662_Y
+ connect \Y $and$libresoc.v:78953$3646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:79140$3674
+ cell $and $and$libresoc.v:78965$3658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$71
- connect \Y $and$libresoc.v:79140$3674_Y
+ connect \Y $and$libresoc.v:78965$3658_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:79141$3675
+ cell $and $and$libresoc.v:78966$3659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:79141$3675_Y
+ connect \Y $and$libresoc.v:78966$3659_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:79143$3677
+ cell $and $and$libresoc.v:78968$3661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$77
- connect \Y $and$libresoc.v:79143$3677_Y
+ connect \Y $and$libresoc.v:78968$3661_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:79145$3679
+ cell $and $and$libresoc.v:78970$3663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$79
connect \B \$81
- connect \Y $and$libresoc.v:79145$3679_Y
+ connect \Y $and$libresoc.v:78970$3663_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189"
- cell $eq $eq$libresoc.v:79110$3644
+ cell $eq $eq$libresoc.v:78935$3628
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:79110$3644_Y
+ connect \Y $eq$libresoc.v:78935$3628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191"
- cell $eq $eq$libresoc.v:79111$3645
+ cell $eq $eq$libresoc.v:78936$3629
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0001010
- connect \Y $eq$libresoc.v:79111$3645_Y
+ connect \Y $eq$libresoc.v:78936$3629_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193"
- cell $eq $eq$libresoc.v:79112$3646
+ cell $eq $eq$libresoc.v:78937$3630
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:79112$3646_Y
+ connect \Y $eq$libresoc.v:78937$3630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197"
- cell $eq $eq$libresoc.v:79113$3647
+ cell $eq $eq$libresoc.v:78938$3631
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0111111
- connect \Y $eq$libresoc.v:79113$3647_Y
+ connect \Y $eq$libresoc.v:78938$3631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223"
- cell $eq $eq$libresoc.v:79117$3651
+ cell $eq $eq$libresoc.v:78942$3635
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0000000
- connect \Y $eq$libresoc.v:79117$3651_Y
+ connect \Y $eq$libresoc.v:78942$3635_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271"
- cell $eq $eq$libresoc.v:79118$3652
+ cell $eq $eq$libresoc.v:78943$3636
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'0111111
- connect \Y $eq$libresoc.v:79118$3652_Y
+ connect \Y $eq$libresoc.v:78943$3636_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
- cell $eq $eq$libresoc.v:79119$3653
+ cell $eq $eq$libresoc.v:78944$3637
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'1001001
- connect \Y $eq$libresoc.v:79119$3653_Y
+ connect \Y $eq$libresoc.v:78944$3637_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281"
- cell $eq $eq$libresoc.v:79121$3655
+ cell $eq $eq$libresoc.v:78946$3639
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'1000110
- connect \Y $eq$libresoc.v:79121$3655_Y
+ connect \Y $eq$libresoc.v:78946$3639_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:79122$3656
+ cell $eq $eq$libresoc.v:78947$3640
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:79122$3656_Y
+ connect \Y $eq$libresoc.v:78947$3640_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:79125$3659
+ cell $eq $eq$libresoc.v:78950$3643
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:79125$3659_Y
+ connect \Y $eq$libresoc.v:78950$3643_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:79129$3663
+ cell $eq $eq$libresoc.v:78954$3647
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:79129$3663_Y
+ connect \Y $eq$libresoc.v:78954$3647_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:79130$3664
+ cell $eq $eq$libresoc.v:78955$3648
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:79130$3664_Y
+ connect \Y $eq$libresoc.v:78955$3648_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:79132$3666
+ cell $eq $eq$libresoc.v:78957$3650
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:79132$3666_Y
+ connect \Y $eq$libresoc.v:78957$3650_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:79133$3667
+ cell $eq $eq$libresoc.v:78958$3651
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:79133$3667_Y
+ connect \Y $eq$libresoc.v:78958$3651_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:79135$3669
+ cell $eq $eq$libresoc.v:78960$3653
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:79135$3669_Y
+ connect \Y $eq$libresoc.v:78960$3653_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:79137$3671
+ cell $eq $eq$libresoc.v:78962$3655
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:79137$3671_Y
+ connect \Y $eq$libresoc.v:78962$3655_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:79139$3673
+ cell $eq $eq$libresoc.v:78964$3657
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:79139$3673_Y
+ connect \Y $eq$libresoc.v:78964$3657_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:79142$3676
+ cell $eq $eq$libresoc.v:78967$3660
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:79142$3676_Y
+ connect \Y $eq$libresoc.v:78967$3660_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79107$3638
+ cell $pos $extend$libresoc.v:78932$3622
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 7
connect \A \dec_cr_in_cr_bitfield_b
- connect \Y $extend$libresoc.v:79107$3638_Y
+ connect \Y $extend$libresoc.v:78932$3622_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79108$3640
+ cell $pos $extend$libresoc.v:78933$3624
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 7
connect \A \dec_cr_in_cr_bitfield_o
- connect \Y $extend$libresoc.v:79108$3640_Y
+ connect \Y $extend$libresoc.v:78933$3624_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79109$3642
+ cell $pos $extend$libresoc.v:78934$3626
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 7
connect \A \dec_cr_out_cr_bitfield
- connect \Y $extend$libresoc.v:79109$3642_Y
+ connect \Y $extend$libresoc.v:78934$3626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79146$3680
+ cell $pos $extend$libresoc.v:78971$3664
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \dec_a_reg_a
- connect \Y $extend$libresoc.v:79146$3680_Y
+ connect \Y $extend$libresoc.v:78971$3664_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79147$3682
+ cell $pos $extend$libresoc.v:78972$3666
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \dec_c_reg_c
- connect \Y $extend$libresoc.v:79147$3682_Y
+ connect \Y $extend$libresoc.v:78972$3666_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79148$3684
+ cell $pos $extend$libresoc.v:78973$3668
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \dec_o_reg_o
- connect \Y $extend$libresoc.v:79148$3684_Y
+ connect \Y $extend$libresoc.v:78973$3668_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79149$3686
+ cell $pos $extend$libresoc.v:78974$3670
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \dec_o2_reg_o2
- connect \Y $extend$libresoc.v:79149$3686_Y
+ connect \Y $extend$libresoc.v:78974$3670_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:79150$3688
+ cell $pos $extend$libresoc.v:78975$3672
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 7
connect \A \dec_cr_in_cr_bitfield
- connect \Y $extend$libresoc.v:79150$3688_Y
+ connect \Y $extend$libresoc.v:78975$3672_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:79127$3661
+ cell $not $not$libresoc.v:78952$3645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:79127$3661_Y
+ connect \Y $not$libresoc.v:78952$3645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:79144$3678
+ cell $not $not$libresoc.v:78969$3662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:79144$3678_Y
+ connect \Y $not$libresoc.v:78969$3662_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
- cell $or $or$libresoc.v:79120$3654
+ cell $or $or$libresoc.v:78945$3638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$28
connect \B \$30
- connect \Y $or$libresoc.v:79120$3654_Y
+ connect \Y $or$libresoc.v:78945$3638_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:79131$3665
+ cell $or $or$libresoc.v:78956$3649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \$53
- connect \Y $or$libresoc.v:79131$3665_Y
+ connect \Y $or$libresoc.v:78956$3649_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:79134$3668
+ cell $or $or$libresoc.v:78959$3652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$57
connect \B \$59
- connect \Y $or$libresoc.v:79134$3668_Y
+ connect \Y $or$libresoc.v:78959$3652_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:79136$3670
+ cell $or $or$libresoc.v:78961$3654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$61
connect \B \$63
- connect \Y $or$libresoc.v:79136$3670_Y
+ connect \Y $or$libresoc.v:78961$3654_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:79138$3672
+ cell $or $or$libresoc.v:78963$3656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$65
connect \B \$67
- connect \Y $or$libresoc.v:79138$3672_Y
+ connect \Y $or$libresoc.v:78963$3656_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79107$3639
+ cell $pos $pos$libresoc.v:78932$3623
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79107$3638_Y
- connect \Y $pos$libresoc.v:79107$3639_Y
+ connect \A $extend$libresoc.v:78932$3622_Y
+ connect \Y $pos$libresoc.v:78932$3623_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79108$3641
+ cell $pos $pos$libresoc.v:78933$3625
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79108$3640_Y
- connect \Y $pos$libresoc.v:79108$3641_Y
+ connect \A $extend$libresoc.v:78933$3624_Y
+ connect \Y $pos$libresoc.v:78933$3625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79109$3643
+ cell $pos $pos$libresoc.v:78934$3627
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79109$3642_Y
- connect \Y $pos$libresoc.v:79109$3643_Y
+ connect \A $extend$libresoc.v:78934$3626_Y
+ connect \Y $pos$libresoc.v:78934$3627_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79146$3681
+ cell $pos $pos$libresoc.v:78971$3665
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79146$3680_Y
- connect \Y $pos$libresoc.v:79146$3681_Y
+ connect \A $extend$libresoc.v:78971$3664_Y
+ connect \Y $pos$libresoc.v:78971$3665_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79147$3683
+ cell $pos $pos$libresoc.v:78972$3667
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79147$3682_Y
- connect \Y $pos$libresoc.v:79147$3683_Y
+ connect \A $extend$libresoc.v:78972$3666_Y
+ connect \Y $pos$libresoc.v:78972$3667_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79148$3685
+ cell $pos $pos$libresoc.v:78973$3669
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79148$3684_Y
- connect \Y $pos$libresoc.v:79148$3685_Y
+ connect \A $extend$libresoc.v:78973$3668_Y
+ connect \Y $pos$libresoc.v:78973$3669_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79149$3687
+ cell $pos $pos$libresoc.v:78974$3671
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79149$3686_Y
- connect \Y $pos$libresoc.v:79149$3687_Y
+ connect \A $extend$libresoc.v:78974$3670_Y
+ connect \Y $pos$libresoc.v:78974$3671_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:79150$3689
+ cell $pos $pos$libresoc.v:78975$3673
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:79150$3688_Y
- connect \Y $pos$libresoc.v:79150$3689_Y
+ connect \A $extend$libresoc.v:78975$3672_Y
+ connect \Y $pos$libresoc.v:78975$3673_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79151.13-79188.4"
+ attribute \src "libresoc.v:78976.13-79013.4"
cell \dec$171 \dec
connect \BA \dec_BA
connect \BB \dec_BB
connect \upd \dec_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79189.9-79204.4"
+ attribute \src "libresoc.v:79014.9-79029.4"
cell \dec_a \dec_a
connect \BO \dec_BO
connect \RA \dec_RA
connect \sv_nz \dec_a_sv_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79205.9-79215.4"
+ attribute \src "libresoc.v:79030.9-79040.4"
cell \dec_b \dec_b
connect \RB \dec_RB
connect \RS \dec_RS
connect \sel_in \dec_b_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79216.9-79222.4"
+ attribute \src "libresoc.v:79041.9-79047.4"
cell \dec_c \dec_c
connect \RB \dec_RB
connect \RS \dec_RS
connect \sel_in \dec_c_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79223.13-79242.4"
+ attribute \src "libresoc.v:79048.13-79067.4"
cell \dec_cr_in \dec_cr_in$10
connect \BA \dec_BA
connect \BB \dec_BB
connect \sel_in \dec_cr_in_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79243.14-79255.4"
+ attribute \src "libresoc.v:79068.14-79080.4"
cell \dec_cr_out \dec_cr_out$11
connect \FXM \dec_FXM
connect \XL_BT \dec_XL_BT
connect \sel_in \dec_cr_out_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79256.9-79269.4"
+ attribute \src "libresoc.v:79081.9-79094.4"
cell \dec_o \dec_o
connect \BO \dec_BO
connect \RA \dec_RA
connect \spr_o_ok \dec_o_spr_o_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79270.10-79279.4"
+ attribute \src "libresoc.v:79095.10-79104.4"
cell \dec_o2 \dec_o2
connect \RA \dec_RA
connect \fast_o2 \dec_o2_fast_o2
connect \upd \dec_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79280.16-79286.4"
+ attribute \src "libresoc.v:79105.16-79111.4"
cell \dec_oe$173 \dec_oe
connect \OE \dec_OE
connect \internal_op \dec_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79287.16-79292.4"
+ attribute \src "libresoc.v:79112.16-79117.4"
cell \dec_rc$172 \dec_rc
connect \Rc \dec_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:77408.7-77408.20"
- process $proc$libresoc.v:77408$3748
+ attribute \src "libresoc.v:77233.7-77233.20"
+ process $proc$libresoc.v:77233$3732
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:79293.3-79307.6"
- process $proc$libresoc.v:79293$3690
+ attribute \src "libresoc.v:79118.3-79132.6"
+ process $proc$libresoc.v:79118$3674
assign { } { }
assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0]
- attribute \src "libresoc.v:79294.5-79294.29"
+ attribute \src "libresoc.v:79119.5-79119.29"
switch \initial
- attribute \src "libresoc.v:79294.9-79294.17"
+ attribute \src "libresoc.v:79119.9-79119.17"
case 1'1
case
end
sync always
update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0]
end
- attribute \src "libresoc.v:79308.3-79317.6"
- process $proc$libresoc.v:79308$3691
+ attribute \src "libresoc.v:79133.3-79142.6"
+ process $proc$libresoc.v:79133$3675
assign { } { }
assign { } { }
assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79309.5-79309.29"
+ attribute \src "libresoc.v:79134.5-79134.29"
switch \initial
- attribute \src "libresoc.v:79309.9-79309.17"
+ attribute \src "libresoc.v:79134.9-79134.17"
case 1'1
case
end
sync always
update \tmp_tmp_lk $0\tmp_tmp_lk[0:0]
end
- attribute \src "libresoc.v:79318.3-79330.6"
- process $proc$libresoc.v:79318$3692
+ attribute \src "libresoc.v:79143.3-79155.6"
+ process $proc$libresoc.v:79143$3676
assign { } { }
assign { } { }
assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79319.5-79319.29"
+ attribute \src "libresoc.v:79144.5-79144.29"
switch \initial
- attribute \src "libresoc.v:79319.9-79319.17"
+ attribute \src "libresoc.v:79144.9-79144.17"
case 1'1
case
end
sync always
update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0]
end
- attribute \src "libresoc.v:79331.3-79346.6"
- process $proc$libresoc.v:79331$3693
+ attribute \src "libresoc.v:79156.3-79171.6"
+ process $proc$libresoc.v:79156$3677
assign { } { }
assign { } { }
assign { } { }
assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79332.5-79332.29"
+ attribute \src "libresoc.v:79157.5-79157.29"
switch \initial
- attribute \src "libresoc.v:79332.9-79332.17"
+ attribute \src "libresoc.v:79157.9-79157.17"
case 1'1
case
end
sync always
update \tmp_xer_in $0\tmp_xer_in[2:0]
end
- attribute \src "libresoc.v:79347.3-79356.6"
- process $proc$libresoc.v:79347$3694
+ attribute \src "libresoc.v:79172.3-79181.6"
+ process $proc$libresoc.v:79172$3678
assign { } { }
assign { } { }
assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79348.5-79348.29"
+ attribute \src "libresoc.v:79173.5-79173.29"
switch \initial
- attribute \src "libresoc.v:79348.9-79348.17"
+ attribute \src "libresoc.v:79173.9-79173.17"
case 1'1
case
end
sync always
update \tmp_xer_out $0\tmp_xer_out[0:0]
end
- attribute \src "libresoc.v:79357.3-79366.6"
- process $proc$libresoc.v:79357$3695
+ attribute \src "libresoc.v:79182.3-79191.6"
+ process $proc$libresoc.v:79182$3679
assign { } { }
assign { } { }
assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79358.5-79358.29"
+ attribute \src "libresoc.v:79183.5-79183.29"
switch \initial
- attribute \src "libresoc.v:79358.9-79358.17"
+ attribute \src "libresoc.v:79183.9-79183.17"
case 1'1
case
end
sync always
update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0]
end
- attribute \src "libresoc.v:79367.3-79390.6"
- process $proc$libresoc.v:79367$3696
+ attribute \src "libresoc.v:79192.3-79215.6"
+ process $proc$libresoc.v:79192$3680
assign { } { }
assign { } { }
assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:79368.5-79368.29"
+ attribute \src "libresoc.v:79193.5-79193.29"
switch \initial
- attribute \src "libresoc.v:79368.9-79368.17"
+ attribute \src "libresoc.v:79193.9-79193.17"
case 1'1
case
end
sync always
update \is_priv_insn $0\is_priv_insn[0:0]
end
- attribute \src "libresoc.v:79391.3-79548.6"
- process $proc$libresoc.v:79391$3697
+ attribute \src "libresoc.v:79216.3-79373.6"
+ process $proc$libresoc.v:79216$3681
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_in1[6:0] $1\cr_in1[6:0]
assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0]
assign $0\cr_in2[6:0] $1\cr_in2[6:0]
- assign $0\cr_in2$1[6:0]$3698 $1\cr_in2$1[6:0]$3708
+ assign $0\cr_in2$1[6:0]$3682 $1\cr_in2$1[6:0]$3692
assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0]
- assign $0\cr_in2_ok$2[0:0]$3699 $1\cr_in2_ok$2[0:0]$3709
+ assign $0\cr_in2_ok$2[0:0]$3683 $1\cr_in2_ok$2[0:0]$3693
assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0]
assign $0\cr_rd[7:0] $1\cr_rd[7:0]
assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0]
assign $0\cr_wr[7:0] $1\cr_wr[7:0]
assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0]
- assign $0\exc_$signal[0:0]$3700 $1\exc_$signal[0:0]$3710
- assign $0\exc_$signal$3[0:0]$3701 $1\exc_$signal$3[0:0]$3711
- assign $0\exc_$signal$4[0:0]$3702 $1\exc_$signal$4[0:0]$3712
- assign $0\exc_$signal$5[0:0]$3703 $1\exc_$signal$5[0:0]$3713
- assign $0\exc_$signal$6[0:0]$3704 $1\exc_$signal$6[0:0]$3714
- assign $0\exc_$signal$7[0:0]$3705 $1\exc_$signal$7[0:0]$3715
- assign $0\exc_$signal$8[0:0]$3706 $1\exc_$signal$8[0:0]$3716
- assign $0\exc_$signal$9[0:0]$3707 $1\exc_$signal$9[0:0]$3717
+ assign $0\exc_$signal[0:0]$3684 $1\exc_$signal[0:0]$3694
+ assign $0\exc_$signal$3[0:0]$3685 $1\exc_$signal$3[0:0]$3695
+ assign $0\exc_$signal$4[0:0]$3686 $1\exc_$signal$4[0:0]$3696
+ assign $0\exc_$signal$5[0:0]$3687 $1\exc_$signal$5[0:0]$3697
+ assign $0\exc_$signal$6[0:0]$3688 $1\exc_$signal$6[0:0]$3698
+ assign $0\exc_$signal$7[0:0]$3689 $1\exc_$signal$7[0:0]$3699
+ assign $0\exc_$signal$8[0:0]$3690 $1\exc_$signal$8[0:0]$3700
+ assign $0\exc_$signal$9[0:0]$3691 $1\exc_$signal$9[0:0]$3701
assign { } { }
assign { } { }
assign { } { }
assign $0\fast2[2:0] $5\fast2[2:0]
assign $0\fast2_ok[0:0] $5\fast2_ok[0:0]
assign $0\asmcode[7:0] \dec_asmcode
- attribute \src "libresoc.v:79392.5-79392.29"
+ attribute \src "libresoc.v:79217.5-79217.29"
switch \initial
- attribute \src "libresoc.v:79392.9-79392.17"
+ attribute \src "libresoc.v:79217.9-79217.17"
case 1'1
case
end
assign $1\cr_in1[6:0] $2\cr_in1[6:0]
assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0]
assign $1\cr_in2[6:0] $2\cr_in2[6:0]
- assign $1\cr_in2$1[6:0]$3708 $2\cr_in2$1[6:0]$3718
+ assign $1\cr_in2$1[6:0]$3692 $2\cr_in2$1[6:0]$3702
assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0]
- assign $1\cr_in2_ok$2[0:0]$3709 $2\cr_in2_ok$2[0:0]$3719
+ assign $1\cr_in2_ok$2[0:0]$3693 $2\cr_in2_ok$2[0:0]$3703
assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0]
assign $1\cr_rd[7:0] $2\cr_rd[7:0]
assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0]
assign $1\cr_wr[7:0] $2\cr_wr[7:0]
assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0]
- assign $1\exc_$signal[0:0]$3710 $2\exc_$signal[0:0]$3720
- assign $1\exc_$signal$3[0:0]$3711 $2\exc_$signal$3[0:0]$3721
- assign $1\exc_$signal$4[0:0]$3712 $2\exc_$signal$4[0:0]$3722
- assign $1\exc_$signal$5[0:0]$3713 $2\exc_$signal$5[0:0]$3723
- assign $1\exc_$signal$6[0:0]$3714 $2\exc_$signal$6[0:0]$3724
- assign $1\exc_$signal$7[0:0]$3715 $2\exc_$signal$7[0:0]$3725
- assign $1\exc_$signal$8[0:0]$3716 $2\exc_$signal$8[0:0]$3726
- assign $1\exc_$signal$9[0:0]$3717 $2\exc_$signal$9[0:0]$3727
+ assign $1\exc_$signal[0:0]$3694 $2\exc_$signal[0:0]$3704
+ assign $1\exc_$signal$3[0:0]$3695 $2\exc_$signal$3[0:0]$3705
+ assign $1\exc_$signal$4[0:0]$3696 $2\exc_$signal$4[0:0]$3706
+ assign $1\exc_$signal$5[0:0]$3697 $2\exc_$signal$5[0:0]$3707
+ assign $1\exc_$signal$6[0:0]$3698 $2\exc_$signal$6[0:0]$3708
+ assign $1\exc_$signal$7[0:0]$3699 $2\exc_$signal$7[0:0]$3709
+ assign $1\exc_$signal$8[0:0]$3700 $2\exc_$signal$8[0:0]$3710
+ assign $1\exc_$signal$9[0:0]$3701 $2\exc_$signal$9[0:0]$3711
assign $1\fasto1[2:0] $2\fasto1[2:0]
assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0]
assign $1\fasto2[2:0] $2\fasto2[2:0]
assign { } { }
assign { } { }
assign { } { }
- assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3727 $2\exc_$signal$8[0:0]$3726 $2\exc_$signal$7[0:0]$3725 $2\exc_$signal$6[0:0]$3724 $2\exc_$signal$5[0:0]$3723 $2\exc_$signal$4[0:0]$3722 $2\exc_$signal$3[0:0]$3721 $2\exc_$signal[0:0]$3720 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3719 $2\cr_in2$1[6:0]$3718 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3711 $2\exc_$signal$8[0:0]$3710 $2\exc_$signal$7[0:0]$3709 $2\exc_$signal$6[0:0]$3708 $2\exc_$signal$5[0:0]$3707 $2\exc_$signal$4[0:0]$3706 $2\exc_$signal$3[0:0]$3705 $2\exc_$signal[0:0]$3704 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3703 $2\cr_in2$1[6:0]$3702 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $2\insn[31:0] \dec_opcode_in
assign $2\insn_type[6:0] 7'0111111
assign $2\fn_unit[13:0] 14'00000010000000
assign $2\cr_in1[6:0] $3\cr_in1[6:0]
assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0]
assign $2\cr_in2[6:0] $3\cr_in2[6:0]
- assign $2\cr_in2$1[6:0]$3718 $3\cr_in2$1[6:0]$3728
+ assign $2\cr_in2$1[6:0]$3702 $3\cr_in2$1[6:0]$3712
assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0]
- assign $2\cr_in2_ok$2[0:0]$3719 $3\cr_in2_ok$2[0:0]$3729
+ assign $2\cr_in2_ok$2[0:0]$3703 $3\cr_in2_ok$2[0:0]$3713
assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0]
assign $2\cr_rd[7:0] $3\cr_rd[7:0]
assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0]
assign $2\cr_wr[7:0] $3\cr_wr[7:0]
assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0]
- assign $2\exc_$signal[0:0]$3720 $3\exc_$signal[0:0]$3730
- assign $2\exc_$signal$3[0:0]$3721 $3\exc_$signal$3[0:0]$3731
- assign $2\exc_$signal$4[0:0]$3722 $3\exc_$signal$4[0:0]$3732
- assign $2\exc_$signal$5[0:0]$3723 $3\exc_$signal$5[0:0]$3733
- assign $2\exc_$signal$6[0:0]$3724 $3\exc_$signal$6[0:0]$3734
- assign $2\exc_$signal$7[0:0]$3725 $3\exc_$signal$7[0:0]$3735
- assign $2\exc_$signal$8[0:0]$3726 $3\exc_$signal$8[0:0]$3736
- assign $2\exc_$signal$9[0:0]$3727 $3\exc_$signal$9[0:0]$3737
+ assign $2\exc_$signal[0:0]$3704 $3\exc_$signal[0:0]$3714
+ assign $2\exc_$signal$3[0:0]$3705 $3\exc_$signal$3[0:0]$3715
+ assign $2\exc_$signal$4[0:0]$3706 $3\exc_$signal$4[0:0]$3716
+ assign $2\exc_$signal$5[0:0]$3707 $3\exc_$signal$5[0:0]$3717
+ assign $2\exc_$signal$6[0:0]$3708 $3\exc_$signal$6[0:0]$3718
+ assign $2\exc_$signal$7[0:0]$3709 $3\exc_$signal$7[0:0]$3719
+ assign $2\exc_$signal$8[0:0]$3710 $3\exc_$signal$8[0:0]$3720
+ assign $2\exc_$signal$9[0:0]$3711 $3\exc_$signal$9[0:0]$3721
assign $2\fasto1[2:0] $3\fasto1[2:0]
assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0]
assign $2\fasto2[2:0] $3\fasto2[2:0]
assign { } { }
assign { } { }
assign { } { }
- assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $3\insn[31:0] \dec_opcode_in
assign $3\insn_type[6:0] 7'0111111
assign $3\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $3\insn[31:0] \dec_opcode_in
assign $3\insn_type[6:0] 7'0111111
assign $3\fn_unit[13:0] 14'00000010000000
assign $3\trapaddr[12:0] 13'0000001000000
assign $3\traptype[7:0] 8'01000000
- assign { $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal }
+ assign { $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal }
assign $3\msr[63:0] \cur_msr
assign $3\cia[63:0] \cur_pc
end
assign $2\cr_in1[6:0] $4\cr_in1[6:0]
assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0]
assign $2\cr_in2[6:0] $4\cr_in2[6:0]
- assign $2\cr_in2$1[6:0]$3718 $4\cr_in2$1[6:0]$3738
+ assign $2\cr_in2$1[6:0]$3702 $4\cr_in2$1[6:0]$3722
assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0]
- assign $2\cr_in2_ok$2[0:0]$3719 $4\cr_in2_ok$2[0:0]$3739
+ assign $2\cr_in2_ok$2[0:0]$3703 $4\cr_in2_ok$2[0:0]$3723
assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0]
assign $2\cr_rd[7:0] $4\cr_rd[7:0]
assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0]
assign $2\cr_wr[7:0] $4\cr_wr[7:0]
assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0]
- assign $2\exc_$signal[0:0]$3720 $4\exc_$signal[0:0]$3740
- assign $2\exc_$signal$3[0:0]$3721 $4\exc_$signal$3[0:0]$3741
- assign $2\exc_$signal$4[0:0]$3722 $4\exc_$signal$4[0:0]$3742
- assign $2\exc_$signal$5[0:0]$3723 $4\exc_$signal$5[0:0]$3743
- assign $2\exc_$signal$6[0:0]$3724 $4\exc_$signal$6[0:0]$3744
- assign $2\exc_$signal$7[0:0]$3725 $4\exc_$signal$7[0:0]$3745
- assign $2\exc_$signal$8[0:0]$3726 $4\exc_$signal$8[0:0]$3746
- assign $2\exc_$signal$9[0:0]$3727 $4\exc_$signal$9[0:0]$3747
+ assign $2\exc_$signal[0:0]$3704 $4\exc_$signal[0:0]$3724
+ assign $2\exc_$signal$3[0:0]$3705 $4\exc_$signal$3[0:0]$3725
+ assign $2\exc_$signal$4[0:0]$3706 $4\exc_$signal$4[0:0]$3726
+ assign $2\exc_$signal$5[0:0]$3707 $4\exc_$signal$5[0:0]$3727
+ assign $2\exc_$signal$6[0:0]$3708 $4\exc_$signal$6[0:0]$3728
+ assign $2\exc_$signal$7[0:0]$3709 $4\exc_$signal$7[0:0]$3729
+ assign $2\exc_$signal$8[0:0]$3710 $4\exc_$signal$8[0:0]$3730
+ assign $2\exc_$signal$9[0:0]$3711 $4\exc_$signal$9[0:0]$3731
assign $2\fasto1[2:0] $4\fasto1[2:0]
assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0]
assign $2\fasto2[2:0] $4\fasto2[2:0]
assign { } { }
assign { } { }
assign { } { }
- assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $4\insn[31:0] \dec_opcode_in
assign $4\insn_type[6:0] 7'0111111
assign $4\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $4\insn[31:0] \dec_opcode_in
assign $4\insn_type[6:0] 7'0111111
assign $4\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[13:0] 14'00000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
switch \$32
update \cr_in1 $0\cr_in1[6:0]
update \cr_in1_ok $0\cr_in1_ok[0:0]
update \cr_in2 $0\cr_in2[6:0]
- update \cr_in2$1 $0\cr_in2$1[6:0]$3698
+ update \cr_in2$1 $0\cr_in2$1[6:0]$3682
update \cr_in2_ok $0\cr_in2_ok[0:0]
- update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3699
+ update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3683
update \cr_out_ok $0\cr_out_ok[0:0]
update \cr_rd $0\cr_rd[7:0]
update \cr_rd_ok $0\cr_rd_ok[0:0]
update \cr_wr $0\cr_wr[7:0]
update \cr_wr_ok $0\cr_wr_ok[0:0]
- update \exc_$signal $0\exc_$signal[0:0]$3700
- update \exc_$signal$3 $0\exc_$signal$3[0:0]$3701
- update \exc_$signal$4 $0\exc_$signal$4[0:0]$3702
- update \exc_$signal$5 $0\exc_$signal$5[0:0]$3703
- update \exc_$signal$6 $0\exc_$signal$6[0:0]$3704
- update \exc_$signal$7 $0\exc_$signal$7[0:0]$3705
- update \exc_$signal$8 $0\exc_$signal$8[0:0]$3706
- update \exc_$signal$9 $0\exc_$signal$9[0:0]$3707
+ update \exc_$signal $0\exc_$signal[0:0]$3684
+ update \exc_$signal$3 $0\exc_$signal$3[0:0]$3685
+ update \exc_$signal$4 $0\exc_$signal$4[0:0]$3686
+ update \exc_$signal$5 $0\exc_$signal$5[0:0]$3687
+ update \exc_$signal$6 $0\exc_$signal$6[0:0]$3688
+ update \exc_$signal$7 $0\exc_$signal$7[0:0]$3689
+ update \exc_$signal$8 $0\exc_$signal$8[0:0]$3690
+ update \exc_$signal$9 $0\exc_$signal$9[0:0]$3691
update \fasto1 $0\fasto1[2:0]
update \fasto1_ok $0\fasto1_ok[0:0]
update \fasto2 $0\fasto2[2:0]
update \xer_in $0\xer_in[2:0]
update \xer_out $0\xer_out[0:0]
end
- connect \$100 $pos$libresoc.v:79107$3639_Y
- connect \$102 $pos$libresoc.v:79108$3641_Y
- connect \$104 $pos$libresoc.v:79109$3643_Y
- connect \$106 $eq$libresoc.v:79110$3644_Y
- connect \$108 $eq$libresoc.v:79111$3645_Y
- connect \$110 $eq$libresoc.v:79112$3646_Y
- connect \$112 $eq$libresoc.v:79113$3647_Y
- connect \$114 $and$libresoc.v:79114$3648_Y
- connect \$116 $and$libresoc.v:79115$3649_Y
- connect \$118 $and$libresoc.v:79116$3650_Y
- connect \$120 $eq$libresoc.v:79117$3651_Y
- connect \$28 $eq$libresoc.v:79118$3652_Y
- connect \$30 $eq$libresoc.v:79119$3653_Y
- connect \$32 $or$libresoc.v:79120$3654_Y
- connect \$34 $eq$libresoc.v:79121$3655_Y
- connect \$37 $eq$libresoc.v:79122$3656_Y
- connect \$39 $and$libresoc.v:79123$3657_Y
- connect \$41 $and$libresoc.v:79124$3658_Y
- connect \$43 $eq$libresoc.v:79125$3659_Y
- connect \$45 $and$libresoc.v:79126$3660_Y
- connect \$47 $not$libresoc.v:79127$3661_Y
- connect \$49 $and$libresoc.v:79128$3662_Y
- connect \$51 $eq$libresoc.v:79129$3663_Y
- connect \$53 $eq$libresoc.v:79130$3664_Y
- connect \$55 $or$libresoc.v:79131$3665_Y
- connect \$57 $eq$libresoc.v:79132$3666_Y
- connect \$59 $eq$libresoc.v:79133$3667_Y
- connect \$61 $or$libresoc.v:79134$3668_Y
- connect \$63 $eq$libresoc.v:79135$3669_Y
- connect \$65 $or$libresoc.v:79136$3670_Y
- connect \$67 $eq$libresoc.v:79137$3671_Y
- connect \$69 $or$libresoc.v:79138$3672_Y
- connect \$71 $eq$libresoc.v:79139$3673_Y
- connect \$73 $and$libresoc.v:79140$3674_Y
- connect \$75 $and$libresoc.v:79141$3675_Y
- connect \$77 $eq$libresoc.v:79142$3676_Y
- connect \$79 $and$libresoc.v:79143$3677_Y
- connect \$81 $not$libresoc.v:79144$3678_Y
- connect \$83 $and$libresoc.v:79145$3679_Y
- connect \$90 $pos$libresoc.v:79146$3681_Y
- connect \$92 $pos$libresoc.v:79147$3683_Y
- connect \$94 $pos$libresoc.v:79148$3685_Y
- connect \$96 $pos$libresoc.v:79149$3687_Y
- connect \$98 $pos$libresoc.v:79150$3689_Y
+ connect \$100 $pos$libresoc.v:78932$3623_Y
+ connect \$102 $pos$libresoc.v:78933$3625_Y
+ connect \$104 $pos$libresoc.v:78934$3627_Y
+ connect \$106 $eq$libresoc.v:78935$3628_Y
+ connect \$108 $eq$libresoc.v:78936$3629_Y
+ connect \$110 $eq$libresoc.v:78937$3630_Y
+ connect \$112 $eq$libresoc.v:78938$3631_Y
+ connect \$114 $and$libresoc.v:78939$3632_Y
+ connect \$116 $and$libresoc.v:78940$3633_Y
+ connect \$118 $and$libresoc.v:78941$3634_Y
+ connect \$120 $eq$libresoc.v:78942$3635_Y
+ connect \$28 $eq$libresoc.v:78943$3636_Y
+ connect \$30 $eq$libresoc.v:78944$3637_Y
+ connect \$32 $or$libresoc.v:78945$3638_Y
+ connect \$34 $eq$libresoc.v:78946$3639_Y
+ connect \$37 $eq$libresoc.v:78947$3640_Y
+ connect \$39 $and$libresoc.v:78948$3641_Y
+ connect \$41 $and$libresoc.v:78949$3642_Y
+ connect \$43 $eq$libresoc.v:78950$3643_Y
+ connect \$45 $and$libresoc.v:78951$3644_Y
+ connect \$47 $not$libresoc.v:78952$3645_Y
+ connect \$49 $and$libresoc.v:78953$3646_Y
+ connect \$51 $eq$libresoc.v:78954$3647_Y
+ connect \$53 $eq$libresoc.v:78955$3648_Y
+ connect \$55 $or$libresoc.v:78956$3649_Y
+ connect \$57 $eq$libresoc.v:78957$3650_Y
+ connect \$59 $eq$libresoc.v:78958$3651_Y
+ connect \$61 $or$libresoc.v:78959$3652_Y
+ connect \$63 $eq$libresoc.v:78960$3653_Y
+ connect \$65 $or$libresoc.v:78961$3654_Y
+ connect \$67 $eq$libresoc.v:78962$3655_Y
+ connect \$69 $or$libresoc.v:78963$3656_Y
+ connect \$71 $eq$libresoc.v:78964$3657_Y
+ connect \$73 $and$libresoc.v:78965$3658_Y
+ connect \$75 $and$libresoc.v:78966$3659_Y
+ connect \$77 $eq$libresoc.v:78967$3660_Y
+ connect \$79 $and$libresoc.v:78968$3661_Y
+ connect \$81 $not$libresoc.v:78969$3662_Y
+ connect \$83 $and$libresoc.v:78970$3663_Y
+ connect \$90 $pos$libresoc.v:78971$3665_Y
+ connect \$92 $pos$libresoc.v:78972$3667_Y
+ connect \$94 $pos$libresoc.v:78973$3669_Y
+ connect \$96 $pos$libresoc.v:78974$3671_Y
+ connect \$98 $pos$libresoc.v:78975$3673_Y
connect \dec2_exc_$signal 1'0
connect \dec2_exc_$signal$12 1'0
connect \dec2_exc_$signal$13 1'0
connect \insn_in$36 \dec_opcode_in
connect \insn_in \dec_opcode_in
end
-attribute \src "libresoc.v:79632.1-80312.10"
+attribute \src "libresoc.v:79457.1-80137.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22"
attribute \generator "nMigen"
module \dec22
- attribute \src "libresoc.v:80251.3-80260.6"
+ attribute \src "libresoc.v:80076.3-80085.6"
wire width 2 $0\dec22_SV_Etype[1:0]
- attribute \src "libresoc.v:80261.3-80270.6"
+ attribute \src "libresoc.v:80086.3-80095.6"
wire width 2 $0\dec22_SV_Ptype[1:0]
- attribute \src "libresoc.v:80131.3-80140.6"
+ attribute \src "libresoc.v:79956.3-79965.6"
wire width 8 $0\dec22_asmcode[7:0]
- attribute \src "libresoc.v:80171.3-80180.6"
+ attribute \src "libresoc.v:79996.3-80005.6"
wire $0\dec22_br[0:0]
- attribute \src "libresoc.v:79991.3-80000.6"
+ attribute \src "libresoc.v:79816.3-79825.6"
wire width 3 $0\dec22_cr_in[2:0]
- attribute \src "libresoc.v:80001.3-80010.6"
+ attribute \src "libresoc.v:79826.3-79835.6"
wire width 3 $0\dec22_cr_out[2:0]
- attribute \src "libresoc.v:80121.3-80130.6"
+ attribute \src "libresoc.v:79946.3-79955.6"
wire width 2 $0\dec22_cry_in[1:0]
- attribute \src "libresoc.v:80161.3-80170.6"
+ attribute \src "libresoc.v:79986.3-79995.6"
wire $0\dec22_cry_out[0:0]
- attribute \src "libresoc.v:80201.3-80210.6"
+ attribute \src "libresoc.v:80026.3-80035.6"
wire width 5 $0\dec22_form[4:0]
- attribute \src "libresoc.v:79981.3-79990.6"
+ attribute \src "libresoc.v:79806.3-79815.6"
wire width 14 $0\dec22_function_unit[13:0]
- attribute \src "libresoc.v:80271.3-80280.6"
+ attribute \src "libresoc.v:80096.3-80105.6"
wire width 3 $0\dec22_in1_sel[2:0]
- attribute \src "libresoc.v:80281.3-80290.6"
+ attribute \src "libresoc.v:80106.3-80115.6"
wire width 4 $0\dec22_in2_sel[3:0]
- attribute \src "libresoc.v:80291.3-80300.6"
+ attribute \src "libresoc.v:80116.3-80125.6"
wire width 2 $0\dec22_in3_sel[1:0]
- attribute \src "libresoc.v:80091.3-80100.6"
+ attribute \src "libresoc.v:79916.3-79925.6"
wire width 7 $0\dec22_internal_op[6:0]
- attribute \src "libresoc.v:80141.3-80150.6"
+ attribute \src "libresoc.v:79966.3-79975.6"
wire $0\dec22_inv_a[0:0]
- attribute \src "libresoc.v:80151.3-80160.6"
+ attribute \src "libresoc.v:79976.3-79985.6"
wire $0\dec22_inv_out[0:0]
- attribute \src "libresoc.v:80211.3-80220.6"
+ attribute \src "libresoc.v:80036.3-80045.6"
wire $0\dec22_is_32b[0:0]
- attribute \src "libresoc.v:80081.3-80090.6"
+ attribute \src "libresoc.v:79906.3-79915.6"
wire width 4 $0\dec22_ldst_len[3:0]
- attribute \src "libresoc.v:80231.3-80240.6"
+ attribute \src "libresoc.v:80056.3-80065.6"
wire $0\dec22_lk[0:0]
- attribute \src "libresoc.v:80301.3-80310.6"
+ attribute \src "libresoc.v:80126.3-80135.6"
wire width 3 $0\dec22_out_sel[2:0]
- attribute \src "libresoc.v:80111.3-80120.6"
+ attribute \src "libresoc.v:79936.3-79945.6"
wire width 2 $0\dec22_rc_sel[1:0]
- attribute \src "libresoc.v:80191.3-80200.6"
+ attribute \src "libresoc.v:80016.3-80025.6"
wire $0\dec22_rsrv[0:0]
- attribute \src "libresoc.v:80241.3-80250.6"
+ attribute \src "libresoc.v:80066.3-80075.6"
wire $0\dec22_sgl_pipe[0:0]
- attribute \src "libresoc.v:80221.3-80230.6"
+ attribute \src "libresoc.v:80046.3-80055.6"
wire $0\dec22_sgn[0:0]
- attribute \src "libresoc.v:80181.3-80190.6"
+ attribute \src "libresoc.v:80006.3-80015.6"
wire $0\dec22_sgn_ext[0:0]
- attribute \src "libresoc.v:80061.3-80070.6"
+ attribute \src "libresoc.v:79886.3-79895.6"
wire width 3 $0\dec22_sv_cr_in[2:0]
- attribute \src "libresoc.v:80071.3-80080.6"
+ attribute \src "libresoc.v:79896.3-79905.6"
wire width 3 $0\dec22_sv_cr_out[2:0]
- attribute \src "libresoc.v:80011.3-80020.6"
+ attribute \src "libresoc.v:79836.3-79845.6"
wire width 3 $0\dec22_sv_in1[2:0]
- attribute \src "libresoc.v:80021.3-80030.6"
+ attribute \src "libresoc.v:79846.3-79855.6"
wire width 3 $0\dec22_sv_in2[2:0]
- attribute \src "libresoc.v:80031.3-80040.6"
+ attribute \src "libresoc.v:79856.3-79865.6"
wire width 3 $0\dec22_sv_in3[2:0]
- attribute \src "libresoc.v:80051.3-80060.6"
+ attribute \src "libresoc.v:79876.3-79885.6"
wire width 3 $0\dec22_sv_out2[2:0]
- attribute \src "libresoc.v:80041.3-80050.6"
+ attribute \src "libresoc.v:79866.3-79875.6"
wire width 3 $0\dec22_sv_out[2:0]
- attribute \src "libresoc.v:80101.3-80110.6"
+ attribute \src "libresoc.v:79926.3-79935.6"
wire width 2 $0\dec22_upd[1:0]
- attribute \src "libresoc.v:79633.7-79633.20"
+ attribute \src "libresoc.v:79458.7-79458.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:80251.3-80260.6"
+ attribute \src "libresoc.v:80076.3-80085.6"
wire width 2 $1\dec22_SV_Etype[1:0]
- attribute \src "libresoc.v:80261.3-80270.6"
+ attribute \src "libresoc.v:80086.3-80095.6"
wire width 2 $1\dec22_SV_Ptype[1:0]
- attribute \src "libresoc.v:80131.3-80140.6"
+ attribute \src "libresoc.v:79956.3-79965.6"
wire width 8 $1\dec22_asmcode[7:0]
- attribute \src "libresoc.v:80171.3-80180.6"
+ attribute \src "libresoc.v:79996.3-80005.6"
wire $1\dec22_br[0:0]
- attribute \src "libresoc.v:79991.3-80000.6"
+ attribute \src "libresoc.v:79816.3-79825.6"
wire width 3 $1\dec22_cr_in[2:0]
- attribute \src "libresoc.v:80001.3-80010.6"
+ attribute \src "libresoc.v:79826.3-79835.6"
wire width 3 $1\dec22_cr_out[2:0]
- attribute \src "libresoc.v:80121.3-80130.6"
+ attribute \src "libresoc.v:79946.3-79955.6"
wire width 2 $1\dec22_cry_in[1:0]
- attribute \src "libresoc.v:80161.3-80170.6"
+ attribute \src "libresoc.v:79986.3-79995.6"
wire $1\dec22_cry_out[0:0]
- attribute \src "libresoc.v:80201.3-80210.6"
+ attribute \src "libresoc.v:80026.3-80035.6"
wire width 5 $1\dec22_form[4:0]
- attribute \src "libresoc.v:79981.3-79990.6"
+ attribute \src "libresoc.v:79806.3-79815.6"
wire width 14 $1\dec22_function_unit[13:0]
- attribute \src "libresoc.v:80271.3-80280.6"
+ attribute \src "libresoc.v:80096.3-80105.6"
wire width 3 $1\dec22_in1_sel[2:0]
- attribute \src "libresoc.v:80281.3-80290.6"
+ attribute \src "libresoc.v:80106.3-80115.6"
wire width 4 $1\dec22_in2_sel[3:0]
- attribute \src "libresoc.v:80291.3-80300.6"
+ attribute \src "libresoc.v:80116.3-80125.6"
wire width 2 $1\dec22_in3_sel[1:0]
- attribute \src "libresoc.v:80091.3-80100.6"
+ attribute \src "libresoc.v:79916.3-79925.6"
wire width 7 $1\dec22_internal_op[6:0]
- attribute \src "libresoc.v:80141.3-80150.6"
+ attribute \src "libresoc.v:79966.3-79975.6"
wire $1\dec22_inv_a[0:0]
- attribute \src "libresoc.v:80151.3-80160.6"
+ attribute \src "libresoc.v:79976.3-79985.6"
wire $1\dec22_inv_out[0:0]
- attribute \src "libresoc.v:80211.3-80220.6"
+ attribute \src "libresoc.v:80036.3-80045.6"
wire $1\dec22_is_32b[0:0]
- attribute \src "libresoc.v:80081.3-80090.6"
+ attribute \src "libresoc.v:79906.3-79915.6"
wire width 4 $1\dec22_ldst_len[3:0]
- attribute \src "libresoc.v:80231.3-80240.6"
+ attribute \src "libresoc.v:80056.3-80065.6"
wire $1\dec22_lk[0:0]
- attribute \src "libresoc.v:80301.3-80310.6"
+ attribute \src "libresoc.v:80126.3-80135.6"
wire width 3 $1\dec22_out_sel[2:0]
- attribute \src "libresoc.v:80111.3-80120.6"
+ attribute \src "libresoc.v:79936.3-79945.6"
wire width 2 $1\dec22_rc_sel[1:0]
- attribute \src "libresoc.v:80191.3-80200.6"
+ attribute \src "libresoc.v:80016.3-80025.6"
wire $1\dec22_rsrv[0:0]
- attribute \src "libresoc.v:80241.3-80250.6"
+ attribute \src "libresoc.v:80066.3-80075.6"
wire $1\dec22_sgl_pipe[0:0]
- attribute \src "libresoc.v:80221.3-80230.6"
+ attribute \src "libresoc.v:80046.3-80055.6"
wire $1\dec22_sgn[0:0]
- attribute \src "libresoc.v:80181.3-80190.6"
+ attribute \src "libresoc.v:80006.3-80015.6"
wire $1\dec22_sgn_ext[0:0]
- attribute \src "libresoc.v:80061.3-80070.6"
+ attribute \src "libresoc.v:79886.3-79895.6"
wire width 3 $1\dec22_sv_cr_in[2:0]
- attribute \src "libresoc.v:80071.3-80080.6"
+ attribute \src "libresoc.v:79896.3-79905.6"
wire width 3 $1\dec22_sv_cr_out[2:0]
- attribute \src "libresoc.v:80011.3-80020.6"
+ attribute \src "libresoc.v:79836.3-79845.6"
wire width 3 $1\dec22_sv_in1[2:0]
- attribute \src "libresoc.v:80021.3-80030.6"
+ attribute \src "libresoc.v:79846.3-79855.6"
wire width 3 $1\dec22_sv_in2[2:0]
- attribute \src "libresoc.v:80031.3-80040.6"
+ attribute \src "libresoc.v:79856.3-79865.6"
wire width 3 $1\dec22_sv_in3[2:0]
- attribute \src "libresoc.v:80051.3-80060.6"
+ attribute \src "libresoc.v:79876.3-79885.6"
wire width 3 $1\dec22_sv_out2[2:0]
- attribute \src "libresoc.v:80041.3-80050.6"
+ attribute \src "libresoc.v:79866.3-79875.6"
wire width 3 $1\dec22_sv_out[2:0]
- attribute \src "libresoc.v:80101.3-80110.6"
+ attribute \src "libresoc.v:79926.3-79935.6"
wire width 2 $1\dec22_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec22_upd
- attribute \src "libresoc.v:79633.7-79633.15"
+ attribute \src "libresoc.v:79458.7-79458.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 4 \opcode_switch
- attribute \src "libresoc.v:79633.7-79633.20"
- process $proc$libresoc.v:79633$3782
+ attribute \src "libresoc.v:79458.7-79458.20"
+ process $proc$libresoc.v:79458$3766
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:79981.3-79990.6"
- process $proc$libresoc.v:79981$3749
+ attribute \src "libresoc.v:79806.3-79815.6"
+ process $proc$libresoc.v:79806$3733
assign { } { }
assign { } { }
assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0]
- attribute \src "libresoc.v:79982.5-79982.29"
+ attribute \src "libresoc.v:79807.5-79807.29"
switch \initial
- attribute \src "libresoc.v:79982.9-79982.17"
+ attribute \src "libresoc.v:79807.9-79807.17"
case 1'1
case
end
sync always
update \dec22_function_unit $0\dec22_function_unit[13:0]
end
- attribute \src "libresoc.v:79991.3-80000.6"
- process $proc$libresoc.v:79991$3750
+ attribute \src "libresoc.v:79816.3-79825.6"
+ process $proc$libresoc.v:79816$3734
assign { } { }
assign { } { }
assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0]
- attribute \src "libresoc.v:79992.5-79992.29"
+ attribute \src "libresoc.v:79817.5-79817.29"
switch \initial
- attribute \src "libresoc.v:79992.9-79992.17"
+ attribute \src "libresoc.v:79817.9-79817.17"
case 1'1
case
end
sync always
update \dec22_cr_in $0\dec22_cr_in[2:0]
end
- attribute \src "libresoc.v:80001.3-80010.6"
- process $proc$libresoc.v:80001$3751
+ attribute \src "libresoc.v:79826.3-79835.6"
+ process $proc$libresoc.v:79826$3735
assign { } { }
assign { } { }
assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0]
- attribute \src "libresoc.v:80002.5-80002.29"
+ attribute \src "libresoc.v:79827.5-79827.29"
switch \initial
- attribute \src "libresoc.v:80002.9-80002.17"
+ attribute \src "libresoc.v:79827.9-79827.17"
case 1'1
case
end
sync always
update \dec22_cr_out $0\dec22_cr_out[2:0]
end
- attribute \src "libresoc.v:80011.3-80020.6"
- process $proc$libresoc.v:80011$3752
+ attribute \src "libresoc.v:79836.3-79845.6"
+ process $proc$libresoc.v:79836$3736
assign { } { }
assign { } { }
assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0]
- attribute \src "libresoc.v:80012.5-80012.29"
+ attribute \src "libresoc.v:79837.5-79837.29"
switch \initial
- attribute \src "libresoc.v:80012.9-80012.17"
+ attribute \src "libresoc.v:79837.9-79837.17"
case 1'1
case
end
sync always
update \dec22_sv_in1 $0\dec22_sv_in1[2:0]
end
- attribute \src "libresoc.v:80021.3-80030.6"
- process $proc$libresoc.v:80021$3753
+ attribute \src "libresoc.v:79846.3-79855.6"
+ process $proc$libresoc.v:79846$3737
assign { } { }
assign { } { }
assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0]
- attribute \src "libresoc.v:80022.5-80022.29"
+ attribute \src "libresoc.v:79847.5-79847.29"
switch \initial
- attribute \src "libresoc.v:80022.9-80022.17"
+ attribute \src "libresoc.v:79847.9-79847.17"
case 1'1
case
end
sync always
update \dec22_sv_in2 $0\dec22_sv_in2[2:0]
end
- attribute \src "libresoc.v:80031.3-80040.6"
- process $proc$libresoc.v:80031$3754
+ attribute \src "libresoc.v:79856.3-79865.6"
+ process $proc$libresoc.v:79856$3738
assign { } { }
assign { } { }
assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0]
- attribute \src "libresoc.v:80032.5-80032.29"
+ attribute \src "libresoc.v:79857.5-79857.29"
switch \initial
- attribute \src "libresoc.v:80032.9-80032.17"
+ attribute \src "libresoc.v:79857.9-79857.17"
case 1'1
case
end
sync always
update \dec22_sv_in3 $0\dec22_sv_in3[2:0]
end
- attribute \src "libresoc.v:80041.3-80050.6"
- process $proc$libresoc.v:80041$3755
+ attribute \src "libresoc.v:79866.3-79875.6"
+ process $proc$libresoc.v:79866$3739
assign { } { }
assign { } { }
assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0]
- attribute \src "libresoc.v:80042.5-80042.29"
+ attribute \src "libresoc.v:79867.5-79867.29"
switch \initial
- attribute \src "libresoc.v:80042.9-80042.17"
+ attribute \src "libresoc.v:79867.9-79867.17"
case 1'1
case
end
sync always
update \dec22_sv_out $0\dec22_sv_out[2:0]
end
- attribute \src "libresoc.v:80051.3-80060.6"
- process $proc$libresoc.v:80051$3756
+ attribute \src "libresoc.v:79876.3-79885.6"
+ process $proc$libresoc.v:79876$3740
assign { } { }
assign { } { }
assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0]
- attribute \src "libresoc.v:80052.5-80052.29"
+ attribute \src "libresoc.v:79877.5-79877.29"
switch \initial
- attribute \src "libresoc.v:80052.9-80052.17"
+ attribute \src "libresoc.v:79877.9-79877.17"
case 1'1
case
end
sync always
update \dec22_sv_out2 $0\dec22_sv_out2[2:0]
end
- attribute \src "libresoc.v:80061.3-80070.6"
- process $proc$libresoc.v:80061$3757
+ attribute \src "libresoc.v:79886.3-79895.6"
+ process $proc$libresoc.v:79886$3741
assign { } { }
assign { } { }
assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0]
- attribute \src "libresoc.v:80062.5-80062.29"
+ attribute \src "libresoc.v:79887.5-79887.29"
switch \initial
- attribute \src "libresoc.v:80062.9-80062.17"
+ attribute \src "libresoc.v:79887.9-79887.17"
case 1'1
case
end
sync always
update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:80071.3-80080.6"
- process $proc$libresoc.v:80071$3758
+ attribute \src "libresoc.v:79896.3-79905.6"
+ process $proc$libresoc.v:79896$3742
assign { } { }
assign { } { }
assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0]
- attribute \src "libresoc.v:80072.5-80072.29"
+ attribute \src "libresoc.v:79897.5-79897.29"
switch \initial
- attribute \src "libresoc.v:80072.9-80072.17"
+ attribute \src "libresoc.v:79897.9-79897.17"
case 1'1
case
end
sync always
update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:80081.3-80090.6"
- process $proc$libresoc.v:80081$3759
+ attribute \src "libresoc.v:79906.3-79915.6"
+ process $proc$libresoc.v:79906$3743
assign { } { }
assign { } { }
assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0]
- attribute \src "libresoc.v:80082.5-80082.29"
+ attribute \src "libresoc.v:79907.5-79907.29"
switch \initial
- attribute \src "libresoc.v:80082.9-80082.17"
+ attribute \src "libresoc.v:79907.9-79907.17"
case 1'1
case
end
sync always
update \dec22_ldst_len $0\dec22_ldst_len[3:0]
end
- attribute \src "libresoc.v:80091.3-80100.6"
- process $proc$libresoc.v:80091$3760
+ attribute \src "libresoc.v:79916.3-79925.6"
+ process $proc$libresoc.v:79916$3744
assign { } { }
assign { } { }
assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0]
- attribute \src "libresoc.v:80092.5-80092.29"
+ attribute \src "libresoc.v:79917.5-79917.29"
switch \initial
- attribute \src "libresoc.v:80092.9-80092.17"
+ attribute \src "libresoc.v:79917.9-79917.17"
case 1'1
case
end
sync always
update \dec22_internal_op $0\dec22_internal_op[6:0]
end
- attribute \src "libresoc.v:80101.3-80110.6"
- process $proc$libresoc.v:80101$3761
+ attribute \src "libresoc.v:79926.3-79935.6"
+ process $proc$libresoc.v:79926$3745
assign { } { }
assign { } { }
assign $0\dec22_upd[1:0] $1\dec22_upd[1:0]
- attribute \src "libresoc.v:80102.5-80102.29"
+ attribute \src "libresoc.v:79927.5-79927.29"
switch \initial
- attribute \src "libresoc.v:80102.9-80102.17"
+ attribute \src "libresoc.v:79927.9-79927.17"
case 1'1
case
end
sync always
update \dec22_upd $0\dec22_upd[1:0]
end
- attribute \src "libresoc.v:80111.3-80120.6"
- process $proc$libresoc.v:80111$3762
+ attribute \src "libresoc.v:79936.3-79945.6"
+ process $proc$libresoc.v:79936$3746
assign { } { }
assign { } { }
assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0]
- attribute \src "libresoc.v:80112.5-80112.29"
+ attribute \src "libresoc.v:79937.5-79937.29"
switch \initial
- attribute \src "libresoc.v:80112.9-80112.17"
+ attribute \src "libresoc.v:79937.9-79937.17"
case 1'1
case
end
sync always
update \dec22_rc_sel $0\dec22_rc_sel[1:0]
end
- attribute \src "libresoc.v:80121.3-80130.6"
- process $proc$libresoc.v:80121$3763
+ attribute \src "libresoc.v:79946.3-79955.6"
+ process $proc$libresoc.v:79946$3747
assign { } { }
assign { } { }
assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0]
- attribute \src "libresoc.v:80122.5-80122.29"
+ attribute \src "libresoc.v:79947.5-79947.29"
switch \initial
- attribute \src "libresoc.v:80122.9-80122.17"
+ attribute \src "libresoc.v:79947.9-79947.17"
case 1'1
case
end
sync always
update \dec22_cry_in $0\dec22_cry_in[1:0]
end
- attribute \src "libresoc.v:80131.3-80140.6"
- process $proc$libresoc.v:80131$3764
+ attribute \src "libresoc.v:79956.3-79965.6"
+ process $proc$libresoc.v:79956$3748
assign { } { }
assign { } { }
assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0]
- attribute \src "libresoc.v:80132.5-80132.29"
+ attribute \src "libresoc.v:79957.5-79957.29"
switch \initial
- attribute \src "libresoc.v:80132.9-80132.17"
+ attribute \src "libresoc.v:79957.9-79957.17"
case 1'1
case
end
sync always
update \dec22_asmcode $0\dec22_asmcode[7:0]
end
- attribute \src "libresoc.v:80141.3-80150.6"
- process $proc$libresoc.v:80141$3765
+ attribute \src "libresoc.v:79966.3-79975.6"
+ process $proc$libresoc.v:79966$3749
assign { } { }
assign { } { }
assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0]
- attribute \src "libresoc.v:80142.5-80142.29"
+ attribute \src "libresoc.v:79967.5-79967.29"
switch \initial
- attribute \src "libresoc.v:80142.9-80142.17"
+ attribute \src "libresoc.v:79967.9-79967.17"
case 1'1
case
end
sync always
update \dec22_inv_a $0\dec22_inv_a[0:0]
end
- attribute \src "libresoc.v:80151.3-80160.6"
- process $proc$libresoc.v:80151$3766
+ attribute \src "libresoc.v:79976.3-79985.6"
+ process $proc$libresoc.v:79976$3750
assign { } { }
assign { } { }
assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0]
- attribute \src "libresoc.v:80152.5-80152.29"
+ attribute \src "libresoc.v:79977.5-79977.29"
switch \initial
- attribute \src "libresoc.v:80152.9-80152.17"
+ attribute \src "libresoc.v:79977.9-79977.17"
case 1'1
case
end
sync always
update \dec22_inv_out $0\dec22_inv_out[0:0]
end
- attribute \src "libresoc.v:80161.3-80170.6"
- process $proc$libresoc.v:80161$3767
+ attribute \src "libresoc.v:79986.3-79995.6"
+ process $proc$libresoc.v:79986$3751
assign { } { }
assign { } { }
assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0]
- attribute \src "libresoc.v:80162.5-80162.29"
+ attribute \src "libresoc.v:79987.5-79987.29"
switch \initial
- attribute \src "libresoc.v:80162.9-80162.17"
+ attribute \src "libresoc.v:79987.9-79987.17"
case 1'1
case
end
sync always
update \dec22_cry_out $0\dec22_cry_out[0:0]
end
- attribute \src "libresoc.v:80171.3-80180.6"
- process $proc$libresoc.v:80171$3768
+ attribute \src "libresoc.v:79996.3-80005.6"
+ process $proc$libresoc.v:79996$3752
assign { } { }
assign { } { }
assign $0\dec22_br[0:0] $1\dec22_br[0:0]
- attribute \src "libresoc.v:80172.5-80172.29"
+ attribute \src "libresoc.v:79997.5-79997.29"
switch \initial
- attribute \src "libresoc.v:80172.9-80172.17"
+ attribute \src "libresoc.v:79997.9-79997.17"
case 1'1
case
end
sync always
update \dec22_br $0\dec22_br[0:0]
end
- attribute \src "libresoc.v:80181.3-80190.6"
- process $proc$libresoc.v:80181$3769
+ attribute \src "libresoc.v:80006.3-80015.6"
+ process $proc$libresoc.v:80006$3753
assign { } { }
assign { } { }
assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0]
- attribute \src "libresoc.v:80182.5-80182.29"
+ attribute \src "libresoc.v:80007.5-80007.29"
switch \initial
- attribute \src "libresoc.v:80182.9-80182.17"
+ attribute \src "libresoc.v:80007.9-80007.17"
case 1'1
case
end
sync always
update \dec22_sgn_ext $0\dec22_sgn_ext[0:0]
end
- attribute \src "libresoc.v:80191.3-80200.6"
- process $proc$libresoc.v:80191$3770
+ attribute \src "libresoc.v:80016.3-80025.6"
+ process $proc$libresoc.v:80016$3754
assign { } { }
assign { } { }
assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0]
- attribute \src "libresoc.v:80192.5-80192.29"
+ attribute \src "libresoc.v:80017.5-80017.29"
switch \initial
- attribute \src "libresoc.v:80192.9-80192.17"
+ attribute \src "libresoc.v:80017.9-80017.17"
case 1'1
case
end
sync always
update \dec22_rsrv $0\dec22_rsrv[0:0]
end
- attribute \src "libresoc.v:80201.3-80210.6"
- process $proc$libresoc.v:80201$3771
+ attribute \src "libresoc.v:80026.3-80035.6"
+ process $proc$libresoc.v:80026$3755
assign { } { }
assign { } { }
assign $0\dec22_form[4:0] $1\dec22_form[4:0]
- attribute \src "libresoc.v:80202.5-80202.29"
+ attribute \src "libresoc.v:80027.5-80027.29"
switch \initial
- attribute \src "libresoc.v:80202.9-80202.17"
+ attribute \src "libresoc.v:80027.9-80027.17"
case 1'1
case
end
sync always
update \dec22_form $0\dec22_form[4:0]
end
- attribute \src "libresoc.v:80211.3-80220.6"
- process $proc$libresoc.v:80211$3772
+ attribute \src "libresoc.v:80036.3-80045.6"
+ process $proc$libresoc.v:80036$3756
assign { } { }
assign { } { }
assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0]
- attribute \src "libresoc.v:80212.5-80212.29"
+ attribute \src "libresoc.v:80037.5-80037.29"
switch \initial
- attribute \src "libresoc.v:80212.9-80212.17"
+ attribute \src "libresoc.v:80037.9-80037.17"
case 1'1
case
end
sync always
update \dec22_is_32b $0\dec22_is_32b[0:0]
end
- attribute \src "libresoc.v:80221.3-80230.6"
- process $proc$libresoc.v:80221$3773
+ attribute \src "libresoc.v:80046.3-80055.6"
+ process $proc$libresoc.v:80046$3757
assign { } { }
assign { } { }
assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0]
- attribute \src "libresoc.v:80222.5-80222.29"
+ attribute \src "libresoc.v:80047.5-80047.29"
switch \initial
- attribute \src "libresoc.v:80222.9-80222.17"
+ attribute \src "libresoc.v:80047.9-80047.17"
case 1'1
case
end
sync always
update \dec22_sgn $0\dec22_sgn[0:0]
end
- attribute \src "libresoc.v:80231.3-80240.6"
- process $proc$libresoc.v:80231$3774
+ attribute \src "libresoc.v:80056.3-80065.6"
+ process $proc$libresoc.v:80056$3758
assign { } { }
assign { } { }
assign $0\dec22_lk[0:0] $1\dec22_lk[0:0]
- attribute \src "libresoc.v:80232.5-80232.29"
+ attribute \src "libresoc.v:80057.5-80057.29"
switch \initial
- attribute \src "libresoc.v:80232.9-80232.17"
+ attribute \src "libresoc.v:80057.9-80057.17"
case 1'1
case
end
sync always
update \dec22_lk $0\dec22_lk[0:0]
end
- attribute \src "libresoc.v:80241.3-80250.6"
- process $proc$libresoc.v:80241$3775
+ attribute \src "libresoc.v:80066.3-80075.6"
+ process $proc$libresoc.v:80066$3759
assign { } { }
assign { } { }
assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0]
- attribute \src "libresoc.v:80242.5-80242.29"
+ attribute \src "libresoc.v:80067.5-80067.29"
switch \initial
- attribute \src "libresoc.v:80242.9-80242.17"
+ attribute \src "libresoc.v:80067.9-80067.17"
case 1'1
case
end
sync always
update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:80251.3-80260.6"
- process $proc$libresoc.v:80251$3776
+ attribute \src "libresoc.v:80076.3-80085.6"
+ process $proc$libresoc.v:80076$3760
assign { } { }
assign { } { }
assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0]
- attribute \src "libresoc.v:80252.5-80252.29"
+ attribute \src "libresoc.v:80077.5-80077.29"
switch \initial
- attribute \src "libresoc.v:80252.9-80252.17"
+ attribute \src "libresoc.v:80077.9-80077.17"
case 1'1
case
end
sync always
update \dec22_SV_Etype $0\dec22_SV_Etype[1:0]
end
- attribute \src "libresoc.v:80261.3-80270.6"
- process $proc$libresoc.v:80261$3777
+ attribute \src "libresoc.v:80086.3-80095.6"
+ process $proc$libresoc.v:80086$3761
assign { } { }
assign { } { }
assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0]
- attribute \src "libresoc.v:80262.5-80262.29"
+ attribute \src "libresoc.v:80087.5-80087.29"
switch \initial
- attribute \src "libresoc.v:80262.9-80262.17"
+ attribute \src "libresoc.v:80087.9-80087.17"
case 1'1
case
end
sync always
update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:80271.3-80280.6"
- process $proc$libresoc.v:80271$3778
+ attribute \src "libresoc.v:80096.3-80105.6"
+ process $proc$libresoc.v:80096$3762
assign { } { }
assign { } { }
assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0]
- attribute \src "libresoc.v:80272.5-80272.29"
+ attribute \src "libresoc.v:80097.5-80097.29"
switch \initial
- attribute \src "libresoc.v:80272.9-80272.17"
+ attribute \src "libresoc.v:80097.9-80097.17"
case 1'1
case
end
sync always
update \dec22_in1_sel $0\dec22_in1_sel[2:0]
end
- attribute \src "libresoc.v:80281.3-80290.6"
- process $proc$libresoc.v:80281$3779
+ attribute \src "libresoc.v:80106.3-80115.6"
+ process $proc$libresoc.v:80106$3763
assign { } { }
assign { } { }
assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0]
- attribute \src "libresoc.v:80282.5-80282.29"
+ attribute \src "libresoc.v:80107.5-80107.29"
switch \initial
- attribute \src "libresoc.v:80282.9-80282.17"
+ attribute \src "libresoc.v:80107.9-80107.17"
case 1'1
case
end
sync always
update \dec22_in2_sel $0\dec22_in2_sel[3:0]
end
- attribute \src "libresoc.v:80291.3-80300.6"
- process $proc$libresoc.v:80291$3780
+ attribute \src "libresoc.v:80116.3-80125.6"
+ process $proc$libresoc.v:80116$3764
assign { } { }
assign { } { }
assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0]
- attribute \src "libresoc.v:80292.5-80292.29"
+ attribute \src "libresoc.v:80117.5-80117.29"
switch \initial
- attribute \src "libresoc.v:80292.9-80292.17"
+ attribute \src "libresoc.v:80117.9-80117.17"
case 1'1
case
end
sync always
update \dec22_in3_sel $0\dec22_in3_sel[1:0]
end
- attribute \src "libresoc.v:80301.3-80310.6"
- process $proc$libresoc.v:80301$3781
+ attribute \src "libresoc.v:80126.3-80135.6"
+ process $proc$libresoc.v:80126$3765
assign { } { }
assign { } { }
assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0]
- attribute \src "libresoc.v:80302.5-80302.29"
+ attribute \src "libresoc.v:80127.5-80127.29"
switch \initial
- attribute \src "libresoc.v:80302.9-80302.17"
+ attribute \src "libresoc.v:80127.9-80127.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [4:1]
end
-attribute \src "libresoc.v:80316.1-81887.10"
+attribute \src "libresoc.v:80141.1-81712.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30"
attribute \generator "nMigen"
module \dec30
- attribute \src "libresoc.v:81664.3-81700.6"
+ attribute \src "libresoc.v:81489.3-81525.6"
wire width 2 $0\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81701.3-81737.6"
+ attribute \src "libresoc.v:81526.3-81562.6"
wire width 2 $0\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:81220.3-81256.6"
+ attribute \src "libresoc.v:81045.3-81081.6"
wire width 8 $0\dec30_asmcode[7:0]
- attribute \src "libresoc.v:81368.3-81404.6"
+ attribute \src "libresoc.v:81193.3-81229.6"
wire $0\dec30_br[0:0]
- attribute \src "libresoc.v:80702.3-80738.6"
+ attribute \src "libresoc.v:80527.3-80563.6"
wire width 3 $0\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80739.3-80775.6"
+ attribute \src "libresoc.v:80564.3-80600.6"
wire width 3 $0\dec30_cr_out[2:0]
- attribute \src "libresoc.v:81183.3-81219.6"
+ attribute \src "libresoc.v:81008.3-81044.6"
wire width 2 $0\dec30_cry_in[1:0]
- attribute \src "libresoc.v:81331.3-81367.6"
+ attribute \src "libresoc.v:81156.3-81192.6"
wire $0\dec30_cry_out[0:0]
- attribute \src "libresoc.v:81479.3-81515.6"
+ attribute \src "libresoc.v:81304.3-81340.6"
wire width 5 $0\dec30_form[4:0]
- attribute \src "libresoc.v:80665.3-80701.6"
+ attribute \src "libresoc.v:80490.3-80526.6"
wire width 14 $0\dec30_function_unit[13:0]
- attribute \src "libresoc.v:81738.3-81774.6"
+ attribute \src "libresoc.v:81563.3-81599.6"
wire width 3 $0\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81775.3-81811.6"
+ attribute \src "libresoc.v:81600.3-81636.6"
wire width 4 $0\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81812.3-81848.6"
+ attribute \src "libresoc.v:81637.3-81673.6"
wire width 2 $0\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:81072.3-81108.6"
+ attribute \src "libresoc.v:80897.3-80933.6"
wire width 7 $0\dec30_internal_op[6:0]
- attribute \src "libresoc.v:81257.3-81293.6"
+ attribute \src "libresoc.v:81082.3-81118.6"
wire $0\dec30_inv_a[0:0]
- attribute \src "libresoc.v:81294.3-81330.6"
+ attribute \src "libresoc.v:81119.3-81155.6"
wire $0\dec30_inv_out[0:0]
- attribute \src "libresoc.v:81516.3-81552.6"
+ attribute \src "libresoc.v:81341.3-81377.6"
wire $0\dec30_is_32b[0:0]
- attribute \src "libresoc.v:81035.3-81071.6"
+ attribute \src "libresoc.v:80860.3-80896.6"
wire width 4 $0\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:81590.3-81626.6"
+ attribute \src "libresoc.v:81415.3-81451.6"
wire $0\dec30_lk[0:0]
- attribute \src "libresoc.v:81849.3-81885.6"
+ attribute \src "libresoc.v:81674.3-81710.6"
wire width 3 $0\dec30_out_sel[2:0]
- attribute \src "libresoc.v:81146.3-81182.6"
+ attribute \src "libresoc.v:80971.3-81007.6"
wire width 2 $0\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:81442.3-81478.6"
+ attribute \src "libresoc.v:81267.3-81303.6"
wire $0\dec30_rsrv[0:0]
- attribute \src "libresoc.v:81627.3-81663.6"
+ attribute \src "libresoc.v:81452.3-81488.6"
wire $0\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:81553.3-81589.6"
+ attribute \src "libresoc.v:81378.3-81414.6"
wire $0\dec30_sgn[0:0]
- attribute \src "libresoc.v:81405.3-81441.6"
+ attribute \src "libresoc.v:81230.3-81266.6"
wire $0\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:80961.3-80997.6"
+ attribute \src "libresoc.v:80786.3-80822.6"
wire width 3 $0\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80998.3-81034.6"
+ attribute \src "libresoc.v:80823.3-80859.6"
wire width 3 $0\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80776.3-80812.6"
+ attribute \src "libresoc.v:80601.3-80637.6"
wire width 3 $0\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80813.3-80849.6"
+ attribute \src "libresoc.v:80638.3-80674.6"
wire width 3 $0\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80850.3-80886.6"
+ attribute \src "libresoc.v:80675.3-80711.6"
wire width 3 $0\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80924.3-80960.6"
+ attribute \src "libresoc.v:80749.3-80785.6"
wire width 3 $0\dec30_sv_out2[2:0]
- attribute \src "libresoc.v:80887.3-80923.6"
+ attribute \src "libresoc.v:80712.3-80748.6"
wire width 3 $0\dec30_sv_out[2:0]
- attribute \src "libresoc.v:81109.3-81145.6"
+ attribute \src "libresoc.v:80934.3-80970.6"
wire width 2 $0\dec30_upd[1:0]
- attribute \src "libresoc.v:80317.7-80317.20"
+ attribute \src "libresoc.v:80142.7-80142.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:81664.3-81700.6"
+ attribute \src "libresoc.v:81489.3-81525.6"
wire width 2 $1\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81701.3-81737.6"
+ attribute \src "libresoc.v:81526.3-81562.6"
wire width 2 $1\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:81220.3-81256.6"
+ attribute \src "libresoc.v:81045.3-81081.6"
wire width 8 $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:81368.3-81404.6"
+ attribute \src "libresoc.v:81193.3-81229.6"
wire $1\dec30_br[0:0]
- attribute \src "libresoc.v:80702.3-80738.6"
+ attribute \src "libresoc.v:80527.3-80563.6"
wire width 3 $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80739.3-80775.6"
+ attribute \src "libresoc.v:80564.3-80600.6"
wire width 3 $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:81183.3-81219.6"
+ attribute \src "libresoc.v:81008.3-81044.6"
wire width 2 $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:81331.3-81367.6"
+ attribute \src "libresoc.v:81156.3-81192.6"
wire $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:81479.3-81515.6"
+ attribute \src "libresoc.v:81304.3-81340.6"
wire width 5 $1\dec30_form[4:0]
- attribute \src "libresoc.v:80665.3-80701.6"
+ attribute \src "libresoc.v:80490.3-80526.6"
wire width 14 $1\dec30_function_unit[13:0]
- attribute \src "libresoc.v:81738.3-81774.6"
+ attribute \src "libresoc.v:81563.3-81599.6"
wire width 3 $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81775.3-81811.6"
+ attribute \src "libresoc.v:81600.3-81636.6"
wire width 4 $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81812.3-81848.6"
+ attribute \src "libresoc.v:81637.3-81673.6"
wire width 2 $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:81072.3-81108.6"
+ attribute \src "libresoc.v:80897.3-80933.6"
wire width 7 $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:81257.3-81293.6"
+ attribute \src "libresoc.v:81082.3-81118.6"
wire $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:81294.3-81330.6"
+ attribute \src "libresoc.v:81119.3-81155.6"
wire $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:81516.3-81552.6"
+ attribute \src "libresoc.v:81341.3-81377.6"
wire $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:81035.3-81071.6"
+ attribute \src "libresoc.v:80860.3-80896.6"
wire width 4 $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:81590.3-81626.6"
+ attribute \src "libresoc.v:81415.3-81451.6"
wire $1\dec30_lk[0:0]
- attribute \src "libresoc.v:81849.3-81885.6"
+ attribute \src "libresoc.v:81674.3-81710.6"
wire width 3 $1\dec30_out_sel[2:0]
- attribute \src "libresoc.v:81146.3-81182.6"
+ attribute \src "libresoc.v:80971.3-81007.6"
wire width 2 $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:81442.3-81478.6"
+ attribute \src "libresoc.v:81267.3-81303.6"
wire $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:81627.3-81663.6"
+ attribute \src "libresoc.v:81452.3-81488.6"
wire $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:81553.3-81589.6"
+ attribute \src "libresoc.v:81378.3-81414.6"
wire $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:81405.3-81441.6"
+ attribute \src "libresoc.v:81230.3-81266.6"
wire $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:80961.3-80997.6"
+ attribute \src "libresoc.v:80786.3-80822.6"
wire width 3 $1\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80998.3-81034.6"
+ attribute \src "libresoc.v:80823.3-80859.6"
wire width 3 $1\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80776.3-80812.6"
+ attribute \src "libresoc.v:80601.3-80637.6"
wire width 3 $1\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80813.3-80849.6"
+ attribute \src "libresoc.v:80638.3-80674.6"
wire width 3 $1\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80850.3-80886.6"
+ attribute \src "libresoc.v:80675.3-80711.6"
wire width 3 $1\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80924.3-80960.6"
+ attribute \src "libresoc.v:80749.3-80785.6"
wire width 3 $1\dec30_sv_out2[2:0]
- attribute \src "libresoc.v:80887.3-80923.6"
+ attribute \src "libresoc.v:80712.3-80748.6"
wire width 3 $1\dec30_sv_out[2:0]
- attribute \src "libresoc.v:81109.3-81145.6"
+ attribute \src "libresoc.v:80934.3-80970.6"
wire width 2 $1\dec30_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec30_upd
- attribute \src "libresoc.v:80317.7-80317.15"
+ attribute \src "libresoc.v:80142.7-80142.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 4 \opcode_switch
- attribute \src "libresoc.v:80317.7-80317.20"
- process $proc$libresoc.v:80317$3816
+ attribute \src "libresoc.v:80142.7-80142.20"
+ process $proc$libresoc.v:80142$3800
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:80665.3-80701.6"
- process $proc$libresoc.v:80665$3783
+ attribute \src "libresoc.v:80490.3-80526.6"
+ process $proc$libresoc.v:80490$3767
assign { } { }
assign { } { }
assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0]
- attribute \src "libresoc.v:80666.5-80666.29"
+ attribute \src "libresoc.v:80491.5-80491.29"
switch \initial
- attribute \src "libresoc.v:80666.9-80666.17"
+ attribute \src "libresoc.v:80491.9-80491.17"
case 1'1
case
end
sync always
update \dec30_function_unit $0\dec30_function_unit[13:0]
end
- attribute \src "libresoc.v:80702.3-80738.6"
- process $proc$libresoc.v:80702$3784
+ attribute \src "libresoc.v:80527.3-80563.6"
+ process $proc$libresoc.v:80527$3768
assign { } { }
assign { } { }
assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80703.5-80703.29"
+ attribute \src "libresoc.v:80528.5-80528.29"
switch \initial
- attribute \src "libresoc.v:80703.9-80703.17"
+ attribute \src "libresoc.v:80528.9-80528.17"
case 1'1
case
end
sync always
update \dec30_cr_in $0\dec30_cr_in[2:0]
end
- attribute \src "libresoc.v:80739.3-80775.6"
- process $proc$libresoc.v:80739$3785
+ attribute \src "libresoc.v:80564.3-80600.6"
+ process $proc$libresoc.v:80564$3769
assign { } { }
assign { } { }
assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:80740.5-80740.29"
+ attribute \src "libresoc.v:80565.5-80565.29"
switch \initial
- attribute \src "libresoc.v:80740.9-80740.17"
+ attribute \src "libresoc.v:80565.9-80565.17"
case 1'1
case
end
sync always
update \dec30_cr_out $0\dec30_cr_out[2:0]
end
- attribute \src "libresoc.v:80776.3-80812.6"
- process $proc$libresoc.v:80776$3786
+ attribute \src "libresoc.v:80601.3-80637.6"
+ process $proc$libresoc.v:80601$3770
assign { } { }
assign { } { }
assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80777.5-80777.29"
+ attribute \src "libresoc.v:80602.5-80602.29"
switch \initial
- attribute \src "libresoc.v:80777.9-80777.17"
+ attribute \src "libresoc.v:80602.9-80602.17"
case 1'1
case
end
sync always
update \dec30_sv_in1 $0\dec30_sv_in1[2:0]
end
- attribute \src "libresoc.v:80813.3-80849.6"
- process $proc$libresoc.v:80813$3787
+ attribute \src "libresoc.v:80638.3-80674.6"
+ process $proc$libresoc.v:80638$3771
assign { } { }
assign { } { }
assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80814.5-80814.29"
+ attribute \src "libresoc.v:80639.5-80639.29"
switch \initial
- attribute \src "libresoc.v:80814.9-80814.17"
+ attribute \src "libresoc.v:80639.9-80639.17"
case 1'1
case
end
sync always
update \dec30_sv_in2 $0\dec30_sv_in2[2:0]
end
- attribute \src "libresoc.v:80850.3-80886.6"
- process $proc$libresoc.v:80850$3788
+ attribute \src "libresoc.v:80675.3-80711.6"
+ process $proc$libresoc.v:80675$3772
assign { } { }
assign { } { }
assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80851.5-80851.29"
+ attribute \src "libresoc.v:80676.5-80676.29"
switch \initial
- attribute \src "libresoc.v:80851.9-80851.17"
+ attribute \src "libresoc.v:80676.9-80676.17"
case 1'1
case
end
sync always
update \dec30_sv_in3 $0\dec30_sv_in3[2:0]
end
- attribute \src "libresoc.v:80887.3-80923.6"
- process $proc$libresoc.v:80887$3789
+ attribute \src "libresoc.v:80712.3-80748.6"
+ process $proc$libresoc.v:80712$3773
assign { } { }
assign { } { }
assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0]
- attribute \src "libresoc.v:80888.5-80888.29"
+ attribute \src "libresoc.v:80713.5-80713.29"
switch \initial
- attribute \src "libresoc.v:80888.9-80888.17"
+ attribute \src "libresoc.v:80713.9-80713.17"
case 1'1
case
end
sync always
update \dec30_sv_out $0\dec30_sv_out[2:0]
end
- attribute \src "libresoc.v:80924.3-80960.6"
- process $proc$libresoc.v:80924$3790
+ attribute \src "libresoc.v:80749.3-80785.6"
+ process $proc$libresoc.v:80749$3774
assign { } { }
assign { } { }
assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0]
- attribute \src "libresoc.v:80925.5-80925.29"
+ attribute \src "libresoc.v:80750.5-80750.29"
switch \initial
- attribute \src "libresoc.v:80925.9-80925.17"
+ attribute \src "libresoc.v:80750.9-80750.17"
case 1'1
case
end
sync always
update \dec30_sv_out2 $0\dec30_sv_out2[2:0]
end
- attribute \src "libresoc.v:80961.3-80997.6"
- process $proc$libresoc.v:80961$3791
+ attribute \src "libresoc.v:80786.3-80822.6"
+ process $proc$libresoc.v:80786$3775
assign { } { }
assign { } { }
assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80962.5-80962.29"
+ attribute \src "libresoc.v:80787.5-80787.29"
switch \initial
- attribute \src "libresoc.v:80962.9-80962.17"
+ attribute \src "libresoc.v:80787.9-80787.17"
case 1'1
case
end
sync always
update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:80998.3-81034.6"
- process $proc$libresoc.v:80998$3792
+ attribute \src "libresoc.v:80823.3-80859.6"
+ process $proc$libresoc.v:80823$3776
assign { } { }
assign { } { }
assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80999.5-80999.29"
+ attribute \src "libresoc.v:80824.5-80824.29"
switch \initial
- attribute \src "libresoc.v:80999.9-80999.17"
+ attribute \src "libresoc.v:80824.9-80824.17"
case 1'1
case
end
sync always
update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:81035.3-81071.6"
- process $proc$libresoc.v:81035$3793
+ attribute \src "libresoc.v:80860.3-80896.6"
+ process $proc$libresoc.v:80860$3777
assign { } { }
assign { } { }
assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:81036.5-81036.29"
+ attribute \src "libresoc.v:80861.5-80861.29"
switch \initial
- attribute \src "libresoc.v:81036.9-81036.17"
+ attribute \src "libresoc.v:80861.9-80861.17"
case 1'1
case
end
sync always
update \dec30_ldst_len $0\dec30_ldst_len[3:0]
end
- attribute \src "libresoc.v:81072.3-81108.6"
- process $proc$libresoc.v:81072$3794
+ attribute \src "libresoc.v:80897.3-80933.6"
+ process $proc$libresoc.v:80897$3778
assign { } { }
assign { } { }
assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:81073.5-81073.29"
+ attribute \src "libresoc.v:80898.5-80898.29"
switch \initial
- attribute \src "libresoc.v:81073.9-81073.17"
+ attribute \src "libresoc.v:80898.9-80898.17"
case 1'1
case
end
sync always
update \dec30_internal_op $0\dec30_internal_op[6:0]
end
- attribute \src "libresoc.v:81109.3-81145.6"
- process $proc$libresoc.v:81109$3795
+ attribute \src "libresoc.v:80934.3-80970.6"
+ process $proc$libresoc.v:80934$3779
assign { } { }
assign { } { }
assign $0\dec30_upd[1:0] $1\dec30_upd[1:0]
- attribute \src "libresoc.v:81110.5-81110.29"
+ attribute \src "libresoc.v:80935.5-80935.29"
switch \initial
- attribute \src "libresoc.v:81110.9-81110.17"
+ attribute \src "libresoc.v:80935.9-80935.17"
case 1'1
case
end
sync always
update \dec30_upd $0\dec30_upd[1:0]
end
- attribute \src "libresoc.v:81146.3-81182.6"
- process $proc$libresoc.v:81146$3796
+ attribute \src "libresoc.v:80971.3-81007.6"
+ process $proc$libresoc.v:80971$3780
assign { } { }
assign { } { }
assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:81147.5-81147.29"
+ attribute \src "libresoc.v:80972.5-80972.29"
switch \initial
- attribute \src "libresoc.v:81147.9-81147.17"
+ attribute \src "libresoc.v:80972.9-80972.17"
case 1'1
case
end
sync always
update \dec30_rc_sel $0\dec30_rc_sel[1:0]
end
- attribute \src "libresoc.v:81183.3-81219.6"
- process $proc$libresoc.v:81183$3797
+ attribute \src "libresoc.v:81008.3-81044.6"
+ process $proc$libresoc.v:81008$3781
assign { } { }
assign { } { }
assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:81184.5-81184.29"
+ attribute \src "libresoc.v:81009.5-81009.29"
switch \initial
- attribute \src "libresoc.v:81184.9-81184.17"
+ attribute \src "libresoc.v:81009.9-81009.17"
case 1'1
case
end
sync always
update \dec30_cry_in $0\dec30_cry_in[1:0]
end
- attribute \src "libresoc.v:81220.3-81256.6"
- process $proc$libresoc.v:81220$3798
+ attribute \src "libresoc.v:81045.3-81081.6"
+ process $proc$libresoc.v:81045$3782
assign { } { }
assign { } { }
assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:81221.5-81221.29"
+ attribute \src "libresoc.v:81046.5-81046.29"
switch \initial
- attribute \src "libresoc.v:81221.9-81221.17"
+ attribute \src "libresoc.v:81046.9-81046.17"
case 1'1
case
end
sync always
update \dec30_asmcode $0\dec30_asmcode[7:0]
end
- attribute \src "libresoc.v:81257.3-81293.6"
- process $proc$libresoc.v:81257$3799
+ attribute \src "libresoc.v:81082.3-81118.6"
+ process $proc$libresoc.v:81082$3783
assign { } { }
assign { } { }
assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:81258.5-81258.29"
+ attribute \src "libresoc.v:81083.5-81083.29"
switch \initial
- attribute \src "libresoc.v:81258.9-81258.17"
+ attribute \src "libresoc.v:81083.9-81083.17"
case 1'1
case
end
sync always
update \dec30_inv_a $0\dec30_inv_a[0:0]
end
- attribute \src "libresoc.v:81294.3-81330.6"
- process $proc$libresoc.v:81294$3800
+ attribute \src "libresoc.v:81119.3-81155.6"
+ process $proc$libresoc.v:81119$3784
assign { } { }
assign { } { }
assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:81295.5-81295.29"
+ attribute \src "libresoc.v:81120.5-81120.29"
switch \initial
- attribute \src "libresoc.v:81295.9-81295.17"
+ attribute \src "libresoc.v:81120.9-81120.17"
case 1'1
case
end
sync always
update \dec30_inv_out $0\dec30_inv_out[0:0]
end
- attribute \src "libresoc.v:81331.3-81367.6"
- process $proc$libresoc.v:81331$3801
+ attribute \src "libresoc.v:81156.3-81192.6"
+ process $proc$libresoc.v:81156$3785
assign { } { }
assign { } { }
assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:81332.5-81332.29"
+ attribute \src "libresoc.v:81157.5-81157.29"
switch \initial
- attribute \src "libresoc.v:81332.9-81332.17"
+ attribute \src "libresoc.v:81157.9-81157.17"
case 1'1
case
end
sync always
update \dec30_cry_out $0\dec30_cry_out[0:0]
end
- attribute \src "libresoc.v:81368.3-81404.6"
- process $proc$libresoc.v:81368$3802
+ attribute \src "libresoc.v:81193.3-81229.6"
+ process $proc$libresoc.v:81193$3786
assign { } { }
assign { } { }
assign $0\dec30_br[0:0] $1\dec30_br[0:0]
- attribute \src "libresoc.v:81369.5-81369.29"
+ attribute \src "libresoc.v:81194.5-81194.29"
switch \initial
- attribute \src "libresoc.v:81369.9-81369.17"
+ attribute \src "libresoc.v:81194.9-81194.17"
case 1'1
case
end
sync always
update \dec30_br $0\dec30_br[0:0]
end
- attribute \src "libresoc.v:81405.3-81441.6"
- process $proc$libresoc.v:81405$3803
+ attribute \src "libresoc.v:81230.3-81266.6"
+ process $proc$libresoc.v:81230$3787
assign { } { }
assign { } { }
assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:81406.5-81406.29"
+ attribute \src "libresoc.v:81231.5-81231.29"
switch \initial
- attribute \src "libresoc.v:81406.9-81406.17"
+ attribute \src "libresoc.v:81231.9-81231.17"
case 1'1
case
end
sync always
update \dec30_sgn_ext $0\dec30_sgn_ext[0:0]
end
- attribute \src "libresoc.v:81442.3-81478.6"
- process $proc$libresoc.v:81442$3804
+ attribute \src "libresoc.v:81267.3-81303.6"
+ process $proc$libresoc.v:81267$3788
assign { } { }
assign { } { }
assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:81443.5-81443.29"
+ attribute \src "libresoc.v:81268.5-81268.29"
switch \initial
- attribute \src "libresoc.v:81443.9-81443.17"
+ attribute \src "libresoc.v:81268.9-81268.17"
case 1'1
case
end
sync always
update \dec30_rsrv $0\dec30_rsrv[0:0]
end
- attribute \src "libresoc.v:81479.3-81515.6"
- process $proc$libresoc.v:81479$3805
+ attribute \src "libresoc.v:81304.3-81340.6"
+ process $proc$libresoc.v:81304$3789
assign { } { }
assign { } { }
assign $0\dec30_form[4:0] $1\dec30_form[4:0]
- attribute \src "libresoc.v:81480.5-81480.29"
+ attribute \src "libresoc.v:81305.5-81305.29"
switch \initial
- attribute \src "libresoc.v:81480.9-81480.17"
+ attribute \src "libresoc.v:81305.9-81305.17"
case 1'1
case
end
sync always
update \dec30_form $0\dec30_form[4:0]
end
- attribute \src "libresoc.v:81516.3-81552.6"
- process $proc$libresoc.v:81516$3806
+ attribute \src "libresoc.v:81341.3-81377.6"
+ process $proc$libresoc.v:81341$3790
assign { } { }
assign { } { }
assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:81517.5-81517.29"
+ attribute \src "libresoc.v:81342.5-81342.29"
switch \initial
- attribute \src "libresoc.v:81517.9-81517.17"
+ attribute \src "libresoc.v:81342.9-81342.17"
case 1'1
case
end
sync always
update \dec30_is_32b $0\dec30_is_32b[0:0]
end
- attribute \src "libresoc.v:81553.3-81589.6"
- process $proc$libresoc.v:81553$3807
+ attribute \src "libresoc.v:81378.3-81414.6"
+ process $proc$libresoc.v:81378$3791
assign { } { }
assign { } { }
assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:81554.5-81554.29"
+ attribute \src "libresoc.v:81379.5-81379.29"
switch \initial
- attribute \src "libresoc.v:81554.9-81554.17"
+ attribute \src "libresoc.v:81379.9-81379.17"
case 1'1
case
end
sync always
update \dec30_sgn $0\dec30_sgn[0:0]
end
- attribute \src "libresoc.v:81590.3-81626.6"
- process $proc$libresoc.v:81590$3808
+ attribute \src "libresoc.v:81415.3-81451.6"
+ process $proc$libresoc.v:81415$3792
assign { } { }
assign { } { }
assign $0\dec30_lk[0:0] $1\dec30_lk[0:0]
- attribute \src "libresoc.v:81591.5-81591.29"
+ attribute \src "libresoc.v:81416.5-81416.29"
switch \initial
- attribute \src "libresoc.v:81591.9-81591.17"
+ attribute \src "libresoc.v:81416.9-81416.17"
case 1'1
case
end
sync always
update \dec30_lk $0\dec30_lk[0:0]
end
- attribute \src "libresoc.v:81627.3-81663.6"
- process $proc$libresoc.v:81627$3809
+ attribute \src "libresoc.v:81452.3-81488.6"
+ process $proc$libresoc.v:81452$3793
assign { } { }
assign { } { }
assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:81628.5-81628.29"
+ attribute \src "libresoc.v:81453.5-81453.29"
switch \initial
- attribute \src "libresoc.v:81628.9-81628.17"
+ attribute \src "libresoc.v:81453.9-81453.17"
case 1'1
case
end
sync always
update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:81664.3-81700.6"
- process $proc$libresoc.v:81664$3810
+ attribute \src "libresoc.v:81489.3-81525.6"
+ process $proc$libresoc.v:81489$3794
assign { } { }
assign { } { }
assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81665.5-81665.29"
+ attribute \src "libresoc.v:81490.5-81490.29"
switch \initial
- attribute \src "libresoc.v:81665.9-81665.17"
+ attribute \src "libresoc.v:81490.9-81490.17"
case 1'1
case
end
sync always
update \dec30_SV_Etype $0\dec30_SV_Etype[1:0]
end
- attribute \src "libresoc.v:81701.3-81737.6"
- process $proc$libresoc.v:81701$3811
+ attribute \src "libresoc.v:81526.3-81562.6"
+ process $proc$libresoc.v:81526$3795
assign { } { }
assign { } { }
assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:81702.5-81702.29"
+ attribute \src "libresoc.v:81527.5-81527.29"
switch \initial
- attribute \src "libresoc.v:81702.9-81702.17"
+ attribute \src "libresoc.v:81527.9-81527.17"
case 1'1
case
end
sync always
update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:81738.3-81774.6"
- process $proc$libresoc.v:81738$3812
+ attribute \src "libresoc.v:81563.3-81599.6"
+ process $proc$libresoc.v:81563$3796
assign { } { }
assign { } { }
assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81739.5-81739.29"
+ attribute \src "libresoc.v:81564.5-81564.29"
switch \initial
- attribute \src "libresoc.v:81739.9-81739.17"
+ attribute \src "libresoc.v:81564.9-81564.17"
case 1'1
case
end
sync always
update \dec30_in1_sel $0\dec30_in1_sel[2:0]
end
- attribute \src "libresoc.v:81775.3-81811.6"
- process $proc$libresoc.v:81775$3813
+ attribute \src "libresoc.v:81600.3-81636.6"
+ process $proc$libresoc.v:81600$3797
assign { } { }
assign { } { }
assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81776.5-81776.29"
+ attribute \src "libresoc.v:81601.5-81601.29"
switch \initial
- attribute \src "libresoc.v:81776.9-81776.17"
+ attribute \src "libresoc.v:81601.9-81601.17"
case 1'1
case
end
sync always
update \dec30_in2_sel $0\dec30_in2_sel[3:0]
end
- attribute \src "libresoc.v:81812.3-81848.6"
- process $proc$libresoc.v:81812$3814
+ attribute \src "libresoc.v:81637.3-81673.6"
+ process $proc$libresoc.v:81637$3798
assign { } { }
assign { } { }
assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:81813.5-81813.29"
+ attribute \src "libresoc.v:81638.5-81638.29"
switch \initial
- attribute \src "libresoc.v:81813.9-81813.17"
+ attribute \src "libresoc.v:81638.9-81638.17"
case 1'1
case
end
sync always
update \dec30_in3_sel $0\dec30_in3_sel[1:0]
end
- attribute \src "libresoc.v:81849.3-81885.6"
- process $proc$libresoc.v:81849$3815
+ attribute \src "libresoc.v:81674.3-81710.6"
+ process $proc$libresoc.v:81674$3799
assign { } { }
assign { } { }
assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0]
- attribute \src "libresoc.v:81850.5-81850.29"
+ attribute \src "libresoc.v:81675.5-81675.29"
switch \initial
- attribute \src "libresoc.v:81850.9-81850.17"
+ attribute \src "libresoc.v:81675.9-81675.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [4:1]
end
-attribute \src "libresoc.v:81891.1-90539.10"
+attribute \src "libresoc.v:81716.1-90364.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31"
attribute \generator "nMigen"
module \dec31
- attribute \src "libresoc.v:88750.3-88810.6"
+ attribute \src "libresoc.v:88575.3-88635.6"
wire width 2 $0\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:88811.3-88871.6"
+ attribute \src "libresoc.v:88636.3-88696.6"
wire width 2 $0\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:88689.3-88749.6"
+ attribute \src "libresoc.v:88514.3-88574.6"
wire width 8 $0\dec31_asmcode[7:0]
- attribute \src "libresoc.v:90092.3-90152.6"
+ attribute \src "libresoc.v:89917.3-89977.6"
wire $0\dec31_br[0:0]
- attribute \src "libresoc.v:89116.3-89176.6"
+ attribute \src "libresoc.v:88941.3-89001.6"
wire width 3 $0\dec31_cr_in[2:0]
- attribute \src "libresoc.v:89177.3-89237.6"
+ attribute \src "libresoc.v:89002.3-89062.6"
wire width 3 $0\dec31_cr_out[2:0]
- attribute \src "libresoc.v:89848.3-89908.6"
+ attribute \src "libresoc.v:89673.3-89733.6"
wire width 2 $0\dec31_cry_in[1:0]
- attribute \src "libresoc.v:90031.3-90091.6"
+ attribute \src "libresoc.v:89856.3-89916.6"
wire $0\dec31_cry_out[0:0]
- attribute \src "libresoc.v:88628.3-88688.6"
+ attribute \src "libresoc.v:88453.3-88513.6"
wire width 5 $0\dec31_form[4:0]
- attribute \src "libresoc.v:88506.3-88566.6"
+ attribute \src "libresoc.v:88331.3-88391.6"
wire width 14 $0\dec31_function_unit[13:0]
- attribute \src "libresoc.v:88872.3-88932.6"
+ attribute \src "libresoc.v:88697.3-88757.6"
wire width 3 $0\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:88933.3-88993.6"
+ attribute \src "libresoc.v:88758.3-88818.6"
wire width 4 $0\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88994.3-89054.6"
+ attribute \src "libresoc.v:88819.3-88879.6"
wire width 2 $0\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:88567.3-88627.6"
+ attribute \src "libresoc.v:88392.3-88452.6"
wire width 7 $0\dec31_internal_op[6:0]
- attribute \src "libresoc.v:89909.3-89969.6"
+ attribute \src "libresoc.v:89734.3-89794.6"
wire $0\dec31_inv_a[0:0]
- attribute \src "libresoc.v:89970.3-90030.6"
+ attribute \src "libresoc.v:89795.3-89855.6"
wire $0\dec31_inv_out[0:0]
- attribute \src "libresoc.v:90275.3-90335.6"
+ attribute \src "libresoc.v:90100.3-90160.6"
wire $0\dec31_is_32b[0:0]
- attribute \src "libresoc.v:89665.3-89725.6"
+ attribute \src "libresoc.v:89490.3-89550.6"
wire width 4 $0\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:90397.3-90457.6"
+ attribute \src "libresoc.v:90222.3-90282.6"
wire $0\dec31_lk[0:0]
- attribute \src "libresoc.v:89055.3-89115.6"
+ attribute \src "libresoc.v:88880.3-88940.6"
wire width 3 $0\dec31_out_sel[2:0]
- attribute \src "libresoc.v:89787.3-89847.6"
+ attribute \src "libresoc.v:89612.3-89672.6"
wire width 2 $0\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:90214.3-90274.6"
+ attribute \src "libresoc.v:90039.3-90099.6"
wire $0\dec31_rsrv[0:0]
- attribute \src "libresoc.v:90458.3-90518.6"
+ attribute \src "libresoc.v:90283.3-90343.6"
wire $0\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:90336.3-90396.6"
+ attribute \src "libresoc.v:90161.3-90221.6"
wire $0\dec31_sgn[0:0]
- attribute \src "libresoc.v:90153.3-90213.6"
+ attribute \src "libresoc.v:89978.3-90038.6"
wire $0\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:89543.3-89603.6"
+ attribute \src "libresoc.v:89368.3-89428.6"
wire width 3 $0\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:89604.3-89664.6"
+ attribute \src "libresoc.v:89429.3-89489.6"
wire width 3 $0\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:89238.3-89298.6"
+ attribute \src "libresoc.v:89063.3-89123.6"
wire width 3 $0\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:89299.3-89359.6"
+ attribute \src "libresoc.v:89124.3-89184.6"
wire width 3 $0\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:89360.3-89420.6"
+ attribute \src "libresoc.v:89185.3-89245.6"
wire width 3 $0\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:89482.3-89542.6"
+ attribute \src "libresoc.v:89307.3-89367.6"
wire width 3 $0\dec31_sv_out2[2:0]
- attribute \src "libresoc.v:89421.3-89481.6"
+ attribute \src "libresoc.v:89246.3-89306.6"
wire width 3 $0\dec31_sv_out[2:0]
- attribute \src "libresoc.v:89726.3-89786.6"
+ attribute \src "libresoc.v:89551.3-89611.6"
wire width 2 $0\dec31_upd[1:0]
- attribute \src "libresoc.v:81892.7-81892.20"
+ attribute \src "libresoc.v:81717.7-81717.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:88750.3-88810.6"
+ attribute \src "libresoc.v:88575.3-88635.6"
wire width 2 $1\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:88811.3-88871.6"
+ attribute \src "libresoc.v:88636.3-88696.6"
wire width 2 $1\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:88689.3-88749.6"
+ attribute \src "libresoc.v:88514.3-88574.6"
wire width 8 $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:90092.3-90152.6"
+ attribute \src "libresoc.v:89917.3-89977.6"
wire $1\dec31_br[0:0]
- attribute \src "libresoc.v:89116.3-89176.6"
+ attribute \src "libresoc.v:88941.3-89001.6"
wire width 3 $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:89177.3-89237.6"
+ attribute \src "libresoc.v:89002.3-89062.6"
wire width 3 $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:89848.3-89908.6"
+ attribute \src "libresoc.v:89673.3-89733.6"
wire width 2 $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:90031.3-90091.6"
+ attribute \src "libresoc.v:89856.3-89916.6"
wire $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:88628.3-88688.6"
+ attribute \src "libresoc.v:88453.3-88513.6"
wire width 5 $1\dec31_form[4:0]
- attribute \src "libresoc.v:88506.3-88566.6"
+ attribute \src "libresoc.v:88331.3-88391.6"
wire width 14 $1\dec31_function_unit[13:0]
- attribute \src "libresoc.v:88872.3-88932.6"
+ attribute \src "libresoc.v:88697.3-88757.6"
wire width 3 $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:88933.3-88993.6"
+ attribute \src "libresoc.v:88758.3-88818.6"
wire width 4 $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88994.3-89054.6"
+ attribute \src "libresoc.v:88819.3-88879.6"
wire width 2 $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:88567.3-88627.6"
+ attribute \src "libresoc.v:88392.3-88452.6"
wire width 7 $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:89909.3-89969.6"
+ attribute \src "libresoc.v:89734.3-89794.6"
wire $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:89970.3-90030.6"
+ attribute \src "libresoc.v:89795.3-89855.6"
wire $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:90275.3-90335.6"
+ attribute \src "libresoc.v:90100.3-90160.6"
wire $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:89665.3-89725.6"
+ attribute \src "libresoc.v:89490.3-89550.6"
wire width 4 $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:90397.3-90457.6"
+ attribute \src "libresoc.v:90222.3-90282.6"
wire $1\dec31_lk[0:0]
- attribute \src "libresoc.v:89055.3-89115.6"
+ attribute \src "libresoc.v:88880.3-88940.6"
wire width 3 $1\dec31_out_sel[2:0]
- attribute \src "libresoc.v:89787.3-89847.6"
+ attribute \src "libresoc.v:89612.3-89672.6"
wire width 2 $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:90214.3-90274.6"
+ attribute \src "libresoc.v:90039.3-90099.6"
wire $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:90458.3-90518.6"
+ attribute \src "libresoc.v:90283.3-90343.6"
wire $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:90336.3-90396.6"
+ attribute \src "libresoc.v:90161.3-90221.6"
wire $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:90153.3-90213.6"
+ attribute \src "libresoc.v:89978.3-90038.6"
wire $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:89543.3-89603.6"
+ attribute \src "libresoc.v:89368.3-89428.6"
wire width 3 $1\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:89604.3-89664.6"
+ attribute \src "libresoc.v:89429.3-89489.6"
wire width 3 $1\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:89238.3-89298.6"
+ attribute \src "libresoc.v:89063.3-89123.6"
wire width 3 $1\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:89299.3-89359.6"
+ attribute \src "libresoc.v:89124.3-89184.6"
wire width 3 $1\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:89360.3-89420.6"
+ attribute \src "libresoc.v:89185.3-89245.6"
wire width 3 $1\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:89482.3-89542.6"
+ attribute \src "libresoc.v:89307.3-89367.6"
wire width 3 $1\dec31_sv_out2[2:0]
- attribute \src "libresoc.v:89421.3-89481.6"
+ attribute \src "libresoc.v:89246.3-89306.6"
wire width 3 $1\dec31_sv_out[2:0]
- attribute \src "libresoc.v:89726.3-89786.6"
+ attribute \src "libresoc.v:89551.3-89611.6"
wire width 2 $1\dec31_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_upd
- attribute \src "libresoc.v:81892.7-81892.15"
+ attribute \src "libresoc.v:81717.7-81717.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349"
wire width 5 \opc_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 10 \opcode_switch
attribute \module_not_derived 1
- attribute \src "libresoc.v:87858.18-87893.4"
+ attribute \src "libresoc.v:87683.18-87718.4"
cell \dec31_dec_sub0 \dec31_dec_sub0
connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype
connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype
connect \opcode_in \dec31_dec_sub0_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87894.19-87929.4"
+ attribute \src "libresoc.v:87719.19-87754.4"
cell \dec31_dec_sub10 \dec31_dec_sub10
connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype
connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype
connect \opcode_in \dec31_dec_sub10_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87930.19-87965.4"
+ attribute \src "libresoc.v:87755.19-87790.4"
cell \dec31_dec_sub11 \dec31_dec_sub11
connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype
connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype
connect \opcode_in \dec31_dec_sub11_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87966.19-88001.4"
+ attribute \src "libresoc.v:87791.19-87826.4"
cell \dec31_dec_sub15 \dec31_dec_sub15
connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype
connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype
connect \opcode_in \dec31_dec_sub15_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88002.19-88037.4"
+ attribute \src "libresoc.v:87827.19-87862.4"
cell \dec31_dec_sub16 \dec31_dec_sub16
connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype
connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype
connect \opcode_in \dec31_dec_sub16_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88038.19-88073.4"
+ attribute \src "libresoc.v:87863.19-87898.4"
cell \dec31_dec_sub18 \dec31_dec_sub18
connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype
connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype
connect \opcode_in \dec31_dec_sub18_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88074.19-88109.4"
+ attribute \src "libresoc.v:87899.19-87934.4"
cell \dec31_dec_sub19 \dec31_dec_sub19
connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype
connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype
connect \opcode_in \dec31_dec_sub19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88110.19-88145.4"
+ attribute \src "libresoc.v:87935.19-87970.4"
cell \dec31_dec_sub20 \dec31_dec_sub20
connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype
connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype
connect \opcode_in \dec31_dec_sub20_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88146.19-88181.4"
+ attribute \src "libresoc.v:87971.19-88006.4"
cell \dec31_dec_sub21 \dec31_dec_sub21
connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype
connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype
connect \opcode_in \dec31_dec_sub21_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88182.19-88217.4"
+ attribute \src "libresoc.v:88007.19-88042.4"
cell \dec31_dec_sub22 \dec31_dec_sub22
connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype
connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype
connect \opcode_in \dec31_dec_sub22_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88218.19-88253.4"
+ attribute \src "libresoc.v:88043.19-88078.4"
cell \dec31_dec_sub23 \dec31_dec_sub23
connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype
connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype
connect \opcode_in \dec31_dec_sub23_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88254.19-88289.4"
+ attribute \src "libresoc.v:88079.19-88114.4"
cell \dec31_dec_sub24 \dec31_dec_sub24
connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype
connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype
connect \opcode_in \dec31_dec_sub24_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88290.19-88325.4"
+ attribute \src "libresoc.v:88115.19-88150.4"
cell \dec31_dec_sub26 \dec31_dec_sub26
connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype
connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype
connect \opcode_in \dec31_dec_sub26_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88326.19-88361.4"
+ attribute \src "libresoc.v:88151.19-88186.4"
cell \dec31_dec_sub27 \dec31_dec_sub27
connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype
connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype
connect \opcode_in \dec31_dec_sub27_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88362.19-88397.4"
+ attribute \src "libresoc.v:88187.19-88222.4"
cell \dec31_dec_sub28 \dec31_dec_sub28
connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype
connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype
connect \opcode_in \dec31_dec_sub28_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88398.18-88433.4"
+ attribute \src "libresoc.v:88223.18-88258.4"
cell \dec31_dec_sub4 \dec31_dec_sub4
connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype
connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype
connect \opcode_in \dec31_dec_sub4_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88434.18-88469.4"
+ attribute \src "libresoc.v:88259.18-88294.4"
cell \dec31_dec_sub8 \dec31_dec_sub8
connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype
connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype
connect \opcode_in \dec31_dec_sub8_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:88470.18-88505.4"
+ attribute \src "libresoc.v:88295.18-88330.4"
cell \dec31_dec_sub9 \dec31_dec_sub9
connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype
connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype
connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd
connect \opcode_in \dec31_dec_sub9_opcode_in
end
- attribute \src "libresoc.v:81892.7-81892.20"
- process $proc$libresoc.v:81892$3850
+ attribute \src "libresoc.v:81717.7-81717.20"
+ process $proc$libresoc.v:81717$3834
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:88506.3-88566.6"
- process $proc$libresoc.v:88506$3817
+ attribute \src "libresoc.v:88331.3-88391.6"
+ process $proc$libresoc.v:88331$3801
assign { } { }
assign { } { }
assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0]
- attribute \src "libresoc.v:88507.5-88507.29"
+ attribute \src "libresoc.v:88332.5-88332.29"
switch \initial
- attribute \src "libresoc.v:88507.9-88507.17"
+ attribute \src "libresoc.v:88332.9-88332.17"
case 1'1
case
end
sync always
update \dec31_function_unit $0\dec31_function_unit[13:0]
end
- attribute \src "libresoc.v:88567.3-88627.6"
- process $proc$libresoc.v:88567$3818
+ attribute \src "libresoc.v:88392.3-88452.6"
+ process $proc$libresoc.v:88392$3802
assign { } { }
assign { } { }
assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:88568.5-88568.29"
+ attribute \src "libresoc.v:88393.5-88393.29"
switch \initial
- attribute \src "libresoc.v:88568.9-88568.17"
+ attribute \src "libresoc.v:88393.9-88393.17"
case 1'1
case
end
sync always
update \dec31_internal_op $0\dec31_internal_op[6:0]
end
- attribute \src "libresoc.v:88628.3-88688.6"
- process $proc$libresoc.v:88628$3819
+ attribute \src "libresoc.v:88453.3-88513.6"
+ process $proc$libresoc.v:88453$3803
assign { } { }
assign { } { }
assign $0\dec31_form[4:0] $1\dec31_form[4:0]
- attribute \src "libresoc.v:88629.5-88629.29"
+ attribute \src "libresoc.v:88454.5-88454.29"
switch \initial
- attribute \src "libresoc.v:88629.9-88629.17"
+ attribute \src "libresoc.v:88454.9-88454.17"
case 1'1
case
end
sync always
update \dec31_form $0\dec31_form[4:0]
end
- attribute \src "libresoc.v:88689.3-88749.6"
- process $proc$libresoc.v:88689$3820
+ attribute \src "libresoc.v:88514.3-88574.6"
+ process $proc$libresoc.v:88514$3804
assign { } { }
assign { } { }
assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:88690.5-88690.29"
+ attribute \src "libresoc.v:88515.5-88515.29"
switch \initial
- attribute \src "libresoc.v:88690.9-88690.17"
+ attribute \src "libresoc.v:88515.9-88515.17"
case 1'1
case
end
sync always
update \dec31_asmcode $0\dec31_asmcode[7:0]
end
- attribute \src "libresoc.v:88750.3-88810.6"
- process $proc$libresoc.v:88750$3821
+ attribute \src "libresoc.v:88575.3-88635.6"
+ process $proc$libresoc.v:88575$3805
assign { } { }
assign { } { }
assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:88751.5-88751.29"
+ attribute \src "libresoc.v:88576.5-88576.29"
switch \initial
- attribute \src "libresoc.v:88751.9-88751.17"
+ attribute \src "libresoc.v:88576.9-88576.17"
case 1'1
case
end
sync always
update \dec31_SV_Etype $0\dec31_SV_Etype[1:0]
end
- attribute \src "libresoc.v:88811.3-88871.6"
- process $proc$libresoc.v:88811$3822
+ attribute \src "libresoc.v:88636.3-88696.6"
+ process $proc$libresoc.v:88636$3806
assign { } { }
assign { } { }
assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:88812.5-88812.29"
+ attribute \src "libresoc.v:88637.5-88637.29"
switch \initial
- attribute \src "libresoc.v:88812.9-88812.17"
+ attribute \src "libresoc.v:88637.9-88637.17"
case 1'1
case
end
sync always
update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:88872.3-88932.6"
- process $proc$libresoc.v:88872$3823
+ attribute \src "libresoc.v:88697.3-88757.6"
+ process $proc$libresoc.v:88697$3807
assign { } { }
assign { } { }
assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:88873.5-88873.29"
+ attribute \src "libresoc.v:88698.5-88698.29"
switch \initial
- attribute \src "libresoc.v:88873.9-88873.17"
+ attribute \src "libresoc.v:88698.9-88698.17"
case 1'1
case
end
sync always
update \dec31_in1_sel $0\dec31_in1_sel[2:0]
end
- attribute \src "libresoc.v:88933.3-88993.6"
- process $proc$libresoc.v:88933$3824
+ attribute \src "libresoc.v:88758.3-88818.6"
+ process $proc$libresoc.v:88758$3808
assign { } { }
assign { } { }
assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88934.5-88934.29"
+ attribute \src "libresoc.v:88759.5-88759.29"
switch \initial
- attribute \src "libresoc.v:88934.9-88934.17"
+ attribute \src "libresoc.v:88759.9-88759.17"
case 1'1
case
end
sync always
update \dec31_in2_sel $0\dec31_in2_sel[3:0]
end
- attribute \src "libresoc.v:88994.3-89054.6"
- process $proc$libresoc.v:88994$3825
+ attribute \src "libresoc.v:88819.3-88879.6"
+ process $proc$libresoc.v:88819$3809
assign { } { }
assign { } { }
assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:88995.5-88995.29"
+ attribute \src "libresoc.v:88820.5-88820.29"
switch \initial
- attribute \src "libresoc.v:88995.9-88995.17"
+ attribute \src "libresoc.v:88820.9-88820.17"
case 1'1
case
end
sync always
update \dec31_in3_sel $0\dec31_in3_sel[1:0]
end
- attribute \src "libresoc.v:89055.3-89115.6"
- process $proc$libresoc.v:89055$3826
+ attribute \src "libresoc.v:88880.3-88940.6"
+ process $proc$libresoc.v:88880$3810
assign { } { }
assign { } { }
assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0]
- attribute \src "libresoc.v:89056.5-89056.29"
+ attribute \src "libresoc.v:88881.5-88881.29"
switch \initial
- attribute \src "libresoc.v:89056.9-89056.17"
+ attribute \src "libresoc.v:88881.9-88881.17"
case 1'1
case
end
sync always
update \dec31_out_sel $0\dec31_out_sel[2:0]
end
- attribute \src "libresoc.v:89116.3-89176.6"
- process $proc$libresoc.v:89116$3827
+ attribute \src "libresoc.v:88941.3-89001.6"
+ process $proc$libresoc.v:88941$3811
assign { } { }
assign { } { }
assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:89117.5-89117.29"
+ attribute \src "libresoc.v:88942.5-88942.29"
switch \initial
- attribute \src "libresoc.v:89117.9-89117.17"
+ attribute \src "libresoc.v:88942.9-88942.17"
case 1'1
case
end
sync always
update \dec31_cr_in $0\dec31_cr_in[2:0]
end
- attribute \src "libresoc.v:89177.3-89237.6"
- process $proc$libresoc.v:89177$3828
+ attribute \src "libresoc.v:89002.3-89062.6"
+ process $proc$libresoc.v:89002$3812
assign { } { }
assign { } { }
assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:89178.5-89178.29"
+ attribute \src "libresoc.v:89003.5-89003.29"
switch \initial
- attribute \src "libresoc.v:89178.9-89178.17"
+ attribute \src "libresoc.v:89003.9-89003.17"
case 1'1
case
end
sync always
update \dec31_cr_out $0\dec31_cr_out[2:0]
end
- attribute \src "libresoc.v:89238.3-89298.6"
- process $proc$libresoc.v:89238$3829
+ attribute \src "libresoc.v:89063.3-89123.6"
+ process $proc$libresoc.v:89063$3813
assign { } { }
assign { } { }
assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:89239.5-89239.29"
+ attribute \src "libresoc.v:89064.5-89064.29"
switch \initial
- attribute \src "libresoc.v:89239.9-89239.17"
+ attribute \src "libresoc.v:89064.9-89064.17"
case 1'1
case
end
sync always
update \dec31_sv_in1 $0\dec31_sv_in1[2:0]
end
- attribute \src "libresoc.v:89299.3-89359.6"
- process $proc$libresoc.v:89299$3830
+ attribute \src "libresoc.v:89124.3-89184.6"
+ process $proc$libresoc.v:89124$3814
assign { } { }
assign { } { }
assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:89300.5-89300.29"
+ attribute \src "libresoc.v:89125.5-89125.29"
switch \initial
- attribute \src "libresoc.v:89300.9-89300.17"
+ attribute \src "libresoc.v:89125.9-89125.17"
case 1'1
case
end
sync always
update \dec31_sv_in2 $0\dec31_sv_in2[2:0]
end
- attribute \src "libresoc.v:89360.3-89420.6"
- process $proc$libresoc.v:89360$3831
+ attribute \src "libresoc.v:89185.3-89245.6"
+ process $proc$libresoc.v:89185$3815
assign { } { }
assign { } { }
assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:89361.5-89361.29"
+ attribute \src "libresoc.v:89186.5-89186.29"
switch \initial
- attribute \src "libresoc.v:89361.9-89361.17"
+ attribute \src "libresoc.v:89186.9-89186.17"
case 1'1
case
end
sync always
update \dec31_sv_in3 $0\dec31_sv_in3[2:0]
end
- attribute \src "libresoc.v:89421.3-89481.6"
- process $proc$libresoc.v:89421$3832
+ attribute \src "libresoc.v:89246.3-89306.6"
+ process $proc$libresoc.v:89246$3816
assign { } { }
assign { } { }
assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0]
- attribute \src "libresoc.v:89422.5-89422.29"
+ attribute \src "libresoc.v:89247.5-89247.29"
switch \initial
- attribute \src "libresoc.v:89422.9-89422.17"
+ attribute \src "libresoc.v:89247.9-89247.17"
case 1'1
case
end
sync always
update \dec31_sv_out $0\dec31_sv_out[2:0]
end
- attribute \src "libresoc.v:89482.3-89542.6"
- process $proc$libresoc.v:89482$3833
+ attribute \src "libresoc.v:89307.3-89367.6"
+ process $proc$libresoc.v:89307$3817
assign { } { }
assign { } { }
assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0]
- attribute \src "libresoc.v:89483.5-89483.29"
+ attribute \src "libresoc.v:89308.5-89308.29"
switch \initial
- attribute \src "libresoc.v:89483.9-89483.17"
+ attribute \src "libresoc.v:89308.9-89308.17"
case 1'1
case
end
sync always
update \dec31_sv_out2 $0\dec31_sv_out2[2:0]
end
- attribute \src "libresoc.v:89543.3-89603.6"
- process $proc$libresoc.v:89543$3834
+ attribute \src "libresoc.v:89368.3-89428.6"
+ process $proc$libresoc.v:89368$3818
assign { } { }
assign { } { }
assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:89544.5-89544.29"
+ attribute \src "libresoc.v:89369.5-89369.29"
switch \initial
- attribute \src "libresoc.v:89544.9-89544.17"
+ attribute \src "libresoc.v:89369.9-89369.17"
case 1'1
case
end
sync always
update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:89604.3-89664.6"
- process $proc$libresoc.v:89604$3835
+ attribute \src "libresoc.v:89429.3-89489.6"
+ process $proc$libresoc.v:89429$3819
assign { } { }
assign { } { }
assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:89605.5-89605.29"
+ attribute \src "libresoc.v:89430.5-89430.29"
switch \initial
- attribute \src "libresoc.v:89605.9-89605.17"
+ attribute \src "libresoc.v:89430.9-89430.17"
case 1'1
case
end
sync always
update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:89665.3-89725.6"
- process $proc$libresoc.v:89665$3836
+ attribute \src "libresoc.v:89490.3-89550.6"
+ process $proc$libresoc.v:89490$3820
assign { } { }
assign { } { }
assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:89666.5-89666.29"
+ attribute \src "libresoc.v:89491.5-89491.29"
switch \initial
- attribute \src "libresoc.v:89666.9-89666.17"
+ attribute \src "libresoc.v:89491.9-89491.17"
case 1'1
case
end
sync always
update \dec31_ldst_len $0\dec31_ldst_len[3:0]
end
- attribute \src "libresoc.v:89726.3-89786.6"
- process $proc$libresoc.v:89726$3837
+ attribute \src "libresoc.v:89551.3-89611.6"
+ process $proc$libresoc.v:89551$3821
assign { } { }
assign { } { }
assign $0\dec31_upd[1:0] $1\dec31_upd[1:0]
- attribute \src "libresoc.v:89727.5-89727.29"
+ attribute \src "libresoc.v:89552.5-89552.29"
switch \initial
- attribute \src "libresoc.v:89727.9-89727.17"
+ attribute \src "libresoc.v:89552.9-89552.17"
case 1'1
case
end
sync always
update \dec31_upd $0\dec31_upd[1:0]
end
- attribute \src "libresoc.v:89787.3-89847.6"
- process $proc$libresoc.v:89787$3838
+ attribute \src "libresoc.v:89612.3-89672.6"
+ process $proc$libresoc.v:89612$3822
assign { } { }
assign { } { }
assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:89788.5-89788.29"
+ attribute \src "libresoc.v:89613.5-89613.29"
switch \initial
- attribute \src "libresoc.v:89788.9-89788.17"
+ attribute \src "libresoc.v:89613.9-89613.17"
case 1'1
case
end
sync always
update \dec31_rc_sel $0\dec31_rc_sel[1:0]
end
- attribute \src "libresoc.v:89848.3-89908.6"
- process $proc$libresoc.v:89848$3839
+ attribute \src "libresoc.v:89673.3-89733.6"
+ process $proc$libresoc.v:89673$3823
assign { } { }
assign { } { }
assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:89849.5-89849.29"
+ attribute \src "libresoc.v:89674.5-89674.29"
switch \initial
- attribute \src "libresoc.v:89849.9-89849.17"
+ attribute \src "libresoc.v:89674.9-89674.17"
case 1'1
case
end
sync always
update \dec31_cry_in $0\dec31_cry_in[1:0]
end
- attribute \src "libresoc.v:89909.3-89969.6"
- process $proc$libresoc.v:89909$3840
+ attribute \src "libresoc.v:89734.3-89794.6"
+ process $proc$libresoc.v:89734$3824
assign { } { }
assign { } { }
assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:89910.5-89910.29"
+ attribute \src "libresoc.v:89735.5-89735.29"
switch \initial
- attribute \src "libresoc.v:89910.9-89910.17"
+ attribute \src "libresoc.v:89735.9-89735.17"
case 1'1
case
end
sync always
update \dec31_inv_a $0\dec31_inv_a[0:0]
end
- attribute \src "libresoc.v:89970.3-90030.6"
- process $proc$libresoc.v:89970$3841
+ attribute \src "libresoc.v:89795.3-89855.6"
+ process $proc$libresoc.v:89795$3825
assign { } { }
assign { } { }
assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:89971.5-89971.29"
+ attribute \src "libresoc.v:89796.5-89796.29"
switch \initial
- attribute \src "libresoc.v:89971.9-89971.17"
+ attribute \src "libresoc.v:89796.9-89796.17"
case 1'1
case
end
sync always
update \dec31_inv_out $0\dec31_inv_out[0:0]
end
- attribute \src "libresoc.v:90031.3-90091.6"
- process $proc$libresoc.v:90031$3842
+ attribute \src "libresoc.v:89856.3-89916.6"
+ process $proc$libresoc.v:89856$3826
assign { } { }
assign { } { }
assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:90032.5-90032.29"
+ attribute \src "libresoc.v:89857.5-89857.29"
switch \initial
- attribute \src "libresoc.v:90032.9-90032.17"
+ attribute \src "libresoc.v:89857.9-89857.17"
case 1'1
case
end
sync always
update \dec31_cry_out $0\dec31_cry_out[0:0]
end
- attribute \src "libresoc.v:90092.3-90152.6"
- process $proc$libresoc.v:90092$3843
+ attribute \src "libresoc.v:89917.3-89977.6"
+ process $proc$libresoc.v:89917$3827
assign { } { }
assign { } { }
assign $0\dec31_br[0:0] $1\dec31_br[0:0]
- attribute \src "libresoc.v:90093.5-90093.29"
+ attribute \src "libresoc.v:89918.5-89918.29"
switch \initial
- attribute \src "libresoc.v:90093.9-90093.17"
+ attribute \src "libresoc.v:89918.9-89918.17"
case 1'1
case
end
sync always
update \dec31_br $0\dec31_br[0:0]
end
- attribute \src "libresoc.v:90153.3-90213.6"
- process $proc$libresoc.v:90153$3844
+ attribute \src "libresoc.v:89978.3-90038.6"
+ process $proc$libresoc.v:89978$3828
assign { } { }
assign { } { }
assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:90154.5-90154.29"
+ attribute \src "libresoc.v:89979.5-89979.29"
switch \initial
- attribute \src "libresoc.v:90154.9-90154.17"
+ attribute \src "libresoc.v:89979.9-89979.17"
case 1'1
case
end
sync always
update \dec31_sgn_ext $0\dec31_sgn_ext[0:0]
end
- attribute \src "libresoc.v:90214.3-90274.6"
- process $proc$libresoc.v:90214$3845
+ attribute \src "libresoc.v:90039.3-90099.6"
+ process $proc$libresoc.v:90039$3829
assign { } { }
assign { } { }
assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:90215.5-90215.29"
+ attribute \src "libresoc.v:90040.5-90040.29"
switch \initial
- attribute \src "libresoc.v:90215.9-90215.17"
+ attribute \src "libresoc.v:90040.9-90040.17"
case 1'1
case
end
sync always
update \dec31_rsrv $0\dec31_rsrv[0:0]
end
- attribute \src "libresoc.v:90275.3-90335.6"
- process $proc$libresoc.v:90275$3846
+ attribute \src "libresoc.v:90100.3-90160.6"
+ process $proc$libresoc.v:90100$3830
assign { } { }
assign { } { }
assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:90276.5-90276.29"
+ attribute \src "libresoc.v:90101.5-90101.29"
switch \initial
- attribute \src "libresoc.v:90276.9-90276.17"
+ attribute \src "libresoc.v:90101.9-90101.17"
case 1'1
case
end
sync always
update \dec31_is_32b $0\dec31_is_32b[0:0]
end
- attribute \src "libresoc.v:90336.3-90396.6"
- process $proc$libresoc.v:90336$3847
+ attribute \src "libresoc.v:90161.3-90221.6"
+ process $proc$libresoc.v:90161$3831
assign { } { }
assign { } { }
assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:90337.5-90337.29"
+ attribute \src "libresoc.v:90162.5-90162.29"
switch \initial
- attribute \src "libresoc.v:90337.9-90337.17"
+ attribute \src "libresoc.v:90162.9-90162.17"
case 1'1
case
end
sync always
update \dec31_sgn $0\dec31_sgn[0:0]
end
- attribute \src "libresoc.v:90397.3-90457.6"
- process $proc$libresoc.v:90397$3848
+ attribute \src "libresoc.v:90222.3-90282.6"
+ process $proc$libresoc.v:90222$3832
assign { } { }
assign { } { }
assign $0\dec31_lk[0:0] $1\dec31_lk[0:0]
- attribute \src "libresoc.v:90398.5-90398.29"
+ attribute \src "libresoc.v:90223.5-90223.29"
switch \initial
- attribute \src "libresoc.v:90398.9-90398.17"
+ attribute \src "libresoc.v:90223.9-90223.17"
case 1'1
case
end
sync always
update \dec31_lk $0\dec31_lk[0:0]
end
- attribute \src "libresoc.v:90458.3-90518.6"
- process $proc$libresoc.v:90458$3849
+ attribute \src "libresoc.v:90283.3-90343.6"
+ process $proc$libresoc.v:90283$3833
assign { } { }
assign { } { }
assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:90459.5-90459.29"
+ attribute \src "libresoc.v:90284.5-90284.29"
switch \initial
- attribute \src "libresoc.v:90459.9-90459.17"
+ attribute \src "libresoc.v:90284.9-90284.17"
case 1'1
case
end
connect \opc_in \opcode_switch [4:0]
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:90543.1-91520.10"
+attribute \src "libresoc.v:90368.1-91345.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0"
attribute \generator "nMigen"
module \dec31_dec_sub0
- attribute \src "libresoc.v:91405.3-91423.6"
+ attribute \src "libresoc.v:91230.3-91248.6"
wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:91424.3-91442.6"
+ attribute \src "libresoc.v:91249.3-91267.6"
wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:91177.3-91195.6"
+ attribute \src "libresoc.v:91002.3-91020.6"
wire width 8 $0\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:91253.3-91271.6"
+ attribute \src "libresoc.v:91078.3-91096.6"
wire $0\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:90911.3-90929.6"
+ attribute \src "libresoc.v:90736.3-90754.6"
wire width 3 $0\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:90930.3-90948.6"
+ attribute \src "libresoc.v:90755.3-90773.6"
wire width 3 $0\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:91158.3-91176.6"
+ attribute \src "libresoc.v:90983.3-91001.6"
wire width 2 $0\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:91234.3-91252.6"
+ attribute \src "libresoc.v:91059.3-91077.6"
wire $0\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:91310.3-91328.6"
+ attribute \src "libresoc.v:91135.3-91153.6"
wire width 5 $0\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:90892.3-90910.6"
+ attribute \src "libresoc.v:90717.3-90735.6"
wire width 14 $0\dec31_dec_sub0_function_unit[13:0]
- attribute \src "libresoc.v:91443.3-91461.6"
+ attribute \src "libresoc.v:91268.3-91286.6"
wire width 3 $0\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:91462.3-91480.6"
+ attribute \src "libresoc.v:91287.3-91305.6"
wire width 4 $0\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:91481.3-91499.6"
+ attribute \src "libresoc.v:91306.3-91324.6"
wire width 2 $0\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:91101.3-91119.6"
+ attribute \src "libresoc.v:90926.3-90944.6"
wire width 7 $0\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:91196.3-91214.6"
+ attribute \src "libresoc.v:91021.3-91039.6"
wire $0\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:91215.3-91233.6"
+ attribute \src "libresoc.v:91040.3-91058.6"
wire $0\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:91329.3-91347.6"
+ attribute \src "libresoc.v:91154.3-91172.6"
wire $0\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:91082.3-91100.6"
+ attribute \src "libresoc.v:90907.3-90925.6"
wire width 4 $0\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:91367.3-91385.6"
+ attribute \src "libresoc.v:91192.3-91210.6"
wire $0\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:91500.3-91518.6"
+ attribute \src "libresoc.v:91325.3-91343.6"
wire width 3 $0\dec31_dec_sub0_out_sel[2:0]
- attribute \src "libresoc.v:91139.3-91157.6"
+ attribute \src "libresoc.v:90964.3-90982.6"
wire width 2 $0\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:91291.3-91309.6"
+ attribute \src "libresoc.v:91116.3-91134.6"
wire $0\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:91386.3-91404.6"
+ attribute \src "libresoc.v:91211.3-91229.6"
wire $0\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:91348.3-91366.6"
+ attribute \src "libresoc.v:91173.3-91191.6"
wire $0\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:91272.3-91290.6"
+ attribute \src "libresoc.v:91097.3-91115.6"
wire $0\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:91044.3-91062.6"
+ attribute \src "libresoc.v:90869.3-90887.6"
wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:91063.3-91081.6"
+ attribute \src "libresoc.v:90888.3-90906.6"
wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:90949.3-90967.6"
+ attribute \src "libresoc.v:90774.3-90792.6"
wire width 3 $0\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90968.3-90986.6"
+ attribute \src "libresoc.v:90793.3-90811.6"
wire width 3 $0\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90987.3-91005.6"
+ attribute \src "libresoc.v:90812.3-90830.6"
wire width 3 $0\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:91025.3-91043.6"
+ attribute \src "libresoc.v:90850.3-90868.6"
wire width 3 $0\dec31_dec_sub0_sv_out2[2:0]
- attribute \src "libresoc.v:91006.3-91024.6"
+ attribute \src "libresoc.v:90831.3-90849.6"
wire width 3 $0\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:91120.3-91138.6"
+ attribute \src "libresoc.v:90945.3-90963.6"
wire width 2 $0\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:90544.7-90544.20"
+ attribute \src "libresoc.v:90369.7-90369.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:91405.3-91423.6"
+ attribute \src "libresoc.v:91230.3-91248.6"
wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:91424.3-91442.6"
+ attribute \src "libresoc.v:91249.3-91267.6"
wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:91177.3-91195.6"
+ attribute \src "libresoc.v:91002.3-91020.6"
wire width 8 $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:91253.3-91271.6"
+ attribute \src "libresoc.v:91078.3-91096.6"
wire $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:90911.3-90929.6"
+ attribute \src "libresoc.v:90736.3-90754.6"
wire width 3 $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:90930.3-90948.6"
+ attribute \src "libresoc.v:90755.3-90773.6"
wire width 3 $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:91158.3-91176.6"
+ attribute \src "libresoc.v:90983.3-91001.6"
wire width 2 $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:91234.3-91252.6"
+ attribute \src "libresoc.v:91059.3-91077.6"
wire $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:91310.3-91328.6"
+ attribute \src "libresoc.v:91135.3-91153.6"
wire width 5 $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:90892.3-90910.6"
+ attribute \src "libresoc.v:90717.3-90735.6"
wire width 14 $1\dec31_dec_sub0_function_unit[13:0]
- attribute \src "libresoc.v:91443.3-91461.6"
+ attribute \src "libresoc.v:91268.3-91286.6"
wire width 3 $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:91462.3-91480.6"
+ attribute \src "libresoc.v:91287.3-91305.6"
wire width 4 $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:91481.3-91499.6"
+ attribute \src "libresoc.v:91306.3-91324.6"
wire width 2 $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:91101.3-91119.6"
+ attribute \src "libresoc.v:90926.3-90944.6"
wire width 7 $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:91196.3-91214.6"
+ attribute \src "libresoc.v:91021.3-91039.6"
wire $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:91215.3-91233.6"
+ attribute \src "libresoc.v:91040.3-91058.6"
wire $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:91329.3-91347.6"
+ attribute \src "libresoc.v:91154.3-91172.6"
wire $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:91082.3-91100.6"
+ attribute \src "libresoc.v:90907.3-90925.6"
wire width 4 $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:91367.3-91385.6"
+ attribute \src "libresoc.v:91192.3-91210.6"
wire $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:91500.3-91518.6"
+ attribute \src "libresoc.v:91325.3-91343.6"
wire width 3 $1\dec31_dec_sub0_out_sel[2:0]
- attribute \src "libresoc.v:91139.3-91157.6"
+ attribute \src "libresoc.v:90964.3-90982.6"
wire width 2 $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:91291.3-91309.6"
+ attribute \src "libresoc.v:91116.3-91134.6"
wire $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:91386.3-91404.6"
+ attribute \src "libresoc.v:91211.3-91229.6"
wire $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:91348.3-91366.6"
+ attribute \src "libresoc.v:91173.3-91191.6"
wire $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:91272.3-91290.6"
+ attribute \src "libresoc.v:91097.3-91115.6"
wire $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:91044.3-91062.6"
+ attribute \src "libresoc.v:90869.3-90887.6"
wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:91063.3-91081.6"
+ attribute \src "libresoc.v:90888.3-90906.6"
wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:90949.3-90967.6"
+ attribute \src "libresoc.v:90774.3-90792.6"
wire width 3 $1\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90968.3-90986.6"
+ attribute \src "libresoc.v:90793.3-90811.6"
wire width 3 $1\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90987.3-91005.6"
+ attribute \src "libresoc.v:90812.3-90830.6"
wire width 3 $1\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:91025.3-91043.6"
+ attribute \src "libresoc.v:90850.3-90868.6"
wire width 3 $1\dec31_dec_sub0_sv_out2[2:0]
- attribute \src "libresoc.v:91006.3-91024.6"
+ attribute \src "libresoc.v:90831.3-90849.6"
wire width 3 $1\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:91120.3-91138.6"
+ attribute \src "libresoc.v:90945.3-90963.6"
wire width 2 $1\dec31_dec_sub0_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub0_upd
- attribute \src "libresoc.v:90544.7-90544.15"
+ attribute \src "libresoc.v:90369.7-90369.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:90544.7-90544.20"
- process $proc$libresoc.v:90544$3884
+ attribute \src "libresoc.v:90369.7-90369.20"
+ process $proc$libresoc.v:90369$3868
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:90892.3-90910.6"
- process $proc$libresoc.v:90892$3851
+ attribute \src "libresoc.v:90717.3-90735.6"
+ process $proc$libresoc.v:90717$3835
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0]
- attribute \src "libresoc.v:90893.5-90893.29"
+ attribute \src "libresoc.v:90718.5-90718.29"
switch \initial
- attribute \src "libresoc.v:90893.9-90893.17"
+ attribute \src "libresoc.v:90718.9-90718.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0]
end
- attribute \src "libresoc.v:90911.3-90929.6"
- process $proc$libresoc.v:90911$3852
+ attribute \src "libresoc.v:90736.3-90754.6"
+ process $proc$libresoc.v:90736$3836
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:90912.5-90912.29"
+ attribute \src "libresoc.v:90737.5-90737.29"
switch \initial
- attribute \src "libresoc.v:90912.9-90912.17"
+ attribute \src "libresoc.v:90737.9-90737.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0]
end
- attribute \src "libresoc.v:90930.3-90948.6"
- process $proc$libresoc.v:90930$3853
+ attribute \src "libresoc.v:90755.3-90773.6"
+ process $proc$libresoc.v:90755$3837
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:90931.5-90931.29"
+ attribute \src "libresoc.v:90756.5-90756.29"
switch \initial
- attribute \src "libresoc.v:90931.9-90931.17"
+ attribute \src "libresoc.v:90756.9-90756.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0]
end
- attribute \src "libresoc.v:90949.3-90967.6"
- process $proc$libresoc.v:90949$3854
+ attribute \src "libresoc.v:90774.3-90792.6"
+ process $proc$libresoc.v:90774$3838
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90950.5-90950.29"
+ attribute \src "libresoc.v:90775.5-90775.29"
switch \initial
- attribute \src "libresoc.v:90950.9-90950.17"
+ attribute \src "libresoc.v:90775.9-90775.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0]
end
- attribute \src "libresoc.v:90968.3-90986.6"
- process $proc$libresoc.v:90968$3855
+ attribute \src "libresoc.v:90793.3-90811.6"
+ process $proc$libresoc.v:90793$3839
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90969.5-90969.29"
+ attribute \src "libresoc.v:90794.5-90794.29"
switch \initial
- attribute \src "libresoc.v:90969.9-90969.17"
+ attribute \src "libresoc.v:90794.9-90794.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0]
end
- attribute \src "libresoc.v:90987.3-91005.6"
- process $proc$libresoc.v:90987$3856
+ attribute \src "libresoc.v:90812.3-90830.6"
+ process $proc$libresoc.v:90812$3840
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:90988.5-90988.29"
+ attribute \src "libresoc.v:90813.5-90813.29"
switch \initial
- attribute \src "libresoc.v:90988.9-90988.17"
+ attribute \src "libresoc.v:90813.9-90813.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0]
end
- attribute \src "libresoc.v:91006.3-91024.6"
- process $proc$libresoc.v:91006$3857
+ attribute \src "libresoc.v:90831.3-90849.6"
+ process $proc$libresoc.v:90831$3841
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:91007.5-91007.29"
+ attribute \src "libresoc.v:90832.5-90832.29"
switch \initial
- attribute \src "libresoc.v:91007.9-91007.17"
+ attribute \src "libresoc.v:90832.9-90832.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0]
end
- attribute \src "libresoc.v:91025.3-91043.6"
- process $proc$libresoc.v:91025$3858
+ attribute \src "libresoc.v:90850.3-90868.6"
+ process $proc$libresoc.v:90850$3842
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0]
- attribute \src "libresoc.v:91026.5-91026.29"
+ attribute \src "libresoc.v:90851.5-90851.29"
switch \initial
- attribute \src "libresoc.v:91026.9-91026.17"
+ attribute \src "libresoc.v:90851.9-90851.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0]
end
- attribute \src "libresoc.v:91044.3-91062.6"
- process $proc$libresoc.v:91044$3859
+ attribute \src "libresoc.v:90869.3-90887.6"
+ process $proc$libresoc.v:90869$3843
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:91045.5-91045.29"
+ attribute \src "libresoc.v:90870.5-90870.29"
switch \initial
- attribute \src "libresoc.v:91045.9-91045.17"
+ attribute \src "libresoc.v:90870.9-90870.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:91063.3-91081.6"
- process $proc$libresoc.v:91063$3860
+ attribute \src "libresoc.v:90888.3-90906.6"
+ process $proc$libresoc.v:90888$3844
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:91064.5-91064.29"
+ attribute \src "libresoc.v:90889.5-90889.29"
switch \initial
- attribute \src "libresoc.v:91064.9-91064.17"
+ attribute \src "libresoc.v:90889.9-90889.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:91082.3-91100.6"
- process $proc$libresoc.v:91082$3861
+ attribute \src "libresoc.v:90907.3-90925.6"
+ process $proc$libresoc.v:90907$3845
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:91083.5-91083.29"
+ attribute \src "libresoc.v:90908.5-90908.29"
switch \initial
- attribute \src "libresoc.v:91083.9-91083.17"
+ attribute \src "libresoc.v:90908.9-90908.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0]
end
- attribute \src "libresoc.v:91101.3-91119.6"
- process $proc$libresoc.v:91101$3862
+ attribute \src "libresoc.v:90926.3-90944.6"
+ process $proc$libresoc.v:90926$3846
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:91102.5-91102.29"
+ attribute \src "libresoc.v:90927.5-90927.29"
switch \initial
- attribute \src "libresoc.v:91102.9-91102.17"
+ attribute \src "libresoc.v:90927.9-90927.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0]
end
- attribute \src "libresoc.v:91120.3-91138.6"
- process $proc$libresoc.v:91120$3863
+ attribute \src "libresoc.v:90945.3-90963.6"
+ process $proc$libresoc.v:90945$3847
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:91121.5-91121.29"
+ attribute \src "libresoc.v:90946.5-90946.29"
switch \initial
- attribute \src "libresoc.v:91121.9-91121.17"
+ attribute \src "libresoc.v:90946.9-90946.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0]
end
- attribute \src "libresoc.v:91139.3-91157.6"
- process $proc$libresoc.v:91139$3864
+ attribute \src "libresoc.v:90964.3-90982.6"
+ process $proc$libresoc.v:90964$3848
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:91140.5-91140.29"
+ attribute \src "libresoc.v:90965.5-90965.29"
switch \initial
- attribute \src "libresoc.v:91140.9-91140.17"
+ attribute \src "libresoc.v:90965.9-90965.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0]
end
- attribute \src "libresoc.v:91158.3-91176.6"
- process $proc$libresoc.v:91158$3865
+ attribute \src "libresoc.v:90983.3-91001.6"
+ process $proc$libresoc.v:90983$3849
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:91159.5-91159.29"
+ attribute \src "libresoc.v:90984.5-90984.29"
switch \initial
- attribute \src "libresoc.v:91159.9-91159.17"
+ attribute \src "libresoc.v:90984.9-90984.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0]
end
- attribute \src "libresoc.v:91177.3-91195.6"
- process $proc$libresoc.v:91177$3866
+ attribute \src "libresoc.v:91002.3-91020.6"
+ process $proc$libresoc.v:91002$3850
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:91178.5-91178.29"
+ attribute \src "libresoc.v:91003.5-91003.29"
switch \initial
- attribute \src "libresoc.v:91178.9-91178.17"
+ attribute \src "libresoc.v:91003.9-91003.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0]
end
- attribute \src "libresoc.v:91196.3-91214.6"
- process $proc$libresoc.v:91196$3867
+ attribute \src "libresoc.v:91021.3-91039.6"
+ process $proc$libresoc.v:91021$3851
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:91197.5-91197.29"
+ attribute \src "libresoc.v:91022.5-91022.29"
switch \initial
- attribute \src "libresoc.v:91197.9-91197.17"
+ attribute \src "libresoc.v:91022.9-91022.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0]
end
- attribute \src "libresoc.v:91215.3-91233.6"
- process $proc$libresoc.v:91215$3868
+ attribute \src "libresoc.v:91040.3-91058.6"
+ process $proc$libresoc.v:91040$3852
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:91216.5-91216.29"
+ attribute \src "libresoc.v:91041.5-91041.29"
switch \initial
- attribute \src "libresoc.v:91216.9-91216.17"
+ attribute \src "libresoc.v:91041.9-91041.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0]
end
- attribute \src "libresoc.v:91234.3-91252.6"
- process $proc$libresoc.v:91234$3869
+ attribute \src "libresoc.v:91059.3-91077.6"
+ process $proc$libresoc.v:91059$3853
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:91235.5-91235.29"
+ attribute \src "libresoc.v:91060.5-91060.29"
switch \initial
- attribute \src "libresoc.v:91235.9-91235.17"
+ attribute \src "libresoc.v:91060.9-91060.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0]
end
- attribute \src "libresoc.v:91253.3-91271.6"
- process $proc$libresoc.v:91253$3870
+ attribute \src "libresoc.v:91078.3-91096.6"
+ process $proc$libresoc.v:91078$3854
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:91254.5-91254.29"
+ attribute \src "libresoc.v:91079.5-91079.29"
switch \initial
- attribute \src "libresoc.v:91254.9-91254.17"
+ attribute \src "libresoc.v:91079.9-91079.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0]
end
- attribute \src "libresoc.v:91272.3-91290.6"
- process $proc$libresoc.v:91272$3871
+ attribute \src "libresoc.v:91097.3-91115.6"
+ process $proc$libresoc.v:91097$3855
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:91273.5-91273.29"
+ attribute \src "libresoc.v:91098.5-91098.29"
switch \initial
- attribute \src "libresoc.v:91273.9-91273.17"
+ attribute \src "libresoc.v:91098.9-91098.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0]
end
- attribute \src "libresoc.v:91291.3-91309.6"
- process $proc$libresoc.v:91291$3872
+ attribute \src "libresoc.v:91116.3-91134.6"
+ process $proc$libresoc.v:91116$3856
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:91292.5-91292.29"
+ attribute \src "libresoc.v:91117.5-91117.29"
switch \initial
- attribute \src "libresoc.v:91292.9-91292.17"
+ attribute \src "libresoc.v:91117.9-91117.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0]
end
- attribute \src "libresoc.v:91310.3-91328.6"
- process $proc$libresoc.v:91310$3873
+ attribute \src "libresoc.v:91135.3-91153.6"
+ process $proc$libresoc.v:91135$3857
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:91311.5-91311.29"
+ attribute \src "libresoc.v:91136.5-91136.29"
switch \initial
- attribute \src "libresoc.v:91311.9-91311.17"
+ attribute \src "libresoc.v:91136.9-91136.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0]
end
- attribute \src "libresoc.v:91329.3-91347.6"
- process $proc$libresoc.v:91329$3874
+ attribute \src "libresoc.v:91154.3-91172.6"
+ process $proc$libresoc.v:91154$3858
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:91330.5-91330.29"
+ attribute \src "libresoc.v:91155.5-91155.29"
switch \initial
- attribute \src "libresoc.v:91330.9-91330.17"
+ attribute \src "libresoc.v:91155.9-91155.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0]
end
- attribute \src "libresoc.v:91348.3-91366.6"
- process $proc$libresoc.v:91348$3875
+ attribute \src "libresoc.v:91173.3-91191.6"
+ process $proc$libresoc.v:91173$3859
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:91349.5-91349.29"
+ attribute \src "libresoc.v:91174.5-91174.29"
switch \initial
- attribute \src "libresoc.v:91349.9-91349.17"
+ attribute \src "libresoc.v:91174.9-91174.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0]
end
- attribute \src "libresoc.v:91367.3-91385.6"
- process $proc$libresoc.v:91367$3876
+ attribute \src "libresoc.v:91192.3-91210.6"
+ process $proc$libresoc.v:91192$3860
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:91368.5-91368.29"
+ attribute \src "libresoc.v:91193.5-91193.29"
switch \initial
- attribute \src "libresoc.v:91368.9-91368.17"
+ attribute \src "libresoc.v:91193.9-91193.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0]
end
- attribute \src "libresoc.v:91386.3-91404.6"
- process $proc$libresoc.v:91386$3877
+ attribute \src "libresoc.v:91211.3-91229.6"
+ process $proc$libresoc.v:91211$3861
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:91387.5-91387.29"
+ attribute \src "libresoc.v:91212.5-91212.29"
switch \initial
- attribute \src "libresoc.v:91387.9-91387.17"
+ attribute \src "libresoc.v:91212.9-91212.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:91405.3-91423.6"
- process $proc$libresoc.v:91405$3878
+ attribute \src "libresoc.v:91230.3-91248.6"
+ process $proc$libresoc.v:91230$3862
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:91406.5-91406.29"
+ attribute \src "libresoc.v:91231.5-91231.29"
switch \initial
- attribute \src "libresoc.v:91406.9-91406.17"
+ attribute \src "libresoc.v:91231.9-91231.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0]
end
- attribute \src "libresoc.v:91424.3-91442.6"
- process $proc$libresoc.v:91424$3879
+ attribute \src "libresoc.v:91249.3-91267.6"
+ process $proc$libresoc.v:91249$3863
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:91425.5-91425.29"
+ attribute \src "libresoc.v:91250.5-91250.29"
switch \initial
- attribute \src "libresoc.v:91425.9-91425.17"
+ attribute \src "libresoc.v:91250.9-91250.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:91443.3-91461.6"
- process $proc$libresoc.v:91443$3880
+ attribute \src "libresoc.v:91268.3-91286.6"
+ process $proc$libresoc.v:91268$3864
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:91444.5-91444.29"
+ attribute \src "libresoc.v:91269.5-91269.29"
switch \initial
- attribute \src "libresoc.v:91444.9-91444.17"
+ attribute \src "libresoc.v:91269.9-91269.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0]
end
- attribute \src "libresoc.v:91462.3-91480.6"
- process $proc$libresoc.v:91462$3881
+ attribute \src "libresoc.v:91287.3-91305.6"
+ process $proc$libresoc.v:91287$3865
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:91463.5-91463.29"
+ attribute \src "libresoc.v:91288.5-91288.29"
switch \initial
- attribute \src "libresoc.v:91463.9-91463.17"
+ attribute \src "libresoc.v:91288.9-91288.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0]
end
- attribute \src "libresoc.v:91481.3-91499.6"
- process $proc$libresoc.v:91481$3882
+ attribute \src "libresoc.v:91306.3-91324.6"
+ process $proc$libresoc.v:91306$3866
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:91482.5-91482.29"
+ attribute \src "libresoc.v:91307.5-91307.29"
switch \initial
- attribute \src "libresoc.v:91482.9-91482.17"
+ attribute \src "libresoc.v:91307.9-91307.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0]
end
- attribute \src "libresoc.v:91500.3-91518.6"
- process $proc$libresoc.v:91500$3883
+ attribute \src "libresoc.v:91325.3-91343.6"
+ process $proc$libresoc.v:91325$3867
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0]
- attribute \src "libresoc.v:91501.5-91501.29"
+ attribute \src "libresoc.v:91326.5-91326.29"
switch \initial
- attribute \src "libresoc.v:91501.9-91501.17"
+ attribute \src "libresoc.v:91326.9-91326.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:91524.1-93095.10"
+attribute \src "libresoc.v:91349.1-92920.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10"
attribute \generator "nMigen"
module \dec31_dec_sub10
- attribute \src "libresoc.v:92872.3-92908.6"
+ attribute \src "libresoc.v:92697.3-92733.6"
wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:92909.3-92945.6"
+ attribute \src "libresoc.v:92734.3-92770.6"
wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:92428.3-92464.6"
+ attribute \src "libresoc.v:92253.3-92289.6"
wire width 8 $0\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:92576.3-92612.6"
+ attribute \src "libresoc.v:92401.3-92437.6"
wire $0\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:91910.3-91946.6"
+ attribute \src "libresoc.v:91735.3-91771.6"
wire width 3 $0\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:91947.3-91983.6"
+ attribute \src "libresoc.v:91772.3-91808.6"
wire width 3 $0\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:92391.3-92427.6"
+ attribute \src "libresoc.v:92216.3-92252.6"
wire width 2 $0\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:92539.3-92575.6"
+ attribute \src "libresoc.v:92364.3-92400.6"
wire $0\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:92687.3-92723.6"
+ attribute \src "libresoc.v:92512.3-92548.6"
wire width 5 $0\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:91873.3-91909.6"
+ attribute \src "libresoc.v:91698.3-91734.6"
wire width 14 $0\dec31_dec_sub10_function_unit[13:0]
- attribute \src "libresoc.v:92946.3-92982.6"
+ attribute \src "libresoc.v:92771.3-92807.6"
wire width 3 $0\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:92983.3-93019.6"
+ attribute \src "libresoc.v:92808.3-92844.6"
wire width 4 $0\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:93020.3-93056.6"
+ attribute \src "libresoc.v:92845.3-92881.6"
wire width 2 $0\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:92280.3-92316.6"
+ attribute \src "libresoc.v:92105.3-92141.6"
wire width 7 $0\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:92465.3-92501.6"
+ attribute \src "libresoc.v:92290.3-92326.6"
wire $0\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:92502.3-92538.6"
+ attribute \src "libresoc.v:92327.3-92363.6"
wire $0\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:92724.3-92760.6"
+ attribute \src "libresoc.v:92549.3-92585.6"
wire $0\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:92243.3-92279.6"
+ attribute \src "libresoc.v:92068.3-92104.6"
wire width 4 $0\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:92798.3-92834.6"
+ attribute \src "libresoc.v:92623.3-92659.6"
wire $0\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:93057.3-93093.6"
+ attribute \src "libresoc.v:92882.3-92918.6"
wire width 3 $0\dec31_dec_sub10_out_sel[2:0]
- attribute \src "libresoc.v:92354.3-92390.6"
+ attribute \src "libresoc.v:92179.3-92215.6"
wire width 2 $0\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:92650.3-92686.6"
+ attribute \src "libresoc.v:92475.3-92511.6"
wire $0\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:92835.3-92871.6"
+ attribute \src "libresoc.v:92660.3-92696.6"
wire $0\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:92761.3-92797.6"
+ attribute \src "libresoc.v:92586.3-92622.6"
wire $0\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:92613.3-92649.6"
+ attribute \src "libresoc.v:92438.3-92474.6"
wire $0\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:92169.3-92205.6"
+ attribute \src "libresoc.v:91994.3-92030.6"
wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:92206.3-92242.6"
+ attribute \src "libresoc.v:92031.3-92067.6"
wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:91984.3-92020.6"
+ attribute \src "libresoc.v:91809.3-91845.6"
wire width 3 $0\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:92021.3-92057.6"
+ attribute \src "libresoc.v:91846.3-91882.6"
wire width 3 $0\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:92058.3-92094.6"
+ attribute \src "libresoc.v:91883.3-91919.6"
wire width 3 $0\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:92132.3-92168.6"
+ attribute \src "libresoc.v:91957.3-91993.6"
wire width 3 $0\dec31_dec_sub10_sv_out2[2:0]
- attribute \src "libresoc.v:92095.3-92131.6"
+ attribute \src "libresoc.v:91920.3-91956.6"
wire width 3 $0\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:92317.3-92353.6"
+ attribute \src "libresoc.v:92142.3-92178.6"
wire width 2 $0\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:91525.7-91525.20"
+ attribute \src "libresoc.v:91350.7-91350.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:92872.3-92908.6"
+ attribute \src "libresoc.v:92697.3-92733.6"
wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:92909.3-92945.6"
+ attribute \src "libresoc.v:92734.3-92770.6"
wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:92428.3-92464.6"
+ attribute \src "libresoc.v:92253.3-92289.6"
wire width 8 $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:92576.3-92612.6"
+ attribute \src "libresoc.v:92401.3-92437.6"
wire $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:91910.3-91946.6"
+ attribute \src "libresoc.v:91735.3-91771.6"
wire width 3 $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:91947.3-91983.6"
+ attribute \src "libresoc.v:91772.3-91808.6"
wire width 3 $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:92391.3-92427.6"
+ attribute \src "libresoc.v:92216.3-92252.6"
wire width 2 $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:92539.3-92575.6"
+ attribute \src "libresoc.v:92364.3-92400.6"
wire $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:92687.3-92723.6"
+ attribute \src "libresoc.v:92512.3-92548.6"
wire width 5 $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:91873.3-91909.6"
+ attribute \src "libresoc.v:91698.3-91734.6"
wire width 14 $1\dec31_dec_sub10_function_unit[13:0]
- attribute \src "libresoc.v:92946.3-92982.6"
+ attribute \src "libresoc.v:92771.3-92807.6"
wire width 3 $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:92983.3-93019.6"
+ attribute \src "libresoc.v:92808.3-92844.6"
wire width 4 $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:93020.3-93056.6"
+ attribute \src "libresoc.v:92845.3-92881.6"
wire width 2 $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:92280.3-92316.6"
+ attribute \src "libresoc.v:92105.3-92141.6"
wire width 7 $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:92465.3-92501.6"
+ attribute \src "libresoc.v:92290.3-92326.6"
wire $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:92502.3-92538.6"
+ attribute \src "libresoc.v:92327.3-92363.6"
wire $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:92724.3-92760.6"
+ attribute \src "libresoc.v:92549.3-92585.6"
wire $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:92243.3-92279.6"
+ attribute \src "libresoc.v:92068.3-92104.6"
wire width 4 $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:92798.3-92834.6"
+ attribute \src "libresoc.v:92623.3-92659.6"
wire $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:93057.3-93093.6"
+ attribute \src "libresoc.v:92882.3-92918.6"
wire width 3 $1\dec31_dec_sub10_out_sel[2:0]
- attribute \src "libresoc.v:92354.3-92390.6"
+ attribute \src "libresoc.v:92179.3-92215.6"
wire width 2 $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:92650.3-92686.6"
+ attribute \src "libresoc.v:92475.3-92511.6"
wire $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:92835.3-92871.6"
+ attribute \src "libresoc.v:92660.3-92696.6"
wire $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:92761.3-92797.6"
+ attribute \src "libresoc.v:92586.3-92622.6"
wire $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:92613.3-92649.6"
+ attribute \src "libresoc.v:92438.3-92474.6"
wire $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:92169.3-92205.6"
+ attribute \src "libresoc.v:91994.3-92030.6"
wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:92206.3-92242.6"
+ attribute \src "libresoc.v:92031.3-92067.6"
wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:91984.3-92020.6"
+ attribute \src "libresoc.v:91809.3-91845.6"
wire width 3 $1\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:92021.3-92057.6"
+ attribute \src "libresoc.v:91846.3-91882.6"
wire width 3 $1\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:92058.3-92094.6"
+ attribute \src "libresoc.v:91883.3-91919.6"
wire width 3 $1\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:92132.3-92168.6"
+ attribute \src "libresoc.v:91957.3-91993.6"
wire width 3 $1\dec31_dec_sub10_sv_out2[2:0]
- attribute \src "libresoc.v:92095.3-92131.6"
+ attribute \src "libresoc.v:91920.3-91956.6"
wire width 3 $1\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:92317.3-92353.6"
+ attribute \src "libresoc.v:92142.3-92178.6"
wire width 2 $1\dec31_dec_sub10_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub10_upd
- attribute \src "libresoc.v:91525.7-91525.15"
+ attribute \src "libresoc.v:91350.7-91350.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:91525.7-91525.20"
- process $proc$libresoc.v:91525$3918
+ attribute \src "libresoc.v:91350.7-91350.20"
+ process $proc$libresoc.v:91350$3902
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:91873.3-91909.6"
- process $proc$libresoc.v:91873$3885
+ attribute \src "libresoc.v:91698.3-91734.6"
+ process $proc$libresoc.v:91698$3869
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0]
- attribute \src "libresoc.v:91874.5-91874.29"
+ attribute \src "libresoc.v:91699.5-91699.29"
switch \initial
- attribute \src "libresoc.v:91874.9-91874.17"
+ attribute \src "libresoc.v:91699.9-91699.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0]
end
- attribute \src "libresoc.v:91910.3-91946.6"
- process $proc$libresoc.v:91910$3886
+ attribute \src "libresoc.v:91735.3-91771.6"
+ process $proc$libresoc.v:91735$3870
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:91911.5-91911.29"
+ attribute \src "libresoc.v:91736.5-91736.29"
switch \initial
- attribute \src "libresoc.v:91911.9-91911.17"
+ attribute \src "libresoc.v:91736.9-91736.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0]
end
- attribute \src "libresoc.v:91947.3-91983.6"
- process $proc$libresoc.v:91947$3887
+ attribute \src "libresoc.v:91772.3-91808.6"
+ process $proc$libresoc.v:91772$3871
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:91948.5-91948.29"
+ attribute \src "libresoc.v:91773.5-91773.29"
switch \initial
- attribute \src "libresoc.v:91948.9-91948.17"
+ attribute \src "libresoc.v:91773.9-91773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0]
end
- attribute \src "libresoc.v:91984.3-92020.6"
- process $proc$libresoc.v:91984$3888
+ attribute \src "libresoc.v:91809.3-91845.6"
+ process $proc$libresoc.v:91809$3872
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:91985.5-91985.29"
+ attribute \src "libresoc.v:91810.5-91810.29"
switch \initial
- attribute \src "libresoc.v:91985.9-91985.17"
+ attribute \src "libresoc.v:91810.9-91810.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0]
end
- attribute \src "libresoc.v:92021.3-92057.6"
- process $proc$libresoc.v:92021$3889
+ attribute \src "libresoc.v:91846.3-91882.6"
+ process $proc$libresoc.v:91846$3873
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:92022.5-92022.29"
+ attribute \src "libresoc.v:91847.5-91847.29"
switch \initial
- attribute \src "libresoc.v:92022.9-92022.17"
+ attribute \src "libresoc.v:91847.9-91847.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0]
end
- attribute \src "libresoc.v:92058.3-92094.6"
- process $proc$libresoc.v:92058$3890
+ attribute \src "libresoc.v:91883.3-91919.6"
+ process $proc$libresoc.v:91883$3874
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:92059.5-92059.29"
+ attribute \src "libresoc.v:91884.5-91884.29"
switch \initial
- attribute \src "libresoc.v:92059.9-92059.17"
+ attribute \src "libresoc.v:91884.9-91884.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0]
end
- attribute \src "libresoc.v:92095.3-92131.6"
- process $proc$libresoc.v:92095$3891
+ attribute \src "libresoc.v:91920.3-91956.6"
+ process $proc$libresoc.v:91920$3875
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:92096.5-92096.29"
+ attribute \src "libresoc.v:91921.5-91921.29"
switch \initial
- attribute \src "libresoc.v:92096.9-92096.17"
+ attribute \src "libresoc.v:91921.9-91921.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0]
end
- attribute \src "libresoc.v:92132.3-92168.6"
- process $proc$libresoc.v:92132$3892
+ attribute \src "libresoc.v:91957.3-91993.6"
+ process $proc$libresoc.v:91957$3876
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0]
- attribute \src "libresoc.v:92133.5-92133.29"
+ attribute \src "libresoc.v:91958.5-91958.29"
switch \initial
- attribute \src "libresoc.v:92133.9-92133.17"
+ attribute \src "libresoc.v:91958.9-91958.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0]
end
- attribute \src "libresoc.v:92169.3-92205.6"
- process $proc$libresoc.v:92169$3893
+ attribute \src "libresoc.v:91994.3-92030.6"
+ process $proc$libresoc.v:91994$3877
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:92170.5-92170.29"
+ attribute \src "libresoc.v:91995.5-91995.29"
switch \initial
- attribute \src "libresoc.v:92170.9-92170.17"
+ attribute \src "libresoc.v:91995.9-91995.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:92206.3-92242.6"
- process $proc$libresoc.v:92206$3894
+ attribute \src "libresoc.v:92031.3-92067.6"
+ process $proc$libresoc.v:92031$3878
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:92207.5-92207.29"
+ attribute \src "libresoc.v:92032.5-92032.29"
switch \initial
- attribute \src "libresoc.v:92207.9-92207.17"
+ attribute \src "libresoc.v:92032.9-92032.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:92243.3-92279.6"
- process $proc$libresoc.v:92243$3895
+ attribute \src "libresoc.v:92068.3-92104.6"
+ process $proc$libresoc.v:92068$3879
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:92244.5-92244.29"
+ attribute \src "libresoc.v:92069.5-92069.29"
switch \initial
- attribute \src "libresoc.v:92244.9-92244.17"
+ attribute \src "libresoc.v:92069.9-92069.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0]
end
- attribute \src "libresoc.v:92280.3-92316.6"
- process $proc$libresoc.v:92280$3896
+ attribute \src "libresoc.v:92105.3-92141.6"
+ process $proc$libresoc.v:92105$3880
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:92281.5-92281.29"
+ attribute \src "libresoc.v:92106.5-92106.29"
switch \initial
- attribute \src "libresoc.v:92281.9-92281.17"
+ attribute \src "libresoc.v:92106.9-92106.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0]
end
- attribute \src "libresoc.v:92317.3-92353.6"
- process $proc$libresoc.v:92317$3897
+ attribute \src "libresoc.v:92142.3-92178.6"
+ process $proc$libresoc.v:92142$3881
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:92318.5-92318.29"
+ attribute \src "libresoc.v:92143.5-92143.29"
switch \initial
- attribute \src "libresoc.v:92318.9-92318.17"
+ attribute \src "libresoc.v:92143.9-92143.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0]
end
- attribute \src "libresoc.v:92354.3-92390.6"
- process $proc$libresoc.v:92354$3898
+ attribute \src "libresoc.v:92179.3-92215.6"
+ process $proc$libresoc.v:92179$3882
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:92355.5-92355.29"
+ attribute \src "libresoc.v:92180.5-92180.29"
switch \initial
- attribute \src "libresoc.v:92355.9-92355.17"
+ attribute \src "libresoc.v:92180.9-92180.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0]
end
- attribute \src "libresoc.v:92391.3-92427.6"
- process $proc$libresoc.v:92391$3899
+ attribute \src "libresoc.v:92216.3-92252.6"
+ process $proc$libresoc.v:92216$3883
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:92392.5-92392.29"
+ attribute \src "libresoc.v:92217.5-92217.29"
switch \initial
- attribute \src "libresoc.v:92392.9-92392.17"
+ attribute \src "libresoc.v:92217.9-92217.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0]
end
- attribute \src "libresoc.v:92428.3-92464.6"
- process $proc$libresoc.v:92428$3900
+ attribute \src "libresoc.v:92253.3-92289.6"
+ process $proc$libresoc.v:92253$3884
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:92429.5-92429.29"
+ attribute \src "libresoc.v:92254.5-92254.29"
switch \initial
- attribute \src "libresoc.v:92429.9-92429.17"
+ attribute \src "libresoc.v:92254.9-92254.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0]
end
- attribute \src "libresoc.v:92465.3-92501.6"
- process $proc$libresoc.v:92465$3901
+ attribute \src "libresoc.v:92290.3-92326.6"
+ process $proc$libresoc.v:92290$3885
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:92466.5-92466.29"
+ attribute \src "libresoc.v:92291.5-92291.29"
switch \initial
- attribute \src "libresoc.v:92466.9-92466.17"
+ attribute \src "libresoc.v:92291.9-92291.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0]
end
- attribute \src "libresoc.v:92502.3-92538.6"
- process $proc$libresoc.v:92502$3902
+ attribute \src "libresoc.v:92327.3-92363.6"
+ process $proc$libresoc.v:92327$3886
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:92503.5-92503.29"
+ attribute \src "libresoc.v:92328.5-92328.29"
switch \initial
- attribute \src "libresoc.v:92503.9-92503.17"
+ attribute \src "libresoc.v:92328.9-92328.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0]
end
- attribute \src "libresoc.v:92539.3-92575.6"
- process $proc$libresoc.v:92539$3903
+ attribute \src "libresoc.v:92364.3-92400.6"
+ process $proc$libresoc.v:92364$3887
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:92540.5-92540.29"
+ attribute \src "libresoc.v:92365.5-92365.29"
switch \initial
- attribute \src "libresoc.v:92540.9-92540.17"
+ attribute \src "libresoc.v:92365.9-92365.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0]
end
- attribute \src "libresoc.v:92576.3-92612.6"
- process $proc$libresoc.v:92576$3904
+ attribute \src "libresoc.v:92401.3-92437.6"
+ process $proc$libresoc.v:92401$3888
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:92577.5-92577.29"
+ attribute \src "libresoc.v:92402.5-92402.29"
switch \initial
- attribute \src "libresoc.v:92577.9-92577.17"
+ attribute \src "libresoc.v:92402.9-92402.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0]
end
- attribute \src "libresoc.v:92613.3-92649.6"
- process $proc$libresoc.v:92613$3905
+ attribute \src "libresoc.v:92438.3-92474.6"
+ process $proc$libresoc.v:92438$3889
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:92614.5-92614.29"
+ attribute \src "libresoc.v:92439.5-92439.29"
switch \initial
- attribute \src "libresoc.v:92614.9-92614.17"
+ attribute \src "libresoc.v:92439.9-92439.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0]
end
- attribute \src "libresoc.v:92650.3-92686.6"
- process $proc$libresoc.v:92650$3906
+ attribute \src "libresoc.v:92475.3-92511.6"
+ process $proc$libresoc.v:92475$3890
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:92651.5-92651.29"
+ attribute \src "libresoc.v:92476.5-92476.29"
switch \initial
- attribute \src "libresoc.v:92651.9-92651.17"
+ attribute \src "libresoc.v:92476.9-92476.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0]
end
- attribute \src "libresoc.v:92687.3-92723.6"
- process $proc$libresoc.v:92687$3907
+ attribute \src "libresoc.v:92512.3-92548.6"
+ process $proc$libresoc.v:92512$3891
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:92688.5-92688.29"
+ attribute \src "libresoc.v:92513.5-92513.29"
switch \initial
- attribute \src "libresoc.v:92688.9-92688.17"
+ attribute \src "libresoc.v:92513.9-92513.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0]
end
- attribute \src "libresoc.v:92724.3-92760.6"
- process $proc$libresoc.v:92724$3908
+ attribute \src "libresoc.v:92549.3-92585.6"
+ process $proc$libresoc.v:92549$3892
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:92725.5-92725.29"
+ attribute \src "libresoc.v:92550.5-92550.29"
switch \initial
- attribute \src "libresoc.v:92725.9-92725.17"
+ attribute \src "libresoc.v:92550.9-92550.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0]
end
- attribute \src "libresoc.v:92761.3-92797.6"
- process $proc$libresoc.v:92761$3909
+ attribute \src "libresoc.v:92586.3-92622.6"
+ process $proc$libresoc.v:92586$3893
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:92762.5-92762.29"
+ attribute \src "libresoc.v:92587.5-92587.29"
switch \initial
- attribute \src "libresoc.v:92762.9-92762.17"
+ attribute \src "libresoc.v:92587.9-92587.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0]
end
- attribute \src "libresoc.v:92798.3-92834.6"
- process $proc$libresoc.v:92798$3910
+ attribute \src "libresoc.v:92623.3-92659.6"
+ process $proc$libresoc.v:92623$3894
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:92799.5-92799.29"
+ attribute \src "libresoc.v:92624.5-92624.29"
switch \initial
- attribute \src "libresoc.v:92799.9-92799.17"
+ attribute \src "libresoc.v:92624.9-92624.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0]
end
- attribute \src "libresoc.v:92835.3-92871.6"
- process $proc$libresoc.v:92835$3911
+ attribute \src "libresoc.v:92660.3-92696.6"
+ process $proc$libresoc.v:92660$3895
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:92836.5-92836.29"
+ attribute \src "libresoc.v:92661.5-92661.29"
switch \initial
- attribute \src "libresoc.v:92836.9-92836.17"
+ attribute \src "libresoc.v:92661.9-92661.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:92872.3-92908.6"
- process $proc$libresoc.v:92872$3912
+ attribute \src "libresoc.v:92697.3-92733.6"
+ process $proc$libresoc.v:92697$3896
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:92873.5-92873.29"
+ attribute \src "libresoc.v:92698.5-92698.29"
switch \initial
- attribute \src "libresoc.v:92873.9-92873.17"
+ attribute \src "libresoc.v:92698.9-92698.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0]
end
- attribute \src "libresoc.v:92909.3-92945.6"
- process $proc$libresoc.v:92909$3913
+ attribute \src "libresoc.v:92734.3-92770.6"
+ process $proc$libresoc.v:92734$3897
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:92910.5-92910.29"
+ attribute \src "libresoc.v:92735.5-92735.29"
switch \initial
- attribute \src "libresoc.v:92910.9-92910.17"
+ attribute \src "libresoc.v:92735.9-92735.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:92946.3-92982.6"
- process $proc$libresoc.v:92946$3914
+ attribute \src "libresoc.v:92771.3-92807.6"
+ process $proc$libresoc.v:92771$3898
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:92947.5-92947.29"
+ attribute \src "libresoc.v:92772.5-92772.29"
switch \initial
- attribute \src "libresoc.v:92947.9-92947.17"
+ attribute \src "libresoc.v:92772.9-92772.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0]
end
- attribute \src "libresoc.v:92983.3-93019.6"
- process $proc$libresoc.v:92983$3915
+ attribute \src "libresoc.v:92808.3-92844.6"
+ process $proc$libresoc.v:92808$3899
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:92984.5-92984.29"
+ attribute \src "libresoc.v:92809.5-92809.29"
switch \initial
- attribute \src "libresoc.v:92984.9-92984.17"
+ attribute \src "libresoc.v:92809.9-92809.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0]
end
- attribute \src "libresoc.v:93020.3-93056.6"
- process $proc$libresoc.v:93020$3916
+ attribute \src "libresoc.v:92845.3-92881.6"
+ process $proc$libresoc.v:92845$3900
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:93021.5-93021.29"
+ attribute \src "libresoc.v:92846.5-92846.29"
switch \initial
- attribute \src "libresoc.v:93021.9-93021.17"
+ attribute \src "libresoc.v:92846.9-92846.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0]
end
- attribute \src "libresoc.v:93057.3-93093.6"
- process $proc$libresoc.v:93057$3917
+ attribute \src "libresoc.v:92882.3-92918.6"
+ process $proc$libresoc.v:92882$3901
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0]
- attribute \src "libresoc.v:93058.5-93058.29"
+ attribute \src "libresoc.v:92883.5-92883.29"
switch \initial
- attribute \src "libresoc.v:93058.9-93058.17"
+ attribute \src "libresoc.v:92883.9-92883.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:93099.1-95264.10"
+attribute \src "libresoc.v:92924.1-95089.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11"
attribute \generator "nMigen"
module \dec31_dec_sub11
- attribute \src "libresoc.v:94933.3-94987.6"
+ attribute \src "libresoc.v:94758.3-94812.6"
wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:94988.3-95042.6"
+ attribute \src "libresoc.v:94813.3-94867.6"
wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:94273.3-94327.6"
+ attribute \src "libresoc.v:94098.3-94152.6"
wire width 8 $0\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:94493.3-94547.6"
+ attribute \src "libresoc.v:94318.3-94372.6"
wire $0\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:93503.3-93557.6"
+ attribute \src "libresoc.v:93328.3-93382.6"
wire width 3 $0\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:93558.3-93612.6"
+ attribute \src "libresoc.v:93383.3-93437.6"
wire width 3 $0\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:94218.3-94272.6"
+ attribute \src "libresoc.v:94043.3-94097.6"
wire width 2 $0\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:94438.3-94492.6"
+ attribute \src "libresoc.v:94263.3-94317.6"
wire $0\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:94658.3-94712.6"
+ attribute \src "libresoc.v:94483.3-94537.6"
wire width 5 $0\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:93448.3-93502.6"
+ attribute \src "libresoc.v:93273.3-93327.6"
wire width 14 $0\dec31_dec_sub11_function_unit[13:0]
- attribute \src "libresoc.v:95043.3-95097.6"
+ attribute \src "libresoc.v:94868.3-94922.6"
wire width 3 $0\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:95098.3-95152.6"
+ attribute \src "libresoc.v:94923.3-94977.6"
wire width 4 $0\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:95153.3-95207.6"
+ attribute \src "libresoc.v:94978.3-95032.6"
wire width 2 $0\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:94053.3-94107.6"
+ attribute \src "libresoc.v:93878.3-93932.6"
wire width 7 $0\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:94328.3-94382.6"
+ attribute \src "libresoc.v:94153.3-94207.6"
wire $0\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:94383.3-94437.6"
+ attribute \src "libresoc.v:94208.3-94262.6"
wire $0\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:94713.3-94767.6"
+ attribute \src "libresoc.v:94538.3-94592.6"
wire $0\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:93998.3-94052.6"
+ attribute \src "libresoc.v:93823.3-93877.6"
wire width 4 $0\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:94823.3-94877.6"
+ attribute \src "libresoc.v:94648.3-94702.6"
wire $0\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:95208.3-95262.6"
+ attribute \src "libresoc.v:95033.3-95087.6"
wire width 3 $0\dec31_dec_sub11_out_sel[2:0]
- attribute \src "libresoc.v:94163.3-94217.6"
+ attribute \src "libresoc.v:93988.3-94042.6"
wire width 2 $0\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:94603.3-94657.6"
+ attribute \src "libresoc.v:94428.3-94482.6"
wire $0\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:94878.3-94932.6"
+ attribute \src "libresoc.v:94703.3-94757.6"
wire $0\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:94768.3-94822.6"
+ attribute \src "libresoc.v:94593.3-94647.6"
wire $0\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:94548.3-94602.6"
+ attribute \src "libresoc.v:94373.3-94427.6"
wire $0\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:93888.3-93942.6"
+ attribute \src "libresoc.v:93713.3-93767.6"
wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:93943.3-93997.6"
+ attribute \src "libresoc.v:93768.3-93822.6"
wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:93613.3-93667.6"
+ attribute \src "libresoc.v:93438.3-93492.6"
wire width 3 $0\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:93668.3-93722.6"
+ attribute \src "libresoc.v:93493.3-93547.6"
wire width 3 $0\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:93723.3-93777.6"
+ attribute \src "libresoc.v:93548.3-93602.6"
wire width 3 $0\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:93833.3-93887.6"
+ attribute \src "libresoc.v:93658.3-93712.6"
wire width 3 $0\dec31_dec_sub11_sv_out2[2:0]
- attribute \src "libresoc.v:93778.3-93832.6"
+ attribute \src "libresoc.v:93603.3-93657.6"
wire width 3 $0\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:94108.3-94162.6"
+ attribute \src "libresoc.v:93933.3-93987.6"
wire width 2 $0\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:93100.7-93100.20"
+ attribute \src "libresoc.v:92925.7-92925.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:94933.3-94987.6"
+ attribute \src "libresoc.v:94758.3-94812.6"
wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:94988.3-95042.6"
+ attribute \src "libresoc.v:94813.3-94867.6"
wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:94273.3-94327.6"
+ attribute \src "libresoc.v:94098.3-94152.6"
wire width 8 $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:94493.3-94547.6"
+ attribute \src "libresoc.v:94318.3-94372.6"
wire $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:93503.3-93557.6"
+ attribute \src "libresoc.v:93328.3-93382.6"
wire width 3 $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:93558.3-93612.6"
+ attribute \src "libresoc.v:93383.3-93437.6"
wire width 3 $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:94218.3-94272.6"
+ attribute \src "libresoc.v:94043.3-94097.6"
wire width 2 $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:94438.3-94492.6"
+ attribute \src "libresoc.v:94263.3-94317.6"
wire $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:94658.3-94712.6"
+ attribute \src "libresoc.v:94483.3-94537.6"
wire width 5 $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:93448.3-93502.6"
+ attribute \src "libresoc.v:93273.3-93327.6"
wire width 14 $1\dec31_dec_sub11_function_unit[13:0]
- attribute \src "libresoc.v:95043.3-95097.6"
+ attribute \src "libresoc.v:94868.3-94922.6"
wire width 3 $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:95098.3-95152.6"
+ attribute \src "libresoc.v:94923.3-94977.6"
wire width 4 $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:95153.3-95207.6"
+ attribute \src "libresoc.v:94978.3-95032.6"
wire width 2 $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:94053.3-94107.6"
+ attribute \src "libresoc.v:93878.3-93932.6"
wire width 7 $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:94328.3-94382.6"
+ attribute \src "libresoc.v:94153.3-94207.6"
wire $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:94383.3-94437.6"
+ attribute \src "libresoc.v:94208.3-94262.6"
wire $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:94713.3-94767.6"
+ attribute \src "libresoc.v:94538.3-94592.6"
wire $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:93998.3-94052.6"
+ attribute \src "libresoc.v:93823.3-93877.6"
wire width 4 $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:94823.3-94877.6"
+ attribute \src "libresoc.v:94648.3-94702.6"
wire $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:95208.3-95262.6"
+ attribute \src "libresoc.v:95033.3-95087.6"
wire width 3 $1\dec31_dec_sub11_out_sel[2:0]
- attribute \src "libresoc.v:94163.3-94217.6"
+ attribute \src "libresoc.v:93988.3-94042.6"
wire width 2 $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:94603.3-94657.6"
+ attribute \src "libresoc.v:94428.3-94482.6"
wire $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:94878.3-94932.6"
+ attribute \src "libresoc.v:94703.3-94757.6"
wire $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:94768.3-94822.6"
+ attribute \src "libresoc.v:94593.3-94647.6"
wire $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:94548.3-94602.6"
+ attribute \src "libresoc.v:94373.3-94427.6"
wire $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:93888.3-93942.6"
+ attribute \src "libresoc.v:93713.3-93767.6"
wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:93943.3-93997.6"
+ attribute \src "libresoc.v:93768.3-93822.6"
wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:93613.3-93667.6"
+ attribute \src "libresoc.v:93438.3-93492.6"
wire width 3 $1\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:93668.3-93722.6"
+ attribute \src "libresoc.v:93493.3-93547.6"
wire width 3 $1\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:93723.3-93777.6"
+ attribute \src "libresoc.v:93548.3-93602.6"
wire width 3 $1\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:93833.3-93887.6"
+ attribute \src "libresoc.v:93658.3-93712.6"
wire width 3 $1\dec31_dec_sub11_sv_out2[2:0]
- attribute \src "libresoc.v:93778.3-93832.6"
+ attribute \src "libresoc.v:93603.3-93657.6"
wire width 3 $1\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:94108.3-94162.6"
+ attribute \src "libresoc.v:93933.3-93987.6"
wire width 2 $1\dec31_dec_sub11_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub11_upd
- attribute \src "libresoc.v:93100.7-93100.15"
+ attribute \src "libresoc.v:92925.7-92925.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:93100.7-93100.20"
- process $proc$libresoc.v:93100$3952
+ attribute \src "libresoc.v:92925.7-92925.20"
+ process $proc$libresoc.v:92925$3936
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:93448.3-93502.6"
- process $proc$libresoc.v:93448$3919
+ attribute \src "libresoc.v:93273.3-93327.6"
+ process $proc$libresoc.v:93273$3903
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0]
- attribute \src "libresoc.v:93449.5-93449.29"
+ attribute \src "libresoc.v:93274.5-93274.29"
switch \initial
- attribute \src "libresoc.v:93449.9-93449.17"
+ attribute \src "libresoc.v:93274.9-93274.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0]
end
- attribute \src "libresoc.v:93503.3-93557.6"
- process $proc$libresoc.v:93503$3920
+ attribute \src "libresoc.v:93328.3-93382.6"
+ process $proc$libresoc.v:93328$3904
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:93504.5-93504.29"
+ attribute \src "libresoc.v:93329.5-93329.29"
switch \initial
- attribute \src "libresoc.v:93504.9-93504.17"
+ attribute \src "libresoc.v:93329.9-93329.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0]
end
- attribute \src "libresoc.v:93558.3-93612.6"
- process $proc$libresoc.v:93558$3921
+ attribute \src "libresoc.v:93383.3-93437.6"
+ process $proc$libresoc.v:93383$3905
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:93559.5-93559.29"
+ attribute \src "libresoc.v:93384.5-93384.29"
switch \initial
- attribute \src "libresoc.v:93559.9-93559.17"
+ attribute \src "libresoc.v:93384.9-93384.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0]
end
- attribute \src "libresoc.v:93613.3-93667.6"
- process $proc$libresoc.v:93613$3922
+ attribute \src "libresoc.v:93438.3-93492.6"
+ process $proc$libresoc.v:93438$3906
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:93614.5-93614.29"
+ attribute \src "libresoc.v:93439.5-93439.29"
switch \initial
- attribute \src "libresoc.v:93614.9-93614.17"
+ attribute \src "libresoc.v:93439.9-93439.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0]
end
- attribute \src "libresoc.v:93668.3-93722.6"
- process $proc$libresoc.v:93668$3923
+ attribute \src "libresoc.v:93493.3-93547.6"
+ process $proc$libresoc.v:93493$3907
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:93669.5-93669.29"
+ attribute \src "libresoc.v:93494.5-93494.29"
switch \initial
- attribute \src "libresoc.v:93669.9-93669.17"
+ attribute \src "libresoc.v:93494.9-93494.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0]
end
- attribute \src "libresoc.v:93723.3-93777.6"
- process $proc$libresoc.v:93723$3924
+ attribute \src "libresoc.v:93548.3-93602.6"
+ process $proc$libresoc.v:93548$3908
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:93724.5-93724.29"
+ attribute \src "libresoc.v:93549.5-93549.29"
switch \initial
- attribute \src "libresoc.v:93724.9-93724.17"
+ attribute \src "libresoc.v:93549.9-93549.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0]
end
- attribute \src "libresoc.v:93778.3-93832.6"
- process $proc$libresoc.v:93778$3925
+ attribute \src "libresoc.v:93603.3-93657.6"
+ process $proc$libresoc.v:93603$3909
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:93779.5-93779.29"
+ attribute \src "libresoc.v:93604.5-93604.29"
switch \initial
- attribute \src "libresoc.v:93779.9-93779.17"
+ attribute \src "libresoc.v:93604.9-93604.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0]
end
- attribute \src "libresoc.v:93833.3-93887.6"
- process $proc$libresoc.v:93833$3926
+ attribute \src "libresoc.v:93658.3-93712.6"
+ process $proc$libresoc.v:93658$3910
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0]
- attribute \src "libresoc.v:93834.5-93834.29"
+ attribute \src "libresoc.v:93659.5-93659.29"
switch \initial
- attribute \src "libresoc.v:93834.9-93834.17"
+ attribute \src "libresoc.v:93659.9-93659.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0]
end
- attribute \src "libresoc.v:93888.3-93942.6"
- process $proc$libresoc.v:93888$3927
+ attribute \src "libresoc.v:93713.3-93767.6"
+ process $proc$libresoc.v:93713$3911
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:93889.5-93889.29"
+ attribute \src "libresoc.v:93714.5-93714.29"
switch \initial
- attribute \src "libresoc.v:93889.9-93889.17"
+ attribute \src "libresoc.v:93714.9-93714.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:93943.3-93997.6"
- process $proc$libresoc.v:93943$3928
+ attribute \src "libresoc.v:93768.3-93822.6"
+ process $proc$libresoc.v:93768$3912
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:93944.5-93944.29"
+ attribute \src "libresoc.v:93769.5-93769.29"
switch \initial
- attribute \src "libresoc.v:93944.9-93944.17"
+ attribute \src "libresoc.v:93769.9-93769.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:93998.3-94052.6"
- process $proc$libresoc.v:93998$3929
+ attribute \src "libresoc.v:93823.3-93877.6"
+ process $proc$libresoc.v:93823$3913
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:93999.5-93999.29"
+ attribute \src "libresoc.v:93824.5-93824.29"
switch \initial
- attribute \src "libresoc.v:93999.9-93999.17"
+ attribute \src "libresoc.v:93824.9-93824.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0]
end
- attribute \src "libresoc.v:94053.3-94107.6"
- process $proc$libresoc.v:94053$3930
+ attribute \src "libresoc.v:93878.3-93932.6"
+ process $proc$libresoc.v:93878$3914
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:94054.5-94054.29"
+ attribute \src "libresoc.v:93879.5-93879.29"
switch \initial
- attribute \src "libresoc.v:94054.9-94054.17"
+ attribute \src "libresoc.v:93879.9-93879.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0]
end
- attribute \src "libresoc.v:94108.3-94162.6"
- process $proc$libresoc.v:94108$3931
+ attribute \src "libresoc.v:93933.3-93987.6"
+ process $proc$libresoc.v:93933$3915
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:94109.5-94109.29"
+ attribute \src "libresoc.v:93934.5-93934.29"
switch \initial
- attribute \src "libresoc.v:94109.9-94109.17"
+ attribute \src "libresoc.v:93934.9-93934.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0]
end
- attribute \src "libresoc.v:94163.3-94217.6"
- process $proc$libresoc.v:94163$3932
+ attribute \src "libresoc.v:93988.3-94042.6"
+ process $proc$libresoc.v:93988$3916
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:94164.5-94164.29"
+ attribute \src "libresoc.v:93989.5-93989.29"
switch \initial
- attribute \src "libresoc.v:94164.9-94164.17"
+ attribute \src "libresoc.v:93989.9-93989.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0]
end
- attribute \src "libresoc.v:94218.3-94272.6"
- process $proc$libresoc.v:94218$3933
+ attribute \src "libresoc.v:94043.3-94097.6"
+ process $proc$libresoc.v:94043$3917
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:94219.5-94219.29"
+ attribute \src "libresoc.v:94044.5-94044.29"
switch \initial
- attribute \src "libresoc.v:94219.9-94219.17"
+ attribute \src "libresoc.v:94044.9-94044.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0]
end
- attribute \src "libresoc.v:94273.3-94327.6"
- process $proc$libresoc.v:94273$3934
+ attribute \src "libresoc.v:94098.3-94152.6"
+ process $proc$libresoc.v:94098$3918
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:94274.5-94274.29"
+ attribute \src "libresoc.v:94099.5-94099.29"
switch \initial
- attribute \src "libresoc.v:94274.9-94274.17"
+ attribute \src "libresoc.v:94099.9-94099.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0]
end
- attribute \src "libresoc.v:94328.3-94382.6"
- process $proc$libresoc.v:94328$3935
+ attribute \src "libresoc.v:94153.3-94207.6"
+ process $proc$libresoc.v:94153$3919
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:94329.5-94329.29"
+ attribute \src "libresoc.v:94154.5-94154.29"
switch \initial
- attribute \src "libresoc.v:94329.9-94329.17"
+ attribute \src "libresoc.v:94154.9-94154.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0]
end
- attribute \src "libresoc.v:94383.3-94437.6"
- process $proc$libresoc.v:94383$3936
+ attribute \src "libresoc.v:94208.3-94262.6"
+ process $proc$libresoc.v:94208$3920
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:94384.5-94384.29"
+ attribute \src "libresoc.v:94209.5-94209.29"
switch \initial
- attribute \src "libresoc.v:94384.9-94384.17"
+ attribute \src "libresoc.v:94209.9-94209.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0]
end
- attribute \src "libresoc.v:94438.3-94492.6"
- process $proc$libresoc.v:94438$3937
+ attribute \src "libresoc.v:94263.3-94317.6"
+ process $proc$libresoc.v:94263$3921
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:94439.5-94439.29"
+ attribute \src "libresoc.v:94264.5-94264.29"
switch \initial
- attribute \src "libresoc.v:94439.9-94439.17"
+ attribute \src "libresoc.v:94264.9-94264.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0]
end
- attribute \src "libresoc.v:94493.3-94547.6"
- process $proc$libresoc.v:94493$3938
+ attribute \src "libresoc.v:94318.3-94372.6"
+ process $proc$libresoc.v:94318$3922
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:94494.5-94494.29"
+ attribute \src "libresoc.v:94319.5-94319.29"
switch \initial
- attribute \src "libresoc.v:94494.9-94494.17"
+ attribute \src "libresoc.v:94319.9-94319.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0]
end
- attribute \src "libresoc.v:94548.3-94602.6"
- process $proc$libresoc.v:94548$3939
+ attribute \src "libresoc.v:94373.3-94427.6"
+ process $proc$libresoc.v:94373$3923
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:94549.5-94549.29"
+ attribute \src "libresoc.v:94374.5-94374.29"
switch \initial
- attribute \src "libresoc.v:94549.9-94549.17"
+ attribute \src "libresoc.v:94374.9-94374.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0]
end
- attribute \src "libresoc.v:94603.3-94657.6"
- process $proc$libresoc.v:94603$3940
+ attribute \src "libresoc.v:94428.3-94482.6"
+ process $proc$libresoc.v:94428$3924
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:94604.5-94604.29"
+ attribute \src "libresoc.v:94429.5-94429.29"
switch \initial
- attribute \src "libresoc.v:94604.9-94604.17"
+ attribute \src "libresoc.v:94429.9-94429.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0]
end
- attribute \src "libresoc.v:94658.3-94712.6"
- process $proc$libresoc.v:94658$3941
+ attribute \src "libresoc.v:94483.3-94537.6"
+ process $proc$libresoc.v:94483$3925
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:94659.5-94659.29"
+ attribute \src "libresoc.v:94484.5-94484.29"
switch \initial
- attribute \src "libresoc.v:94659.9-94659.17"
+ attribute \src "libresoc.v:94484.9-94484.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0]
end
- attribute \src "libresoc.v:94713.3-94767.6"
- process $proc$libresoc.v:94713$3942
+ attribute \src "libresoc.v:94538.3-94592.6"
+ process $proc$libresoc.v:94538$3926
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:94714.5-94714.29"
+ attribute \src "libresoc.v:94539.5-94539.29"
switch \initial
- attribute \src "libresoc.v:94714.9-94714.17"
+ attribute \src "libresoc.v:94539.9-94539.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0]
end
- attribute \src "libresoc.v:94768.3-94822.6"
- process $proc$libresoc.v:94768$3943
+ attribute \src "libresoc.v:94593.3-94647.6"
+ process $proc$libresoc.v:94593$3927
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:94769.5-94769.29"
+ attribute \src "libresoc.v:94594.5-94594.29"
switch \initial
- attribute \src "libresoc.v:94769.9-94769.17"
+ attribute \src "libresoc.v:94594.9-94594.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0]
end
- attribute \src "libresoc.v:94823.3-94877.6"
- process $proc$libresoc.v:94823$3944
+ attribute \src "libresoc.v:94648.3-94702.6"
+ process $proc$libresoc.v:94648$3928
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:94824.5-94824.29"
+ attribute \src "libresoc.v:94649.5-94649.29"
switch \initial
- attribute \src "libresoc.v:94824.9-94824.17"
+ attribute \src "libresoc.v:94649.9-94649.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0]
end
- attribute \src "libresoc.v:94878.3-94932.6"
- process $proc$libresoc.v:94878$3945
+ attribute \src "libresoc.v:94703.3-94757.6"
+ process $proc$libresoc.v:94703$3929
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:94879.5-94879.29"
+ attribute \src "libresoc.v:94704.5-94704.29"
switch \initial
- attribute \src "libresoc.v:94879.9-94879.17"
+ attribute \src "libresoc.v:94704.9-94704.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:94933.3-94987.6"
- process $proc$libresoc.v:94933$3946
+ attribute \src "libresoc.v:94758.3-94812.6"
+ process $proc$libresoc.v:94758$3930
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:94934.5-94934.29"
+ attribute \src "libresoc.v:94759.5-94759.29"
switch \initial
- attribute \src "libresoc.v:94934.9-94934.17"
+ attribute \src "libresoc.v:94759.9-94759.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0]
end
- attribute \src "libresoc.v:94988.3-95042.6"
- process $proc$libresoc.v:94988$3947
+ attribute \src "libresoc.v:94813.3-94867.6"
+ process $proc$libresoc.v:94813$3931
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:94989.5-94989.29"
+ attribute \src "libresoc.v:94814.5-94814.29"
switch \initial
- attribute \src "libresoc.v:94989.9-94989.17"
+ attribute \src "libresoc.v:94814.9-94814.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:95043.3-95097.6"
- process $proc$libresoc.v:95043$3948
+ attribute \src "libresoc.v:94868.3-94922.6"
+ process $proc$libresoc.v:94868$3932
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:95044.5-95044.29"
+ attribute \src "libresoc.v:94869.5-94869.29"
switch \initial
- attribute \src "libresoc.v:95044.9-95044.17"
+ attribute \src "libresoc.v:94869.9-94869.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0]
end
- attribute \src "libresoc.v:95098.3-95152.6"
- process $proc$libresoc.v:95098$3949
+ attribute \src "libresoc.v:94923.3-94977.6"
+ process $proc$libresoc.v:94923$3933
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:95099.5-95099.29"
+ attribute \src "libresoc.v:94924.5-94924.29"
switch \initial
- attribute \src "libresoc.v:95099.9-95099.17"
+ attribute \src "libresoc.v:94924.9-94924.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0]
end
- attribute \src "libresoc.v:95153.3-95207.6"
- process $proc$libresoc.v:95153$3950
+ attribute \src "libresoc.v:94978.3-95032.6"
+ process $proc$libresoc.v:94978$3934
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:95154.5-95154.29"
+ attribute \src "libresoc.v:94979.5-94979.29"
switch \initial
- attribute \src "libresoc.v:95154.9-95154.17"
+ attribute \src "libresoc.v:94979.9-94979.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0]
end
- attribute \src "libresoc.v:95208.3-95262.6"
- process $proc$libresoc.v:95208$3951
+ attribute \src "libresoc.v:95033.3-95087.6"
+ process $proc$libresoc.v:95033$3935
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0]
- attribute \src "libresoc.v:95209.5-95209.29"
+ attribute \src "libresoc.v:95034.5-95034.29"
switch \initial
- attribute \src "libresoc.v:95209.9-95209.17"
+ attribute \src "libresoc.v:95034.9-95034.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:95268.1-99017.10"
+attribute \src "libresoc.v:95093.1-98842.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15"
attribute \generator "nMigen"
module \dec31_dec_sub15
- attribute \src "libresoc.v:98398.3-98500.6"
+ attribute \src "libresoc.v:98223.3-98325.6"
wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:98501.3-98603.6"
+ attribute \src "libresoc.v:98326.3-98428.6"
wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:97162.3-97264.6"
+ attribute \src "libresoc.v:96987.3-97089.6"
wire width 8 $0\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:97574.3-97676.6"
+ attribute \src "libresoc.v:97399.3-97501.6"
wire $0\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:95720.3-95822.6"
+ attribute \src "libresoc.v:95545.3-95647.6"
wire width 3 $0\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:95823.3-95925.6"
+ attribute \src "libresoc.v:95648.3-95750.6"
wire width 3 $0\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:97059.3-97161.6"
+ attribute \src "libresoc.v:96884.3-96986.6"
wire width 2 $0\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:97471.3-97573.6"
+ attribute \src "libresoc.v:97296.3-97398.6"
wire $0\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:97883.3-97985.6"
+ attribute \src "libresoc.v:97708.3-97810.6"
wire width 5 $0\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:95617.3-95719.6"
+ attribute \src "libresoc.v:95442.3-95544.6"
wire width 14 $0\dec31_dec_sub15_function_unit[13:0]
- attribute \src "libresoc.v:98604.3-98706.6"
+ attribute \src "libresoc.v:98429.3-98531.6"
wire width 3 $0\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:98707.3-98809.6"
+ attribute \src "libresoc.v:98532.3-98634.6"
wire width 4 $0\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:98810.3-98912.6"
+ attribute \src "libresoc.v:98635.3-98737.6"
wire width 2 $0\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:96750.3-96852.6"
+ attribute \src "libresoc.v:96575.3-96677.6"
wire width 7 $0\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:97265.3-97367.6"
+ attribute \src "libresoc.v:97090.3-97192.6"
wire $0\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:97368.3-97470.6"
+ attribute \src "libresoc.v:97193.3-97295.6"
wire $0\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:97986.3-98088.6"
+ attribute \src "libresoc.v:97811.3-97913.6"
wire $0\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:96647.3-96749.6"
+ attribute \src "libresoc.v:96472.3-96574.6"
wire width 4 $0\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:98192.3-98294.6"
+ attribute \src "libresoc.v:98017.3-98119.6"
wire $0\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:98913.3-99015.6"
+ attribute \src "libresoc.v:98738.3-98840.6"
wire width 3 $0\dec31_dec_sub15_out_sel[2:0]
- attribute \src "libresoc.v:96956.3-97058.6"
+ attribute \src "libresoc.v:96781.3-96883.6"
wire width 2 $0\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:97780.3-97882.6"
+ attribute \src "libresoc.v:97605.3-97707.6"
wire $0\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:98295.3-98397.6"
+ attribute \src "libresoc.v:98120.3-98222.6"
wire $0\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:98089.3-98191.6"
+ attribute \src "libresoc.v:97914.3-98016.6"
wire $0\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:97677.3-97779.6"
+ attribute \src "libresoc.v:97502.3-97604.6"
wire $0\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:96441.3-96543.6"
+ attribute \src "libresoc.v:96266.3-96368.6"
wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:96544.3-96646.6"
+ attribute \src "libresoc.v:96369.3-96471.6"
wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:95926.3-96028.6"
+ attribute \src "libresoc.v:95751.3-95853.6"
wire width 3 $0\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:96029.3-96131.6"
+ attribute \src "libresoc.v:95854.3-95956.6"
wire width 3 $0\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:96132.3-96234.6"
+ attribute \src "libresoc.v:95957.3-96059.6"
wire width 3 $0\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:96338.3-96440.6"
+ attribute \src "libresoc.v:96163.3-96265.6"
wire width 3 $0\dec31_dec_sub15_sv_out2[2:0]
- attribute \src "libresoc.v:96235.3-96337.6"
+ attribute \src "libresoc.v:96060.3-96162.6"
wire width 3 $0\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:96853.3-96955.6"
+ attribute \src "libresoc.v:96678.3-96780.6"
wire width 2 $0\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:95269.7-95269.20"
+ attribute \src "libresoc.v:95094.7-95094.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:98398.3-98500.6"
+ attribute \src "libresoc.v:98223.3-98325.6"
wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:98501.3-98603.6"
+ attribute \src "libresoc.v:98326.3-98428.6"
wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:97162.3-97264.6"
+ attribute \src "libresoc.v:96987.3-97089.6"
wire width 8 $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:97574.3-97676.6"
+ attribute \src "libresoc.v:97399.3-97501.6"
wire $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:95720.3-95822.6"
+ attribute \src "libresoc.v:95545.3-95647.6"
wire width 3 $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:95823.3-95925.6"
+ attribute \src "libresoc.v:95648.3-95750.6"
wire width 3 $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:97059.3-97161.6"
+ attribute \src "libresoc.v:96884.3-96986.6"
wire width 2 $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:97471.3-97573.6"
+ attribute \src "libresoc.v:97296.3-97398.6"
wire $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:97883.3-97985.6"
+ attribute \src "libresoc.v:97708.3-97810.6"
wire width 5 $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:95617.3-95719.6"
+ attribute \src "libresoc.v:95442.3-95544.6"
wire width 14 $1\dec31_dec_sub15_function_unit[13:0]
- attribute \src "libresoc.v:98604.3-98706.6"
+ attribute \src "libresoc.v:98429.3-98531.6"
wire width 3 $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:98707.3-98809.6"
+ attribute \src "libresoc.v:98532.3-98634.6"
wire width 4 $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:98810.3-98912.6"
+ attribute \src "libresoc.v:98635.3-98737.6"
wire width 2 $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:96750.3-96852.6"
+ attribute \src "libresoc.v:96575.3-96677.6"
wire width 7 $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:97265.3-97367.6"
+ attribute \src "libresoc.v:97090.3-97192.6"
wire $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:97368.3-97470.6"
+ attribute \src "libresoc.v:97193.3-97295.6"
wire $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:97986.3-98088.6"
+ attribute \src "libresoc.v:97811.3-97913.6"
wire $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:96647.3-96749.6"
+ attribute \src "libresoc.v:96472.3-96574.6"
wire width 4 $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:98192.3-98294.6"
+ attribute \src "libresoc.v:98017.3-98119.6"
wire $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:98913.3-99015.6"
+ attribute \src "libresoc.v:98738.3-98840.6"
wire width 3 $1\dec31_dec_sub15_out_sel[2:0]
- attribute \src "libresoc.v:96956.3-97058.6"
+ attribute \src "libresoc.v:96781.3-96883.6"
wire width 2 $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:97780.3-97882.6"
+ attribute \src "libresoc.v:97605.3-97707.6"
wire $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:98295.3-98397.6"
+ attribute \src "libresoc.v:98120.3-98222.6"
wire $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:98089.3-98191.6"
+ attribute \src "libresoc.v:97914.3-98016.6"
wire $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:97677.3-97779.6"
+ attribute \src "libresoc.v:97502.3-97604.6"
wire $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:96441.3-96543.6"
+ attribute \src "libresoc.v:96266.3-96368.6"
wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:96544.3-96646.6"
+ attribute \src "libresoc.v:96369.3-96471.6"
wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:95926.3-96028.6"
+ attribute \src "libresoc.v:95751.3-95853.6"
wire width 3 $1\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:96029.3-96131.6"
+ attribute \src "libresoc.v:95854.3-95956.6"
wire width 3 $1\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:96132.3-96234.6"
+ attribute \src "libresoc.v:95957.3-96059.6"
wire width 3 $1\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:96338.3-96440.6"
+ attribute \src "libresoc.v:96163.3-96265.6"
wire width 3 $1\dec31_dec_sub15_sv_out2[2:0]
- attribute \src "libresoc.v:96235.3-96337.6"
+ attribute \src "libresoc.v:96060.3-96162.6"
wire width 3 $1\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:96853.3-96955.6"
+ attribute \src "libresoc.v:96678.3-96780.6"
wire width 2 $1\dec31_dec_sub15_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub15_upd
- attribute \src "libresoc.v:95269.7-95269.15"
+ attribute \src "libresoc.v:95094.7-95094.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:95269.7-95269.20"
- process $proc$libresoc.v:95269$3986
+ attribute \src "libresoc.v:95094.7-95094.20"
+ process $proc$libresoc.v:95094$3970
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:95617.3-95719.6"
- process $proc$libresoc.v:95617$3953
+ attribute \src "libresoc.v:95442.3-95544.6"
+ process $proc$libresoc.v:95442$3937
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0]
- attribute \src "libresoc.v:95618.5-95618.29"
+ attribute \src "libresoc.v:95443.5-95443.29"
switch \initial
- attribute \src "libresoc.v:95618.9-95618.17"
+ attribute \src "libresoc.v:95443.9-95443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0]
end
- attribute \src "libresoc.v:95720.3-95822.6"
- process $proc$libresoc.v:95720$3954
+ attribute \src "libresoc.v:95545.3-95647.6"
+ process $proc$libresoc.v:95545$3938
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:95721.5-95721.29"
+ attribute \src "libresoc.v:95546.5-95546.29"
switch \initial
- attribute \src "libresoc.v:95721.9-95721.17"
+ attribute \src "libresoc.v:95546.9-95546.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0]
end
- attribute \src "libresoc.v:95823.3-95925.6"
- process $proc$libresoc.v:95823$3955
+ attribute \src "libresoc.v:95648.3-95750.6"
+ process $proc$libresoc.v:95648$3939
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:95824.5-95824.29"
+ attribute \src "libresoc.v:95649.5-95649.29"
switch \initial
- attribute \src "libresoc.v:95824.9-95824.17"
+ attribute \src "libresoc.v:95649.9-95649.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0]
end
- attribute \src "libresoc.v:95926.3-96028.6"
- process $proc$libresoc.v:95926$3956
+ attribute \src "libresoc.v:95751.3-95853.6"
+ process $proc$libresoc.v:95751$3940
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:95927.5-95927.29"
+ attribute \src "libresoc.v:95752.5-95752.29"
switch \initial
- attribute \src "libresoc.v:95927.9-95927.17"
+ attribute \src "libresoc.v:95752.9-95752.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0]
end
- attribute \src "libresoc.v:96029.3-96131.6"
- process $proc$libresoc.v:96029$3957
+ attribute \src "libresoc.v:95854.3-95956.6"
+ process $proc$libresoc.v:95854$3941
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:96030.5-96030.29"
+ attribute \src "libresoc.v:95855.5-95855.29"
switch \initial
- attribute \src "libresoc.v:96030.9-96030.17"
+ attribute \src "libresoc.v:95855.9-95855.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0]
end
- attribute \src "libresoc.v:96132.3-96234.6"
- process $proc$libresoc.v:96132$3958
+ attribute \src "libresoc.v:95957.3-96059.6"
+ process $proc$libresoc.v:95957$3942
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:96133.5-96133.29"
+ attribute \src "libresoc.v:95958.5-95958.29"
switch \initial
- attribute \src "libresoc.v:96133.9-96133.17"
+ attribute \src "libresoc.v:95958.9-95958.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0]
end
- attribute \src "libresoc.v:96235.3-96337.6"
- process $proc$libresoc.v:96235$3959
+ attribute \src "libresoc.v:96060.3-96162.6"
+ process $proc$libresoc.v:96060$3943
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:96236.5-96236.29"
+ attribute \src "libresoc.v:96061.5-96061.29"
switch \initial
- attribute \src "libresoc.v:96236.9-96236.17"
+ attribute \src "libresoc.v:96061.9-96061.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0]
end
- attribute \src "libresoc.v:96338.3-96440.6"
- process $proc$libresoc.v:96338$3960
+ attribute \src "libresoc.v:96163.3-96265.6"
+ process $proc$libresoc.v:96163$3944
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0]
- attribute \src "libresoc.v:96339.5-96339.29"
+ attribute \src "libresoc.v:96164.5-96164.29"
switch \initial
- attribute \src "libresoc.v:96339.9-96339.17"
+ attribute \src "libresoc.v:96164.9-96164.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0]
end
- attribute \src "libresoc.v:96441.3-96543.6"
- process $proc$libresoc.v:96441$3961
+ attribute \src "libresoc.v:96266.3-96368.6"
+ process $proc$libresoc.v:96266$3945
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:96442.5-96442.29"
+ attribute \src "libresoc.v:96267.5-96267.29"
switch \initial
- attribute \src "libresoc.v:96442.9-96442.17"
+ attribute \src "libresoc.v:96267.9-96267.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:96544.3-96646.6"
- process $proc$libresoc.v:96544$3962
+ attribute \src "libresoc.v:96369.3-96471.6"
+ process $proc$libresoc.v:96369$3946
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:96545.5-96545.29"
+ attribute \src "libresoc.v:96370.5-96370.29"
switch \initial
- attribute \src "libresoc.v:96545.9-96545.17"
+ attribute \src "libresoc.v:96370.9-96370.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:96647.3-96749.6"
- process $proc$libresoc.v:96647$3963
+ attribute \src "libresoc.v:96472.3-96574.6"
+ process $proc$libresoc.v:96472$3947
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:96648.5-96648.29"
+ attribute \src "libresoc.v:96473.5-96473.29"
switch \initial
- attribute \src "libresoc.v:96648.9-96648.17"
+ attribute \src "libresoc.v:96473.9-96473.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0]
end
- attribute \src "libresoc.v:96750.3-96852.6"
- process $proc$libresoc.v:96750$3964
+ attribute \src "libresoc.v:96575.3-96677.6"
+ process $proc$libresoc.v:96575$3948
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:96751.5-96751.29"
+ attribute \src "libresoc.v:96576.5-96576.29"
switch \initial
- attribute \src "libresoc.v:96751.9-96751.17"
+ attribute \src "libresoc.v:96576.9-96576.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0]
end
- attribute \src "libresoc.v:96853.3-96955.6"
- process $proc$libresoc.v:96853$3965
+ attribute \src "libresoc.v:96678.3-96780.6"
+ process $proc$libresoc.v:96678$3949
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:96854.5-96854.29"
+ attribute \src "libresoc.v:96679.5-96679.29"
switch \initial
- attribute \src "libresoc.v:96854.9-96854.17"
+ attribute \src "libresoc.v:96679.9-96679.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0]
end
- attribute \src "libresoc.v:96956.3-97058.6"
- process $proc$libresoc.v:96956$3966
+ attribute \src "libresoc.v:96781.3-96883.6"
+ process $proc$libresoc.v:96781$3950
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:96957.5-96957.29"
+ attribute \src "libresoc.v:96782.5-96782.29"
switch \initial
- attribute \src "libresoc.v:96957.9-96957.17"
+ attribute \src "libresoc.v:96782.9-96782.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0]
end
- attribute \src "libresoc.v:97059.3-97161.6"
- process $proc$libresoc.v:97059$3967
+ attribute \src "libresoc.v:96884.3-96986.6"
+ process $proc$libresoc.v:96884$3951
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:97060.5-97060.29"
+ attribute \src "libresoc.v:96885.5-96885.29"
switch \initial
- attribute \src "libresoc.v:97060.9-97060.17"
+ attribute \src "libresoc.v:96885.9-96885.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0]
end
- attribute \src "libresoc.v:97162.3-97264.6"
- process $proc$libresoc.v:97162$3968
+ attribute \src "libresoc.v:96987.3-97089.6"
+ process $proc$libresoc.v:96987$3952
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:97163.5-97163.29"
+ attribute \src "libresoc.v:96988.5-96988.29"
switch \initial
- attribute \src "libresoc.v:97163.9-97163.17"
+ attribute \src "libresoc.v:96988.9-96988.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0]
end
- attribute \src "libresoc.v:97265.3-97367.6"
- process $proc$libresoc.v:97265$3969
+ attribute \src "libresoc.v:97090.3-97192.6"
+ process $proc$libresoc.v:97090$3953
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:97266.5-97266.29"
+ attribute \src "libresoc.v:97091.5-97091.29"
switch \initial
- attribute \src "libresoc.v:97266.9-97266.17"
+ attribute \src "libresoc.v:97091.9-97091.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0]
end
- attribute \src "libresoc.v:97368.3-97470.6"
- process $proc$libresoc.v:97368$3970
+ attribute \src "libresoc.v:97193.3-97295.6"
+ process $proc$libresoc.v:97193$3954
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:97369.5-97369.29"
+ attribute \src "libresoc.v:97194.5-97194.29"
switch \initial
- attribute \src "libresoc.v:97369.9-97369.17"
+ attribute \src "libresoc.v:97194.9-97194.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0]
end
- attribute \src "libresoc.v:97471.3-97573.6"
- process $proc$libresoc.v:97471$3971
+ attribute \src "libresoc.v:97296.3-97398.6"
+ process $proc$libresoc.v:97296$3955
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:97472.5-97472.29"
+ attribute \src "libresoc.v:97297.5-97297.29"
switch \initial
- attribute \src "libresoc.v:97472.9-97472.17"
+ attribute \src "libresoc.v:97297.9-97297.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0]
end
- attribute \src "libresoc.v:97574.3-97676.6"
- process $proc$libresoc.v:97574$3972
+ attribute \src "libresoc.v:97399.3-97501.6"
+ process $proc$libresoc.v:97399$3956
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:97575.5-97575.29"
+ attribute \src "libresoc.v:97400.5-97400.29"
switch \initial
- attribute \src "libresoc.v:97575.9-97575.17"
+ attribute \src "libresoc.v:97400.9-97400.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0]
end
- attribute \src "libresoc.v:97677.3-97779.6"
- process $proc$libresoc.v:97677$3973
+ attribute \src "libresoc.v:97502.3-97604.6"
+ process $proc$libresoc.v:97502$3957
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:97678.5-97678.29"
+ attribute \src "libresoc.v:97503.5-97503.29"
switch \initial
- attribute \src "libresoc.v:97678.9-97678.17"
+ attribute \src "libresoc.v:97503.9-97503.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0]
end
- attribute \src "libresoc.v:97780.3-97882.6"
- process $proc$libresoc.v:97780$3974
+ attribute \src "libresoc.v:97605.3-97707.6"
+ process $proc$libresoc.v:97605$3958
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:97781.5-97781.29"
+ attribute \src "libresoc.v:97606.5-97606.29"
switch \initial
- attribute \src "libresoc.v:97781.9-97781.17"
+ attribute \src "libresoc.v:97606.9-97606.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0]
end
- attribute \src "libresoc.v:97883.3-97985.6"
- process $proc$libresoc.v:97883$3975
+ attribute \src "libresoc.v:97708.3-97810.6"
+ process $proc$libresoc.v:97708$3959
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:97884.5-97884.29"
+ attribute \src "libresoc.v:97709.5-97709.29"
switch \initial
- attribute \src "libresoc.v:97884.9-97884.17"
+ attribute \src "libresoc.v:97709.9-97709.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0]
end
- attribute \src "libresoc.v:97986.3-98088.6"
- process $proc$libresoc.v:97986$3976
+ attribute \src "libresoc.v:97811.3-97913.6"
+ process $proc$libresoc.v:97811$3960
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:97987.5-97987.29"
+ attribute \src "libresoc.v:97812.5-97812.29"
switch \initial
- attribute \src "libresoc.v:97987.9-97987.17"
+ attribute \src "libresoc.v:97812.9-97812.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0]
end
- attribute \src "libresoc.v:98089.3-98191.6"
- process $proc$libresoc.v:98089$3977
+ attribute \src "libresoc.v:97914.3-98016.6"
+ process $proc$libresoc.v:97914$3961
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:98090.5-98090.29"
+ attribute \src "libresoc.v:97915.5-97915.29"
switch \initial
- attribute \src "libresoc.v:98090.9-98090.17"
+ attribute \src "libresoc.v:97915.9-97915.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0]
end
- attribute \src "libresoc.v:98192.3-98294.6"
- process $proc$libresoc.v:98192$3978
+ attribute \src "libresoc.v:98017.3-98119.6"
+ process $proc$libresoc.v:98017$3962
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:98193.5-98193.29"
+ attribute \src "libresoc.v:98018.5-98018.29"
switch \initial
- attribute \src "libresoc.v:98193.9-98193.17"
+ attribute \src "libresoc.v:98018.9-98018.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0]
end
- attribute \src "libresoc.v:98295.3-98397.6"
- process $proc$libresoc.v:98295$3979
+ attribute \src "libresoc.v:98120.3-98222.6"
+ process $proc$libresoc.v:98120$3963
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:98296.5-98296.29"
+ attribute \src "libresoc.v:98121.5-98121.29"
switch \initial
- attribute \src "libresoc.v:98296.9-98296.17"
+ attribute \src "libresoc.v:98121.9-98121.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:98398.3-98500.6"
- process $proc$libresoc.v:98398$3980
+ attribute \src "libresoc.v:98223.3-98325.6"
+ process $proc$libresoc.v:98223$3964
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:98399.5-98399.29"
+ attribute \src "libresoc.v:98224.5-98224.29"
switch \initial
- attribute \src "libresoc.v:98399.9-98399.17"
+ attribute \src "libresoc.v:98224.9-98224.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0]
end
- attribute \src "libresoc.v:98501.3-98603.6"
- process $proc$libresoc.v:98501$3981
+ attribute \src "libresoc.v:98326.3-98428.6"
+ process $proc$libresoc.v:98326$3965
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:98502.5-98502.29"
+ attribute \src "libresoc.v:98327.5-98327.29"
switch \initial
- attribute \src "libresoc.v:98502.9-98502.17"
+ attribute \src "libresoc.v:98327.9-98327.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:98604.3-98706.6"
- process $proc$libresoc.v:98604$3982
+ attribute \src "libresoc.v:98429.3-98531.6"
+ process $proc$libresoc.v:98429$3966
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:98605.5-98605.29"
+ attribute \src "libresoc.v:98430.5-98430.29"
switch \initial
- attribute \src "libresoc.v:98605.9-98605.17"
+ attribute \src "libresoc.v:98430.9-98430.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0]
end
- attribute \src "libresoc.v:98707.3-98809.6"
- process $proc$libresoc.v:98707$3983
+ attribute \src "libresoc.v:98532.3-98634.6"
+ process $proc$libresoc.v:98532$3967
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:98708.5-98708.29"
+ attribute \src "libresoc.v:98533.5-98533.29"
switch \initial
- attribute \src "libresoc.v:98708.9-98708.17"
+ attribute \src "libresoc.v:98533.9-98533.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0]
end
- attribute \src "libresoc.v:98810.3-98912.6"
- process $proc$libresoc.v:98810$3984
+ attribute \src "libresoc.v:98635.3-98737.6"
+ process $proc$libresoc.v:98635$3968
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:98811.5-98811.29"
+ attribute \src "libresoc.v:98636.5-98636.29"
switch \initial
- attribute \src "libresoc.v:98811.9-98811.17"
+ attribute \src "libresoc.v:98636.9-98636.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0]
end
- attribute \src "libresoc.v:98913.3-99015.6"
- process $proc$libresoc.v:98913$3985
+ attribute \src "libresoc.v:98738.3-98840.6"
+ process $proc$libresoc.v:98738$3969
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0]
- attribute \src "libresoc.v:98914.5-98914.29"
+ attribute \src "libresoc.v:98739.5-98739.29"
switch \initial
- attribute \src "libresoc.v:98914.9-98914.17"
+ attribute \src "libresoc.v:98739.9-98739.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:99021.1-99701.10"
+attribute \src "libresoc.v:98846.1-99526.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16"
attribute \generator "nMigen"
module \dec31_dec_sub16
- attribute \src "libresoc.v:99640.3-99649.6"
+ attribute \src "libresoc.v:99465.3-99474.6"
wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:99650.3-99659.6"
+ attribute \src "libresoc.v:99475.3-99484.6"
wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:99520.3-99529.6"
+ attribute \src "libresoc.v:99345.3-99354.6"
wire width 8 $0\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:99560.3-99569.6"
+ attribute \src "libresoc.v:99385.3-99394.6"
wire $0\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:99380.3-99389.6"
+ attribute \src "libresoc.v:99205.3-99214.6"
wire width 3 $0\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:99390.3-99399.6"
+ attribute \src "libresoc.v:99215.3-99224.6"
wire width 3 $0\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:99510.3-99519.6"
+ attribute \src "libresoc.v:99335.3-99344.6"
wire width 2 $0\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:99550.3-99559.6"
+ attribute \src "libresoc.v:99375.3-99384.6"
wire $0\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:99590.3-99599.6"
+ attribute \src "libresoc.v:99415.3-99424.6"
wire width 5 $0\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:99370.3-99379.6"
+ attribute \src "libresoc.v:99195.3-99204.6"
wire width 14 $0\dec31_dec_sub16_function_unit[13:0]
- attribute \src "libresoc.v:99660.3-99669.6"
+ attribute \src "libresoc.v:99485.3-99494.6"
wire width 3 $0\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:99670.3-99679.6"
+ attribute \src "libresoc.v:99495.3-99504.6"
wire width 4 $0\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:99680.3-99689.6"
+ attribute \src "libresoc.v:99505.3-99514.6"
wire width 2 $0\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:99480.3-99489.6"
+ attribute \src "libresoc.v:99305.3-99314.6"
wire width 7 $0\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:99530.3-99539.6"
+ attribute \src "libresoc.v:99355.3-99364.6"
wire $0\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:99540.3-99549.6"
+ attribute \src "libresoc.v:99365.3-99374.6"
wire $0\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:99600.3-99609.6"
+ attribute \src "libresoc.v:99425.3-99434.6"
wire $0\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:99470.3-99479.6"
+ attribute \src "libresoc.v:99295.3-99304.6"
wire width 4 $0\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:99620.3-99629.6"
+ attribute \src "libresoc.v:99445.3-99454.6"
wire $0\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:99690.3-99699.6"
+ attribute \src "libresoc.v:99515.3-99524.6"
wire width 3 $0\dec31_dec_sub16_out_sel[2:0]
- attribute \src "libresoc.v:99500.3-99509.6"
+ attribute \src "libresoc.v:99325.3-99334.6"
wire width 2 $0\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:99580.3-99589.6"
+ attribute \src "libresoc.v:99405.3-99414.6"
wire $0\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:99630.3-99639.6"
+ attribute \src "libresoc.v:99455.3-99464.6"
wire $0\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:99610.3-99619.6"
+ attribute \src "libresoc.v:99435.3-99444.6"
wire $0\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:99570.3-99579.6"
+ attribute \src "libresoc.v:99395.3-99404.6"
wire $0\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:99450.3-99459.6"
+ attribute \src "libresoc.v:99275.3-99284.6"
wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:99460.3-99469.6"
+ attribute \src "libresoc.v:99285.3-99294.6"
wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:99400.3-99409.6"
+ attribute \src "libresoc.v:99225.3-99234.6"
wire width 3 $0\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:99410.3-99419.6"
+ attribute \src "libresoc.v:99235.3-99244.6"
wire width 3 $0\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:99420.3-99429.6"
+ attribute \src "libresoc.v:99245.3-99254.6"
wire width 3 $0\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:99440.3-99449.6"
+ attribute \src "libresoc.v:99265.3-99274.6"
wire width 3 $0\dec31_dec_sub16_sv_out2[2:0]
- attribute \src "libresoc.v:99430.3-99439.6"
+ attribute \src "libresoc.v:99255.3-99264.6"
wire width 3 $0\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:99490.3-99499.6"
+ attribute \src "libresoc.v:99315.3-99324.6"
wire width 2 $0\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:99022.7-99022.20"
+ attribute \src "libresoc.v:98847.7-98847.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:99640.3-99649.6"
+ attribute \src "libresoc.v:99465.3-99474.6"
wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:99650.3-99659.6"
+ attribute \src "libresoc.v:99475.3-99484.6"
wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:99520.3-99529.6"
+ attribute \src "libresoc.v:99345.3-99354.6"
wire width 8 $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:99560.3-99569.6"
+ attribute \src "libresoc.v:99385.3-99394.6"
wire $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:99380.3-99389.6"
+ attribute \src "libresoc.v:99205.3-99214.6"
wire width 3 $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:99390.3-99399.6"
+ attribute \src "libresoc.v:99215.3-99224.6"
wire width 3 $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:99510.3-99519.6"
+ attribute \src "libresoc.v:99335.3-99344.6"
wire width 2 $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:99550.3-99559.6"
+ attribute \src "libresoc.v:99375.3-99384.6"
wire $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:99590.3-99599.6"
+ attribute \src "libresoc.v:99415.3-99424.6"
wire width 5 $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:99370.3-99379.6"
+ attribute \src "libresoc.v:99195.3-99204.6"
wire width 14 $1\dec31_dec_sub16_function_unit[13:0]
- attribute \src "libresoc.v:99660.3-99669.6"
+ attribute \src "libresoc.v:99485.3-99494.6"
wire width 3 $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:99670.3-99679.6"
+ attribute \src "libresoc.v:99495.3-99504.6"
wire width 4 $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:99680.3-99689.6"
+ attribute \src "libresoc.v:99505.3-99514.6"
wire width 2 $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:99480.3-99489.6"
+ attribute \src "libresoc.v:99305.3-99314.6"
wire width 7 $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:99530.3-99539.6"
+ attribute \src "libresoc.v:99355.3-99364.6"
wire $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:99540.3-99549.6"
+ attribute \src "libresoc.v:99365.3-99374.6"
wire $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:99600.3-99609.6"
+ attribute \src "libresoc.v:99425.3-99434.6"
wire $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:99470.3-99479.6"
+ attribute \src "libresoc.v:99295.3-99304.6"
wire width 4 $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:99620.3-99629.6"
+ attribute \src "libresoc.v:99445.3-99454.6"
wire $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:99690.3-99699.6"
+ attribute \src "libresoc.v:99515.3-99524.6"
wire width 3 $1\dec31_dec_sub16_out_sel[2:0]
- attribute \src "libresoc.v:99500.3-99509.6"
+ attribute \src "libresoc.v:99325.3-99334.6"
wire width 2 $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:99580.3-99589.6"
+ attribute \src "libresoc.v:99405.3-99414.6"
wire $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:99630.3-99639.6"
+ attribute \src "libresoc.v:99455.3-99464.6"
wire $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:99610.3-99619.6"
+ attribute \src "libresoc.v:99435.3-99444.6"
wire $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:99570.3-99579.6"
+ attribute \src "libresoc.v:99395.3-99404.6"
wire $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:99450.3-99459.6"
+ attribute \src "libresoc.v:99275.3-99284.6"
wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:99460.3-99469.6"
+ attribute \src "libresoc.v:99285.3-99294.6"
wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:99400.3-99409.6"
+ attribute \src "libresoc.v:99225.3-99234.6"
wire width 3 $1\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:99410.3-99419.6"
+ attribute \src "libresoc.v:99235.3-99244.6"
wire width 3 $1\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:99420.3-99429.6"
+ attribute \src "libresoc.v:99245.3-99254.6"
wire width 3 $1\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:99440.3-99449.6"
+ attribute \src "libresoc.v:99265.3-99274.6"
wire width 3 $1\dec31_dec_sub16_sv_out2[2:0]
- attribute \src "libresoc.v:99430.3-99439.6"
+ attribute \src "libresoc.v:99255.3-99264.6"
wire width 3 $1\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:99490.3-99499.6"
+ attribute \src "libresoc.v:99315.3-99324.6"
wire width 2 $1\dec31_dec_sub16_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub16_upd
- attribute \src "libresoc.v:99022.7-99022.15"
+ attribute \src "libresoc.v:98847.7-98847.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:99022.7-99022.20"
- process $proc$libresoc.v:99022$4020
+ attribute \src "libresoc.v:98847.7-98847.20"
+ process $proc$libresoc.v:98847$4004
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:99370.3-99379.6"
- process $proc$libresoc.v:99370$3987
+ attribute \src "libresoc.v:99195.3-99204.6"
+ process $proc$libresoc.v:99195$3971
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0]
- attribute \src "libresoc.v:99371.5-99371.29"
+ attribute \src "libresoc.v:99196.5-99196.29"
switch \initial
- attribute \src "libresoc.v:99371.9-99371.17"
+ attribute \src "libresoc.v:99196.9-99196.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0]
end
- attribute \src "libresoc.v:99380.3-99389.6"
- process $proc$libresoc.v:99380$3988
+ attribute \src "libresoc.v:99205.3-99214.6"
+ process $proc$libresoc.v:99205$3972
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:99381.5-99381.29"
+ attribute \src "libresoc.v:99206.5-99206.29"
switch \initial
- attribute \src "libresoc.v:99381.9-99381.17"
+ attribute \src "libresoc.v:99206.9-99206.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0]
end
- attribute \src "libresoc.v:99390.3-99399.6"
- process $proc$libresoc.v:99390$3989
+ attribute \src "libresoc.v:99215.3-99224.6"
+ process $proc$libresoc.v:99215$3973
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:99391.5-99391.29"
+ attribute \src "libresoc.v:99216.5-99216.29"
switch \initial
- attribute \src "libresoc.v:99391.9-99391.17"
+ attribute \src "libresoc.v:99216.9-99216.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0]
end
- attribute \src "libresoc.v:99400.3-99409.6"
- process $proc$libresoc.v:99400$3990
+ attribute \src "libresoc.v:99225.3-99234.6"
+ process $proc$libresoc.v:99225$3974
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:99401.5-99401.29"
+ attribute \src "libresoc.v:99226.5-99226.29"
switch \initial
- attribute \src "libresoc.v:99401.9-99401.17"
+ attribute \src "libresoc.v:99226.9-99226.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0]
end
- attribute \src "libresoc.v:99410.3-99419.6"
- process $proc$libresoc.v:99410$3991
+ attribute \src "libresoc.v:99235.3-99244.6"
+ process $proc$libresoc.v:99235$3975
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:99411.5-99411.29"
+ attribute \src "libresoc.v:99236.5-99236.29"
switch \initial
- attribute \src "libresoc.v:99411.9-99411.17"
+ attribute \src "libresoc.v:99236.9-99236.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0]
end
- attribute \src "libresoc.v:99420.3-99429.6"
- process $proc$libresoc.v:99420$3992
+ attribute \src "libresoc.v:99245.3-99254.6"
+ process $proc$libresoc.v:99245$3976
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:99421.5-99421.29"
+ attribute \src "libresoc.v:99246.5-99246.29"
switch \initial
- attribute \src "libresoc.v:99421.9-99421.17"
+ attribute \src "libresoc.v:99246.9-99246.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0]
end
- attribute \src "libresoc.v:99430.3-99439.6"
- process $proc$libresoc.v:99430$3993
+ attribute \src "libresoc.v:99255.3-99264.6"
+ process $proc$libresoc.v:99255$3977
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:99431.5-99431.29"
+ attribute \src "libresoc.v:99256.5-99256.29"
switch \initial
- attribute \src "libresoc.v:99431.9-99431.17"
+ attribute \src "libresoc.v:99256.9-99256.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0]
end
- attribute \src "libresoc.v:99440.3-99449.6"
- process $proc$libresoc.v:99440$3994
+ attribute \src "libresoc.v:99265.3-99274.6"
+ process $proc$libresoc.v:99265$3978
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0]
- attribute \src "libresoc.v:99441.5-99441.29"
+ attribute \src "libresoc.v:99266.5-99266.29"
switch \initial
- attribute \src "libresoc.v:99441.9-99441.17"
+ attribute \src "libresoc.v:99266.9-99266.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0]
end
- attribute \src "libresoc.v:99450.3-99459.6"
- process $proc$libresoc.v:99450$3995
+ attribute \src "libresoc.v:99275.3-99284.6"
+ process $proc$libresoc.v:99275$3979
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:99451.5-99451.29"
+ attribute \src "libresoc.v:99276.5-99276.29"
switch \initial
- attribute \src "libresoc.v:99451.9-99451.17"
+ attribute \src "libresoc.v:99276.9-99276.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:99460.3-99469.6"
- process $proc$libresoc.v:99460$3996
+ attribute \src "libresoc.v:99285.3-99294.6"
+ process $proc$libresoc.v:99285$3980
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:99461.5-99461.29"
+ attribute \src "libresoc.v:99286.5-99286.29"
switch \initial
- attribute \src "libresoc.v:99461.9-99461.17"
+ attribute \src "libresoc.v:99286.9-99286.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:99470.3-99479.6"
- process $proc$libresoc.v:99470$3997
+ attribute \src "libresoc.v:99295.3-99304.6"
+ process $proc$libresoc.v:99295$3981
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:99471.5-99471.29"
+ attribute \src "libresoc.v:99296.5-99296.29"
switch \initial
- attribute \src "libresoc.v:99471.9-99471.17"
+ attribute \src "libresoc.v:99296.9-99296.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0]
end
- attribute \src "libresoc.v:99480.3-99489.6"
- process $proc$libresoc.v:99480$3998
+ attribute \src "libresoc.v:99305.3-99314.6"
+ process $proc$libresoc.v:99305$3982
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:99481.5-99481.29"
+ attribute \src "libresoc.v:99306.5-99306.29"
switch \initial
- attribute \src "libresoc.v:99481.9-99481.17"
+ attribute \src "libresoc.v:99306.9-99306.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0]
end
- attribute \src "libresoc.v:99490.3-99499.6"
- process $proc$libresoc.v:99490$3999
+ attribute \src "libresoc.v:99315.3-99324.6"
+ process $proc$libresoc.v:99315$3983
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:99491.5-99491.29"
+ attribute \src "libresoc.v:99316.5-99316.29"
switch \initial
- attribute \src "libresoc.v:99491.9-99491.17"
+ attribute \src "libresoc.v:99316.9-99316.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0]
end
- attribute \src "libresoc.v:99500.3-99509.6"
- process $proc$libresoc.v:99500$4000
+ attribute \src "libresoc.v:99325.3-99334.6"
+ process $proc$libresoc.v:99325$3984
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:99501.5-99501.29"
+ attribute \src "libresoc.v:99326.5-99326.29"
switch \initial
- attribute \src "libresoc.v:99501.9-99501.17"
+ attribute \src "libresoc.v:99326.9-99326.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0]
end
- attribute \src "libresoc.v:99510.3-99519.6"
- process $proc$libresoc.v:99510$4001
+ attribute \src "libresoc.v:99335.3-99344.6"
+ process $proc$libresoc.v:99335$3985
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:99511.5-99511.29"
+ attribute \src "libresoc.v:99336.5-99336.29"
switch \initial
- attribute \src "libresoc.v:99511.9-99511.17"
+ attribute \src "libresoc.v:99336.9-99336.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0]
end
- attribute \src "libresoc.v:99520.3-99529.6"
- process $proc$libresoc.v:99520$4002
+ attribute \src "libresoc.v:99345.3-99354.6"
+ process $proc$libresoc.v:99345$3986
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:99521.5-99521.29"
+ attribute \src "libresoc.v:99346.5-99346.29"
switch \initial
- attribute \src "libresoc.v:99521.9-99521.17"
+ attribute \src "libresoc.v:99346.9-99346.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0]
end
- attribute \src "libresoc.v:99530.3-99539.6"
- process $proc$libresoc.v:99530$4003
+ attribute \src "libresoc.v:99355.3-99364.6"
+ process $proc$libresoc.v:99355$3987
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:99531.5-99531.29"
+ attribute \src "libresoc.v:99356.5-99356.29"
switch \initial
- attribute \src "libresoc.v:99531.9-99531.17"
+ attribute \src "libresoc.v:99356.9-99356.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0]
end
- attribute \src "libresoc.v:99540.3-99549.6"
- process $proc$libresoc.v:99540$4004
+ attribute \src "libresoc.v:99365.3-99374.6"
+ process $proc$libresoc.v:99365$3988
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:99541.5-99541.29"
+ attribute \src "libresoc.v:99366.5-99366.29"
switch \initial
- attribute \src "libresoc.v:99541.9-99541.17"
+ attribute \src "libresoc.v:99366.9-99366.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0]
end
- attribute \src "libresoc.v:99550.3-99559.6"
- process $proc$libresoc.v:99550$4005
+ attribute \src "libresoc.v:99375.3-99384.6"
+ process $proc$libresoc.v:99375$3989
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:99551.5-99551.29"
+ attribute \src "libresoc.v:99376.5-99376.29"
switch \initial
- attribute \src "libresoc.v:99551.9-99551.17"
+ attribute \src "libresoc.v:99376.9-99376.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0]
end
- attribute \src "libresoc.v:99560.3-99569.6"
- process $proc$libresoc.v:99560$4006
+ attribute \src "libresoc.v:99385.3-99394.6"
+ process $proc$libresoc.v:99385$3990
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:99561.5-99561.29"
+ attribute \src "libresoc.v:99386.5-99386.29"
switch \initial
- attribute \src "libresoc.v:99561.9-99561.17"
+ attribute \src "libresoc.v:99386.9-99386.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0]
end
- attribute \src "libresoc.v:99570.3-99579.6"
- process $proc$libresoc.v:99570$4007
+ attribute \src "libresoc.v:99395.3-99404.6"
+ process $proc$libresoc.v:99395$3991
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:99571.5-99571.29"
+ attribute \src "libresoc.v:99396.5-99396.29"
switch \initial
- attribute \src "libresoc.v:99571.9-99571.17"
+ attribute \src "libresoc.v:99396.9-99396.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0]
end
- attribute \src "libresoc.v:99580.3-99589.6"
- process $proc$libresoc.v:99580$4008
+ attribute \src "libresoc.v:99405.3-99414.6"
+ process $proc$libresoc.v:99405$3992
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:99581.5-99581.29"
+ attribute \src "libresoc.v:99406.5-99406.29"
switch \initial
- attribute \src "libresoc.v:99581.9-99581.17"
+ attribute \src "libresoc.v:99406.9-99406.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0]
end
- attribute \src "libresoc.v:99590.3-99599.6"
- process $proc$libresoc.v:99590$4009
+ attribute \src "libresoc.v:99415.3-99424.6"
+ process $proc$libresoc.v:99415$3993
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:99591.5-99591.29"
+ attribute \src "libresoc.v:99416.5-99416.29"
switch \initial
- attribute \src "libresoc.v:99591.9-99591.17"
+ attribute \src "libresoc.v:99416.9-99416.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0]
end
- attribute \src "libresoc.v:99600.3-99609.6"
- process $proc$libresoc.v:99600$4010
+ attribute \src "libresoc.v:99425.3-99434.6"
+ process $proc$libresoc.v:99425$3994
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:99601.5-99601.29"
+ attribute \src "libresoc.v:99426.5-99426.29"
switch \initial
- attribute \src "libresoc.v:99601.9-99601.17"
+ attribute \src "libresoc.v:99426.9-99426.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0]
end
- attribute \src "libresoc.v:99610.3-99619.6"
- process $proc$libresoc.v:99610$4011
+ attribute \src "libresoc.v:99435.3-99444.6"
+ process $proc$libresoc.v:99435$3995
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:99611.5-99611.29"
+ attribute \src "libresoc.v:99436.5-99436.29"
switch \initial
- attribute \src "libresoc.v:99611.9-99611.17"
+ attribute \src "libresoc.v:99436.9-99436.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0]
end
- attribute \src "libresoc.v:99620.3-99629.6"
- process $proc$libresoc.v:99620$4012
+ attribute \src "libresoc.v:99445.3-99454.6"
+ process $proc$libresoc.v:99445$3996
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:99621.5-99621.29"
+ attribute \src "libresoc.v:99446.5-99446.29"
switch \initial
- attribute \src "libresoc.v:99621.9-99621.17"
+ attribute \src "libresoc.v:99446.9-99446.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0]
end
- attribute \src "libresoc.v:99630.3-99639.6"
- process $proc$libresoc.v:99630$4013
+ attribute \src "libresoc.v:99455.3-99464.6"
+ process $proc$libresoc.v:99455$3997
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:99631.5-99631.29"
+ attribute \src "libresoc.v:99456.5-99456.29"
switch \initial
- attribute \src "libresoc.v:99631.9-99631.17"
+ attribute \src "libresoc.v:99456.9-99456.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:99640.3-99649.6"
- process $proc$libresoc.v:99640$4014
+ attribute \src "libresoc.v:99465.3-99474.6"
+ process $proc$libresoc.v:99465$3998
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:99641.5-99641.29"
+ attribute \src "libresoc.v:99466.5-99466.29"
switch \initial
- attribute \src "libresoc.v:99641.9-99641.17"
+ attribute \src "libresoc.v:99466.9-99466.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0]
end
- attribute \src "libresoc.v:99650.3-99659.6"
- process $proc$libresoc.v:99650$4015
+ attribute \src "libresoc.v:99475.3-99484.6"
+ process $proc$libresoc.v:99475$3999
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:99651.5-99651.29"
+ attribute \src "libresoc.v:99476.5-99476.29"
switch \initial
- attribute \src "libresoc.v:99651.9-99651.17"
+ attribute \src "libresoc.v:99476.9-99476.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:99660.3-99669.6"
- process $proc$libresoc.v:99660$4016
+ attribute \src "libresoc.v:99485.3-99494.6"
+ process $proc$libresoc.v:99485$4000
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:99661.5-99661.29"
+ attribute \src "libresoc.v:99486.5-99486.29"
switch \initial
- attribute \src "libresoc.v:99661.9-99661.17"
+ attribute \src "libresoc.v:99486.9-99486.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0]
end
- attribute \src "libresoc.v:99670.3-99679.6"
- process $proc$libresoc.v:99670$4017
+ attribute \src "libresoc.v:99495.3-99504.6"
+ process $proc$libresoc.v:99495$4001
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:99671.5-99671.29"
+ attribute \src "libresoc.v:99496.5-99496.29"
switch \initial
- attribute \src "libresoc.v:99671.9-99671.17"
+ attribute \src "libresoc.v:99496.9-99496.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0]
end
- attribute \src "libresoc.v:99680.3-99689.6"
- process $proc$libresoc.v:99680$4018
+ attribute \src "libresoc.v:99505.3-99514.6"
+ process $proc$libresoc.v:99505$4002
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:99681.5-99681.29"
+ attribute \src "libresoc.v:99506.5-99506.29"
switch \initial
- attribute \src "libresoc.v:99681.9-99681.17"
+ attribute \src "libresoc.v:99506.9-99506.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0]
end
- attribute \src "libresoc.v:99690.3-99699.6"
- process $proc$libresoc.v:99690$4019
+ attribute \src "libresoc.v:99515.3-99524.6"
+ process $proc$libresoc.v:99515$4003
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0]
- attribute \src "libresoc.v:99691.5-99691.29"
+ attribute \src "libresoc.v:99516.5-99516.29"
switch \initial
- attribute \src "libresoc.v:99691.9-99691.17"
+ attribute \src "libresoc.v:99516.9-99516.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:99705.1-100781.10"
+attribute \src "libresoc.v:99530.1-100606.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18"
attribute \generator "nMigen"
module \dec31_dec_sub18
- attribute \src "libresoc.v:100648.3-100669.6"
+ attribute \src "libresoc.v:100473.3-100494.6"
wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:100670.3-100691.6"
+ attribute \src "libresoc.v:100495.3-100516.6"
wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:100384.3-100405.6"
+ attribute \src "libresoc.v:100209.3-100230.6"
wire width 8 $0\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:100472.3-100493.6"
+ attribute \src "libresoc.v:100297.3-100318.6"
wire $0\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:100076.3-100097.6"
+ attribute \src "libresoc.v:99901.3-99922.6"
wire width 3 $0\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:100098.3-100119.6"
+ attribute \src "libresoc.v:99923.3-99944.6"
wire width 3 $0\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:100362.3-100383.6"
+ attribute \src "libresoc.v:100187.3-100208.6"
wire width 2 $0\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:100450.3-100471.6"
+ attribute \src "libresoc.v:100275.3-100296.6"
wire $0\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:100538.3-100559.6"
+ attribute \src "libresoc.v:100363.3-100384.6"
wire width 5 $0\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:100054.3-100075.6"
+ attribute \src "libresoc.v:99879.3-99900.6"
wire width 14 $0\dec31_dec_sub18_function_unit[13:0]
- attribute \src "libresoc.v:100692.3-100713.6"
+ attribute \src "libresoc.v:100517.3-100538.6"
wire width 3 $0\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:100714.3-100735.6"
+ attribute \src "libresoc.v:100539.3-100560.6"
wire width 4 $0\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:100736.3-100757.6"
+ attribute \src "libresoc.v:100561.3-100582.6"
wire width 2 $0\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:100296.3-100317.6"
+ attribute \src "libresoc.v:100121.3-100142.6"
wire width 7 $0\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:100406.3-100427.6"
+ attribute \src "libresoc.v:100231.3-100252.6"
wire $0\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:100428.3-100449.6"
+ attribute \src "libresoc.v:100253.3-100274.6"
wire $0\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:100560.3-100581.6"
+ attribute \src "libresoc.v:100385.3-100406.6"
wire $0\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:100274.3-100295.6"
+ attribute \src "libresoc.v:100099.3-100120.6"
wire width 4 $0\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:100604.3-100625.6"
+ attribute \src "libresoc.v:100429.3-100450.6"
wire $0\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:100758.3-100779.6"
+ attribute \src "libresoc.v:100583.3-100604.6"
wire width 3 $0\dec31_dec_sub18_out_sel[2:0]
- attribute \src "libresoc.v:100340.3-100361.6"
+ attribute \src "libresoc.v:100165.3-100186.6"
wire width 2 $0\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:100516.3-100537.6"
+ attribute \src "libresoc.v:100341.3-100362.6"
wire $0\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:100626.3-100647.6"
+ attribute \src "libresoc.v:100451.3-100472.6"
wire $0\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:100582.3-100603.6"
+ attribute \src "libresoc.v:100407.3-100428.6"
wire $0\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:100494.3-100515.6"
+ attribute \src "libresoc.v:100319.3-100340.6"
wire $0\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:100230.3-100251.6"
+ attribute \src "libresoc.v:100055.3-100076.6"
wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:100252.3-100273.6"
+ attribute \src "libresoc.v:100077.3-100098.6"
wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:100120.3-100141.6"
+ attribute \src "libresoc.v:99945.3-99966.6"
wire width 3 $0\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:100142.3-100163.6"
+ attribute \src "libresoc.v:99967.3-99988.6"
wire width 3 $0\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:100164.3-100185.6"
+ attribute \src "libresoc.v:99989.3-100010.6"
wire width 3 $0\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:100208.3-100229.6"
+ attribute \src "libresoc.v:100033.3-100054.6"
wire width 3 $0\dec31_dec_sub18_sv_out2[2:0]
- attribute \src "libresoc.v:100186.3-100207.6"
+ attribute \src "libresoc.v:100011.3-100032.6"
wire width 3 $0\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:100318.3-100339.6"
+ attribute \src "libresoc.v:100143.3-100164.6"
wire width 2 $0\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:99706.7-99706.20"
+ attribute \src "libresoc.v:99531.7-99531.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:100648.3-100669.6"
+ attribute \src "libresoc.v:100473.3-100494.6"
wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:100670.3-100691.6"
+ attribute \src "libresoc.v:100495.3-100516.6"
wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:100384.3-100405.6"
+ attribute \src "libresoc.v:100209.3-100230.6"
wire width 8 $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:100472.3-100493.6"
+ attribute \src "libresoc.v:100297.3-100318.6"
wire $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:100076.3-100097.6"
+ attribute \src "libresoc.v:99901.3-99922.6"
wire width 3 $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:100098.3-100119.6"
+ attribute \src "libresoc.v:99923.3-99944.6"
wire width 3 $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:100362.3-100383.6"
+ attribute \src "libresoc.v:100187.3-100208.6"
wire width 2 $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:100450.3-100471.6"
+ attribute \src "libresoc.v:100275.3-100296.6"
wire $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:100538.3-100559.6"
+ attribute \src "libresoc.v:100363.3-100384.6"
wire width 5 $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:100054.3-100075.6"
+ attribute \src "libresoc.v:99879.3-99900.6"
wire width 14 $1\dec31_dec_sub18_function_unit[13:0]
- attribute \src "libresoc.v:100692.3-100713.6"
+ attribute \src "libresoc.v:100517.3-100538.6"
wire width 3 $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:100714.3-100735.6"
+ attribute \src "libresoc.v:100539.3-100560.6"
wire width 4 $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:100736.3-100757.6"
+ attribute \src "libresoc.v:100561.3-100582.6"
wire width 2 $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:100296.3-100317.6"
+ attribute \src "libresoc.v:100121.3-100142.6"
wire width 7 $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:100406.3-100427.6"
+ attribute \src "libresoc.v:100231.3-100252.6"
wire $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:100428.3-100449.6"
+ attribute \src "libresoc.v:100253.3-100274.6"
wire $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:100560.3-100581.6"
+ attribute \src "libresoc.v:100385.3-100406.6"
wire $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:100274.3-100295.6"
+ attribute \src "libresoc.v:100099.3-100120.6"
wire width 4 $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:100604.3-100625.6"
+ attribute \src "libresoc.v:100429.3-100450.6"
wire $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:100758.3-100779.6"
+ attribute \src "libresoc.v:100583.3-100604.6"
wire width 3 $1\dec31_dec_sub18_out_sel[2:0]
- attribute \src "libresoc.v:100340.3-100361.6"
+ attribute \src "libresoc.v:100165.3-100186.6"
wire width 2 $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:100516.3-100537.6"
+ attribute \src "libresoc.v:100341.3-100362.6"
wire $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:100626.3-100647.6"
+ attribute \src "libresoc.v:100451.3-100472.6"
wire $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:100582.3-100603.6"
+ attribute \src "libresoc.v:100407.3-100428.6"
wire $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:100494.3-100515.6"
+ attribute \src "libresoc.v:100319.3-100340.6"
wire $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:100230.3-100251.6"
+ attribute \src "libresoc.v:100055.3-100076.6"
wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:100252.3-100273.6"
+ attribute \src "libresoc.v:100077.3-100098.6"
wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:100120.3-100141.6"
+ attribute \src "libresoc.v:99945.3-99966.6"
wire width 3 $1\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:100142.3-100163.6"
+ attribute \src "libresoc.v:99967.3-99988.6"
wire width 3 $1\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:100164.3-100185.6"
+ attribute \src "libresoc.v:99989.3-100010.6"
wire width 3 $1\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:100208.3-100229.6"
+ attribute \src "libresoc.v:100033.3-100054.6"
wire width 3 $1\dec31_dec_sub18_sv_out2[2:0]
- attribute \src "libresoc.v:100186.3-100207.6"
+ attribute \src "libresoc.v:100011.3-100032.6"
wire width 3 $1\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:100318.3-100339.6"
+ attribute \src "libresoc.v:100143.3-100164.6"
wire width 2 $1\dec31_dec_sub18_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub18_upd
- attribute \src "libresoc.v:99706.7-99706.15"
+ attribute \src "libresoc.v:99531.7-99531.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:100054.3-100075.6"
- process $proc$libresoc.v:100054$4021
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0]
- attribute \src "libresoc.v:100055.5-100055.29"
- switch \initial
- attribute \src "libresoc.v:100055.9-100055.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
- case
- assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000
- end
- sync always
- update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0]
- end
- attribute \src "libresoc.v:100076.3-100097.6"
- process $proc$libresoc.v:100076$4022
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:100077.5-100077.29"
- switch \initial
- attribute \src "libresoc.v:100077.9-100077.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- case
- assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0]
- end
- attribute \src "libresoc.v:100098.3-100119.6"
- process $proc$libresoc.v:100098$4023
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:100099.5-100099.29"
- switch \initial
- attribute \src "libresoc.v:100099.9-100099.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- case
- assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0]
- end
- attribute \src "libresoc.v:100120.3-100141.6"
- process $proc$libresoc.v:100120$4024
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:100121.5-100121.29"
- switch \initial
- attribute \src "libresoc.v:100121.9-100121.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- case
- assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0]
- end
- attribute \src "libresoc.v:100142.3-100163.6"
- process $proc$libresoc.v:100142$4025
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:100143.5-100143.29"
- switch \initial
- attribute \src "libresoc.v:100143.9-100143.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- case
- assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0]
- end
- attribute \src "libresoc.v:100164.3-100185.6"
- process $proc$libresoc.v:100164$4026
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:100165.5-100165.29"
- switch \initial
- attribute \src "libresoc.v:100165.9-100165.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00101
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00100
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01111
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01001
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- attribute \src "libresoc.v:0.0-0.0"
- case 5'01000
- assign { } { }
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- case
- assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0]
- end
- attribute \src "libresoc.v:100186.3-100207.6"
- process $proc$libresoc.v:100186$4027
+ attribute \src "libresoc.v:100011.3-100032.6"
+ process $proc$libresoc.v:100011$4011
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:100187.5-100187.29"
+ attribute \src "libresoc.v:100012.5-100012.29"
switch \initial
- attribute \src "libresoc.v:100187.9-100187.17"
+ attribute \src "libresoc.v:100012.9-100012.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0]
end
- attribute \src "libresoc.v:100208.3-100229.6"
- process $proc$libresoc.v:100208$4028
+ attribute \src "libresoc.v:100033.3-100054.6"
+ process $proc$libresoc.v:100033$4012
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0]
- attribute \src "libresoc.v:100209.5-100209.29"
+ attribute \src "libresoc.v:100034.5-100034.29"
switch \initial
- attribute \src "libresoc.v:100209.9-100209.17"
+ attribute \src "libresoc.v:100034.9-100034.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0]
end
- attribute \src "libresoc.v:100230.3-100251.6"
- process $proc$libresoc.v:100230$4029
+ attribute \src "libresoc.v:100055.3-100076.6"
+ process $proc$libresoc.v:100055$4013
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:100231.5-100231.29"
+ attribute \src "libresoc.v:100056.5-100056.29"
switch \initial
- attribute \src "libresoc.v:100231.9-100231.17"
+ attribute \src "libresoc.v:100056.9-100056.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:100252.3-100273.6"
- process $proc$libresoc.v:100252$4030
+ attribute \src "libresoc.v:100077.3-100098.6"
+ process $proc$libresoc.v:100077$4014
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:100253.5-100253.29"
+ attribute \src "libresoc.v:100078.5-100078.29"
switch \initial
- attribute \src "libresoc.v:100253.9-100253.17"
+ attribute \src "libresoc.v:100078.9-100078.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:100274.3-100295.6"
- process $proc$libresoc.v:100274$4031
+ attribute \src "libresoc.v:100099.3-100120.6"
+ process $proc$libresoc.v:100099$4015
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:100275.5-100275.29"
+ attribute \src "libresoc.v:100100.5-100100.29"
switch \initial
- attribute \src "libresoc.v:100275.9-100275.17"
+ attribute \src "libresoc.v:100100.9-100100.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0]
end
- attribute \src "libresoc.v:100296.3-100317.6"
- process $proc$libresoc.v:100296$4032
+ attribute \src "libresoc.v:100121.3-100142.6"
+ process $proc$libresoc.v:100121$4016
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:100297.5-100297.29"
+ attribute \src "libresoc.v:100122.5-100122.29"
switch \initial
- attribute \src "libresoc.v:100297.9-100297.17"
+ attribute \src "libresoc.v:100122.9-100122.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0]
end
- attribute \src "libresoc.v:100318.3-100339.6"
- process $proc$libresoc.v:100318$4033
+ attribute \src "libresoc.v:100143.3-100164.6"
+ process $proc$libresoc.v:100143$4017
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:100319.5-100319.29"
+ attribute \src "libresoc.v:100144.5-100144.29"
switch \initial
- attribute \src "libresoc.v:100319.9-100319.17"
+ attribute \src "libresoc.v:100144.9-100144.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0]
end
- attribute \src "libresoc.v:100340.3-100361.6"
- process $proc$libresoc.v:100340$4034
+ attribute \src "libresoc.v:100165.3-100186.6"
+ process $proc$libresoc.v:100165$4018
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:100341.5-100341.29"
+ attribute \src "libresoc.v:100166.5-100166.29"
switch \initial
- attribute \src "libresoc.v:100341.9-100341.17"
+ attribute \src "libresoc.v:100166.9-100166.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0]
end
- attribute \src "libresoc.v:100362.3-100383.6"
- process $proc$libresoc.v:100362$4035
+ attribute \src "libresoc.v:100187.3-100208.6"
+ process $proc$libresoc.v:100187$4019
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:100363.5-100363.29"
+ attribute \src "libresoc.v:100188.5-100188.29"
switch \initial
- attribute \src "libresoc.v:100363.9-100363.17"
+ attribute \src "libresoc.v:100188.9-100188.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0]
end
- attribute \src "libresoc.v:100384.3-100405.6"
- process $proc$libresoc.v:100384$4036
+ attribute \src "libresoc.v:100209.3-100230.6"
+ process $proc$libresoc.v:100209$4020
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:100385.5-100385.29"
+ attribute \src "libresoc.v:100210.5-100210.29"
switch \initial
- attribute \src "libresoc.v:100385.9-100385.17"
+ attribute \src "libresoc.v:100210.9-100210.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0]
end
- attribute \src "libresoc.v:100406.3-100427.6"
- process $proc$libresoc.v:100406$4037
+ attribute \src "libresoc.v:100231.3-100252.6"
+ process $proc$libresoc.v:100231$4021
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:100407.5-100407.29"
+ attribute \src "libresoc.v:100232.5-100232.29"
switch \initial
- attribute \src "libresoc.v:100407.9-100407.17"
+ attribute \src "libresoc.v:100232.9-100232.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0]
end
- attribute \src "libresoc.v:100428.3-100449.6"
- process $proc$libresoc.v:100428$4038
+ attribute \src "libresoc.v:100253.3-100274.6"
+ process $proc$libresoc.v:100253$4022
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:100429.5-100429.29"
+ attribute \src "libresoc.v:100254.5-100254.29"
switch \initial
- attribute \src "libresoc.v:100429.9-100429.17"
+ attribute \src "libresoc.v:100254.9-100254.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0]
end
- attribute \src "libresoc.v:100450.3-100471.6"
- process $proc$libresoc.v:100450$4039
+ attribute \src "libresoc.v:100275.3-100296.6"
+ process $proc$libresoc.v:100275$4023
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:100451.5-100451.29"
+ attribute \src "libresoc.v:100276.5-100276.29"
switch \initial
- attribute \src "libresoc.v:100451.9-100451.17"
+ attribute \src "libresoc.v:100276.9-100276.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0]
end
- attribute \src "libresoc.v:100472.3-100493.6"
- process $proc$libresoc.v:100472$4040
+ attribute \src "libresoc.v:100297.3-100318.6"
+ process $proc$libresoc.v:100297$4024
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:100473.5-100473.29"
+ attribute \src "libresoc.v:100298.5-100298.29"
switch \initial
- attribute \src "libresoc.v:100473.9-100473.17"
+ attribute \src "libresoc.v:100298.9-100298.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0]
end
- attribute \src "libresoc.v:100494.3-100515.6"
- process $proc$libresoc.v:100494$4041
+ attribute \src "libresoc.v:100319.3-100340.6"
+ process $proc$libresoc.v:100319$4025
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:100495.5-100495.29"
+ attribute \src "libresoc.v:100320.5-100320.29"
switch \initial
- attribute \src "libresoc.v:100495.9-100495.17"
+ attribute \src "libresoc.v:100320.9-100320.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0]
end
- attribute \src "libresoc.v:100516.3-100537.6"
- process $proc$libresoc.v:100516$4042
+ attribute \src "libresoc.v:100341.3-100362.6"
+ process $proc$libresoc.v:100341$4026
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:100517.5-100517.29"
+ attribute \src "libresoc.v:100342.5-100342.29"
switch \initial
- attribute \src "libresoc.v:100517.9-100517.17"
+ attribute \src "libresoc.v:100342.9-100342.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0]
end
- attribute \src "libresoc.v:100538.3-100559.6"
- process $proc$libresoc.v:100538$4043
+ attribute \src "libresoc.v:100363.3-100384.6"
+ process $proc$libresoc.v:100363$4027
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:100539.5-100539.29"
+ attribute \src "libresoc.v:100364.5-100364.29"
switch \initial
- attribute \src "libresoc.v:100539.9-100539.17"
+ attribute \src "libresoc.v:100364.9-100364.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0]
end
- attribute \src "libresoc.v:100560.3-100581.6"
- process $proc$libresoc.v:100560$4044
+ attribute \src "libresoc.v:100385.3-100406.6"
+ process $proc$libresoc.v:100385$4028
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:100561.5-100561.29"
+ attribute \src "libresoc.v:100386.5-100386.29"
switch \initial
- attribute \src "libresoc.v:100561.9-100561.17"
+ attribute \src "libresoc.v:100386.9-100386.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0]
end
- attribute \src "libresoc.v:100582.3-100603.6"
- process $proc$libresoc.v:100582$4045
+ attribute \src "libresoc.v:100407.3-100428.6"
+ process $proc$libresoc.v:100407$4029
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:100583.5-100583.29"
+ attribute \src "libresoc.v:100408.5-100408.29"
switch \initial
- attribute \src "libresoc.v:100583.9-100583.17"
+ attribute \src "libresoc.v:100408.9-100408.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0]
end
- attribute \src "libresoc.v:100604.3-100625.6"
- process $proc$libresoc.v:100604$4046
+ attribute \src "libresoc.v:100429.3-100450.6"
+ process $proc$libresoc.v:100429$4030
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:100605.5-100605.29"
+ attribute \src "libresoc.v:100430.5-100430.29"
switch \initial
- attribute \src "libresoc.v:100605.9-100605.17"
+ attribute \src "libresoc.v:100430.9-100430.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0]
end
- attribute \src "libresoc.v:100626.3-100647.6"
- process $proc$libresoc.v:100626$4047
+ attribute \src "libresoc.v:100451.3-100472.6"
+ process $proc$libresoc.v:100451$4031
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:100627.5-100627.29"
+ attribute \src "libresoc.v:100452.5-100452.29"
switch \initial
- attribute \src "libresoc.v:100627.9-100627.17"
+ attribute \src "libresoc.v:100452.9-100452.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:100648.3-100669.6"
- process $proc$libresoc.v:100648$4048
+ attribute \src "libresoc.v:100473.3-100494.6"
+ process $proc$libresoc.v:100473$4032
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:100649.5-100649.29"
+ attribute \src "libresoc.v:100474.5-100474.29"
switch \initial
- attribute \src "libresoc.v:100649.9-100649.17"
+ attribute \src "libresoc.v:100474.9-100474.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0]
end
- attribute \src "libresoc.v:100670.3-100691.6"
- process $proc$libresoc.v:100670$4049
+ attribute \src "libresoc.v:100495.3-100516.6"
+ process $proc$libresoc.v:100495$4033
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:100671.5-100671.29"
+ attribute \src "libresoc.v:100496.5-100496.29"
switch \initial
- attribute \src "libresoc.v:100671.9-100671.17"
+ attribute \src "libresoc.v:100496.9-100496.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:100692.3-100713.6"
- process $proc$libresoc.v:100692$4050
+ attribute \src "libresoc.v:100517.3-100538.6"
+ process $proc$libresoc.v:100517$4034
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:100693.5-100693.29"
+ attribute \src "libresoc.v:100518.5-100518.29"
switch \initial
- attribute \src "libresoc.v:100693.9-100693.17"
+ attribute \src "libresoc.v:100518.9-100518.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0]
end
- attribute \src "libresoc.v:100714.3-100735.6"
- process $proc$libresoc.v:100714$4051
+ attribute \src "libresoc.v:100539.3-100560.6"
+ process $proc$libresoc.v:100539$4035
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:100715.5-100715.29"
+ attribute \src "libresoc.v:100540.5-100540.29"
switch \initial
- attribute \src "libresoc.v:100715.9-100715.17"
+ attribute \src "libresoc.v:100540.9-100540.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0]
end
- attribute \src "libresoc.v:100736.3-100757.6"
- process $proc$libresoc.v:100736$4052
+ attribute \src "libresoc.v:100561.3-100582.6"
+ process $proc$libresoc.v:100561$4036
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:100737.5-100737.29"
+ attribute \src "libresoc.v:100562.5-100562.29"
switch \initial
- attribute \src "libresoc.v:100737.9-100737.17"
+ attribute \src "libresoc.v:100562.9-100562.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0]
end
- attribute \src "libresoc.v:100758.3-100779.6"
- process $proc$libresoc.v:100758$4053
+ attribute \src "libresoc.v:100583.3-100604.6"
+ process $proc$libresoc.v:100583$4037
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0]
- attribute \src "libresoc.v:100759.5-100759.29"
+ attribute \src "libresoc.v:100584.5-100584.29"
switch \initial
- attribute \src "libresoc.v:100759.9-100759.17"
+ attribute \src "libresoc.v:100584.9-100584.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0]
end
- attribute \src "libresoc.v:99706.7-99706.20"
- process $proc$libresoc.v:99706$4054
+ attribute \src "libresoc.v:99531.7-99531.20"
+ process $proc$libresoc.v:99531$4038
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
+ attribute \src "libresoc.v:99879.3-99900.6"
+ process $proc$libresoc.v:99879$4005
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0]
+ attribute \src "libresoc.v:99880.5-99880.29"
+ switch \initial
+ attribute \src "libresoc.v:99880.9-99880.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000
+ case
+ assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000
+ end
+ sync always
+ update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0]
+ end
+ attribute \src "libresoc.v:99901.3-99922.6"
+ process $proc$libresoc.v:99901$4006
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0]
+ attribute \src "libresoc.v:99902.5-99902.29"
+ switch \initial
+ attribute \src "libresoc.v:99902.9-99902.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ case
+ assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0]
+ end
+ attribute \src "libresoc.v:99923.3-99944.6"
+ process $proc$libresoc.v:99923$4007
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0]
+ attribute \src "libresoc.v:99924.5-99924.29"
+ switch \initial
+ attribute \src "libresoc.v:99924.9-99924.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ case
+ assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0]
+ end
+ attribute \src "libresoc.v:99945.3-99966.6"
+ process $proc$libresoc.v:99945$4008
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0]
+ attribute \src "libresoc.v:99946.5-99946.29"
+ switch \initial
+ attribute \src "libresoc.v:99946.9-99946.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ case
+ assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0]
+ end
+ attribute \src "libresoc.v:99967.3-99988.6"
+ process $proc$libresoc.v:99967$4009
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0]
+ attribute \src "libresoc.v:99968.5-99968.29"
+ switch \initial
+ attribute \src "libresoc.v:99968.9-99968.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ case
+ assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0]
+ end
+ attribute \src "libresoc.v:99989.3-100010.6"
+ process $proc$libresoc.v:99989$4010
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0]
+ attribute \src "libresoc.v:99990.5-99990.29"
+ switch \initial
+ attribute \src "libresoc.v:99990.9-99990.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00101
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00100
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01111
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01001
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'01000
+ assign { } { }
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ case
+ assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0]
+ end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:100785.1-101762.10"
+attribute \src "libresoc.v:100610.1-101587.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19"
attribute \generator "nMigen"
module \dec31_dec_sub19
- attribute \src "libresoc.v:101647.3-101665.6"
+ attribute \src "libresoc.v:101472.3-101490.6"
wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:101666.3-101684.6"
+ attribute \src "libresoc.v:101491.3-101509.6"
wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:101419.3-101437.6"
+ attribute \src "libresoc.v:101244.3-101262.6"
wire width 8 $0\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:101495.3-101513.6"
+ attribute \src "libresoc.v:101320.3-101338.6"
wire $0\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:101153.3-101171.6"
+ attribute \src "libresoc.v:100978.3-100996.6"
wire width 3 $0\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:101172.3-101190.6"
+ attribute \src "libresoc.v:100997.3-101015.6"
wire width 3 $0\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:101400.3-101418.6"
+ attribute \src "libresoc.v:101225.3-101243.6"
wire width 2 $0\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:101476.3-101494.6"
+ attribute \src "libresoc.v:101301.3-101319.6"
wire $0\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:101552.3-101570.6"
+ attribute \src "libresoc.v:101377.3-101395.6"
wire width 5 $0\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:101134.3-101152.6"
+ attribute \src "libresoc.v:100959.3-100977.6"
wire width 14 $0\dec31_dec_sub19_function_unit[13:0]
- attribute \src "libresoc.v:101685.3-101703.6"
+ attribute \src "libresoc.v:101510.3-101528.6"
wire width 3 $0\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:101704.3-101722.6"
+ attribute \src "libresoc.v:101529.3-101547.6"
wire width 4 $0\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:101723.3-101741.6"
+ attribute \src "libresoc.v:101548.3-101566.6"
wire width 2 $0\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:101343.3-101361.6"
+ attribute \src "libresoc.v:101168.3-101186.6"
wire width 7 $0\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:101438.3-101456.6"
+ attribute \src "libresoc.v:101263.3-101281.6"
wire $0\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:101457.3-101475.6"
+ attribute \src "libresoc.v:101282.3-101300.6"
wire $0\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:101571.3-101589.6"
+ attribute \src "libresoc.v:101396.3-101414.6"
wire $0\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:101324.3-101342.6"
+ attribute \src "libresoc.v:101149.3-101167.6"
wire width 4 $0\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:101609.3-101627.6"
+ attribute \src "libresoc.v:101434.3-101452.6"
wire $0\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:101742.3-101760.6"
+ attribute \src "libresoc.v:101567.3-101585.6"
wire width 3 $0\dec31_dec_sub19_out_sel[2:0]
- attribute \src "libresoc.v:101381.3-101399.6"
+ attribute \src "libresoc.v:101206.3-101224.6"
wire width 2 $0\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:101533.3-101551.6"
+ attribute \src "libresoc.v:101358.3-101376.6"
wire $0\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:101628.3-101646.6"
+ attribute \src "libresoc.v:101453.3-101471.6"
wire $0\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:101590.3-101608.6"
+ attribute \src "libresoc.v:101415.3-101433.6"
wire $0\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:101514.3-101532.6"
+ attribute \src "libresoc.v:101339.3-101357.6"
wire $0\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:101286.3-101304.6"
+ attribute \src "libresoc.v:101111.3-101129.6"
wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:101305.3-101323.6"
+ attribute \src "libresoc.v:101130.3-101148.6"
wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:101191.3-101209.6"
+ attribute \src "libresoc.v:101016.3-101034.6"
wire width 3 $0\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:101210.3-101228.6"
+ attribute \src "libresoc.v:101035.3-101053.6"
wire width 3 $0\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:101229.3-101247.6"
+ attribute \src "libresoc.v:101054.3-101072.6"
wire width 3 $0\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:101267.3-101285.6"
+ attribute \src "libresoc.v:101092.3-101110.6"
wire width 3 $0\dec31_dec_sub19_sv_out2[2:0]
- attribute \src "libresoc.v:101248.3-101266.6"
+ attribute \src "libresoc.v:101073.3-101091.6"
wire width 3 $0\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:101362.3-101380.6"
+ attribute \src "libresoc.v:101187.3-101205.6"
wire width 2 $0\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:100786.7-100786.20"
+ attribute \src "libresoc.v:100611.7-100611.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:101647.3-101665.6"
+ attribute \src "libresoc.v:101472.3-101490.6"
wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:101666.3-101684.6"
+ attribute \src "libresoc.v:101491.3-101509.6"
wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:101419.3-101437.6"
+ attribute \src "libresoc.v:101244.3-101262.6"
wire width 8 $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:101495.3-101513.6"
+ attribute \src "libresoc.v:101320.3-101338.6"
wire $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:101153.3-101171.6"
+ attribute \src "libresoc.v:100978.3-100996.6"
wire width 3 $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:101172.3-101190.6"
+ attribute \src "libresoc.v:100997.3-101015.6"
wire width 3 $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:101400.3-101418.6"
+ attribute \src "libresoc.v:101225.3-101243.6"
wire width 2 $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:101476.3-101494.6"
+ attribute \src "libresoc.v:101301.3-101319.6"
wire $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:101552.3-101570.6"
+ attribute \src "libresoc.v:101377.3-101395.6"
wire width 5 $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:101134.3-101152.6"
+ attribute \src "libresoc.v:100959.3-100977.6"
wire width 14 $1\dec31_dec_sub19_function_unit[13:0]
- attribute \src "libresoc.v:101685.3-101703.6"
+ attribute \src "libresoc.v:101510.3-101528.6"
wire width 3 $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:101704.3-101722.6"
+ attribute \src "libresoc.v:101529.3-101547.6"
wire width 4 $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:101723.3-101741.6"
+ attribute \src "libresoc.v:101548.3-101566.6"
wire width 2 $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:101343.3-101361.6"
+ attribute \src "libresoc.v:101168.3-101186.6"
wire width 7 $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:101438.3-101456.6"
+ attribute \src "libresoc.v:101263.3-101281.6"
wire $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:101457.3-101475.6"
+ attribute \src "libresoc.v:101282.3-101300.6"
wire $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:101571.3-101589.6"
+ attribute \src "libresoc.v:101396.3-101414.6"
wire $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:101324.3-101342.6"
+ attribute \src "libresoc.v:101149.3-101167.6"
wire width 4 $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:101609.3-101627.6"
+ attribute \src "libresoc.v:101434.3-101452.6"
wire $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:101742.3-101760.6"
+ attribute \src "libresoc.v:101567.3-101585.6"
wire width 3 $1\dec31_dec_sub19_out_sel[2:0]
- attribute \src "libresoc.v:101381.3-101399.6"
+ attribute \src "libresoc.v:101206.3-101224.6"
wire width 2 $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:101533.3-101551.6"
+ attribute \src "libresoc.v:101358.3-101376.6"
wire $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:101628.3-101646.6"
+ attribute \src "libresoc.v:101453.3-101471.6"
wire $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:101590.3-101608.6"
+ attribute \src "libresoc.v:101415.3-101433.6"
wire $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:101514.3-101532.6"
+ attribute \src "libresoc.v:101339.3-101357.6"
wire $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:101286.3-101304.6"
+ attribute \src "libresoc.v:101111.3-101129.6"
wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:101305.3-101323.6"
+ attribute \src "libresoc.v:101130.3-101148.6"
wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:101191.3-101209.6"
+ attribute \src "libresoc.v:101016.3-101034.6"
wire width 3 $1\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:101210.3-101228.6"
+ attribute \src "libresoc.v:101035.3-101053.6"
wire width 3 $1\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:101229.3-101247.6"
+ attribute \src "libresoc.v:101054.3-101072.6"
wire width 3 $1\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:101267.3-101285.6"
+ attribute \src "libresoc.v:101092.3-101110.6"
wire width 3 $1\dec31_dec_sub19_sv_out2[2:0]
- attribute \src "libresoc.v:101248.3-101266.6"
+ attribute \src "libresoc.v:101073.3-101091.6"
wire width 3 $1\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:101362.3-101380.6"
+ attribute \src "libresoc.v:101187.3-101205.6"
wire width 2 $1\dec31_dec_sub19_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub19_upd
- attribute \src "libresoc.v:100786.7-100786.15"
+ attribute \src "libresoc.v:100611.7-100611.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:100786.7-100786.20"
- process $proc$libresoc.v:100786$4088
+ attribute \src "libresoc.v:100611.7-100611.20"
+ process $proc$libresoc.v:100611$4072
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:101134.3-101152.6"
- process $proc$libresoc.v:101134$4055
+ attribute \src "libresoc.v:100959.3-100977.6"
+ process $proc$libresoc.v:100959$4039
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0]
- attribute \src "libresoc.v:101135.5-101135.29"
+ attribute \src "libresoc.v:100960.5-100960.29"
switch \initial
- attribute \src "libresoc.v:101135.9-101135.17"
+ attribute \src "libresoc.v:100960.9-100960.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0]
end
- attribute \src "libresoc.v:101153.3-101171.6"
- process $proc$libresoc.v:101153$4056
+ attribute \src "libresoc.v:100978.3-100996.6"
+ process $proc$libresoc.v:100978$4040
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:101154.5-101154.29"
+ attribute \src "libresoc.v:100979.5-100979.29"
switch \initial
- attribute \src "libresoc.v:101154.9-101154.17"
+ attribute \src "libresoc.v:100979.9-100979.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0]
end
- attribute \src "libresoc.v:101172.3-101190.6"
- process $proc$libresoc.v:101172$4057
+ attribute \src "libresoc.v:100997.3-101015.6"
+ process $proc$libresoc.v:100997$4041
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:101173.5-101173.29"
+ attribute \src "libresoc.v:100998.5-100998.29"
switch \initial
- attribute \src "libresoc.v:101173.9-101173.17"
+ attribute \src "libresoc.v:100998.9-100998.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0]
end
- attribute \src "libresoc.v:101191.3-101209.6"
- process $proc$libresoc.v:101191$4058
+ attribute \src "libresoc.v:101016.3-101034.6"
+ process $proc$libresoc.v:101016$4042
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:101192.5-101192.29"
+ attribute \src "libresoc.v:101017.5-101017.29"
switch \initial
- attribute \src "libresoc.v:101192.9-101192.17"
+ attribute \src "libresoc.v:101017.9-101017.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0]
end
- attribute \src "libresoc.v:101210.3-101228.6"
- process $proc$libresoc.v:101210$4059
+ attribute \src "libresoc.v:101035.3-101053.6"
+ process $proc$libresoc.v:101035$4043
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:101211.5-101211.29"
+ attribute \src "libresoc.v:101036.5-101036.29"
switch \initial
- attribute \src "libresoc.v:101211.9-101211.17"
+ attribute \src "libresoc.v:101036.9-101036.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0]
end
- attribute \src "libresoc.v:101229.3-101247.6"
- process $proc$libresoc.v:101229$4060
+ attribute \src "libresoc.v:101054.3-101072.6"
+ process $proc$libresoc.v:101054$4044
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:101230.5-101230.29"
+ attribute \src "libresoc.v:101055.5-101055.29"
switch \initial
- attribute \src "libresoc.v:101230.9-101230.17"
+ attribute \src "libresoc.v:101055.9-101055.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0]
end
- attribute \src "libresoc.v:101248.3-101266.6"
- process $proc$libresoc.v:101248$4061
+ attribute \src "libresoc.v:101073.3-101091.6"
+ process $proc$libresoc.v:101073$4045
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:101249.5-101249.29"
+ attribute \src "libresoc.v:101074.5-101074.29"
switch \initial
- attribute \src "libresoc.v:101249.9-101249.17"
+ attribute \src "libresoc.v:101074.9-101074.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0]
end
- attribute \src "libresoc.v:101267.3-101285.6"
- process $proc$libresoc.v:101267$4062
+ attribute \src "libresoc.v:101092.3-101110.6"
+ process $proc$libresoc.v:101092$4046
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0]
- attribute \src "libresoc.v:101268.5-101268.29"
+ attribute \src "libresoc.v:101093.5-101093.29"
switch \initial
- attribute \src "libresoc.v:101268.9-101268.17"
+ attribute \src "libresoc.v:101093.9-101093.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0]
end
- attribute \src "libresoc.v:101286.3-101304.6"
- process $proc$libresoc.v:101286$4063
+ attribute \src "libresoc.v:101111.3-101129.6"
+ process $proc$libresoc.v:101111$4047
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:101287.5-101287.29"
+ attribute \src "libresoc.v:101112.5-101112.29"
switch \initial
- attribute \src "libresoc.v:101287.9-101287.17"
+ attribute \src "libresoc.v:101112.9-101112.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:101305.3-101323.6"
- process $proc$libresoc.v:101305$4064
+ attribute \src "libresoc.v:101130.3-101148.6"
+ process $proc$libresoc.v:101130$4048
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:101306.5-101306.29"
+ attribute \src "libresoc.v:101131.5-101131.29"
switch \initial
- attribute \src "libresoc.v:101306.9-101306.17"
+ attribute \src "libresoc.v:101131.9-101131.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:101324.3-101342.6"
- process $proc$libresoc.v:101324$4065
+ attribute \src "libresoc.v:101149.3-101167.6"
+ process $proc$libresoc.v:101149$4049
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:101325.5-101325.29"
+ attribute \src "libresoc.v:101150.5-101150.29"
switch \initial
- attribute \src "libresoc.v:101325.9-101325.17"
+ attribute \src "libresoc.v:101150.9-101150.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0]
end
- attribute \src "libresoc.v:101343.3-101361.6"
- process $proc$libresoc.v:101343$4066
+ attribute \src "libresoc.v:101168.3-101186.6"
+ process $proc$libresoc.v:101168$4050
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:101344.5-101344.29"
+ attribute \src "libresoc.v:101169.5-101169.29"
switch \initial
- attribute \src "libresoc.v:101344.9-101344.17"
+ attribute \src "libresoc.v:101169.9-101169.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0]
end
- attribute \src "libresoc.v:101362.3-101380.6"
- process $proc$libresoc.v:101362$4067
+ attribute \src "libresoc.v:101187.3-101205.6"
+ process $proc$libresoc.v:101187$4051
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:101363.5-101363.29"
+ attribute \src "libresoc.v:101188.5-101188.29"
switch \initial
- attribute \src "libresoc.v:101363.9-101363.17"
+ attribute \src "libresoc.v:101188.9-101188.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0]
end
- attribute \src "libresoc.v:101381.3-101399.6"
- process $proc$libresoc.v:101381$4068
+ attribute \src "libresoc.v:101206.3-101224.6"
+ process $proc$libresoc.v:101206$4052
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:101382.5-101382.29"
+ attribute \src "libresoc.v:101207.5-101207.29"
switch \initial
- attribute \src "libresoc.v:101382.9-101382.17"
+ attribute \src "libresoc.v:101207.9-101207.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0]
end
- attribute \src "libresoc.v:101400.3-101418.6"
- process $proc$libresoc.v:101400$4069
+ attribute \src "libresoc.v:101225.3-101243.6"
+ process $proc$libresoc.v:101225$4053
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:101401.5-101401.29"
+ attribute \src "libresoc.v:101226.5-101226.29"
switch \initial
- attribute \src "libresoc.v:101401.9-101401.17"
+ attribute \src "libresoc.v:101226.9-101226.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0]
end
- attribute \src "libresoc.v:101419.3-101437.6"
- process $proc$libresoc.v:101419$4070
+ attribute \src "libresoc.v:101244.3-101262.6"
+ process $proc$libresoc.v:101244$4054
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:101420.5-101420.29"
+ attribute \src "libresoc.v:101245.5-101245.29"
switch \initial
- attribute \src "libresoc.v:101420.9-101420.17"
+ attribute \src "libresoc.v:101245.9-101245.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0]
end
- attribute \src "libresoc.v:101438.3-101456.6"
- process $proc$libresoc.v:101438$4071
+ attribute \src "libresoc.v:101263.3-101281.6"
+ process $proc$libresoc.v:101263$4055
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:101439.5-101439.29"
+ attribute \src "libresoc.v:101264.5-101264.29"
switch \initial
- attribute \src "libresoc.v:101439.9-101439.17"
+ attribute \src "libresoc.v:101264.9-101264.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0]
end
- attribute \src "libresoc.v:101457.3-101475.6"
- process $proc$libresoc.v:101457$4072
+ attribute \src "libresoc.v:101282.3-101300.6"
+ process $proc$libresoc.v:101282$4056
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:101458.5-101458.29"
+ attribute \src "libresoc.v:101283.5-101283.29"
switch \initial
- attribute \src "libresoc.v:101458.9-101458.17"
+ attribute \src "libresoc.v:101283.9-101283.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0]
end
- attribute \src "libresoc.v:101476.3-101494.6"
- process $proc$libresoc.v:101476$4073
+ attribute \src "libresoc.v:101301.3-101319.6"
+ process $proc$libresoc.v:101301$4057
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:101477.5-101477.29"
+ attribute \src "libresoc.v:101302.5-101302.29"
switch \initial
- attribute \src "libresoc.v:101477.9-101477.17"
+ attribute \src "libresoc.v:101302.9-101302.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0]
end
- attribute \src "libresoc.v:101495.3-101513.6"
- process $proc$libresoc.v:101495$4074
+ attribute \src "libresoc.v:101320.3-101338.6"
+ process $proc$libresoc.v:101320$4058
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:101496.5-101496.29"
+ attribute \src "libresoc.v:101321.5-101321.29"
switch \initial
- attribute \src "libresoc.v:101496.9-101496.17"
+ attribute \src "libresoc.v:101321.9-101321.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0]
end
- attribute \src "libresoc.v:101514.3-101532.6"
- process $proc$libresoc.v:101514$4075
+ attribute \src "libresoc.v:101339.3-101357.6"
+ process $proc$libresoc.v:101339$4059
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:101515.5-101515.29"
+ attribute \src "libresoc.v:101340.5-101340.29"
switch \initial
- attribute \src "libresoc.v:101515.9-101515.17"
+ attribute \src "libresoc.v:101340.9-101340.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:101533.3-101551.6"
- process $proc$libresoc.v:101533$4076
+ attribute \src "libresoc.v:101358.3-101376.6"
+ process $proc$libresoc.v:101358$4060
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:101534.5-101534.29"
+ attribute \src "libresoc.v:101359.5-101359.29"
switch \initial
- attribute \src "libresoc.v:101534.9-101534.17"
+ attribute \src "libresoc.v:101359.9-101359.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0]
end
- attribute \src "libresoc.v:101552.3-101570.6"
- process $proc$libresoc.v:101552$4077
+ attribute \src "libresoc.v:101377.3-101395.6"
+ process $proc$libresoc.v:101377$4061
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:101553.5-101553.29"
+ attribute \src "libresoc.v:101378.5-101378.29"
switch \initial
- attribute \src "libresoc.v:101553.9-101553.17"
+ attribute \src "libresoc.v:101378.9-101378.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0]
end
- attribute \src "libresoc.v:101571.3-101589.6"
- process $proc$libresoc.v:101571$4078
+ attribute \src "libresoc.v:101396.3-101414.6"
+ process $proc$libresoc.v:101396$4062
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:101572.5-101572.29"
+ attribute \src "libresoc.v:101397.5-101397.29"
switch \initial
- attribute \src "libresoc.v:101572.9-101572.17"
+ attribute \src "libresoc.v:101397.9-101397.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0]
end
- attribute \src "libresoc.v:101590.3-101608.6"
- process $proc$libresoc.v:101590$4079
+ attribute \src "libresoc.v:101415.3-101433.6"
+ process $proc$libresoc.v:101415$4063
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:101591.5-101591.29"
+ attribute \src "libresoc.v:101416.5-101416.29"
switch \initial
- attribute \src "libresoc.v:101591.9-101591.17"
+ attribute \src "libresoc.v:101416.9-101416.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0]
end
- attribute \src "libresoc.v:101609.3-101627.6"
- process $proc$libresoc.v:101609$4080
+ attribute \src "libresoc.v:101434.3-101452.6"
+ process $proc$libresoc.v:101434$4064
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:101610.5-101610.29"
+ attribute \src "libresoc.v:101435.5-101435.29"
switch \initial
- attribute \src "libresoc.v:101610.9-101610.17"
+ attribute \src "libresoc.v:101435.9-101435.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0]
end
- attribute \src "libresoc.v:101628.3-101646.6"
- process $proc$libresoc.v:101628$4081
+ attribute \src "libresoc.v:101453.3-101471.6"
+ process $proc$libresoc.v:101453$4065
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:101629.5-101629.29"
+ attribute \src "libresoc.v:101454.5-101454.29"
switch \initial
- attribute \src "libresoc.v:101629.9-101629.17"
+ attribute \src "libresoc.v:101454.9-101454.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:101647.3-101665.6"
- process $proc$libresoc.v:101647$4082
+ attribute \src "libresoc.v:101472.3-101490.6"
+ process $proc$libresoc.v:101472$4066
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:101648.5-101648.29"
+ attribute \src "libresoc.v:101473.5-101473.29"
switch \initial
- attribute \src "libresoc.v:101648.9-101648.17"
+ attribute \src "libresoc.v:101473.9-101473.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0]
end
- attribute \src "libresoc.v:101666.3-101684.6"
- process $proc$libresoc.v:101666$4083
+ attribute \src "libresoc.v:101491.3-101509.6"
+ process $proc$libresoc.v:101491$4067
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:101667.5-101667.29"
+ attribute \src "libresoc.v:101492.5-101492.29"
switch \initial
- attribute \src "libresoc.v:101667.9-101667.17"
+ attribute \src "libresoc.v:101492.9-101492.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:101685.3-101703.6"
- process $proc$libresoc.v:101685$4084
+ attribute \src "libresoc.v:101510.3-101528.6"
+ process $proc$libresoc.v:101510$4068
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:101686.5-101686.29"
+ attribute \src "libresoc.v:101511.5-101511.29"
switch \initial
- attribute \src "libresoc.v:101686.9-101686.17"
+ attribute \src "libresoc.v:101511.9-101511.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0]
end
- attribute \src "libresoc.v:101704.3-101722.6"
- process $proc$libresoc.v:101704$4085
+ attribute \src "libresoc.v:101529.3-101547.6"
+ process $proc$libresoc.v:101529$4069
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:101705.5-101705.29"
+ attribute \src "libresoc.v:101530.5-101530.29"
switch \initial
- attribute \src "libresoc.v:101705.9-101705.17"
+ attribute \src "libresoc.v:101530.9-101530.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0]
end
- attribute \src "libresoc.v:101723.3-101741.6"
- process $proc$libresoc.v:101723$4086
+ attribute \src "libresoc.v:101548.3-101566.6"
+ process $proc$libresoc.v:101548$4070
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:101724.5-101724.29"
+ attribute \src "libresoc.v:101549.5-101549.29"
switch \initial
- attribute \src "libresoc.v:101724.9-101724.17"
+ attribute \src "libresoc.v:101549.9-101549.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0]
end
- attribute \src "libresoc.v:101742.3-101760.6"
- process $proc$libresoc.v:101742$4087
+ attribute \src "libresoc.v:101567.3-101585.6"
+ process $proc$libresoc.v:101567$4071
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0]
- attribute \src "libresoc.v:101743.5-101743.29"
+ attribute \src "libresoc.v:101568.5-101568.29"
switch \initial
- attribute \src "libresoc.v:101743.9-101743.17"
+ attribute \src "libresoc.v:101568.9-101568.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:101766.1-102941.10"
+attribute \src "libresoc.v:101591.1-102766.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20"
attribute \generator "nMigen"
module \dec31_dec_sub20
- attribute \src "libresoc.v:102790.3-102814.6"
+ attribute \src "libresoc.v:102615.3-102639.6"
wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:102815.3-102839.6"
+ attribute \src "libresoc.v:102640.3-102664.6"
wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:102490.3-102514.6"
+ attribute \src "libresoc.v:102315.3-102339.6"
wire width 8 $0\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:102590.3-102614.6"
+ attribute \src "libresoc.v:102415.3-102439.6"
wire $0\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:102140.3-102164.6"
+ attribute \src "libresoc.v:101965.3-101989.6"
wire width 3 $0\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:102165.3-102189.6"
+ attribute \src "libresoc.v:101990.3-102014.6"
wire width 3 $0\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:102465.3-102489.6"
+ attribute \src "libresoc.v:102290.3-102314.6"
wire width 2 $0\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:102565.3-102589.6"
+ attribute \src "libresoc.v:102390.3-102414.6"
wire $0\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:102665.3-102689.6"
+ attribute \src "libresoc.v:102490.3-102514.6"
wire width 5 $0\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:102115.3-102139.6"
+ attribute \src "libresoc.v:101940.3-101964.6"
wire width 14 $0\dec31_dec_sub20_function_unit[13:0]
- attribute \src "libresoc.v:102840.3-102864.6"
+ attribute \src "libresoc.v:102665.3-102689.6"
wire width 3 $0\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:102865.3-102889.6"
+ attribute \src "libresoc.v:102690.3-102714.6"
wire width 4 $0\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:102890.3-102914.6"
+ attribute \src "libresoc.v:102715.3-102739.6"
wire width 2 $0\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:102390.3-102414.6"
+ attribute \src "libresoc.v:102215.3-102239.6"
wire width 7 $0\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:102515.3-102539.6"
+ attribute \src "libresoc.v:102340.3-102364.6"
wire $0\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:102540.3-102564.6"
+ attribute \src "libresoc.v:102365.3-102389.6"
wire $0\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:102690.3-102714.6"
+ attribute \src "libresoc.v:102515.3-102539.6"
wire $0\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:102365.3-102389.6"
+ attribute \src "libresoc.v:102190.3-102214.6"
wire width 4 $0\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:102740.3-102764.6"
+ attribute \src "libresoc.v:102565.3-102589.6"
wire $0\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:102915.3-102939.6"
+ attribute \src "libresoc.v:102740.3-102764.6"
wire width 3 $0\dec31_dec_sub20_out_sel[2:0]
- attribute \src "libresoc.v:102440.3-102464.6"
+ attribute \src "libresoc.v:102265.3-102289.6"
wire width 2 $0\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:102640.3-102664.6"
+ attribute \src "libresoc.v:102465.3-102489.6"
wire $0\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:102765.3-102789.6"
+ attribute \src "libresoc.v:102590.3-102614.6"
wire $0\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:102715.3-102739.6"
+ attribute \src "libresoc.v:102540.3-102564.6"
wire $0\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:102615.3-102639.6"
+ attribute \src "libresoc.v:102440.3-102464.6"
wire $0\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:102315.3-102339.6"
+ attribute \src "libresoc.v:102140.3-102164.6"
wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:102340.3-102364.6"
+ attribute \src "libresoc.v:102165.3-102189.6"
wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:102190.3-102214.6"
+ attribute \src "libresoc.v:102015.3-102039.6"
wire width 3 $0\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:102215.3-102239.6"
+ attribute \src "libresoc.v:102040.3-102064.6"
wire width 3 $0\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:102240.3-102264.6"
+ attribute \src "libresoc.v:102065.3-102089.6"
wire width 3 $0\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:102290.3-102314.6"
+ attribute \src "libresoc.v:102115.3-102139.6"
wire width 3 $0\dec31_dec_sub20_sv_out2[2:0]
- attribute \src "libresoc.v:102265.3-102289.6"
+ attribute \src "libresoc.v:102090.3-102114.6"
wire width 3 $0\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:102415.3-102439.6"
+ attribute \src "libresoc.v:102240.3-102264.6"
wire width 2 $0\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:101767.7-101767.20"
+ attribute \src "libresoc.v:101592.7-101592.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:102790.3-102814.6"
+ attribute \src "libresoc.v:102615.3-102639.6"
wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:102815.3-102839.6"
+ attribute \src "libresoc.v:102640.3-102664.6"
wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:102490.3-102514.6"
+ attribute \src "libresoc.v:102315.3-102339.6"
wire width 8 $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:102590.3-102614.6"
+ attribute \src "libresoc.v:102415.3-102439.6"
wire $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:102140.3-102164.6"
+ attribute \src "libresoc.v:101965.3-101989.6"
wire width 3 $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:102165.3-102189.6"
+ attribute \src "libresoc.v:101990.3-102014.6"
wire width 3 $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:102465.3-102489.6"
+ attribute \src "libresoc.v:102290.3-102314.6"
wire width 2 $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:102565.3-102589.6"
+ attribute \src "libresoc.v:102390.3-102414.6"
wire $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:102665.3-102689.6"
+ attribute \src "libresoc.v:102490.3-102514.6"
wire width 5 $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:102115.3-102139.6"
+ attribute \src "libresoc.v:101940.3-101964.6"
wire width 14 $1\dec31_dec_sub20_function_unit[13:0]
- attribute \src "libresoc.v:102840.3-102864.6"
+ attribute \src "libresoc.v:102665.3-102689.6"
wire width 3 $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:102865.3-102889.6"
+ attribute \src "libresoc.v:102690.3-102714.6"
wire width 4 $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:102890.3-102914.6"
+ attribute \src "libresoc.v:102715.3-102739.6"
wire width 2 $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:102390.3-102414.6"
+ attribute \src "libresoc.v:102215.3-102239.6"
wire width 7 $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:102515.3-102539.6"
+ attribute \src "libresoc.v:102340.3-102364.6"
wire $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:102540.3-102564.6"
+ attribute \src "libresoc.v:102365.3-102389.6"
wire $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:102690.3-102714.6"
+ attribute \src "libresoc.v:102515.3-102539.6"
wire $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:102365.3-102389.6"
+ attribute \src "libresoc.v:102190.3-102214.6"
wire width 4 $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:102740.3-102764.6"
+ attribute \src "libresoc.v:102565.3-102589.6"
wire $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:102915.3-102939.6"
+ attribute \src "libresoc.v:102740.3-102764.6"
wire width 3 $1\dec31_dec_sub20_out_sel[2:0]
- attribute \src "libresoc.v:102440.3-102464.6"
+ attribute \src "libresoc.v:102265.3-102289.6"
wire width 2 $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:102640.3-102664.6"
+ attribute \src "libresoc.v:102465.3-102489.6"
wire $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:102765.3-102789.6"
+ attribute \src "libresoc.v:102590.3-102614.6"
wire $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:102715.3-102739.6"
+ attribute \src "libresoc.v:102540.3-102564.6"
wire $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:102615.3-102639.6"
+ attribute \src "libresoc.v:102440.3-102464.6"
wire $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:102315.3-102339.6"
+ attribute \src "libresoc.v:102140.3-102164.6"
wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:102340.3-102364.6"
+ attribute \src "libresoc.v:102165.3-102189.6"
wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:102190.3-102214.6"
+ attribute \src "libresoc.v:102015.3-102039.6"
wire width 3 $1\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:102215.3-102239.6"
+ attribute \src "libresoc.v:102040.3-102064.6"
wire width 3 $1\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:102240.3-102264.6"
+ attribute \src "libresoc.v:102065.3-102089.6"
wire width 3 $1\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:102290.3-102314.6"
+ attribute \src "libresoc.v:102115.3-102139.6"
wire width 3 $1\dec31_dec_sub20_sv_out2[2:0]
- attribute \src "libresoc.v:102265.3-102289.6"
+ attribute \src "libresoc.v:102090.3-102114.6"
wire width 3 $1\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:102415.3-102439.6"
+ attribute \src "libresoc.v:102240.3-102264.6"
wire width 2 $1\dec31_dec_sub20_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub20_upd
- attribute \src "libresoc.v:101767.7-101767.15"
+ attribute \src "libresoc.v:101592.7-101592.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:101767.7-101767.20"
- process $proc$libresoc.v:101767$4122
+ attribute \src "libresoc.v:101592.7-101592.20"
+ process $proc$libresoc.v:101592$4106
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:102115.3-102139.6"
- process $proc$libresoc.v:102115$4089
+ attribute \src "libresoc.v:101940.3-101964.6"
+ process $proc$libresoc.v:101940$4073
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0]
- attribute \src "libresoc.v:102116.5-102116.29"
+ attribute \src "libresoc.v:101941.5-101941.29"
switch \initial
- attribute \src "libresoc.v:102116.9-102116.17"
+ attribute \src "libresoc.v:101941.9-101941.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0]
end
- attribute \src "libresoc.v:102140.3-102164.6"
- process $proc$libresoc.v:102140$4090
+ attribute \src "libresoc.v:101965.3-101989.6"
+ process $proc$libresoc.v:101965$4074
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:102141.5-102141.29"
+ attribute \src "libresoc.v:101966.5-101966.29"
switch \initial
- attribute \src "libresoc.v:102141.9-102141.17"
+ attribute \src "libresoc.v:101966.9-101966.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0]
end
- attribute \src "libresoc.v:102165.3-102189.6"
- process $proc$libresoc.v:102165$4091
+ attribute \src "libresoc.v:101990.3-102014.6"
+ process $proc$libresoc.v:101990$4075
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:102166.5-102166.29"
+ attribute \src "libresoc.v:101991.5-101991.29"
switch \initial
- attribute \src "libresoc.v:102166.9-102166.17"
+ attribute \src "libresoc.v:101991.9-101991.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0]
end
- attribute \src "libresoc.v:102190.3-102214.6"
- process $proc$libresoc.v:102190$4092
+ attribute \src "libresoc.v:102015.3-102039.6"
+ process $proc$libresoc.v:102015$4076
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:102191.5-102191.29"
+ attribute \src "libresoc.v:102016.5-102016.29"
switch \initial
- attribute \src "libresoc.v:102191.9-102191.17"
+ attribute \src "libresoc.v:102016.9-102016.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0]
end
- attribute \src "libresoc.v:102215.3-102239.6"
- process $proc$libresoc.v:102215$4093
+ attribute \src "libresoc.v:102040.3-102064.6"
+ process $proc$libresoc.v:102040$4077
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:102216.5-102216.29"
+ attribute \src "libresoc.v:102041.5-102041.29"
switch \initial
- attribute \src "libresoc.v:102216.9-102216.17"
+ attribute \src "libresoc.v:102041.9-102041.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0]
end
- attribute \src "libresoc.v:102240.3-102264.6"
- process $proc$libresoc.v:102240$4094
+ attribute \src "libresoc.v:102065.3-102089.6"
+ process $proc$libresoc.v:102065$4078
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:102241.5-102241.29"
+ attribute \src "libresoc.v:102066.5-102066.29"
switch \initial
- attribute \src "libresoc.v:102241.9-102241.17"
+ attribute \src "libresoc.v:102066.9-102066.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0]
end
- attribute \src "libresoc.v:102265.3-102289.6"
- process $proc$libresoc.v:102265$4095
+ attribute \src "libresoc.v:102090.3-102114.6"
+ process $proc$libresoc.v:102090$4079
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:102266.5-102266.29"
+ attribute \src "libresoc.v:102091.5-102091.29"
switch \initial
- attribute \src "libresoc.v:102266.9-102266.17"
+ attribute \src "libresoc.v:102091.9-102091.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0]
end
- attribute \src "libresoc.v:102290.3-102314.6"
- process $proc$libresoc.v:102290$4096
+ attribute \src "libresoc.v:102115.3-102139.6"
+ process $proc$libresoc.v:102115$4080
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0]
- attribute \src "libresoc.v:102291.5-102291.29"
+ attribute \src "libresoc.v:102116.5-102116.29"
switch \initial
- attribute \src "libresoc.v:102291.9-102291.17"
+ attribute \src "libresoc.v:102116.9-102116.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0]
end
- attribute \src "libresoc.v:102315.3-102339.6"
- process $proc$libresoc.v:102315$4097
+ attribute \src "libresoc.v:102140.3-102164.6"
+ process $proc$libresoc.v:102140$4081
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:102316.5-102316.29"
+ attribute \src "libresoc.v:102141.5-102141.29"
switch \initial
- attribute \src "libresoc.v:102316.9-102316.17"
+ attribute \src "libresoc.v:102141.9-102141.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:102340.3-102364.6"
- process $proc$libresoc.v:102340$4098
+ attribute \src "libresoc.v:102165.3-102189.6"
+ process $proc$libresoc.v:102165$4082
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:102341.5-102341.29"
+ attribute \src "libresoc.v:102166.5-102166.29"
switch \initial
- attribute \src "libresoc.v:102341.9-102341.17"
+ attribute \src "libresoc.v:102166.9-102166.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:102365.3-102389.6"
- process $proc$libresoc.v:102365$4099
+ attribute \src "libresoc.v:102190.3-102214.6"
+ process $proc$libresoc.v:102190$4083
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:102366.5-102366.29"
+ attribute \src "libresoc.v:102191.5-102191.29"
switch \initial
- attribute \src "libresoc.v:102366.9-102366.17"
+ attribute \src "libresoc.v:102191.9-102191.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0]
end
- attribute \src "libresoc.v:102390.3-102414.6"
- process $proc$libresoc.v:102390$4100
+ attribute \src "libresoc.v:102215.3-102239.6"
+ process $proc$libresoc.v:102215$4084
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:102391.5-102391.29"
+ attribute \src "libresoc.v:102216.5-102216.29"
switch \initial
- attribute \src "libresoc.v:102391.9-102391.17"
+ attribute \src "libresoc.v:102216.9-102216.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0]
end
- attribute \src "libresoc.v:102415.3-102439.6"
- process $proc$libresoc.v:102415$4101
+ attribute \src "libresoc.v:102240.3-102264.6"
+ process $proc$libresoc.v:102240$4085
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:102416.5-102416.29"
+ attribute \src "libresoc.v:102241.5-102241.29"
switch \initial
- attribute \src "libresoc.v:102416.9-102416.17"
+ attribute \src "libresoc.v:102241.9-102241.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0]
end
- attribute \src "libresoc.v:102440.3-102464.6"
- process $proc$libresoc.v:102440$4102
+ attribute \src "libresoc.v:102265.3-102289.6"
+ process $proc$libresoc.v:102265$4086
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:102441.5-102441.29"
+ attribute \src "libresoc.v:102266.5-102266.29"
switch \initial
- attribute \src "libresoc.v:102441.9-102441.17"
+ attribute \src "libresoc.v:102266.9-102266.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0]
end
- attribute \src "libresoc.v:102465.3-102489.6"
- process $proc$libresoc.v:102465$4103
+ attribute \src "libresoc.v:102290.3-102314.6"
+ process $proc$libresoc.v:102290$4087
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:102466.5-102466.29"
+ attribute \src "libresoc.v:102291.5-102291.29"
switch \initial
- attribute \src "libresoc.v:102466.9-102466.17"
+ attribute \src "libresoc.v:102291.9-102291.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0]
end
- attribute \src "libresoc.v:102490.3-102514.6"
- process $proc$libresoc.v:102490$4104
+ attribute \src "libresoc.v:102315.3-102339.6"
+ process $proc$libresoc.v:102315$4088
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:102491.5-102491.29"
+ attribute \src "libresoc.v:102316.5-102316.29"
switch \initial
- attribute \src "libresoc.v:102491.9-102491.17"
+ attribute \src "libresoc.v:102316.9-102316.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0]
end
- attribute \src "libresoc.v:102515.3-102539.6"
- process $proc$libresoc.v:102515$4105
+ attribute \src "libresoc.v:102340.3-102364.6"
+ process $proc$libresoc.v:102340$4089
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:102516.5-102516.29"
+ attribute \src "libresoc.v:102341.5-102341.29"
switch \initial
- attribute \src "libresoc.v:102516.9-102516.17"
+ attribute \src "libresoc.v:102341.9-102341.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0]
end
- attribute \src "libresoc.v:102540.3-102564.6"
- process $proc$libresoc.v:102540$4106
+ attribute \src "libresoc.v:102365.3-102389.6"
+ process $proc$libresoc.v:102365$4090
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:102541.5-102541.29"
+ attribute \src "libresoc.v:102366.5-102366.29"
switch \initial
- attribute \src "libresoc.v:102541.9-102541.17"
+ attribute \src "libresoc.v:102366.9-102366.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0]
end
- attribute \src "libresoc.v:102565.3-102589.6"
- process $proc$libresoc.v:102565$4107
+ attribute \src "libresoc.v:102390.3-102414.6"
+ process $proc$libresoc.v:102390$4091
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:102566.5-102566.29"
+ attribute \src "libresoc.v:102391.5-102391.29"
switch \initial
- attribute \src "libresoc.v:102566.9-102566.17"
+ attribute \src "libresoc.v:102391.9-102391.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0]
end
- attribute \src "libresoc.v:102590.3-102614.6"
- process $proc$libresoc.v:102590$4108
+ attribute \src "libresoc.v:102415.3-102439.6"
+ process $proc$libresoc.v:102415$4092
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:102591.5-102591.29"
+ attribute \src "libresoc.v:102416.5-102416.29"
switch \initial
- attribute \src "libresoc.v:102591.9-102591.17"
+ attribute \src "libresoc.v:102416.9-102416.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0]
end
- attribute \src "libresoc.v:102615.3-102639.6"
- process $proc$libresoc.v:102615$4109
+ attribute \src "libresoc.v:102440.3-102464.6"
+ process $proc$libresoc.v:102440$4093
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:102616.5-102616.29"
+ attribute \src "libresoc.v:102441.5-102441.29"
switch \initial
- attribute \src "libresoc.v:102616.9-102616.17"
+ attribute \src "libresoc.v:102441.9-102441.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0]
end
- attribute \src "libresoc.v:102640.3-102664.6"
- process $proc$libresoc.v:102640$4110
+ attribute \src "libresoc.v:102465.3-102489.6"
+ process $proc$libresoc.v:102465$4094
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:102641.5-102641.29"
+ attribute \src "libresoc.v:102466.5-102466.29"
switch \initial
- attribute \src "libresoc.v:102641.9-102641.17"
+ attribute \src "libresoc.v:102466.9-102466.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0]
end
- attribute \src "libresoc.v:102665.3-102689.6"
- process $proc$libresoc.v:102665$4111
+ attribute \src "libresoc.v:102490.3-102514.6"
+ process $proc$libresoc.v:102490$4095
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:102666.5-102666.29"
+ attribute \src "libresoc.v:102491.5-102491.29"
switch \initial
- attribute \src "libresoc.v:102666.9-102666.17"
+ attribute \src "libresoc.v:102491.9-102491.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0]
end
- attribute \src "libresoc.v:102690.3-102714.6"
- process $proc$libresoc.v:102690$4112
+ attribute \src "libresoc.v:102515.3-102539.6"
+ process $proc$libresoc.v:102515$4096
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:102691.5-102691.29"
+ attribute \src "libresoc.v:102516.5-102516.29"
switch \initial
- attribute \src "libresoc.v:102691.9-102691.17"
+ attribute \src "libresoc.v:102516.9-102516.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0]
end
- attribute \src "libresoc.v:102715.3-102739.6"
- process $proc$libresoc.v:102715$4113
+ attribute \src "libresoc.v:102540.3-102564.6"
+ process $proc$libresoc.v:102540$4097
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:102716.5-102716.29"
+ attribute \src "libresoc.v:102541.5-102541.29"
switch \initial
- attribute \src "libresoc.v:102716.9-102716.17"
+ attribute \src "libresoc.v:102541.9-102541.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0]
end
- attribute \src "libresoc.v:102740.3-102764.6"
- process $proc$libresoc.v:102740$4114
+ attribute \src "libresoc.v:102565.3-102589.6"
+ process $proc$libresoc.v:102565$4098
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:102741.5-102741.29"
+ attribute \src "libresoc.v:102566.5-102566.29"
switch \initial
- attribute \src "libresoc.v:102741.9-102741.17"
+ attribute \src "libresoc.v:102566.9-102566.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0]
end
- attribute \src "libresoc.v:102765.3-102789.6"
- process $proc$libresoc.v:102765$4115
+ attribute \src "libresoc.v:102590.3-102614.6"
+ process $proc$libresoc.v:102590$4099
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:102766.5-102766.29"
+ attribute \src "libresoc.v:102591.5-102591.29"
switch \initial
- attribute \src "libresoc.v:102766.9-102766.17"
+ attribute \src "libresoc.v:102591.9-102591.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:102790.3-102814.6"
- process $proc$libresoc.v:102790$4116
+ attribute \src "libresoc.v:102615.3-102639.6"
+ process $proc$libresoc.v:102615$4100
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:102791.5-102791.29"
+ attribute \src "libresoc.v:102616.5-102616.29"
switch \initial
- attribute \src "libresoc.v:102791.9-102791.17"
+ attribute \src "libresoc.v:102616.9-102616.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0]
end
- attribute \src "libresoc.v:102815.3-102839.6"
- process $proc$libresoc.v:102815$4117
+ attribute \src "libresoc.v:102640.3-102664.6"
+ process $proc$libresoc.v:102640$4101
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:102816.5-102816.29"
+ attribute \src "libresoc.v:102641.5-102641.29"
switch \initial
- attribute \src "libresoc.v:102816.9-102816.17"
+ attribute \src "libresoc.v:102641.9-102641.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:102840.3-102864.6"
- process $proc$libresoc.v:102840$4118
+ attribute \src "libresoc.v:102665.3-102689.6"
+ process $proc$libresoc.v:102665$4102
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:102841.5-102841.29"
+ attribute \src "libresoc.v:102666.5-102666.29"
switch \initial
- attribute \src "libresoc.v:102841.9-102841.17"
+ attribute \src "libresoc.v:102666.9-102666.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0]
end
- attribute \src "libresoc.v:102865.3-102889.6"
- process $proc$libresoc.v:102865$4119
+ attribute \src "libresoc.v:102690.3-102714.6"
+ process $proc$libresoc.v:102690$4103
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:102866.5-102866.29"
+ attribute \src "libresoc.v:102691.5-102691.29"
switch \initial
- attribute \src "libresoc.v:102866.9-102866.17"
+ attribute \src "libresoc.v:102691.9-102691.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0]
end
- attribute \src "libresoc.v:102890.3-102914.6"
- process $proc$libresoc.v:102890$4120
+ attribute \src "libresoc.v:102715.3-102739.6"
+ process $proc$libresoc.v:102715$4104
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:102891.5-102891.29"
+ attribute \src "libresoc.v:102716.5-102716.29"
switch \initial
- attribute \src "libresoc.v:102891.9-102891.17"
+ attribute \src "libresoc.v:102716.9-102716.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0]
end
- attribute \src "libresoc.v:102915.3-102939.6"
- process $proc$libresoc.v:102915$4121
+ attribute \src "libresoc.v:102740.3-102764.6"
+ process $proc$libresoc.v:102740$4105
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0]
- attribute \src "libresoc.v:102916.5-102916.29"
+ attribute \src "libresoc.v:102741.5-102741.29"
switch \initial
- attribute \src "libresoc.v:102916.9-102916.17"
+ attribute \src "libresoc.v:102741.9-102741.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:102945.1-104906.10"
+attribute \src "libresoc.v:102770.1-104731.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21"
attribute \generator "nMigen"
module \dec31_dec_sub21
- attribute \src "libresoc.v:104611.3-104659.6"
+ attribute \src "libresoc.v:104436.3-104484.6"
wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:104660.3-104708.6"
+ attribute \src "libresoc.v:104485.3-104533.6"
wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:104568.3-104610.6"
+ attribute \src "libresoc.v:104393.3-104435.6"
wire width 8 $0\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:104176.3-104224.6"
+ attribute \src "libresoc.v:104001.3-104049.6"
wire $0\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:103343.3-103391.6"
+ attribute \src "libresoc.v:103168.3-103216.6"
wire width 3 $0\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:103392.3-103440.6"
+ attribute \src "libresoc.v:103217.3-103265.6"
wire width 3 $0\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:103980.3-104028.6"
+ attribute \src "libresoc.v:103805.3-103853.6"
wire width 2 $0\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:104127.3-104175.6"
+ attribute \src "libresoc.v:103952.3-104000.6"
wire $0\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:104372.3-104420.6"
+ attribute \src "libresoc.v:104197.3-104245.6"
wire width 5 $0\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:103294.3-103342.6"
+ attribute \src "libresoc.v:103119.3-103167.6"
wire width 14 $0\dec31_dec_sub21_function_unit[13:0]
- attribute \src "libresoc.v:104709.3-104757.6"
+ attribute \src "libresoc.v:104534.3-104582.6"
wire width 3 $0\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:104758.3-104806.6"
+ attribute \src "libresoc.v:104583.3-104631.6"
wire width 4 $0\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:104807.3-104855.6"
+ attribute \src "libresoc.v:104632.3-104680.6"
wire width 2 $0\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:103833.3-103881.6"
+ attribute \src "libresoc.v:103658.3-103706.6"
wire width 7 $0\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:104029.3-104077.6"
+ attribute \src "libresoc.v:103854.3-103902.6"
wire $0\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:104078.3-104126.6"
+ attribute \src "libresoc.v:103903.3-103951.6"
wire $0\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:104323.3-104371.6"
+ attribute \src "libresoc.v:104148.3-104196.6"
wire $0\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:103784.3-103832.6"
+ attribute \src "libresoc.v:103609.3-103657.6"
wire width 4 $0\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:104470.3-104518.6"
+ attribute \src "libresoc.v:104295.3-104343.6"
wire $0\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:104856.3-104904.6"
+ attribute \src "libresoc.v:104681.3-104729.6"
wire width 3 $0\dec31_dec_sub21_out_sel[2:0]
- attribute \src "libresoc.v:103931.3-103979.6"
+ attribute \src "libresoc.v:103756.3-103804.6"
wire width 2 $0\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:104274.3-104322.6"
+ attribute \src "libresoc.v:104099.3-104147.6"
wire $0\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:104519.3-104567.6"
+ attribute \src "libresoc.v:104344.3-104392.6"
wire $0\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:104421.3-104469.6"
+ attribute \src "libresoc.v:104246.3-104294.6"
wire $0\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:104225.3-104273.6"
+ attribute \src "libresoc.v:104050.3-104098.6"
wire $0\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:103686.3-103734.6"
+ attribute \src "libresoc.v:103511.3-103559.6"
wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:103735.3-103783.6"
+ attribute \src "libresoc.v:103560.3-103608.6"
wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:103441.3-103489.6"
+ attribute \src "libresoc.v:103266.3-103314.6"
wire width 3 $0\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:103490.3-103538.6"
+ attribute \src "libresoc.v:103315.3-103363.6"
wire width 3 $0\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:103539.3-103587.6"
+ attribute \src "libresoc.v:103364.3-103412.6"
wire width 3 $0\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:103637.3-103685.6"
+ attribute \src "libresoc.v:103462.3-103510.6"
wire width 3 $0\dec31_dec_sub21_sv_out2[2:0]
- attribute \src "libresoc.v:103588.3-103636.6"
+ attribute \src "libresoc.v:103413.3-103461.6"
wire width 3 $0\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:103882.3-103930.6"
+ attribute \src "libresoc.v:103707.3-103755.6"
wire width 2 $0\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:102946.7-102946.20"
+ attribute \src "libresoc.v:102771.7-102771.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:104611.3-104659.6"
+ attribute \src "libresoc.v:104436.3-104484.6"
wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:104660.3-104708.6"
+ attribute \src "libresoc.v:104485.3-104533.6"
wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:104568.3-104610.6"
+ attribute \src "libresoc.v:104393.3-104435.6"
wire width 8 $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:104176.3-104224.6"
+ attribute \src "libresoc.v:104001.3-104049.6"
wire $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:103343.3-103391.6"
+ attribute \src "libresoc.v:103168.3-103216.6"
wire width 3 $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:103392.3-103440.6"
+ attribute \src "libresoc.v:103217.3-103265.6"
wire width 3 $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:103980.3-104028.6"
+ attribute \src "libresoc.v:103805.3-103853.6"
wire width 2 $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:104127.3-104175.6"
+ attribute \src "libresoc.v:103952.3-104000.6"
wire $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:104372.3-104420.6"
+ attribute \src "libresoc.v:104197.3-104245.6"
wire width 5 $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:103294.3-103342.6"
+ attribute \src "libresoc.v:103119.3-103167.6"
wire width 14 $1\dec31_dec_sub21_function_unit[13:0]
- attribute \src "libresoc.v:104709.3-104757.6"
+ attribute \src "libresoc.v:104534.3-104582.6"
wire width 3 $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:104758.3-104806.6"
+ attribute \src "libresoc.v:104583.3-104631.6"
wire width 4 $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:104807.3-104855.6"
+ attribute \src "libresoc.v:104632.3-104680.6"
wire width 2 $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:103833.3-103881.6"
+ attribute \src "libresoc.v:103658.3-103706.6"
wire width 7 $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:104029.3-104077.6"
+ attribute \src "libresoc.v:103854.3-103902.6"
wire $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:104078.3-104126.6"
+ attribute \src "libresoc.v:103903.3-103951.6"
wire $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:104323.3-104371.6"
+ attribute \src "libresoc.v:104148.3-104196.6"
wire $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:103784.3-103832.6"
+ attribute \src "libresoc.v:103609.3-103657.6"
wire width 4 $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:104470.3-104518.6"
+ attribute \src "libresoc.v:104295.3-104343.6"
wire $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:104856.3-104904.6"
+ attribute \src "libresoc.v:104681.3-104729.6"
wire width 3 $1\dec31_dec_sub21_out_sel[2:0]
- attribute \src "libresoc.v:103931.3-103979.6"
+ attribute \src "libresoc.v:103756.3-103804.6"
wire width 2 $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:104274.3-104322.6"
+ attribute \src "libresoc.v:104099.3-104147.6"
wire $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:104519.3-104567.6"
+ attribute \src "libresoc.v:104344.3-104392.6"
wire $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:104421.3-104469.6"
+ attribute \src "libresoc.v:104246.3-104294.6"
wire $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:104225.3-104273.6"
+ attribute \src "libresoc.v:104050.3-104098.6"
wire $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:103686.3-103734.6"
+ attribute \src "libresoc.v:103511.3-103559.6"
wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:103735.3-103783.6"
+ attribute \src "libresoc.v:103560.3-103608.6"
wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:103441.3-103489.6"
+ attribute \src "libresoc.v:103266.3-103314.6"
wire width 3 $1\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:103490.3-103538.6"
+ attribute \src "libresoc.v:103315.3-103363.6"
wire width 3 $1\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:103539.3-103587.6"
+ attribute \src "libresoc.v:103364.3-103412.6"
wire width 3 $1\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:103637.3-103685.6"
+ attribute \src "libresoc.v:103462.3-103510.6"
wire width 3 $1\dec31_dec_sub21_sv_out2[2:0]
- attribute \src "libresoc.v:103588.3-103636.6"
+ attribute \src "libresoc.v:103413.3-103461.6"
wire width 3 $1\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:103882.3-103930.6"
+ attribute \src "libresoc.v:103707.3-103755.6"
wire width 2 $1\dec31_dec_sub21_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub21_upd
- attribute \src "libresoc.v:102946.7-102946.15"
+ attribute \src "libresoc.v:102771.7-102771.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:102946.7-102946.20"
- process $proc$libresoc.v:102946$4156
+ attribute \src "libresoc.v:102771.7-102771.20"
+ process $proc$libresoc.v:102771$4140
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:103294.3-103342.6"
- process $proc$libresoc.v:103294$4123
+ attribute \src "libresoc.v:103119.3-103167.6"
+ process $proc$libresoc.v:103119$4107
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0]
- attribute \src "libresoc.v:103295.5-103295.29"
+ attribute \src "libresoc.v:103120.5-103120.29"
switch \initial
- attribute \src "libresoc.v:103295.9-103295.17"
+ attribute \src "libresoc.v:103120.9-103120.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0]
end
- attribute \src "libresoc.v:103343.3-103391.6"
- process $proc$libresoc.v:103343$4124
+ attribute \src "libresoc.v:103168.3-103216.6"
+ process $proc$libresoc.v:103168$4108
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:103344.5-103344.29"
+ attribute \src "libresoc.v:103169.5-103169.29"
switch \initial
- attribute \src "libresoc.v:103344.9-103344.17"
+ attribute \src "libresoc.v:103169.9-103169.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0]
end
- attribute \src "libresoc.v:103392.3-103440.6"
- process $proc$libresoc.v:103392$4125
+ attribute \src "libresoc.v:103217.3-103265.6"
+ process $proc$libresoc.v:103217$4109
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:103393.5-103393.29"
+ attribute \src "libresoc.v:103218.5-103218.29"
switch \initial
- attribute \src "libresoc.v:103393.9-103393.17"
+ attribute \src "libresoc.v:103218.9-103218.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0]
end
- attribute \src "libresoc.v:103441.3-103489.6"
- process $proc$libresoc.v:103441$4126
+ attribute \src "libresoc.v:103266.3-103314.6"
+ process $proc$libresoc.v:103266$4110
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:103442.5-103442.29"
+ attribute \src "libresoc.v:103267.5-103267.29"
switch \initial
- attribute \src "libresoc.v:103442.9-103442.17"
+ attribute \src "libresoc.v:103267.9-103267.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0]
end
- attribute \src "libresoc.v:103490.3-103538.6"
- process $proc$libresoc.v:103490$4127
+ attribute \src "libresoc.v:103315.3-103363.6"
+ process $proc$libresoc.v:103315$4111
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:103491.5-103491.29"
+ attribute \src "libresoc.v:103316.5-103316.29"
switch \initial
- attribute \src "libresoc.v:103491.9-103491.17"
+ attribute \src "libresoc.v:103316.9-103316.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0]
end
- attribute \src "libresoc.v:103539.3-103587.6"
- process $proc$libresoc.v:103539$4128
+ attribute \src "libresoc.v:103364.3-103412.6"
+ process $proc$libresoc.v:103364$4112
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:103540.5-103540.29"
+ attribute \src "libresoc.v:103365.5-103365.29"
switch \initial
- attribute \src "libresoc.v:103540.9-103540.17"
+ attribute \src "libresoc.v:103365.9-103365.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0]
end
- attribute \src "libresoc.v:103588.3-103636.6"
- process $proc$libresoc.v:103588$4129
+ attribute \src "libresoc.v:103413.3-103461.6"
+ process $proc$libresoc.v:103413$4113
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:103589.5-103589.29"
+ attribute \src "libresoc.v:103414.5-103414.29"
switch \initial
- attribute \src "libresoc.v:103589.9-103589.17"
+ attribute \src "libresoc.v:103414.9-103414.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0]
end
- attribute \src "libresoc.v:103637.3-103685.6"
- process $proc$libresoc.v:103637$4130
+ attribute \src "libresoc.v:103462.3-103510.6"
+ process $proc$libresoc.v:103462$4114
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0]
- attribute \src "libresoc.v:103638.5-103638.29"
+ attribute \src "libresoc.v:103463.5-103463.29"
switch \initial
- attribute \src "libresoc.v:103638.9-103638.17"
+ attribute \src "libresoc.v:103463.9-103463.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0]
end
- attribute \src "libresoc.v:103686.3-103734.6"
- process $proc$libresoc.v:103686$4131
+ attribute \src "libresoc.v:103511.3-103559.6"
+ process $proc$libresoc.v:103511$4115
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:103687.5-103687.29"
+ attribute \src "libresoc.v:103512.5-103512.29"
switch \initial
- attribute \src "libresoc.v:103687.9-103687.17"
+ attribute \src "libresoc.v:103512.9-103512.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:103735.3-103783.6"
- process $proc$libresoc.v:103735$4132
+ attribute \src "libresoc.v:103560.3-103608.6"
+ process $proc$libresoc.v:103560$4116
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:103736.5-103736.29"
+ attribute \src "libresoc.v:103561.5-103561.29"
switch \initial
- attribute \src "libresoc.v:103736.9-103736.17"
+ attribute \src "libresoc.v:103561.9-103561.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:103784.3-103832.6"
- process $proc$libresoc.v:103784$4133
+ attribute \src "libresoc.v:103609.3-103657.6"
+ process $proc$libresoc.v:103609$4117
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:103785.5-103785.29"
+ attribute \src "libresoc.v:103610.5-103610.29"
switch \initial
- attribute \src "libresoc.v:103785.9-103785.17"
+ attribute \src "libresoc.v:103610.9-103610.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0]
end
- attribute \src "libresoc.v:103833.3-103881.6"
- process $proc$libresoc.v:103833$4134
+ attribute \src "libresoc.v:103658.3-103706.6"
+ process $proc$libresoc.v:103658$4118
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:103834.5-103834.29"
+ attribute \src "libresoc.v:103659.5-103659.29"
switch \initial
- attribute \src "libresoc.v:103834.9-103834.17"
+ attribute \src "libresoc.v:103659.9-103659.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0]
end
- attribute \src "libresoc.v:103882.3-103930.6"
- process $proc$libresoc.v:103882$4135
+ attribute \src "libresoc.v:103707.3-103755.6"
+ process $proc$libresoc.v:103707$4119
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:103883.5-103883.29"
+ attribute \src "libresoc.v:103708.5-103708.29"
switch \initial
- attribute \src "libresoc.v:103883.9-103883.17"
+ attribute \src "libresoc.v:103708.9-103708.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0]
end
- attribute \src "libresoc.v:103931.3-103979.6"
- process $proc$libresoc.v:103931$4136
+ attribute \src "libresoc.v:103756.3-103804.6"
+ process $proc$libresoc.v:103756$4120
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:103932.5-103932.29"
+ attribute \src "libresoc.v:103757.5-103757.29"
switch \initial
- attribute \src "libresoc.v:103932.9-103932.17"
+ attribute \src "libresoc.v:103757.9-103757.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0]
end
- attribute \src "libresoc.v:103980.3-104028.6"
- process $proc$libresoc.v:103980$4137
+ attribute \src "libresoc.v:103805.3-103853.6"
+ process $proc$libresoc.v:103805$4121
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:103981.5-103981.29"
+ attribute \src "libresoc.v:103806.5-103806.29"
switch \initial
- attribute \src "libresoc.v:103981.9-103981.17"
+ attribute \src "libresoc.v:103806.9-103806.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0]
end
- attribute \src "libresoc.v:104029.3-104077.6"
- process $proc$libresoc.v:104029$4138
+ attribute \src "libresoc.v:103854.3-103902.6"
+ process $proc$libresoc.v:103854$4122
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:104030.5-104030.29"
+ attribute \src "libresoc.v:103855.5-103855.29"
switch \initial
- attribute \src "libresoc.v:104030.9-104030.17"
+ attribute \src "libresoc.v:103855.9-103855.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0]
end
- attribute \src "libresoc.v:104078.3-104126.6"
- process $proc$libresoc.v:104078$4139
+ attribute \src "libresoc.v:103903.3-103951.6"
+ process $proc$libresoc.v:103903$4123
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:104079.5-104079.29"
+ attribute \src "libresoc.v:103904.5-103904.29"
switch \initial
- attribute \src "libresoc.v:104079.9-104079.17"
+ attribute \src "libresoc.v:103904.9-103904.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0]
end
- attribute \src "libresoc.v:104127.3-104175.6"
- process $proc$libresoc.v:104127$4140
+ attribute \src "libresoc.v:103952.3-104000.6"
+ process $proc$libresoc.v:103952$4124
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:104128.5-104128.29"
+ attribute \src "libresoc.v:103953.5-103953.29"
switch \initial
- attribute \src "libresoc.v:104128.9-104128.17"
+ attribute \src "libresoc.v:103953.9-103953.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0]
end
- attribute \src "libresoc.v:104176.3-104224.6"
- process $proc$libresoc.v:104176$4141
+ attribute \src "libresoc.v:104001.3-104049.6"
+ process $proc$libresoc.v:104001$4125
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:104177.5-104177.29"
+ attribute \src "libresoc.v:104002.5-104002.29"
switch \initial
- attribute \src "libresoc.v:104177.9-104177.17"
+ attribute \src "libresoc.v:104002.9-104002.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0]
end
- attribute \src "libresoc.v:104225.3-104273.6"
- process $proc$libresoc.v:104225$4142
+ attribute \src "libresoc.v:104050.3-104098.6"
+ process $proc$libresoc.v:104050$4126
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:104226.5-104226.29"
+ attribute \src "libresoc.v:104051.5-104051.29"
switch \initial
- attribute \src "libresoc.v:104226.9-104226.17"
+ attribute \src "libresoc.v:104051.9-104051.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0]
end
- attribute \src "libresoc.v:104274.3-104322.6"
- process $proc$libresoc.v:104274$4143
+ attribute \src "libresoc.v:104099.3-104147.6"
+ process $proc$libresoc.v:104099$4127
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:104275.5-104275.29"
+ attribute \src "libresoc.v:104100.5-104100.29"
switch \initial
- attribute \src "libresoc.v:104275.9-104275.17"
+ attribute \src "libresoc.v:104100.9-104100.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0]
end
- attribute \src "libresoc.v:104323.3-104371.6"
- process $proc$libresoc.v:104323$4144
+ attribute \src "libresoc.v:104148.3-104196.6"
+ process $proc$libresoc.v:104148$4128
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:104324.5-104324.29"
+ attribute \src "libresoc.v:104149.5-104149.29"
switch \initial
- attribute \src "libresoc.v:104324.9-104324.17"
+ attribute \src "libresoc.v:104149.9-104149.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0]
end
- attribute \src "libresoc.v:104372.3-104420.6"
- process $proc$libresoc.v:104372$4145
+ attribute \src "libresoc.v:104197.3-104245.6"
+ process $proc$libresoc.v:104197$4129
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:104373.5-104373.29"
+ attribute \src "libresoc.v:104198.5-104198.29"
switch \initial
- attribute \src "libresoc.v:104373.9-104373.17"
+ attribute \src "libresoc.v:104198.9-104198.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0]
end
- attribute \src "libresoc.v:104421.3-104469.6"
- process $proc$libresoc.v:104421$4146
+ attribute \src "libresoc.v:104246.3-104294.6"
+ process $proc$libresoc.v:104246$4130
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:104422.5-104422.29"
+ attribute \src "libresoc.v:104247.5-104247.29"
switch \initial
- attribute \src "libresoc.v:104422.9-104422.17"
+ attribute \src "libresoc.v:104247.9-104247.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0]
end
- attribute \src "libresoc.v:104470.3-104518.6"
- process $proc$libresoc.v:104470$4147
+ attribute \src "libresoc.v:104295.3-104343.6"
+ process $proc$libresoc.v:104295$4131
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:104471.5-104471.29"
+ attribute \src "libresoc.v:104296.5-104296.29"
switch \initial
- attribute \src "libresoc.v:104471.9-104471.17"
+ attribute \src "libresoc.v:104296.9-104296.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0]
end
- attribute \src "libresoc.v:104519.3-104567.6"
- process $proc$libresoc.v:104519$4148
+ attribute \src "libresoc.v:104344.3-104392.6"
+ process $proc$libresoc.v:104344$4132
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:104520.5-104520.29"
+ attribute \src "libresoc.v:104345.5-104345.29"
switch \initial
- attribute \src "libresoc.v:104520.9-104520.17"
+ attribute \src "libresoc.v:104345.9-104345.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:104568.3-104610.6"
- process $proc$libresoc.v:104568$4149
+ attribute \src "libresoc.v:104393.3-104435.6"
+ process $proc$libresoc.v:104393$4133
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:104569.5-104569.29"
+ attribute \src "libresoc.v:104394.5-104394.29"
switch \initial
- attribute \src "libresoc.v:104569.9-104569.17"
+ attribute \src "libresoc.v:104394.9-104394.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0]
end
- attribute \src "libresoc.v:104611.3-104659.6"
- process $proc$libresoc.v:104611$4150
+ attribute \src "libresoc.v:104436.3-104484.6"
+ process $proc$libresoc.v:104436$4134
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:104612.5-104612.29"
+ attribute \src "libresoc.v:104437.5-104437.29"
switch \initial
- attribute \src "libresoc.v:104612.9-104612.17"
+ attribute \src "libresoc.v:104437.9-104437.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0]
end
- attribute \src "libresoc.v:104660.3-104708.6"
- process $proc$libresoc.v:104660$4151
+ attribute \src "libresoc.v:104485.3-104533.6"
+ process $proc$libresoc.v:104485$4135
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:104661.5-104661.29"
+ attribute \src "libresoc.v:104486.5-104486.29"
switch \initial
- attribute \src "libresoc.v:104661.9-104661.17"
+ attribute \src "libresoc.v:104486.9-104486.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:104709.3-104757.6"
- process $proc$libresoc.v:104709$4152
+ attribute \src "libresoc.v:104534.3-104582.6"
+ process $proc$libresoc.v:104534$4136
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:104710.5-104710.29"
+ attribute \src "libresoc.v:104535.5-104535.29"
switch \initial
- attribute \src "libresoc.v:104710.9-104710.17"
+ attribute \src "libresoc.v:104535.9-104535.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0]
end
- attribute \src "libresoc.v:104758.3-104806.6"
- process $proc$libresoc.v:104758$4153
+ attribute \src "libresoc.v:104583.3-104631.6"
+ process $proc$libresoc.v:104583$4137
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:104759.5-104759.29"
+ attribute \src "libresoc.v:104584.5-104584.29"
switch \initial
- attribute \src "libresoc.v:104759.9-104759.17"
+ attribute \src "libresoc.v:104584.9-104584.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0]
end
- attribute \src "libresoc.v:104807.3-104855.6"
- process $proc$libresoc.v:104807$4154
+ attribute \src "libresoc.v:104632.3-104680.6"
+ process $proc$libresoc.v:104632$4138
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:104808.5-104808.29"
+ attribute \src "libresoc.v:104633.5-104633.29"
switch \initial
- attribute \src "libresoc.v:104808.9-104808.17"
+ attribute \src "libresoc.v:104633.9-104633.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0]
end
- attribute \src "libresoc.v:104856.3-104904.6"
- process $proc$libresoc.v:104856$4155
+ attribute \src "libresoc.v:104681.3-104729.6"
+ process $proc$libresoc.v:104681$4139
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0]
- attribute \src "libresoc.v:104857.5-104857.29"
+ attribute \src "libresoc.v:104682.5-104682.29"
switch \initial
- attribute \src "libresoc.v:104857.9-104857.17"
+ attribute \src "libresoc.v:104682.9-104682.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:104910.1-107075.10"
+attribute \src "libresoc.v:104735.1-106900.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22"
attribute \generator "nMigen"
module \dec31_dec_sub22
- attribute \src "libresoc.v:106744.3-106798.6"
+ attribute \src "libresoc.v:106569.3-106623.6"
wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:106799.3-106853.6"
+ attribute \src "libresoc.v:106624.3-106678.6"
wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:106084.3-106138.6"
+ attribute \src "libresoc.v:105909.3-105963.6"
wire width 8 $0\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:106304.3-106358.6"
+ attribute \src "libresoc.v:106129.3-106183.6"
wire $0\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:105314.3-105368.6"
+ attribute \src "libresoc.v:105139.3-105193.6"
wire width 3 $0\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:105369.3-105423.6"
+ attribute \src "libresoc.v:105194.3-105248.6"
wire width 3 $0\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:106029.3-106083.6"
+ attribute \src "libresoc.v:105854.3-105908.6"
wire width 2 $0\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:106249.3-106303.6"
+ attribute \src "libresoc.v:106074.3-106128.6"
wire $0\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:106469.3-106523.6"
+ attribute \src "libresoc.v:106294.3-106348.6"
wire width 5 $0\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:105259.3-105313.6"
+ attribute \src "libresoc.v:105084.3-105138.6"
wire width 14 $0\dec31_dec_sub22_function_unit[13:0]
- attribute \src "libresoc.v:106854.3-106908.6"
+ attribute \src "libresoc.v:106679.3-106733.6"
wire width 3 $0\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:106909.3-106963.6"
+ attribute \src "libresoc.v:106734.3-106788.6"
wire width 4 $0\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:106964.3-107018.6"
+ attribute \src "libresoc.v:106789.3-106843.6"
wire width 2 $0\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:105864.3-105918.6"
+ attribute \src "libresoc.v:105689.3-105743.6"
wire width 7 $0\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:106139.3-106193.6"
+ attribute \src "libresoc.v:105964.3-106018.6"
wire $0\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:106194.3-106248.6"
+ attribute \src "libresoc.v:106019.3-106073.6"
wire $0\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:106524.3-106578.6"
+ attribute \src "libresoc.v:106349.3-106403.6"
wire $0\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:105809.3-105863.6"
+ attribute \src "libresoc.v:105634.3-105688.6"
wire width 4 $0\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:106634.3-106688.6"
+ attribute \src "libresoc.v:106459.3-106513.6"
wire $0\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:107019.3-107073.6"
+ attribute \src "libresoc.v:106844.3-106898.6"
wire width 3 $0\dec31_dec_sub22_out_sel[2:0]
- attribute \src "libresoc.v:105974.3-106028.6"
+ attribute \src "libresoc.v:105799.3-105853.6"
wire width 2 $0\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:106414.3-106468.6"
+ attribute \src "libresoc.v:106239.3-106293.6"
wire $0\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:106689.3-106743.6"
+ attribute \src "libresoc.v:106514.3-106568.6"
wire $0\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:106579.3-106633.6"
+ attribute \src "libresoc.v:106404.3-106458.6"
wire $0\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:106359.3-106413.6"
+ attribute \src "libresoc.v:106184.3-106238.6"
wire $0\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:105699.3-105753.6"
+ attribute \src "libresoc.v:105524.3-105578.6"
wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:105754.3-105808.6"
+ attribute \src "libresoc.v:105579.3-105633.6"
wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:105424.3-105478.6"
+ attribute \src "libresoc.v:105249.3-105303.6"
wire width 3 $0\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:105479.3-105533.6"
+ attribute \src "libresoc.v:105304.3-105358.6"
wire width 3 $0\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:105534.3-105588.6"
+ attribute \src "libresoc.v:105359.3-105413.6"
wire width 3 $0\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:105644.3-105698.6"
+ attribute \src "libresoc.v:105469.3-105523.6"
wire width 3 $0\dec31_dec_sub22_sv_out2[2:0]
- attribute \src "libresoc.v:105589.3-105643.6"
+ attribute \src "libresoc.v:105414.3-105468.6"
wire width 3 $0\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:105919.3-105973.6"
+ attribute \src "libresoc.v:105744.3-105798.6"
wire width 2 $0\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:104911.7-104911.20"
+ attribute \src "libresoc.v:104736.7-104736.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:106744.3-106798.6"
+ attribute \src "libresoc.v:106569.3-106623.6"
wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:106799.3-106853.6"
+ attribute \src "libresoc.v:106624.3-106678.6"
wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:106084.3-106138.6"
+ attribute \src "libresoc.v:105909.3-105963.6"
wire width 8 $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:106304.3-106358.6"
+ attribute \src "libresoc.v:106129.3-106183.6"
wire $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:105314.3-105368.6"
+ attribute \src "libresoc.v:105139.3-105193.6"
wire width 3 $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:105369.3-105423.6"
+ attribute \src "libresoc.v:105194.3-105248.6"
wire width 3 $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:106029.3-106083.6"
+ attribute \src "libresoc.v:105854.3-105908.6"
wire width 2 $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:106249.3-106303.6"
+ attribute \src "libresoc.v:106074.3-106128.6"
wire $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:106469.3-106523.6"
+ attribute \src "libresoc.v:106294.3-106348.6"
wire width 5 $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:105259.3-105313.6"
+ attribute \src "libresoc.v:105084.3-105138.6"
wire width 14 $1\dec31_dec_sub22_function_unit[13:0]
- attribute \src "libresoc.v:106854.3-106908.6"
+ attribute \src "libresoc.v:106679.3-106733.6"
wire width 3 $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:106909.3-106963.6"
+ attribute \src "libresoc.v:106734.3-106788.6"
wire width 4 $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:106964.3-107018.6"
+ attribute \src "libresoc.v:106789.3-106843.6"
wire width 2 $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:105864.3-105918.6"
+ attribute \src "libresoc.v:105689.3-105743.6"
wire width 7 $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:106139.3-106193.6"
+ attribute \src "libresoc.v:105964.3-106018.6"
wire $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:106194.3-106248.6"
+ attribute \src "libresoc.v:106019.3-106073.6"
wire $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:106524.3-106578.6"
+ attribute \src "libresoc.v:106349.3-106403.6"
wire $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:105809.3-105863.6"
+ attribute \src "libresoc.v:105634.3-105688.6"
wire width 4 $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:106634.3-106688.6"
+ attribute \src "libresoc.v:106459.3-106513.6"
wire $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:107019.3-107073.6"
+ attribute \src "libresoc.v:106844.3-106898.6"
wire width 3 $1\dec31_dec_sub22_out_sel[2:0]
- attribute \src "libresoc.v:105974.3-106028.6"
+ attribute \src "libresoc.v:105799.3-105853.6"
wire width 2 $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:106414.3-106468.6"
+ attribute \src "libresoc.v:106239.3-106293.6"
wire $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:106689.3-106743.6"
+ attribute \src "libresoc.v:106514.3-106568.6"
wire $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:106579.3-106633.6"
+ attribute \src "libresoc.v:106404.3-106458.6"
wire $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:106359.3-106413.6"
+ attribute \src "libresoc.v:106184.3-106238.6"
wire $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:105699.3-105753.6"
+ attribute \src "libresoc.v:105524.3-105578.6"
wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:105754.3-105808.6"
+ attribute \src "libresoc.v:105579.3-105633.6"
wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:105424.3-105478.6"
+ attribute \src "libresoc.v:105249.3-105303.6"
wire width 3 $1\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:105479.3-105533.6"
+ attribute \src "libresoc.v:105304.3-105358.6"
wire width 3 $1\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:105534.3-105588.6"
+ attribute \src "libresoc.v:105359.3-105413.6"
wire width 3 $1\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:105644.3-105698.6"
+ attribute \src "libresoc.v:105469.3-105523.6"
wire width 3 $1\dec31_dec_sub22_sv_out2[2:0]
- attribute \src "libresoc.v:105589.3-105643.6"
+ attribute \src "libresoc.v:105414.3-105468.6"
wire width 3 $1\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:105919.3-105973.6"
+ attribute \src "libresoc.v:105744.3-105798.6"
wire width 2 $1\dec31_dec_sub22_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub22_upd
- attribute \src "libresoc.v:104911.7-104911.15"
+ attribute \src "libresoc.v:104736.7-104736.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:104911.7-104911.20"
- process $proc$libresoc.v:104911$4190
+ attribute \src "libresoc.v:104736.7-104736.20"
+ process $proc$libresoc.v:104736$4174
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:105259.3-105313.6"
- process $proc$libresoc.v:105259$4157
+ attribute \src "libresoc.v:105084.3-105138.6"
+ process $proc$libresoc.v:105084$4141
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0]
- attribute \src "libresoc.v:105260.5-105260.29"
+ attribute \src "libresoc.v:105085.5-105085.29"
switch \initial
- attribute \src "libresoc.v:105260.9-105260.17"
+ attribute \src "libresoc.v:105085.9-105085.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0]
end
- attribute \src "libresoc.v:105314.3-105368.6"
- process $proc$libresoc.v:105314$4158
+ attribute \src "libresoc.v:105139.3-105193.6"
+ process $proc$libresoc.v:105139$4142
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:105315.5-105315.29"
+ attribute \src "libresoc.v:105140.5-105140.29"
switch \initial
- attribute \src "libresoc.v:105315.9-105315.17"
+ attribute \src "libresoc.v:105140.9-105140.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0]
end
- attribute \src "libresoc.v:105369.3-105423.6"
- process $proc$libresoc.v:105369$4159
+ attribute \src "libresoc.v:105194.3-105248.6"
+ process $proc$libresoc.v:105194$4143
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:105370.5-105370.29"
+ attribute \src "libresoc.v:105195.5-105195.29"
switch \initial
- attribute \src "libresoc.v:105370.9-105370.17"
+ attribute \src "libresoc.v:105195.9-105195.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0]
end
- attribute \src "libresoc.v:105424.3-105478.6"
- process $proc$libresoc.v:105424$4160
+ attribute \src "libresoc.v:105249.3-105303.6"
+ process $proc$libresoc.v:105249$4144
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:105425.5-105425.29"
+ attribute \src "libresoc.v:105250.5-105250.29"
switch \initial
- attribute \src "libresoc.v:105425.9-105425.17"
+ attribute \src "libresoc.v:105250.9-105250.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0]
end
- attribute \src "libresoc.v:105479.3-105533.6"
- process $proc$libresoc.v:105479$4161
+ attribute \src "libresoc.v:105304.3-105358.6"
+ process $proc$libresoc.v:105304$4145
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:105480.5-105480.29"
+ attribute \src "libresoc.v:105305.5-105305.29"
switch \initial
- attribute \src "libresoc.v:105480.9-105480.17"
+ attribute \src "libresoc.v:105305.9-105305.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0]
end
- attribute \src "libresoc.v:105534.3-105588.6"
- process $proc$libresoc.v:105534$4162
+ attribute \src "libresoc.v:105359.3-105413.6"
+ process $proc$libresoc.v:105359$4146
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:105535.5-105535.29"
+ attribute \src "libresoc.v:105360.5-105360.29"
switch \initial
- attribute \src "libresoc.v:105535.9-105535.17"
+ attribute \src "libresoc.v:105360.9-105360.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0]
end
- attribute \src "libresoc.v:105589.3-105643.6"
- process $proc$libresoc.v:105589$4163
+ attribute \src "libresoc.v:105414.3-105468.6"
+ process $proc$libresoc.v:105414$4147
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:105590.5-105590.29"
+ attribute \src "libresoc.v:105415.5-105415.29"
switch \initial
- attribute \src "libresoc.v:105590.9-105590.17"
+ attribute \src "libresoc.v:105415.9-105415.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0]
end
- attribute \src "libresoc.v:105644.3-105698.6"
- process $proc$libresoc.v:105644$4164
+ attribute \src "libresoc.v:105469.3-105523.6"
+ process $proc$libresoc.v:105469$4148
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0]
- attribute \src "libresoc.v:105645.5-105645.29"
+ attribute \src "libresoc.v:105470.5-105470.29"
switch \initial
- attribute \src "libresoc.v:105645.9-105645.17"
+ attribute \src "libresoc.v:105470.9-105470.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0]
end
- attribute \src "libresoc.v:105699.3-105753.6"
- process $proc$libresoc.v:105699$4165
+ attribute \src "libresoc.v:105524.3-105578.6"
+ process $proc$libresoc.v:105524$4149
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:105700.5-105700.29"
+ attribute \src "libresoc.v:105525.5-105525.29"
switch \initial
- attribute \src "libresoc.v:105700.9-105700.17"
+ attribute \src "libresoc.v:105525.9-105525.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:105754.3-105808.6"
- process $proc$libresoc.v:105754$4166
+ attribute \src "libresoc.v:105579.3-105633.6"
+ process $proc$libresoc.v:105579$4150
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:105755.5-105755.29"
+ attribute \src "libresoc.v:105580.5-105580.29"
switch \initial
- attribute \src "libresoc.v:105755.9-105755.17"
+ attribute \src "libresoc.v:105580.9-105580.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:105809.3-105863.6"
- process $proc$libresoc.v:105809$4167
+ attribute \src "libresoc.v:105634.3-105688.6"
+ process $proc$libresoc.v:105634$4151
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:105810.5-105810.29"
+ attribute \src "libresoc.v:105635.5-105635.29"
switch \initial
- attribute \src "libresoc.v:105810.9-105810.17"
+ attribute \src "libresoc.v:105635.9-105635.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0]
end
- attribute \src "libresoc.v:105864.3-105918.6"
- process $proc$libresoc.v:105864$4168
+ attribute \src "libresoc.v:105689.3-105743.6"
+ process $proc$libresoc.v:105689$4152
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:105865.5-105865.29"
+ attribute \src "libresoc.v:105690.5-105690.29"
switch \initial
- attribute \src "libresoc.v:105865.9-105865.17"
+ attribute \src "libresoc.v:105690.9-105690.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0]
end
- attribute \src "libresoc.v:105919.3-105973.6"
- process $proc$libresoc.v:105919$4169
+ attribute \src "libresoc.v:105744.3-105798.6"
+ process $proc$libresoc.v:105744$4153
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:105920.5-105920.29"
+ attribute \src "libresoc.v:105745.5-105745.29"
switch \initial
- attribute \src "libresoc.v:105920.9-105920.17"
+ attribute \src "libresoc.v:105745.9-105745.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0]
end
- attribute \src "libresoc.v:105974.3-106028.6"
- process $proc$libresoc.v:105974$4170
+ attribute \src "libresoc.v:105799.3-105853.6"
+ process $proc$libresoc.v:105799$4154
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:105975.5-105975.29"
+ attribute \src "libresoc.v:105800.5-105800.29"
switch \initial
- attribute \src "libresoc.v:105975.9-105975.17"
+ attribute \src "libresoc.v:105800.9-105800.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0]
end
- attribute \src "libresoc.v:106029.3-106083.6"
- process $proc$libresoc.v:106029$4171
+ attribute \src "libresoc.v:105854.3-105908.6"
+ process $proc$libresoc.v:105854$4155
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:106030.5-106030.29"
+ attribute \src "libresoc.v:105855.5-105855.29"
switch \initial
- attribute \src "libresoc.v:106030.9-106030.17"
+ attribute \src "libresoc.v:105855.9-105855.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0]
end
- attribute \src "libresoc.v:106084.3-106138.6"
- process $proc$libresoc.v:106084$4172
+ attribute \src "libresoc.v:105909.3-105963.6"
+ process $proc$libresoc.v:105909$4156
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:106085.5-106085.29"
+ attribute \src "libresoc.v:105910.5-105910.29"
switch \initial
- attribute \src "libresoc.v:106085.9-106085.17"
+ attribute \src "libresoc.v:105910.9-105910.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0]
end
- attribute \src "libresoc.v:106139.3-106193.6"
- process $proc$libresoc.v:106139$4173
+ attribute \src "libresoc.v:105964.3-106018.6"
+ process $proc$libresoc.v:105964$4157
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:106140.5-106140.29"
+ attribute \src "libresoc.v:105965.5-105965.29"
switch \initial
- attribute \src "libresoc.v:106140.9-106140.17"
+ attribute \src "libresoc.v:105965.9-105965.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0]
end
- attribute \src "libresoc.v:106194.3-106248.6"
- process $proc$libresoc.v:106194$4174
+ attribute \src "libresoc.v:106019.3-106073.6"
+ process $proc$libresoc.v:106019$4158
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:106195.5-106195.29"
+ attribute \src "libresoc.v:106020.5-106020.29"
switch \initial
- attribute \src "libresoc.v:106195.9-106195.17"
+ attribute \src "libresoc.v:106020.9-106020.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0]
end
- attribute \src "libresoc.v:106249.3-106303.6"
- process $proc$libresoc.v:106249$4175
+ attribute \src "libresoc.v:106074.3-106128.6"
+ process $proc$libresoc.v:106074$4159
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:106250.5-106250.29"
+ attribute \src "libresoc.v:106075.5-106075.29"
switch \initial
- attribute \src "libresoc.v:106250.9-106250.17"
+ attribute \src "libresoc.v:106075.9-106075.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0]
end
- attribute \src "libresoc.v:106304.3-106358.6"
- process $proc$libresoc.v:106304$4176
+ attribute \src "libresoc.v:106129.3-106183.6"
+ process $proc$libresoc.v:106129$4160
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:106305.5-106305.29"
+ attribute \src "libresoc.v:106130.5-106130.29"
switch \initial
- attribute \src "libresoc.v:106305.9-106305.17"
+ attribute \src "libresoc.v:106130.9-106130.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0]
end
- attribute \src "libresoc.v:106359.3-106413.6"
- process $proc$libresoc.v:106359$4177
+ attribute \src "libresoc.v:106184.3-106238.6"
+ process $proc$libresoc.v:106184$4161
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:106360.5-106360.29"
+ attribute \src "libresoc.v:106185.5-106185.29"
switch \initial
- attribute \src "libresoc.v:106360.9-106360.17"
+ attribute \src "libresoc.v:106185.9-106185.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0]
end
- attribute \src "libresoc.v:106414.3-106468.6"
- process $proc$libresoc.v:106414$4178
+ attribute \src "libresoc.v:106239.3-106293.6"
+ process $proc$libresoc.v:106239$4162
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:106415.5-106415.29"
+ attribute \src "libresoc.v:106240.5-106240.29"
switch \initial
- attribute \src "libresoc.v:106415.9-106415.17"
+ attribute \src "libresoc.v:106240.9-106240.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0]
end
- attribute \src "libresoc.v:106469.3-106523.6"
- process $proc$libresoc.v:106469$4179
+ attribute \src "libresoc.v:106294.3-106348.6"
+ process $proc$libresoc.v:106294$4163
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:106470.5-106470.29"
+ attribute \src "libresoc.v:106295.5-106295.29"
switch \initial
- attribute \src "libresoc.v:106470.9-106470.17"
+ attribute \src "libresoc.v:106295.9-106295.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0]
end
- attribute \src "libresoc.v:106524.3-106578.6"
- process $proc$libresoc.v:106524$4180
+ attribute \src "libresoc.v:106349.3-106403.6"
+ process $proc$libresoc.v:106349$4164
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:106525.5-106525.29"
+ attribute \src "libresoc.v:106350.5-106350.29"
switch \initial
- attribute \src "libresoc.v:106525.9-106525.17"
+ attribute \src "libresoc.v:106350.9-106350.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0]
end
- attribute \src "libresoc.v:106579.3-106633.6"
- process $proc$libresoc.v:106579$4181
+ attribute \src "libresoc.v:106404.3-106458.6"
+ process $proc$libresoc.v:106404$4165
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:106580.5-106580.29"
+ attribute \src "libresoc.v:106405.5-106405.29"
switch \initial
- attribute \src "libresoc.v:106580.9-106580.17"
+ attribute \src "libresoc.v:106405.9-106405.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0]
end
- attribute \src "libresoc.v:106634.3-106688.6"
- process $proc$libresoc.v:106634$4182
+ attribute \src "libresoc.v:106459.3-106513.6"
+ process $proc$libresoc.v:106459$4166
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:106635.5-106635.29"
+ attribute \src "libresoc.v:106460.5-106460.29"
switch \initial
- attribute \src "libresoc.v:106635.9-106635.17"
+ attribute \src "libresoc.v:106460.9-106460.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0]
end
- attribute \src "libresoc.v:106689.3-106743.6"
- process $proc$libresoc.v:106689$4183
+ attribute \src "libresoc.v:106514.3-106568.6"
+ process $proc$libresoc.v:106514$4167
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:106690.5-106690.29"
+ attribute \src "libresoc.v:106515.5-106515.29"
switch \initial
- attribute \src "libresoc.v:106690.9-106690.17"
+ attribute \src "libresoc.v:106515.9-106515.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:106744.3-106798.6"
- process $proc$libresoc.v:106744$4184
+ attribute \src "libresoc.v:106569.3-106623.6"
+ process $proc$libresoc.v:106569$4168
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:106745.5-106745.29"
+ attribute \src "libresoc.v:106570.5-106570.29"
switch \initial
- attribute \src "libresoc.v:106745.9-106745.17"
+ attribute \src "libresoc.v:106570.9-106570.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0]
end
- attribute \src "libresoc.v:106799.3-106853.6"
- process $proc$libresoc.v:106799$4185
+ attribute \src "libresoc.v:106624.3-106678.6"
+ process $proc$libresoc.v:106624$4169
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:106800.5-106800.29"
+ attribute \src "libresoc.v:106625.5-106625.29"
switch \initial
- attribute \src "libresoc.v:106800.9-106800.17"
+ attribute \src "libresoc.v:106625.9-106625.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:106854.3-106908.6"
- process $proc$libresoc.v:106854$4186
+ attribute \src "libresoc.v:106679.3-106733.6"
+ process $proc$libresoc.v:106679$4170
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:106855.5-106855.29"
+ attribute \src "libresoc.v:106680.5-106680.29"
switch \initial
- attribute \src "libresoc.v:106855.9-106855.17"
+ attribute \src "libresoc.v:106680.9-106680.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0]
end
- attribute \src "libresoc.v:106909.3-106963.6"
- process $proc$libresoc.v:106909$4187
+ attribute \src "libresoc.v:106734.3-106788.6"
+ process $proc$libresoc.v:106734$4171
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:106910.5-106910.29"
+ attribute \src "libresoc.v:106735.5-106735.29"
switch \initial
- attribute \src "libresoc.v:106910.9-106910.17"
+ attribute \src "libresoc.v:106735.9-106735.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0]
end
- attribute \src "libresoc.v:106964.3-107018.6"
- process $proc$libresoc.v:106964$4188
+ attribute \src "libresoc.v:106789.3-106843.6"
+ process $proc$libresoc.v:106789$4172
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:106965.5-106965.29"
+ attribute \src "libresoc.v:106790.5-106790.29"
switch \initial
- attribute \src "libresoc.v:106965.9-106965.17"
+ attribute \src "libresoc.v:106790.9-106790.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0]
end
- attribute \src "libresoc.v:107019.3-107073.6"
- process $proc$libresoc.v:107019$4189
+ attribute \src "libresoc.v:106844.3-106898.6"
+ process $proc$libresoc.v:106844$4173
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0]
- attribute \src "libresoc.v:107020.5-107020.29"
+ attribute \src "libresoc.v:106845.5-106845.29"
switch \initial
- attribute \src "libresoc.v:107020.9-107020.17"
+ attribute \src "libresoc.v:106845.9-106845.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:107079.1-109046.10"
+attribute \src "libresoc.v:106904.1-108871.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23"
attribute \generator "nMigen"
module \dec31_dec_sub23
- attribute \src "libresoc.v:108751.3-108799.6"
+ attribute \src "libresoc.v:108576.3-108624.6"
wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:108800.3-108848.6"
+ attribute \src "libresoc.v:108625.3-108673.6"
wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:108163.3-108211.6"
+ attribute \src "libresoc.v:107988.3-108036.6"
wire width 8 $0\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:108359.3-108407.6"
+ attribute \src "libresoc.v:108184.3-108232.6"
wire $0\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:107477.3-107525.6"
+ attribute \src "libresoc.v:107302.3-107350.6"
wire width 3 $0\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:107526.3-107574.6"
+ attribute \src "libresoc.v:107351.3-107399.6"
wire width 3 $0\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:108114.3-108162.6"
+ attribute \src "libresoc.v:107939.3-107987.6"
wire width 2 $0\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:108310.3-108358.6"
+ attribute \src "libresoc.v:108135.3-108183.6"
wire $0\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:108506.3-108554.6"
+ attribute \src "libresoc.v:108331.3-108379.6"
wire width 5 $0\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:107428.3-107476.6"
+ attribute \src "libresoc.v:107253.3-107301.6"
wire width 14 $0\dec31_dec_sub23_function_unit[13:0]
- attribute \src "libresoc.v:108849.3-108897.6"
+ attribute \src "libresoc.v:108674.3-108722.6"
wire width 3 $0\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:108898.3-108946.6"
+ attribute \src "libresoc.v:108723.3-108771.6"
wire width 4 $0\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:108947.3-108995.6"
+ attribute \src "libresoc.v:108772.3-108820.6"
wire width 2 $0\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:107967.3-108015.6"
+ attribute \src "libresoc.v:107792.3-107840.6"
wire width 7 $0\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:108212.3-108260.6"
+ attribute \src "libresoc.v:108037.3-108085.6"
wire $0\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:108261.3-108309.6"
+ attribute \src "libresoc.v:108086.3-108134.6"
wire $0\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:108555.3-108603.6"
+ attribute \src "libresoc.v:108380.3-108428.6"
wire $0\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:107918.3-107966.6"
+ attribute \src "libresoc.v:107743.3-107791.6"
wire width 4 $0\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:108653.3-108701.6"
+ attribute \src "libresoc.v:108478.3-108526.6"
wire $0\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:108996.3-109044.6"
+ attribute \src "libresoc.v:108821.3-108869.6"
wire width 3 $0\dec31_dec_sub23_out_sel[2:0]
- attribute \src "libresoc.v:108065.3-108113.6"
+ attribute \src "libresoc.v:107890.3-107938.6"
wire width 2 $0\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:108457.3-108505.6"
+ attribute \src "libresoc.v:108282.3-108330.6"
wire $0\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:108702.3-108750.6"
+ attribute \src "libresoc.v:108527.3-108575.6"
wire $0\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:108604.3-108652.6"
+ attribute \src "libresoc.v:108429.3-108477.6"
wire $0\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:108408.3-108456.6"
+ attribute \src "libresoc.v:108233.3-108281.6"
wire $0\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:107820.3-107868.6"
+ attribute \src "libresoc.v:107645.3-107693.6"
wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:107869.3-107917.6"
+ attribute \src "libresoc.v:107694.3-107742.6"
wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:107575.3-107623.6"
+ attribute \src "libresoc.v:107400.3-107448.6"
wire width 3 $0\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:107624.3-107672.6"
+ attribute \src "libresoc.v:107449.3-107497.6"
wire width 3 $0\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:107673.3-107721.6"
+ attribute \src "libresoc.v:107498.3-107546.6"
wire width 3 $0\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:107771.3-107819.6"
+ attribute \src "libresoc.v:107596.3-107644.6"
wire width 3 $0\dec31_dec_sub23_sv_out2[2:0]
- attribute \src "libresoc.v:107722.3-107770.6"
+ attribute \src "libresoc.v:107547.3-107595.6"
wire width 3 $0\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:108016.3-108064.6"
+ attribute \src "libresoc.v:107841.3-107889.6"
wire width 2 $0\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:107080.7-107080.20"
+ attribute \src "libresoc.v:106905.7-106905.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:108751.3-108799.6"
+ attribute \src "libresoc.v:108576.3-108624.6"
wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:108800.3-108848.6"
+ attribute \src "libresoc.v:108625.3-108673.6"
wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:108163.3-108211.6"
+ attribute \src "libresoc.v:107988.3-108036.6"
wire width 8 $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:108359.3-108407.6"
+ attribute \src "libresoc.v:108184.3-108232.6"
wire $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:107477.3-107525.6"
+ attribute \src "libresoc.v:107302.3-107350.6"
wire width 3 $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:107526.3-107574.6"
+ attribute \src "libresoc.v:107351.3-107399.6"
wire width 3 $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:108114.3-108162.6"
+ attribute \src "libresoc.v:107939.3-107987.6"
wire width 2 $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:108310.3-108358.6"
+ attribute \src "libresoc.v:108135.3-108183.6"
wire $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:108506.3-108554.6"
+ attribute \src "libresoc.v:108331.3-108379.6"
wire width 5 $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:107428.3-107476.6"
+ attribute \src "libresoc.v:107253.3-107301.6"
wire width 14 $1\dec31_dec_sub23_function_unit[13:0]
- attribute \src "libresoc.v:108849.3-108897.6"
+ attribute \src "libresoc.v:108674.3-108722.6"
wire width 3 $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:108898.3-108946.6"
+ attribute \src "libresoc.v:108723.3-108771.6"
wire width 4 $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:108947.3-108995.6"
+ attribute \src "libresoc.v:108772.3-108820.6"
wire width 2 $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:107967.3-108015.6"
+ attribute \src "libresoc.v:107792.3-107840.6"
wire width 7 $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:108212.3-108260.6"
+ attribute \src "libresoc.v:108037.3-108085.6"
wire $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:108261.3-108309.6"
+ attribute \src "libresoc.v:108086.3-108134.6"
wire $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:108555.3-108603.6"
+ attribute \src "libresoc.v:108380.3-108428.6"
wire $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:107918.3-107966.6"
+ attribute \src "libresoc.v:107743.3-107791.6"
wire width 4 $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:108653.3-108701.6"
+ attribute \src "libresoc.v:108478.3-108526.6"
wire $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:108996.3-109044.6"
+ attribute \src "libresoc.v:108821.3-108869.6"
wire width 3 $1\dec31_dec_sub23_out_sel[2:0]
- attribute \src "libresoc.v:108065.3-108113.6"
+ attribute \src "libresoc.v:107890.3-107938.6"
wire width 2 $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:108457.3-108505.6"
+ attribute \src "libresoc.v:108282.3-108330.6"
wire $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:108702.3-108750.6"
+ attribute \src "libresoc.v:108527.3-108575.6"
wire $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:108604.3-108652.6"
+ attribute \src "libresoc.v:108429.3-108477.6"
wire $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:108408.3-108456.6"
+ attribute \src "libresoc.v:108233.3-108281.6"
wire $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:107820.3-107868.6"
+ attribute \src "libresoc.v:107645.3-107693.6"
wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:107869.3-107917.6"
+ attribute \src "libresoc.v:107694.3-107742.6"
wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:107575.3-107623.6"
+ attribute \src "libresoc.v:107400.3-107448.6"
wire width 3 $1\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:107624.3-107672.6"
+ attribute \src "libresoc.v:107449.3-107497.6"
wire width 3 $1\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:107673.3-107721.6"
+ attribute \src "libresoc.v:107498.3-107546.6"
wire width 3 $1\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:107771.3-107819.6"
+ attribute \src "libresoc.v:107596.3-107644.6"
wire width 3 $1\dec31_dec_sub23_sv_out2[2:0]
- attribute \src "libresoc.v:107722.3-107770.6"
+ attribute \src "libresoc.v:107547.3-107595.6"
wire width 3 $1\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:108016.3-108064.6"
+ attribute \src "libresoc.v:107841.3-107889.6"
wire width 2 $1\dec31_dec_sub23_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub23_upd
- attribute \src "libresoc.v:107080.7-107080.15"
+ attribute \src "libresoc.v:106905.7-106905.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:107080.7-107080.20"
- process $proc$libresoc.v:107080$4224
+ attribute \src "libresoc.v:106905.7-106905.20"
+ process $proc$libresoc.v:106905$4208
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:107428.3-107476.6"
- process $proc$libresoc.v:107428$4191
+ attribute \src "libresoc.v:107253.3-107301.6"
+ process $proc$libresoc.v:107253$4175
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0]
- attribute \src "libresoc.v:107429.5-107429.29"
+ attribute \src "libresoc.v:107254.5-107254.29"
switch \initial
- attribute \src "libresoc.v:107429.9-107429.17"
+ attribute \src "libresoc.v:107254.9-107254.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0]
end
- attribute \src "libresoc.v:107477.3-107525.6"
- process $proc$libresoc.v:107477$4192
+ attribute \src "libresoc.v:107302.3-107350.6"
+ process $proc$libresoc.v:107302$4176
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:107478.5-107478.29"
+ attribute \src "libresoc.v:107303.5-107303.29"
switch \initial
- attribute \src "libresoc.v:107478.9-107478.17"
+ attribute \src "libresoc.v:107303.9-107303.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0]
end
- attribute \src "libresoc.v:107526.3-107574.6"
- process $proc$libresoc.v:107526$4193
+ attribute \src "libresoc.v:107351.3-107399.6"
+ process $proc$libresoc.v:107351$4177
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:107527.5-107527.29"
+ attribute \src "libresoc.v:107352.5-107352.29"
switch \initial
- attribute \src "libresoc.v:107527.9-107527.17"
+ attribute \src "libresoc.v:107352.9-107352.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0]
end
- attribute \src "libresoc.v:107575.3-107623.6"
- process $proc$libresoc.v:107575$4194
+ attribute \src "libresoc.v:107400.3-107448.6"
+ process $proc$libresoc.v:107400$4178
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:107576.5-107576.29"
+ attribute \src "libresoc.v:107401.5-107401.29"
switch \initial
- attribute \src "libresoc.v:107576.9-107576.17"
+ attribute \src "libresoc.v:107401.9-107401.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0]
end
- attribute \src "libresoc.v:107624.3-107672.6"
- process $proc$libresoc.v:107624$4195
+ attribute \src "libresoc.v:107449.3-107497.6"
+ process $proc$libresoc.v:107449$4179
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:107625.5-107625.29"
+ attribute \src "libresoc.v:107450.5-107450.29"
switch \initial
- attribute \src "libresoc.v:107625.9-107625.17"
+ attribute \src "libresoc.v:107450.9-107450.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0]
end
- attribute \src "libresoc.v:107673.3-107721.6"
- process $proc$libresoc.v:107673$4196
+ attribute \src "libresoc.v:107498.3-107546.6"
+ process $proc$libresoc.v:107498$4180
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:107674.5-107674.29"
+ attribute \src "libresoc.v:107499.5-107499.29"
switch \initial
- attribute \src "libresoc.v:107674.9-107674.17"
+ attribute \src "libresoc.v:107499.9-107499.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0]
end
- attribute \src "libresoc.v:107722.3-107770.6"
- process $proc$libresoc.v:107722$4197
+ attribute \src "libresoc.v:107547.3-107595.6"
+ process $proc$libresoc.v:107547$4181
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:107723.5-107723.29"
+ attribute \src "libresoc.v:107548.5-107548.29"
switch \initial
- attribute \src "libresoc.v:107723.9-107723.17"
+ attribute \src "libresoc.v:107548.9-107548.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0]
end
- attribute \src "libresoc.v:107771.3-107819.6"
- process $proc$libresoc.v:107771$4198
+ attribute \src "libresoc.v:107596.3-107644.6"
+ process $proc$libresoc.v:107596$4182
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0]
- attribute \src "libresoc.v:107772.5-107772.29"
+ attribute \src "libresoc.v:107597.5-107597.29"
switch \initial
- attribute \src "libresoc.v:107772.9-107772.17"
+ attribute \src "libresoc.v:107597.9-107597.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0]
end
- attribute \src "libresoc.v:107820.3-107868.6"
- process $proc$libresoc.v:107820$4199
+ attribute \src "libresoc.v:107645.3-107693.6"
+ process $proc$libresoc.v:107645$4183
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:107821.5-107821.29"
+ attribute \src "libresoc.v:107646.5-107646.29"
switch \initial
- attribute \src "libresoc.v:107821.9-107821.17"
+ attribute \src "libresoc.v:107646.9-107646.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:107869.3-107917.6"
- process $proc$libresoc.v:107869$4200
+ attribute \src "libresoc.v:107694.3-107742.6"
+ process $proc$libresoc.v:107694$4184
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:107870.5-107870.29"
+ attribute \src "libresoc.v:107695.5-107695.29"
switch \initial
- attribute \src "libresoc.v:107870.9-107870.17"
+ attribute \src "libresoc.v:107695.9-107695.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:107918.3-107966.6"
- process $proc$libresoc.v:107918$4201
+ attribute \src "libresoc.v:107743.3-107791.6"
+ process $proc$libresoc.v:107743$4185
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:107919.5-107919.29"
+ attribute \src "libresoc.v:107744.5-107744.29"
switch \initial
- attribute \src "libresoc.v:107919.9-107919.17"
+ attribute \src "libresoc.v:107744.9-107744.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0]
end
- attribute \src "libresoc.v:107967.3-108015.6"
- process $proc$libresoc.v:107967$4202
+ attribute \src "libresoc.v:107792.3-107840.6"
+ process $proc$libresoc.v:107792$4186
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:107968.5-107968.29"
+ attribute \src "libresoc.v:107793.5-107793.29"
switch \initial
- attribute \src "libresoc.v:107968.9-107968.17"
+ attribute \src "libresoc.v:107793.9-107793.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0]
end
- attribute \src "libresoc.v:108016.3-108064.6"
- process $proc$libresoc.v:108016$4203
+ attribute \src "libresoc.v:107841.3-107889.6"
+ process $proc$libresoc.v:107841$4187
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:108017.5-108017.29"
+ attribute \src "libresoc.v:107842.5-107842.29"
switch \initial
- attribute \src "libresoc.v:108017.9-108017.17"
+ attribute \src "libresoc.v:107842.9-107842.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0]
end
- attribute \src "libresoc.v:108065.3-108113.6"
- process $proc$libresoc.v:108065$4204
+ attribute \src "libresoc.v:107890.3-107938.6"
+ process $proc$libresoc.v:107890$4188
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:108066.5-108066.29"
+ attribute \src "libresoc.v:107891.5-107891.29"
switch \initial
- attribute \src "libresoc.v:108066.9-108066.17"
+ attribute \src "libresoc.v:107891.9-107891.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0]
end
- attribute \src "libresoc.v:108114.3-108162.6"
- process $proc$libresoc.v:108114$4205
+ attribute \src "libresoc.v:107939.3-107987.6"
+ process $proc$libresoc.v:107939$4189
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:108115.5-108115.29"
+ attribute \src "libresoc.v:107940.5-107940.29"
switch \initial
- attribute \src "libresoc.v:108115.9-108115.17"
+ attribute \src "libresoc.v:107940.9-107940.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0]
end
- attribute \src "libresoc.v:108163.3-108211.6"
- process $proc$libresoc.v:108163$4206
+ attribute \src "libresoc.v:107988.3-108036.6"
+ process $proc$libresoc.v:107988$4190
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:108164.5-108164.29"
+ attribute \src "libresoc.v:107989.5-107989.29"
switch \initial
- attribute \src "libresoc.v:108164.9-108164.17"
+ attribute \src "libresoc.v:107989.9-107989.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0]
end
- attribute \src "libresoc.v:108212.3-108260.6"
- process $proc$libresoc.v:108212$4207
+ attribute \src "libresoc.v:108037.3-108085.6"
+ process $proc$libresoc.v:108037$4191
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:108213.5-108213.29"
+ attribute \src "libresoc.v:108038.5-108038.29"
switch \initial
- attribute \src "libresoc.v:108213.9-108213.17"
+ attribute \src "libresoc.v:108038.9-108038.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0]
end
- attribute \src "libresoc.v:108261.3-108309.6"
- process $proc$libresoc.v:108261$4208
+ attribute \src "libresoc.v:108086.3-108134.6"
+ process $proc$libresoc.v:108086$4192
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:108262.5-108262.29"
+ attribute \src "libresoc.v:108087.5-108087.29"
switch \initial
- attribute \src "libresoc.v:108262.9-108262.17"
+ attribute \src "libresoc.v:108087.9-108087.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0]
end
- attribute \src "libresoc.v:108310.3-108358.6"
- process $proc$libresoc.v:108310$4209
+ attribute \src "libresoc.v:108135.3-108183.6"
+ process $proc$libresoc.v:108135$4193
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:108311.5-108311.29"
+ attribute \src "libresoc.v:108136.5-108136.29"
switch \initial
- attribute \src "libresoc.v:108311.9-108311.17"
+ attribute \src "libresoc.v:108136.9-108136.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0]
end
- attribute \src "libresoc.v:108359.3-108407.6"
- process $proc$libresoc.v:108359$4210
+ attribute \src "libresoc.v:108184.3-108232.6"
+ process $proc$libresoc.v:108184$4194
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:108360.5-108360.29"
+ attribute \src "libresoc.v:108185.5-108185.29"
switch \initial
- attribute \src "libresoc.v:108360.9-108360.17"
+ attribute \src "libresoc.v:108185.9-108185.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0]
end
- attribute \src "libresoc.v:108408.3-108456.6"
- process $proc$libresoc.v:108408$4211
+ attribute \src "libresoc.v:108233.3-108281.6"
+ process $proc$libresoc.v:108233$4195
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:108409.5-108409.29"
+ attribute \src "libresoc.v:108234.5-108234.29"
switch \initial
- attribute \src "libresoc.v:108409.9-108409.17"
+ attribute \src "libresoc.v:108234.9-108234.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0]
end
- attribute \src "libresoc.v:108457.3-108505.6"
- process $proc$libresoc.v:108457$4212
+ attribute \src "libresoc.v:108282.3-108330.6"
+ process $proc$libresoc.v:108282$4196
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:108458.5-108458.29"
+ attribute \src "libresoc.v:108283.5-108283.29"
switch \initial
- attribute \src "libresoc.v:108458.9-108458.17"
+ attribute \src "libresoc.v:108283.9-108283.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0]
end
- attribute \src "libresoc.v:108506.3-108554.6"
- process $proc$libresoc.v:108506$4213
+ attribute \src "libresoc.v:108331.3-108379.6"
+ process $proc$libresoc.v:108331$4197
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:108507.5-108507.29"
+ attribute \src "libresoc.v:108332.5-108332.29"
switch \initial
- attribute \src "libresoc.v:108507.9-108507.17"
+ attribute \src "libresoc.v:108332.9-108332.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0]
end
- attribute \src "libresoc.v:108555.3-108603.6"
- process $proc$libresoc.v:108555$4214
+ attribute \src "libresoc.v:108380.3-108428.6"
+ process $proc$libresoc.v:108380$4198
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:108556.5-108556.29"
+ attribute \src "libresoc.v:108381.5-108381.29"
switch \initial
- attribute \src "libresoc.v:108556.9-108556.17"
+ attribute \src "libresoc.v:108381.9-108381.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0]
end
- attribute \src "libresoc.v:108604.3-108652.6"
- process $proc$libresoc.v:108604$4215
+ attribute \src "libresoc.v:108429.3-108477.6"
+ process $proc$libresoc.v:108429$4199
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:108605.5-108605.29"
+ attribute \src "libresoc.v:108430.5-108430.29"
switch \initial
- attribute \src "libresoc.v:108605.9-108605.17"
+ attribute \src "libresoc.v:108430.9-108430.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0]
end
- attribute \src "libresoc.v:108653.3-108701.6"
- process $proc$libresoc.v:108653$4216
+ attribute \src "libresoc.v:108478.3-108526.6"
+ process $proc$libresoc.v:108478$4200
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:108654.5-108654.29"
+ attribute \src "libresoc.v:108479.5-108479.29"
switch \initial
- attribute \src "libresoc.v:108654.9-108654.17"
+ attribute \src "libresoc.v:108479.9-108479.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0]
end
- attribute \src "libresoc.v:108702.3-108750.6"
- process $proc$libresoc.v:108702$4217
+ attribute \src "libresoc.v:108527.3-108575.6"
+ process $proc$libresoc.v:108527$4201
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:108703.5-108703.29"
+ attribute \src "libresoc.v:108528.5-108528.29"
switch \initial
- attribute \src "libresoc.v:108703.9-108703.17"
+ attribute \src "libresoc.v:108528.9-108528.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:108751.3-108799.6"
- process $proc$libresoc.v:108751$4218
+ attribute \src "libresoc.v:108576.3-108624.6"
+ process $proc$libresoc.v:108576$4202
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:108752.5-108752.29"
+ attribute \src "libresoc.v:108577.5-108577.29"
switch \initial
- attribute \src "libresoc.v:108752.9-108752.17"
+ attribute \src "libresoc.v:108577.9-108577.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0]
end
- attribute \src "libresoc.v:108800.3-108848.6"
- process $proc$libresoc.v:108800$4219
+ attribute \src "libresoc.v:108625.3-108673.6"
+ process $proc$libresoc.v:108625$4203
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:108801.5-108801.29"
+ attribute \src "libresoc.v:108626.5-108626.29"
switch \initial
- attribute \src "libresoc.v:108801.9-108801.17"
+ attribute \src "libresoc.v:108626.9-108626.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:108849.3-108897.6"
- process $proc$libresoc.v:108849$4220
+ attribute \src "libresoc.v:108674.3-108722.6"
+ process $proc$libresoc.v:108674$4204
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:108850.5-108850.29"
+ attribute \src "libresoc.v:108675.5-108675.29"
switch \initial
- attribute \src "libresoc.v:108850.9-108850.17"
+ attribute \src "libresoc.v:108675.9-108675.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0]
end
- attribute \src "libresoc.v:108898.3-108946.6"
- process $proc$libresoc.v:108898$4221
+ attribute \src "libresoc.v:108723.3-108771.6"
+ process $proc$libresoc.v:108723$4205
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:108899.5-108899.29"
+ attribute \src "libresoc.v:108724.5-108724.29"
switch \initial
- attribute \src "libresoc.v:108899.9-108899.17"
+ attribute \src "libresoc.v:108724.9-108724.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0]
end
- attribute \src "libresoc.v:108947.3-108995.6"
- process $proc$libresoc.v:108947$4222
+ attribute \src "libresoc.v:108772.3-108820.6"
+ process $proc$libresoc.v:108772$4206
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:108948.5-108948.29"
+ attribute \src "libresoc.v:108773.5-108773.29"
switch \initial
- attribute \src "libresoc.v:108948.9-108948.17"
+ attribute \src "libresoc.v:108773.9-108773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0]
end
- attribute \src "libresoc.v:108996.3-109044.6"
- process $proc$libresoc.v:108996$4223
+ attribute \src "libresoc.v:108821.3-108869.6"
+ process $proc$libresoc.v:108821$4207
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0]
- attribute \src "libresoc.v:108997.5-108997.29"
+ attribute \src "libresoc.v:108822.5-108822.29"
switch \initial
- attribute \src "libresoc.v:108997.9-108997.17"
+ attribute \src "libresoc.v:108822.9-108822.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:109050.1-110027.10"
+attribute \src "libresoc.v:108875.1-109852.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24"
attribute \generator "nMigen"
module \dec31_dec_sub24
- attribute \src "libresoc.v:109912.3-109930.6"
+ attribute \src "libresoc.v:109737.3-109755.6"
wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:109931.3-109949.6"
+ attribute \src "libresoc.v:109756.3-109774.6"
wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:109684.3-109702.6"
+ attribute \src "libresoc.v:109509.3-109527.6"
wire width 8 $0\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:109760.3-109778.6"
+ attribute \src "libresoc.v:109585.3-109603.6"
wire $0\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:109418.3-109436.6"
+ attribute \src "libresoc.v:109243.3-109261.6"
wire width 3 $0\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:109437.3-109455.6"
+ attribute \src "libresoc.v:109262.3-109280.6"
wire width 3 $0\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:109665.3-109683.6"
+ attribute \src "libresoc.v:109490.3-109508.6"
wire width 2 $0\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:109741.3-109759.6"
+ attribute \src "libresoc.v:109566.3-109584.6"
wire $0\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:109817.3-109835.6"
+ attribute \src "libresoc.v:109642.3-109660.6"
wire width 5 $0\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:109399.3-109417.6"
+ attribute \src "libresoc.v:109224.3-109242.6"
wire width 14 $0\dec31_dec_sub24_function_unit[13:0]
- attribute \src "libresoc.v:109950.3-109968.6"
+ attribute \src "libresoc.v:109775.3-109793.6"
wire width 3 $0\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:109969.3-109987.6"
+ attribute \src "libresoc.v:109794.3-109812.6"
wire width 4 $0\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:109988.3-110006.6"
+ attribute \src "libresoc.v:109813.3-109831.6"
wire width 2 $0\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:109608.3-109626.6"
+ attribute \src "libresoc.v:109433.3-109451.6"
wire width 7 $0\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:109703.3-109721.6"
+ attribute \src "libresoc.v:109528.3-109546.6"
wire $0\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:109722.3-109740.6"
+ attribute \src "libresoc.v:109547.3-109565.6"
wire $0\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:109836.3-109854.6"
+ attribute \src "libresoc.v:109661.3-109679.6"
wire $0\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:109589.3-109607.6"
+ attribute \src "libresoc.v:109414.3-109432.6"
wire width 4 $0\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:109874.3-109892.6"
+ attribute \src "libresoc.v:109699.3-109717.6"
wire $0\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:110007.3-110025.6"
+ attribute \src "libresoc.v:109832.3-109850.6"
wire width 3 $0\dec31_dec_sub24_out_sel[2:0]
- attribute \src "libresoc.v:109646.3-109664.6"
+ attribute \src "libresoc.v:109471.3-109489.6"
wire width 2 $0\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:109798.3-109816.6"
+ attribute \src "libresoc.v:109623.3-109641.6"
wire $0\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:109893.3-109911.6"
+ attribute \src "libresoc.v:109718.3-109736.6"
wire $0\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:109855.3-109873.6"
+ attribute \src "libresoc.v:109680.3-109698.6"
wire $0\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:109779.3-109797.6"
+ attribute \src "libresoc.v:109604.3-109622.6"
wire $0\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:109551.3-109569.6"
+ attribute \src "libresoc.v:109376.3-109394.6"
wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:109570.3-109588.6"
+ attribute \src "libresoc.v:109395.3-109413.6"
wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:109456.3-109474.6"
+ attribute \src "libresoc.v:109281.3-109299.6"
wire width 3 $0\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:109475.3-109493.6"
+ attribute \src "libresoc.v:109300.3-109318.6"
wire width 3 $0\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:109494.3-109512.6"
+ attribute \src "libresoc.v:109319.3-109337.6"
wire width 3 $0\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:109532.3-109550.6"
+ attribute \src "libresoc.v:109357.3-109375.6"
wire width 3 $0\dec31_dec_sub24_sv_out2[2:0]
- attribute \src "libresoc.v:109513.3-109531.6"
+ attribute \src "libresoc.v:109338.3-109356.6"
wire width 3 $0\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:109627.3-109645.6"
+ attribute \src "libresoc.v:109452.3-109470.6"
wire width 2 $0\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:109051.7-109051.20"
+ attribute \src "libresoc.v:108876.7-108876.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:109912.3-109930.6"
+ attribute \src "libresoc.v:109737.3-109755.6"
wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:109931.3-109949.6"
+ attribute \src "libresoc.v:109756.3-109774.6"
wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:109684.3-109702.6"
+ attribute \src "libresoc.v:109509.3-109527.6"
wire width 8 $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:109760.3-109778.6"
+ attribute \src "libresoc.v:109585.3-109603.6"
wire $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:109418.3-109436.6"
+ attribute \src "libresoc.v:109243.3-109261.6"
wire width 3 $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:109437.3-109455.6"
+ attribute \src "libresoc.v:109262.3-109280.6"
wire width 3 $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:109665.3-109683.6"
+ attribute \src "libresoc.v:109490.3-109508.6"
wire width 2 $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:109741.3-109759.6"
+ attribute \src "libresoc.v:109566.3-109584.6"
wire $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:109817.3-109835.6"
+ attribute \src "libresoc.v:109642.3-109660.6"
wire width 5 $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:109399.3-109417.6"
+ attribute \src "libresoc.v:109224.3-109242.6"
wire width 14 $1\dec31_dec_sub24_function_unit[13:0]
- attribute \src "libresoc.v:109950.3-109968.6"
+ attribute \src "libresoc.v:109775.3-109793.6"
wire width 3 $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:109969.3-109987.6"
+ attribute \src "libresoc.v:109794.3-109812.6"
wire width 4 $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:109988.3-110006.6"
+ attribute \src "libresoc.v:109813.3-109831.6"
wire width 2 $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:109608.3-109626.6"
+ attribute \src "libresoc.v:109433.3-109451.6"
wire width 7 $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:109703.3-109721.6"
+ attribute \src "libresoc.v:109528.3-109546.6"
wire $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:109722.3-109740.6"
+ attribute \src "libresoc.v:109547.3-109565.6"
wire $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:109836.3-109854.6"
+ attribute \src "libresoc.v:109661.3-109679.6"
wire $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:109589.3-109607.6"
+ attribute \src "libresoc.v:109414.3-109432.6"
wire width 4 $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:109874.3-109892.6"
+ attribute \src "libresoc.v:109699.3-109717.6"
wire $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:110007.3-110025.6"
+ attribute \src "libresoc.v:109832.3-109850.6"
wire width 3 $1\dec31_dec_sub24_out_sel[2:0]
- attribute \src "libresoc.v:109646.3-109664.6"
+ attribute \src "libresoc.v:109471.3-109489.6"
wire width 2 $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:109798.3-109816.6"
+ attribute \src "libresoc.v:109623.3-109641.6"
wire $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:109893.3-109911.6"
+ attribute \src "libresoc.v:109718.3-109736.6"
wire $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:109855.3-109873.6"
+ attribute \src "libresoc.v:109680.3-109698.6"
wire $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:109779.3-109797.6"
+ attribute \src "libresoc.v:109604.3-109622.6"
wire $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:109551.3-109569.6"
+ attribute \src "libresoc.v:109376.3-109394.6"
wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:109570.3-109588.6"
+ attribute \src "libresoc.v:109395.3-109413.6"
wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:109456.3-109474.6"
+ attribute \src "libresoc.v:109281.3-109299.6"
wire width 3 $1\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:109475.3-109493.6"
+ attribute \src "libresoc.v:109300.3-109318.6"
wire width 3 $1\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:109494.3-109512.6"
+ attribute \src "libresoc.v:109319.3-109337.6"
wire width 3 $1\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:109532.3-109550.6"
+ attribute \src "libresoc.v:109357.3-109375.6"
wire width 3 $1\dec31_dec_sub24_sv_out2[2:0]
- attribute \src "libresoc.v:109513.3-109531.6"
+ attribute \src "libresoc.v:109338.3-109356.6"
wire width 3 $1\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:109627.3-109645.6"
+ attribute \src "libresoc.v:109452.3-109470.6"
wire width 2 $1\dec31_dec_sub24_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub24_upd
- attribute \src "libresoc.v:109051.7-109051.15"
+ attribute \src "libresoc.v:108876.7-108876.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:109051.7-109051.20"
- process $proc$libresoc.v:109051$4258
+ attribute \src "libresoc.v:108876.7-108876.20"
+ process $proc$libresoc.v:108876$4242
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:109399.3-109417.6"
- process $proc$libresoc.v:109399$4225
+ attribute \src "libresoc.v:109224.3-109242.6"
+ process $proc$libresoc.v:109224$4209
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0]
- attribute \src "libresoc.v:109400.5-109400.29"
+ attribute \src "libresoc.v:109225.5-109225.29"
switch \initial
- attribute \src "libresoc.v:109400.9-109400.17"
+ attribute \src "libresoc.v:109225.9-109225.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0]
end
- attribute \src "libresoc.v:109418.3-109436.6"
- process $proc$libresoc.v:109418$4226
+ attribute \src "libresoc.v:109243.3-109261.6"
+ process $proc$libresoc.v:109243$4210
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:109419.5-109419.29"
+ attribute \src "libresoc.v:109244.5-109244.29"
switch \initial
- attribute \src "libresoc.v:109419.9-109419.17"
+ attribute \src "libresoc.v:109244.9-109244.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0]
end
- attribute \src "libresoc.v:109437.3-109455.6"
- process $proc$libresoc.v:109437$4227
+ attribute \src "libresoc.v:109262.3-109280.6"
+ process $proc$libresoc.v:109262$4211
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:109438.5-109438.29"
+ attribute \src "libresoc.v:109263.5-109263.29"
switch \initial
- attribute \src "libresoc.v:109438.9-109438.17"
+ attribute \src "libresoc.v:109263.9-109263.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0]
end
- attribute \src "libresoc.v:109456.3-109474.6"
- process $proc$libresoc.v:109456$4228
+ attribute \src "libresoc.v:109281.3-109299.6"
+ process $proc$libresoc.v:109281$4212
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:109457.5-109457.29"
+ attribute \src "libresoc.v:109282.5-109282.29"
switch \initial
- attribute \src "libresoc.v:109457.9-109457.17"
+ attribute \src "libresoc.v:109282.9-109282.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0]
end
- attribute \src "libresoc.v:109475.3-109493.6"
- process $proc$libresoc.v:109475$4229
+ attribute \src "libresoc.v:109300.3-109318.6"
+ process $proc$libresoc.v:109300$4213
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:109476.5-109476.29"
+ attribute \src "libresoc.v:109301.5-109301.29"
switch \initial
- attribute \src "libresoc.v:109476.9-109476.17"
+ attribute \src "libresoc.v:109301.9-109301.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0]
end
- attribute \src "libresoc.v:109494.3-109512.6"
- process $proc$libresoc.v:109494$4230
+ attribute \src "libresoc.v:109319.3-109337.6"
+ process $proc$libresoc.v:109319$4214
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:109495.5-109495.29"
+ attribute \src "libresoc.v:109320.5-109320.29"
switch \initial
- attribute \src "libresoc.v:109495.9-109495.17"
+ attribute \src "libresoc.v:109320.9-109320.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0]
end
- attribute \src "libresoc.v:109513.3-109531.6"
- process $proc$libresoc.v:109513$4231
+ attribute \src "libresoc.v:109338.3-109356.6"
+ process $proc$libresoc.v:109338$4215
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:109514.5-109514.29"
+ attribute \src "libresoc.v:109339.5-109339.29"
switch \initial
- attribute \src "libresoc.v:109514.9-109514.17"
+ attribute \src "libresoc.v:109339.9-109339.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0]
end
- attribute \src "libresoc.v:109532.3-109550.6"
- process $proc$libresoc.v:109532$4232
+ attribute \src "libresoc.v:109357.3-109375.6"
+ process $proc$libresoc.v:109357$4216
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0]
- attribute \src "libresoc.v:109533.5-109533.29"
+ attribute \src "libresoc.v:109358.5-109358.29"
switch \initial
- attribute \src "libresoc.v:109533.9-109533.17"
+ attribute \src "libresoc.v:109358.9-109358.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0]
end
- attribute \src "libresoc.v:109551.3-109569.6"
- process $proc$libresoc.v:109551$4233
+ attribute \src "libresoc.v:109376.3-109394.6"
+ process $proc$libresoc.v:109376$4217
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:109552.5-109552.29"
+ attribute \src "libresoc.v:109377.5-109377.29"
switch \initial
- attribute \src "libresoc.v:109552.9-109552.17"
+ attribute \src "libresoc.v:109377.9-109377.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:109570.3-109588.6"
- process $proc$libresoc.v:109570$4234
+ attribute \src "libresoc.v:109395.3-109413.6"
+ process $proc$libresoc.v:109395$4218
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:109571.5-109571.29"
+ attribute \src "libresoc.v:109396.5-109396.29"
switch \initial
- attribute \src "libresoc.v:109571.9-109571.17"
+ attribute \src "libresoc.v:109396.9-109396.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:109589.3-109607.6"
- process $proc$libresoc.v:109589$4235
+ attribute \src "libresoc.v:109414.3-109432.6"
+ process $proc$libresoc.v:109414$4219
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:109590.5-109590.29"
+ attribute \src "libresoc.v:109415.5-109415.29"
switch \initial
- attribute \src "libresoc.v:109590.9-109590.17"
+ attribute \src "libresoc.v:109415.9-109415.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0]
end
- attribute \src "libresoc.v:109608.3-109626.6"
- process $proc$libresoc.v:109608$4236
+ attribute \src "libresoc.v:109433.3-109451.6"
+ process $proc$libresoc.v:109433$4220
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:109609.5-109609.29"
+ attribute \src "libresoc.v:109434.5-109434.29"
switch \initial
- attribute \src "libresoc.v:109609.9-109609.17"
+ attribute \src "libresoc.v:109434.9-109434.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0]
end
- attribute \src "libresoc.v:109627.3-109645.6"
- process $proc$libresoc.v:109627$4237
+ attribute \src "libresoc.v:109452.3-109470.6"
+ process $proc$libresoc.v:109452$4221
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:109628.5-109628.29"
+ attribute \src "libresoc.v:109453.5-109453.29"
switch \initial
- attribute \src "libresoc.v:109628.9-109628.17"
+ attribute \src "libresoc.v:109453.9-109453.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0]
end
- attribute \src "libresoc.v:109646.3-109664.6"
- process $proc$libresoc.v:109646$4238
+ attribute \src "libresoc.v:109471.3-109489.6"
+ process $proc$libresoc.v:109471$4222
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:109647.5-109647.29"
+ attribute \src "libresoc.v:109472.5-109472.29"
switch \initial
- attribute \src "libresoc.v:109647.9-109647.17"
+ attribute \src "libresoc.v:109472.9-109472.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0]
end
- attribute \src "libresoc.v:109665.3-109683.6"
- process $proc$libresoc.v:109665$4239
+ attribute \src "libresoc.v:109490.3-109508.6"
+ process $proc$libresoc.v:109490$4223
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:109666.5-109666.29"
+ attribute \src "libresoc.v:109491.5-109491.29"
switch \initial
- attribute \src "libresoc.v:109666.9-109666.17"
+ attribute \src "libresoc.v:109491.9-109491.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0]
end
- attribute \src "libresoc.v:109684.3-109702.6"
- process $proc$libresoc.v:109684$4240
+ attribute \src "libresoc.v:109509.3-109527.6"
+ process $proc$libresoc.v:109509$4224
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:109685.5-109685.29"
+ attribute \src "libresoc.v:109510.5-109510.29"
switch \initial
- attribute \src "libresoc.v:109685.9-109685.17"
+ attribute \src "libresoc.v:109510.9-109510.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0]
end
- attribute \src "libresoc.v:109703.3-109721.6"
- process $proc$libresoc.v:109703$4241
+ attribute \src "libresoc.v:109528.3-109546.6"
+ process $proc$libresoc.v:109528$4225
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:109704.5-109704.29"
+ attribute \src "libresoc.v:109529.5-109529.29"
switch \initial
- attribute \src "libresoc.v:109704.9-109704.17"
+ attribute \src "libresoc.v:109529.9-109529.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0]
end
- attribute \src "libresoc.v:109722.3-109740.6"
- process $proc$libresoc.v:109722$4242
+ attribute \src "libresoc.v:109547.3-109565.6"
+ process $proc$libresoc.v:109547$4226
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:109723.5-109723.29"
+ attribute \src "libresoc.v:109548.5-109548.29"
switch \initial
- attribute \src "libresoc.v:109723.9-109723.17"
+ attribute \src "libresoc.v:109548.9-109548.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0]
end
- attribute \src "libresoc.v:109741.3-109759.6"
- process $proc$libresoc.v:109741$4243
+ attribute \src "libresoc.v:109566.3-109584.6"
+ process $proc$libresoc.v:109566$4227
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:109742.5-109742.29"
+ attribute \src "libresoc.v:109567.5-109567.29"
switch \initial
- attribute \src "libresoc.v:109742.9-109742.17"
+ attribute \src "libresoc.v:109567.9-109567.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0]
end
- attribute \src "libresoc.v:109760.3-109778.6"
- process $proc$libresoc.v:109760$4244
+ attribute \src "libresoc.v:109585.3-109603.6"
+ process $proc$libresoc.v:109585$4228
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:109761.5-109761.29"
+ attribute \src "libresoc.v:109586.5-109586.29"
switch \initial
- attribute \src "libresoc.v:109761.9-109761.17"
+ attribute \src "libresoc.v:109586.9-109586.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0]
end
- attribute \src "libresoc.v:109779.3-109797.6"
- process $proc$libresoc.v:109779$4245
+ attribute \src "libresoc.v:109604.3-109622.6"
+ process $proc$libresoc.v:109604$4229
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:109780.5-109780.29"
+ attribute \src "libresoc.v:109605.5-109605.29"
switch \initial
- attribute \src "libresoc.v:109780.9-109780.17"
+ attribute \src "libresoc.v:109605.9-109605.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0]
end
- attribute \src "libresoc.v:109798.3-109816.6"
- process $proc$libresoc.v:109798$4246
+ attribute \src "libresoc.v:109623.3-109641.6"
+ process $proc$libresoc.v:109623$4230
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:109799.5-109799.29"
+ attribute \src "libresoc.v:109624.5-109624.29"
switch \initial
- attribute \src "libresoc.v:109799.9-109799.17"
+ attribute \src "libresoc.v:109624.9-109624.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0]
end
- attribute \src "libresoc.v:109817.3-109835.6"
- process $proc$libresoc.v:109817$4247
+ attribute \src "libresoc.v:109642.3-109660.6"
+ process $proc$libresoc.v:109642$4231
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:109818.5-109818.29"
+ attribute \src "libresoc.v:109643.5-109643.29"
switch \initial
- attribute \src "libresoc.v:109818.9-109818.17"
+ attribute \src "libresoc.v:109643.9-109643.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0]
end
- attribute \src "libresoc.v:109836.3-109854.6"
- process $proc$libresoc.v:109836$4248
+ attribute \src "libresoc.v:109661.3-109679.6"
+ process $proc$libresoc.v:109661$4232
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:109837.5-109837.29"
+ attribute \src "libresoc.v:109662.5-109662.29"
switch \initial
- attribute \src "libresoc.v:109837.9-109837.17"
+ attribute \src "libresoc.v:109662.9-109662.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0]
end
- attribute \src "libresoc.v:109855.3-109873.6"
- process $proc$libresoc.v:109855$4249
+ attribute \src "libresoc.v:109680.3-109698.6"
+ process $proc$libresoc.v:109680$4233
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:109856.5-109856.29"
+ attribute \src "libresoc.v:109681.5-109681.29"
switch \initial
- attribute \src "libresoc.v:109856.9-109856.17"
+ attribute \src "libresoc.v:109681.9-109681.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0]
end
- attribute \src "libresoc.v:109874.3-109892.6"
- process $proc$libresoc.v:109874$4250
+ attribute \src "libresoc.v:109699.3-109717.6"
+ process $proc$libresoc.v:109699$4234
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:109875.5-109875.29"
+ attribute \src "libresoc.v:109700.5-109700.29"
switch \initial
- attribute \src "libresoc.v:109875.9-109875.17"
+ attribute \src "libresoc.v:109700.9-109700.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0]
end
- attribute \src "libresoc.v:109893.3-109911.6"
- process $proc$libresoc.v:109893$4251
+ attribute \src "libresoc.v:109718.3-109736.6"
+ process $proc$libresoc.v:109718$4235
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:109894.5-109894.29"
+ attribute \src "libresoc.v:109719.5-109719.29"
switch \initial
- attribute \src "libresoc.v:109894.9-109894.17"
+ attribute \src "libresoc.v:109719.9-109719.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:109912.3-109930.6"
- process $proc$libresoc.v:109912$4252
+ attribute \src "libresoc.v:109737.3-109755.6"
+ process $proc$libresoc.v:109737$4236
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:109913.5-109913.29"
+ attribute \src "libresoc.v:109738.5-109738.29"
switch \initial
- attribute \src "libresoc.v:109913.9-109913.17"
+ attribute \src "libresoc.v:109738.9-109738.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0]
end
- attribute \src "libresoc.v:109931.3-109949.6"
- process $proc$libresoc.v:109931$4253
+ attribute \src "libresoc.v:109756.3-109774.6"
+ process $proc$libresoc.v:109756$4237
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:109932.5-109932.29"
+ attribute \src "libresoc.v:109757.5-109757.29"
switch \initial
- attribute \src "libresoc.v:109932.9-109932.17"
+ attribute \src "libresoc.v:109757.9-109757.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:109950.3-109968.6"
- process $proc$libresoc.v:109950$4254
+ attribute \src "libresoc.v:109775.3-109793.6"
+ process $proc$libresoc.v:109775$4238
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:109951.5-109951.29"
+ attribute \src "libresoc.v:109776.5-109776.29"
switch \initial
- attribute \src "libresoc.v:109951.9-109951.17"
+ attribute \src "libresoc.v:109776.9-109776.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0]
end
- attribute \src "libresoc.v:109969.3-109987.6"
- process $proc$libresoc.v:109969$4255
+ attribute \src "libresoc.v:109794.3-109812.6"
+ process $proc$libresoc.v:109794$4239
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:109970.5-109970.29"
+ attribute \src "libresoc.v:109795.5-109795.29"
switch \initial
- attribute \src "libresoc.v:109970.9-109970.17"
+ attribute \src "libresoc.v:109795.9-109795.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0]
end
- attribute \src "libresoc.v:109988.3-110006.6"
- process $proc$libresoc.v:109988$4256
+ attribute \src "libresoc.v:109813.3-109831.6"
+ process $proc$libresoc.v:109813$4240
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:109989.5-109989.29"
+ attribute \src "libresoc.v:109814.5-109814.29"
switch \initial
- attribute \src "libresoc.v:109989.9-109989.17"
+ attribute \src "libresoc.v:109814.9-109814.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0]
end
- attribute \src "libresoc.v:110007.3-110025.6"
- process $proc$libresoc.v:110007$4257
+ attribute \src "libresoc.v:109832.3-109850.6"
+ process $proc$libresoc.v:109832$4241
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0]
- attribute \src "libresoc.v:110008.5-110008.29"
+ attribute \src "libresoc.v:109833.5-109833.29"
switch \initial
- attribute \src "libresoc.v:110008.9-110008.17"
+ attribute \src "libresoc.v:109833.9-109833.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:110031.1-112097.10"
+attribute \src "libresoc.v:109856.1-111922.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26"
attribute \generator "nMigen"
module \dec31_dec_sub26
- attribute \src "libresoc.v:111784.3-111835.6"
+ attribute \src "libresoc.v:111609.3-111660.6"
wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:111836.3-111887.6"
+ attribute \src "libresoc.v:111661.3-111712.6"
wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:111160.3-111211.6"
+ attribute \src "libresoc.v:110985.3-111036.6"
wire width 8 $0\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:111368.3-111419.6"
+ attribute \src "libresoc.v:111193.3-111244.6"
wire $0\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:110432.3-110483.6"
+ attribute \src "libresoc.v:110257.3-110308.6"
wire width 3 $0\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:110484.3-110535.6"
+ attribute \src "libresoc.v:110309.3-110360.6"
wire width 3 $0\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:111108.3-111159.6"
+ attribute \src "libresoc.v:110933.3-110984.6"
wire width 2 $0\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:111316.3-111367.6"
+ attribute \src "libresoc.v:111141.3-111192.6"
wire $0\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:111524.3-111575.6"
+ attribute \src "libresoc.v:111349.3-111400.6"
wire width 5 $0\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:110380.3-110431.6"
+ attribute \src "libresoc.v:110205.3-110256.6"
wire width 14 $0\dec31_dec_sub26_function_unit[13:0]
- attribute \src "libresoc.v:111888.3-111939.6"
+ attribute \src "libresoc.v:111713.3-111764.6"
wire width 3 $0\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:111940.3-111991.6"
+ attribute \src "libresoc.v:111765.3-111816.6"
wire width 4 $0\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:111992.3-112043.6"
+ attribute \src "libresoc.v:111817.3-111868.6"
wire width 2 $0\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:110952.3-111003.6"
+ attribute \src "libresoc.v:110777.3-110828.6"
wire width 7 $0\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:111212.3-111263.6"
+ attribute \src "libresoc.v:111037.3-111088.6"
wire $0\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:111264.3-111315.6"
+ attribute \src "libresoc.v:111089.3-111140.6"
wire $0\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:111576.3-111627.6"
+ attribute \src "libresoc.v:111401.3-111452.6"
wire $0\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:110900.3-110951.6"
+ attribute \src "libresoc.v:110725.3-110776.6"
wire width 4 $0\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:111680.3-111731.6"
+ attribute \src "libresoc.v:111505.3-111556.6"
wire $0\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:112044.3-112095.6"
+ attribute \src "libresoc.v:111869.3-111920.6"
wire width 3 $0\dec31_dec_sub26_out_sel[2:0]
- attribute \src "libresoc.v:111056.3-111107.6"
+ attribute \src "libresoc.v:110881.3-110932.6"
wire width 2 $0\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:111472.3-111523.6"
+ attribute \src "libresoc.v:111297.3-111348.6"
wire $0\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:111732.3-111783.6"
+ attribute \src "libresoc.v:111557.3-111608.6"
wire $0\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:111628.3-111679.6"
+ attribute \src "libresoc.v:111453.3-111504.6"
wire $0\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:111420.3-111471.6"
+ attribute \src "libresoc.v:111245.3-111296.6"
wire $0\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:110796.3-110847.6"
+ attribute \src "libresoc.v:110621.3-110672.6"
wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:110848.3-110899.6"
+ attribute \src "libresoc.v:110673.3-110724.6"
wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:110536.3-110587.6"
+ attribute \src "libresoc.v:110361.3-110412.6"
wire width 3 $0\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:110588.3-110639.6"
+ attribute \src "libresoc.v:110413.3-110464.6"
wire width 3 $0\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:110640.3-110691.6"
+ attribute \src "libresoc.v:110465.3-110516.6"
wire width 3 $0\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:110744.3-110795.6"
+ attribute \src "libresoc.v:110569.3-110620.6"
wire width 3 $0\dec31_dec_sub26_sv_out2[2:0]
- attribute \src "libresoc.v:110692.3-110743.6"
+ attribute \src "libresoc.v:110517.3-110568.6"
wire width 3 $0\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:111004.3-111055.6"
+ attribute \src "libresoc.v:110829.3-110880.6"
wire width 2 $0\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:110032.7-110032.20"
+ attribute \src "libresoc.v:109857.7-109857.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:111784.3-111835.6"
+ attribute \src "libresoc.v:111609.3-111660.6"
wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:111836.3-111887.6"
+ attribute \src "libresoc.v:111661.3-111712.6"
wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:111160.3-111211.6"
+ attribute \src "libresoc.v:110985.3-111036.6"
wire width 8 $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:111368.3-111419.6"
+ attribute \src "libresoc.v:111193.3-111244.6"
wire $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:110432.3-110483.6"
+ attribute \src "libresoc.v:110257.3-110308.6"
wire width 3 $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:110484.3-110535.6"
+ attribute \src "libresoc.v:110309.3-110360.6"
wire width 3 $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:111108.3-111159.6"
+ attribute \src "libresoc.v:110933.3-110984.6"
wire width 2 $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:111316.3-111367.6"
+ attribute \src "libresoc.v:111141.3-111192.6"
wire $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:111524.3-111575.6"
+ attribute \src "libresoc.v:111349.3-111400.6"
wire width 5 $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:110380.3-110431.6"
+ attribute \src "libresoc.v:110205.3-110256.6"
wire width 14 $1\dec31_dec_sub26_function_unit[13:0]
- attribute \src "libresoc.v:111888.3-111939.6"
+ attribute \src "libresoc.v:111713.3-111764.6"
wire width 3 $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:111940.3-111991.6"
+ attribute \src "libresoc.v:111765.3-111816.6"
wire width 4 $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:111992.3-112043.6"
+ attribute \src "libresoc.v:111817.3-111868.6"
wire width 2 $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:110952.3-111003.6"
+ attribute \src "libresoc.v:110777.3-110828.6"
wire width 7 $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:111212.3-111263.6"
+ attribute \src "libresoc.v:111037.3-111088.6"
wire $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:111264.3-111315.6"
+ attribute \src "libresoc.v:111089.3-111140.6"
wire $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:111576.3-111627.6"
+ attribute \src "libresoc.v:111401.3-111452.6"
wire $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:110900.3-110951.6"
+ attribute \src "libresoc.v:110725.3-110776.6"
wire width 4 $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:111680.3-111731.6"
+ attribute \src "libresoc.v:111505.3-111556.6"
wire $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:112044.3-112095.6"
+ attribute \src "libresoc.v:111869.3-111920.6"
wire width 3 $1\dec31_dec_sub26_out_sel[2:0]
- attribute \src "libresoc.v:111056.3-111107.6"
+ attribute \src "libresoc.v:110881.3-110932.6"
wire width 2 $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:111472.3-111523.6"
+ attribute \src "libresoc.v:111297.3-111348.6"
wire $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:111732.3-111783.6"
+ attribute \src "libresoc.v:111557.3-111608.6"
wire $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:111628.3-111679.6"
+ attribute \src "libresoc.v:111453.3-111504.6"
wire $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:111420.3-111471.6"
+ attribute \src "libresoc.v:111245.3-111296.6"
wire $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:110796.3-110847.6"
+ attribute \src "libresoc.v:110621.3-110672.6"
wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:110848.3-110899.6"
+ attribute \src "libresoc.v:110673.3-110724.6"
wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:110536.3-110587.6"
+ attribute \src "libresoc.v:110361.3-110412.6"
wire width 3 $1\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:110588.3-110639.6"
+ attribute \src "libresoc.v:110413.3-110464.6"
wire width 3 $1\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:110640.3-110691.6"
+ attribute \src "libresoc.v:110465.3-110516.6"
wire width 3 $1\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:110744.3-110795.6"
+ attribute \src "libresoc.v:110569.3-110620.6"
wire width 3 $1\dec31_dec_sub26_sv_out2[2:0]
- attribute \src "libresoc.v:110692.3-110743.6"
+ attribute \src "libresoc.v:110517.3-110568.6"
wire width 3 $1\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:111004.3-111055.6"
+ attribute \src "libresoc.v:110829.3-110880.6"
wire width 2 $1\dec31_dec_sub26_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub26_upd
- attribute \src "libresoc.v:110032.7-110032.15"
+ attribute \src "libresoc.v:109857.7-109857.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:110032.7-110032.20"
- process $proc$libresoc.v:110032$4292
+ attribute \src "libresoc.v:109857.7-109857.20"
+ process $proc$libresoc.v:109857$4276
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:110380.3-110431.6"
- process $proc$libresoc.v:110380$4259
+ attribute \src "libresoc.v:110205.3-110256.6"
+ process $proc$libresoc.v:110205$4243
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0]
- attribute \src "libresoc.v:110381.5-110381.29"
+ attribute \src "libresoc.v:110206.5-110206.29"
switch \initial
- attribute \src "libresoc.v:110381.9-110381.17"
+ attribute \src "libresoc.v:110206.9-110206.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0]
end
- attribute \src "libresoc.v:110432.3-110483.6"
- process $proc$libresoc.v:110432$4260
+ attribute \src "libresoc.v:110257.3-110308.6"
+ process $proc$libresoc.v:110257$4244
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:110433.5-110433.29"
+ attribute \src "libresoc.v:110258.5-110258.29"
switch \initial
- attribute \src "libresoc.v:110433.9-110433.17"
+ attribute \src "libresoc.v:110258.9-110258.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0]
end
- attribute \src "libresoc.v:110484.3-110535.6"
- process $proc$libresoc.v:110484$4261
+ attribute \src "libresoc.v:110309.3-110360.6"
+ process $proc$libresoc.v:110309$4245
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:110485.5-110485.29"
+ attribute \src "libresoc.v:110310.5-110310.29"
switch \initial
- attribute \src "libresoc.v:110485.9-110485.17"
+ attribute \src "libresoc.v:110310.9-110310.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0]
end
- attribute \src "libresoc.v:110536.3-110587.6"
- process $proc$libresoc.v:110536$4262
+ attribute \src "libresoc.v:110361.3-110412.6"
+ process $proc$libresoc.v:110361$4246
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:110537.5-110537.29"
+ attribute \src "libresoc.v:110362.5-110362.29"
switch \initial
- attribute \src "libresoc.v:110537.9-110537.17"
+ attribute \src "libresoc.v:110362.9-110362.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0]
end
- attribute \src "libresoc.v:110588.3-110639.6"
- process $proc$libresoc.v:110588$4263
+ attribute \src "libresoc.v:110413.3-110464.6"
+ process $proc$libresoc.v:110413$4247
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:110589.5-110589.29"
+ attribute \src "libresoc.v:110414.5-110414.29"
switch \initial
- attribute \src "libresoc.v:110589.9-110589.17"
+ attribute \src "libresoc.v:110414.9-110414.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0]
end
- attribute \src "libresoc.v:110640.3-110691.6"
- process $proc$libresoc.v:110640$4264
+ attribute \src "libresoc.v:110465.3-110516.6"
+ process $proc$libresoc.v:110465$4248
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:110641.5-110641.29"
+ attribute \src "libresoc.v:110466.5-110466.29"
switch \initial
- attribute \src "libresoc.v:110641.9-110641.17"
+ attribute \src "libresoc.v:110466.9-110466.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0]
end
- attribute \src "libresoc.v:110692.3-110743.6"
- process $proc$libresoc.v:110692$4265
+ attribute \src "libresoc.v:110517.3-110568.6"
+ process $proc$libresoc.v:110517$4249
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:110693.5-110693.29"
+ attribute \src "libresoc.v:110518.5-110518.29"
switch \initial
- attribute \src "libresoc.v:110693.9-110693.17"
+ attribute \src "libresoc.v:110518.9-110518.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0]
end
- attribute \src "libresoc.v:110744.3-110795.6"
- process $proc$libresoc.v:110744$4266
+ attribute \src "libresoc.v:110569.3-110620.6"
+ process $proc$libresoc.v:110569$4250
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0]
- attribute \src "libresoc.v:110745.5-110745.29"
+ attribute \src "libresoc.v:110570.5-110570.29"
switch \initial
- attribute \src "libresoc.v:110745.9-110745.17"
+ attribute \src "libresoc.v:110570.9-110570.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0]
end
- attribute \src "libresoc.v:110796.3-110847.6"
- process $proc$libresoc.v:110796$4267
+ attribute \src "libresoc.v:110621.3-110672.6"
+ process $proc$libresoc.v:110621$4251
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:110797.5-110797.29"
+ attribute \src "libresoc.v:110622.5-110622.29"
switch \initial
- attribute \src "libresoc.v:110797.9-110797.17"
+ attribute \src "libresoc.v:110622.9-110622.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:110848.3-110899.6"
- process $proc$libresoc.v:110848$4268
+ attribute \src "libresoc.v:110673.3-110724.6"
+ process $proc$libresoc.v:110673$4252
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:110849.5-110849.29"
+ attribute \src "libresoc.v:110674.5-110674.29"
switch \initial
- attribute \src "libresoc.v:110849.9-110849.17"
+ attribute \src "libresoc.v:110674.9-110674.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:110900.3-110951.6"
- process $proc$libresoc.v:110900$4269
+ attribute \src "libresoc.v:110725.3-110776.6"
+ process $proc$libresoc.v:110725$4253
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:110901.5-110901.29"
+ attribute \src "libresoc.v:110726.5-110726.29"
switch \initial
- attribute \src "libresoc.v:110901.9-110901.17"
+ attribute \src "libresoc.v:110726.9-110726.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0]
end
- attribute \src "libresoc.v:110952.3-111003.6"
- process $proc$libresoc.v:110952$4270
+ attribute \src "libresoc.v:110777.3-110828.6"
+ process $proc$libresoc.v:110777$4254
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:110953.5-110953.29"
+ attribute \src "libresoc.v:110778.5-110778.29"
switch \initial
- attribute \src "libresoc.v:110953.9-110953.17"
+ attribute \src "libresoc.v:110778.9-110778.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0]
end
- attribute \src "libresoc.v:111004.3-111055.6"
- process $proc$libresoc.v:111004$4271
+ attribute \src "libresoc.v:110829.3-110880.6"
+ process $proc$libresoc.v:110829$4255
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:111005.5-111005.29"
+ attribute \src "libresoc.v:110830.5-110830.29"
switch \initial
- attribute \src "libresoc.v:111005.9-111005.17"
+ attribute \src "libresoc.v:110830.9-110830.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0]
end
- attribute \src "libresoc.v:111056.3-111107.6"
- process $proc$libresoc.v:111056$4272
+ attribute \src "libresoc.v:110881.3-110932.6"
+ process $proc$libresoc.v:110881$4256
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:111057.5-111057.29"
+ attribute \src "libresoc.v:110882.5-110882.29"
switch \initial
- attribute \src "libresoc.v:111057.9-111057.17"
+ attribute \src "libresoc.v:110882.9-110882.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0]
end
- attribute \src "libresoc.v:111108.3-111159.6"
- process $proc$libresoc.v:111108$4273
+ attribute \src "libresoc.v:110933.3-110984.6"
+ process $proc$libresoc.v:110933$4257
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:111109.5-111109.29"
+ attribute \src "libresoc.v:110934.5-110934.29"
switch \initial
- attribute \src "libresoc.v:111109.9-111109.17"
+ attribute \src "libresoc.v:110934.9-110934.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0]
end
- attribute \src "libresoc.v:111160.3-111211.6"
- process $proc$libresoc.v:111160$4274
+ attribute \src "libresoc.v:110985.3-111036.6"
+ process $proc$libresoc.v:110985$4258
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:111161.5-111161.29"
+ attribute \src "libresoc.v:110986.5-110986.29"
switch \initial
- attribute \src "libresoc.v:111161.9-111161.17"
+ attribute \src "libresoc.v:110986.9-110986.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0]
end
- attribute \src "libresoc.v:111212.3-111263.6"
- process $proc$libresoc.v:111212$4275
+ attribute \src "libresoc.v:111037.3-111088.6"
+ process $proc$libresoc.v:111037$4259
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:111213.5-111213.29"
+ attribute \src "libresoc.v:111038.5-111038.29"
switch \initial
- attribute \src "libresoc.v:111213.9-111213.17"
+ attribute \src "libresoc.v:111038.9-111038.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0]
end
- attribute \src "libresoc.v:111264.3-111315.6"
- process $proc$libresoc.v:111264$4276
+ attribute \src "libresoc.v:111089.3-111140.6"
+ process $proc$libresoc.v:111089$4260
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:111265.5-111265.29"
+ attribute \src "libresoc.v:111090.5-111090.29"
switch \initial
- attribute \src "libresoc.v:111265.9-111265.17"
+ attribute \src "libresoc.v:111090.9-111090.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0]
end
- attribute \src "libresoc.v:111316.3-111367.6"
- process $proc$libresoc.v:111316$4277
+ attribute \src "libresoc.v:111141.3-111192.6"
+ process $proc$libresoc.v:111141$4261
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:111317.5-111317.29"
+ attribute \src "libresoc.v:111142.5-111142.29"
switch \initial
- attribute \src "libresoc.v:111317.9-111317.17"
+ attribute \src "libresoc.v:111142.9-111142.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0]
end
- attribute \src "libresoc.v:111368.3-111419.6"
- process $proc$libresoc.v:111368$4278
+ attribute \src "libresoc.v:111193.3-111244.6"
+ process $proc$libresoc.v:111193$4262
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:111369.5-111369.29"
+ attribute \src "libresoc.v:111194.5-111194.29"
switch \initial
- attribute \src "libresoc.v:111369.9-111369.17"
+ attribute \src "libresoc.v:111194.9-111194.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0]
end
- attribute \src "libresoc.v:111420.3-111471.6"
- process $proc$libresoc.v:111420$4279
+ attribute \src "libresoc.v:111245.3-111296.6"
+ process $proc$libresoc.v:111245$4263
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:111421.5-111421.29"
+ attribute \src "libresoc.v:111246.5-111246.29"
switch \initial
- attribute \src "libresoc.v:111421.9-111421.17"
+ attribute \src "libresoc.v:111246.9-111246.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0]
end
- attribute \src "libresoc.v:111472.3-111523.6"
- process $proc$libresoc.v:111472$4280
+ attribute \src "libresoc.v:111297.3-111348.6"
+ process $proc$libresoc.v:111297$4264
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:111473.5-111473.29"
+ attribute \src "libresoc.v:111298.5-111298.29"
switch \initial
- attribute \src "libresoc.v:111473.9-111473.17"
+ attribute \src "libresoc.v:111298.9-111298.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0]
end
- attribute \src "libresoc.v:111524.3-111575.6"
- process $proc$libresoc.v:111524$4281
+ attribute \src "libresoc.v:111349.3-111400.6"
+ process $proc$libresoc.v:111349$4265
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:111525.5-111525.29"
+ attribute \src "libresoc.v:111350.5-111350.29"
switch \initial
- attribute \src "libresoc.v:111525.9-111525.17"
+ attribute \src "libresoc.v:111350.9-111350.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0]
end
- attribute \src "libresoc.v:111576.3-111627.6"
- process $proc$libresoc.v:111576$4282
+ attribute \src "libresoc.v:111401.3-111452.6"
+ process $proc$libresoc.v:111401$4266
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:111577.5-111577.29"
+ attribute \src "libresoc.v:111402.5-111402.29"
switch \initial
- attribute \src "libresoc.v:111577.9-111577.17"
+ attribute \src "libresoc.v:111402.9-111402.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0]
end
- attribute \src "libresoc.v:111628.3-111679.6"
- process $proc$libresoc.v:111628$4283
+ attribute \src "libresoc.v:111453.3-111504.6"
+ process $proc$libresoc.v:111453$4267
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:111629.5-111629.29"
+ attribute \src "libresoc.v:111454.5-111454.29"
switch \initial
- attribute \src "libresoc.v:111629.9-111629.17"
+ attribute \src "libresoc.v:111454.9-111454.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0]
end
- attribute \src "libresoc.v:111680.3-111731.6"
- process $proc$libresoc.v:111680$4284
+ attribute \src "libresoc.v:111505.3-111556.6"
+ process $proc$libresoc.v:111505$4268
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:111681.5-111681.29"
+ attribute \src "libresoc.v:111506.5-111506.29"
switch \initial
- attribute \src "libresoc.v:111681.9-111681.17"
+ attribute \src "libresoc.v:111506.9-111506.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0]
end
- attribute \src "libresoc.v:111732.3-111783.6"
- process $proc$libresoc.v:111732$4285
+ attribute \src "libresoc.v:111557.3-111608.6"
+ process $proc$libresoc.v:111557$4269
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:111733.5-111733.29"
+ attribute \src "libresoc.v:111558.5-111558.29"
switch \initial
- attribute \src "libresoc.v:111733.9-111733.17"
+ attribute \src "libresoc.v:111558.9-111558.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:111784.3-111835.6"
- process $proc$libresoc.v:111784$4286
+ attribute \src "libresoc.v:111609.3-111660.6"
+ process $proc$libresoc.v:111609$4270
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:111785.5-111785.29"
+ attribute \src "libresoc.v:111610.5-111610.29"
switch \initial
- attribute \src "libresoc.v:111785.9-111785.17"
+ attribute \src "libresoc.v:111610.9-111610.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0]
end
- attribute \src "libresoc.v:111836.3-111887.6"
- process $proc$libresoc.v:111836$4287
+ attribute \src "libresoc.v:111661.3-111712.6"
+ process $proc$libresoc.v:111661$4271
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:111837.5-111837.29"
+ attribute \src "libresoc.v:111662.5-111662.29"
switch \initial
- attribute \src "libresoc.v:111837.9-111837.17"
+ attribute \src "libresoc.v:111662.9-111662.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:111888.3-111939.6"
- process $proc$libresoc.v:111888$4288
+ attribute \src "libresoc.v:111713.3-111764.6"
+ process $proc$libresoc.v:111713$4272
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:111889.5-111889.29"
+ attribute \src "libresoc.v:111714.5-111714.29"
switch \initial
- attribute \src "libresoc.v:111889.9-111889.17"
+ attribute \src "libresoc.v:111714.9-111714.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0]
end
- attribute \src "libresoc.v:111940.3-111991.6"
- process $proc$libresoc.v:111940$4289
+ attribute \src "libresoc.v:111765.3-111816.6"
+ process $proc$libresoc.v:111765$4273
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:111941.5-111941.29"
+ attribute \src "libresoc.v:111766.5-111766.29"
switch \initial
- attribute \src "libresoc.v:111941.9-111941.17"
+ attribute \src "libresoc.v:111766.9-111766.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0]
end
- attribute \src "libresoc.v:111992.3-112043.6"
- process $proc$libresoc.v:111992$4290
+ attribute \src "libresoc.v:111817.3-111868.6"
+ process $proc$libresoc.v:111817$4274
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:111993.5-111993.29"
+ attribute \src "libresoc.v:111818.5-111818.29"
switch \initial
- attribute \src "libresoc.v:111993.9-111993.17"
+ attribute \src "libresoc.v:111818.9-111818.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0]
end
- attribute \src "libresoc.v:112044.3-112095.6"
- process $proc$libresoc.v:112044$4291
+ attribute \src "libresoc.v:111869.3-111920.6"
+ process $proc$libresoc.v:111869$4275
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0]
- attribute \src "libresoc.v:112045.5-112045.29"
+ attribute \src "libresoc.v:111870.5-111870.29"
switch \initial
- attribute \src "libresoc.v:112045.9-112045.17"
+ attribute \src "libresoc.v:111870.9-111870.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:112101.1-113078.10"
+attribute \src "libresoc.v:111926.1-112903.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27"
attribute \generator "nMigen"
module \dec31_dec_sub27
- attribute \src "libresoc.v:112963.3-112981.6"
+ attribute \src "libresoc.v:112788.3-112806.6"
wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:112982.3-113000.6"
+ attribute \src "libresoc.v:112807.3-112825.6"
wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:112735.3-112753.6"
+ attribute \src "libresoc.v:112560.3-112578.6"
wire width 8 $0\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:112811.3-112829.6"
+ attribute \src "libresoc.v:112636.3-112654.6"
wire $0\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:112469.3-112487.6"
+ attribute \src "libresoc.v:112294.3-112312.6"
wire width 3 $0\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:112488.3-112506.6"
+ attribute \src "libresoc.v:112313.3-112331.6"
wire width 3 $0\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:112716.3-112734.6"
+ attribute \src "libresoc.v:112541.3-112559.6"
wire width 2 $0\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:112792.3-112810.6"
+ attribute \src "libresoc.v:112617.3-112635.6"
wire $0\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:112868.3-112886.6"
+ attribute \src "libresoc.v:112693.3-112711.6"
wire width 5 $0\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:112450.3-112468.6"
+ attribute \src "libresoc.v:112275.3-112293.6"
wire width 14 $0\dec31_dec_sub27_function_unit[13:0]
- attribute \src "libresoc.v:113001.3-113019.6"
+ attribute \src "libresoc.v:112826.3-112844.6"
wire width 3 $0\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:113020.3-113038.6"
+ attribute \src "libresoc.v:112845.3-112863.6"
wire width 4 $0\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:113039.3-113057.6"
+ attribute \src "libresoc.v:112864.3-112882.6"
wire width 2 $0\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:112659.3-112677.6"
+ attribute \src "libresoc.v:112484.3-112502.6"
wire width 7 $0\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:112754.3-112772.6"
+ attribute \src "libresoc.v:112579.3-112597.6"
wire $0\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:112773.3-112791.6"
+ attribute \src "libresoc.v:112598.3-112616.6"
wire $0\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:112887.3-112905.6"
+ attribute \src "libresoc.v:112712.3-112730.6"
wire $0\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:112640.3-112658.6"
+ attribute \src "libresoc.v:112465.3-112483.6"
wire width 4 $0\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:112925.3-112943.6"
+ attribute \src "libresoc.v:112750.3-112768.6"
wire $0\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:113058.3-113076.6"
+ attribute \src "libresoc.v:112883.3-112901.6"
wire width 3 $0\dec31_dec_sub27_out_sel[2:0]
- attribute \src "libresoc.v:112697.3-112715.6"
+ attribute \src "libresoc.v:112522.3-112540.6"
wire width 2 $0\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:112849.3-112867.6"
+ attribute \src "libresoc.v:112674.3-112692.6"
wire $0\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:112944.3-112962.6"
+ attribute \src "libresoc.v:112769.3-112787.6"
wire $0\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:112906.3-112924.6"
+ attribute \src "libresoc.v:112731.3-112749.6"
wire $0\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:112830.3-112848.6"
+ attribute \src "libresoc.v:112655.3-112673.6"
wire $0\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:112602.3-112620.6"
+ attribute \src "libresoc.v:112427.3-112445.6"
wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:112621.3-112639.6"
+ attribute \src "libresoc.v:112446.3-112464.6"
wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:112507.3-112525.6"
+ attribute \src "libresoc.v:112332.3-112350.6"
wire width 3 $0\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:112526.3-112544.6"
+ attribute \src "libresoc.v:112351.3-112369.6"
wire width 3 $0\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:112545.3-112563.6"
+ attribute \src "libresoc.v:112370.3-112388.6"
wire width 3 $0\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:112583.3-112601.6"
+ attribute \src "libresoc.v:112408.3-112426.6"
wire width 3 $0\dec31_dec_sub27_sv_out2[2:0]
- attribute \src "libresoc.v:112564.3-112582.6"
+ attribute \src "libresoc.v:112389.3-112407.6"
wire width 3 $0\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:112678.3-112696.6"
+ attribute \src "libresoc.v:112503.3-112521.6"
wire width 2 $0\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:112102.7-112102.20"
+ attribute \src "libresoc.v:111927.7-111927.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:112963.3-112981.6"
+ attribute \src "libresoc.v:112788.3-112806.6"
wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:112982.3-113000.6"
+ attribute \src "libresoc.v:112807.3-112825.6"
wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:112735.3-112753.6"
+ attribute \src "libresoc.v:112560.3-112578.6"
wire width 8 $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:112811.3-112829.6"
+ attribute \src "libresoc.v:112636.3-112654.6"
wire $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:112469.3-112487.6"
+ attribute \src "libresoc.v:112294.3-112312.6"
wire width 3 $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:112488.3-112506.6"
+ attribute \src "libresoc.v:112313.3-112331.6"
wire width 3 $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:112716.3-112734.6"
+ attribute \src "libresoc.v:112541.3-112559.6"
wire width 2 $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:112792.3-112810.6"
+ attribute \src "libresoc.v:112617.3-112635.6"
wire $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:112868.3-112886.6"
+ attribute \src "libresoc.v:112693.3-112711.6"
wire width 5 $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:112450.3-112468.6"
+ attribute \src "libresoc.v:112275.3-112293.6"
wire width 14 $1\dec31_dec_sub27_function_unit[13:0]
- attribute \src "libresoc.v:113001.3-113019.6"
+ attribute \src "libresoc.v:112826.3-112844.6"
wire width 3 $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:113020.3-113038.6"
+ attribute \src "libresoc.v:112845.3-112863.6"
wire width 4 $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:113039.3-113057.6"
+ attribute \src "libresoc.v:112864.3-112882.6"
wire width 2 $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:112659.3-112677.6"
+ attribute \src "libresoc.v:112484.3-112502.6"
wire width 7 $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:112754.3-112772.6"
+ attribute \src "libresoc.v:112579.3-112597.6"
wire $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:112773.3-112791.6"
+ attribute \src "libresoc.v:112598.3-112616.6"
wire $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:112887.3-112905.6"
+ attribute \src "libresoc.v:112712.3-112730.6"
wire $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:112640.3-112658.6"
+ attribute \src "libresoc.v:112465.3-112483.6"
wire width 4 $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:112925.3-112943.6"
+ attribute \src "libresoc.v:112750.3-112768.6"
wire $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:113058.3-113076.6"
+ attribute \src "libresoc.v:112883.3-112901.6"
wire width 3 $1\dec31_dec_sub27_out_sel[2:0]
- attribute \src "libresoc.v:112697.3-112715.6"
+ attribute \src "libresoc.v:112522.3-112540.6"
wire width 2 $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:112849.3-112867.6"
+ attribute \src "libresoc.v:112674.3-112692.6"
wire $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:112944.3-112962.6"
+ attribute \src "libresoc.v:112769.3-112787.6"
wire $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:112906.3-112924.6"
+ attribute \src "libresoc.v:112731.3-112749.6"
wire $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:112830.3-112848.6"
+ attribute \src "libresoc.v:112655.3-112673.6"
wire $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:112602.3-112620.6"
+ attribute \src "libresoc.v:112427.3-112445.6"
wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:112621.3-112639.6"
+ attribute \src "libresoc.v:112446.3-112464.6"
wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:112507.3-112525.6"
+ attribute \src "libresoc.v:112332.3-112350.6"
wire width 3 $1\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:112526.3-112544.6"
+ attribute \src "libresoc.v:112351.3-112369.6"
wire width 3 $1\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:112545.3-112563.6"
+ attribute \src "libresoc.v:112370.3-112388.6"
wire width 3 $1\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:112583.3-112601.6"
+ attribute \src "libresoc.v:112408.3-112426.6"
wire width 3 $1\dec31_dec_sub27_sv_out2[2:0]
- attribute \src "libresoc.v:112564.3-112582.6"
+ attribute \src "libresoc.v:112389.3-112407.6"
wire width 3 $1\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:112678.3-112696.6"
+ attribute \src "libresoc.v:112503.3-112521.6"
wire width 2 $1\dec31_dec_sub27_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub27_upd
- attribute \src "libresoc.v:112102.7-112102.15"
+ attribute \src "libresoc.v:111927.7-111927.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:112102.7-112102.20"
- process $proc$libresoc.v:112102$4326
+ attribute \src "libresoc.v:111927.7-111927.20"
+ process $proc$libresoc.v:111927$4310
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:112450.3-112468.6"
- process $proc$libresoc.v:112450$4293
+ attribute \src "libresoc.v:112275.3-112293.6"
+ process $proc$libresoc.v:112275$4277
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0]
- attribute \src "libresoc.v:112451.5-112451.29"
+ attribute \src "libresoc.v:112276.5-112276.29"
switch \initial
- attribute \src "libresoc.v:112451.9-112451.17"
+ attribute \src "libresoc.v:112276.9-112276.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0]
end
- attribute \src "libresoc.v:112469.3-112487.6"
- process $proc$libresoc.v:112469$4294
+ attribute \src "libresoc.v:112294.3-112312.6"
+ process $proc$libresoc.v:112294$4278
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:112470.5-112470.29"
+ attribute \src "libresoc.v:112295.5-112295.29"
switch \initial
- attribute \src "libresoc.v:112470.9-112470.17"
+ attribute \src "libresoc.v:112295.9-112295.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0]
end
- attribute \src "libresoc.v:112488.3-112506.6"
- process $proc$libresoc.v:112488$4295
+ attribute \src "libresoc.v:112313.3-112331.6"
+ process $proc$libresoc.v:112313$4279
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:112489.5-112489.29"
+ attribute \src "libresoc.v:112314.5-112314.29"
switch \initial
- attribute \src "libresoc.v:112489.9-112489.17"
+ attribute \src "libresoc.v:112314.9-112314.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0]
end
- attribute \src "libresoc.v:112507.3-112525.6"
- process $proc$libresoc.v:112507$4296
+ attribute \src "libresoc.v:112332.3-112350.6"
+ process $proc$libresoc.v:112332$4280
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:112508.5-112508.29"
+ attribute \src "libresoc.v:112333.5-112333.29"
switch \initial
- attribute \src "libresoc.v:112508.9-112508.17"
+ attribute \src "libresoc.v:112333.9-112333.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0]
end
- attribute \src "libresoc.v:112526.3-112544.6"
- process $proc$libresoc.v:112526$4297
+ attribute \src "libresoc.v:112351.3-112369.6"
+ process $proc$libresoc.v:112351$4281
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:112527.5-112527.29"
+ attribute \src "libresoc.v:112352.5-112352.29"
switch \initial
- attribute \src "libresoc.v:112527.9-112527.17"
+ attribute \src "libresoc.v:112352.9-112352.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0]
end
- attribute \src "libresoc.v:112545.3-112563.6"
- process $proc$libresoc.v:112545$4298
+ attribute \src "libresoc.v:112370.3-112388.6"
+ process $proc$libresoc.v:112370$4282
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:112546.5-112546.29"
+ attribute \src "libresoc.v:112371.5-112371.29"
switch \initial
- attribute \src "libresoc.v:112546.9-112546.17"
+ attribute \src "libresoc.v:112371.9-112371.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0]
end
- attribute \src "libresoc.v:112564.3-112582.6"
- process $proc$libresoc.v:112564$4299
+ attribute \src "libresoc.v:112389.3-112407.6"
+ process $proc$libresoc.v:112389$4283
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:112565.5-112565.29"
+ attribute \src "libresoc.v:112390.5-112390.29"
switch \initial
- attribute \src "libresoc.v:112565.9-112565.17"
+ attribute \src "libresoc.v:112390.9-112390.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0]
end
- attribute \src "libresoc.v:112583.3-112601.6"
- process $proc$libresoc.v:112583$4300
+ attribute \src "libresoc.v:112408.3-112426.6"
+ process $proc$libresoc.v:112408$4284
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0]
- attribute \src "libresoc.v:112584.5-112584.29"
+ attribute \src "libresoc.v:112409.5-112409.29"
switch \initial
- attribute \src "libresoc.v:112584.9-112584.17"
+ attribute \src "libresoc.v:112409.9-112409.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0]
end
- attribute \src "libresoc.v:112602.3-112620.6"
- process $proc$libresoc.v:112602$4301
+ attribute \src "libresoc.v:112427.3-112445.6"
+ process $proc$libresoc.v:112427$4285
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:112603.5-112603.29"
+ attribute \src "libresoc.v:112428.5-112428.29"
switch \initial
- attribute \src "libresoc.v:112603.9-112603.17"
+ attribute \src "libresoc.v:112428.9-112428.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:112621.3-112639.6"
- process $proc$libresoc.v:112621$4302
+ attribute \src "libresoc.v:112446.3-112464.6"
+ process $proc$libresoc.v:112446$4286
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:112622.5-112622.29"
+ attribute \src "libresoc.v:112447.5-112447.29"
switch \initial
- attribute \src "libresoc.v:112622.9-112622.17"
+ attribute \src "libresoc.v:112447.9-112447.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:112640.3-112658.6"
- process $proc$libresoc.v:112640$4303
+ attribute \src "libresoc.v:112465.3-112483.6"
+ process $proc$libresoc.v:112465$4287
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:112641.5-112641.29"
+ attribute \src "libresoc.v:112466.5-112466.29"
switch \initial
- attribute \src "libresoc.v:112641.9-112641.17"
+ attribute \src "libresoc.v:112466.9-112466.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0]
end
- attribute \src "libresoc.v:112659.3-112677.6"
- process $proc$libresoc.v:112659$4304
+ attribute \src "libresoc.v:112484.3-112502.6"
+ process $proc$libresoc.v:112484$4288
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:112660.5-112660.29"
+ attribute \src "libresoc.v:112485.5-112485.29"
switch \initial
- attribute \src "libresoc.v:112660.9-112660.17"
+ attribute \src "libresoc.v:112485.9-112485.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0]
end
- attribute \src "libresoc.v:112678.3-112696.6"
- process $proc$libresoc.v:112678$4305
+ attribute \src "libresoc.v:112503.3-112521.6"
+ process $proc$libresoc.v:112503$4289
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:112679.5-112679.29"
+ attribute \src "libresoc.v:112504.5-112504.29"
switch \initial
- attribute \src "libresoc.v:112679.9-112679.17"
+ attribute \src "libresoc.v:112504.9-112504.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0]
end
- attribute \src "libresoc.v:112697.3-112715.6"
- process $proc$libresoc.v:112697$4306
+ attribute \src "libresoc.v:112522.3-112540.6"
+ process $proc$libresoc.v:112522$4290
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:112698.5-112698.29"
+ attribute \src "libresoc.v:112523.5-112523.29"
switch \initial
- attribute \src "libresoc.v:112698.9-112698.17"
+ attribute \src "libresoc.v:112523.9-112523.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0]
end
- attribute \src "libresoc.v:112716.3-112734.6"
- process $proc$libresoc.v:112716$4307
+ attribute \src "libresoc.v:112541.3-112559.6"
+ process $proc$libresoc.v:112541$4291
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:112717.5-112717.29"
+ attribute \src "libresoc.v:112542.5-112542.29"
switch \initial
- attribute \src "libresoc.v:112717.9-112717.17"
+ attribute \src "libresoc.v:112542.9-112542.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0]
end
- attribute \src "libresoc.v:112735.3-112753.6"
- process $proc$libresoc.v:112735$4308
+ attribute \src "libresoc.v:112560.3-112578.6"
+ process $proc$libresoc.v:112560$4292
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:112736.5-112736.29"
+ attribute \src "libresoc.v:112561.5-112561.29"
switch \initial
- attribute \src "libresoc.v:112736.9-112736.17"
+ attribute \src "libresoc.v:112561.9-112561.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0]
end
- attribute \src "libresoc.v:112754.3-112772.6"
- process $proc$libresoc.v:112754$4309
+ attribute \src "libresoc.v:112579.3-112597.6"
+ process $proc$libresoc.v:112579$4293
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:112755.5-112755.29"
+ attribute \src "libresoc.v:112580.5-112580.29"
switch \initial
- attribute \src "libresoc.v:112755.9-112755.17"
+ attribute \src "libresoc.v:112580.9-112580.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0]
end
- attribute \src "libresoc.v:112773.3-112791.6"
- process $proc$libresoc.v:112773$4310
+ attribute \src "libresoc.v:112598.3-112616.6"
+ process $proc$libresoc.v:112598$4294
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:112774.5-112774.29"
+ attribute \src "libresoc.v:112599.5-112599.29"
switch \initial
- attribute \src "libresoc.v:112774.9-112774.17"
+ attribute \src "libresoc.v:112599.9-112599.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0]
end
- attribute \src "libresoc.v:112792.3-112810.6"
- process $proc$libresoc.v:112792$4311
+ attribute \src "libresoc.v:112617.3-112635.6"
+ process $proc$libresoc.v:112617$4295
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:112793.5-112793.29"
+ attribute \src "libresoc.v:112618.5-112618.29"
switch \initial
- attribute \src "libresoc.v:112793.9-112793.17"
+ attribute \src "libresoc.v:112618.9-112618.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0]
end
- attribute \src "libresoc.v:112811.3-112829.6"
- process $proc$libresoc.v:112811$4312
+ attribute \src "libresoc.v:112636.3-112654.6"
+ process $proc$libresoc.v:112636$4296
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:112812.5-112812.29"
+ attribute \src "libresoc.v:112637.5-112637.29"
switch \initial
- attribute \src "libresoc.v:112812.9-112812.17"
+ attribute \src "libresoc.v:112637.9-112637.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0]
end
- attribute \src "libresoc.v:112830.3-112848.6"
- process $proc$libresoc.v:112830$4313
+ attribute \src "libresoc.v:112655.3-112673.6"
+ process $proc$libresoc.v:112655$4297
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:112831.5-112831.29"
+ attribute \src "libresoc.v:112656.5-112656.29"
switch \initial
- attribute \src "libresoc.v:112831.9-112831.17"
+ attribute \src "libresoc.v:112656.9-112656.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0]
end
- attribute \src "libresoc.v:112849.3-112867.6"
- process $proc$libresoc.v:112849$4314
+ attribute \src "libresoc.v:112674.3-112692.6"
+ process $proc$libresoc.v:112674$4298
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:112850.5-112850.29"
+ attribute \src "libresoc.v:112675.5-112675.29"
switch \initial
- attribute \src "libresoc.v:112850.9-112850.17"
+ attribute \src "libresoc.v:112675.9-112675.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0]
end
- attribute \src "libresoc.v:112868.3-112886.6"
- process $proc$libresoc.v:112868$4315
+ attribute \src "libresoc.v:112693.3-112711.6"
+ process $proc$libresoc.v:112693$4299
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:112869.5-112869.29"
+ attribute \src "libresoc.v:112694.5-112694.29"
switch \initial
- attribute \src "libresoc.v:112869.9-112869.17"
+ attribute \src "libresoc.v:112694.9-112694.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0]
end
- attribute \src "libresoc.v:112887.3-112905.6"
- process $proc$libresoc.v:112887$4316
+ attribute \src "libresoc.v:112712.3-112730.6"
+ process $proc$libresoc.v:112712$4300
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:112888.5-112888.29"
+ attribute \src "libresoc.v:112713.5-112713.29"
switch \initial
- attribute \src "libresoc.v:112888.9-112888.17"
+ attribute \src "libresoc.v:112713.9-112713.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0]
end
- attribute \src "libresoc.v:112906.3-112924.6"
- process $proc$libresoc.v:112906$4317
+ attribute \src "libresoc.v:112731.3-112749.6"
+ process $proc$libresoc.v:112731$4301
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:112907.5-112907.29"
+ attribute \src "libresoc.v:112732.5-112732.29"
switch \initial
- attribute \src "libresoc.v:112907.9-112907.17"
+ attribute \src "libresoc.v:112732.9-112732.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0]
end
- attribute \src "libresoc.v:112925.3-112943.6"
- process $proc$libresoc.v:112925$4318
+ attribute \src "libresoc.v:112750.3-112768.6"
+ process $proc$libresoc.v:112750$4302
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:112926.5-112926.29"
+ attribute \src "libresoc.v:112751.5-112751.29"
switch \initial
- attribute \src "libresoc.v:112926.9-112926.17"
+ attribute \src "libresoc.v:112751.9-112751.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0]
end
- attribute \src "libresoc.v:112944.3-112962.6"
- process $proc$libresoc.v:112944$4319
+ attribute \src "libresoc.v:112769.3-112787.6"
+ process $proc$libresoc.v:112769$4303
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:112945.5-112945.29"
+ attribute \src "libresoc.v:112770.5-112770.29"
switch \initial
- attribute \src "libresoc.v:112945.9-112945.17"
+ attribute \src "libresoc.v:112770.9-112770.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:112963.3-112981.6"
- process $proc$libresoc.v:112963$4320
+ attribute \src "libresoc.v:112788.3-112806.6"
+ process $proc$libresoc.v:112788$4304
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:112964.5-112964.29"
+ attribute \src "libresoc.v:112789.5-112789.29"
switch \initial
- attribute \src "libresoc.v:112964.9-112964.17"
+ attribute \src "libresoc.v:112789.9-112789.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0]
end
- attribute \src "libresoc.v:112982.3-113000.6"
- process $proc$libresoc.v:112982$4321
+ attribute \src "libresoc.v:112807.3-112825.6"
+ process $proc$libresoc.v:112807$4305
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:112983.5-112983.29"
+ attribute \src "libresoc.v:112808.5-112808.29"
switch \initial
- attribute \src "libresoc.v:112983.9-112983.17"
+ attribute \src "libresoc.v:112808.9-112808.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:113001.3-113019.6"
- process $proc$libresoc.v:113001$4322
+ attribute \src "libresoc.v:112826.3-112844.6"
+ process $proc$libresoc.v:112826$4306
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:113002.5-113002.29"
+ attribute \src "libresoc.v:112827.5-112827.29"
switch \initial
- attribute \src "libresoc.v:113002.9-113002.17"
+ attribute \src "libresoc.v:112827.9-112827.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0]
end
- attribute \src "libresoc.v:113020.3-113038.6"
- process $proc$libresoc.v:113020$4323
+ attribute \src "libresoc.v:112845.3-112863.6"
+ process $proc$libresoc.v:112845$4307
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:113021.5-113021.29"
+ attribute \src "libresoc.v:112846.5-112846.29"
switch \initial
- attribute \src "libresoc.v:113021.9-113021.17"
+ attribute \src "libresoc.v:112846.9-112846.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0]
end
- attribute \src "libresoc.v:113039.3-113057.6"
- process $proc$libresoc.v:113039$4324
+ attribute \src "libresoc.v:112864.3-112882.6"
+ process $proc$libresoc.v:112864$4308
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:113040.5-113040.29"
+ attribute \src "libresoc.v:112865.5-112865.29"
switch \initial
- attribute \src "libresoc.v:113040.9-113040.17"
+ attribute \src "libresoc.v:112865.9-112865.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0]
end
- attribute \src "libresoc.v:113058.3-113076.6"
- process $proc$libresoc.v:113058$4325
+ attribute \src "libresoc.v:112883.3-112901.6"
+ process $proc$libresoc.v:112883$4309
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0]
- attribute \src "libresoc.v:113059.5-113059.29"
+ attribute \src "libresoc.v:112884.5-112884.29"
switch \initial
- attribute \src "libresoc.v:113059.9-113059.17"
+ attribute \src "libresoc.v:112884.9-112884.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:113082.1-114653.10"
+attribute \src "libresoc.v:112907.1-114478.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28"
attribute \generator "nMigen"
module \dec31_dec_sub28
- attribute \src "libresoc.v:114430.3-114466.6"
+ attribute \src "libresoc.v:114255.3-114291.6"
wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:114467.3-114503.6"
+ attribute \src "libresoc.v:114292.3-114328.6"
wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:113986.3-114022.6"
+ attribute \src "libresoc.v:113811.3-113847.6"
wire width 8 $0\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:114134.3-114170.6"
+ attribute \src "libresoc.v:113959.3-113995.6"
wire $0\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:113468.3-113504.6"
+ attribute \src "libresoc.v:113293.3-113329.6"
wire width 3 $0\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:113505.3-113541.6"
+ attribute \src "libresoc.v:113330.3-113366.6"
wire width 3 $0\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:113949.3-113985.6"
+ attribute \src "libresoc.v:113774.3-113810.6"
wire width 2 $0\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:114097.3-114133.6"
+ attribute \src "libresoc.v:113922.3-113958.6"
wire $0\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:114245.3-114281.6"
+ attribute \src "libresoc.v:114070.3-114106.6"
wire width 5 $0\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:113431.3-113467.6"
+ attribute \src "libresoc.v:113256.3-113292.6"
wire width 14 $0\dec31_dec_sub28_function_unit[13:0]
- attribute \src "libresoc.v:114504.3-114540.6"
+ attribute \src "libresoc.v:114329.3-114365.6"
wire width 3 $0\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:114541.3-114577.6"
+ attribute \src "libresoc.v:114366.3-114402.6"
wire width 4 $0\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:114578.3-114614.6"
+ attribute \src "libresoc.v:114403.3-114439.6"
wire width 2 $0\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:113838.3-113874.6"
+ attribute \src "libresoc.v:113663.3-113699.6"
wire width 7 $0\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:114023.3-114059.6"
+ attribute \src "libresoc.v:113848.3-113884.6"
wire $0\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:114060.3-114096.6"
+ attribute \src "libresoc.v:113885.3-113921.6"
wire $0\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:114282.3-114318.6"
+ attribute \src "libresoc.v:114107.3-114143.6"
wire $0\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:113801.3-113837.6"
+ attribute \src "libresoc.v:113626.3-113662.6"
wire width 4 $0\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:114356.3-114392.6"
+ attribute \src "libresoc.v:114181.3-114217.6"
wire $0\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:114615.3-114651.6"
+ attribute \src "libresoc.v:114440.3-114476.6"
wire width 3 $0\dec31_dec_sub28_out_sel[2:0]
- attribute \src "libresoc.v:113912.3-113948.6"
+ attribute \src "libresoc.v:113737.3-113773.6"
wire width 2 $0\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:114208.3-114244.6"
+ attribute \src "libresoc.v:114033.3-114069.6"
wire $0\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:114393.3-114429.6"
+ attribute \src "libresoc.v:114218.3-114254.6"
wire $0\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:114319.3-114355.6"
+ attribute \src "libresoc.v:114144.3-114180.6"
wire $0\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:114171.3-114207.6"
+ attribute \src "libresoc.v:113996.3-114032.6"
wire $0\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:113727.3-113763.6"
+ attribute \src "libresoc.v:113552.3-113588.6"
wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:113764.3-113800.6"
+ attribute \src "libresoc.v:113589.3-113625.6"
wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:113542.3-113578.6"
+ attribute \src "libresoc.v:113367.3-113403.6"
wire width 3 $0\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:113579.3-113615.6"
+ attribute \src "libresoc.v:113404.3-113440.6"
wire width 3 $0\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:113616.3-113652.6"
+ attribute \src "libresoc.v:113441.3-113477.6"
wire width 3 $0\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:113690.3-113726.6"
+ attribute \src "libresoc.v:113515.3-113551.6"
wire width 3 $0\dec31_dec_sub28_sv_out2[2:0]
- attribute \src "libresoc.v:113653.3-113689.6"
+ attribute \src "libresoc.v:113478.3-113514.6"
wire width 3 $0\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:113875.3-113911.6"
+ attribute \src "libresoc.v:113700.3-113736.6"
wire width 2 $0\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:113083.7-113083.20"
+ attribute \src "libresoc.v:112908.7-112908.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:114430.3-114466.6"
+ attribute \src "libresoc.v:114255.3-114291.6"
wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:114467.3-114503.6"
+ attribute \src "libresoc.v:114292.3-114328.6"
wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:113986.3-114022.6"
+ attribute \src "libresoc.v:113811.3-113847.6"
wire width 8 $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:114134.3-114170.6"
+ attribute \src "libresoc.v:113959.3-113995.6"
wire $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:113468.3-113504.6"
+ attribute \src "libresoc.v:113293.3-113329.6"
wire width 3 $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:113505.3-113541.6"
+ attribute \src "libresoc.v:113330.3-113366.6"
wire width 3 $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:113949.3-113985.6"
+ attribute \src "libresoc.v:113774.3-113810.6"
wire width 2 $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:114097.3-114133.6"
+ attribute \src "libresoc.v:113922.3-113958.6"
wire $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:114245.3-114281.6"
+ attribute \src "libresoc.v:114070.3-114106.6"
wire width 5 $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:113431.3-113467.6"
+ attribute \src "libresoc.v:113256.3-113292.6"
wire width 14 $1\dec31_dec_sub28_function_unit[13:0]
- attribute \src "libresoc.v:114504.3-114540.6"
+ attribute \src "libresoc.v:114329.3-114365.6"
wire width 3 $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:114541.3-114577.6"
+ attribute \src "libresoc.v:114366.3-114402.6"
wire width 4 $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:114578.3-114614.6"
+ attribute \src "libresoc.v:114403.3-114439.6"
wire width 2 $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:113838.3-113874.6"
+ attribute \src "libresoc.v:113663.3-113699.6"
wire width 7 $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:114023.3-114059.6"
+ attribute \src "libresoc.v:113848.3-113884.6"
wire $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:114060.3-114096.6"
+ attribute \src "libresoc.v:113885.3-113921.6"
wire $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:114282.3-114318.6"
+ attribute \src "libresoc.v:114107.3-114143.6"
wire $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:113801.3-113837.6"
+ attribute \src "libresoc.v:113626.3-113662.6"
wire width 4 $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:114356.3-114392.6"
+ attribute \src "libresoc.v:114181.3-114217.6"
wire $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:114615.3-114651.6"
+ attribute \src "libresoc.v:114440.3-114476.6"
wire width 3 $1\dec31_dec_sub28_out_sel[2:0]
- attribute \src "libresoc.v:113912.3-113948.6"
+ attribute \src "libresoc.v:113737.3-113773.6"
wire width 2 $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:114208.3-114244.6"
+ attribute \src "libresoc.v:114033.3-114069.6"
wire $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:114393.3-114429.6"
+ attribute \src "libresoc.v:114218.3-114254.6"
wire $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:114319.3-114355.6"
+ attribute \src "libresoc.v:114144.3-114180.6"
wire $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:114171.3-114207.6"
+ attribute \src "libresoc.v:113996.3-114032.6"
wire $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:113727.3-113763.6"
+ attribute \src "libresoc.v:113552.3-113588.6"
wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:113764.3-113800.6"
+ attribute \src "libresoc.v:113589.3-113625.6"
wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:113542.3-113578.6"
+ attribute \src "libresoc.v:113367.3-113403.6"
wire width 3 $1\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:113579.3-113615.6"
+ attribute \src "libresoc.v:113404.3-113440.6"
wire width 3 $1\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:113616.3-113652.6"
+ attribute \src "libresoc.v:113441.3-113477.6"
wire width 3 $1\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:113690.3-113726.6"
+ attribute \src "libresoc.v:113515.3-113551.6"
wire width 3 $1\dec31_dec_sub28_sv_out2[2:0]
- attribute \src "libresoc.v:113653.3-113689.6"
+ attribute \src "libresoc.v:113478.3-113514.6"
wire width 3 $1\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:113875.3-113911.6"
+ attribute \src "libresoc.v:113700.3-113736.6"
wire width 2 $1\dec31_dec_sub28_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub28_upd
- attribute \src "libresoc.v:113083.7-113083.15"
+ attribute \src "libresoc.v:112908.7-112908.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:113083.7-113083.20"
- process $proc$libresoc.v:113083$4360
+ attribute \src "libresoc.v:112908.7-112908.20"
+ process $proc$libresoc.v:112908$4344
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:113431.3-113467.6"
- process $proc$libresoc.v:113431$4327
+ attribute \src "libresoc.v:113256.3-113292.6"
+ process $proc$libresoc.v:113256$4311
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0]
- attribute \src "libresoc.v:113432.5-113432.29"
+ attribute \src "libresoc.v:113257.5-113257.29"
switch \initial
- attribute \src "libresoc.v:113432.9-113432.17"
+ attribute \src "libresoc.v:113257.9-113257.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0]
end
- attribute \src "libresoc.v:113468.3-113504.6"
- process $proc$libresoc.v:113468$4328
+ attribute \src "libresoc.v:113293.3-113329.6"
+ process $proc$libresoc.v:113293$4312
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:113469.5-113469.29"
+ attribute \src "libresoc.v:113294.5-113294.29"
switch \initial
- attribute \src "libresoc.v:113469.9-113469.17"
+ attribute \src "libresoc.v:113294.9-113294.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0]
end
- attribute \src "libresoc.v:113505.3-113541.6"
- process $proc$libresoc.v:113505$4329
+ attribute \src "libresoc.v:113330.3-113366.6"
+ process $proc$libresoc.v:113330$4313
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:113506.5-113506.29"
+ attribute \src "libresoc.v:113331.5-113331.29"
switch \initial
- attribute \src "libresoc.v:113506.9-113506.17"
+ attribute \src "libresoc.v:113331.9-113331.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0]
end
- attribute \src "libresoc.v:113542.3-113578.6"
- process $proc$libresoc.v:113542$4330
+ attribute \src "libresoc.v:113367.3-113403.6"
+ process $proc$libresoc.v:113367$4314
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:113543.5-113543.29"
+ attribute \src "libresoc.v:113368.5-113368.29"
switch \initial
- attribute \src "libresoc.v:113543.9-113543.17"
+ attribute \src "libresoc.v:113368.9-113368.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0]
end
- attribute \src "libresoc.v:113579.3-113615.6"
- process $proc$libresoc.v:113579$4331
+ attribute \src "libresoc.v:113404.3-113440.6"
+ process $proc$libresoc.v:113404$4315
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:113580.5-113580.29"
+ attribute \src "libresoc.v:113405.5-113405.29"
switch \initial
- attribute \src "libresoc.v:113580.9-113580.17"
+ attribute \src "libresoc.v:113405.9-113405.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0]
end
- attribute \src "libresoc.v:113616.3-113652.6"
- process $proc$libresoc.v:113616$4332
+ attribute \src "libresoc.v:113441.3-113477.6"
+ process $proc$libresoc.v:113441$4316
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:113617.5-113617.29"
+ attribute \src "libresoc.v:113442.5-113442.29"
switch \initial
- attribute \src "libresoc.v:113617.9-113617.17"
+ attribute \src "libresoc.v:113442.9-113442.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0]
end
- attribute \src "libresoc.v:113653.3-113689.6"
- process $proc$libresoc.v:113653$4333
+ attribute \src "libresoc.v:113478.3-113514.6"
+ process $proc$libresoc.v:113478$4317
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:113654.5-113654.29"
+ attribute \src "libresoc.v:113479.5-113479.29"
switch \initial
- attribute \src "libresoc.v:113654.9-113654.17"
+ attribute \src "libresoc.v:113479.9-113479.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0]
end
- attribute \src "libresoc.v:113690.3-113726.6"
- process $proc$libresoc.v:113690$4334
+ attribute \src "libresoc.v:113515.3-113551.6"
+ process $proc$libresoc.v:113515$4318
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0]
- attribute \src "libresoc.v:113691.5-113691.29"
+ attribute \src "libresoc.v:113516.5-113516.29"
switch \initial
- attribute \src "libresoc.v:113691.9-113691.17"
+ attribute \src "libresoc.v:113516.9-113516.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0]
end
- attribute \src "libresoc.v:113727.3-113763.6"
- process $proc$libresoc.v:113727$4335
+ attribute \src "libresoc.v:113552.3-113588.6"
+ process $proc$libresoc.v:113552$4319
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:113728.5-113728.29"
+ attribute \src "libresoc.v:113553.5-113553.29"
switch \initial
- attribute \src "libresoc.v:113728.9-113728.17"
+ attribute \src "libresoc.v:113553.9-113553.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:113764.3-113800.6"
- process $proc$libresoc.v:113764$4336
+ attribute \src "libresoc.v:113589.3-113625.6"
+ process $proc$libresoc.v:113589$4320
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:113765.5-113765.29"
+ attribute \src "libresoc.v:113590.5-113590.29"
switch \initial
- attribute \src "libresoc.v:113765.9-113765.17"
+ attribute \src "libresoc.v:113590.9-113590.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:113801.3-113837.6"
- process $proc$libresoc.v:113801$4337
+ attribute \src "libresoc.v:113626.3-113662.6"
+ process $proc$libresoc.v:113626$4321
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:113802.5-113802.29"
+ attribute \src "libresoc.v:113627.5-113627.29"
switch \initial
- attribute \src "libresoc.v:113802.9-113802.17"
+ attribute \src "libresoc.v:113627.9-113627.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0]
end
- attribute \src "libresoc.v:113838.3-113874.6"
- process $proc$libresoc.v:113838$4338
+ attribute \src "libresoc.v:113663.3-113699.6"
+ process $proc$libresoc.v:113663$4322
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:113839.5-113839.29"
+ attribute \src "libresoc.v:113664.5-113664.29"
switch \initial
- attribute \src "libresoc.v:113839.9-113839.17"
+ attribute \src "libresoc.v:113664.9-113664.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0]
end
- attribute \src "libresoc.v:113875.3-113911.6"
- process $proc$libresoc.v:113875$4339
+ attribute \src "libresoc.v:113700.3-113736.6"
+ process $proc$libresoc.v:113700$4323
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:113876.5-113876.29"
+ attribute \src "libresoc.v:113701.5-113701.29"
switch \initial
- attribute \src "libresoc.v:113876.9-113876.17"
+ attribute \src "libresoc.v:113701.9-113701.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0]
end
- attribute \src "libresoc.v:113912.3-113948.6"
- process $proc$libresoc.v:113912$4340
+ attribute \src "libresoc.v:113737.3-113773.6"
+ process $proc$libresoc.v:113737$4324
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:113913.5-113913.29"
+ attribute \src "libresoc.v:113738.5-113738.29"
switch \initial
- attribute \src "libresoc.v:113913.9-113913.17"
+ attribute \src "libresoc.v:113738.9-113738.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0]
end
- attribute \src "libresoc.v:113949.3-113985.6"
- process $proc$libresoc.v:113949$4341
+ attribute \src "libresoc.v:113774.3-113810.6"
+ process $proc$libresoc.v:113774$4325
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:113950.5-113950.29"
+ attribute \src "libresoc.v:113775.5-113775.29"
switch \initial
- attribute \src "libresoc.v:113950.9-113950.17"
+ attribute \src "libresoc.v:113775.9-113775.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0]
end
- attribute \src "libresoc.v:113986.3-114022.6"
- process $proc$libresoc.v:113986$4342
+ attribute \src "libresoc.v:113811.3-113847.6"
+ process $proc$libresoc.v:113811$4326
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:113987.5-113987.29"
+ attribute \src "libresoc.v:113812.5-113812.29"
switch \initial
- attribute \src "libresoc.v:113987.9-113987.17"
+ attribute \src "libresoc.v:113812.9-113812.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0]
end
- attribute \src "libresoc.v:114023.3-114059.6"
- process $proc$libresoc.v:114023$4343
+ attribute \src "libresoc.v:113848.3-113884.6"
+ process $proc$libresoc.v:113848$4327
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:114024.5-114024.29"
+ attribute \src "libresoc.v:113849.5-113849.29"
switch \initial
- attribute \src "libresoc.v:114024.9-114024.17"
+ attribute \src "libresoc.v:113849.9-113849.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0]
end
- attribute \src "libresoc.v:114060.3-114096.6"
- process $proc$libresoc.v:114060$4344
+ attribute \src "libresoc.v:113885.3-113921.6"
+ process $proc$libresoc.v:113885$4328
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:114061.5-114061.29"
+ attribute \src "libresoc.v:113886.5-113886.29"
switch \initial
- attribute \src "libresoc.v:114061.9-114061.17"
+ attribute \src "libresoc.v:113886.9-113886.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0]
end
- attribute \src "libresoc.v:114097.3-114133.6"
- process $proc$libresoc.v:114097$4345
+ attribute \src "libresoc.v:113922.3-113958.6"
+ process $proc$libresoc.v:113922$4329
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:114098.5-114098.29"
+ attribute \src "libresoc.v:113923.5-113923.29"
switch \initial
- attribute \src "libresoc.v:114098.9-114098.17"
+ attribute \src "libresoc.v:113923.9-113923.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0]
end
- attribute \src "libresoc.v:114134.3-114170.6"
- process $proc$libresoc.v:114134$4346
+ attribute \src "libresoc.v:113959.3-113995.6"
+ process $proc$libresoc.v:113959$4330
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:114135.5-114135.29"
+ attribute \src "libresoc.v:113960.5-113960.29"
switch \initial
- attribute \src "libresoc.v:114135.9-114135.17"
+ attribute \src "libresoc.v:113960.9-113960.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0]
end
- attribute \src "libresoc.v:114171.3-114207.6"
- process $proc$libresoc.v:114171$4347
+ attribute \src "libresoc.v:113996.3-114032.6"
+ process $proc$libresoc.v:113996$4331
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:114172.5-114172.29"
+ attribute \src "libresoc.v:113997.5-113997.29"
switch \initial
- attribute \src "libresoc.v:114172.9-114172.17"
+ attribute \src "libresoc.v:113997.9-113997.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0]
end
- attribute \src "libresoc.v:114208.3-114244.6"
- process $proc$libresoc.v:114208$4348
+ attribute \src "libresoc.v:114033.3-114069.6"
+ process $proc$libresoc.v:114033$4332
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:114209.5-114209.29"
+ attribute \src "libresoc.v:114034.5-114034.29"
switch \initial
- attribute \src "libresoc.v:114209.9-114209.17"
+ attribute \src "libresoc.v:114034.9-114034.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0]
end
- attribute \src "libresoc.v:114245.3-114281.6"
- process $proc$libresoc.v:114245$4349
+ attribute \src "libresoc.v:114070.3-114106.6"
+ process $proc$libresoc.v:114070$4333
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:114246.5-114246.29"
+ attribute \src "libresoc.v:114071.5-114071.29"
switch \initial
- attribute \src "libresoc.v:114246.9-114246.17"
+ attribute \src "libresoc.v:114071.9-114071.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0]
end
- attribute \src "libresoc.v:114282.3-114318.6"
- process $proc$libresoc.v:114282$4350
+ attribute \src "libresoc.v:114107.3-114143.6"
+ process $proc$libresoc.v:114107$4334
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:114283.5-114283.29"
+ attribute \src "libresoc.v:114108.5-114108.29"
switch \initial
- attribute \src "libresoc.v:114283.9-114283.17"
+ attribute \src "libresoc.v:114108.9-114108.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0]
end
- attribute \src "libresoc.v:114319.3-114355.6"
- process $proc$libresoc.v:114319$4351
+ attribute \src "libresoc.v:114144.3-114180.6"
+ process $proc$libresoc.v:114144$4335
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:114320.5-114320.29"
+ attribute \src "libresoc.v:114145.5-114145.29"
switch \initial
- attribute \src "libresoc.v:114320.9-114320.17"
+ attribute \src "libresoc.v:114145.9-114145.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0]
end
- attribute \src "libresoc.v:114356.3-114392.6"
- process $proc$libresoc.v:114356$4352
+ attribute \src "libresoc.v:114181.3-114217.6"
+ process $proc$libresoc.v:114181$4336
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:114357.5-114357.29"
+ attribute \src "libresoc.v:114182.5-114182.29"
switch \initial
- attribute \src "libresoc.v:114357.9-114357.17"
+ attribute \src "libresoc.v:114182.9-114182.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0]
end
- attribute \src "libresoc.v:114393.3-114429.6"
- process $proc$libresoc.v:114393$4353
+ attribute \src "libresoc.v:114218.3-114254.6"
+ process $proc$libresoc.v:114218$4337
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:114394.5-114394.29"
+ attribute \src "libresoc.v:114219.5-114219.29"
switch \initial
- attribute \src "libresoc.v:114394.9-114394.17"
+ attribute \src "libresoc.v:114219.9-114219.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:114430.3-114466.6"
- process $proc$libresoc.v:114430$4354
+ attribute \src "libresoc.v:114255.3-114291.6"
+ process $proc$libresoc.v:114255$4338
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:114431.5-114431.29"
+ attribute \src "libresoc.v:114256.5-114256.29"
switch \initial
- attribute \src "libresoc.v:114431.9-114431.17"
+ attribute \src "libresoc.v:114256.9-114256.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0]
end
- attribute \src "libresoc.v:114467.3-114503.6"
- process $proc$libresoc.v:114467$4355
+ attribute \src "libresoc.v:114292.3-114328.6"
+ process $proc$libresoc.v:114292$4339
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:114468.5-114468.29"
+ attribute \src "libresoc.v:114293.5-114293.29"
switch \initial
- attribute \src "libresoc.v:114468.9-114468.17"
+ attribute \src "libresoc.v:114293.9-114293.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:114504.3-114540.6"
- process $proc$libresoc.v:114504$4356
+ attribute \src "libresoc.v:114329.3-114365.6"
+ process $proc$libresoc.v:114329$4340
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:114505.5-114505.29"
+ attribute \src "libresoc.v:114330.5-114330.29"
switch \initial
- attribute \src "libresoc.v:114505.9-114505.17"
+ attribute \src "libresoc.v:114330.9-114330.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0]
end
- attribute \src "libresoc.v:114541.3-114577.6"
- process $proc$libresoc.v:114541$4357
+ attribute \src "libresoc.v:114366.3-114402.6"
+ process $proc$libresoc.v:114366$4341
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:114542.5-114542.29"
+ attribute \src "libresoc.v:114367.5-114367.29"
switch \initial
- attribute \src "libresoc.v:114542.9-114542.17"
+ attribute \src "libresoc.v:114367.9-114367.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0]
end
- attribute \src "libresoc.v:114578.3-114614.6"
- process $proc$libresoc.v:114578$4358
+ attribute \src "libresoc.v:114403.3-114439.6"
+ process $proc$libresoc.v:114403$4342
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:114579.5-114579.29"
+ attribute \src "libresoc.v:114404.5-114404.29"
switch \initial
- attribute \src "libresoc.v:114579.9-114579.17"
+ attribute \src "libresoc.v:114404.9-114404.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0]
end
- attribute \src "libresoc.v:114615.3-114651.6"
- process $proc$libresoc.v:114615$4359
+ attribute \src "libresoc.v:114440.3-114476.6"
+ process $proc$libresoc.v:114440$4343
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0]
- attribute \src "libresoc.v:114616.5-114616.29"
+ attribute \src "libresoc.v:114441.5-114441.29"
switch \initial
- attribute \src "libresoc.v:114616.9-114616.17"
+ attribute \src "libresoc.v:114441.9-114441.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:114657.1-115436.10"
+attribute \src "libresoc.v:114482.1-115261.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4"
attribute \generator "nMigen"
module \dec31_dec_sub4
- attribute \src "libresoc.v:115357.3-115369.6"
+ attribute \src "libresoc.v:115182.3-115194.6"
wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:115370.3-115382.6"
+ attribute \src "libresoc.v:115195.3-115207.6"
wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:115201.3-115213.6"
+ attribute \src "libresoc.v:115026.3-115038.6"
wire width 8 $0\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:115253.3-115265.6"
+ attribute \src "libresoc.v:115078.3-115090.6"
wire $0\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:115019.3-115031.6"
+ attribute \src "libresoc.v:114844.3-114856.6"
wire width 3 $0\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:115032.3-115044.6"
+ attribute \src "libresoc.v:114857.3-114869.6"
wire width 3 $0\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:115188.3-115200.6"
+ attribute \src "libresoc.v:115013.3-115025.6"
wire width 2 $0\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:115240.3-115252.6"
+ attribute \src "libresoc.v:115065.3-115077.6"
wire $0\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:115292.3-115304.6"
+ attribute \src "libresoc.v:115117.3-115129.6"
wire width 5 $0\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:115006.3-115018.6"
+ attribute \src "libresoc.v:114831.3-114843.6"
wire width 14 $0\dec31_dec_sub4_function_unit[13:0]
- attribute \src "libresoc.v:115383.3-115395.6"
+ attribute \src "libresoc.v:115208.3-115220.6"
wire width 3 $0\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:115396.3-115408.6"
+ attribute \src "libresoc.v:115221.3-115233.6"
wire width 4 $0\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:115409.3-115421.6"
+ attribute \src "libresoc.v:115234.3-115246.6"
wire width 2 $0\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:115149.3-115161.6"
+ attribute \src "libresoc.v:114974.3-114986.6"
wire width 7 $0\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:115214.3-115226.6"
+ attribute \src "libresoc.v:115039.3-115051.6"
wire $0\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:115227.3-115239.6"
+ attribute \src "libresoc.v:115052.3-115064.6"
wire $0\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:115305.3-115317.6"
+ attribute \src "libresoc.v:115130.3-115142.6"
wire $0\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:115136.3-115148.6"
+ attribute \src "libresoc.v:114961.3-114973.6"
wire width 4 $0\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:115331.3-115343.6"
+ attribute \src "libresoc.v:115156.3-115168.6"
wire $0\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:115422.3-115434.6"
+ attribute \src "libresoc.v:115247.3-115259.6"
wire width 3 $0\dec31_dec_sub4_out_sel[2:0]
- attribute \src "libresoc.v:115175.3-115187.6"
+ attribute \src "libresoc.v:115000.3-115012.6"
wire width 2 $0\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:115279.3-115291.6"
+ attribute \src "libresoc.v:115104.3-115116.6"
wire $0\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:115344.3-115356.6"
+ attribute \src "libresoc.v:115169.3-115181.6"
wire $0\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:115318.3-115330.6"
+ attribute \src "libresoc.v:115143.3-115155.6"
wire $0\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:115266.3-115278.6"
+ attribute \src "libresoc.v:115091.3-115103.6"
wire $0\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:115110.3-115122.6"
+ attribute \src "libresoc.v:114935.3-114947.6"
wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:115123.3-115135.6"
+ attribute \src "libresoc.v:114948.3-114960.6"
wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:115045.3-115057.6"
+ attribute \src "libresoc.v:114870.3-114882.6"
wire width 3 $0\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:115058.3-115070.6"
+ attribute \src "libresoc.v:114883.3-114895.6"
wire width 3 $0\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:115071.3-115083.6"
+ attribute \src "libresoc.v:114896.3-114908.6"
wire width 3 $0\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:115097.3-115109.6"
+ attribute \src "libresoc.v:114922.3-114934.6"
wire width 3 $0\dec31_dec_sub4_sv_out2[2:0]
- attribute \src "libresoc.v:115084.3-115096.6"
+ attribute \src "libresoc.v:114909.3-114921.6"
wire width 3 $0\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:115162.3-115174.6"
+ attribute \src "libresoc.v:114987.3-114999.6"
wire width 2 $0\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:114658.7-114658.20"
+ attribute \src "libresoc.v:114483.7-114483.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:115357.3-115369.6"
+ attribute \src "libresoc.v:115182.3-115194.6"
wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:115370.3-115382.6"
+ attribute \src "libresoc.v:115195.3-115207.6"
wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:115201.3-115213.6"
+ attribute \src "libresoc.v:115026.3-115038.6"
wire width 8 $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:115253.3-115265.6"
+ attribute \src "libresoc.v:115078.3-115090.6"
wire $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:115019.3-115031.6"
+ attribute \src "libresoc.v:114844.3-114856.6"
wire width 3 $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:115032.3-115044.6"
+ attribute \src "libresoc.v:114857.3-114869.6"
wire width 3 $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:115188.3-115200.6"
+ attribute \src "libresoc.v:115013.3-115025.6"
wire width 2 $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:115240.3-115252.6"
+ attribute \src "libresoc.v:115065.3-115077.6"
wire $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:115292.3-115304.6"
+ attribute \src "libresoc.v:115117.3-115129.6"
wire width 5 $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:115006.3-115018.6"
+ attribute \src "libresoc.v:114831.3-114843.6"
wire width 14 $1\dec31_dec_sub4_function_unit[13:0]
- attribute \src "libresoc.v:115383.3-115395.6"
+ attribute \src "libresoc.v:115208.3-115220.6"
wire width 3 $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:115396.3-115408.6"
+ attribute \src "libresoc.v:115221.3-115233.6"
wire width 4 $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:115409.3-115421.6"
+ attribute \src "libresoc.v:115234.3-115246.6"
wire width 2 $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:115149.3-115161.6"
+ attribute \src "libresoc.v:114974.3-114986.6"
wire width 7 $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:115214.3-115226.6"
+ attribute \src "libresoc.v:115039.3-115051.6"
wire $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:115227.3-115239.6"
+ attribute \src "libresoc.v:115052.3-115064.6"
wire $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:115305.3-115317.6"
+ attribute \src "libresoc.v:115130.3-115142.6"
wire $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:115136.3-115148.6"
+ attribute \src "libresoc.v:114961.3-114973.6"
wire width 4 $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:115331.3-115343.6"
+ attribute \src "libresoc.v:115156.3-115168.6"
wire $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:115422.3-115434.6"
+ attribute \src "libresoc.v:115247.3-115259.6"
wire width 3 $1\dec31_dec_sub4_out_sel[2:0]
- attribute \src "libresoc.v:115175.3-115187.6"
+ attribute \src "libresoc.v:115000.3-115012.6"
wire width 2 $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:115279.3-115291.6"
+ attribute \src "libresoc.v:115104.3-115116.6"
wire $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:115344.3-115356.6"
+ attribute \src "libresoc.v:115169.3-115181.6"
wire $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:115318.3-115330.6"
+ attribute \src "libresoc.v:115143.3-115155.6"
wire $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:115266.3-115278.6"
+ attribute \src "libresoc.v:115091.3-115103.6"
wire $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:115110.3-115122.6"
+ attribute \src "libresoc.v:114935.3-114947.6"
wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:115123.3-115135.6"
+ attribute \src "libresoc.v:114948.3-114960.6"
wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:115045.3-115057.6"
+ attribute \src "libresoc.v:114870.3-114882.6"
wire width 3 $1\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:115058.3-115070.6"
+ attribute \src "libresoc.v:114883.3-114895.6"
wire width 3 $1\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:115071.3-115083.6"
+ attribute \src "libresoc.v:114896.3-114908.6"
wire width 3 $1\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:115097.3-115109.6"
+ attribute \src "libresoc.v:114922.3-114934.6"
wire width 3 $1\dec31_dec_sub4_sv_out2[2:0]
- attribute \src "libresoc.v:115084.3-115096.6"
+ attribute \src "libresoc.v:114909.3-114921.6"
wire width 3 $1\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:115162.3-115174.6"
+ attribute \src "libresoc.v:114987.3-114999.6"
wire width 2 $1\dec31_dec_sub4_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub4_upd
- attribute \src "libresoc.v:114658.7-114658.15"
+ attribute \src "libresoc.v:114483.7-114483.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:114658.7-114658.20"
- process $proc$libresoc.v:114658$4394
+ attribute \src "libresoc.v:114483.7-114483.20"
+ process $proc$libresoc.v:114483$4378
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:115006.3-115018.6"
- process $proc$libresoc.v:115006$4361
+ attribute \src "libresoc.v:114831.3-114843.6"
+ process $proc$libresoc.v:114831$4345
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0]
- attribute \src "libresoc.v:115007.5-115007.29"
+ attribute \src "libresoc.v:114832.5-114832.29"
switch \initial
- attribute \src "libresoc.v:115007.9-115007.17"
+ attribute \src "libresoc.v:114832.9-114832.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0]
end
- attribute \src "libresoc.v:115019.3-115031.6"
- process $proc$libresoc.v:115019$4362
+ attribute \src "libresoc.v:114844.3-114856.6"
+ process $proc$libresoc.v:114844$4346
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:115020.5-115020.29"
+ attribute \src "libresoc.v:114845.5-114845.29"
switch \initial
- attribute \src "libresoc.v:115020.9-115020.17"
+ attribute \src "libresoc.v:114845.9-114845.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0]
end
- attribute \src "libresoc.v:115032.3-115044.6"
- process $proc$libresoc.v:115032$4363
+ attribute \src "libresoc.v:114857.3-114869.6"
+ process $proc$libresoc.v:114857$4347
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:115033.5-115033.29"
+ attribute \src "libresoc.v:114858.5-114858.29"
switch \initial
- attribute \src "libresoc.v:115033.9-115033.17"
+ attribute \src "libresoc.v:114858.9-114858.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0]
end
- attribute \src "libresoc.v:115045.3-115057.6"
- process $proc$libresoc.v:115045$4364
+ attribute \src "libresoc.v:114870.3-114882.6"
+ process $proc$libresoc.v:114870$4348
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:115046.5-115046.29"
+ attribute \src "libresoc.v:114871.5-114871.29"
switch \initial
- attribute \src "libresoc.v:115046.9-115046.17"
+ attribute \src "libresoc.v:114871.9-114871.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0]
end
- attribute \src "libresoc.v:115058.3-115070.6"
- process $proc$libresoc.v:115058$4365
+ attribute \src "libresoc.v:114883.3-114895.6"
+ process $proc$libresoc.v:114883$4349
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:115059.5-115059.29"
+ attribute \src "libresoc.v:114884.5-114884.29"
switch \initial
- attribute \src "libresoc.v:115059.9-115059.17"
+ attribute \src "libresoc.v:114884.9-114884.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0]
end
- attribute \src "libresoc.v:115071.3-115083.6"
- process $proc$libresoc.v:115071$4366
+ attribute \src "libresoc.v:114896.3-114908.6"
+ process $proc$libresoc.v:114896$4350
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:115072.5-115072.29"
+ attribute \src "libresoc.v:114897.5-114897.29"
switch \initial
- attribute \src "libresoc.v:115072.9-115072.17"
+ attribute \src "libresoc.v:114897.9-114897.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0]
end
- attribute \src "libresoc.v:115084.3-115096.6"
- process $proc$libresoc.v:115084$4367
+ attribute \src "libresoc.v:114909.3-114921.6"
+ process $proc$libresoc.v:114909$4351
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:115085.5-115085.29"
+ attribute \src "libresoc.v:114910.5-114910.29"
switch \initial
- attribute \src "libresoc.v:115085.9-115085.17"
+ attribute \src "libresoc.v:114910.9-114910.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0]
end
- attribute \src "libresoc.v:115097.3-115109.6"
- process $proc$libresoc.v:115097$4368
+ attribute \src "libresoc.v:114922.3-114934.6"
+ process $proc$libresoc.v:114922$4352
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0]
- attribute \src "libresoc.v:115098.5-115098.29"
+ attribute \src "libresoc.v:114923.5-114923.29"
switch \initial
- attribute \src "libresoc.v:115098.9-115098.17"
+ attribute \src "libresoc.v:114923.9-114923.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0]
end
- attribute \src "libresoc.v:115110.3-115122.6"
- process $proc$libresoc.v:115110$4369
+ attribute \src "libresoc.v:114935.3-114947.6"
+ process $proc$libresoc.v:114935$4353
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:115111.5-115111.29"
+ attribute \src "libresoc.v:114936.5-114936.29"
switch \initial
- attribute \src "libresoc.v:115111.9-115111.17"
+ attribute \src "libresoc.v:114936.9-114936.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:115123.3-115135.6"
- process $proc$libresoc.v:115123$4370
+ attribute \src "libresoc.v:114948.3-114960.6"
+ process $proc$libresoc.v:114948$4354
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:115124.5-115124.29"
+ attribute \src "libresoc.v:114949.5-114949.29"
switch \initial
- attribute \src "libresoc.v:115124.9-115124.17"
+ attribute \src "libresoc.v:114949.9-114949.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:115136.3-115148.6"
- process $proc$libresoc.v:115136$4371
+ attribute \src "libresoc.v:114961.3-114973.6"
+ process $proc$libresoc.v:114961$4355
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:115137.5-115137.29"
+ attribute \src "libresoc.v:114962.5-114962.29"
switch \initial
- attribute \src "libresoc.v:115137.9-115137.17"
+ attribute \src "libresoc.v:114962.9-114962.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0]
end
- attribute \src "libresoc.v:115149.3-115161.6"
- process $proc$libresoc.v:115149$4372
+ attribute \src "libresoc.v:114974.3-114986.6"
+ process $proc$libresoc.v:114974$4356
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:115150.5-115150.29"
+ attribute \src "libresoc.v:114975.5-114975.29"
switch \initial
- attribute \src "libresoc.v:115150.9-115150.17"
+ attribute \src "libresoc.v:114975.9-114975.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0]
end
- attribute \src "libresoc.v:115162.3-115174.6"
- process $proc$libresoc.v:115162$4373
+ attribute \src "libresoc.v:114987.3-114999.6"
+ process $proc$libresoc.v:114987$4357
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:115163.5-115163.29"
+ attribute \src "libresoc.v:114988.5-114988.29"
switch \initial
- attribute \src "libresoc.v:115163.9-115163.17"
+ attribute \src "libresoc.v:114988.9-114988.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0]
end
- attribute \src "libresoc.v:115175.3-115187.6"
- process $proc$libresoc.v:115175$4374
+ attribute \src "libresoc.v:115000.3-115012.6"
+ process $proc$libresoc.v:115000$4358
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:115176.5-115176.29"
+ attribute \src "libresoc.v:115001.5-115001.29"
switch \initial
- attribute \src "libresoc.v:115176.9-115176.17"
+ attribute \src "libresoc.v:115001.9-115001.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0]
end
- attribute \src "libresoc.v:115188.3-115200.6"
- process $proc$libresoc.v:115188$4375
+ attribute \src "libresoc.v:115013.3-115025.6"
+ process $proc$libresoc.v:115013$4359
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:115189.5-115189.29"
+ attribute \src "libresoc.v:115014.5-115014.29"
switch \initial
- attribute \src "libresoc.v:115189.9-115189.17"
+ attribute \src "libresoc.v:115014.9-115014.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0]
end
- attribute \src "libresoc.v:115201.3-115213.6"
- process $proc$libresoc.v:115201$4376
+ attribute \src "libresoc.v:115026.3-115038.6"
+ process $proc$libresoc.v:115026$4360
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:115202.5-115202.29"
+ attribute \src "libresoc.v:115027.5-115027.29"
switch \initial
- attribute \src "libresoc.v:115202.9-115202.17"
+ attribute \src "libresoc.v:115027.9-115027.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0]
end
- attribute \src "libresoc.v:115214.3-115226.6"
- process $proc$libresoc.v:115214$4377
+ attribute \src "libresoc.v:115039.3-115051.6"
+ process $proc$libresoc.v:115039$4361
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:115215.5-115215.29"
+ attribute \src "libresoc.v:115040.5-115040.29"
switch \initial
- attribute \src "libresoc.v:115215.9-115215.17"
+ attribute \src "libresoc.v:115040.9-115040.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0]
end
- attribute \src "libresoc.v:115227.3-115239.6"
- process $proc$libresoc.v:115227$4378
+ attribute \src "libresoc.v:115052.3-115064.6"
+ process $proc$libresoc.v:115052$4362
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:115228.5-115228.29"
+ attribute \src "libresoc.v:115053.5-115053.29"
switch \initial
- attribute \src "libresoc.v:115228.9-115228.17"
+ attribute \src "libresoc.v:115053.9-115053.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0]
end
- attribute \src "libresoc.v:115240.3-115252.6"
- process $proc$libresoc.v:115240$4379
+ attribute \src "libresoc.v:115065.3-115077.6"
+ process $proc$libresoc.v:115065$4363
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:115241.5-115241.29"
+ attribute \src "libresoc.v:115066.5-115066.29"
switch \initial
- attribute \src "libresoc.v:115241.9-115241.17"
+ attribute \src "libresoc.v:115066.9-115066.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0]
end
- attribute \src "libresoc.v:115253.3-115265.6"
- process $proc$libresoc.v:115253$4380
+ attribute \src "libresoc.v:115078.3-115090.6"
+ process $proc$libresoc.v:115078$4364
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:115254.5-115254.29"
+ attribute \src "libresoc.v:115079.5-115079.29"
switch \initial
- attribute \src "libresoc.v:115254.9-115254.17"
+ attribute \src "libresoc.v:115079.9-115079.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0]
end
- attribute \src "libresoc.v:115266.3-115278.6"
- process $proc$libresoc.v:115266$4381
+ attribute \src "libresoc.v:115091.3-115103.6"
+ process $proc$libresoc.v:115091$4365
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:115267.5-115267.29"
+ attribute \src "libresoc.v:115092.5-115092.29"
switch \initial
- attribute \src "libresoc.v:115267.9-115267.17"
+ attribute \src "libresoc.v:115092.9-115092.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0]
end
- attribute \src "libresoc.v:115279.3-115291.6"
- process $proc$libresoc.v:115279$4382
+ attribute \src "libresoc.v:115104.3-115116.6"
+ process $proc$libresoc.v:115104$4366
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:115280.5-115280.29"
+ attribute \src "libresoc.v:115105.5-115105.29"
switch \initial
- attribute \src "libresoc.v:115280.9-115280.17"
+ attribute \src "libresoc.v:115105.9-115105.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0]
end
- attribute \src "libresoc.v:115292.3-115304.6"
- process $proc$libresoc.v:115292$4383
+ attribute \src "libresoc.v:115117.3-115129.6"
+ process $proc$libresoc.v:115117$4367
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:115293.5-115293.29"
+ attribute \src "libresoc.v:115118.5-115118.29"
switch \initial
- attribute \src "libresoc.v:115293.9-115293.17"
+ attribute \src "libresoc.v:115118.9-115118.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0]
end
- attribute \src "libresoc.v:115305.3-115317.6"
- process $proc$libresoc.v:115305$4384
+ attribute \src "libresoc.v:115130.3-115142.6"
+ process $proc$libresoc.v:115130$4368
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:115306.5-115306.29"
+ attribute \src "libresoc.v:115131.5-115131.29"
switch \initial
- attribute \src "libresoc.v:115306.9-115306.17"
+ attribute \src "libresoc.v:115131.9-115131.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0]
end
- attribute \src "libresoc.v:115318.3-115330.6"
- process $proc$libresoc.v:115318$4385
+ attribute \src "libresoc.v:115143.3-115155.6"
+ process $proc$libresoc.v:115143$4369
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:115319.5-115319.29"
+ attribute \src "libresoc.v:115144.5-115144.29"
switch \initial
- attribute \src "libresoc.v:115319.9-115319.17"
+ attribute \src "libresoc.v:115144.9-115144.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0]
end
- attribute \src "libresoc.v:115331.3-115343.6"
- process $proc$libresoc.v:115331$4386
+ attribute \src "libresoc.v:115156.3-115168.6"
+ process $proc$libresoc.v:115156$4370
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:115332.5-115332.29"
+ attribute \src "libresoc.v:115157.5-115157.29"
switch \initial
- attribute \src "libresoc.v:115332.9-115332.17"
+ attribute \src "libresoc.v:115157.9-115157.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0]
end
- attribute \src "libresoc.v:115344.3-115356.6"
- process $proc$libresoc.v:115344$4387
+ attribute \src "libresoc.v:115169.3-115181.6"
+ process $proc$libresoc.v:115169$4371
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:115345.5-115345.29"
+ attribute \src "libresoc.v:115170.5-115170.29"
switch \initial
- attribute \src "libresoc.v:115345.9-115345.17"
+ attribute \src "libresoc.v:115170.9-115170.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:115357.3-115369.6"
- process $proc$libresoc.v:115357$4388
+ attribute \src "libresoc.v:115182.3-115194.6"
+ process $proc$libresoc.v:115182$4372
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:115358.5-115358.29"
+ attribute \src "libresoc.v:115183.5-115183.29"
switch \initial
- attribute \src "libresoc.v:115358.9-115358.17"
+ attribute \src "libresoc.v:115183.9-115183.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0]
end
- attribute \src "libresoc.v:115370.3-115382.6"
- process $proc$libresoc.v:115370$4389
+ attribute \src "libresoc.v:115195.3-115207.6"
+ process $proc$libresoc.v:115195$4373
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:115371.5-115371.29"
+ attribute \src "libresoc.v:115196.5-115196.29"
switch \initial
- attribute \src "libresoc.v:115371.9-115371.17"
+ attribute \src "libresoc.v:115196.9-115196.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:115383.3-115395.6"
- process $proc$libresoc.v:115383$4390
+ attribute \src "libresoc.v:115208.3-115220.6"
+ process $proc$libresoc.v:115208$4374
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:115384.5-115384.29"
+ attribute \src "libresoc.v:115209.5-115209.29"
switch \initial
- attribute \src "libresoc.v:115384.9-115384.17"
+ attribute \src "libresoc.v:115209.9-115209.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0]
end
- attribute \src "libresoc.v:115396.3-115408.6"
- process $proc$libresoc.v:115396$4391
+ attribute \src "libresoc.v:115221.3-115233.6"
+ process $proc$libresoc.v:115221$4375
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:115397.5-115397.29"
+ attribute \src "libresoc.v:115222.5-115222.29"
switch \initial
- attribute \src "libresoc.v:115397.9-115397.17"
+ attribute \src "libresoc.v:115222.9-115222.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0]
end
- attribute \src "libresoc.v:115409.3-115421.6"
- process $proc$libresoc.v:115409$4392
+ attribute \src "libresoc.v:115234.3-115246.6"
+ process $proc$libresoc.v:115234$4376
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:115410.5-115410.29"
+ attribute \src "libresoc.v:115235.5-115235.29"
switch \initial
- attribute \src "libresoc.v:115410.9-115410.17"
+ attribute \src "libresoc.v:115235.9-115235.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0]
end
- attribute \src "libresoc.v:115422.3-115434.6"
- process $proc$libresoc.v:115422$4393
+ attribute \src "libresoc.v:115247.3-115259.6"
+ process $proc$libresoc.v:115247$4377
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0]
- attribute \src "libresoc.v:115423.5-115423.29"
+ attribute \src "libresoc.v:115248.5-115248.29"
switch \initial
- attribute \src "libresoc.v:115423.9-115423.17"
+ attribute \src "libresoc.v:115248.9-115248.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:115440.1-117209.10"
+attribute \src "libresoc.v:115265.1-117034.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8"
attribute \generator "nMigen"
module \dec31_dec_sub8
- attribute \src "libresoc.v:116950.3-116992.6"
+ attribute \src "libresoc.v:116775.3-116817.6"
wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:116993.3-117035.6"
+ attribute \src "libresoc.v:116818.3-116860.6"
wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:116434.3-116476.6"
+ attribute \src "libresoc.v:116259.3-116301.6"
wire width 8 $0\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:116606.3-116648.6"
+ attribute \src "libresoc.v:116431.3-116473.6"
wire $0\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:115832.3-115874.6"
+ attribute \src "libresoc.v:115657.3-115699.6"
wire width 3 $0\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:115875.3-115917.6"
+ attribute \src "libresoc.v:115700.3-115742.6"
wire width 3 $0\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:116391.3-116433.6"
+ attribute \src "libresoc.v:116216.3-116258.6"
wire width 2 $0\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:116563.3-116605.6"
+ attribute \src "libresoc.v:116388.3-116430.6"
wire $0\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:116735.3-116777.6"
+ attribute \src "libresoc.v:116560.3-116602.6"
wire width 5 $0\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:115789.3-115831.6"
+ attribute \src "libresoc.v:115614.3-115656.6"
wire width 14 $0\dec31_dec_sub8_function_unit[13:0]
- attribute \src "libresoc.v:117036.3-117078.6"
+ attribute \src "libresoc.v:116861.3-116903.6"
wire width 3 $0\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:117079.3-117121.6"
+ attribute \src "libresoc.v:116904.3-116946.6"
wire width 4 $0\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:117122.3-117164.6"
+ attribute \src "libresoc.v:116947.3-116989.6"
wire width 2 $0\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:116262.3-116304.6"
+ attribute \src "libresoc.v:116087.3-116129.6"
wire width 7 $0\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:116477.3-116519.6"
+ attribute \src "libresoc.v:116302.3-116344.6"
wire $0\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:116520.3-116562.6"
+ attribute \src "libresoc.v:116345.3-116387.6"
wire $0\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:116778.3-116820.6"
+ attribute \src "libresoc.v:116603.3-116645.6"
wire $0\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:116219.3-116261.6"
+ attribute \src "libresoc.v:116044.3-116086.6"
wire width 4 $0\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:116864.3-116906.6"
+ attribute \src "libresoc.v:116689.3-116731.6"
wire $0\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:117165.3-117207.6"
+ attribute \src "libresoc.v:116990.3-117032.6"
wire width 3 $0\dec31_dec_sub8_out_sel[2:0]
- attribute \src "libresoc.v:116348.3-116390.6"
+ attribute \src "libresoc.v:116173.3-116215.6"
wire width 2 $0\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:116692.3-116734.6"
+ attribute \src "libresoc.v:116517.3-116559.6"
wire $0\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:116907.3-116949.6"
+ attribute \src "libresoc.v:116732.3-116774.6"
wire $0\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:116821.3-116863.6"
+ attribute \src "libresoc.v:116646.3-116688.6"
wire $0\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:116649.3-116691.6"
+ attribute \src "libresoc.v:116474.3-116516.6"
wire $0\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:116133.3-116175.6"
+ attribute \src "libresoc.v:115958.3-116000.6"
wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:116176.3-116218.6"
+ attribute \src "libresoc.v:116001.3-116043.6"
wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:115918.3-115960.6"
+ attribute \src "libresoc.v:115743.3-115785.6"
wire width 3 $0\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:115961.3-116003.6"
+ attribute \src "libresoc.v:115786.3-115828.6"
wire width 3 $0\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:116004.3-116046.6"
+ attribute \src "libresoc.v:115829.3-115871.6"
wire width 3 $0\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:116090.3-116132.6"
+ attribute \src "libresoc.v:115915.3-115957.6"
wire width 3 $0\dec31_dec_sub8_sv_out2[2:0]
- attribute \src "libresoc.v:116047.3-116089.6"
+ attribute \src "libresoc.v:115872.3-115914.6"
wire width 3 $0\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:116305.3-116347.6"
+ attribute \src "libresoc.v:116130.3-116172.6"
wire width 2 $0\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:115441.7-115441.20"
+ attribute \src "libresoc.v:115266.7-115266.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:116950.3-116992.6"
+ attribute \src "libresoc.v:116775.3-116817.6"
wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:116993.3-117035.6"
+ attribute \src "libresoc.v:116818.3-116860.6"
wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:116434.3-116476.6"
+ attribute \src "libresoc.v:116259.3-116301.6"
wire width 8 $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:116606.3-116648.6"
+ attribute \src "libresoc.v:116431.3-116473.6"
wire $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:115832.3-115874.6"
+ attribute \src "libresoc.v:115657.3-115699.6"
wire width 3 $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:115875.3-115917.6"
+ attribute \src "libresoc.v:115700.3-115742.6"
wire width 3 $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:116391.3-116433.6"
+ attribute \src "libresoc.v:116216.3-116258.6"
wire width 2 $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:116563.3-116605.6"
+ attribute \src "libresoc.v:116388.3-116430.6"
wire $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:116735.3-116777.6"
+ attribute \src "libresoc.v:116560.3-116602.6"
wire width 5 $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:115789.3-115831.6"
+ attribute \src "libresoc.v:115614.3-115656.6"
wire width 14 $1\dec31_dec_sub8_function_unit[13:0]
- attribute \src "libresoc.v:117036.3-117078.6"
+ attribute \src "libresoc.v:116861.3-116903.6"
wire width 3 $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:117079.3-117121.6"
+ attribute \src "libresoc.v:116904.3-116946.6"
wire width 4 $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:117122.3-117164.6"
+ attribute \src "libresoc.v:116947.3-116989.6"
wire width 2 $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:116262.3-116304.6"
+ attribute \src "libresoc.v:116087.3-116129.6"
wire width 7 $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:116477.3-116519.6"
+ attribute \src "libresoc.v:116302.3-116344.6"
wire $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:116520.3-116562.6"
+ attribute \src "libresoc.v:116345.3-116387.6"
wire $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:116778.3-116820.6"
+ attribute \src "libresoc.v:116603.3-116645.6"
wire $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:116219.3-116261.6"
+ attribute \src "libresoc.v:116044.3-116086.6"
wire width 4 $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:116864.3-116906.6"
+ attribute \src "libresoc.v:116689.3-116731.6"
wire $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:117165.3-117207.6"
+ attribute \src "libresoc.v:116990.3-117032.6"
wire width 3 $1\dec31_dec_sub8_out_sel[2:0]
- attribute \src "libresoc.v:116348.3-116390.6"
+ attribute \src "libresoc.v:116173.3-116215.6"
wire width 2 $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:116692.3-116734.6"
+ attribute \src "libresoc.v:116517.3-116559.6"
wire $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:116907.3-116949.6"
+ attribute \src "libresoc.v:116732.3-116774.6"
wire $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:116821.3-116863.6"
+ attribute \src "libresoc.v:116646.3-116688.6"
wire $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:116649.3-116691.6"
+ attribute \src "libresoc.v:116474.3-116516.6"
wire $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:116133.3-116175.6"
+ attribute \src "libresoc.v:115958.3-116000.6"
wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:116176.3-116218.6"
+ attribute \src "libresoc.v:116001.3-116043.6"
wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:115918.3-115960.6"
+ attribute \src "libresoc.v:115743.3-115785.6"
wire width 3 $1\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:115961.3-116003.6"
+ attribute \src "libresoc.v:115786.3-115828.6"
wire width 3 $1\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:116004.3-116046.6"
+ attribute \src "libresoc.v:115829.3-115871.6"
wire width 3 $1\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:116090.3-116132.6"
+ attribute \src "libresoc.v:115915.3-115957.6"
wire width 3 $1\dec31_dec_sub8_sv_out2[2:0]
- attribute \src "libresoc.v:116047.3-116089.6"
+ attribute \src "libresoc.v:115872.3-115914.6"
wire width 3 $1\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:116305.3-116347.6"
+ attribute \src "libresoc.v:116130.3-116172.6"
wire width 2 $1\dec31_dec_sub8_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub8_upd
- attribute \src "libresoc.v:115441.7-115441.15"
+ attribute \src "libresoc.v:115266.7-115266.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:115441.7-115441.20"
- process $proc$libresoc.v:115441$4428
+ attribute \src "libresoc.v:115266.7-115266.20"
+ process $proc$libresoc.v:115266$4412
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:115789.3-115831.6"
- process $proc$libresoc.v:115789$4395
+ attribute \src "libresoc.v:115614.3-115656.6"
+ process $proc$libresoc.v:115614$4379
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0]
- attribute \src "libresoc.v:115790.5-115790.29"
+ attribute \src "libresoc.v:115615.5-115615.29"
switch \initial
- attribute \src "libresoc.v:115790.9-115790.17"
+ attribute \src "libresoc.v:115615.9-115615.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0]
end
- attribute \src "libresoc.v:115832.3-115874.6"
- process $proc$libresoc.v:115832$4396
+ attribute \src "libresoc.v:115657.3-115699.6"
+ process $proc$libresoc.v:115657$4380
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:115833.5-115833.29"
+ attribute \src "libresoc.v:115658.5-115658.29"
switch \initial
- attribute \src "libresoc.v:115833.9-115833.17"
+ attribute \src "libresoc.v:115658.9-115658.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0]
end
- attribute \src "libresoc.v:115875.3-115917.6"
- process $proc$libresoc.v:115875$4397
+ attribute \src "libresoc.v:115700.3-115742.6"
+ process $proc$libresoc.v:115700$4381
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:115876.5-115876.29"
+ attribute \src "libresoc.v:115701.5-115701.29"
switch \initial
- attribute \src "libresoc.v:115876.9-115876.17"
+ attribute \src "libresoc.v:115701.9-115701.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0]
end
- attribute \src "libresoc.v:115918.3-115960.6"
- process $proc$libresoc.v:115918$4398
+ attribute \src "libresoc.v:115743.3-115785.6"
+ process $proc$libresoc.v:115743$4382
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:115919.5-115919.29"
+ attribute \src "libresoc.v:115744.5-115744.29"
switch \initial
- attribute \src "libresoc.v:115919.9-115919.17"
+ attribute \src "libresoc.v:115744.9-115744.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0]
end
- attribute \src "libresoc.v:115961.3-116003.6"
- process $proc$libresoc.v:115961$4399
+ attribute \src "libresoc.v:115786.3-115828.6"
+ process $proc$libresoc.v:115786$4383
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:115962.5-115962.29"
+ attribute \src "libresoc.v:115787.5-115787.29"
switch \initial
- attribute \src "libresoc.v:115962.9-115962.17"
+ attribute \src "libresoc.v:115787.9-115787.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0]
end
- attribute \src "libresoc.v:116004.3-116046.6"
- process $proc$libresoc.v:116004$4400
+ attribute \src "libresoc.v:115829.3-115871.6"
+ process $proc$libresoc.v:115829$4384
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:116005.5-116005.29"
+ attribute \src "libresoc.v:115830.5-115830.29"
switch \initial
- attribute \src "libresoc.v:116005.9-116005.17"
+ attribute \src "libresoc.v:115830.9-115830.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0]
end
- attribute \src "libresoc.v:116047.3-116089.6"
- process $proc$libresoc.v:116047$4401
+ attribute \src "libresoc.v:115872.3-115914.6"
+ process $proc$libresoc.v:115872$4385
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:116048.5-116048.29"
+ attribute \src "libresoc.v:115873.5-115873.29"
switch \initial
- attribute \src "libresoc.v:116048.9-116048.17"
+ attribute \src "libresoc.v:115873.9-115873.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0]
end
- attribute \src "libresoc.v:116090.3-116132.6"
- process $proc$libresoc.v:116090$4402
+ attribute \src "libresoc.v:115915.3-115957.6"
+ process $proc$libresoc.v:115915$4386
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0]
- attribute \src "libresoc.v:116091.5-116091.29"
+ attribute \src "libresoc.v:115916.5-115916.29"
switch \initial
- attribute \src "libresoc.v:116091.9-116091.17"
+ attribute \src "libresoc.v:115916.9-115916.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0]
end
- attribute \src "libresoc.v:116133.3-116175.6"
- process $proc$libresoc.v:116133$4403
+ attribute \src "libresoc.v:115958.3-116000.6"
+ process $proc$libresoc.v:115958$4387
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:116134.5-116134.29"
+ attribute \src "libresoc.v:115959.5-115959.29"
switch \initial
- attribute \src "libresoc.v:116134.9-116134.17"
+ attribute \src "libresoc.v:115959.9-115959.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:116176.3-116218.6"
- process $proc$libresoc.v:116176$4404
+ attribute \src "libresoc.v:116001.3-116043.6"
+ process $proc$libresoc.v:116001$4388
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:116177.5-116177.29"
+ attribute \src "libresoc.v:116002.5-116002.29"
switch \initial
- attribute \src "libresoc.v:116177.9-116177.17"
+ attribute \src "libresoc.v:116002.9-116002.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:116219.3-116261.6"
- process $proc$libresoc.v:116219$4405
+ attribute \src "libresoc.v:116044.3-116086.6"
+ process $proc$libresoc.v:116044$4389
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:116220.5-116220.29"
+ attribute \src "libresoc.v:116045.5-116045.29"
switch \initial
- attribute \src "libresoc.v:116220.9-116220.17"
+ attribute \src "libresoc.v:116045.9-116045.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0]
end
- attribute \src "libresoc.v:116262.3-116304.6"
- process $proc$libresoc.v:116262$4406
+ attribute \src "libresoc.v:116087.3-116129.6"
+ process $proc$libresoc.v:116087$4390
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:116263.5-116263.29"
+ attribute \src "libresoc.v:116088.5-116088.29"
switch \initial
- attribute \src "libresoc.v:116263.9-116263.17"
+ attribute \src "libresoc.v:116088.9-116088.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0]
end
- attribute \src "libresoc.v:116305.3-116347.6"
- process $proc$libresoc.v:116305$4407
+ attribute \src "libresoc.v:116130.3-116172.6"
+ process $proc$libresoc.v:116130$4391
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:116306.5-116306.29"
+ attribute \src "libresoc.v:116131.5-116131.29"
switch \initial
- attribute \src "libresoc.v:116306.9-116306.17"
+ attribute \src "libresoc.v:116131.9-116131.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0]
end
- attribute \src "libresoc.v:116348.3-116390.6"
- process $proc$libresoc.v:116348$4408
+ attribute \src "libresoc.v:116173.3-116215.6"
+ process $proc$libresoc.v:116173$4392
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:116349.5-116349.29"
+ attribute \src "libresoc.v:116174.5-116174.29"
switch \initial
- attribute \src "libresoc.v:116349.9-116349.17"
+ attribute \src "libresoc.v:116174.9-116174.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0]
end
- attribute \src "libresoc.v:116391.3-116433.6"
- process $proc$libresoc.v:116391$4409
+ attribute \src "libresoc.v:116216.3-116258.6"
+ process $proc$libresoc.v:116216$4393
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:116392.5-116392.29"
+ attribute \src "libresoc.v:116217.5-116217.29"
switch \initial
- attribute \src "libresoc.v:116392.9-116392.17"
+ attribute \src "libresoc.v:116217.9-116217.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0]
end
- attribute \src "libresoc.v:116434.3-116476.6"
- process $proc$libresoc.v:116434$4410
+ attribute \src "libresoc.v:116259.3-116301.6"
+ process $proc$libresoc.v:116259$4394
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:116435.5-116435.29"
+ attribute \src "libresoc.v:116260.5-116260.29"
switch \initial
- attribute \src "libresoc.v:116435.9-116435.17"
+ attribute \src "libresoc.v:116260.9-116260.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0]
end
- attribute \src "libresoc.v:116477.3-116519.6"
- process $proc$libresoc.v:116477$4411
+ attribute \src "libresoc.v:116302.3-116344.6"
+ process $proc$libresoc.v:116302$4395
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:116478.5-116478.29"
+ attribute \src "libresoc.v:116303.5-116303.29"
switch \initial
- attribute \src "libresoc.v:116478.9-116478.17"
+ attribute \src "libresoc.v:116303.9-116303.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0]
end
- attribute \src "libresoc.v:116520.3-116562.6"
- process $proc$libresoc.v:116520$4412
+ attribute \src "libresoc.v:116345.3-116387.6"
+ process $proc$libresoc.v:116345$4396
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:116521.5-116521.29"
+ attribute \src "libresoc.v:116346.5-116346.29"
switch \initial
- attribute \src "libresoc.v:116521.9-116521.17"
+ attribute \src "libresoc.v:116346.9-116346.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0]
end
- attribute \src "libresoc.v:116563.3-116605.6"
- process $proc$libresoc.v:116563$4413
+ attribute \src "libresoc.v:116388.3-116430.6"
+ process $proc$libresoc.v:116388$4397
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:116564.5-116564.29"
+ attribute \src "libresoc.v:116389.5-116389.29"
switch \initial
- attribute \src "libresoc.v:116564.9-116564.17"
+ attribute \src "libresoc.v:116389.9-116389.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0]
end
- attribute \src "libresoc.v:116606.3-116648.6"
- process $proc$libresoc.v:116606$4414
+ attribute \src "libresoc.v:116431.3-116473.6"
+ process $proc$libresoc.v:116431$4398
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:116607.5-116607.29"
+ attribute \src "libresoc.v:116432.5-116432.29"
switch \initial
- attribute \src "libresoc.v:116607.9-116607.17"
+ attribute \src "libresoc.v:116432.9-116432.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0]
end
- attribute \src "libresoc.v:116649.3-116691.6"
- process $proc$libresoc.v:116649$4415
+ attribute \src "libresoc.v:116474.3-116516.6"
+ process $proc$libresoc.v:116474$4399
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:116650.5-116650.29"
+ attribute \src "libresoc.v:116475.5-116475.29"
switch \initial
- attribute \src "libresoc.v:116650.9-116650.17"
+ attribute \src "libresoc.v:116475.9-116475.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0]
end
- attribute \src "libresoc.v:116692.3-116734.6"
- process $proc$libresoc.v:116692$4416
+ attribute \src "libresoc.v:116517.3-116559.6"
+ process $proc$libresoc.v:116517$4400
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:116693.5-116693.29"
+ attribute \src "libresoc.v:116518.5-116518.29"
switch \initial
- attribute \src "libresoc.v:116693.9-116693.17"
+ attribute \src "libresoc.v:116518.9-116518.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0]
end
- attribute \src "libresoc.v:116735.3-116777.6"
- process $proc$libresoc.v:116735$4417
+ attribute \src "libresoc.v:116560.3-116602.6"
+ process $proc$libresoc.v:116560$4401
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:116736.5-116736.29"
+ attribute \src "libresoc.v:116561.5-116561.29"
switch \initial
- attribute \src "libresoc.v:116736.9-116736.17"
+ attribute \src "libresoc.v:116561.9-116561.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0]
end
- attribute \src "libresoc.v:116778.3-116820.6"
- process $proc$libresoc.v:116778$4418
+ attribute \src "libresoc.v:116603.3-116645.6"
+ process $proc$libresoc.v:116603$4402
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:116779.5-116779.29"
+ attribute \src "libresoc.v:116604.5-116604.29"
switch \initial
- attribute \src "libresoc.v:116779.9-116779.17"
+ attribute \src "libresoc.v:116604.9-116604.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0]
end
- attribute \src "libresoc.v:116821.3-116863.6"
- process $proc$libresoc.v:116821$4419
+ attribute \src "libresoc.v:116646.3-116688.6"
+ process $proc$libresoc.v:116646$4403
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:116822.5-116822.29"
+ attribute \src "libresoc.v:116647.5-116647.29"
switch \initial
- attribute \src "libresoc.v:116822.9-116822.17"
+ attribute \src "libresoc.v:116647.9-116647.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0]
end
- attribute \src "libresoc.v:116864.3-116906.6"
- process $proc$libresoc.v:116864$4420
+ attribute \src "libresoc.v:116689.3-116731.6"
+ process $proc$libresoc.v:116689$4404
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:116865.5-116865.29"
+ attribute \src "libresoc.v:116690.5-116690.29"
switch \initial
- attribute \src "libresoc.v:116865.9-116865.17"
+ attribute \src "libresoc.v:116690.9-116690.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0]
end
- attribute \src "libresoc.v:116907.3-116949.6"
- process $proc$libresoc.v:116907$4421
+ attribute \src "libresoc.v:116732.3-116774.6"
+ process $proc$libresoc.v:116732$4405
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:116908.5-116908.29"
+ attribute \src "libresoc.v:116733.5-116733.29"
switch \initial
- attribute \src "libresoc.v:116908.9-116908.17"
+ attribute \src "libresoc.v:116733.9-116733.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:116950.3-116992.6"
- process $proc$libresoc.v:116950$4422
+ attribute \src "libresoc.v:116775.3-116817.6"
+ process $proc$libresoc.v:116775$4406
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:116951.5-116951.29"
+ attribute \src "libresoc.v:116776.5-116776.29"
switch \initial
- attribute \src "libresoc.v:116951.9-116951.17"
+ attribute \src "libresoc.v:116776.9-116776.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0]
end
- attribute \src "libresoc.v:116993.3-117035.6"
- process $proc$libresoc.v:116993$4423
+ attribute \src "libresoc.v:116818.3-116860.6"
+ process $proc$libresoc.v:116818$4407
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:116994.5-116994.29"
+ attribute \src "libresoc.v:116819.5-116819.29"
switch \initial
- attribute \src "libresoc.v:116994.9-116994.17"
+ attribute \src "libresoc.v:116819.9-116819.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:117036.3-117078.6"
- process $proc$libresoc.v:117036$4424
+ attribute \src "libresoc.v:116861.3-116903.6"
+ process $proc$libresoc.v:116861$4408
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:117037.5-117037.29"
+ attribute \src "libresoc.v:116862.5-116862.29"
switch \initial
- attribute \src "libresoc.v:117037.9-117037.17"
+ attribute \src "libresoc.v:116862.9-116862.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0]
end
- attribute \src "libresoc.v:117079.3-117121.6"
- process $proc$libresoc.v:117079$4425
+ attribute \src "libresoc.v:116904.3-116946.6"
+ process $proc$libresoc.v:116904$4409
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:117080.5-117080.29"
+ attribute \src "libresoc.v:116905.5-116905.29"
switch \initial
- attribute \src "libresoc.v:117080.9-117080.17"
+ attribute \src "libresoc.v:116905.9-116905.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0]
end
- attribute \src "libresoc.v:117122.3-117164.6"
- process $proc$libresoc.v:117122$4426
+ attribute \src "libresoc.v:116947.3-116989.6"
+ process $proc$libresoc.v:116947$4410
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:117123.5-117123.29"
+ attribute \src "libresoc.v:116948.5-116948.29"
switch \initial
- attribute \src "libresoc.v:117123.9-117123.17"
+ attribute \src "libresoc.v:116948.9-116948.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0]
end
- attribute \src "libresoc.v:117165.3-117207.6"
- process $proc$libresoc.v:117165$4427
+ attribute \src "libresoc.v:116990.3-117032.6"
+ process $proc$libresoc.v:116990$4411
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0]
- attribute \src "libresoc.v:117166.5-117166.29"
+ attribute \src "libresoc.v:116991.5-116991.29"
switch \initial
- attribute \src "libresoc.v:117166.9-117166.17"
+ attribute \src "libresoc.v:116991.9-116991.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:117213.1-119378.10"
+attribute \src "libresoc.v:117038.1-119203.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9"
attribute \generator "nMigen"
module \dec31_dec_sub9
- attribute \src "libresoc.v:119047.3-119101.6"
+ attribute \src "libresoc.v:118872.3-118926.6"
wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:119102.3-119156.6"
+ attribute \src "libresoc.v:118927.3-118981.6"
wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:118387.3-118441.6"
+ attribute \src "libresoc.v:118212.3-118266.6"
wire width 8 $0\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:118607.3-118661.6"
+ attribute \src "libresoc.v:118432.3-118486.6"
wire $0\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:117617.3-117671.6"
+ attribute \src "libresoc.v:117442.3-117496.6"
wire width 3 $0\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:117672.3-117726.6"
+ attribute \src "libresoc.v:117497.3-117551.6"
wire width 3 $0\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:118332.3-118386.6"
+ attribute \src "libresoc.v:118157.3-118211.6"
wire width 2 $0\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:118552.3-118606.6"
+ attribute \src "libresoc.v:118377.3-118431.6"
wire $0\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:118772.3-118826.6"
+ attribute \src "libresoc.v:118597.3-118651.6"
wire width 5 $0\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:117562.3-117616.6"
+ attribute \src "libresoc.v:117387.3-117441.6"
wire width 14 $0\dec31_dec_sub9_function_unit[13:0]
- attribute \src "libresoc.v:119157.3-119211.6"
+ attribute \src "libresoc.v:118982.3-119036.6"
wire width 3 $0\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:119212.3-119266.6"
+ attribute \src "libresoc.v:119037.3-119091.6"
wire width 4 $0\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:119267.3-119321.6"
+ attribute \src "libresoc.v:119092.3-119146.6"
wire width 2 $0\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:118167.3-118221.6"
+ attribute \src "libresoc.v:117992.3-118046.6"
wire width 7 $0\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:118442.3-118496.6"
+ attribute \src "libresoc.v:118267.3-118321.6"
wire $0\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:118497.3-118551.6"
+ attribute \src "libresoc.v:118322.3-118376.6"
wire $0\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:118827.3-118881.6"
+ attribute \src "libresoc.v:118652.3-118706.6"
wire $0\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:118112.3-118166.6"
+ attribute \src "libresoc.v:117937.3-117991.6"
wire width 4 $0\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:118937.3-118991.6"
+ attribute \src "libresoc.v:118762.3-118816.6"
wire $0\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:119322.3-119376.6"
+ attribute \src "libresoc.v:119147.3-119201.6"
wire width 3 $0\dec31_dec_sub9_out_sel[2:0]
- attribute \src "libresoc.v:118277.3-118331.6"
+ attribute \src "libresoc.v:118102.3-118156.6"
wire width 2 $0\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:118717.3-118771.6"
+ attribute \src "libresoc.v:118542.3-118596.6"
wire $0\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:118992.3-119046.6"
+ attribute \src "libresoc.v:118817.3-118871.6"
wire $0\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:118882.3-118936.6"
+ attribute \src "libresoc.v:118707.3-118761.6"
wire $0\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:118662.3-118716.6"
+ attribute \src "libresoc.v:118487.3-118541.6"
wire $0\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:118002.3-118056.6"
+ attribute \src "libresoc.v:117827.3-117881.6"
wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:118057.3-118111.6"
+ attribute \src "libresoc.v:117882.3-117936.6"
wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:117727.3-117781.6"
+ attribute \src "libresoc.v:117552.3-117606.6"
wire width 3 $0\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:117782.3-117836.6"
+ attribute \src "libresoc.v:117607.3-117661.6"
wire width 3 $0\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:117837.3-117891.6"
+ attribute \src "libresoc.v:117662.3-117716.6"
wire width 3 $0\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:117947.3-118001.6"
+ attribute \src "libresoc.v:117772.3-117826.6"
wire width 3 $0\dec31_dec_sub9_sv_out2[2:0]
- attribute \src "libresoc.v:117892.3-117946.6"
+ attribute \src "libresoc.v:117717.3-117771.6"
wire width 3 $0\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:118222.3-118276.6"
+ attribute \src "libresoc.v:118047.3-118101.6"
wire width 2 $0\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:117214.7-117214.20"
+ attribute \src "libresoc.v:117039.7-117039.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:119047.3-119101.6"
+ attribute \src "libresoc.v:118872.3-118926.6"
wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:119102.3-119156.6"
+ attribute \src "libresoc.v:118927.3-118981.6"
wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:118387.3-118441.6"
+ attribute \src "libresoc.v:118212.3-118266.6"
wire width 8 $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:118607.3-118661.6"
+ attribute \src "libresoc.v:118432.3-118486.6"
wire $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:117617.3-117671.6"
+ attribute \src "libresoc.v:117442.3-117496.6"
wire width 3 $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:117672.3-117726.6"
+ attribute \src "libresoc.v:117497.3-117551.6"
wire width 3 $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:118332.3-118386.6"
+ attribute \src "libresoc.v:118157.3-118211.6"
wire width 2 $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:118552.3-118606.6"
+ attribute \src "libresoc.v:118377.3-118431.6"
wire $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:118772.3-118826.6"
+ attribute \src "libresoc.v:118597.3-118651.6"
wire width 5 $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:117562.3-117616.6"
+ attribute \src "libresoc.v:117387.3-117441.6"
wire width 14 $1\dec31_dec_sub9_function_unit[13:0]
- attribute \src "libresoc.v:119157.3-119211.6"
+ attribute \src "libresoc.v:118982.3-119036.6"
wire width 3 $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:119212.3-119266.6"
+ attribute \src "libresoc.v:119037.3-119091.6"
wire width 4 $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:119267.3-119321.6"
+ attribute \src "libresoc.v:119092.3-119146.6"
wire width 2 $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:118167.3-118221.6"
+ attribute \src "libresoc.v:117992.3-118046.6"
wire width 7 $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:118442.3-118496.6"
+ attribute \src "libresoc.v:118267.3-118321.6"
wire $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:118497.3-118551.6"
+ attribute \src "libresoc.v:118322.3-118376.6"
wire $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:118827.3-118881.6"
+ attribute \src "libresoc.v:118652.3-118706.6"
wire $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:118112.3-118166.6"
+ attribute \src "libresoc.v:117937.3-117991.6"
wire width 4 $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:118937.3-118991.6"
+ attribute \src "libresoc.v:118762.3-118816.6"
wire $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:119322.3-119376.6"
+ attribute \src "libresoc.v:119147.3-119201.6"
wire width 3 $1\dec31_dec_sub9_out_sel[2:0]
- attribute \src "libresoc.v:118277.3-118331.6"
+ attribute \src "libresoc.v:118102.3-118156.6"
wire width 2 $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:118717.3-118771.6"
+ attribute \src "libresoc.v:118542.3-118596.6"
wire $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:118992.3-119046.6"
+ attribute \src "libresoc.v:118817.3-118871.6"
wire $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:118882.3-118936.6"
+ attribute \src "libresoc.v:118707.3-118761.6"
wire $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:118662.3-118716.6"
+ attribute \src "libresoc.v:118487.3-118541.6"
wire $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:118002.3-118056.6"
+ attribute \src "libresoc.v:117827.3-117881.6"
wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:118057.3-118111.6"
+ attribute \src "libresoc.v:117882.3-117936.6"
wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:117727.3-117781.6"
+ attribute \src "libresoc.v:117552.3-117606.6"
wire width 3 $1\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:117782.3-117836.6"
+ attribute \src "libresoc.v:117607.3-117661.6"
wire width 3 $1\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:117837.3-117891.6"
+ attribute \src "libresoc.v:117662.3-117716.6"
wire width 3 $1\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:117947.3-118001.6"
+ attribute \src "libresoc.v:117772.3-117826.6"
wire width 3 $1\dec31_dec_sub9_sv_out2[2:0]
- attribute \src "libresoc.v:117892.3-117946.6"
+ attribute \src "libresoc.v:117717.3-117771.6"
wire width 3 $1\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:118222.3-118276.6"
+ attribute \src "libresoc.v:118047.3-118101.6"
wire width 2 $1\dec31_dec_sub9_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec31_dec_sub9_upd
- attribute \src "libresoc.v:117214.7-117214.15"
+ attribute \src "libresoc.v:117039.7-117039.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:117214.7-117214.20"
- process $proc$libresoc.v:117214$4462
+ attribute \src "libresoc.v:117039.7-117039.20"
+ process $proc$libresoc.v:117039$4446
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:117562.3-117616.6"
- process $proc$libresoc.v:117562$4429
+ attribute \src "libresoc.v:117387.3-117441.6"
+ process $proc$libresoc.v:117387$4413
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0]
- attribute \src "libresoc.v:117563.5-117563.29"
+ attribute \src "libresoc.v:117388.5-117388.29"
switch \initial
- attribute \src "libresoc.v:117563.9-117563.17"
+ attribute \src "libresoc.v:117388.9-117388.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0]
end
- attribute \src "libresoc.v:117617.3-117671.6"
- process $proc$libresoc.v:117617$4430
+ attribute \src "libresoc.v:117442.3-117496.6"
+ process $proc$libresoc.v:117442$4414
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:117618.5-117618.29"
+ attribute \src "libresoc.v:117443.5-117443.29"
switch \initial
- attribute \src "libresoc.v:117618.9-117618.17"
+ attribute \src "libresoc.v:117443.9-117443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0]
end
- attribute \src "libresoc.v:117672.3-117726.6"
- process $proc$libresoc.v:117672$4431
+ attribute \src "libresoc.v:117497.3-117551.6"
+ process $proc$libresoc.v:117497$4415
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:117673.5-117673.29"
+ attribute \src "libresoc.v:117498.5-117498.29"
switch \initial
- attribute \src "libresoc.v:117673.9-117673.17"
+ attribute \src "libresoc.v:117498.9-117498.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0]
end
- attribute \src "libresoc.v:117727.3-117781.6"
- process $proc$libresoc.v:117727$4432
+ attribute \src "libresoc.v:117552.3-117606.6"
+ process $proc$libresoc.v:117552$4416
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:117728.5-117728.29"
+ attribute \src "libresoc.v:117553.5-117553.29"
switch \initial
- attribute \src "libresoc.v:117728.9-117728.17"
+ attribute \src "libresoc.v:117553.9-117553.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0]
end
- attribute \src "libresoc.v:117782.3-117836.6"
- process $proc$libresoc.v:117782$4433
+ attribute \src "libresoc.v:117607.3-117661.6"
+ process $proc$libresoc.v:117607$4417
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:117783.5-117783.29"
+ attribute \src "libresoc.v:117608.5-117608.29"
switch \initial
- attribute \src "libresoc.v:117783.9-117783.17"
+ attribute \src "libresoc.v:117608.9-117608.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0]
end
- attribute \src "libresoc.v:117837.3-117891.6"
- process $proc$libresoc.v:117837$4434
+ attribute \src "libresoc.v:117662.3-117716.6"
+ process $proc$libresoc.v:117662$4418
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:117838.5-117838.29"
+ attribute \src "libresoc.v:117663.5-117663.29"
switch \initial
- attribute \src "libresoc.v:117838.9-117838.17"
+ attribute \src "libresoc.v:117663.9-117663.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0]
end
- attribute \src "libresoc.v:117892.3-117946.6"
- process $proc$libresoc.v:117892$4435
+ attribute \src "libresoc.v:117717.3-117771.6"
+ process $proc$libresoc.v:117717$4419
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:117893.5-117893.29"
+ attribute \src "libresoc.v:117718.5-117718.29"
switch \initial
- attribute \src "libresoc.v:117893.9-117893.17"
+ attribute \src "libresoc.v:117718.9-117718.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0]
end
- attribute \src "libresoc.v:117947.3-118001.6"
- process $proc$libresoc.v:117947$4436
+ attribute \src "libresoc.v:117772.3-117826.6"
+ process $proc$libresoc.v:117772$4420
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0]
- attribute \src "libresoc.v:117948.5-117948.29"
+ attribute \src "libresoc.v:117773.5-117773.29"
switch \initial
- attribute \src "libresoc.v:117948.9-117948.17"
+ attribute \src "libresoc.v:117773.9-117773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0]
end
- attribute \src "libresoc.v:118002.3-118056.6"
- process $proc$libresoc.v:118002$4437
+ attribute \src "libresoc.v:117827.3-117881.6"
+ process $proc$libresoc.v:117827$4421
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:118003.5-118003.29"
+ attribute \src "libresoc.v:117828.5-117828.29"
switch \initial
- attribute \src "libresoc.v:118003.9-118003.17"
+ attribute \src "libresoc.v:117828.9-117828.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:118057.3-118111.6"
- process $proc$libresoc.v:118057$4438
+ attribute \src "libresoc.v:117882.3-117936.6"
+ process $proc$libresoc.v:117882$4422
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:118058.5-118058.29"
+ attribute \src "libresoc.v:117883.5-117883.29"
switch \initial
- attribute \src "libresoc.v:118058.9-118058.17"
+ attribute \src "libresoc.v:117883.9-117883.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:118112.3-118166.6"
- process $proc$libresoc.v:118112$4439
+ attribute \src "libresoc.v:117937.3-117991.6"
+ process $proc$libresoc.v:117937$4423
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:118113.5-118113.29"
+ attribute \src "libresoc.v:117938.5-117938.29"
switch \initial
- attribute \src "libresoc.v:118113.9-118113.17"
+ attribute \src "libresoc.v:117938.9-117938.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0]
end
- attribute \src "libresoc.v:118167.3-118221.6"
- process $proc$libresoc.v:118167$4440
+ attribute \src "libresoc.v:117992.3-118046.6"
+ process $proc$libresoc.v:117992$4424
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:118168.5-118168.29"
+ attribute \src "libresoc.v:117993.5-117993.29"
switch \initial
- attribute \src "libresoc.v:118168.9-118168.17"
+ attribute \src "libresoc.v:117993.9-117993.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0]
end
- attribute \src "libresoc.v:118222.3-118276.6"
- process $proc$libresoc.v:118222$4441
+ attribute \src "libresoc.v:118047.3-118101.6"
+ process $proc$libresoc.v:118047$4425
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:118223.5-118223.29"
+ attribute \src "libresoc.v:118048.5-118048.29"
switch \initial
- attribute \src "libresoc.v:118223.9-118223.17"
+ attribute \src "libresoc.v:118048.9-118048.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0]
end
- attribute \src "libresoc.v:118277.3-118331.6"
- process $proc$libresoc.v:118277$4442
+ attribute \src "libresoc.v:118102.3-118156.6"
+ process $proc$libresoc.v:118102$4426
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:118278.5-118278.29"
+ attribute \src "libresoc.v:118103.5-118103.29"
switch \initial
- attribute \src "libresoc.v:118278.9-118278.17"
+ attribute \src "libresoc.v:118103.9-118103.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0]
end
- attribute \src "libresoc.v:118332.3-118386.6"
- process $proc$libresoc.v:118332$4443
+ attribute \src "libresoc.v:118157.3-118211.6"
+ process $proc$libresoc.v:118157$4427
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:118333.5-118333.29"
+ attribute \src "libresoc.v:118158.5-118158.29"
switch \initial
- attribute \src "libresoc.v:118333.9-118333.17"
+ attribute \src "libresoc.v:118158.9-118158.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0]
end
- attribute \src "libresoc.v:118387.3-118441.6"
- process $proc$libresoc.v:118387$4444
+ attribute \src "libresoc.v:118212.3-118266.6"
+ process $proc$libresoc.v:118212$4428
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:118388.5-118388.29"
+ attribute \src "libresoc.v:118213.5-118213.29"
switch \initial
- attribute \src "libresoc.v:118388.9-118388.17"
+ attribute \src "libresoc.v:118213.9-118213.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0]
end
- attribute \src "libresoc.v:118442.3-118496.6"
- process $proc$libresoc.v:118442$4445
+ attribute \src "libresoc.v:118267.3-118321.6"
+ process $proc$libresoc.v:118267$4429
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:118443.5-118443.29"
+ attribute \src "libresoc.v:118268.5-118268.29"
switch \initial
- attribute \src "libresoc.v:118443.9-118443.17"
+ attribute \src "libresoc.v:118268.9-118268.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0]
end
- attribute \src "libresoc.v:118497.3-118551.6"
- process $proc$libresoc.v:118497$4446
+ attribute \src "libresoc.v:118322.3-118376.6"
+ process $proc$libresoc.v:118322$4430
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:118498.5-118498.29"
+ attribute \src "libresoc.v:118323.5-118323.29"
switch \initial
- attribute \src "libresoc.v:118498.9-118498.17"
+ attribute \src "libresoc.v:118323.9-118323.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0]
end
- attribute \src "libresoc.v:118552.3-118606.6"
- process $proc$libresoc.v:118552$4447
+ attribute \src "libresoc.v:118377.3-118431.6"
+ process $proc$libresoc.v:118377$4431
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:118553.5-118553.29"
+ attribute \src "libresoc.v:118378.5-118378.29"
switch \initial
- attribute \src "libresoc.v:118553.9-118553.17"
+ attribute \src "libresoc.v:118378.9-118378.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0]
end
- attribute \src "libresoc.v:118607.3-118661.6"
- process $proc$libresoc.v:118607$4448
+ attribute \src "libresoc.v:118432.3-118486.6"
+ process $proc$libresoc.v:118432$4432
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:118608.5-118608.29"
+ attribute \src "libresoc.v:118433.5-118433.29"
switch \initial
- attribute \src "libresoc.v:118608.9-118608.17"
+ attribute \src "libresoc.v:118433.9-118433.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0]
end
- attribute \src "libresoc.v:118662.3-118716.6"
- process $proc$libresoc.v:118662$4449
+ attribute \src "libresoc.v:118487.3-118541.6"
+ process $proc$libresoc.v:118487$4433
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:118663.5-118663.29"
+ attribute \src "libresoc.v:118488.5-118488.29"
switch \initial
- attribute \src "libresoc.v:118663.9-118663.17"
+ attribute \src "libresoc.v:118488.9-118488.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0]
end
- attribute \src "libresoc.v:118717.3-118771.6"
- process $proc$libresoc.v:118717$4450
+ attribute \src "libresoc.v:118542.3-118596.6"
+ process $proc$libresoc.v:118542$4434
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:118718.5-118718.29"
+ attribute \src "libresoc.v:118543.5-118543.29"
switch \initial
- attribute \src "libresoc.v:118718.9-118718.17"
+ attribute \src "libresoc.v:118543.9-118543.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0]
end
- attribute \src "libresoc.v:118772.3-118826.6"
- process $proc$libresoc.v:118772$4451
+ attribute \src "libresoc.v:118597.3-118651.6"
+ process $proc$libresoc.v:118597$4435
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:118773.5-118773.29"
+ attribute \src "libresoc.v:118598.5-118598.29"
switch \initial
- attribute \src "libresoc.v:118773.9-118773.17"
+ attribute \src "libresoc.v:118598.9-118598.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0]
end
- attribute \src "libresoc.v:118827.3-118881.6"
- process $proc$libresoc.v:118827$4452
+ attribute \src "libresoc.v:118652.3-118706.6"
+ process $proc$libresoc.v:118652$4436
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:118828.5-118828.29"
+ attribute \src "libresoc.v:118653.5-118653.29"
switch \initial
- attribute \src "libresoc.v:118828.9-118828.17"
+ attribute \src "libresoc.v:118653.9-118653.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0]
end
- attribute \src "libresoc.v:118882.3-118936.6"
- process $proc$libresoc.v:118882$4453
+ attribute \src "libresoc.v:118707.3-118761.6"
+ process $proc$libresoc.v:118707$4437
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:118883.5-118883.29"
+ attribute \src "libresoc.v:118708.5-118708.29"
switch \initial
- attribute \src "libresoc.v:118883.9-118883.17"
+ attribute \src "libresoc.v:118708.9-118708.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0]
end
- attribute \src "libresoc.v:118937.3-118991.6"
- process $proc$libresoc.v:118937$4454
+ attribute \src "libresoc.v:118762.3-118816.6"
+ process $proc$libresoc.v:118762$4438
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:118938.5-118938.29"
+ attribute \src "libresoc.v:118763.5-118763.29"
switch \initial
- attribute \src "libresoc.v:118938.9-118938.17"
+ attribute \src "libresoc.v:118763.9-118763.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0]
end
- attribute \src "libresoc.v:118992.3-119046.6"
- process $proc$libresoc.v:118992$4455
+ attribute \src "libresoc.v:118817.3-118871.6"
+ process $proc$libresoc.v:118817$4439
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:118993.5-118993.29"
+ attribute \src "libresoc.v:118818.5-118818.29"
switch \initial
- attribute \src "libresoc.v:118993.9-118993.17"
+ attribute \src "libresoc.v:118818.9-118818.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:119047.3-119101.6"
- process $proc$libresoc.v:119047$4456
+ attribute \src "libresoc.v:118872.3-118926.6"
+ process $proc$libresoc.v:118872$4440
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:119048.5-119048.29"
+ attribute \src "libresoc.v:118873.5-118873.29"
switch \initial
- attribute \src "libresoc.v:119048.9-119048.17"
+ attribute \src "libresoc.v:118873.9-118873.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0]
end
- attribute \src "libresoc.v:119102.3-119156.6"
- process $proc$libresoc.v:119102$4457
+ attribute \src "libresoc.v:118927.3-118981.6"
+ process $proc$libresoc.v:118927$4441
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:119103.5-119103.29"
+ attribute \src "libresoc.v:118928.5-118928.29"
switch \initial
- attribute \src "libresoc.v:119103.9-119103.17"
+ attribute \src "libresoc.v:118928.9-118928.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:119157.3-119211.6"
- process $proc$libresoc.v:119157$4458
+ attribute \src "libresoc.v:118982.3-119036.6"
+ process $proc$libresoc.v:118982$4442
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:119158.5-119158.29"
+ attribute \src "libresoc.v:118983.5-118983.29"
switch \initial
- attribute \src "libresoc.v:119158.9-119158.17"
+ attribute \src "libresoc.v:118983.9-118983.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0]
end
- attribute \src "libresoc.v:119212.3-119266.6"
- process $proc$libresoc.v:119212$4459
+ attribute \src "libresoc.v:119037.3-119091.6"
+ process $proc$libresoc.v:119037$4443
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:119213.5-119213.29"
+ attribute \src "libresoc.v:119038.5-119038.29"
switch \initial
- attribute \src "libresoc.v:119213.9-119213.17"
+ attribute \src "libresoc.v:119038.9-119038.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0]
end
- attribute \src "libresoc.v:119267.3-119321.6"
- process $proc$libresoc.v:119267$4460
+ attribute \src "libresoc.v:119092.3-119146.6"
+ process $proc$libresoc.v:119092$4444
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:119268.5-119268.29"
+ attribute \src "libresoc.v:119093.5-119093.29"
switch \initial
- attribute \src "libresoc.v:119268.9-119268.17"
+ attribute \src "libresoc.v:119093.9-119093.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0]
end
- attribute \src "libresoc.v:119322.3-119376.6"
- process $proc$libresoc.v:119322$4461
+ attribute \src "libresoc.v:119147.3-119201.6"
+ process $proc$libresoc.v:119147$4445
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0]
- attribute \src "libresoc.v:119323.5-119323.29"
+ attribute \src "libresoc.v:119148.5-119148.29"
switch \initial
- attribute \src "libresoc.v:119323.9-119323.17"
+ attribute \src "libresoc.v:119148.9-119148.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:119382.1-120260.10"
+attribute \src "libresoc.v:119207.1-120085.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58"
attribute \generator "nMigen"
module \dec58
- attribute \src "libresoc.v:120163.3-120178.6"
+ attribute \src "libresoc.v:119988.3-120003.6"
wire width 2 $0\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:120179.3-120194.6"
+ attribute \src "libresoc.v:120004.3-120019.6"
wire width 2 $0\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:119971.3-119986.6"
+ attribute \src "libresoc.v:119796.3-119811.6"
wire width 8 $0\dec58_asmcode[7:0]
- attribute \src "libresoc.v:120035.3-120050.6"
+ attribute \src "libresoc.v:119860.3-119875.6"
wire $0\dec58_br[0:0]
- attribute \src "libresoc.v:119747.3-119762.6"
+ attribute \src "libresoc.v:119572.3-119587.6"
wire width 3 $0\dec58_cr_in[2:0]
- attribute \src "libresoc.v:119763.3-119778.6"
+ attribute \src "libresoc.v:119588.3-119603.6"
wire width 3 $0\dec58_cr_out[2:0]
- attribute \src "libresoc.v:119955.3-119970.6"
+ attribute \src "libresoc.v:119780.3-119795.6"
wire width 2 $0\dec58_cry_in[1:0]
- attribute \src "libresoc.v:120019.3-120034.6"
+ attribute \src "libresoc.v:119844.3-119859.6"
wire $0\dec58_cry_out[0:0]
- attribute \src "libresoc.v:120083.3-120098.6"
+ attribute \src "libresoc.v:119908.3-119923.6"
wire width 5 $0\dec58_form[4:0]
- attribute \src "libresoc.v:119731.3-119746.6"
+ attribute \src "libresoc.v:119556.3-119571.6"
wire width 14 $0\dec58_function_unit[13:0]
- attribute \src "libresoc.v:120195.3-120210.6"
+ attribute \src "libresoc.v:120020.3-120035.6"
wire width 3 $0\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:120211.3-120226.6"
+ attribute \src "libresoc.v:120036.3-120051.6"
wire width 4 $0\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:120227.3-120242.6"
+ attribute \src "libresoc.v:120052.3-120067.6"
wire width 2 $0\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:119907.3-119922.6"
+ attribute \src "libresoc.v:119732.3-119747.6"
wire width 7 $0\dec58_internal_op[6:0]
- attribute \src "libresoc.v:119987.3-120002.6"
+ attribute \src "libresoc.v:119812.3-119827.6"
wire $0\dec58_inv_a[0:0]
- attribute \src "libresoc.v:120003.3-120018.6"
+ attribute \src "libresoc.v:119828.3-119843.6"
wire $0\dec58_inv_out[0:0]
- attribute \src "libresoc.v:120099.3-120114.6"
+ attribute \src "libresoc.v:119924.3-119939.6"
wire $0\dec58_is_32b[0:0]
- attribute \src "libresoc.v:119891.3-119906.6"
+ attribute \src "libresoc.v:119716.3-119731.6"
wire width 4 $0\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:120131.3-120146.6"
+ attribute \src "libresoc.v:119956.3-119971.6"
wire $0\dec58_lk[0:0]
- attribute \src "libresoc.v:120243.3-120258.6"
+ attribute \src "libresoc.v:120068.3-120083.6"
wire width 3 $0\dec58_out_sel[2:0]
- attribute \src "libresoc.v:119939.3-119954.6"
+ attribute \src "libresoc.v:119764.3-119779.6"
wire width 2 $0\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:120067.3-120082.6"
+ attribute \src "libresoc.v:119892.3-119907.6"
wire $0\dec58_rsrv[0:0]
- attribute \src "libresoc.v:120147.3-120162.6"
+ attribute \src "libresoc.v:119972.3-119987.6"
wire $0\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:120115.3-120130.6"
+ attribute \src "libresoc.v:119940.3-119955.6"
wire $0\dec58_sgn[0:0]
- attribute \src "libresoc.v:120051.3-120066.6"
+ attribute \src "libresoc.v:119876.3-119891.6"
wire $0\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:119859.3-119874.6"
+ attribute \src "libresoc.v:119684.3-119699.6"
wire width 3 $0\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:119875.3-119890.6"
+ attribute \src "libresoc.v:119700.3-119715.6"
wire width 3 $0\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:119779.3-119794.6"
+ attribute \src "libresoc.v:119604.3-119619.6"
wire width 3 $0\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:119795.3-119810.6"
+ attribute \src "libresoc.v:119620.3-119635.6"
wire width 3 $0\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:119811.3-119826.6"
+ attribute \src "libresoc.v:119636.3-119651.6"
wire width 3 $0\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:119843.3-119858.6"
+ attribute \src "libresoc.v:119668.3-119683.6"
wire width 3 $0\dec58_sv_out2[2:0]
- attribute \src "libresoc.v:119827.3-119842.6"
+ attribute \src "libresoc.v:119652.3-119667.6"
wire width 3 $0\dec58_sv_out[2:0]
- attribute \src "libresoc.v:119923.3-119938.6"
+ attribute \src "libresoc.v:119748.3-119763.6"
wire width 2 $0\dec58_upd[1:0]
- attribute \src "libresoc.v:119383.7-119383.20"
+ attribute \src "libresoc.v:119208.7-119208.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:120163.3-120178.6"
+ attribute \src "libresoc.v:119988.3-120003.6"
wire width 2 $1\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:120179.3-120194.6"
+ attribute \src "libresoc.v:120004.3-120019.6"
wire width 2 $1\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:119971.3-119986.6"
+ attribute \src "libresoc.v:119796.3-119811.6"
wire width 8 $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:120035.3-120050.6"
+ attribute \src "libresoc.v:119860.3-119875.6"
wire $1\dec58_br[0:0]
- attribute \src "libresoc.v:119747.3-119762.6"
+ attribute \src "libresoc.v:119572.3-119587.6"
wire width 3 $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:119763.3-119778.6"
+ attribute \src "libresoc.v:119588.3-119603.6"
wire width 3 $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:119955.3-119970.6"
+ attribute \src "libresoc.v:119780.3-119795.6"
wire width 2 $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:120019.3-120034.6"
+ attribute \src "libresoc.v:119844.3-119859.6"
wire $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:120083.3-120098.6"
+ attribute \src "libresoc.v:119908.3-119923.6"
wire width 5 $1\dec58_form[4:0]
- attribute \src "libresoc.v:119731.3-119746.6"
+ attribute \src "libresoc.v:119556.3-119571.6"
wire width 14 $1\dec58_function_unit[13:0]
- attribute \src "libresoc.v:120195.3-120210.6"
+ attribute \src "libresoc.v:120020.3-120035.6"
wire width 3 $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:120211.3-120226.6"
+ attribute \src "libresoc.v:120036.3-120051.6"
wire width 4 $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:120227.3-120242.6"
+ attribute \src "libresoc.v:120052.3-120067.6"
wire width 2 $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:119907.3-119922.6"
+ attribute \src "libresoc.v:119732.3-119747.6"
wire width 7 $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:119987.3-120002.6"
+ attribute \src "libresoc.v:119812.3-119827.6"
wire $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:120003.3-120018.6"
+ attribute \src "libresoc.v:119828.3-119843.6"
wire $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:120099.3-120114.6"
+ attribute \src "libresoc.v:119924.3-119939.6"
wire $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:119891.3-119906.6"
+ attribute \src "libresoc.v:119716.3-119731.6"
wire width 4 $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:120131.3-120146.6"
+ attribute \src "libresoc.v:119956.3-119971.6"
wire $1\dec58_lk[0:0]
- attribute \src "libresoc.v:120243.3-120258.6"
+ attribute \src "libresoc.v:120068.3-120083.6"
wire width 3 $1\dec58_out_sel[2:0]
- attribute \src "libresoc.v:119939.3-119954.6"
+ attribute \src "libresoc.v:119764.3-119779.6"
wire width 2 $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:120067.3-120082.6"
+ attribute \src "libresoc.v:119892.3-119907.6"
wire $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:120147.3-120162.6"
+ attribute \src "libresoc.v:119972.3-119987.6"
wire $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:120115.3-120130.6"
+ attribute \src "libresoc.v:119940.3-119955.6"
wire $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:120051.3-120066.6"
+ attribute \src "libresoc.v:119876.3-119891.6"
wire $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:119859.3-119874.6"
+ attribute \src "libresoc.v:119684.3-119699.6"
wire width 3 $1\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:119875.3-119890.6"
+ attribute \src "libresoc.v:119700.3-119715.6"
wire width 3 $1\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:119779.3-119794.6"
+ attribute \src "libresoc.v:119604.3-119619.6"
wire width 3 $1\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:119795.3-119810.6"
+ attribute \src "libresoc.v:119620.3-119635.6"
wire width 3 $1\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:119811.3-119826.6"
+ attribute \src "libresoc.v:119636.3-119651.6"
wire width 3 $1\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:119843.3-119858.6"
+ attribute \src "libresoc.v:119668.3-119683.6"
wire width 3 $1\dec58_sv_out2[2:0]
- attribute \src "libresoc.v:119827.3-119842.6"
+ attribute \src "libresoc.v:119652.3-119667.6"
wire width 3 $1\dec58_sv_out[2:0]
- attribute \src "libresoc.v:119923.3-119938.6"
+ attribute \src "libresoc.v:119748.3-119763.6"
wire width 2 $1\dec58_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec58_upd
- attribute \src "libresoc.v:119383.7-119383.15"
+ attribute \src "libresoc.v:119208.7-119208.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:119383.7-119383.20"
- process $proc$libresoc.v:119383$4496
+ attribute \src "libresoc.v:119208.7-119208.20"
+ process $proc$libresoc.v:119208$4480
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:119731.3-119746.6"
- process $proc$libresoc.v:119731$4463
+ attribute \src "libresoc.v:119556.3-119571.6"
+ process $proc$libresoc.v:119556$4447
assign { } { }
assign { } { }
assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0]
- attribute \src "libresoc.v:119732.5-119732.29"
+ attribute \src "libresoc.v:119557.5-119557.29"
switch \initial
- attribute \src "libresoc.v:119732.9-119732.17"
+ attribute \src "libresoc.v:119557.9-119557.17"
case 1'1
case
end
sync always
update \dec58_function_unit $0\dec58_function_unit[13:0]
end
- attribute \src "libresoc.v:119747.3-119762.6"
- process $proc$libresoc.v:119747$4464
+ attribute \src "libresoc.v:119572.3-119587.6"
+ process $proc$libresoc.v:119572$4448
assign { } { }
assign { } { }
assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:119748.5-119748.29"
+ attribute \src "libresoc.v:119573.5-119573.29"
switch \initial
- attribute \src "libresoc.v:119748.9-119748.17"
+ attribute \src "libresoc.v:119573.9-119573.17"
case 1'1
case
end
sync always
update \dec58_cr_in $0\dec58_cr_in[2:0]
end
- attribute \src "libresoc.v:119763.3-119778.6"
- process $proc$libresoc.v:119763$4465
+ attribute \src "libresoc.v:119588.3-119603.6"
+ process $proc$libresoc.v:119588$4449
assign { } { }
assign { } { }
assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:119764.5-119764.29"
+ attribute \src "libresoc.v:119589.5-119589.29"
switch \initial
- attribute \src "libresoc.v:119764.9-119764.17"
+ attribute \src "libresoc.v:119589.9-119589.17"
case 1'1
case
end
sync always
update \dec58_cr_out $0\dec58_cr_out[2:0]
end
- attribute \src "libresoc.v:119779.3-119794.6"
- process $proc$libresoc.v:119779$4466
+ attribute \src "libresoc.v:119604.3-119619.6"
+ process $proc$libresoc.v:119604$4450
assign { } { }
assign { } { }
assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:119780.5-119780.29"
+ attribute \src "libresoc.v:119605.5-119605.29"
switch \initial
- attribute \src "libresoc.v:119780.9-119780.17"
+ attribute \src "libresoc.v:119605.9-119605.17"
case 1'1
case
end
sync always
update \dec58_sv_in1 $0\dec58_sv_in1[2:0]
end
- attribute \src "libresoc.v:119795.3-119810.6"
- process $proc$libresoc.v:119795$4467
+ attribute \src "libresoc.v:119620.3-119635.6"
+ process $proc$libresoc.v:119620$4451
assign { } { }
assign { } { }
assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:119796.5-119796.29"
+ attribute \src "libresoc.v:119621.5-119621.29"
switch \initial
- attribute \src "libresoc.v:119796.9-119796.17"
+ attribute \src "libresoc.v:119621.9-119621.17"
case 1'1
case
end
sync always
update \dec58_sv_in2 $0\dec58_sv_in2[2:0]
end
- attribute \src "libresoc.v:119811.3-119826.6"
- process $proc$libresoc.v:119811$4468
+ attribute \src "libresoc.v:119636.3-119651.6"
+ process $proc$libresoc.v:119636$4452
assign { } { }
assign { } { }
assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:119812.5-119812.29"
+ attribute \src "libresoc.v:119637.5-119637.29"
switch \initial
- attribute \src "libresoc.v:119812.9-119812.17"
+ attribute \src "libresoc.v:119637.9-119637.17"
case 1'1
case
end
sync always
update \dec58_sv_in3 $0\dec58_sv_in3[2:0]
end
- attribute \src "libresoc.v:119827.3-119842.6"
- process $proc$libresoc.v:119827$4469
+ attribute \src "libresoc.v:119652.3-119667.6"
+ process $proc$libresoc.v:119652$4453
assign { } { }
assign { } { }
assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0]
- attribute \src "libresoc.v:119828.5-119828.29"
+ attribute \src "libresoc.v:119653.5-119653.29"
switch \initial
- attribute \src "libresoc.v:119828.9-119828.17"
+ attribute \src "libresoc.v:119653.9-119653.17"
case 1'1
case
end
sync always
update \dec58_sv_out $0\dec58_sv_out[2:0]
end
- attribute \src "libresoc.v:119843.3-119858.6"
- process $proc$libresoc.v:119843$4470
+ attribute \src "libresoc.v:119668.3-119683.6"
+ process $proc$libresoc.v:119668$4454
assign { } { }
assign { } { }
assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0]
- attribute \src "libresoc.v:119844.5-119844.29"
+ attribute \src "libresoc.v:119669.5-119669.29"
switch \initial
- attribute \src "libresoc.v:119844.9-119844.17"
+ attribute \src "libresoc.v:119669.9-119669.17"
case 1'1
case
end
sync always
update \dec58_sv_out2 $0\dec58_sv_out2[2:0]
end
- attribute \src "libresoc.v:119859.3-119874.6"
- process $proc$libresoc.v:119859$4471
+ attribute \src "libresoc.v:119684.3-119699.6"
+ process $proc$libresoc.v:119684$4455
assign { } { }
assign { } { }
assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:119860.5-119860.29"
+ attribute \src "libresoc.v:119685.5-119685.29"
switch \initial
- attribute \src "libresoc.v:119860.9-119860.17"
+ attribute \src "libresoc.v:119685.9-119685.17"
case 1'1
case
end
sync always
update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:119875.3-119890.6"
- process $proc$libresoc.v:119875$4472
+ attribute \src "libresoc.v:119700.3-119715.6"
+ process $proc$libresoc.v:119700$4456
assign { } { }
assign { } { }
assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:119876.5-119876.29"
+ attribute \src "libresoc.v:119701.5-119701.29"
switch \initial
- attribute \src "libresoc.v:119876.9-119876.17"
+ attribute \src "libresoc.v:119701.9-119701.17"
case 1'1
case
end
sync always
update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:119891.3-119906.6"
- process $proc$libresoc.v:119891$4473
+ attribute \src "libresoc.v:119716.3-119731.6"
+ process $proc$libresoc.v:119716$4457
assign { } { }
assign { } { }
assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:119892.5-119892.29"
+ attribute \src "libresoc.v:119717.5-119717.29"
switch \initial
- attribute \src "libresoc.v:119892.9-119892.17"
+ attribute \src "libresoc.v:119717.9-119717.17"
case 1'1
case
end
sync always
update \dec58_ldst_len $0\dec58_ldst_len[3:0]
end
- attribute \src "libresoc.v:119907.3-119922.6"
- process $proc$libresoc.v:119907$4474
+ attribute \src "libresoc.v:119732.3-119747.6"
+ process $proc$libresoc.v:119732$4458
assign { } { }
assign { } { }
assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:119908.5-119908.29"
+ attribute \src "libresoc.v:119733.5-119733.29"
switch \initial
- attribute \src "libresoc.v:119908.9-119908.17"
+ attribute \src "libresoc.v:119733.9-119733.17"
case 1'1
case
end
sync always
update \dec58_internal_op $0\dec58_internal_op[6:0]
end
- attribute \src "libresoc.v:119923.3-119938.6"
- process $proc$libresoc.v:119923$4475
+ attribute \src "libresoc.v:119748.3-119763.6"
+ process $proc$libresoc.v:119748$4459
assign { } { }
assign { } { }
assign $0\dec58_upd[1:0] $1\dec58_upd[1:0]
- attribute \src "libresoc.v:119924.5-119924.29"
+ attribute \src "libresoc.v:119749.5-119749.29"
switch \initial
- attribute \src "libresoc.v:119924.9-119924.17"
+ attribute \src "libresoc.v:119749.9-119749.17"
case 1'1
case
end
sync always
update \dec58_upd $0\dec58_upd[1:0]
end
- attribute \src "libresoc.v:119939.3-119954.6"
- process $proc$libresoc.v:119939$4476
+ attribute \src "libresoc.v:119764.3-119779.6"
+ process $proc$libresoc.v:119764$4460
assign { } { }
assign { } { }
assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:119940.5-119940.29"
+ attribute \src "libresoc.v:119765.5-119765.29"
switch \initial
- attribute \src "libresoc.v:119940.9-119940.17"
+ attribute \src "libresoc.v:119765.9-119765.17"
case 1'1
case
end
sync always
update \dec58_rc_sel $0\dec58_rc_sel[1:0]
end
- attribute \src "libresoc.v:119955.3-119970.6"
- process $proc$libresoc.v:119955$4477
+ attribute \src "libresoc.v:119780.3-119795.6"
+ process $proc$libresoc.v:119780$4461
assign { } { }
assign { } { }
assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:119956.5-119956.29"
+ attribute \src "libresoc.v:119781.5-119781.29"
switch \initial
- attribute \src "libresoc.v:119956.9-119956.17"
+ attribute \src "libresoc.v:119781.9-119781.17"
case 1'1
case
end
sync always
update \dec58_cry_in $0\dec58_cry_in[1:0]
end
- attribute \src "libresoc.v:119971.3-119986.6"
- process $proc$libresoc.v:119971$4478
+ attribute \src "libresoc.v:119796.3-119811.6"
+ process $proc$libresoc.v:119796$4462
assign { } { }
assign { } { }
assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:119972.5-119972.29"
+ attribute \src "libresoc.v:119797.5-119797.29"
switch \initial
- attribute \src "libresoc.v:119972.9-119972.17"
+ attribute \src "libresoc.v:119797.9-119797.17"
case 1'1
case
end
sync always
update \dec58_asmcode $0\dec58_asmcode[7:0]
end
- attribute \src "libresoc.v:119987.3-120002.6"
- process $proc$libresoc.v:119987$4479
+ attribute \src "libresoc.v:119812.3-119827.6"
+ process $proc$libresoc.v:119812$4463
assign { } { }
assign { } { }
assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:119988.5-119988.29"
+ attribute \src "libresoc.v:119813.5-119813.29"
switch \initial
- attribute \src "libresoc.v:119988.9-119988.17"
+ attribute \src "libresoc.v:119813.9-119813.17"
case 1'1
case
end
sync always
update \dec58_inv_a $0\dec58_inv_a[0:0]
end
- attribute \src "libresoc.v:120003.3-120018.6"
- process $proc$libresoc.v:120003$4480
+ attribute \src "libresoc.v:119828.3-119843.6"
+ process $proc$libresoc.v:119828$4464
assign { } { }
assign { } { }
assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:120004.5-120004.29"
+ attribute \src "libresoc.v:119829.5-119829.29"
switch \initial
- attribute \src "libresoc.v:120004.9-120004.17"
+ attribute \src "libresoc.v:119829.9-119829.17"
case 1'1
case
end
sync always
update \dec58_inv_out $0\dec58_inv_out[0:0]
end
- attribute \src "libresoc.v:120019.3-120034.6"
- process $proc$libresoc.v:120019$4481
+ attribute \src "libresoc.v:119844.3-119859.6"
+ process $proc$libresoc.v:119844$4465
assign { } { }
assign { } { }
assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:120020.5-120020.29"
+ attribute \src "libresoc.v:119845.5-119845.29"
switch \initial
- attribute \src "libresoc.v:120020.9-120020.17"
+ attribute \src "libresoc.v:119845.9-119845.17"
case 1'1
case
end
sync always
update \dec58_cry_out $0\dec58_cry_out[0:0]
end
- attribute \src "libresoc.v:120035.3-120050.6"
- process $proc$libresoc.v:120035$4482
+ attribute \src "libresoc.v:119860.3-119875.6"
+ process $proc$libresoc.v:119860$4466
assign { } { }
assign { } { }
assign $0\dec58_br[0:0] $1\dec58_br[0:0]
- attribute \src "libresoc.v:120036.5-120036.29"
+ attribute \src "libresoc.v:119861.5-119861.29"
switch \initial
- attribute \src "libresoc.v:120036.9-120036.17"
+ attribute \src "libresoc.v:119861.9-119861.17"
case 1'1
case
end
sync always
update \dec58_br $0\dec58_br[0:0]
end
- attribute \src "libresoc.v:120051.3-120066.6"
- process $proc$libresoc.v:120051$4483
+ attribute \src "libresoc.v:119876.3-119891.6"
+ process $proc$libresoc.v:119876$4467
assign { } { }
assign { } { }
assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:120052.5-120052.29"
+ attribute \src "libresoc.v:119877.5-119877.29"
switch \initial
- attribute \src "libresoc.v:120052.9-120052.17"
+ attribute \src "libresoc.v:119877.9-119877.17"
case 1'1
case
end
sync always
update \dec58_sgn_ext $0\dec58_sgn_ext[0:0]
end
- attribute \src "libresoc.v:120067.3-120082.6"
- process $proc$libresoc.v:120067$4484
+ attribute \src "libresoc.v:119892.3-119907.6"
+ process $proc$libresoc.v:119892$4468
assign { } { }
assign { } { }
assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:120068.5-120068.29"
+ attribute \src "libresoc.v:119893.5-119893.29"
switch \initial
- attribute \src "libresoc.v:120068.9-120068.17"
+ attribute \src "libresoc.v:119893.9-119893.17"
case 1'1
case
end
sync always
update \dec58_rsrv $0\dec58_rsrv[0:0]
end
- attribute \src "libresoc.v:120083.3-120098.6"
- process $proc$libresoc.v:120083$4485
+ attribute \src "libresoc.v:119908.3-119923.6"
+ process $proc$libresoc.v:119908$4469
assign { } { }
assign { } { }
assign $0\dec58_form[4:0] $1\dec58_form[4:0]
- attribute \src "libresoc.v:120084.5-120084.29"
+ attribute \src "libresoc.v:119909.5-119909.29"
switch \initial
- attribute \src "libresoc.v:120084.9-120084.17"
+ attribute \src "libresoc.v:119909.9-119909.17"
case 1'1
case
end
sync always
update \dec58_form $0\dec58_form[4:0]
end
- attribute \src "libresoc.v:120099.3-120114.6"
- process $proc$libresoc.v:120099$4486
+ attribute \src "libresoc.v:119924.3-119939.6"
+ process $proc$libresoc.v:119924$4470
assign { } { }
assign { } { }
assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:120100.5-120100.29"
+ attribute \src "libresoc.v:119925.5-119925.29"
switch \initial
- attribute \src "libresoc.v:120100.9-120100.17"
+ attribute \src "libresoc.v:119925.9-119925.17"
case 1'1
case
end
sync always
update \dec58_is_32b $0\dec58_is_32b[0:0]
end
- attribute \src "libresoc.v:120115.3-120130.6"
- process $proc$libresoc.v:120115$4487
+ attribute \src "libresoc.v:119940.3-119955.6"
+ process $proc$libresoc.v:119940$4471
assign { } { }
assign { } { }
assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:120116.5-120116.29"
+ attribute \src "libresoc.v:119941.5-119941.29"
switch \initial
- attribute \src "libresoc.v:120116.9-120116.17"
+ attribute \src "libresoc.v:119941.9-119941.17"
case 1'1
case
end
sync always
update \dec58_sgn $0\dec58_sgn[0:0]
end
- attribute \src "libresoc.v:120131.3-120146.6"
- process $proc$libresoc.v:120131$4488
+ attribute \src "libresoc.v:119956.3-119971.6"
+ process $proc$libresoc.v:119956$4472
assign { } { }
assign { } { }
assign $0\dec58_lk[0:0] $1\dec58_lk[0:0]
- attribute \src "libresoc.v:120132.5-120132.29"
+ attribute \src "libresoc.v:119957.5-119957.29"
switch \initial
- attribute \src "libresoc.v:120132.9-120132.17"
+ attribute \src "libresoc.v:119957.9-119957.17"
case 1'1
case
end
sync always
update \dec58_lk $0\dec58_lk[0:0]
end
- attribute \src "libresoc.v:120147.3-120162.6"
- process $proc$libresoc.v:120147$4489
+ attribute \src "libresoc.v:119972.3-119987.6"
+ process $proc$libresoc.v:119972$4473
assign { } { }
assign { } { }
assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:120148.5-120148.29"
+ attribute \src "libresoc.v:119973.5-119973.29"
switch \initial
- attribute \src "libresoc.v:120148.9-120148.17"
+ attribute \src "libresoc.v:119973.9-119973.17"
case 1'1
case
end
sync always
update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:120163.3-120178.6"
- process $proc$libresoc.v:120163$4490
+ attribute \src "libresoc.v:119988.3-120003.6"
+ process $proc$libresoc.v:119988$4474
assign { } { }
assign { } { }
assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:120164.5-120164.29"
+ attribute \src "libresoc.v:119989.5-119989.29"
switch \initial
- attribute \src "libresoc.v:120164.9-120164.17"
+ attribute \src "libresoc.v:119989.9-119989.17"
case 1'1
case
end
sync always
update \dec58_SV_Etype $0\dec58_SV_Etype[1:0]
end
- attribute \src "libresoc.v:120179.3-120194.6"
- process $proc$libresoc.v:120179$4491
+ attribute \src "libresoc.v:120004.3-120019.6"
+ process $proc$libresoc.v:120004$4475
assign { } { }
assign { } { }
assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:120180.5-120180.29"
+ attribute \src "libresoc.v:120005.5-120005.29"
switch \initial
- attribute \src "libresoc.v:120180.9-120180.17"
+ attribute \src "libresoc.v:120005.9-120005.17"
case 1'1
case
end
sync always
update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:120195.3-120210.6"
- process $proc$libresoc.v:120195$4492
+ attribute \src "libresoc.v:120020.3-120035.6"
+ process $proc$libresoc.v:120020$4476
assign { } { }
assign { } { }
assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:120196.5-120196.29"
+ attribute \src "libresoc.v:120021.5-120021.29"
switch \initial
- attribute \src "libresoc.v:120196.9-120196.17"
+ attribute \src "libresoc.v:120021.9-120021.17"
case 1'1
case
end
sync always
update \dec58_in1_sel $0\dec58_in1_sel[2:0]
end
- attribute \src "libresoc.v:120211.3-120226.6"
- process $proc$libresoc.v:120211$4493
+ attribute \src "libresoc.v:120036.3-120051.6"
+ process $proc$libresoc.v:120036$4477
assign { } { }
assign { } { }
assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:120212.5-120212.29"
+ attribute \src "libresoc.v:120037.5-120037.29"
switch \initial
- attribute \src "libresoc.v:120212.9-120212.17"
+ attribute \src "libresoc.v:120037.9-120037.17"
case 1'1
case
end
sync always
update \dec58_in2_sel $0\dec58_in2_sel[3:0]
end
- attribute \src "libresoc.v:120227.3-120242.6"
- process $proc$libresoc.v:120227$4494
+ attribute \src "libresoc.v:120052.3-120067.6"
+ process $proc$libresoc.v:120052$4478
assign { } { }
assign { } { }
assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:120228.5-120228.29"
+ attribute \src "libresoc.v:120053.5-120053.29"
switch \initial
- attribute \src "libresoc.v:120228.9-120228.17"
+ attribute \src "libresoc.v:120053.9-120053.17"
case 1'1
case
end
sync always
update \dec58_in3_sel $0\dec58_in3_sel[1:0]
end
- attribute \src "libresoc.v:120243.3-120258.6"
- process $proc$libresoc.v:120243$4495
+ attribute \src "libresoc.v:120068.3-120083.6"
+ process $proc$libresoc.v:120068$4479
assign { } { }
assign { } { }
assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0]
- attribute \src "libresoc.v:120244.5-120244.29"
+ attribute \src "libresoc.v:120069.5-120069.29"
switch \initial
- attribute \src "libresoc.v:120244.9-120244.17"
+ attribute \src "libresoc.v:120069.9-120069.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:120264.1-121043.10"
+attribute \src "libresoc.v:120089.1-120868.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62"
attribute \generator "nMigen"
module \dec62
- attribute \src "libresoc.v:120964.3-120976.6"
+ attribute \src "libresoc.v:120789.3-120801.6"
wire width 2 $0\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:120977.3-120989.6"
+ attribute \src "libresoc.v:120802.3-120814.6"
wire width 2 $0\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:120808.3-120820.6"
+ attribute \src "libresoc.v:120633.3-120645.6"
wire width 8 $0\dec62_asmcode[7:0]
- attribute \src "libresoc.v:120860.3-120872.6"
+ attribute \src "libresoc.v:120685.3-120697.6"
wire $0\dec62_br[0:0]
- attribute \src "libresoc.v:120626.3-120638.6"
+ attribute \src "libresoc.v:120451.3-120463.6"
wire width 3 $0\dec62_cr_in[2:0]
- attribute \src "libresoc.v:120639.3-120651.6"
+ attribute \src "libresoc.v:120464.3-120476.6"
wire width 3 $0\dec62_cr_out[2:0]
- attribute \src "libresoc.v:120795.3-120807.6"
+ attribute \src "libresoc.v:120620.3-120632.6"
wire width 2 $0\dec62_cry_in[1:0]
- attribute \src "libresoc.v:120847.3-120859.6"
+ attribute \src "libresoc.v:120672.3-120684.6"
wire $0\dec62_cry_out[0:0]
- attribute \src "libresoc.v:120899.3-120911.6"
+ attribute \src "libresoc.v:120724.3-120736.6"
wire width 5 $0\dec62_form[4:0]
- attribute \src "libresoc.v:120613.3-120625.6"
+ attribute \src "libresoc.v:120438.3-120450.6"
wire width 14 $0\dec62_function_unit[13:0]
- attribute \src "libresoc.v:120990.3-121002.6"
+ attribute \src "libresoc.v:120815.3-120827.6"
wire width 3 $0\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:121003.3-121015.6"
+ attribute \src "libresoc.v:120828.3-120840.6"
wire width 4 $0\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:121016.3-121028.6"
+ attribute \src "libresoc.v:120841.3-120853.6"
wire width 2 $0\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:120756.3-120768.6"
+ attribute \src "libresoc.v:120581.3-120593.6"
wire width 7 $0\dec62_internal_op[6:0]
- attribute \src "libresoc.v:120821.3-120833.6"
+ attribute \src "libresoc.v:120646.3-120658.6"
wire $0\dec62_inv_a[0:0]
- attribute \src "libresoc.v:120834.3-120846.6"
+ attribute \src "libresoc.v:120659.3-120671.6"
wire $0\dec62_inv_out[0:0]
- attribute \src "libresoc.v:120912.3-120924.6"
+ attribute \src "libresoc.v:120737.3-120749.6"
wire $0\dec62_is_32b[0:0]
- attribute \src "libresoc.v:120743.3-120755.6"
+ attribute \src "libresoc.v:120568.3-120580.6"
wire width 4 $0\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:120938.3-120950.6"
+ attribute \src "libresoc.v:120763.3-120775.6"
wire $0\dec62_lk[0:0]
- attribute \src "libresoc.v:121029.3-121041.6"
+ attribute \src "libresoc.v:120854.3-120866.6"
wire width 3 $0\dec62_out_sel[2:0]
- attribute \src "libresoc.v:120782.3-120794.6"
+ attribute \src "libresoc.v:120607.3-120619.6"
wire width 2 $0\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:120886.3-120898.6"
+ attribute \src "libresoc.v:120711.3-120723.6"
wire $0\dec62_rsrv[0:0]
- attribute \src "libresoc.v:120951.3-120963.6"
+ attribute \src "libresoc.v:120776.3-120788.6"
wire $0\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:120925.3-120937.6"
+ attribute \src "libresoc.v:120750.3-120762.6"
wire $0\dec62_sgn[0:0]
- attribute \src "libresoc.v:120873.3-120885.6"
+ attribute \src "libresoc.v:120698.3-120710.6"
wire $0\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:120717.3-120729.6"
+ attribute \src "libresoc.v:120542.3-120554.6"
wire width 3 $0\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:120730.3-120742.6"
+ attribute \src "libresoc.v:120555.3-120567.6"
wire width 3 $0\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:120652.3-120664.6"
+ attribute \src "libresoc.v:120477.3-120489.6"
wire width 3 $0\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:120665.3-120677.6"
+ attribute \src "libresoc.v:120490.3-120502.6"
wire width 3 $0\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:120678.3-120690.6"
+ attribute \src "libresoc.v:120503.3-120515.6"
wire width 3 $0\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:120704.3-120716.6"
+ attribute \src "libresoc.v:120529.3-120541.6"
wire width 3 $0\dec62_sv_out2[2:0]
- attribute \src "libresoc.v:120691.3-120703.6"
+ attribute \src "libresoc.v:120516.3-120528.6"
wire width 3 $0\dec62_sv_out[2:0]
- attribute \src "libresoc.v:120769.3-120781.6"
+ attribute \src "libresoc.v:120594.3-120606.6"
wire width 2 $0\dec62_upd[1:0]
- attribute \src "libresoc.v:120265.7-120265.20"
+ attribute \src "libresoc.v:120090.7-120090.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:120964.3-120976.6"
+ attribute \src "libresoc.v:120789.3-120801.6"
wire width 2 $1\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:120977.3-120989.6"
+ attribute \src "libresoc.v:120802.3-120814.6"
wire width 2 $1\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:120808.3-120820.6"
+ attribute \src "libresoc.v:120633.3-120645.6"
wire width 8 $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:120860.3-120872.6"
+ attribute \src "libresoc.v:120685.3-120697.6"
wire $1\dec62_br[0:0]
- attribute \src "libresoc.v:120626.3-120638.6"
+ attribute \src "libresoc.v:120451.3-120463.6"
wire width 3 $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:120639.3-120651.6"
+ attribute \src "libresoc.v:120464.3-120476.6"
wire width 3 $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:120795.3-120807.6"
+ attribute \src "libresoc.v:120620.3-120632.6"
wire width 2 $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:120847.3-120859.6"
+ attribute \src "libresoc.v:120672.3-120684.6"
wire $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:120899.3-120911.6"
+ attribute \src "libresoc.v:120724.3-120736.6"
wire width 5 $1\dec62_form[4:0]
- attribute \src "libresoc.v:120613.3-120625.6"
+ attribute \src "libresoc.v:120438.3-120450.6"
wire width 14 $1\dec62_function_unit[13:0]
- attribute \src "libresoc.v:120990.3-121002.6"
+ attribute \src "libresoc.v:120815.3-120827.6"
wire width 3 $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:121003.3-121015.6"
+ attribute \src "libresoc.v:120828.3-120840.6"
wire width 4 $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:121016.3-121028.6"
+ attribute \src "libresoc.v:120841.3-120853.6"
wire width 2 $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:120756.3-120768.6"
+ attribute \src "libresoc.v:120581.3-120593.6"
wire width 7 $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:120821.3-120833.6"
+ attribute \src "libresoc.v:120646.3-120658.6"
wire $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:120834.3-120846.6"
+ attribute \src "libresoc.v:120659.3-120671.6"
wire $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:120912.3-120924.6"
+ attribute \src "libresoc.v:120737.3-120749.6"
wire $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:120743.3-120755.6"
+ attribute \src "libresoc.v:120568.3-120580.6"
wire width 4 $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:120938.3-120950.6"
+ attribute \src "libresoc.v:120763.3-120775.6"
wire $1\dec62_lk[0:0]
- attribute \src "libresoc.v:121029.3-121041.6"
+ attribute \src "libresoc.v:120854.3-120866.6"
wire width 3 $1\dec62_out_sel[2:0]
- attribute \src "libresoc.v:120782.3-120794.6"
+ attribute \src "libresoc.v:120607.3-120619.6"
wire width 2 $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:120886.3-120898.6"
+ attribute \src "libresoc.v:120711.3-120723.6"
wire $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:120951.3-120963.6"
+ attribute \src "libresoc.v:120776.3-120788.6"
wire $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:120925.3-120937.6"
+ attribute \src "libresoc.v:120750.3-120762.6"
wire $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:120873.3-120885.6"
+ attribute \src "libresoc.v:120698.3-120710.6"
wire $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:120717.3-120729.6"
+ attribute \src "libresoc.v:120542.3-120554.6"
wire width 3 $1\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:120730.3-120742.6"
+ attribute \src "libresoc.v:120555.3-120567.6"
wire width 3 $1\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:120652.3-120664.6"
+ attribute \src "libresoc.v:120477.3-120489.6"
wire width 3 $1\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:120665.3-120677.6"
+ attribute \src "libresoc.v:120490.3-120502.6"
wire width 3 $1\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:120678.3-120690.6"
+ attribute \src "libresoc.v:120503.3-120515.6"
wire width 3 $1\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:120704.3-120716.6"
+ attribute \src "libresoc.v:120529.3-120541.6"
wire width 3 $1\dec62_sv_out2[2:0]
- attribute \src "libresoc.v:120691.3-120703.6"
+ attribute \src "libresoc.v:120516.3-120528.6"
wire width 3 $1\dec62_sv_out[2:0]
- attribute \src "libresoc.v:120769.3-120781.6"
+ attribute \src "libresoc.v:120594.3-120606.6"
wire width 2 $1\dec62_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 output 21 \dec62_upd
- attribute \src "libresoc.v:120265.7-120265.15"
+ attribute \src "libresoc.v:120090.7-120090.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 input 34 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:120265.7-120265.20"
- process $proc$libresoc.v:120265$4530
+ attribute \src "libresoc.v:120090.7-120090.20"
+ process $proc$libresoc.v:120090$4514
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:120613.3-120625.6"
- process $proc$libresoc.v:120613$4497
+ attribute \src "libresoc.v:120438.3-120450.6"
+ process $proc$libresoc.v:120438$4481
assign { } { }
assign { } { }
assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0]
- attribute \src "libresoc.v:120614.5-120614.29"
+ attribute \src "libresoc.v:120439.5-120439.29"
switch \initial
- attribute \src "libresoc.v:120614.9-120614.17"
+ attribute \src "libresoc.v:120439.9-120439.17"
case 1'1
case
end
sync always
update \dec62_function_unit $0\dec62_function_unit[13:0]
end
- attribute \src "libresoc.v:120626.3-120638.6"
- process $proc$libresoc.v:120626$4498
+ attribute \src "libresoc.v:120451.3-120463.6"
+ process $proc$libresoc.v:120451$4482
assign { } { }
assign { } { }
assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:120627.5-120627.29"
+ attribute \src "libresoc.v:120452.5-120452.29"
switch \initial
- attribute \src "libresoc.v:120627.9-120627.17"
+ attribute \src "libresoc.v:120452.9-120452.17"
case 1'1
case
end
sync always
update \dec62_cr_in $0\dec62_cr_in[2:0]
end
- attribute \src "libresoc.v:120639.3-120651.6"
- process $proc$libresoc.v:120639$4499
+ attribute \src "libresoc.v:120464.3-120476.6"
+ process $proc$libresoc.v:120464$4483
assign { } { }
assign { } { }
assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:120640.5-120640.29"
+ attribute \src "libresoc.v:120465.5-120465.29"
switch \initial
- attribute \src "libresoc.v:120640.9-120640.17"
+ attribute \src "libresoc.v:120465.9-120465.17"
case 1'1
case
end
sync always
update \dec62_cr_out $0\dec62_cr_out[2:0]
end
- attribute \src "libresoc.v:120652.3-120664.6"
- process $proc$libresoc.v:120652$4500
+ attribute \src "libresoc.v:120477.3-120489.6"
+ process $proc$libresoc.v:120477$4484
assign { } { }
assign { } { }
assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:120653.5-120653.29"
+ attribute \src "libresoc.v:120478.5-120478.29"
switch \initial
- attribute \src "libresoc.v:120653.9-120653.17"
+ attribute \src "libresoc.v:120478.9-120478.17"
case 1'1
case
end
sync always
update \dec62_sv_in1 $0\dec62_sv_in1[2:0]
end
- attribute \src "libresoc.v:120665.3-120677.6"
- process $proc$libresoc.v:120665$4501
+ attribute \src "libresoc.v:120490.3-120502.6"
+ process $proc$libresoc.v:120490$4485
assign { } { }
assign { } { }
assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:120666.5-120666.29"
+ attribute \src "libresoc.v:120491.5-120491.29"
switch \initial
- attribute \src "libresoc.v:120666.9-120666.17"
+ attribute \src "libresoc.v:120491.9-120491.17"
case 1'1
case
end
sync always
update \dec62_sv_in2 $0\dec62_sv_in2[2:0]
end
- attribute \src "libresoc.v:120678.3-120690.6"
- process $proc$libresoc.v:120678$4502
+ attribute \src "libresoc.v:120503.3-120515.6"
+ process $proc$libresoc.v:120503$4486
assign { } { }
assign { } { }
assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:120679.5-120679.29"
+ attribute \src "libresoc.v:120504.5-120504.29"
switch \initial
- attribute \src "libresoc.v:120679.9-120679.17"
+ attribute \src "libresoc.v:120504.9-120504.17"
case 1'1
case
end
sync always
update \dec62_sv_in3 $0\dec62_sv_in3[2:0]
end
- attribute \src "libresoc.v:120691.3-120703.6"
- process $proc$libresoc.v:120691$4503
+ attribute \src "libresoc.v:120516.3-120528.6"
+ process $proc$libresoc.v:120516$4487
assign { } { }
assign { } { }
assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0]
- attribute \src "libresoc.v:120692.5-120692.29"
+ attribute \src "libresoc.v:120517.5-120517.29"
switch \initial
- attribute \src "libresoc.v:120692.9-120692.17"
+ attribute \src "libresoc.v:120517.9-120517.17"
case 1'1
case
end
sync always
update \dec62_sv_out $0\dec62_sv_out[2:0]
end
- attribute \src "libresoc.v:120704.3-120716.6"
- process $proc$libresoc.v:120704$4504
+ attribute \src "libresoc.v:120529.3-120541.6"
+ process $proc$libresoc.v:120529$4488
assign { } { }
assign { } { }
assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0]
- attribute \src "libresoc.v:120705.5-120705.29"
+ attribute \src "libresoc.v:120530.5-120530.29"
switch \initial
- attribute \src "libresoc.v:120705.9-120705.17"
+ attribute \src "libresoc.v:120530.9-120530.17"
case 1'1
case
end
sync always
update \dec62_sv_out2 $0\dec62_sv_out2[2:0]
end
- attribute \src "libresoc.v:120717.3-120729.6"
- process $proc$libresoc.v:120717$4505
+ attribute \src "libresoc.v:120542.3-120554.6"
+ process $proc$libresoc.v:120542$4489
assign { } { }
assign { } { }
assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:120718.5-120718.29"
+ attribute \src "libresoc.v:120543.5-120543.29"
switch \initial
- attribute \src "libresoc.v:120718.9-120718.17"
+ attribute \src "libresoc.v:120543.9-120543.17"
case 1'1
case
end
sync always
update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:120730.3-120742.6"
- process $proc$libresoc.v:120730$4506
+ attribute \src "libresoc.v:120555.3-120567.6"
+ process $proc$libresoc.v:120555$4490
assign { } { }
assign { } { }
assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:120731.5-120731.29"
+ attribute \src "libresoc.v:120556.5-120556.29"
switch \initial
- attribute \src "libresoc.v:120731.9-120731.17"
+ attribute \src "libresoc.v:120556.9-120556.17"
case 1'1
case
end
sync always
update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:120743.3-120755.6"
- process $proc$libresoc.v:120743$4507
+ attribute \src "libresoc.v:120568.3-120580.6"
+ process $proc$libresoc.v:120568$4491
assign { } { }
assign { } { }
assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:120744.5-120744.29"
+ attribute \src "libresoc.v:120569.5-120569.29"
switch \initial
- attribute \src "libresoc.v:120744.9-120744.17"
+ attribute \src "libresoc.v:120569.9-120569.17"
case 1'1
case
end
sync always
update \dec62_ldst_len $0\dec62_ldst_len[3:0]
end
- attribute \src "libresoc.v:120756.3-120768.6"
- process $proc$libresoc.v:120756$4508
+ attribute \src "libresoc.v:120581.3-120593.6"
+ process $proc$libresoc.v:120581$4492
assign { } { }
assign { } { }
assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:120757.5-120757.29"
+ attribute \src "libresoc.v:120582.5-120582.29"
switch \initial
- attribute \src "libresoc.v:120757.9-120757.17"
+ attribute \src "libresoc.v:120582.9-120582.17"
case 1'1
case
end
sync always
update \dec62_internal_op $0\dec62_internal_op[6:0]
end
- attribute \src "libresoc.v:120769.3-120781.6"
- process $proc$libresoc.v:120769$4509
+ attribute \src "libresoc.v:120594.3-120606.6"
+ process $proc$libresoc.v:120594$4493
assign { } { }
assign { } { }
assign $0\dec62_upd[1:0] $1\dec62_upd[1:0]
- attribute \src "libresoc.v:120770.5-120770.29"
+ attribute \src "libresoc.v:120595.5-120595.29"
switch \initial
- attribute \src "libresoc.v:120770.9-120770.17"
+ attribute \src "libresoc.v:120595.9-120595.17"
case 1'1
case
end
sync always
update \dec62_upd $0\dec62_upd[1:0]
end
- attribute \src "libresoc.v:120782.3-120794.6"
- process $proc$libresoc.v:120782$4510
+ attribute \src "libresoc.v:120607.3-120619.6"
+ process $proc$libresoc.v:120607$4494
assign { } { }
assign { } { }
assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:120783.5-120783.29"
+ attribute \src "libresoc.v:120608.5-120608.29"
switch \initial
- attribute \src "libresoc.v:120783.9-120783.17"
+ attribute \src "libresoc.v:120608.9-120608.17"
case 1'1
case
end
sync always
update \dec62_rc_sel $0\dec62_rc_sel[1:0]
end
- attribute \src "libresoc.v:120795.3-120807.6"
- process $proc$libresoc.v:120795$4511
+ attribute \src "libresoc.v:120620.3-120632.6"
+ process $proc$libresoc.v:120620$4495
assign { } { }
assign { } { }
assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:120796.5-120796.29"
+ attribute \src "libresoc.v:120621.5-120621.29"
switch \initial
- attribute \src "libresoc.v:120796.9-120796.17"
+ attribute \src "libresoc.v:120621.9-120621.17"
case 1'1
case
end
sync always
update \dec62_cry_in $0\dec62_cry_in[1:0]
end
- attribute \src "libresoc.v:120808.3-120820.6"
- process $proc$libresoc.v:120808$4512
+ attribute \src "libresoc.v:120633.3-120645.6"
+ process $proc$libresoc.v:120633$4496
assign { } { }
assign { } { }
assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:120809.5-120809.29"
+ attribute \src "libresoc.v:120634.5-120634.29"
switch \initial
- attribute \src "libresoc.v:120809.9-120809.17"
+ attribute \src "libresoc.v:120634.9-120634.17"
case 1'1
case
end
sync always
update \dec62_asmcode $0\dec62_asmcode[7:0]
end
- attribute \src "libresoc.v:120821.3-120833.6"
- process $proc$libresoc.v:120821$4513
+ attribute \src "libresoc.v:120646.3-120658.6"
+ process $proc$libresoc.v:120646$4497
assign { } { }
assign { } { }
assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:120822.5-120822.29"
+ attribute \src "libresoc.v:120647.5-120647.29"
switch \initial
- attribute \src "libresoc.v:120822.9-120822.17"
+ attribute \src "libresoc.v:120647.9-120647.17"
case 1'1
case
end
sync always
update \dec62_inv_a $0\dec62_inv_a[0:0]
end
- attribute \src "libresoc.v:120834.3-120846.6"
- process $proc$libresoc.v:120834$4514
+ attribute \src "libresoc.v:120659.3-120671.6"
+ process $proc$libresoc.v:120659$4498
assign { } { }
assign { } { }
assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:120835.5-120835.29"
+ attribute \src "libresoc.v:120660.5-120660.29"
switch \initial
- attribute \src "libresoc.v:120835.9-120835.17"
+ attribute \src "libresoc.v:120660.9-120660.17"
case 1'1
case
end
sync always
update \dec62_inv_out $0\dec62_inv_out[0:0]
end
- attribute \src "libresoc.v:120847.3-120859.6"
- process $proc$libresoc.v:120847$4515
+ attribute \src "libresoc.v:120672.3-120684.6"
+ process $proc$libresoc.v:120672$4499
assign { } { }
assign { } { }
assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:120848.5-120848.29"
+ attribute \src "libresoc.v:120673.5-120673.29"
switch \initial
- attribute \src "libresoc.v:120848.9-120848.17"
+ attribute \src "libresoc.v:120673.9-120673.17"
case 1'1
case
end
sync always
update \dec62_cry_out $0\dec62_cry_out[0:0]
end
- attribute \src "libresoc.v:120860.3-120872.6"
- process $proc$libresoc.v:120860$4516
+ attribute \src "libresoc.v:120685.3-120697.6"
+ process $proc$libresoc.v:120685$4500
assign { } { }
assign { } { }
assign $0\dec62_br[0:0] $1\dec62_br[0:0]
- attribute \src "libresoc.v:120861.5-120861.29"
+ attribute \src "libresoc.v:120686.5-120686.29"
switch \initial
- attribute \src "libresoc.v:120861.9-120861.17"
+ attribute \src "libresoc.v:120686.9-120686.17"
case 1'1
case
end
sync always
update \dec62_br $0\dec62_br[0:0]
end
- attribute \src "libresoc.v:120873.3-120885.6"
- process $proc$libresoc.v:120873$4517
+ attribute \src "libresoc.v:120698.3-120710.6"
+ process $proc$libresoc.v:120698$4501
assign { } { }
assign { } { }
assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:120874.5-120874.29"
+ attribute \src "libresoc.v:120699.5-120699.29"
switch \initial
- attribute \src "libresoc.v:120874.9-120874.17"
+ attribute \src "libresoc.v:120699.9-120699.17"
case 1'1
case
end
sync always
update \dec62_sgn_ext $0\dec62_sgn_ext[0:0]
end
- attribute \src "libresoc.v:120886.3-120898.6"
- process $proc$libresoc.v:120886$4518
+ attribute \src "libresoc.v:120711.3-120723.6"
+ process $proc$libresoc.v:120711$4502
assign { } { }
assign { } { }
assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:120887.5-120887.29"
+ attribute \src "libresoc.v:120712.5-120712.29"
switch \initial
- attribute \src "libresoc.v:120887.9-120887.17"
+ attribute \src "libresoc.v:120712.9-120712.17"
case 1'1
case
end
sync always
update \dec62_rsrv $0\dec62_rsrv[0:0]
end
- attribute \src "libresoc.v:120899.3-120911.6"
- process $proc$libresoc.v:120899$4519
+ attribute \src "libresoc.v:120724.3-120736.6"
+ process $proc$libresoc.v:120724$4503
assign { } { }
assign { } { }
assign $0\dec62_form[4:0] $1\dec62_form[4:0]
- attribute \src "libresoc.v:120900.5-120900.29"
+ attribute \src "libresoc.v:120725.5-120725.29"
switch \initial
- attribute \src "libresoc.v:120900.9-120900.17"
+ attribute \src "libresoc.v:120725.9-120725.17"
case 1'1
case
end
sync always
update \dec62_form $0\dec62_form[4:0]
end
- attribute \src "libresoc.v:120912.3-120924.6"
- process $proc$libresoc.v:120912$4520
+ attribute \src "libresoc.v:120737.3-120749.6"
+ process $proc$libresoc.v:120737$4504
assign { } { }
assign { } { }
assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:120913.5-120913.29"
+ attribute \src "libresoc.v:120738.5-120738.29"
switch \initial
- attribute \src "libresoc.v:120913.9-120913.17"
+ attribute \src "libresoc.v:120738.9-120738.17"
case 1'1
case
end
sync always
update \dec62_is_32b $0\dec62_is_32b[0:0]
end
- attribute \src "libresoc.v:120925.3-120937.6"
- process $proc$libresoc.v:120925$4521
+ attribute \src "libresoc.v:120750.3-120762.6"
+ process $proc$libresoc.v:120750$4505
assign { } { }
assign { } { }
assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:120926.5-120926.29"
+ attribute \src "libresoc.v:120751.5-120751.29"
switch \initial
- attribute \src "libresoc.v:120926.9-120926.17"
+ attribute \src "libresoc.v:120751.9-120751.17"
case 1'1
case
end
sync always
update \dec62_sgn $0\dec62_sgn[0:0]
end
- attribute \src "libresoc.v:120938.3-120950.6"
- process $proc$libresoc.v:120938$4522
+ attribute \src "libresoc.v:120763.3-120775.6"
+ process $proc$libresoc.v:120763$4506
assign { } { }
assign { } { }
assign $0\dec62_lk[0:0] $1\dec62_lk[0:0]
- attribute \src "libresoc.v:120939.5-120939.29"
+ attribute \src "libresoc.v:120764.5-120764.29"
switch \initial
- attribute \src "libresoc.v:120939.9-120939.17"
+ attribute \src "libresoc.v:120764.9-120764.17"
case 1'1
case
end
sync always
update \dec62_lk $0\dec62_lk[0:0]
end
- attribute \src "libresoc.v:120951.3-120963.6"
- process $proc$libresoc.v:120951$4523
+ attribute \src "libresoc.v:120776.3-120788.6"
+ process $proc$libresoc.v:120776$4507
assign { } { }
assign { } { }
assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:120952.5-120952.29"
+ attribute \src "libresoc.v:120777.5-120777.29"
switch \initial
- attribute \src "libresoc.v:120952.9-120952.17"
+ attribute \src "libresoc.v:120777.9-120777.17"
case 1'1
case
end
sync always
update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:120964.3-120976.6"
- process $proc$libresoc.v:120964$4524
+ attribute \src "libresoc.v:120789.3-120801.6"
+ process $proc$libresoc.v:120789$4508
assign { } { }
assign { } { }
assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:120965.5-120965.29"
+ attribute \src "libresoc.v:120790.5-120790.29"
switch \initial
- attribute \src "libresoc.v:120965.9-120965.17"
+ attribute \src "libresoc.v:120790.9-120790.17"
case 1'1
case
end
sync always
update \dec62_SV_Etype $0\dec62_SV_Etype[1:0]
end
- attribute \src "libresoc.v:120977.3-120989.6"
- process $proc$libresoc.v:120977$4525
+ attribute \src "libresoc.v:120802.3-120814.6"
+ process $proc$libresoc.v:120802$4509
assign { } { }
assign { } { }
assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:120978.5-120978.29"
+ attribute \src "libresoc.v:120803.5-120803.29"
switch \initial
- attribute \src "libresoc.v:120978.9-120978.17"
+ attribute \src "libresoc.v:120803.9-120803.17"
case 1'1
case
end
sync always
update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:120990.3-121002.6"
- process $proc$libresoc.v:120990$4526
+ attribute \src "libresoc.v:120815.3-120827.6"
+ process $proc$libresoc.v:120815$4510
assign { } { }
assign { } { }
assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:120991.5-120991.29"
+ attribute \src "libresoc.v:120816.5-120816.29"
switch \initial
- attribute \src "libresoc.v:120991.9-120991.17"
+ attribute \src "libresoc.v:120816.9-120816.17"
case 1'1
case
end
sync always
update \dec62_in1_sel $0\dec62_in1_sel[2:0]
end
- attribute \src "libresoc.v:121003.3-121015.6"
- process $proc$libresoc.v:121003$4527
+ attribute \src "libresoc.v:120828.3-120840.6"
+ process $proc$libresoc.v:120828$4511
assign { } { }
assign { } { }
assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:121004.5-121004.29"
+ attribute \src "libresoc.v:120829.5-120829.29"
switch \initial
- attribute \src "libresoc.v:121004.9-121004.17"
+ attribute \src "libresoc.v:120829.9-120829.17"
case 1'1
case
end
sync always
update \dec62_in2_sel $0\dec62_in2_sel[3:0]
end
- attribute \src "libresoc.v:121016.3-121028.6"
- process $proc$libresoc.v:121016$4528
+ attribute \src "libresoc.v:120841.3-120853.6"
+ process $proc$libresoc.v:120841$4512
assign { } { }
assign { } { }
assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:121017.5-121017.29"
+ attribute \src "libresoc.v:120842.5-120842.29"
switch \initial
- attribute \src "libresoc.v:121017.9-121017.17"
+ attribute \src "libresoc.v:120842.9-120842.17"
case 1'1
case
end
sync always
update \dec62_in3_sel $0\dec62_in3_sel[1:0]
end
- attribute \src "libresoc.v:121029.3-121041.6"
- process $proc$libresoc.v:121029$4529
+ attribute \src "libresoc.v:120854.3-120866.6"
+ process $proc$libresoc.v:120854$4513
assign { } { }
assign { } { }
assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0]
- attribute \src "libresoc.v:121030.5-121030.29"
+ attribute \src "libresoc.v:120855.5-120855.29"
switch \initial
- attribute \src "libresoc.v:121030.9-121030.17"
+ attribute \src "libresoc.v:120855.9-120855.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:121047.1-121630.10"
+attribute \src "libresoc.v:120872.1-121455.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU"
attribute \generator "nMigen"
module \dec_ALU
- attribute \src "libresoc.v:121593.3-121607.6"
+ attribute \src "libresoc.v:121418.3-121432.6"
wire width 14 $0\ALU__fn_unit[13:0]
- attribute \src "libresoc.v:121580.3-121592.6"
+ attribute \src "libresoc.v:121405.3-121417.6"
wire width 7 $0\ALU__insn_type[6:0]
- attribute \src "libresoc.v:121565.3-121579.6"
+ attribute \src "libresoc.v:121390.3-121404.6"
wire $0\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:121048.7-121048.20"
+ attribute \src "libresoc.v:120873.7-120873.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:121593.3-121607.6"
+ attribute \src "libresoc.v:121418.3-121432.6"
wire width 14 $1\ALU__fn_unit[13:0]
- attribute \src "libresoc.v:121580.3-121592.6"
+ attribute \src "libresoc.v:121405.3-121417.6"
wire width 7 $1\ALU__insn_type[6:0]
- attribute \src "libresoc.v:121565.3-121579.6"
+ attribute \src "libresoc.v:121390.3-121404.6"
wire $1\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:121481.18-121481.113"
- wire $and$libresoc.v:121481$4531_Y
- attribute \src "libresoc.v:121483.18-121483.110"
- wire $and$libresoc.v:121483$4533_Y
- attribute \src "libresoc.v:121496.18-121496.114"
- wire $and$libresoc.v:121496$4546_Y
- attribute \src "libresoc.v:121497.18-121497.116"
- wire $and$libresoc.v:121497$4547_Y
- attribute \src "libresoc.v:121499.18-121499.114"
- wire $and$libresoc.v:121499$4549_Y
- attribute \src "libresoc.v:121501.18-121501.110"
- wire $and$libresoc.v:121501$4551_Y
- attribute \src "libresoc.v:121502.17-121502.112"
- wire $and$libresoc.v:121502$4552_Y
- attribute \src "libresoc.v:121503.17-121503.114"
- wire $and$libresoc.v:121503$4553_Y
- attribute \src "libresoc.v:121484.18-121484.126"
- wire $eq$libresoc.v:121484$4534_Y
- attribute \src "libresoc.v:121485.18-121485.126"
- wire $eq$libresoc.v:121485$4535_Y
- attribute \src "libresoc.v:121487.18-121487.110"
- wire $eq$libresoc.v:121487$4537_Y
- attribute \src "libresoc.v:121488.18-121488.110"
- wire $eq$libresoc.v:121488$4538_Y
- attribute \src "libresoc.v:121490.18-121490.112"
- wire $eq$libresoc.v:121490$4540_Y
- attribute \src "libresoc.v:121491.17-121491.130"
- wire $eq$libresoc.v:121491$4541_Y
- attribute \src "libresoc.v:121493.18-121493.110"
- wire $eq$libresoc.v:121493$4543_Y
- attribute \src "libresoc.v:121495.18-121495.131"
- wire $eq$libresoc.v:121495$4545_Y
- attribute \src "libresoc.v:121498.18-121498.131"
- wire $eq$libresoc.v:121498$4548_Y
- attribute \src "libresoc.v:121504.17-121504.130"
- wire $eq$libresoc.v:121504$4554_Y
- attribute \src "libresoc.v:121482.18-121482.110"
- wire $not$libresoc.v:121482$4532_Y
- attribute \src "libresoc.v:121500.18-121500.110"
- wire $not$libresoc.v:121500$4550_Y
- attribute \src "libresoc.v:121486.18-121486.110"
- wire $or$libresoc.v:121486$4536_Y
- attribute \src "libresoc.v:121489.18-121489.110"
- wire $or$libresoc.v:121489$4539_Y
- attribute \src "libresoc.v:121492.18-121492.110"
- wire $or$libresoc.v:121492$4542_Y
- attribute \src "libresoc.v:121494.18-121494.110"
- wire $or$libresoc.v:121494$4544_Y
+ attribute \src "libresoc.v:121306.18-121306.113"
+ wire $and$libresoc.v:121306$4515_Y
+ attribute \src "libresoc.v:121308.18-121308.110"
+ wire $and$libresoc.v:121308$4517_Y
+ attribute \src "libresoc.v:121321.18-121321.114"
+ wire $and$libresoc.v:121321$4530_Y
+ attribute \src "libresoc.v:121322.18-121322.116"
+ wire $and$libresoc.v:121322$4531_Y
+ attribute \src "libresoc.v:121324.18-121324.114"
+ wire $and$libresoc.v:121324$4533_Y
+ attribute \src "libresoc.v:121326.18-121326.110"
+ wire $and$libresoc.v:121326$4535_Y
+ attribute \src "libresoc.v:121327.17-121327.112"
+ wire $and$libresoc.v:121327$4536_Y
+ attribute \src "libresoc.v:121328.17-121328.114"
+ wire $and$libresoc.v:121328$4537_Y
+ attribute \src "libresoc.v:121309.18-121309.126"
+ wire $eq$libresoc.v:121309$4518_Y
+ attribute \src "libresoc.v:121310.18-121310.126"
+ wire $eq$libresoc.v:121310$4519_Y
+ attribute \src "libresoc.v:121312.18-121312.110"
+ wire $eq$libresoc.v:121312$4521_Y
+ attribute \src "libresoc.v:121313.18-121313.110"
+ wire $eq$libresoc.v:121313$4522_Y
+ attribute \src "libresoc.v:121315.18-121315.112"
+ wire $eq$libresoc.v:121315$4524_Y
+ attribute \src "libresoc.v:121316.17-121316.130"
+ wire $eq$libresoc.v:121316$4525_Y
+ attribute \src "libresoc.v:121318.18-121318.110"
+ wire $eq$libresoc.v:121318$4527_Y
+ attribute \src "libresoc.v:121320.18-121320.131"
+ wire $eq$libresoc.v:121320$4529_Y
+ attribute \src "libresoc.v:121323.18-121323.131"
+ wire $eq$libresoc.v:121323$4532_Y
+ attribute \src "libresoc.v:121329.17-121329.130"
+ wire $eq$libresoc.v:121329$4538_Y
+ attribute \src "libresoc.v:121307.18-121307.110"
+ wire $not$libresoc.v:121307$4516_Y
+ attribute \src "libresoc.v:121325.18-121325.110"
+ wire $not$libresoc.v:121325$4534_Y
+ attribute \src "libresoc.v:121311.18-121311.110"
+ wire $or$libresoc.v:121311$4520_Y
+ attribute \src "libresoc.v:121314.18-121314.110"
+ wire $or$libresoc.v:121314$4523_Y
+ attribute \src "libresoc.v:121317.18-121317.110"
+ wire $or$libresoc.v:121317$4526_Y
+ attribute \src "libresoc.v:121319.18-121319.110"
+ wire $or$libresoc.v:121319$4528_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:121048.7-121048.15"
+ attribute \src "libresoc.v:120873.7-120873.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
wire input 2 \sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121481$4531
+ cell $and $and$libresoc.v:121306$4515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:121481$4531_Y
+ connect \Y $and$libresoc.v:121306$4515_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121483$4533
+ cell $and $and$libresoc.v:121308$4517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:121483$4533_Y
+ connect \Y $and$libresoc.v:121308$4517_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:121496$4546
+ cell $and $and$libresoc.v:121321$4530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:121496$4546_Y
+ connect \Y $and$libresoc.v:121321$4530_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:121497$4547
+ cell $and $and$libresoc.v:121322$4531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121497$4547_Y
+ connect \Y $and$libresoc.v:121322$4531_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121499$4549
+ cell $and $and$libresoc.v:121324$4533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:121499$4549_Y
+ connect \Y $and$libresoc.v:121324$4533_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121501$4551
+ cell $and $and$libresoc.v:121326$4535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:121501$4551_Y
+ connect \Y $and$libresoc.v:121326$4535_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:121502$4552
+ cell $and $and$libresoc.v:121327$4536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:121502$4552_Y
+ connect \Y $and$libresoc.v:121327$4536_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:121503$4553
+ cell $and $and$libresoc.v:121328$4537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121503$4553_Y
+ connect \Y $and$libresoc.v:121328$4537_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:121484$4534
+ cell $eq $eq$libresoc.v:121309$4518
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:121484$4534_Y
+ connect \Y $eq$libresoc.v:121309$4518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:121485$4535
+ cell $eq $eq$libresoc.v:121310$4519
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:121485$4535_Y
+ connect \Y $eq$libresoc.v:121310$4519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:121487$4537
+ cell $eq $eq$libresoc.v:121312$4521
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:121487$4537_Y
+ connect \Y $eq$libresoc.v:121312$4521_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:121488$4538
+ cell $eq $eq$libresoc.v:121313$4522
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:121488$4538_Y
+ connect \Y $eq$libresoc.v:121313$4522_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:121490$4540
+ cell $eq $eq$libresoc.v:121315$4524
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:121490$4540_Y
+ connect \Y $eq$libresoc.v:121315$4524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:121491$4541
+ cell $eq $eq$libresoc.v:121316$4525
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:121491$4541_Y
+ connect \Y $eq$libresoc.v:121316$4525_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:121493$4543
+ cell $eq $eq$libresoc.v:121318$4527
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:121493$4543_Y
+ connect \Y $eq$libresoc.v:121318$4527_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:121495$4545
+ cell $eq $eq$libresoc.v:121320$4529
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:121495$4545_Y
+ connect \Y $eq$libresoc.v:121320$4529_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:121498$4548
+ cell $eq $eq$libresoc.v:121323$4532
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:121498$4548_Y
+ connect \Y $eq$libresoc.v:121323$4532_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:121504$4554
+ cell $eq $eq$libresoc.v:121329$4538
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:121504$4554_Y
+ connect \Y $eq$libresoc.v:121329$4538_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:121482$4532
+ cell $not $not$libresoc.v:121307$4516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121482$4532_Y
+ connect \Y $not$libresoc.v:121307$4516_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:121500$4550
+ cell $not $not$libresoc.v:121325$4534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121500$4550_Y
+ connect \Y $not$libresoc.v:121325$4534_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:121486$4536
+ cell $or $or$libresoc.v:121311$4520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:121486$4536_Y
+ connect \Y $or$libresoc.v:121311$4520_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:121489$4539
+ cell $or $or$libresoc.v:121314$4523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:121489$4539_Y
+ connect \Y $or$libresoc.v:121314$4523_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:121492$4542
+ cell $or $or$libresoc.v:121317$4526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:121492$4542_Y
+ connect \Y $or$libresoc.v:121317$4526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:121494$4544
+ cell $or $or$libresoc.v:121319$4528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:121494$4544_Y
+ connect \Y $or$libresoc.v:121319$4528_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121505.7-121533.4"
+ attribute \src "libresoc.v:121330.7-121358.4"
cell \dec \dec
connect \ALU_BD \dec_ALU_BD
connect \ALU_DS \dec_ALU_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121534.10-121539.4"
+ attribute \src "libresoc.v:121359.10-121364.4"
cell \dec_ai \dec_ai
connect \ALU_RA \dec_ALU_RA
connect \immz_out \dec_ai_immz_out
connect \sv_nz \dec_ai_sv_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121540.10-121551.4"
+ attribute \src "libresoc.v:121365.10-121376.4"
cell \dec_bi \dec_bi
connect \ALU_BD \dec_ALU_BD
connect \ALU_DS \dec_ALU_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121552.10-121558.4"
+ attribute \src "libresoc.v:121377.10-121383.4"
cell \dec_oe \dec_oe
connect \ALU_OE \dec_ALU_OE
connect \ALU_internal_op \dec_ALU_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121559.10-121564.4"
+ attribute \src "libresoc.v:121384.10-121389.4"
cell \dec_rc \dec_rc
connect \ALU_Rc \dec_ALU_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:121048.7-121048.20"
- process $proc$libresoc.v:121048$4558
+ attribute \src "libresoc.v:120873.7-120873.20"
+ process $proc$libresoc.v:120873$4542
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:121565.3-121579.6"
- process $proc$libresoc.v:121565$4555
+ attribute \src "libresoc.v:121390.3-121404.6"
+ process $proc$libresoc.v:121390$4539
assign { } { }
assign { } { }
assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:121566.5-121566.29"
+ attribute \src "libresoc.v:121391.5-121391.29"
switch \initial
- attribute \src "libresoc.v:121566.9-121566.17"
+ attribute \src "libresoc.v:121391.9-121391.17"
case 1'1
case
end
sync always
update \ALU__write_cr0 $0\ALU__write_cr0[0:0]
end
- attribute \src "libresoc.v:121580.3-121592.6"
- process $proc$libresoc.v:121580$4556
+ attribute \src "libresoc.v:121405.3-121417.6"
+ process $proc$libresoc.v:121405$4540
assign { } { }
assign { } { }
assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0]
- attribute \src "libresoc.v:121581.5-121581.29"
+ attribute \src "libresoc.v:121406.5-121406.29"
switch \initial
- attribute \src "libresoc.v:121581.9-121581.17"
+ attribute \src "libresoc.v:121406.9-121406.17"
case 1'1
case
end
sync always
update \ALU__insn_type $0\ALU__insn_type[6:0]
end
- attribute \src "libresoc.v:121593.3-121607.6"
- process $proc$libresoc.v:121593$4557
+ attribute \src "libresoc.v:121418.3-121432.6"
+ process $proc$libresoc.v:121418$4541
assign { } { }
assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0]
- attribute \src "libresoc.v:121594.5-121594.29"
+ attribute \src "libresoc.v:121419.5-121419.29"
switch \initial
- attribute \src "libresoc.v:121594.9-121594.17"
+ attribute \src "libresoc.v:121419.9-121419.17"
case 1'1
case
end
sync always
update \ALU__fn_unit $0\ALU__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:121481$4531_Y
- connect \$12 $not$libresoc.v:121482$4532_Y
- connect \$14 $and$libresoc.v:121483$4533_Y
- connect \$16 $eq$libresoc.v:121484$4534_Y
- connect \$18 $eq$libresoc.v:121485$4535_Y
- connect \$20 $or$libresoc.v:121486$4536_Y
- connect \$22 $eq$libresoc.v:121487$4537_Y
- connect \$24 $eq$libresoc.v:121488$4538_Y
- connect \$26 $or$libresoc.v:121489$4539_Y
- connect \$28 $eq$libresoc.v:121490$4540_Y
- connect \$2 $eq$libresoc.v:121491$4541_Y
- connect \$30 $or$libresoc.v:121492$4542_Y
- connect \$32 $eq$libresoc.v:121493$4543_Y
- connect \$34 $or$libresoc.v:121494$4544_Y
- connect \$36 $eq$libresoc.v:121495$4545_Y
- connect \$38 $and$libresoc.v:121496$4546_Y
- connect \$40 $and$libresoc.v:121497$4547_Y
- connect \$42 $eq$libresoc.v:121498$4548_Y
- connect \$44 $and$libresoc.v:121499$4549_Y
- connect \$46 $not$libresoc.v:121500$4550_Y
- connect \$48 $and$libresoc.v:121501$4551_Y
- connect \$4 $and$libresoc.v:121502$4552_Y
- connect \$6 $and$libresoc.v:121503$4553_Y
- connect \$8 $eq$libresoc.v:121504$4554_Y
+ connect \$10 $and$libresoc.v:121306$4515_Y
+ connect \$12 $not$libresoc.v:121307$4516_Y
+ connect \$14 $and$libresoc.v:121308$4517_Y
+ connect \$16 $eq$libresoc.v:121309$4518_Y
+ connect \$18 $eq$libresoc.v:121310$4519_Y
+ connect \$20 $or$libresoc.v:121311$4520_Y
+ connect \$22 $eq$libresoc.v:121312$4521_Y
+ connect \$24 $eq$libresoc.v:121313$4522_Y
+ connect \$26 $or$libresoc.v:121314$4523_Y
+ connect \$28 $eq$libresoc.v:121315$4524_Y
+ connect \$2 $eq$libresoc.v:121316$4525_Y
+ connect \$30 $or$libresoc.v:121317$4526_Y
+ connect \$32 $eq$libresoc.v:121318$4527_Y
+ connect \$34 $or$libresoc.v:121319$4528_Y
+ connect \$36 $eq$libresoc.v:121320$4529_Y
+ connect \$38 $and$libresoc.v:121321$4530_Y
+ connect \$40 $and$libresoc.v:121322$4531_Y
+ connect \$42 $eq$libresoc.v:121323$4532_Y
+ connect \$44 $and$libresoc.v:121324$4533_Y
+ connect \$46 $not$libresoc.v:121325$4534_Y
+ connect \$48 $and$libresoc.v:121326$4535_Y
+ connect \$4 $and$libresoc.v:121327$4536_Y
+ connect \$6 $and$libresoc.v:121328$4537_Y
+ connect \$8 $eq$libresoc.v:121329$4538_Y
connect \ALU__is_signed \dec_ALU_sgn
connect \ALU__is_32bit \dec_ALU_is_32b
connect \ALU__output_carry \dec_ALU_cry_out
connect \insn_in \dec_opcode_in
connect \ALU__insn \dec_opcode_in
end
-attribute \src "libresoc.v:121634.1-122114.10"
+attribute \src "libresoc.v:121459.1-121939.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH"
attribute \generator "nMigen"
module \dec_BRANCH
- attribute \src "libresoc.v:122064.3-122078.6"
+ attribute \src "libresoc.v:121889.3-121903.6"
wire width 14 $0\BRANCH__fn_unit[13:0]
- attribute \src "libresoc.v:122089.3-122101.6"
+ attribute \src "libresoc.v:121914.3-121926.6"
wire width 7 $0\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:122079.3-122088.6"
+ attribute \src "libresoc.v:121904.3-121913.6"
wire $0\BRANCH__lk[0:0]
- attribute \src "libresoc.v:121635.7-121635.20"
+ attribute \src "libresoc.v:121460.7-121460.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:122064.3-122078.6"
+ attribute \src "libresoc.v:121889.3-121903.6"
wire width 14 $1\BRANCH__fn_unit[13:0]
- attribute \src "libresoc.v:122089.3-122101.6"
+ attribute \src "libresoc.v:121914.3-121926.6"
wire width 7 $1\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:122079.3-122088.6"
+ attribute \src "libresoc.v:121904.3-121913.6"
wire $1\BRANCH__lk[0:0]
- attribute \src "libresoc.v:121996.18-121996.113"
- wire $and$libresoc.v:121996$4559_Y
- attribute \src "libresoc.v:121998.18-121998.110"
- wire $and$libresoc.v:121998$4561_Y
- attribute \src "libresoc.v:122011.18-122011.114"
- wire $and$libresoc.v:122011$4574_Y
- attribute \src "libresoc.v:122012.18-122012.116"
- wire $and$libresoc.v:122012$4575_Y
- attribute \src "libresoc.v:122014.18-122014.114"
- wire $and$libresoc.v:122014$4577_Y
- attribute \src "libresoc.v:122016.18-122016.110"
- wire $and$libresoc.v:122016$4579_Y
- attribute \src "libresoc.v:122017.17-122017.112"
- wire $and$libresoc.v:122017$4580_Y
- attribute \src "libresoc.v:122018.17-122018.114"
- wire $and$libresoc.v:122018$4581_Y
- attribute \src "libresoc.v:121999.18-121999.129"
- wire $eq$libresoc.v:121999$4562_Y
- attribute \src "libresoc.v:122000.18-122000.129"
- wire $eq$libresoc.v:122000$4563_Y
- attribute \src "libresoc.v:122002.18-122002.110"
- wire $eq$libresoc.v:122002$4565_Y
- attribute \src "libresoc.v:122003.18-122003.110"
- wire $eq$libresoc.v:122003$4566_Y
- attribute \src "libresoc.v:122005.18-122005.112"
- wire $eq$libresoc.v:122005$4568_Y
- attribute \src "libresoc.v:122006.17-122006.133"
- wire $eq$libresoc.v:122006$4569_Y
- attribute \src "libresoc.v:122008.18-122008.110"
- wire $eq$libresoc.v:122008$4571_Y
- attribute \src "libresoc.v:122010.18-122010.134"
- wire $eq$libresoc.v:122010$4573_Y
- attribute \src "libresoc.v:122013.18-122013.134"
- wire $eq$libresoc.v:122013$4576_Y
- attribute \src "libresoc.v:122019.17-122019.133"
- wire $eq$libresoc.v:122019$4582_Y
- attribute \src "libresoc.v:121997.18-121997.110"
- wire $not$libresoc.v:121997$4560_Y
- attribute \src "libresoc.v:122015.18-122015.110"
- wire $not$libresoc.v:122015$4578_Y
- attribute \src "libresoc.v:122001.18-122001.110"
- wire $or$libresoc.v:122001$4564_Y
- attribute \src "libresoc.v:122004.18-122004.110"
- wire $or$libresoc.v:122004$4567_Y
- attribute \src "libresoc.v:122007.18-122007.110"
- wire $or$libresoc.v:122007$4570_Y
- attribute \src "libresoc.v:122009.18-122009.110"
- wire $or$libresoc.v:122009$4572_Y
+ attribute \src "libresoc.v:121821.18-121821.113"
+ wire $and$libresoc.v:121821$4543_Y
+ attribute \src "libresoc.v:121823.18-121823.110"
+ wire $and$libresoc.v:121823$4545_Y
+ attribute \src "libresoc.v:121836.18-121836.114"
+ wire $and$libresoc.v:121836$4558_Y
+ attribute \src "libresoc.v:121837.18-121837.116"
+ wire $and$libresoc.v:121837$4559_Y
+ attribute \src "libresoc.v:121839.18-121839.114"
+ wire $and$libresoc.v:121839$4561_Y
+ attribute \src "libresoc.v:121841.18-121841.110"
+ wire $and$libresoc.v:121841$4563_Y
+ attribute \src "libresoc.v:121842.17-121842.112"
+ wire $and$libresoc.v:121842$4564_Y
+ attribute \src "libresoc.v:121843.17-121843.114"
+ wire $and$libresoc.v:121843$4565_Y
+ attribute \src "libresoc.v:121824.18-121824.129"
+ wire $eq$libresoc.v:121824$4546_Y
+ attribute \src "libresoc.v:121825.18-121825.129"
+ wire $eq$libresoc.v:121825$4547_Y
+ attribute \src "libresoc.v:121827.18-121827.110"
+ wire $eq$libresoc.v:121827$4549_Y
+ attribute \src "libresoc.v:121828.18-121828.110"
+ wire $eq$libresoc.v:121828$4550_Y
+ attribute \src "libresoc.v:121830.18-121830.112"
+ wire $eq$libresoc.v:121830$4552_Y
+ attribute \src "libresoc.v:121831.17-121831.133"
+ wire $eq$libresoc.v:121831$4553_Y
+ attribute \src "libresoc.v:121833.18-121833.110"
+ wire $eq$libresoc.v:121833$4555_Y
+ attribute \src "libresoc.v:121835.18-121835.134"
+ wire $eq$libresoc.v:121835$4557_Y
+ attribute \src "libresoc.v:121838.18-121838.134"
+ wire $eq$libresoc.v:121838$4560_Y
+ attribute \src "libresoc.v:121844.17-121844.133"
+ wire $eq$libresoc.v:121844$4566_Y
+ attribute \src "libresoc.v:121822.18-121822.110"
+ wire $not$libresoc.v:121822$4544_Y
+ attribute \src "libresoc.v:121840.18-121840.110"
+ wire $not$libresoc.v:121840$4562_Y
+ attribute \src "libresoc.v:121826.18-121826.110"
+ wire $or$libresoc.v:121826$4548_Y
+ attribute \src "libresoc.v:121829.18-121829.110"
+ wire $or$libresoc.v:121829$4551_Y
+ attribute \src "libresoc.v:121832.18-121832.110"
+ wire $or$libresoc.v:121832$4554_Y
+ attribute \src "libresoc.v:121834.18-121834.110"
+ wire $or$libresoc.v:121834$4556_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:121635.7-121635.15"
+ attribute \src "libresoc.v:121460.7-121460.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121996$4559
+ cell $and $and$libresoc.v:121821$4543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:121996$4559_Y
+ connect \Y $and$libresoc.v:121821$4543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:121998$4561
+ cell $and $and$libresoc.v:121823$4545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:121998$4561_Y
+ connect \Y $and$libresoc.v:121823$4545_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122011$4574
+ cell $and $and$libresoc.v:121836$4558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:122011$4574_Y
+ connect \Y $and$libresoc.v:121836$4558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122012$4575
+ cell $and $and$libresoc.v:121837$4559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122012$4575_Y
+ connect \Y $and$libresoc.v:121837$4559_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122014$4577
+ cell $and $and$libresoc.v:121839$4561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:122014$4577_Y
+ connect \Y $and$libresoc.v:121839$4561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122016$4579
+ cell $and $and$libresoc.v:121841$4563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:122016$4579_Y
+ connect \Y $and$libresoc.v:121841$4563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122017$4580
+ cell $and $and$libresoc.v:121842$4564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:122017$4580_Y
+ connect \Y $and$libresoc.v:121842$4564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122018$4581
+ cell $and $and$libresoc.v:121843$4565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122018$4581_Y
+ connect \Y $and$libresoc.v:121843$4565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:121999$4562
+ cell $eq $eq$libresoc.v:121824$4546
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:121999$4562_Y
+ connect \Y $eq$libresoc.v:121824$4546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:122000$4563
+ cell $eq $eq$libresoc.v:121825$4547
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:122000$4563_Y
+ connect \Y $eq$libresoc.v:121825$4547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122002$4565
+ cell $eq $eq$libresoc.v:121827$4549
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:122002$4565_Y
+ connect \Y $eq$libresoc.v:121827$4549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122003$4566
+ cell $eq $eq$libresoc.v:121828$4550
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:122003$4566_Y
+ connect \Y $eq$libresoc.v:121828$4550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122005$4568
+ cell $eq $eq$libresoc.v:121830$4552
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:122005$4568_Y
+ connect \Y $eq$libresoc.v:121830$4552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122006$4569
+ cell $eq $eq$libresoc.v:121831$4553
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122006$4569_Y
+ connect \Y $eq$libresoc.v:121831$4553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:122008$4571
+ cell $eq $eq$libresoc.v:121833$4555
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:122008$4571_Y
+ connect \Y $eq$libresoc.v:121833$4555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122010$4573
+ cell $eq $eq$libresoc.v:121835$4557
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122010$4573_Y
+ connect \Y $eq$libresoc.v:121835$4557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122013$4576
+ cell $eq $eq$libresoc.v:121838$4560
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122013$4576_Y
+ connect \Y $eq$libresoc.v:121838$4560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122019$4582
+ cell $eq $eq$libresoc.v:121844$4566
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122019$4582_Y
+ connect \Y $eq$libresoc.v:121844$4566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:121997$4560
+ cell $not $not$libresoc.v:121822$4544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121997$4560_Y
+ connect \Y $not$libresoc.v:121822$4544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:122015$4578
+ cell $not $not$libresoc.v:121840$4562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122015$4578_Y
+ connect \Y $not$libresoc.v:121840$4562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:122001$4564
+ cell $or $or$libresoc.v:121826$4548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:122001$4564_Y
+ connect \Y $or$libresoc.v:121826$4548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122004$4567
+ cell $or $or$libresoc.v:121829$4551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:122004$4567_Y
+ connect \Y $or$libresoc.v:121829$4551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122007$4570
+ cell $or $or$libresoc.v:121832$4554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:122007$4570_Y
+ connect \Y $or$libresoc.v:121832$4554_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:122009$4572
+ cell $or $or$libresoc.v:121834$4556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:122009$4572_Y
+ connect \Y $or$libresoc.v:121834$4556_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122020.13-122042.4"
+ attribute \src "libresoc.v:121845.13-121867.4"
cell \dec$141 \dec
connect \BRANCH_BD \dec_BRANCH_BD
connect \BRANCH_DS \dec_BRANCH_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122043.16-122054.4"
+ attribute \src "libresoc.v:121868.16-121879.4"
cell \dec_bi$144 \dec_bi
connect \BRANCH_BD \dec_BRANCH_BD
connect \BRANCH_DS \dec_BRANCH_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122055.16-122059.4"
+ attribute \src "libresoc.v:121880.16-121884.4"
cell \dec_oe$143 \dec_oe
connect \BRANCH_OE \dec_BRANCH_OE
connect \BRANCH_internal_op \dec_BRANCH_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122060.16-122063.4"
+ attribute \src "libresoc.v:121885.16-121888.4"
cell \dec_rc$142 \dec_rc
connect \BRANCH_Rc \dec_BRANCH_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:121635.7-121635.20"
- process $proc$libresoc.v:121635$4586
+ attribute \src "libresoc.v:121460.7-121460.20"
+ process $proc$libresoc.v:121460$4570
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:122064.3-122078.6"
- process $proc$libresoc.v:122064$4583
+ attribute \src "libresoc.v:121889.3-121903.6"
+ process $proc$libresoc.v:121889$4567
assign { } { }
assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0]
- attribute \src "libresoc.v:122065.5-122065.29"
+ attribute \src "libresoc.v:121890.5-121890.29"
switch \initial
- attribute \src "libresoc.v:122065.9-122065.17"
+ attribute \src "libresoc.v:121890.9-121890.17"
case 1'1
case
end
sync always
update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0]
end
- attribute \src "libresoc.v:122079.3-122088.6"
- process $proc$libresoc.v:122079$4584
+ attribute \src "libresoc.v:121904.3-121913.6"
+ process $proc$libresoc.v:121904$4568
assign { } { }
assign { } { }
assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0]
- attribute \src "libresoc.v:122080.5-122080.29"
+ attribute \src "libresoc.v:121905.5-121905.29"
switch \initial
- attribute \src "libresoc.v:122080.9-122080.17"
+ attribute \src "libresoc.v:121905.9-121905.17"
case 1'1
case
end
sync always
update \BRANCH__lk $0\BRANCH__lk[0:0]
end
- attribute \src "libresoc.v:122089.3-122101.6"
- process $proc$libresoc.v:122089$4585
+ attribute \src "libresoc.v:121914.3-121926.6"
+ process $proc$libresoc.v:121914$4569
assign { } { }
assign { } { }
assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:122090.5-122090.29"
+ attribute \src "libresoc.v:121915.5-121915.29"
switch \initial
- attribute \src "libresoc.v:122090.9-122090.17"
+ attribute \src "libresoc.v:121915.9-121915.17"
case 1'1
case
end
sync always
update \BRANCH__insn_type $0\BRANCH__insn_type[6:0]
end
- connect \$10 $and$libresoc.v:121996$4559_Y
- connect \$12 $not$libresoc.v:121997$4560_Y
- connect \$14 $and$libresoc.v:121998$4561_Y
- connect \$16 $eq$libresoc.v:121999$4562_Y
- connect \$18 $eq$libresoc.v:122000$4563_Y
- connect \$20 $or$libresoc.v:122001$4564_Y
- connect \$22 $eq$libresoc.v:122002$4565_Y
- connect \$24 $eq$libresoc.v:122003$4566_Y
- connect \$26 $or$libresoc.v:122004$4567_Y
- connect \$28 $eq$libresoc.v:122005$4568_Y
- connect \$2 $eq$libresoc.v:122006$4569_Y
- connect \$30 $or$libresoc.v:122007$4570_Y
- connect \$32 $eq$libresoc.v:122008$4571_Y
- connect \$34 $or$libresoc.v:122009$4572_Y
- connect \$36 $eq$libresoc.v:122010$4573_Y
- connect \$38 $and$libresoc.v:122011$4574_Y
- connect \$40 $and$libresoc.v:122012$4575_Y
- connect \$42 $eq$libresoc.v:122013$4576_Y
- connect \$44 $and$libresoc.v:122014$4577_Y
- connect \$46 $not$libresoc.v:122015$4578_Y
- connect \$48 $and$libresoc.v:122016$4579_Y
- connect \$4 $and$libresoc.v:122017$4580_Y
- connect \$6 $and$libresoc.v:122018$4581_Y
- connect \$8 $eq$libresoc.v:122019$4582_Y
+ connect \$10 $and$libresoc.v:121821$4543_Y
+ connect \$12 $not$libresoc.v:121822$4544_Y
+ connect \$14 $and$libresoc.v:121823$4545_Y
+ connect \$16 $eq$libresoc.v:121824$4546_Y
+ connect \$18 $eq$libresoc.v:121825$4547_Y
+ connect \$20 $or$libresoc.v:121826$4548_Y
+ connect \$22 $eq$libresoc.v:121827$4549_Y
+ connect \$24 $eq$libresoc.v:121828$4550_Y
+ connect \$26 $or$libresoc.v:121829$4551_Y
+ connect \$28 $eq$libresoc.v:121830$4552_Y
+ connect \$2 $eq$libresoc.v:121831$4553_Y
+ connect \$30 $or$libresoc.v:121832$4554_Y
+ connect \$32 $eq$libresoc.v:121833$4555_Y
+ connect \$34 $or$libresoc.v:121834$4556_Y
+ connect \$36 $eq$libresoc.v:121835$4557_Y
+ connect \$38 $and$libresoc.v:121836$4558_Y
+ connect \$40 $and$libresoc.v:121837$4559_Y
+ connect \$42 $eq$libresoc.v:121838$4560_Y
+ connect \$44 $and$libresoc.v:121839$4561_Y
+ connect \$46 $not$libresoc.v:121840$4562_Y
+ connect \$48 $and$libresoc.v:121841$4563_Y
+ connect \$4 $and$libresoc.v:121842$4564_Y
+ connect \$6 $and$libresoc.v:121843$4565_Y
+ connect \$8 $eq$libresoc.v:121844$4566_Y
connect \BRANCH__is_32bit \dec_BRANCH_is_32b
connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b }
connect \dec_bi_sel_in \dec_BRANCH_in2_sel
connect \insn_in \dec_opcode_in
connect \BRANCH__insn \dec_opcode_in
end
-attribute \src "libresoc.v:122118.1-122490.10"
+attribute \src "libresoc.v:121943.1-122315.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR"
attribute \generator "nMigen"
module \dec_CR
- attribute \src "libresoc.v:122467.3-122481.6"
+ attribute \src "libresoc.v:122292.3-122306.6"
wire width 14 $0\CR__fn_unit[13:0]
- attribute \src "libresoc.v:122454.3-122466.6"
+ attribute \src "libresoc.v:122279.3-122291.6"
wire width 7 $0\CR__insn_type[6:0]
- attribute \src "libresoc.v:122119.7-122119.20"
+ attribute \src "libresoc.v:121944.7-121944.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:122467.3-122481.6"
+ attribute \src "libresoc.v:122292.3-122306.6"
wire width 14 $1\CR__fn_unit[13:0]
- attribute \src "libresoc.v:122454.3-122466.6"
+ attribute \src "libresoc.v:122279.3-122291.6"
wire width 7 $1\CR__insn_type[6:0]
- attribute \src "libresoc.v:122409.18-122409.113"
- wire $and$libresoc.v:122409$4587_Y
- attribute \src "libresoc.v:122411.18-122411.110"
- wire $and$libresoc.v:122411$4589_Y
- attribute \src "libresoc.v:122424.18-122424.114"
- wire $and$libresoc.v:122424$4602_Y
- attribute \src "libresoc.v:122425.18-122425.116"
- wire $and$libresoc.v:122425$4603_Y
- attribute \src "libresoc.v:122427.18-122427.114"
- wire $and$libresoc.v:122427$4605_Y
- attribute \src "libresoc.v:122429.18-122429.110"
- wire $and$libresoc.v:122429$4607_Y
- attribute \src "libresoc.v:122430.17-122430.112"
- wire $and$libresoc.v:122430$4608_Y
- attribute \src "libresoc.v:122431.17-122431.114"
- wire $and$libresoc.v:122431$4609_Y
- attribute \src "libresoc.v:122412.18-122412.125"
- wire $eq$libresoc.v:122412$4590_Y
- attribute \src "libresoc.v:122413.18-122413.125"
- wire $eq$libresoc.v:122413$4591_Y
- attribute \src "libresoc.v:122415.18-122415.110"
- wire $eq$libresoc.v:122415$4593_Y
- attribute \src "libresoc.v:122416.18-122416.110"
- wire $eq$libresoc.v:122416$4594_Y
- attribute \src "libresoc.v:122418.18-122418.112"
- wire $eq$libresoc.v:122418$4596_Y
- attribute \src "libresoc.v:122419.17-122419.129"
- wire $eq$libresoc.v:122419$4597_Y
- attribute \src "libresoc.v:122421.18-122421.110"
- wire $eq$libresoc.v:122421$4599_Y
- attribute \src "libresoc.v:122423.18-122423.130"
- wire $eq$libresoc.v:122423$4601_Y
- attribute \src "libresoc.v:122426.18-122426.130"
- wire $eq$libresoc.v:122426$4604_Y
- attribute \src "libresoc.v:122432.17-122432.129"
- wire $eq$libresoc.v:122432$4610_Y
- attribute \src "libresoc.v:122410.18-122410.110"
- wire $not$libresoc.v:122410$4588_Y
- attribute \src "libresoc.v:122428.18-122428.110"
- wire $not$libresoc.v:122428$4606_Y
- attribute \src "libresoc.v:122414.18-122414.110"
- wire $or$libresoc.v:122414$4592_Y
- attribute \src "libresoc.v:122417.18-122417.110"
- wire $or$libresoc.v:122417$4595_Y
- attribute \src "libresoc.v:122420.18-122420.110"
- wire $or$libresoc.v:122420$4598_Y
- attribute \src "libresoc.v:122422.18-122422.110"
- wire $or$libresoc.v:122422$4600_Y
+ attribute \src "libresoc.v:122234.18-122234.113"
+ wire $and$libresoc.v:122234$4571_Y
+ attribute \src "libresoc.v:122236.18-122236.110"
+ wire $and$libresoc.v:122236$4573_Y
+ attribute \src "libresoc.v:122249.18-122249.114"
+ wire $and$libresoc.v:122249$4586_Y
+ attribute \src "libresoc.v:122250.18-122250.116"
+ wire $and$libresoc.v:122250$4587_Y
+ attribute \src "libresoc.v:122252.18-122252.114"
+ wire $and$libresoc.v:122252$4589_Y
+ attribute \src "libresoc.v:122254.18-122254.110"
+ wire $and$libresoc.v:122254$4591_Y
+ attribute \src "libresoc.v:122255.17-122255.112"
+ wire $and$libresoc.v:122255$4592_Y
+ attribute \src "libresoc.v:122256.17-122256.114"
+ wire $and$libresoc.v:122256$4593_Y
+ attribute \src "libresoc.v:122237.18-122237.125"
+ wire $eq$libresoc.v:122237$4574_Y
+ attribute \src "libresoc.v:122238.18-122238.125"
+ wire $eq$libresoc.v:122238$4575_Y
+ attribute \src "libresoc.v:122240.18-122240.110"
+ wire $eq$libresoc.v:122240$4577_Y
+ attribute \src "libresoc.v:122241.18-122241.110"
+ wire $eq$libresoc.v:122241$4578_Y
+ attribute \src "libresoc.v:122243.18-122243.112"
+ wire $eq$libresoc.v:122243$4580_Y
+ attribute \src "libresoc.v:122244.17-122244.129"
+ wire $eq$libresoc.v:122244$4581_Y
+ attribute \src "libresoc.v:122246.18-122246.110"
+ wire $eq$libresoc.v:122246$4583_Y
+ attribute \src "libresoc.v:122248.18-122248.130"
+ wire $eq$libresoc.v:122248$4585_Y
+ attribute \src "libresoc.v:122251.18-122251.130"
+ wire $eq$libresoc.v:122251$4588_Y
+ attribute \src "libresoc.v:122257.17-122257.129"
+ wire $eq$libresoc.v:122257$4594_Y
+ attribute \src "libresoc.v:122235.18-122235.110"
+ wire $not$libresoc.v:122235$4572_Y
+ attribute \src "libresoc.v:122253.18-122253.110"
+ wire $not$libresoc.v:122253$4590_Y
+ attribute \src "libresoc.v:122239.18-122239.110"
+ wire $or$libresoc.v:122239$4576_Y
+ attribute \src "libresoc.v:122242.18-122242.110"
+ wire $or$libresoc.v:122242$4579_Y
+ attribute \src "libresoc.v:122245.18-122245.110"
+ wire $or$libresoc.v:122245$4582_Y
+ attribute \src "libresoc.v:122247.18-122247.110"
+ wire $or$libresoc.v:122247$4584_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:122119.7-122119.15"
+ attribute \src "libresoc.v:121944.7-121944.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122409$4587
+ cell $and $and$libresoc.v:122234$4571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:122409$4587_Y
+ connect \Y $and$libresoc.v:122234$4571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122411$4589
+ cell $and $and$libresoc.v:122236$4573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:122411$4589_Y
+ connect \Y $and$libresoc.v:122236$4573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122424$4602
+ cell $and $and$libresoc.v:122249$4586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:122424$4602_Y
+ connect \Y $and$libresoc.v:122249$4586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122425$4603
+ cell $and $and$libresoc.v:122250$4587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122425$4603_Y
+ connect \Y $and$libresoc.v:122250$4587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122427$4605
+ cell $and $and$libresoc.v:122252$4589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:122427$4605_Y
+ connect \Y $and$libresoc.v:122252$4589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122429$4607
+ cell $and $and$libresoc.v:122254$4591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:122429$4607_Y
+ connect \Y $and$libresoc.v:122254$4591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122430$4608
+ cell $and $and$libresoc.v:122255$4592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:122430$4608_Y
+ connect \Y $and$libresoc.v:122255$4592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122431$4609
+ cell $and $and$libresoc.v:122256$4593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122431$4609_Y
+ connect \Y $and$libresoc.v:122256$4593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:122412$4590
+ cell $eq $eq$libresoc.v:122237$4574
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:122412$4590_Y
+ connect \Y $eq$libresoc.v:122237$4574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:122413$4591
+ cell $eq $eq$libresoc.v:122238$4575
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:122413$4591_Y
+ connect \Y $eq$libresoc.v:122238$4575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122415$4593
+ cell $eq $eq$libresoc.v:122240$4577
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:122415$4593_Y
+ connect \Y $eq$libresoc.v:122240$4577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122416$4594
+ cell $eq $eq$libresoc.v:122241$4578
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:122416$4594_Y
+ connect \Y $eq$libresoc.v:122241$4578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122418$4596
+ cell $eq $eq$libresoc.v:122243$4580
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:122418$4596_Y
+ connect \Y $eq$libresoc.v:122243$4580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122419$4597
+ cell $eq $eq$libresoc.v:122244$4581
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122419$4597_Y
+ connect \Y $eq$libresoc.v:122244$4581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:122421$4599
+ cell $eq $eq$libresoc.v:122246$4583
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:122421$4599_Y
+ connect \Y $eq$libresoc.v:122246$4583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122423$4601
+ cell $eq $eq$libresoc.v:122248$4585
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122423$4601_Y
+ connect \Y $eq$libresoc.v:122248$4585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122426$4604
+ cell $eq $eq$libresoc.v:122251$4588
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122426$4604_Y
+ connect \Y $eq$libresoc.v:122251$4588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122432$4610
+ cell $eq $eq$libresoc.v:122257$4594
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122432$4610_Y
+ connect \Y $eq$libresoc.v:122257$4594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:122410$4588
+ cell $not $not$libresoc.v:122235$4572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122410$4588_Y
+ connect \Y $not$libresoc.v:122235$4572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:122428$4606
+ cell $not $not$libresoc.v:122253$4590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122428$4606_Y
+ connect \Y $not$libresoc.v:122253$4590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:122414$4592
+ cell $or $or$libresoc.v:122239$4576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:122414$4592_Y
+ connect \Y $or$libresoc.v:122239$4576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122417$4595
+ cell $or $or$libresoc.v:122242$4579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:122417$4595_Y
+ connect \Y $or$libresoc.v:122242$4579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122420$4598
+ cell $or $or$libresoc.v:122245$4582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:122420$4598_Y
+ connect \Y $or$libresoc.v:122245$4582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:122422$4600
+ cell $or $or$libresoc.v:122247$4584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:122422$4600_Y
+ connect \Y $or$libresoc.v:122247$4584_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122433.13-122444.4"
+ attribute \src "libresoc.v:122258.13-122269.4"
cell \dec$138 \dec
connect \CR_OE \dec_CR_OE
connect \CR_Rc \dec_CR_Rc
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122445.16-122449.4"
+ attribute \src "libresoc.v:122270.16-122274.4"
cell \dec_oe$140 \dec_oe
connect \CR_OE \dec_CR_OE
connect \CR_internal_op \dec_CR_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122450.16-122453.4"
+ attribute \src "libresoc.v:122275.16-122278.4"
cell \dec_rc$139 \dec_rc
connect \CR_Rc \dec_CR_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:122119.7-122119.20"
- process $proc$libresoc.v:122119$4613
+ attribute \src "libresoc.v:121944.7-121944.20"
+ process $proc$libresoc.v:121944$4597
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:122454.3-122466.6"
- process $proc$libresoc.v:122454$4611
+ attribute \src "libresoc.v:122279.3-122291.6"
+ process $proc$libresoc.v:122279$4595
assign { } { }
assign { } { }
assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0]
- attribute \src "libresoc.v:122455.5-122455.29"
+ attribute \src "libresoc.v:122280.5-122280.29"
switch \initial
- attribute \src "libresoc.v:122455.9-122455.17"
+ attribute \src "libresoc.v:122280.9-122280.17"
case 1'1
case
end
sync always
update \CR__insn_type $0\CR__insn_type[6:0]
end
- attribute \src "libresoc.v:122467.3-122481.6"
- process $proc$libresoc.v:122467$4612
+ attribute \src "libresoc.v:122292.3-122306.6"
+ process $proc$libresoc.v:122292$4596
assign { } { }
assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0]
- attribute \src "libresoc.v:122468.5-122468.29"
+ attribute \src "libresoc.v:122293.5-122293.29"
switch \initial
- attribute \src "libresoc.v:122468.9-122468.17"
+ attribute \src "libresoc.v:122293.9-122293.17"
case 1'1
case
end
sync always
update \CR__fn_unit $0\CR__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:122409$4587_Y
- connect \$12 $not$libresoc.v:122410$4588_Y
- connect \$14 $and$libresoc.v:122411$4589_Y
- connect \$16 $eq$libresoc.v:122412$4590_Y
- connect \$18 $eq$libresoc.v:122413$4591_Y
- connect \$20 $or$libresoc.v:122414$4592_Y
- connect \$22 $eq$libresoc.v:122415$4593_Y
- connect \$24 $eq$libresoc.v:122416$4594_Y
- connect \$26 $or$libresoc.v:122417$4595_Y
- connect \$28 $eq$libresoc.v:122418$4596_Y
- connect \$2 $eq$libresoc.v:122419$4597_Y
- connect \$30 $or$libresoc.v:122420$4598_Y
- connect \$32 $eq$libresoc.v:122421$4599_Y
- connect \$34 $or$libresoc.v:122422$4600_Y
- connect \$36 $eq$libresoc.v:122423$4601_Y
- connect \$38 $and$libresoc.v:122424$4602_Y
- connect \$40 $and$libresoc.v:122425$4603_Y
- connect \$42 $eq$libresoc.v:122426$4604_Y
- connect \$44 $and$libresoc.v:122427$4605_Y
- connect \$46 $not$libresoc.v:122428$4606_Y
- connect \$48 $and$libresoc.v:122429$4607_Y
- connect \$4 $and$libresoc.v:122430$4608_Y
- connect \$6 $and$libresoc.v:122431$4609_Y
- connect \$8 $eq$libresoc.v:122432$4610_Y
+ connect \$10 $and$libresoc.v:122234$4571_Y
+ connect \$12 $not$libresoc.v:122235$4572_Y
+ connect \$14 $and$libresoc.v:122236$4573_Y
+ connect \$16 $eq$libresoc.v:122237$4574_Y
+ connect \$18 $eq$libresoc.v:122238$4575_Y
+ connect \$20 $or$libresoc.v:122239$4576_Y
+ connect \$22 $eq$libresoc.v:122240$4577_Y
+ connect \$24 $eq$libresoc.v:122241$4578_Y
+ connect \$26 $or$libresoc.v:122242$4579_Y
+ connect \$28 $eq$libresoc.v:122243$4580_Y
+ connect \$2 $eq$libresoc.v:122244$4581_Y
+ connect \$30 $or$libresoc.v:122245$4582_Y
+ connect \$32 $eq$libresoc.v:122246$4583_Y
+ connect \$34 $or$libresoc.v:122247$4584_Y
+ connect \$36 $eq$libresoc.v:122248$4585_Y
+ connect \$38 $and$libresoc.v:122249$4586_Y
+ connect \$40 $and$libresoc.v:122250$4587_Y
+ connect \$42 $eq$libresoc.v:122251$4588_Y
+ connect \$44 $and$libresoc.v:122252$4589_Y
+ connect \$46 $not$libresoc.v:122253$4590_Y
+ connect \$48 $and$libresoc.v:122254$4591_Y
+ connect \$4 $and$libresoc.v:122255$4592_Y
+ connect \$6 $and$libresoc.v:122256$4593_Y
+ connect \$8 $eq$libresoc.v:122257$4594_Y
connect \is_mmu_spr \$34
connect \is_spr_mv \$20
connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] }
connect \insn_in \dec_opcode_in
connect \CR__insn \dec_opcode_in
end
-attribute \src "libresoc.v:122494.1-123077.10"
+attribute \src "libresoc.v:122319.1-122902.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV"
attribute \generator "nMigen"
module \dec_DIV
- attribute \src "libresoc.v:123040.3-123054.6"
+ attribute \src "libresoc.v:122865.3-122879.6"
wire width 14 $0\DIV__fn_unit[13:0]
- attribute \src "libresoc.v:123027.3-123039.6"
+ attribute \src "libresoc.v:122852.3-122864.6"
wire width 7 $0\DIV__insn_type[6:0]
- attribute \src "libresoc.v:123012.3-123026.6"
+ attribute \src "libresoc.v:122837.3-122851.6"
wire $0\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:122495.7-122495.20"
+ attribute \src "libresoc.v:122320.7-122320.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:123040.3-123054.6"
+ attribute \src "libresoc.v:122865.3-122879.6"
wire width 14 $1\DIV__fn_unit[13:0]
- attribute \src "libresoc.v:123027.3-123039.6"
+ attribute \src "libresoc.v:122852.3-122864.6"
wire width 7 $1\DIV__insn_type[6:0]
- attribute \src "libresoc.v:123012.3-123026.6"
+ attribute \src "libresoc.v:122837.3-122851.6"
wire $1\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:122928.18-122928.113"
- wire $and$libresoc.v:122928$4614_Y
- attribute \src "libresoc.v:122930.18-122930.110"
- wire $and$libresoc.v:122930$4616_Y
- attribute \src "libresoc.v:122943.18-122943.114"
- wire $and$libresoc.v:122943$4629_Y
- attribute \src "libresoc.v:122944.18-122944.116"
- wire $and$libresoc.v:122944$4630_Y
- attribute \src "libresoc.v:122946.18-122946.114"
- wire $and$libresoc.v:122946$4632_Y
- attribute \src "libresoc.v:122948.18-122948.110"
- wire $and$libresoc.v:122948$4634_Y
- attribute \src "libresoc.v:122949.17-122949.112"
- wire $and$libresoc.v:122949$4635_Y
- attribute \src "libresoc.v:122950.17-122950.114"
- wire $and$libresoc.v:122950$4636_Y
- attribute \src "libresoc.v:122931.18-122931.126"
- wire $eq$libresoc.v:122931$4617_Y
- attribute \src "libresoc.v:122932.18-122932.126"
- wire $eq$libresoc.v:122932$4618_Y
- attribute \src "libresoc.v:122934.18-122934.110"
- wire $eq$libresoc.v:122934$4620_Y
- attribute \src "libresoc.v:122935.18-122935.110"
- wire $eq$libresoc.v:122935$4621_Y
- attribute \src "libresoc.v:122937.18-122937.112"
- wire $eq$libresoc.v:122937$4623_Y
- attribute \src "libresoc.v:122938.17-122938.130"
- wire $eq$libresoc.v:122938$4624_Y
- attribute \src "libresoc.v:122940.18-122940.110"
- wire $eq$libresoc.v:122940$4626_Y
- attribute \src "libresoc.v:122942.18-122942.131"
- wire $eq$libresoc.v:122942$4628_Y
- attribute \src "libresoc.v:122945.18-122945.131"
- wire $eq$libresoc.v:122945$4631_Y
- attribute \src "libresoc.v:122951.17-122951.130"
- wire $eq$libresoc.v:122951$4637_Y
- attribute \src "libresoc.v:122929.18-122929.110"
- wire $not$libresoc.v:122929$4615_Y
- attribute \src "libresoc.v:122947.18-122947.110"
- wire $not$libresoc.v:122947$4633_Y
- attribute \src "libresoc.v:122933.18-122933.110"
- wire $or$libresoc.v:122933$4619_Y
- attribute \src "libresoc.v:122936.18-122936.110"
- wire $or$libresoc.v:122936$4622_Y
- attribute \src "libresoc.v:122939.18-122939.110"
- wire $or$libresoc.v:122939$4625_Y
- attribute \src "libresoc.v:122941.18-122941.110"
- wire $or$libresoc.v:122941$4627_Y
+ attribute \src "libresoc.v:122753.18-122753.113"
+ wire $and$libresoc.v:122753$4598_Y
+ attribute \src "libresoc.v:122755.18-122755.110"
+ wire $and$libresoc.v:122755$4600_Y
+ attribute \src "libresoc.v:122768.18-122768.114"
+ wire $and$libresoc.v:122768$4613_Y
+ attribute \src "libresoc.v:122769.18-122769.116"
+ wire $and$libresoc.v:122769$4614_Y
+ attribute \src "libresoc.v:122771.18-122771.114"
+ wire $and$libresoc.v:122771$4616_Y
+ attribute \src "libresoc.v:122773.18-122773.110"
+ wire $and$libresoc.v:122773$4618_Y
+ attribute \src "libresoc.v:122774.17-122774.112"
+ wire $and$libresoc.v:122774$4619_Y
+ attribute \src "libresoc.v:122775.17-122775.114"
+ wire $and$libresoc.v:122775$4620_Y
+ attribute \src "libresoc.v:122756.18-122756.126"
+ wire $eq$libresoc.v:122756$4601_Y
+ attribute \src "libresoc.v:122757.18-122757.126"
+ wire $eq$libresoc.v:122757$4602_Y
+ attribute \src "libresoc.v:122759.18-122759.110"
+ wire $eq$libresoc.v:122759$4604_Y
+ attribute \src "libresoc.v:122760.18-122760.110"
+ wire $eq$libresoc.v:122760$4605_Y
+ attribute \src "libresoc.v:122762.18-122762.112"
+ wire $eq$libresoc.v:122762$4607_Y
+ attribute \src "libresoc.v:122763.17-122763.130"
+ wire $eq$libresoc.v:122763$4608_Y
+ attribute \src "libresoc.v:122765.18-122765.110"
+ wire $eq$libresoc.v:122765$4610_Y
+ attribute \src "libresoc.v:122767.18-122767.131"
+ wire $eq$libresoc.v:122767$4612_Y
+ attribute \src "libresoc.v:122770.18-122770.131"
+ wire $eq$libresoc.v:122770$4615_Y
+ attribute \src "libresoc.v:122776.17-122776.130"
+ wire $eq$libresoc.v:122776$4621_Y
+ attribute \src "libresoc.v:122754.18-122754.110"
+ wire $not$libresoc.v:122754$4599_Y
+ attribute \src "libresoc.v:122772.18-122772.110"
+ wire $not$libresoc.v:122772$4617_Y
+ attribute \src "libresoc.v:122758.18-122758.110"
+ wire $or$libresoc.v:122758$4603_Y
+ attribute \src "libresoc.v:122761.18-122761.110"
+ wire $or$libresoc.v:122761$4606_Y
+ attribute \src "libresoc.v:122764.18-122764.110"
+ wire $or$libresoc.v:122764$4609_Y
+ attribute \src "libresoc.v:122766.18-122766.110"
+ wire $or$libresoc.v:122766$4611_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:122495.7-122495.15"
+ attribute \src "libresoc.v:122320.7-122320.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
wire input 2 \sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122928$4614
+ cell $and $and$libresoc.v:122753$4598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:122928$4614_Y
+ connect \Y $and$libresoc.v:122753$4598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122930$4616
+ cell $and $and$libresoc.v:122755$4600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:122930$4616_Y
+ connect \Y $and$libresoc.v:122755$4600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122943$4629
+ cell $and $and$libresoc.v:122768$4613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:122943$4629_Y
+ connect \Y $and$libresoc.v:122768$4613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122944$4630
+ cell $and $and$libresoc.v:122769$4614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122944$4630_Y
+ connect \Y $and$libresoc.v:122769$4614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122946$4632
+ cell $and $and$libresoc.v:122771$4616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:122946$4632_Y
+ connect \Y $and$libresoc.v:122771$4616_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:122948$4634
+ cell $and $and$libresoc.v:122773$4618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:122948$4634_Y
+ connect \Y $and$libresoc.v:122773$4618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122949$4635
+ cell $and $and$libresoc.v:122774$4619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:122949$4635_Y
+ connect \Y $and$libresoc.v:122774$4619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:122950$4636
+ cell $and $and$libresoc.v:122775$4620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122950$4636_Y
+ connect \Y $and$libresoc.v:122775$4620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:122931$4617
+ cell $eq $eq$libresoc.v:122756$4601
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:122931$4617_Y
+ connect \Y $eq$libresoc.v:122756$4601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:122932$4618
+ cell $eq $eq$libresoc.v:122757$4602
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:122932$4618_Y
+ connect \Y $eq$libresoc.v:122757$4602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122934$4620
+ cell $eq $eq$libresoc.v:122759$4604
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:122934$4620_Y
+ connect \Y $eq$libresoc.v:122759$4604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122935$4621
+ cell $eq $eq$libresoc.v:122760$4605
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:122935$4621_Y
+ connect \Y $eq$libresoc.v:122760$4605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:122937$4623
+ cell $eq $eq$libresoc.v:122762$4607
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:122937$4623_Y
+ connect \Y $eq$libresoc.v:122762$4607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122938$4624
+ cell $eq $eq$libresoc.v:122763$4608
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122938$4624_Y
+ connect \Y $eq$libresoc.v:122763$4608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:122940$4626
+ cell $eq $eq$libresoc.v:122765$4610
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:122940$4626_Y
+ connect \Y $eq$libresoc.v:122765$4610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:122942$4628
+ cell $eq $eq$libresoc.v:122767$4612
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:122942$4628_Y
+ connect \Y $eq$libresoc.v:122767$4612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122945$4631
+ cell $eq $eq$libresoc.v:122770$4615
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122945$4631_Y
+ connect \Y $eq$libresoc.v:122770$4615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:122951$4637
+ cell $eq $eq$libresoc.v:122776$4621
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:122951$4637_Y
+ connect \Y $eq$libresoc.v:122776$4621_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:122929$4615
+ cell $not $not$libresoc.v:122754$4599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122929$4615_Y
+ connect \Y $not$libresoc.v:122754$4599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:122947$4633
+ cell $not $not$libresoc.v:122772$4617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122947$4633_Y
+ connect \Y $not$libresoc.v:122772$4617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:122933$4619
+ cell $or $or$libresoc.v:122758$4603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:122933$4619_Y
+ connect \Y $or$libresoc.v:122758$4603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122936$4622
+ cell $or $or$libresoc.v:122761$4606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:122936$4622_Y
+ connect \Y $or$libresoc.v:122761$4606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:122939$4625
+ cell $or $or$libresoc.v:122764$4609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:122939$4625_Y
+ connect \Y $or$libresoc.v:122764$4609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:122941$4627
+ cell $or $or$libresoc.v:122766$4611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:122941$4627_Y
+ connect \Y $or$libresoc.v:122766$4611_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122952.13-122980.4"
+ attribute \src "libresoc.v:122777.13-122805.4"
cell \dec$153 \dec
connect \DIV_BD \dec_DIV_BD
connect \DIV_DS \dec_DIV_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122981.16-122986.4"
+ attribute \src "libresoc.v:122806.16-122811.4"
cell \dec_ai$156 \dec_ai
connect \DIV_RA \dec_DIV_RA
connect \immz_out \dec_ai_immz_out
connect \sv_nz \dec_ai_sv_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122987.16-122998.4"
+ attribute \src "libresoc.v:122812.16-122823.4"
cell \dec_bi$157 \dec_bi
connect \DIV_BD \dec_DIV_BD
connect \DIV_DS \dec_DIV_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122999.16-123005.4"
+ attribute \src "libresoc.v:122824.16-122830.4"
cell \dec_oe$155 \dec_oe
connect \DIV_OE \dec_DIV_OE
connect \DIV_internal_op \dec_DIV_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123006.16-123011.4"
+ attribute \src "libresoc.v:122831.16-122836.4"
cell \dec_rc$154 \dec_rc
connect \DIV_Rc \dec_DIV_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:122495.7-122495.20"
- process $proc$libresoc.v:122495$4641
+ attribute \src "libresoc.v:122320.7-122320.20"
+ process $proc$libresoc.v:122320$4625
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:123012.3-123026.6"
- process $proc$libresoc.v:123012$4638
+ attribute \src "libresoc.v:122837.3-122851.6"
+ process $proc$libresoc.v:122837$4622
assign { } { }
assign { } { }
assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:123013.5-123013.29"
+ attribute \src "libresoc.v:122838.5-122838.29"
switch \initial
- attribute \src "libresoc.v:123013.9-123013.17"
+ attribute \src "libresoc.v:122838.9-122838.17"
case 1'1
case
end
sync always
update \DIV__write_cr0 $0\DIV__write_cr0[0:0]
end
- attribute \src "libresoc.v:123027.3-123039.6"
- process $proc$libresoc.v:123027$4639
+ attribute \src "libresoc.v:122852.3-122864.6"
+ process $proc$libresoc.v:122852$4623
assign { } { }
assign { } { }
assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0]
- attribute \src "libresoc.v:123028.5-123028.29"
+ attribute \src "libresoc.v:122853.5-122853.29"
switch \initial
- attribute \src "libresoc.v:123028.9-123028.17"
+ attribute \src "libresoc.v:122853.9-122853.17"
case 1'1
case
end
sync always
update \DIV__insn_type $0\DIV__insn_type[6:0]
end
- attribute \src "libresoc.v:123040.3-123054.6"
- process $proc$libresoc.v:123040$4640
+ attribute \src "libresoc.v:122865.3-122879.6"
+ process $proc$libresoc.v:122865$4624
assign { } { }
assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0]
- attribute \src "libresoc.v:123041.5-123041.29"
+ attribute \src "libresoc.v:122866.5-122866.29"
switch \initial
- attribute \src "libresoc.v:123041.9-123041.17"
+ attribute \src "libresoc.v:122866.9-122866.17"
case 1'1
case
end
sync always
update \DIV__fn_unit $0\DIV__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:122928$4614_Y
- connect \$12 $not$libresoc.v:122929$4615_Y
- connect \$14 $and$libresoc.v:122930$4616_Y
- connect \$16 $eq$libresoc.v:122931$4617_Y
- connect \$18 $eq$libresoc.v:122932$4618_Y
- connect \$20 $or$libresoc.v:122933$4619_Y
- connect \$22 $eq$libresoc.v:122934$4620_Y
- connect \$24 $eq$libresoc.v:122935$4621_Y
- connect \$26 $or$libresoc.v:122936$4622_Y
- connect \$28 $eq$libresoc.v:122937$4623_Y
- connect \$2 $eq$libresoc.v:122938$4624_Y
- connect \$30 $or$libresoc.v:122939$4625_Y
- connect \$32 $eq$libresoc.v:122940$4626_Y
- connect \$34 $or$libresoc.v:122941$4627_Y
- connect \$36 $eq$libresoc.v:122942$4628_Y
- connect \$38 $and$libresoc.v:122943$4629_Y
- connect \$40 $and$libresoc.v:122944$4630_Y
- connect \$42 $eq$libresoc.v:122945$4631_Y
- connect \$44 $and$libresoc.v:122946$4632_Y
- connect \$46 $not$libresoc.v:122947$4633_Y
- connect \$48 $and$libresoc.v:122948$4634_Y
- connect \$4 $and$libresoc.v:122949$4635_Y
- connect \$6 $and$libresoc.v:122950$4636_Y
- connect \$8 $eq$libresoc.v:122951$4637_Y
+ connect \$10 $and$libresoc.v:122753$4598_Y
+ connect \$12 $not$libresoc.v:122754$4599_Y
+ connect \$14 $and$libresoc.v:122755$4600_Y
+ connect \$16 $eq$libresoc.v:122756$4601_Y
+ connect \$18 $eq$libresoc.v:122757$4602_Y
+ connect \$20 $or$libresoc.v:122758$4603_Y
+ connect \$22 $eq$libresoc.v:122759$4604_Y
+ connect \$24 $eq$libresoc.v:122760$4605_Y
+ connect \$26 $or$libresoc.v:122761$4606_Y
+ connect \$28 $eq$libresoc.v:122762$4607_Y
+ connect \$2 $eq$libresoc.v:122763$4608_Y
+ connect \$30 $or$libresoc.v:122764$4609_Y
+ connect \$32 $eq$libresoc.v:122765$4610_Y
+ connect \$34 $or$libresoc.v:122766$4611_Y
+ connect \$36 $eq$libresoc.v:122767$4612_Y
+ connect \$38 $and$libresoc.v:122768$4613_Y
+ connect \$40 $and$libresoc.v:122769$4614_Y
+ connect \$42 $eq$libresoc.v:122770$4615_Y
+ connect \$44 $and$libresoc.v:122771$4616_Y
+ connect \$46 $not$libresoc.v:122772$4617_Y
+ connect \$48 $and$libresoc.v:122773$4618_Y
+ connect \$4 $and$libresoc.v:122774$4619_Y
+ connect \$6 $and$libresoc.v:122775$4620_Y
+ connect \$8 $eq$libresoc.v:122776$4621_Y
connect \DIV__is_signed \dec_DIV_sgn
connect \DIV__is_32bit \dec_DIV_is_32b
connect \DIV__output_carry \dec_DIV_cry_out
connect \insn_in \dec_opcode_in
connect \DIV__insn \dec_opcode_in
end
-attribute \src "libresoc.v:123081.1-123642.10"
+attribute \src "libresoc.v:122906.1-123467.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST"
attribute \generator "nMigen"
module \dec_LDST
- attribute \src "libresoc.v:123606.3-123620.6"
+ attribute \src "libresoc.v:123431.3-123445.6"
wire width 14 $0\LDST__fn_unit[13:0]
- attribute \src "libresoc.v:123593.3-123605.6"
+ attribute \src "libresoc.v:123418.3-123430.6"
wire width 7 $0\LDST__insn_type[6:0]
- attribute \src "libresoc.v:123082.7-123082.20"
+ attribute \src "libresoc.v:122907.7-122907.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:123606.3-123620.6"
+ attribute \src "libresoc.v:123431.3-123445.6"
wire width 14 $1\LDST__fn_unit[13:0]
- attribute \src "libresoc.v:123593.3-123605.6"
+ attribute \src "libresoc.v:123418.3-123430.6"
wire width 7 $1\LDST__insn_type[6:0]
- attribute \src "libresoc.v:123510.18-123510.113"
- wire $and$libresoc.v:123510$4642_Y
- attribute \src "libresoc.v:123512.18-123512.110"
- wire $and$libresoc.v:123512$4644_Y
- attribute \src "libresoc.v:123525.18-123525.114"
- wire $and$libresoc.v:123525$4657_Y
- attribute \src "libresoc.v:123526.18-123526.116"
- wire $and$libresoc.v:123526$4658_Y
- attribute \src "libresoc.v:123528.18-123528.114"
- wire $and$libresoc.v:123528$4660_Y
- attribute \src "libresoc.v:123530.18-123530.110"
- wire $and$libresoc.v:123530$4662_Y
- attribute \src "libresoc.v:123531.17-123531.112"
- wire $and$libresoc.v:123531$4663_Y
- attribute \src "libresoc.v:123532.17-123532.114"
- wire $and$libresoc.v:123532$4664_Y
- attribute \src "libresoc.v:123513.18-123513.127"
- wire $eq$libresoc.v:123513$4645_Y
- attribute \src "libresoc.v:123514.18-123514.127"
- wire $eq$libresoc.v:123514$4646_Y
- attribute \src "libresoc.v:123516.18-123516.110"
- wire $eq$libresoc.v:123516$4648_Y
- attribute \src "libresoc.v:123517.18-123517.110"
- wire $eq$libresoc.v:123517$4649_Y
- attribute \src "libresoc.v:123519.18-123519.112"
- wire $eq$libresoc.v:123519$4651_Y
- attribute \src "libresoc.v:123520.17-123520.131"
- wire $eq$libresoc.v:123520$4652_Y
- attribute \src "libresoc.v:123522.18-123522.110"
- wire $eq$libresoc.v:123522$4654_Y
- attribute \src "libresoc.v:123524.18-123524.132"
- wire $eq$libresoc.v:123524$4656_Y
- attribute \src "libresoc.v:123527.18-123527.132"
- wire $eq$libresoc.v:123527$4659_Y
- attribute \src "libresoc.v:123533.17-123533.131"
- wire $eq$libresoc.v:123533$4665_Y
- attribute \src "libresoc.v:123511.18-123511.110"
- wire $not$libresoc.v:123511$4643_Y
- attribute \src "libresoc.v:123529.18-123529.110"
- wire $not$libresoc.v:123529$4661_Y
- attribute \src "libresoc.v:123515.18-123515.110"
- wire $or$libresoc.v:123515$4647_Y
- attribute \src "libresoc.v:123518.18-123518.110"
- wire $or$libresoc.v:123518$4650_Y
- attribute \src "libresoc.v:123521.18-123521.110"
- wire $or$libresoc.v:123521$4653_Y
- attribute \src "libresoc.v:123523.18-123523.110"
- wire $or$libresoc.v:123523$4655_Y
+ attribute \src "libresoc.v:123335.18-123335.113"
+ wire $and$libresoc.v:123335$4626_Y
+ attribute \src "libresoc.v:123337.18-123337.110"
+ wire $and$libresoc.v:123337$4628_Y
+ attribute \src "libresoc.v:123350.18-123350.114"
+ wire $and$libresoc.v:123350$4641_Y
+ attribute \src "libresoc.v:123351.18-123351.116"
+ wire $and$libresoc.v:123351$4642_Y
+ attribute \src "libresoc.v:123353.18-123353.114"
+ wire $and$libresoc.v:123353$4644_Y
+ attribute \src "libresoc.v:123355.18-123355.110"
+ wire $and$libresoc.v:123355$4646_Y
+ attribute \src "libresoc.v:123356.17-123356.112"
+ wire $and$libresoc.v:123356$4647_Y
+ attribute \src "libresoc.v:123357.17-123357.114"
+ wire $and$libresoc.v:123357$4648_Y
+ attribute \src "libresoc.v:123338.18-123338.127"
+ wire $eq$libresoc.v:123338$4629_Y
+ attribute \src "libresoc.v:123339.18-123339.127"
+ wire $eq$libresoc.v:123339$4630_Y
+ attribute \src "libresoc.v:123341.18-123341.110"
+ wire $eq$libresoc.v:123341$4632_Y
+ attribute \src "libresoc.v:123342.18-123342.110"
+ wire $eq$libresoc.v:123342$4633_Y
+ attribute \src "libresoc.v:123344.18-123344.112"
+ wire $eq$libresoc.v:123344$4635_Y
+ attribute \src "libresoc.v:123345.17-123345.131"
+ wire $eq$libresoc.v:123345$4636_Y
+ attribute \src "libresoc.v:123347.18-123347.110"
+ wire $eq$libresoc.v:123347$4638_Y
+ attribute \src "libresoc.v:123349.18-123349.132"
+ wire $eq$libresoc.v:123349$4640_Y
+ attribute \src "libresoc.v:123352.18-123352.132"
+ wire $eq$libresoc.v:123352$4643_Y
+ attribute \src "libresoc.v:123358.17-123358.131"
+ wire $eq$libresoc.v:123358$4649_Y
+ attribute \src "libresoc.v:123336.18-123336.110"
+ wire $not$libresoc.v:123336$4627_Y
+ attribute \src "libresoc.v:123354.18-123354.110"
+ wire $not$libresoc.v:123354$4645_Y
+ attribute \src "libresoc.v:123340.18-123340.110"
+ wire $or$libresoc.v:123340$4631_Y
+ attribute \src "libresoc.v:123343.18-123343.110"
+ wire $or$libresoc.v:123343$4634_Y
+ attribute \src "libresoc.v:123346.18-123346.110"
+ wire $or$libresoc.v:123346$4637_Y
+ attribute \src "libresoc.v:123348.18-123348.110"
+ wire $or$libresoc.v:123348$4639_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:123082.7-123082.15"
+ attribute \src "libresoc.v:122907.7-122907.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
wire input 2 \sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:123510$4642
+ cell $and $and$libresoc.v:123335$4626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:123510$4642_Y
+ connect \Y $and$libresoc.v:123335$4626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:123512$4644
+ cell $and $and$libresoc.v:123337$4628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:123512$4644_Y
+ connect \Y $and$libresoc.v:123337$4628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:123525$4657
+ cell $and $and$libresoc.v:123350$4641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:123525$4657_Y
+ connect \Y $and$libresoc.v:123350$4641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:123526$4658
+ cell $and $and$libresoc.v:123351$4642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123526$4658_Y
+ connect \Y $and$libresoc.v:123351$4642_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:123528$4660
+ cell $and $and$libresoc.v:123353$4644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:123528$4660_Y
+ connect \Y $and$libresoc.v:123353$4644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:123530$4662
+ cell $and $and$libresoc.v:123355$4646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:123530$4662_Y
+ connect \Y $and$libresoc.v:123355$4646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:123531$4663
+ cell $and $and$libresoc.v:123356$4647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:123531$4663_Y
+ connect \Y $and$libresoc.v:123356$4647_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:123532$4664
+ cell $and $and$libresoc.v:123357$4648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123532$4664_Y
+ connect \Y $and$libresoc.v:123357$4648_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:123513$4645
+ cell $eq $eq$libresoc.v:123338$4629
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:123513$4645_Y
+ connect \Y $eq$libresoc.v:123338$4629_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:123514$4646
+ cell $eq $eq$libresoc.v:123339$4630
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:123514$4646_Y
+ connect \Y $eq$libresoc.v:123339$4630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:123516$4648
+ cell $eq $eq$libresoc.v:123341$4632
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:123516$4648_Y
+ connect \Y $eq$libresoc.v:123341$4632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:123517$4649
+ cell $eq $eq$libresoc.v:123342$4633
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:123517$4649_Y
+ connect \Y $eq$libresoc.v:123342$4633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:123519$4651
+ cell $eq $eq$libresoc.v:123344$4635
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:123519$4651_Y
+ connect \Y $eq$libresoc.v:123344$4635_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:123520$4652
+ cell $eq $eq$libresoc.v:123345$4636
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:123520$4652_Y
+ connect \Y $eq$libresoc.v:123345$4636_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:123522$4654
+ cell $eq $eq$libresoc.v:123347$4638
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:123522$4654_Y
+ connect \Y $eq$libresoc.v:123347$4638_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:123524$4656
+ cell $eq $eq$libresoc.v:123349$4640
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:123524$4656_Y
+ connect \Y $eq$libresoc.v:123349$4640_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:123527$4659
+ cell $eq $eq$libresoc.v:123352$4643
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:123527$4659_Y
+ connect \Y $eq$libresoc.v:123352$4643_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:123533$4665
+ cell $eq $eq$libresoc.v:123358$4649
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:123533$4665_Y
+ connect \Y $eq$libresoc.v:123358$4649_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:123511$4643
+ cell $not $not$libresoc.v:123336$4627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123511$4643_Y
+ connect \Y $not$libresoc.v:123336$4627_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:123529$4661
+ cell $not $not$libresoc.v:123354$4645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123529$4661_Y
+ connect \Y $not$libresoc.v:123354$4645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:123515$4647
+ cell $or $or$libresoc.v:123340$4631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:123515$4647_Y
+ connect \Y $or$libresoc.v:123340$4631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:123518$4650
+ cell $or $or$libresoc.v:123343$4634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:123518$4650_Y
+ connect \Y $or$libresoc.v:123343$4634_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:123521$4653
+ cell $or $or$libresoc.v:123346$4637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:123521$4653_Y
+ connect \Y $or$libresoc.v:123346$4637_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:123523$4655
+ cell $or $or$libresoc.v:123348$4639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:123523$4655_Y
+ connect \Y $or$libresoc.v:123348$4639_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123534.13-123561.4"
+ attribute \src "libresoc.v:123359.13-123386.4"
cell \dec$166 \dec
connect \LDST_BD \dec_LDST_BD
connect \LDST_DS \dec_LDST_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123562.16-123567.4"
+ attribute \src "libresoc.v:123387.16-123392.4"
cell \dec_ai$169 \dec_ai
connect \LDST_RA \dec_LDST_RA
connect \immz_out \dec_ai_immz_out
connect \sv_nz \dec_ai_sv_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123568.16-123579.4"
+ attribute \src "libresoc.v:123393.16-123404.4"
cell \dec_bi$170 \dec_bi
connect \LDST_BD \dec_LDST_BD
connect \LDST_DS \dec_LDST_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123580.16-123586.4"
+ attribute \src "libresoc.v:123405.16-123411.4"
cell \dec_oe$168 \dec_oe
connect \LDST_OE \dec_LDST_OE
connect \LDST_internal_op \dec_LDST_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123587.16-123592.4"
+ attribute \src "libresoc.v:123412.16-123417.4"
cell \dec_rc$167 \dec_rc
connect \LDST_Rc \dec_LDST_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:123082.7-123082.20"
- process $proc$libresoc.v:123082$4668
+ attribute \src "libresoc.v:122907.7-122907.20"
+ process $proc$libresoc.v:122907$4652
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:123593.3-123605.6"
- process $proc$libresoc.v:123593$4666
+ attribute \src "libresoc.v:123418.3-123430.6"
+ process $proc$libresoc.v:123418$4650
assign { } { }
assign { } { }
assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0]
- attribute \src "libresoc.v:123594.5-123594.29"
+ attribute \src "libresoc.v:123419.5-123419.29"
switch \initial
- attribute \src "libresoc.v:123594.9-123594.17"
+ attribute \src "libresoc.v:123419.9-123419.17"
case 1'1
case
end
sync always
update \LDST__insn_type $0\LDST__insn_type[6:0]
end
- attribute \src "libresoc.v:123606.3-123620.6"
- process $proc$libresoc.v:123606$4667
+ attribute \src "libresoc.v:123431.3-123445.6"
+ process $proc$libresoc.v:123431$4651
assign { } { }
assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0]
- attribute \src "libresoc.v:123607.5-123607.29"
+ attribute \src "libresoc.v:123432.5-123432.29"
switch \initial
- attribute \src "libresoc.v:123607.9-123607.17"
+ attribute \src "libresoc.v:123432.9-123432.17"
case 1'1
case
end
sync always
update \LDST__fn_unit $0\LDST__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:123510$4642_Y
- connect \$12 $not$libresoc.v:123511$4643_Y
- connect \$14 $and$libresoc.v:123512$4644_Y
- connect \$16 $eq$libresoc.v:123513$4645_Y
- connect \$18 $eq$libresoc.v:123514$4646_Y
- connect \$20 $or$libresoc.v:123515$4647_Y
- connect \$22 $eq$libresoc.v:123516$4648_Y
- connect \$24 $eq$libresoc.v:123517$4649_Y
- connect \$26 $or$libresoc.v:123518$4650_Y
- connect \$28 $eq$libresoc.v:123519$4651_Y
- connect \$2 $eq$libresoc.v:123520$4652_Y
- connect \$30 $or$libresoc.v:123521$4653_Y
- connect \$32 $eq$libresoc.v:123522$4654_Y
- connect \$34 $or$libresoc.v:123523$4655_Y
- connect \$36 $eq$libresoc.v:123524$4656_Y
- connect \$38 $and$libresoc.v:123525$4657_Y
- connect \$40 $and$libresoc.v:123526$4658_Y
- connect \$42 $eq$libresoc.v:123527$4659_Y
- connect \$44 $and$libresoc.v:123528$4660_Y
- connect \$46 $not$libresoc.v:123529$4661_Y
- connect \$48 $and$libresoc.v:123530$4662_Y
- connect \$4 $and$libresoc.v:123531$4663_Y
- connect \$6 $and$libresoc.v:123532$4664_Y
- connect \$8 $eq$libresoc.v:123533$4665_Y
+ connect \$10 $and$libresoc.v:123335$4626_Y
+ connect \$12 $not$libresoc.v:123336$4627_Y
+ connect \$14 $and$libresoc.v:123337$4628_Y
+ connect \$16 $eq$libresoc.v:123338$4629_Y
+ connect \$18 $eq$libresoc.v:123339$4630_Y
+ connect \$20 $or$libresoc.v:123340$4631_Y
+ connect \$22 $eq$libresoc.v:123341$4632_Y
+ connect \$24 $eq$libresoc.v:123342$4633_Y
+ connect \$26 $or$libresoc.v:123343$4634_Y
+ connect \$28 $eq$libresoc.v:123344$4635_Y
+ connect \$2 $eq$libresoc.v:123345$4636_Y
+ connect \$30 $or$libresoc.v:123346$4637_Y
+ connect \$32 $eq$libresoc.v:123347$4638_Y
+ connect \$34 $or$libresoc.v:123348$4639_Y
+ connect \$36 $eq$libresoc.v:123349$4640_Y
+ connect \$38 $and$libresoc.v:123350$4641_Y
+ connect \$40 $and$libresoc.v:123351$4642_Y
+ connect \$42 $eq$libresoc.v:123352$4643_Y
+ connect \$44 $and$libresoc.v:123353$4644_Y
+ connect \$46 $not$libresoc.v:123354$4645_Y
+ connect \$48 $and$libresoc.v:123355$4646_Y
+ connect \$4 $and$libresoc.v:123356$4647_Y
+ connect \$6 $and$libresoc.v:123357$4648_Y
+ connect \$8 $eq$libresoc.v:123358$4649_Y
connect \LDST__ldst_mode \dec_LDST_upd
connect \LDST__sign_extend \dec_LDST_sgn_ext
connect \LDST__byte_reverse \dec_LDST_br
connect \insn_in \dec_opcode_in
connect \LDST__insn \dec_opcode_in
end
-attribute \src "libresoc.v:123646.1-124229.10"
+attribute \src "libresoc.v:123471.1-124054.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL"
attribute \generator "nMigen"
module \dec_LOGICAL
- attribute \src "libresoc.v:124192.3-124206.6"
+ attribute \src "libresoc.v:124017.3-124031.6"
wire width 14 $0\LOGICAL__fn_unit[13:0]
- attribute \src "libresoc.v:124179.3-124191.6"
+ attribute \src "libresoc.v:124004.3-124016.6"
wire width 7 $0\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:124164.3-124178.6"
+ attribute \src "libresoc.v:123989.3-124003.6"
wire $0\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:123647.7-123647.20"
+ attribute \src "libresoc.v:123472.7-123472.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124192.3-124206.6"
+ attribute \src "libresoc.v:124017.3-124031.6"
wire width 14 $1\LOGICAL__fn_unit[13:0]
- attribute \src "libresoc.v:124179.3-124191.6"
+ attribute \src "libresoc.v:124004.3-124016.6"
wire width 7 $1\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:124164.3-124178.6"
+ attribute \src "libresoc.v:123989.3-124003.6"
wire $1\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:124080.18-124080.113"
- wire $and$libresoc.v:124080$4669_Y
- attribute \src "libresoc.v:124082.18-124082.110"
- wire $and$libresoc.v:124082$4671_Y
- attribute \src "libresoc.v:124095.18-124095.114"
- wire $and$libresoc.v:124095$4684_Y
- attribute \src "libresoc.v:124096.18-124096.116"
- wire $and$libresoc.v:124096$4685_Y
- attribute \src "libresoc.v:124098.18-124098.114"
- wire $and$libresoc.v:124098$4687_Y
- attribute \src "libresoc.v:124100.18-124100.110"
- wire $and$libresoc.v:124100$4689_Y
- attribute \src "libresoc.v:124101.17-124101.112"
- wire $and$libresoc.v:124101$4690_Y
- attribute \src "libresoc.v:124102.17-124102.114"
- wire $and$libresoc.v:124102$4691_Y
- attribute \src "libresoc.v:124083.18-124083.130"
- wire $eq$libresoc.v:124083$4672_Y
- attribute \src "libresoc.v:124084.18-124084.130"
- wire $eq$libresoc.v:124084$4673_Y
- attribute \src "libresoc.v:124086.18-124086.110"
- wire $eq$libresoc.v:124086$4675_Y
- attribute \src "libresoc.v:124087.18-124087.110"
- wire $eq$libresoc.v:124087$4676_Y
- attribute \src "libresoc.v:124089.18-124089.112"
- wire $eq$libresoc.v:124089$4678_Y
- attribute \src "libresoc.v:124090.17-124090.134"
- wire $eq$libresoc.v:124090$4679_Y
- attribute \src "libresoc.v:124092.18-124092.110"
- wire $eq$libresoc.v:124092$4681_Y
- attribute \src "libresoc.v:124094.18-124094.135"
- wire $eq$libresoc.v:124094$4683_Y
- attribute \src "libresoc.v:124097.18-124097.135"
- wire $eq$libresoc.v:124097$4686_Y
- attribute \src "libresoc.v:124103.17-124103.134"
- wire $eq$libresoc.v:124103$4692_Y
- attribute \src "libresoc.v:124081.18-124081.110"
- wire $not$libresoc.v:124081$4670_Y
- attribute \src "libresoc.v:124099.18-124099.110"
- wire $not$libresoc.v:124099$4688_Y
- attribute \src "libresoc.v:124085.18-124085.110"
- wire $or$libresoc.v:124085$4674_Y
- attribute \src "libresoc.v:124088.18-124088.110"
- wire $or$libresoc.v:124088$4677_Y
- attribute \src "libresoc.v:124091.18-124091.110"
- wire $or$libresoc.v:124091$4680_Y
- attribute \src "libresoc.v:124093.18-124093.110"
- wire $or$libresoc.v:124093$4682_Y
+ attribute \src "libresoc.v:123905.18-123905.113"
+ wire $and$libresoc.v:123905$4653_Y
+ attribute \src "libresoc.v:123907.18-123907.110"
+ wire $and$libresoc.v:123907$4655_Y
+ attribute \src "libresoc.v:123920.18-123920.114"
+ wire $and$libresoc.v:123920$4668_Y
+ attribute \src "libresoc.v:123921.18-123921.116"
+ wire $and$libresoc.v:123921$4669_Y
+ attribute \src "libresoc.v:123923.18-123923.114"
+ wire $and$libresoc.v:123923$4671_Y
+ attribute \src "libresoc.v:123925.18-123925.110"
+ wire $and$libresoc.v:123925$4673_Y
+ attribute \src "libresoc.v:123926.17-123926.112"
+ wire $and$libresoc.v:123926$4674_Y
+ attribute \src "libresoc.v:123927.17-123927.114"
+ wire $and$libresoc.v:123927$4675_Y
+ attribute \src "libresoc.v:123908.18-123908.130"
+ wire $eq$libresoc.v:123908$4656_Y
+ attribute \src "libresoc.v:123909.18-123909.130"
+ wire $eq$libresoc.v:123909$4657_Y
+ attribute \src "libresoc.v:123911.18-123911.110"
+ wire $eq$libresoc.v:123911$4659_Y
+ attribute \src "libresoc.v:123912.18-123912.110"
+ wire $eq$libresoc.v:123912$4660_Y
+ attribute \src "libresoc.v:123914.18-123914.112"
+ wire $eq$libresoc.v:123914$4662_Y
+ attribute \src "libresoc.v:123915.17-123915.134"
+ wire $eq$libresoc.v:123915$4663_Y
+ attribute \src "libresoc.v:123917.18-123917.110"
+ wire $eq$libresoc.v:123917$4665_Y
+ attribute \src "libresoc.v:123919.18-123919.135"
+ wire $eq$libresoc.v:123919$4667_Y
+ attribute \src "libresoc.v:123922.18-123922.135"
+ wire $eq$libresoc.v:123922$4670_Y
+ attribute \src "libresoc.v:123928.17-123928.134"
+ wire $eq$libresoc.v:123928$4676_Y
+ attribute \src "libresoc.v:123906.18-123906.110"
+ wire $not$libresoc.v:123906$4654_Y
+ attribute \src "libresoc.v:123924.18-123924.110"
+ wire $not$libresoc.v:123924$4672_Y
+ attribute \src "libresoc.v:123910.18-123910.110"
+ wire $or$libresoc.v:123910$4658_Y
+ attribute \src "libresoc.v:123913.18-123913.110"
+ wire $or$libresoc.v:123913$4661_Y
+ attribute \src "libresoc.v:123916.18-123916.110"
+ wire $or$libresoc.v:123916$4664_Y
+ attribute \src "libresoc.v:123918.18-123918.110"
+ wire $or$libresoc.v:123918$4666_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:123647.7-123647.15"
+ attribute \src "libresoc.v:123472.7-123472.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
wire input 2 \sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124080$4669
+ cell $and $and$libresoc.v:123905$4653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:124080$4669_Y
+ connect \Y $and$libresoc.v:123905$4653_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124082$4671
+ cell $and $and$libresoc.v:123907$4655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:124082$4671_Y
+ connect \Y $and$libresoc.v:123907$4655_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124095$4684
+ cell $and $and$libresoc.v:123920$4668
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:124095$4684_Y
+ connect \Y $and$libresoc.v:123920$4668_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124096$4685
+ cell $and $and$libresoc.v:123921$4669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:124096$4685_Y
+ connect \Y $and$libresoc.v:123921$4669_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124098$4687
+ cell $and $and$libresoc.v:123923$4671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:124098$4687_Y
+ connect \Y $and$libresoc.v:123923$4671_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124100$4689
+ cell $and $and$libresoc.v:123925$4673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:124100$4689_Y
+ connect \Y $and$libresoc.v:123925$4673_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124101$4690
+ cell $and $and$libresoc.v:123926$4674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:124101$4690_Y
+ connect \Y $and$libresoc.v:123926$4674_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124102$4691
+ cell $and $and$libresoc.v:123927$4675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:124102$4691_Y
+ connect \Y $and$libresoc.v:123927$4675_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:124083$4672
+ cell $eq $eq$libresoc.v:123908$4656
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:124083$4672_Y
+ connect \Y $eq$libresoc.v:123908$4656_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:124084$4673
+ cell $eq $eq$libresoc.v:123909$4657
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:124084$4673_Y
+ connect \Y $eq$libresoc.v:123909$4657_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124086$4675
+ cell $eq $eq$libresoc.v:123911$4659
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:124086$4675_Y
+ connect \Y $eq$libresoc.v:123911$4659_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124087$4676
+ cell $eq $eq$libresoc.v:123912$4660
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:124087$4676_Y
+ connect \Y $eq$libresoc.v:123912$4660_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124089$4678
+ cell $eq $eq$libresoc.v:123914$4662
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:124089$4678_Y
+ connect \Y $eq$libresoc.v:123914$4662_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:124090$4679
+ cell $eq $eq$libresoc.v:123915$4663
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:124090$4679_Y
+ connect \Y $eq$libresoc.v:123915$4663_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:124092$4681
+ cell $eq $eq$libresoc.v:123917$4665
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:124092$4681_Y
+ connect \Y $eq$libresoc.v:123917$4665_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:124094$4683
+ cell $eq $eq$libresoc.v:123919$4667
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:124094$4683_Y
+ connect \Y $eq$libresoc.v:123919$4667_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:124097$4686
+ cell $eq $eq$libresoc.v:123922$4670
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:124097$4686_Y
+ connect \Y $eq$libresoc.v:123922$4670_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:124103$4692
+ cell $eq $eq$libresoc.v:123928$4676
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:124103$4692_Y
+ connect \Y $eq$libresoc.v:123928$4676_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:124081$4670
+ cell $not $not$libresoc.v:123906$4654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:124081$4670_Y
+ connect \Y $not$libresoc.v:123906$4654_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:124099$4688
+ cell $not $not$libresoc.v:123924$4672
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:124099$4688_Y
+ connect \Y $not$libresoc.v:123924$4672_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:124085$4674
+ cell $or $or$libresoc.v:123910$4658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:124085$4674_Y
+ connect \Y $or$libresoc.v:123910$4658_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:124088$4677
+ cell $or $or$libresoc.v:123913$4661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:124088$4677_Y
+ connect \Y $or$libresoc.v:123913$4661_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:124091$4680
+ cell $or $or$libresoc.v:123916$4664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:124091$4680_Y
+ connect \Y $or$libresoc.v:123916$4664_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:124093$4682
+ cell $or $or$libresoc.v:123918$4666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:124093$4682_Y
+ connect \Y $or$libresoc.v:123918$4666_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124104.13-124132.4"
+ attribute \src "libresoc.v:123929.13-123957.4"
cell \dec$145 \dec
connect \LOGICAL_BD \dec_LOGICAL_BD
connect \LOGICAL_DS \dec_LOGICAL_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124133.16-124138.4"
+ attribute \src "libresoc.v:123958.16-123963.4"
cell \dec_ai$148 \dec_ai
connect \LOGICAL_RA \dec_LOGICAL_RA
connect \immz_out \dec_ai_immz_out
connect \sv_nz \dec_ai_sv_nz
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124139.16-124150.4"
+ attribute \src "libresoc.v:123964.16-123975.4"
cell \dec_bi$149 \dec_bi
connect \LOGICAL_BD \dec_LOGICAL_BD
connect \LOGICAL_DS \dec_LOGICAL_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124151.16-124157.4"
+ attribute \src "libresoc.v:123976.16-123982.4"
cell \dec_oe$147 \dec_oe
connect \LOGICAL_OE \dec_LOGICAL_OE
connect \LOGICAL_internal_op \dec_LOGICAL_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124158.16-124163.4"
+ attribute \src "libresoc.v:123983.16-123988.4"
cell \dec_rc$146 \dec_rc
connect \LOGICAL_Rc \dec_LOGICAL_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:123647.7-123647.20"
- process $proc$libresoc.v:123647$4696
+ attribute \src "libresoc.v:123472.7-123472.20"
+ process $proc$libresoc.v:123472$4680
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124164.3-124178.6"
- process $proc$libresoc.v:124164$4693
+ attribute \src "libresoc.v:123989.3-124003.6"
+ process $proc$libresoc.v:123989$4677
assign { } { }
assign { } { }
assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:124165.5-124165.29"
+ attribute \src "libresoc.v:123990.5-123990.29"
switch \initial
- attribute \src "libresoc.v:124165.9-124165.17"
+ attribute \src "libresoc.v:123990.9-123990.17"
case 1'1
case
end
sync always
update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0]
end
- attribute \src "libresoc.v:124179.3-124191.6"
- process $proc$libresoc.v:124179$4694
+ attribute \src "libresoc.v:124004.3-124016.6"
+ process $proc$libresoc.v:124004$4678
assign { } { }
assign { } { }
assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:124180.5-124180.29"
+ attribute \src "libresoc.v:124005.5-124005.29"
switch \initial
- attribute \src "libresoc.v:124180.9-124180.17"
+ attribute \src "libresoc.v:124005.9-124005.17"
case 1'1
case
end
sync always
update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0]
end
- attribute \src "libresoc.v:124192.3-124206.6"
- process $proc$libresoc.v:124192$4695
+ attribute \src "libresoc.v:124017.3-124031.6"
+ process $proc$libresoc.v:124017$4679
assign { } { }
assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0]
- attribute \src "libresoc.v:124193.5-124193.29"
+ attribute \src "libresoc.v:124018.5-124018.29"
switch \initial
- attribute \src "libresoc.v:124193.9-124193.17"
+ attribute \src "libresoc.v:124018.9-124018.17"
case 1'1
case
end
sync always
update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:124080$4669_Y
- connect \$12 $not$libresoc.v:124081$4670_Y
- connect \$14 $and$libresoc.v:124082$4671_Y
- connect \$16 $eq$libresoc.v:124083$4672_Y
- connect \$18 $eq$libresoc.v:124084$4673_Y
- connect \$20 $or$libresoc.v:124085$4674_Y
- connect \$22 $eq$libresoc.v:124086$4675_Y
- connect \$24 $eq$libresoc.v:124087$4676_Y
- connect \$26 $or$libresoc.v:124088$4677_Y
- connect \$28 $eq$libresoc.v:124089$4678_Y
- connect \$2 $eq$libresoc.v:124090$4679_Y
- connect \$30 $or$libresoc.v:124091$4680_Y
- connect \$32 $eq$libresoc.v:124092$4681_Y
- connect \$34 $or$libresoc.v:124093$4682_Y
- connect \$36 $eq$libresoc.v:124094$4683_Y
- connect \$38 $and$libresoc.v:124095$4684_Y
- connect \$40 $and$libresoc.v:124096$4685_Y
- connect \$42 $eq$libresoc.v:124097$4686_Y
- connect \$44 $and$libresoc.v:124098$4687_Y
- connect \$46 $not$libresoc.v:124099$4688_Y
- connect \$48 $and$libresoc.v:124100$4689_Y
- connect \$4 $and$libresoc.v:124101$4690_Y
- connect \$6 $and$libresoc.v:124102$4691_Y
- connect \$8 $eq$libresoc.v:124103$4692_Y
+ connect \$10 $and$libresoc.v:123905$4653_Y
+ connect \$12 $not$libresoc.v:123906$4654_Y
+ connect \$14 $and$libresoc.v:123907$4655_Y
+ connect \$16 $eq$libresoc.v:123908$4656_Y
+ connect \$18 $eq$libresoc.v:123909$4657_Y
+ connect \$20 $or$libresoc.v:123910$4658_Y
+ connect \$22 $eq$libresoc.v:123911$4659_Y
+ connect \$24 $eq$libresoc.v:123912$4660_Y
+ connect \$26 $or$libresoc.v:123913$4661_Y
+ connect \$28 $eq$libresoc.v:123914$4662_Y
+ connect \$2 $eq$libresoc.v:123915$4663_Y
+ connect \$30 $or$libresoc.v:123916$4664_Y
+ connect \$32 $eq$libresoc.v:123917$4665_Y
+ connect \$34 $or$libresoc.v:123918$4666_Y
+ connect \$36 $eq$libresoc.v:123919$4667_Y
+ connect \$38 $and$libresoc.v:123920$4668_Y
+ connect \$40 $and$libresoc.v:123921$4669_Y
+ connect \$42 $eq$libresoc.v:123922$4670_Y
+ connect \$44 $and$libresoc.v:123923$4671_Y
+ connect \$46 $not$libresoc.v:123924$4672_Y
+ connect \$48 $and$libresoc.v:123925$4673_Y
+ connect \$4 $and$libresoc.v:123926$4674_Y
+ connect \$6 $and$libresoc.v:123927$4675_Y
+ connect \$8 $eq$libresoc.v:123928$4676_Y
connect \LOGICAL__is_signed \dec_LOGICAL_sgn
connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b
connect \LOGICAL__output_carry \dec_LOGICAL_cry_out
connect \insn_in \dec_opcode_in
connect \LOGICAL__insn \dec_opcode_in
end
-attribute \src "libresoc.v:124233.1-124735.10"
+attribute \src "libresoc.v:124058.1-124560.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL"
attribute \generator "nMigen"
module \dec_MUL
- attribute \src "libresoc.v:124706.3-124720.6"
+ attribute \src "libresoc.v:124531.3-124545.6"
wire width 14 $0\MUL__fn_unit[13:0]
- attribute \src "libresoc.v:124693.3-124705.6"
+ attribute \src "libresoc.v:124518.3-124530.6"
wire width 7 $0\MUL__insn_type[6:0]
- attribute \src "libresoc.v:124678.3-124692.6"
+ attribute \src "libresoc.v:124503.3-124517.6"
wire $0\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:124234.7-124234.20"
+ attribute \src "libresoc.v:124059.7-124059.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124706.3-124720.6"
+ attribute \src "libresoc.v:124531.3-124545.6"
wire width 14 $1\MUL__fn_unit[13:0]
- attribute \src "libresoc.v:124693.3-124705.6"
+ attribute \src "libresoc.v:124518.3-124530.6"
wire width 7 $1\MUL__insn_type[6:0]
- attribute \src "libresoc.v:124678.3-124692.6"
+ attribute \src "libresoc.v:124503.3-124517.6"
wire $1\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:124607.18-124607.113"
- wire $and$libresoc.v:124607$4697_Y
- attribute \src "libresoc.v:124609.18-124609.110"
- wire $and$libresoc.v:124609$4699_Y
- attribute \src "libresoc.v:124622.18-124622.114"
- wire $and$libresoc.v:124622$4712_Y
- attribute \src "libresoc.v:124623.18-124623.116"
- wire $and$libresoc.v:124623$4713_Y
- attribute \src "libresoc.v:124625.18-124625.114"
- wire $and$libresoc.v:124625$4715_Y
- attribute \src "libresoc.v:124627.18-124627.110"
- wire $and$libresoc.v:124627$4717_Y
- attribute \src "libresoc.v:124628.17-124628.112"
- wire $and$libresoc.v:124628$4718_Y
- attribute \src "libresoc.v:124629.17-124629.114"
- wire $and$libresoc.v:124629$4719_Y
- attribute \src "libresoc.v:124610.18-124610.126"
- wire $eq$libresoc.v:124610$4700_Y
- attribute \src "libresoc.v:124611.18-124611.126"
- wire $eq$libresoc.v:124611$4701_Y
- attribute \src "libresoc.v:124613.18-124613.110"
- wire $eq$libresoc.v:124613$4703_Y
- attribute \src "libresoc.v:124614.18-124614.110"
- wire $eq$libresoc.v:124614$4704_Y
- attribute \src "libresoc.v:124616.18-124616.112"
- wire $eq$libresoc.v:124616$4706_Y
- attribute \src "libresoc.v:124617.17-124617.130"
- wire $eq$libresoc.v:124617$4707_Y
- attribute \src "libresoc.v:124619.18-124619.110"
- wire $eq$libresoc.v:124619$4709_Y
- attribute \src "libresoc.v:124621.18-124621.131"
- wire $eq$libresoc.v:124621$4711_Y
- attribute \src "libresoc.v:124624.18-124624.131"
- wire $eq$libresoc.v:124624$4714_Y
- attribute \src "libresoc.v:124630.17-124630.130"
- wire $eq$libresoc.v:124630$4720_Y
- attribute \src "libresoc.v:124608.18-124608.110"
- wire $not$libresoc.v:124608$4698_Y
- attribute \src "libresoc.v:124626.18-124626.110"
- wire $not$libresoc.v:124626$4716_Y
- attribute \src "libresoc.v:124612.18-124612.110"
- wire $or$libresoc.v:124612$4702_Y
- attribute \src "libresoc.v:124615.18-124615.110"
- wire $or$libresoc.v:124615$4705_Y
- attribute \src "libresoc.v:124618.18-124618.110"
- wire $or$libresoc.v:124618$4708_Y
- attribute \src "libresoc.v:124620.18-124620.110"
- wire $or$libresoc.v:124620$4710_Y
+ attribute \src "libresoc.v:124432.18-124432.113"
+ wire $and$libresoc.v:124432$4681_Y
+ attribute \src "libresoc.v:124434.18-124434.110"
+ wire $and$libresoc.v:124434$4683_Y
+ attribute \src "libresoc.v:124447.18-124447.114"
+ wire $and$libresoc.v:124447$4696_Y
+ attribute \src "libresoc.v:124448.18-124448.116"
+ wire $and$libresoc.v:124448$4697_Y
+ attribute \src "libresoc.v:124450.18-124450.114"
+ wire $and$libresoc.v:124450$4699_Y
+ attribute \src "libresoc.v:124452.18-124452.110"
+ wire $and$libresoc.v:124452$4701_Y
+ attribute \src "libresoc.v:124453.17-124453.112"
+ wire $and$libresoc.v:124453$4702_Y
+ attribute \src "libresoc.v:124454.17-124454.114"
+ wire $and$libresoc.v:124454$4703_Y
+ attribute \src "libresoc.v:124435.18-124435.126"
+ wire $eq$libresoc.v:124435$4684_Y
+ attribute \src "libresoc.v:124436.18-124436.126"
+ wire $eq$libresoc.v:124436$4685_Y
+ attribute \src "libresoc.v:124438.18-124438.110"
+ wire $eq$libresoc.v:124438$4687_Y
+ attribute \src "libresoc.v:124439.18-124439.110"
+ wire $eq$libresoc.v:124439$4688_Y
+ attribute \src "libresoc.v:124441.18-124441.112"
+ wire $eq$libresoc.v:124441$4690_Y
+ attribute \src "libresoc.v:124442.17-124442.130"
+ wire $eq$libresoc.v:124442$4691_Y
+ attribute \src "libresoc.v:124444.18-124444.110"
+ wire $eq$libresoc.v:124444$4693_Y
+ attribute \src "libresoc.v:124446.18-124446.131"
+ wire $eq$libresoc.v:124446$4695_Y
+ attribute \src "libresoc.v:124449.18-124449.131"
+ wire $eq$libresoc.v:124449$4698_Y
+ attribute \src "libresoc.v:124455.17-124455.130"
+ wire $eq$libresoc.v:124455$4704_Y
+ attribute \src "libresoc.v:124433.18-124433.110"
+ wire $not$libresoc.v:124433$4682_Y
+ attribute \src "libresoc.v:124451.18-124451.110"
+ wire $not$libresoc.v:124451$4700_Y
+ attribute \src "libresoc.v:124437.18-124437.110"
+ wire $or$libresoc.v:124437$4686_Y
+ attribute \src "libresoc.v:124440.18-124440.110"
+ wire $or$libresoc.v:124440$4689_Y
+ attribute \src "libresoc.v:124443.18-124443.110"
+ wire $or$libresoc.v:124443$4692_Y
+ attribute \src "libresoc.v:124445.18-124445.110"
+ wire $or$libresoc.v:124445$4694_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:124234.7-124234.15"
+ attribute \src "libresoc.v:124059.7-124059.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124607$4697
+ cell $and $and$libresoc.v:124432$4681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:124607$4697_Y
+ connect \Y $and$libresoc.v:124432$4681_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124609$4699
+ cell $and $and$libresoc.v:124434$4683
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:124609$4699_Y
+ connect \Y $and$libresoc.v:124434$4683_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124622$4712
+ cell $and $and$libresoc.v:124447$4696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:124622$4712_Y
+ connect \Y $and$libresoc.v:124447$4696_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124623$4713
+ cell $and $and$libresoc.v:124448$4697
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:124623$4713_Y
+ connect \Y $and$libresoc.v:124448$4697_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124625$4715
+ cell $and $and$libresoc.v:124450$4699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:124625$4715_Y
+ connect \Y $and$libresoc.v:124450$4699_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:124627$4717
+ cell $and $and$libresoc.v:124452$4701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:124627$4717_Y
+ connect \Y $and$libresoc.v:124452$4701_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124628$4718
+ cell $and $and$libresoc.v:124453$4702
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:124628$4718_Y
+ connect \Y $and$libresoc.v:124453$4702_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:124629$4719
+ cell $and $and$libresoc.v:124454$4703
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:124629$4719_Y
+ connect \Y $and$libresoc.v:124454$4703_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:124610$4700
+ cell $eq $eq$libresoc.v:124435$4684
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:124610$4700_Y
+ connect \Y $eq$libresoc.v:124435$4684_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:124611$4701
+ cell $eq $eq$libresoc.v:124436$4685
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:124611$4701_Y
+ connect \Y $eq$libresoc.v:124436$4685_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124613$4703
+ cell $eq $eq$libresoc.v:124438$4687
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:124613$4703_Y
+ connect \Y $eq$libresoc.v:124438$4687_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124614$4704
+ cell $eq $eq$libresoc.v:124439$4688
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:124614$4704_Y
+ connect \Y $eq$libresoc.v:124439$4688_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:124616$4706
+ cell $eq $eq$libresoc.v:124441$4690
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:124616$4706_Y
+ connect \Y $eq$libresoc.v:124441$4690_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:124617$4707
+ cell $eq $eq$libresoc.v:124442$4691
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:124617$4707_Y
+ connect \Y $eq$libresoc.v:124442$4691_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:124619$4709
+ cell $eq $eq$libresoc.v:124444$4693
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:124619$4709_Y
+ connect \Y $eq$libresoc.v:124444$4693_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:124621$4711
+ cell $eq $eq$libresoc.v:124446$4695
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:124621$4711_Y
+ connect \Y $eq$libresoc.v:124446$4695_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:124624$4714
+ cell $eq $eq$libresoc.v:124449$4698
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:124624$4714_Y
+ connect \Y $eq$libresoc.v:124449$4698_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:124630$4720
+ cell $eq $eq$libresoc.v:124455$4704
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:124630$4720_Y
+ connect \Y $eq$libresoc.v:124455$4704_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:124608$4698
+ cell $not $not$libresoc.v:124433$4682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:124608$4698_Y
+ connect \Y $not$libresoc.v:124433$4682_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:124626$4716
+ cell $not $not$libresoc.v:124451$4700
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:124626$4716_Y
+ connect \Y $not$libresoc.v:124451$4700_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:124612$4702
+ cell $or $or$libresoc.v:124437$4686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:124612$4702_Y
+ connect \Y $or$libresoc.v:124437$4686_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:124615$4705
+ cell $or $or$libresoc.v:124440$4689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:124615$4705_Y
+ connect \Y $or$libresoc.v:124440$4689_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:124618$4708
+ cell $or $or$libresoc.v:124443$4692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:124618$4708_Y
+ connect \Y $or$libresoc.v:124443$4692_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:124620$4710
+ cell $or $or$libresoc.v:124445$4694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:124620$4710_Y
+ connect \Y $or$libresoc.v:124445$4694_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124631.13-124652.4"
+ attribute \src "libresoc.v:124456.13-124477.4"
cell \dec$158 \dec
connect \MUL_BD \dec_MUL_BD
connect \MUL_DS \dec_MUL_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124653.16-124664.4"
+ attribute \src "libresoc.v:124478.16-124489.4"
cell \dec_bi$161 \dec_bi
connect \MUL_BD \dec_MUL_BD
connect \MUL_DS \dec_MUL_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124665.16-124671.4"
+ attribute \src "libresoc.v:124490.16-124496.4"
cell \dec_oe$160 \dec_oe
connect \MUL_OE \dec_MUL_OE
connect \MUL_internal_op \dec_MUL_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124672.16-124677.4"
+ attribute \src "libresoc.v:124497.16-124502.4"
cell \dec_rc$159 \dec_rc
connect \MUL_Rc \dec_MUL_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:124234.7-124234.20"
- process $proc$libresoc.v:124234$4724
+ attribute \src "libresoc.v:124059.7-124059.20"
+ process $proc$libresoc.v:124059$4708
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124678.3-124692.6"
- process $proc$libresoc.v:124678$4721
+ attribute \src "libresoc.v:124503.3-124517.6"
+ process $proc$libresoc.v:124503$4705
assign { } { }
assign { } { }
assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:124679.5-124679.29"
+ attribute \src "libresoc.v:124504.5-124504.29"
switch \initial
- attribute \src "libresoc.v:124679.9-124679.17"
+ attribute \src "libresoc.v:124504.9-124504.17"
case 1'1
case
end
sync always
update \MUL__write_cr0 $0\MUL__write_cr0[0:0]
end
- attribute \src "libresoc.v:124693.3-124705.6"
- process $proc$libresoc.v:124693$4722
+ attribute \src "libresoc.v:124518.3-124530.6"
+ process $proc$libresoc.v:124518$4706
assign { } { }
assign { } { }
assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0]
- attribute \src "libresoc.v:124694.5-124694.29"
+ attribute \src "libresoc.v:124519.5-124519.29"
switch \initial
- attribute \src "libresoc.v:124694.9-124694.17"
+ attribute \src "libresoc.v:124519.9-124519.17"
case 1'1
case
end
sync always
update \MUL__insn_type $0\MUL__insn_type[6:0]
end
- attribute \src "libresoc.v:124706.3-124720.6"
- process $proc$libresoc.v:124706$4723
+ attribute \src "libresoc.v:124531.3-124545.6"
+ process $proc$libresoc.v:124531$4707
assign { } { }
assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0]
- attribute \src "libresoc.v:124707.5-124707.29"
+ attribute \src "libresoc.v:124532.5-124532.29"
switch \initial
- attribute \src "libresoc.v:124707.9-124707.17"
+ attribute \src "libresoc.v:124532.9-124532.17"
case 1'1
case
end
sync always
update \MUL__fn_unit $0\MUL__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:124607$4697_Y
- connect \$12 $not$libresoc.v:124608$4698_Y
- connect \$14 $and$libresoc.v:124609$4699_Y
- connect \$16 $eq$libresoc.v:124610$4700_Y
- connect \$18 $eq$libresoc.v:124611$4701_Y
- connect \$20 $or$libresoc.v:124612$4702_Y
- connect \$22 $eq$libresoc.v:124613$4703_Y
- connect \$24 $eq$libresoc.v:124614$4704_Y
- connect \$26 $or$libresoc.v:124615$4705_Y
- connect \$28 $eq$libresoc.v:124616$4706_Y
- connect \$2 $eq$libresoc.v:124617$4707_Y
- connect \$30 $or$libresoc.v:124618$4708_Y
- connect \$32 $eq$libresoc.v:124619$4709_Y
- connect \$34 $or$libresoc.v:124620$4710_Y
- connect \$36 $eq$libresoc.v:124621$4711_Y
- connect \$38 $and$libresoc.v:124622$4712_Y
- connect \$40 $and$libresoc.v:124623$4713_Y
- connect \$42 $eq$libresoc.v:124624$4714_Y
- connect \$44 $and$libresoc.v:124625$4715_Y
- connect \$46 $not$libresoc.v:124626$4716_Y
- connect \$48 $and$libresoc.v:124627$4717_Y
- connect \$4 $and$libresoc.v:124628$4718_Y
- connect \$6 $and$libresoc.v:124629$4719_Y
- connect \$8 $eq$libresoc.v:124630$4720_Y
+ connect \$10 $and$libresoc.v:124432$4681_Y
+ connect \$12 $not$libresoc.v:124433$4682_Y
+ connect \$14 $and$libresoc.v:124434$4683_Y
+ connect \$16 $eq$libresoc.v:124435$4684_Y
+ connect \$18 $eq$libresoc.v:124436$4685_Y
+ connect \$20 $or$libresoc.v:124437$4686_Y
+ connect \$22 $eq$libresoc.v:124438$4687_Y
+ connect \$24 $eq$libresoc.v:124439$4688_Y
+ connect \$26 $or$libresoc.v:124440$4689_Y
+ connect \$28 $eq$libresoc.v:124441$4690_Y
+ connect \$2 $eq$libresoc.v:124442$4691_Y
+ connect \$30 $or$libresoc.v:124443$4692_Y
+ connect \$32 $eq$libresoc.v:124444$4693_Y
+ connect \$34 $or$libresoc.v:124445$4694_Y
+ connect \$36 $eq$libresoc.v:124446$4695_Y
+ connect \$38 $and$libresoc.v:124447$4696_Y
+ connect \$40 $and$libresoc.v:124448$4697_Y
+ connect \$42 $eq$libresoc.v:124449$4698_Y
+ connect \$44 $and$libresoc.v:124450$4699_Y
+ connect \$46 $not$libresoc.v:124451$4700_Y
+ connect \$48 $and$libresoc.v:124452$4701_Y
+ connect \$4 $and$libresoc.v:124453$4702_Y
+ connect \$6 $and$libresoc.v:124454$4703_Y
+ connect \$8 $eq$libresoc.v:124455$4704_Y
connect \MUL__is_signed \dec_MUL_sgn
connect \MUL__is_32bit \dec_MUL_is_32b
connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe }
connect \insn_in \dec_opcode_in
connect \MUL__insn \dec_opcode_in
end
-attribute \src "libresoc.v:124739.1-125285.10"
+attribute \src "libresoc.v:124564.1-125110.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT"
attribute \generator "nMigen"
module \dec_SHIFT_ROT
- attribute \src "libresoc.v:125251.3-125265.6"
+ attribute \src "libresoc.v:125076.3-125090.6"
wire width 14 $0\SHIFT_ROT__fn_unit[13:0]
- attribute \src "libresoc.v:125238.3-125250.6"
+ attribute \src "libresoc.v:125063.3-125075.6"
wire width 7 $0\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:125223.3-125237.6"
+ attribute \src "libresoc.v:125048.3-125062.6"
wire $0\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:124740.7-124740.20"
+ attribute \src "libresoc.v:124565.7-124565.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125251.3-125265.6"
+ attribute \src "libresoc.v:125076.3-125090.6"
wire width 14 $1\SHIFT_ROT__fn_unit[13:0]
- attribute \src "libresoc.v:125238.3-125250.6"
+ attribute \src "libresoc.v:125063.3-125075.6"
wire width 7 $1\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:125223.3-125237.6"
+ attribute \src "libresoc.v:125048.3-125062.6"
wire $1\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:125148.18-125148.113"
- wire $and$libresoc.v:125148$4725_Y
- attribute \src "libresoc.v:125150.18-125150.110"
- wire $and$libresoc.v:125150$4727_Y
- attribute \src "libresoc.v:125163.18-125163.114"
- wire $and$libresoc.v:125163$4740_Y
- attribute \src "libresoc.v:125164.18-125164.116"
- wire $and$libresoc.v:125164$4741_Y
- attribute \src "libresoc.v:125166.18-125166.114"
- wire $and$libresoc.v:125166$4743_Y
- attribute \src "libresoc.v:125168.18-125168.110"
- wire $and$libresoc.v:125168$4745_Y
- attribute \src "libresoc.v:125169.17-125169.112"
- wire $and$libresoc.v:125169$4746_Y
- attribute \src "libresoc.v:125170.17-125170.114"
- wire $and$libresoc.v:125170$4747_Y
- attribute \src "libresoc.v:125151.18-125151.132"
- wire $eq$libresoc.v:125151$4728_Y
- attribute \src "libresoc.v:125152.18-125152.132"
- wire $eq$libresoc.v:125152$4729_Y
- attribute \src "libresoc.v:125154.18-125154.110"
- wire $eq$libresoc.v:125154$4731_Y
- attribute \src "libresoc.v:125155.18-125155.110"
- wire $eq$libresoc.v:125155$4732_Y
- attribute \src "libresoc.v:125157.18-125157.112"
- wire $eq$libresoc.v:125157$4734_Y
- attribute \src "libresoc.v:125158.17-125158.136"
- wire $eq$libresoc.v:125158$4735_Y
- attribute \src "libresoc.v:125160.18-125160.110"
- wire $eq$libresoc.v:125160$4737_Y
- attribute \src "libresoc.v:125162.18-125162.137"
- wire $eq$libresoc.v:125162$4739_Y
- attribute \src "libresoc.v:125165.18-125165.137"
- wire $eq$libresoc.v:125165$4742_Y
- attribute \src "libresoc.v:125171.17-125171.136"
- wire $eq$libresoc.v:125171$4748_Y
- attribute \src "libresoc.v:125149.18-125149.110"
- wire $not$libresoc.v:125149$4726_Y
- attribute \src "libresoc.v:125167.18-125167.110"
- wire $not$libresoc.v:125167$4744_Y
- attribute \src "libresoc.v:125153.18-125153.110"
- wire $or$libresoc.v:125153$4730_Y
- attribute \src "libresoc.v:125156.18-125156.110"
- wire $or$libresoc.v:125156$4733_Y
- attribute \src "libresoc.v:125159.18-125159.110"
- wire $or$libresoc.v:125159$4736_Y
- attribute \src "libresoc.v:125161.18-125161.110"
- wire $or$libresoc.v:125161$4738_Y
+ attribute \src "libresoc.v:124973.18-124973.113"
+ wire $and$libresoc.v:124973$4709_Y
+ attribute \src "libresoc.v:124975.18-124975.110"
+ wire $and$libresoc.v:124975$4711_Y
+ attribute \src "libresoc.v:124988.18-124988.114"
+ wire $and$libresoc.v:124988$4724_Y
+ attribute \src "libresoc.v:124989.18-124989.116"
+ wire $and$libresoc.v:124989$4725_Y
+ attribute \src "libresoc.v:124991.18-124991.114"
+ wire $and$libresoc.v:124991$4727_Y
+ attribute \src "libresoc.v:124993.18-124993.110"
+ wire $and$libresoc.v:124993$4729_Y
+ attribute \src "libresoc.v:124994.17-124994.112"
+ wire $and$libresoc.v:124994$4730_Y
+ attribute \src "libresoc.v:124995.17-124995.114"
+ wire $and$libresoc.v:124995$4731_Y
+ attribute \src "libresoc.v:124976.18-124976.132"
+ wire $eq$libresoc.v:124976$4712_Y
+ attribute \src "libresoc.v:124977.18-124977.132"
+ wire $eq$libresoc.v:124977$4713_Y
+ attribute \src "libresoc.v:124979.18-124979.110"
+ wire $eq$libresoc.v:124979$4715_Y
+ attribute \src "libresoc.v:124980.18-124980.110"
+ wire $eq$libresoc.v:124980$4716_Y
+ attribute \src "libresoc.v:124982.18-124982.112"
+ wire $eq$libresoc.v:124982$4718_Y
+ attribute \src "libresoc.v:124983.17-124983.136"
+ wire $eq$libresoc.v:124983$4719_Y
+ attribute \src "libresoc.v:124985.18-124985.110"
+ wire $eq$libresoc.v:124985$4721_Y
+ attribute \src "libresoc.v:124987.18-124987.137"
+ wire $eq$libresoc.v:124987$4723_Y
+ attribute \src "libresoc.v:124990.18-124990.137"
+ wire $eq$libresoc.v:124990$4726_Y
+ attribute \src "libresoc.v:124996.17-124996.136"
+ wire $eq$libresoc.v:124996$4732_Y
+ attribute \src "libresoc.v:124974.18-124974.110"
+ wire $not$libresoc.v:124974$4710_Y
+ attribute \src "libresoc.v:124992.18-124992.110"
+ wire $not$libresoc.v:124992$4728_Y
+ attribute \src "libresoc.v:124978.18-124978.110"
+ wire $or$libresoc.v:124978$4714_Y
+ attribute \src "libresoc.v:124981.18-124981.110"
+ wire $or$libresoc.v:124981$4717_Y
+ attribute \src "libresoc.v:124984.18-124984.110"
+ wire $or$libresoc.v:124984$4720_Y
+ attribute \src "libresoc.v:124986.18-124986.110"
+ wire $or$libresoc.v:124986$4722_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:124740.7-124740.15"
+ attribute \src "libresoc.v:124565.7-124565.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125148$4725
+ cell $and $and$libresoc.v:124973$4709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:125148$4725_Y
+ connect \Y $and$libresoc.v:124973$4709_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125150$4727
+ cell $and $and$libresoc.v:124975$4711
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:125150$4727_Y
+ connect \Y $and$libresoc.v:124975$4711_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125163$4740
+ cell $and $and$libresoc.v:124988$4724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:125163$4740_Y
+ connect \Y $and$libresoc.v:124988$4724_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125164$4741
+ cell $and $and$libresoc.v:124989$4725
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:125164$4741_Y
+ connect \Y $and$libresoc.v:124989$4725_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125166$4743
+ cell $and $and$libresoc.v:124991$4727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:125166$4743_Y
+ connect \Y $and$libresoc.v:124991$4727_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125168$4745
+ cell $and $and$libresoc.v:124993$4729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:125168$4745_Y
+ connect \Y $and$libresoc.v:124993$4729_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125169$4746
+ cell $and $and$libresoc.v:124994$4730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:125169$4746_Y
+ connect \Y $and$libresoc.v:124994$4730_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125170$4747
+ cell $and $and$libresoc.v:124995$4731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:125170$4747_Y
+ connect \Y $and$libresoc.v:124995$4731_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:125151$4728
+ cell $eq $eq$libresoc.v:124976$4712
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:125151$4728_Y
+ connect \Y $eq$libresoc.v:124976$4712_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:125152$4729
+ cell $eq $eq$libresoc.v:124977$4713
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:125152$4729_Y
+ connect \Y $eq$libresoc.v:124977$4713_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125154$4731
+ cell $eq $eq$libresoc.v:124979$4715
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:125154$4731_Y
+ connect \Y $eq$libresoc.v:124979$4715_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125155$4732
+ cell $eq $eq$libresoc.v:124980$4716
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:125155$4732_Y
+ connect \Y $eq$libresoc.v:124980$4716_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125157$4734
+ cell $eq $eq$libresoc.v:124982$4718
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:125157$4734_Y
+ connect \Y $eq$libresoc.v:124982$4718_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:125158$4735
+ cell $eq $eq$libresoc.v:124983$4719
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:125158$4735_Y
+ connect \Y $eq$libresoc.v:124983$4719_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:125160$4737
+ cell $eq $eq$libresoc.v:124985$4721
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:125160$4737_Y
+ connect \Y $eq$libresoc.v:124985$4721_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:125162$4739
+ cell $eq $eq$libresoc.v:124987$4723
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:125162$4739_Y
+ connect \Y $eq$libresoc.v:124987$4723_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:125165$4742
+ cell $eq $eq$libresoc.v:124990$4726
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:125165$4742_Y
+ connect \Y $eq$libresoc.v:124990$4726_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:125171$4748
+ cell $eq $eq$libresoc.v:124996$4732
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:125171$4748_Y
+ connect \Y $eq$libresoc.v:124996$4732_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:125149$4726
+ cell $not $not$libresoc.v:124974$4710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:125149$4726_Y
+ connect \Y $not$libresoc.v:124974$4710_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:125167$4744
+ cell $not $not$libresoc.v:124992$4728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:125167$4744_Y
+ connect \Y $not$libresoc.v:124992$4728_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:125153$4730
+ cell $or $or$libresoc.v:124978$4714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:125153$4730_Y
+ connect \Y $or$libresoc.v:124978$4714_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:125156$4733
+ cell $or $or$libresoc.v:124981$4717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:125156$4733_Y
+ connect \Y $or$libresoc.v:124981$4717_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:125159$4736
+ cell $or $or$libresoc.v:124984$4720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:125159$4736_Y
+ connect \Y $or$libresoc.v:124984$4720_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:125161$4738
+ cell $or $or$libresoc.v:124986$4722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:125161$4738_Y
+ connect \Y $or$libresoc.v:124986$4722_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125172.13-125197.4"
+ attribute \src "libresoc.v:124997.13-125022.4"
cell \dec$162 \dec
connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD
connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125198.16-125209.4"
+ attribute \src "libresoc.v:125023.16-125034.4"
cell \dec_bi$165 \dec_bi
connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD
connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125210.16-125216.4"
+ attribute \src "libresoc.v:125035.16-125041.4"
cell \dec_oe$164 \dec_oe
connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE
connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125217.16-125222.4"
+ attribute \src "libresoc.v:125042.16-125047.4"
cell \dec_rc$163 \dec_rc
connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:124740.7-124740.20"
- process $proc$libresoc.v:124740$4752
+ attribute \src "libresoc.v:124565.7-124565.20"
+ process $proc$libresoc.v:124565$4736
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125223.3-125237.6"
- process $proc$libresoc.v:125223$4749
+ attribute \src "libresoc.v:125048.3-125062.6"
+ process $proc$libresoc.v:125048$4733
assign { } { }
assign { } { }
assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:125224.5-125224.29"
+ attribute \src "libresoc.v:125049.5-125049.29"
switch \initial
- attribute \src "libresoc.v:125224.9-125224.17"
+ attribute \src "libresoc.v:125049.9-125049.17"
case 1'1
case
end
sync always
update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0]
end
- attribute \src "libresoc.v:125238.3-125250.6"
- process $proc$libresoc.v:125238$4750
+ attribute \src "libresoc.v:125063.3-125075.6"
+ process $proc$libresoc.v:125063$4734
assign { } { }
assign { } { }
assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:125239.5-125239.29"
+ attribute \src "libresoc.v:125064.5-125064.29"
switch \initial
- attribute \src "libresoc.v:125239.9-125239.17"
+ attribute \src "libresoc.v:125064.9-125064.17"
case 1'1
case
end
sync always
update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0]
end
- attribute \src "libresoc.v:125251.3-125265.6"
- process $proc$libresoc.v:125251$4751
+ attribute \src "libresoc.v:125076.3-125090.6"
+ process $proc$libresoc.v:125076$4735
assign { } { }
assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0]
- attribute \src "libresoc.v:125252.5-125252.29"
+ attribute \src "libresoc.v:125077.5-125077.29"
switch \initial
- attribute \src "libresoc.v:125252.9-125252.17"
+ attribute \src "libresoc.v:125077.9-125077.17"
case 1'1
case
end
sync always
update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:125148$4725_Y
- connect \$12 $not$libresoc.v:125149$4726_Y
- connect \$14 $and$libresoc.v:125150$4727_Y
- connect \$16 $eq$libresoc.v:125151$4728_Y
- connect \$18 $eq$libresoc.v:125152$4729_Y
- connect \$20 $or$libresoc.v:125153$4730_Y
- connect \$22 $eq$libresoc.v:125154$4731_Y
- connect \$24 $eq$libresoc.v:125155$4732_Y
- connect \$26 $or$libresoc.v:125156$4733_Y
- connect \$28 $eq$libresoc.v:125157$4734_Y
- connect \$2 $eq$libresoc.v:125158$4735_Y
- connect \$30 $or$libresoc.v:125159$4736_Y
- connect \$32 $eq$libresoc.v:125160$4737_Y
- connect \$34 $or$libresoc.v:125161$4738_Y
- connect \$36 $eq$libresoc.v:125162$4739_Y
- connect \$38 $and$libresoc.v:125163$4740_Y
- connect \$40 $and$libresoc.v:125164$4741_Y
- connect \$42 $eq$libresoc.v:125165$4742_Y
- connect \$44 $and$libresoc.v:125166$4743_Y
- connect \$46 $not$libresoc.v:125167$4744_Y
- connect \$48 $and$libresoc.v:125168$4745_Y
- connect \$4 $and$libresoc.v:125169$4746_Y
- connect \$6 $and$libresoc.v:125170$4747_Y
- connect \$8 $eq$libresoc.v:125171$4748_Y
+ connect \$10 $and$libresoc.v:124973$4709_Y
+ connect \$12 $not$libresoc.v:124974$4710_Y
+ connect \$14 $and$libresoc.v:124975$4711_Y
+ connect \$16 $eq$libresoc.v:124976$4712_Y
+ connect \$18 $eq$libresoc.v:124977$4713_Y
+ connect \$20 $or$libresoc.v:124978$4714_Y
+ connect \$22 $eq$libresoc.v:124979$4715_Y
+ connect \$24 $eq$libresoc.v:124980$4716_Y
+ connect \$26 $or$libresoc.v:124981$4717_Y
+ connect \$28 $eq$libresoc.v:124982$4718_Y
+ connect \$2 $eq$libresoc.v:124983$4719_Y
+ connect \$30 $or$libresoc.v:124984$4720_Y
+ connect \$32 $eq$libresoc.v:124985$4721_Y
+ connect \$34 $or$libresoc.v:124986$4722_Y
+ connect \$36 $eq$libresoc.v:124987$4723_Y
+ connect \$38 $and$libresoc.v:124988$4724_Y
+ connect \$40 $and$libresoc.v:124989$4725_Y
+ connect \$42 $eq$libresoc.v:124990$4726_Y
+ connect \$44 $and$libresoc.v:124991$4727_Y
+ connect \$46 $not$libresoc.v:124992$4728_Y
+ connect \$48 $and$libresoc.v:124993$4729_Y
+ connect \$4 $and$libresoc.v:124994$4730_Y
+ connect \$6 $and$libresoc.v:124995$4731_Y
+ connect \$8 $eq$libresoc.v:124996$4732_Y
connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn
connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b
connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out
connect \insn_in \dec_opcode_in
connect \SHIFT_ROT__insn \dec_opcode_in
end
-attribute \src "libresoc.v:125289.1-125667.10"
+attribute \src "libresoc.v:125114.1-125492.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR"
attribute \generator "nMigen"
module \dec_SPR
- attribute \src "libresoc.v:125643.3-125657.6"
+ attribute \src "libresoc.v:125468.3-125482.6"
wire width 14 $0\SPR__fn_unit[13:0]
- attribute \src "libresoc.v:125630.3-125642.6"
+ attribute \src "libresoc.v:125455.3-125467.6"
wire width 7 $0\SPR__insn_type[6:0]
- attribute \src "libresoc.v:125290.7-125290.20"
+ attribute \src "libresoc.v:125115.7-125115.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125643.3-125657.6"
+ attribute \src "libresoc.v:125468.3-125482.6"
wire width 14 $1\SPR__fn_unit[13:0]
- attribute \src "libresoc.v:125630.3-125642.6"
+ attribute \src "libresoc.v:125455.3-125467.6"
wire width 7 $1\SPR__insn_type[6:0]
- attribute \src "libresoc.v:125584.18-125584.113"
- wire $and$libresoc.v:125584$4753_Y
- attribute \src "libresoc.v:125586.18-125586.110"
- wire $and$libresoc.v:125586$4755_Y
- attribute \src "libresoc.v:125599.18-125599.114"
- wire $and$libresoc.v:125599$4768_Y
- attribute \src "libresoc.v:125600.18-125600.116"
- wire $and$libresoc.v:125600$4769_Y
- attribute \src "libresoc.v:125602.18-125602.114"
- wire $and$libresoc.v:125602$4771_Y
- attribute \src "libresoc.v:125604.18-125604.110"
- wire $and$libresoc.v:125604$4773_Y
- attribute \src "libresoc.v:125605.17-125605.112"
- wire $and$libresoc.v:125605$4774_Y
- attribute \src "libresoc.v:125606.17-125606.114"
- wire $and$libresoc.v:125606$4775_Y
- attribute \src "libresoc.v:125587.18-125587.126"
- wire $eq$libresoc.v:125587$4756_Y
- attribute \src "libresoc.v:125588.18-125588.126"
- wire $eq$libresoc.v:125588$4757_Y
- attribute \src "libresoc.v:125590.18-125590.110"
- wire $eq$libresoc.v:125590$4759_Y
- attribute \src "libresoc.v:125591.18-125591.110"
- wire $eq$libresoc.v:125591$4760_Y
- attribute \src "libresoc.v:125593.18-125593.112"
- wire $eq$libresoc.v:125593$4762_Y
- attribute \src "libresoc.v:125594.17-125594.130"
- wire $eq$libresoc.v:125594$4763_Y
- attribute \src "libresoc.v:125596.18-125596.110"
- wire $eq$libresoc.v:125596$4765_Y
- attribute \src "libresoc.v:125598.18-125598.131"
- wire $eq$libresoc.v:125598$4767_Y
- attribute \src "libresoc.v:125601.18-125601.131"
- wire $eq$libresoc.v:125601$4770_Y
- attribute \src "libresoc.v:125607.17-125607.130"
- wire $eq$libresoc.v:125607$4776_Y
- attribute \src "libresoc.v:125585.18-125585.110"
- wire $not$libresoc.v:125585$4754_Y
- attribute \src "libresoc.v:125603.18-125603.110"
- wire $not$libresoc.v:125603$4772_Y
- attribute \src "libresoc.v:125589.18-125589.110"
- wire $or$libresoc.v:125589$4758_Y
- attribute \src "libresoc.v:125592.18-125592.110"
- wire $or$libresoc.v:125592$4761_Y
- attribute \src "libresoc.v:125595.18-125595.110"
- wire $or$libresoc.v:125595$4764_Y
- attribute \src "libresoc.v:125597.18-125597.110"
- wire $or$libresoc.v:125597$4766_Y
+ attribute \src "libresoc.v:125409.18-125409.113"
+ wire $and$libresoc.v:125409$4737_Y
+ attribute \src "libresoc.v:125411.18-125411.110"
+ wire $and$libresoc.v:125411$4739_Y
+ attribute \src "libresoc.v:125424.18-125424.114"
+ wire $and$libresoc.v:125424$4752_Y
+ attribute \src "libresoc.v:125425.18-125425.116"
+ wire $and$libresoc.v:125425$4753_Y
+ attribute \src "libresoc.v:125427.18-125427.114"
+ wire $and$libresoc.v:125427$4755_Y
+ attribute \src "libresoc.v:125429.18-125429.110"
+ wire $and$libresoc.v:125429$4757_Y
+ attribute \src "libresoc.v:125430.17-125430.112"
+ wire $and$libresoc.v:125430$4758_Y
+ attribute \src "libresoc.v:125431.17-125431.114"
+ wire $and$libresoc.v:125431$4759_Y
+ attribute \src "libresoc.v:125412.18-125412.126"
+ wire $eq$libresoc.v:125412$4740_Y
+ attribute \src "libresoc.v:125413.18-125413.126"
+ wire $eq$libresoc.v:125413$4741_Y
+ attribute \src "libresoc.v:125415.18-125415.110"
+ wire $eq$libresoc.v:125415$4743_Y
+ attribute \src "libresoc.v:125416.18-125416.110"
+ wire $eq$libresoc.v:125416$4744_Y
+ attribute \src "libresoc.v:125418.18-125418.112"
+ wire $eq$libresoc.v:125418$4746_Y
+ attribute \src "libresoc.v:125419.17-125419.130"
+ wire $eq$libresoc.v:125419$4747_Y
+ attribute \src "libresoc.v:125421.18-125421.110"
+ wire $eq$libresoc.v:125421$4749_Y
+ attribute \src "libresoc.v:125423.18-125423.131"
+ wire $eq$libresoc.v:125423$4751_Y
+ attribute \src "libresoc.v:125426.18-125426.131"
+ wire $eq$libresoc.v:125426$4754_Y
+ attribute \src "libresoc.v:125432.17-125432.130"
+ wire $eq$libresoc.v:125432$4760_Y
+ attribute \src "libresoc.v:125410.18-125410.110"
+ wire $not$libresoc.v:125410$4738_Y
+ attribute \src "libresoc.v:125428.18-125428.110"
+ wire $not$libresoc.v:125428$4756_Y
+ attribute \src "libresoc.v:125414.18-125414.110"
+ wire $or$libresoc.v:125414$4742_Y
+ attribute \src "libresoc.v:125417.18-125417.110"
+ wire $or$libresoc.v:125417$4745_Y
+ attribute \src "libresoc.v:125420.18-125420.110"
+ wire $or$libresoc.v:125420$4748_Y
+ attribute \src "libresoc.v:125422.18-125422.110"
+ wire $or$libresoc.v:125422$4750_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:125290.7-125290.15"
+ attribute \src "libresoc.v:125115.7-125115.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125584$4753
+ cell $and $and$libresoc.v:125409$4737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:125584$4753_Y
+ connect \Y $and$libresoc.v:125409$4737_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125586$4755
+ cell $and $and$libresoc.v:125411$4739
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:125586$4755_Y
+ connect \Y $and$libresoc.v:125411$4739_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125599$4768
+ cell $and $and$libresoc.v:125424$4752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:125599$4768_Y
+ connect \Y $and$libresoc.v:125424$4752_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125600$4769
+ cell $and $and$libresoc.v:125425$4753
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:125600$4769_Y
+ connect \Y $and$libresoc.v:125425$4753_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125602$4771
+ cell $and $and$libresoc.v:125427$4755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:125602$4771_Y
+ connect \Y $and$libresoc.v:125427$4755_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $and $and$libresoc.v:125604$4773
+ cell $and $and$libresoc.v:125429$4757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:125604$4773_Y
+ connect \Y $and$libresoc.v:125429$4757_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125605$4774
+ cell $and $and$libresoc.v:125430$4758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:125605$4774_Y
+ connect \Y $and$libresoc.v:125430$4758_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $and $and$libresoc.v:125606$4775
+ cell $and $and$libresoc.v:125431$4759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:125606$4775_Y
+ connect \Y $and$libresoc.v:125431$4759_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
- cell $eq $eq$libresoc.v:125587$4756
+ cell $eq $eq$libresoc.v:125412$4740
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:125587$4756_Y
+ connect \Y $eq$libresoc.v:125412$4740_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $eq $eq$libresoc.v:125588$4757
+ cell $eq $eq$libresoc.v:125413$4741
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:125588$4757_Y
+ connect \Y $eq$libresoc.v:125413$4741_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125590$4759
+ cell $eq $eq$libresoc.v:125415$4743
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:125590$4759_Y
+ connect \Y $eq$libresoc.v:125415$4743_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125591$4760
+ cell $eq $eq$libresoc.v:125416$4744
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:125591$4760_Y
+ connect \Y $eq$libresoc.v:125416$4744_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $eq $eq$libresoc.v:125593$4762
+ cell $eq $eq$libresoc.v:125418$4746
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:125593$4762_Y
+ connect \Y $eq$libresoc.v:125418$4746_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:125594$4763
+ cell $eq $eq$libresoc.v:125419$4747
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:125594$4763_Y
+ connect \Y $eq$libresoc.v:125419$4747_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $eq $eq$libresoc.v:125596$4765
+ cell $eq $eq$libresoc.v:125421$4749
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:125596$4765_Y
+ connect \Y $eq$libresoc.v:125421$4749_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
- cell $eq $eq$libresoc.v:125598$4767
+ cell $eq $eq$libresoc.v:125423$4751
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 14'00010000000000
- connect \Y $eq$libresoc.v:125598$4767_Y
+ connect \Y $eq$libresoc.v:125423$4751_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:125601$4770
+ cell $eq $eq$libresoc.v:125426$4754
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:125601$4770_Y
+ connect \Y $eq$libresoc.v:125426$4754_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $eq $eq$libresoc.v:125607$4776
+ cell $eq $eq$libresoc.v:125432$4760
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 14'00100000000000
- connect \Y $eq$libresoc.v:125607$4776_Y
+ connect \Y $eq$libresoc.v:125432$4760_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:125585$4754
+ cell $not $not$libresoc.v:125410$4738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:125585$4754_Y
+ connect \Y $not$libresoc.v:125410$4738_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
- cell $not $not$libresoc.v:125603$4772
+ cell $not $not$libresoc.v:125428$4756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:125603$4772_Y
+ connect \Y $not$libresoc.v:125428$4756_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
- cell $or $or$libresoc.v:125589$4758
+ cell $or $or$libresoc.v:125414$4742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:125589$4758_Y
+ connect \Y $or$libresoc.v:125414$4742_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:125592$4761
+ cell $or $or$libresoc.v:125417$4745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:125592$4761_Y
+ connect \Y $or$libresoc.v:125417$4745_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
- cell $or $or$libresoc.v:125595$4764
+ cell $or $or$libresoc.v:125420$4748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:125595$4764_Y
+ connect \Y $or$libresoc.v:125420$4748_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
- cell $or $or$libresoc.v:125597$4766
+ cell $or $or$libresoc.v:125422$4750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:125597$4766_Y
+ connect \Y $or$libresoc.v:125422$4750_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125608.13-125620.4"
+ attribute \src "libresoc.v:125433.13-125445.4"
cell \dec$150 \dec
connect \SPR_OE \dec_SPR_OE
connect \SPR_Rc \dec_SPR_Rc
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125621.16-125625.4"
+ attribute \src "libresoc.v:125446.16-125450.4"
cell \dec_oe$152 \dec_oe
connect \SPR_OE \dec_SPR_OE
connect \SPR_internal_op \dec_SPR_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:125626.16-125629.4"
+ attribute \src "libresoc.v:125451.16-125454.4"
cell \dec_rc$151 \dec_rc
connect \SPR_Rc \dec_SPR_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:125290.7-125290.20"
- process $proc$libresoc.v:125290$4779
+ attribute \src "libresoc.v:125115.7-125115.20"
+ process $proc$libresoc.v:125115$4763
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125630.3-125642.6"
- process $proc$libresoc.v:125630$4777
+ attribute \src "libresoc.v:125455.3-125467.6"
+ process $proc$libresoc.v:125455$4761
assign { } { }
assign { } { }
assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0]
- attribute \src "libresoc.v:125631.5-125631.29"
+ attribute \src "libresoc.v:125456.5-125456.29"
switch \initial
- attribute \src "libresoc.v:125631.9-125631.17"
+ attribute \src "libresoc.v:125456.9-125456.17"
case 1'1
case
end
sync always
update \SPR__insn_type $0\SPR__insn_type[6:0]
end
- attribute \src "libresoc.v:125643.3-125657.6"
- process $proc$libresoc.v:125643$4778
+ attribute \src "libresoc.v:125468.3-125482.6"
+ process $proc$libresoc.v:125468$4762
assign { } { }
assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0]
- attribute \src "libresoc.v:125644.5-125644.29"
+ attribute \src "libresoc.v:125469.5-125469.29"
switch \initial
- attribute \src "libresoc.v:125644.9-125644.17"
+ attribute \src "libresoc.v:125469.9-125469.17"
case 1'1
case
end
sync always
update \SPR__fn_unit $0\SPR__fn_unit[13:0]
end
- connect \$10 $and$libresoc.v:125584$4753_Y
- connect \$12 $not$libresoc.v:125585$4754_Y
- connect \$14 $and$libresoc.v:125586$4755_Y
- connect \$16 $eq$libresoc.v:125587$4756_Y
- connect \$18 $eq$libresoc.v:125588$4757_Y
- connect \$20 $or$libresoc.v:125589$4758_Y
- connect \$22 $eq$libresoc.v:125590$4759_Y
- connect \$24 $eq$libresoc.v:125591$4760_Y
- connect \$26 $or$libresoc.v:125592$4761_Y
- connect \$28 $eq$libresoc.v:125593$4762_Y
- connect \$2 $eq$libresoc.v:125594$4763_Y
- connect \$30 $or$libresoc.v:125595$4764_Y
- connect \$32 $eq$libresoc.v:125596$4765_Y
- connect \$34 $or$libresoc.v:125597$4766_Y
- connect \$36 $eq$libresoc.v:125598$4767_Y
- connect \$38 $and$libresoc.v:125599$4768_Y
- connect \$40 $and$libresoc.v:125600$4769_Y
- connect \$42 $eq$libresoc.v:125601$4770_Y
- connect \$44 $and$libresoc.v:125602$4771_Y
- connect \$46 $not$libresoc.v:125603$4772_Y
- connect \$48 $and$libresoc.v:125604$4773_Y
- connect \$4 $and$libresoc.v:125605$4774_Y
- connect \$6 $and$libresoc.v:125606$4775_Y
- connect \$8 $eq$libresoc.v:125607$4776_Y
+ connect \$10 $and$libresoc.v:125409$4737_Y
+ connect \$12 $not$libresoc.v:125410$4738_Y
+ connect \$14 $and$libresoc.v:125411$4739_Y
+ connect \$16 $eq$libresoc.v:125412$4740_Y
+ connect \$18 $eq$libresoc.v:125413$4741_Y
+ connect \$20 $or$libresoc.v:125414$4742_Y
+ connect \$22 $eq$libresoc.v:125415$4743_Y
+ connect \$24 $eq$libresoc.v:125416$4744_Y
+ connect \$26 $or$libresoc.v:125417$4745_Y
+ connect \$28 $eq$libresoc.v:125418$4746_Y
+ connect \$2 $eq$libresoc.v:125419$4747_Y
+ connect \$30 $or$libresoc.v:125420$4748_Y
+ connect \$32 $eq$libresoc.v:125421$4749_Y
+ connect \$34 $or$libresoc.v:125422$4750_Y
+ connect \$36 $eq$libresoc.v:125423$4751_Y
+ connect \$38 $and$libresoc.v:125424$4752_Y
+ connect \$40 $and$libresoc.v:125425$4753_Y
+ connect \$42 $eq$libresoc.v:125426$4754_Y
+ connect \$44 $and$libresoc.v:125427$4755_Y
+ connect \$46 $not$libresoc.v:125428$4756_Y
+ connect \$48 $and$libresoc.v:125429$4757_Y
+ connect \$4 $and$libresoc.v:125430$4758_Y
+ connect \$6 $and$libresoc.v:125431$4759_Y
+ connect \$8 $eq$libresoc.v:125432$4760_Y
connect \SPR__is_32bit \dec_SPR_is_32b
connect \is_mmu_spr \$34
connect \is_spr_mv \$20
connect \insn_in \dec_opcode_in
connect \SPR__insn \dec_opcode_in
end
-attribute \src "libresoc.v:125671.1-126224.10"
+attribute \src "libresoc.v:125496.1-126049.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a"
attribute \generator "nMigen"
module \dec_a
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire width 3 $0\fast_a[2:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire $0\fast_a_ok[0:0]
- attribute \src "libresoc.v:125672.7-125672.20"
+ attribute \src "libresoc.v:125497.7-125497.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126096.3-126111.6"
+ attribute \src "libresoc.v:125921.3-125936.6"
wire width 5 $0\reg_a[4:0]
- attribute \src "libresoc.v:126112.3-126127.6"
+ attribute \src "libresoc.v:125937.3-125952.6"
wire $0\reg_a_ok[0:0]
- attribute \src "libresoc.v:126164.3-126182.6"
+ attribute \src "libresoc.v:125989.3-126007.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:126202.3-126221.6"
+ attribute \src "libresoc.v:126027.3-126046.6"
wire width 10 $0\spr_a[9:0]
- attribute \src "libresoc.v:126202.3-126221.6"
+ attribute \src "libresoc.v:126027.3-126046.6"
wire $0\spr_a_ok[0:0]
- attribute \src "libresoc.v:126183.3-126201.6"
+ attribute \src "libresoc.v:126008.3-126026.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire width 3 $1\fast_a[2:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:126096.3-126111.6"
+ attribute \src "libresoc.v:125921.3-125936.6"
wire width 5 $1\reg_a[4:0]
- attribute \src "libresoc.v:126112.3-126127.6"
+ attribute \src "libresoc.v:125937.3-125952.6"
wire $1\reg_a_ok[0:0]
- attribute \src "libresoc.v:126164.3-126182.6"
+ attribute \src "libresoc.v:125989.3-126007.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:126202.3-126221.6"
+ attribute \src "libresoc.v:126027.3-126046.6"
wire width 10 $1\spr_a[9:0]
- attribute \src "libresoc.v:126202.3-126221.6"
+ attribute \src "libresoc.v:126027.3-126046.6"
wire $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:126183.3-126201.6"
+ attribute \src "libresoc.v:126008.3-126026.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire width 3 $2\fast_a[2:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire $2\fast_a_ok[0:0]
- attribute \src "libresoc.v:126096.3-126111.6"
+ attribute \src "libresoc.v:125921.3-125936.6"
wire width 5 $2\reg_a[4:0]
- attribute \src "libresoc.v:126112.3-126127.6"
+ attribute \src "libresoc.v:125937.3-125952.6"
wire $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire width 3 $3\fast_a[2:0]
- attribute \src "libresoc.v:126128.3-126163.6"
+ attribute \src "libresoc.v:125953.3-125988.6"
wire $3\fast_a_ok[0:0]
- attribute \src "libresoc.v:126071.18-126071.108"
- wire $and$libresoc.v:126071$4781_Y
- attribute \src "libresoc.v:126080.18-126080.110"
- wire $and$libresoc.v:126080$4790_Y
- attribute \src "libresoc.v:126085.18-126085.113"
- wire $and$libresoc.v:126085$4795_Y
- attribute \src "libresoc.v:126073.18-126073.112"
- wire $eq$libresoc.v:126073$4783_Y
- attribute \src "libresoc.v:126074.18-126074.112"
- wire $eq$libresoc.v:126074$4784_Y
- attribute \src "libresoc.v:126075.17-126075.111"
- wire $eq$libresoc.v:126075$4785_Y
- attribute \src "libresoc.v:126076.18-126076.112"
- wire $eq$libresoc.v:126076$4786_Y
- attribute \src "libresoc.v:126082.18-126082.112"
- wire $eq$libresoc.v:126082$4792_Y
- attribute \src "libresoc.v:126086.17-126086.111"
- wire $eq$libresoc.v:126086$4796_Y
- attribute \src "libresoc.v:126077.18-126077.109"
- wire $ne$libresoc.v:126077$4787_Y
- attribute \src "libresoc.v:126078.18-126078.111"
- wire $ne$libresoc.v:126078$4788_Y
- attribute \src "libresoc.v:126087.17-126087.108"
- wire $ne$libresoc.v:126087$4797_Y
- attribute \src "libresoc.v:126088.17-126088.110"
- wire $ne$libresoc.v:126088$4798_Y
- attribute \src "libresoc.v:126083.18-126083.105"
- wire $not$libresoc.v:126083$4793_Y
- attribute \src "libresoc.v:126084.18-126084.108"
- wire $not$libresoc.v:126084$4794_Y
- attribute \src "libresoc.v:126070.17-126070.107"
- wire $or$libresoc.v:126070$4780_Y
- attribute \src "libresoc.v:126072.18-126072.109"
- wire $or$libresoc.v:126072$4782_Y
- attribute \src "libresoc.v:126079.18-126079.110"
- wire $or$libresoc.v:126079$4789_Y
- attribute \src "libresoc.v:126081.18-126081.110"
- wire $or$libresoc.v:126081$4791_Y
+ attribute \src "libresoc.v:125896.18-125896.108"
+ wire $and$libresoc.v:125896$4765_Y
+ attribute \src "libresoc.v:125905.18-125905.110"
+ wire $and$libresoc.v:125905$4774_Y
+ attribute \src "libresoc.v:125910.18-125910.113"
+ wire $and$libresoc.v:125910$4779_Y
+ attribute \src "libresoc.v:125898.18-125898.112"
+ wire $eq$libresoc.v:125898$4767_Y
+ attribute \src "libresoc.v:125899.18-125899.112"
+ wire $eq$libresoc.v:125899$4768_Y
+ attribute \src "libresoc.v:125900.17-125900.111"
+ wire $eq$libresoc.v:125900$4769_Y
+ attribute \src "libresoc.v:125901.18-125901.112"
+ wire $eq$libresoc.v:125901$4770_Y
+ attribute \src "libresoc.v:125907.18-125907.112"
+ wire $eq$libresoc.v:125907$4776_Y
+ attribute \src "libresoc.v:125911.17-125911.111"
+ wire $eq$libresoc.v:125911$4780_Y
+ attribute \src "libresoc.v:125902.18-125902.109"
+ wire $ne$libresoc.v:125902$4771_Y
+ attribute \src "libresoc.v:125903.18-125903.111"
+ wire $ne$libresoc.v:125903$4772_Y
+ attribute \src "libresoc.v:125912.17-125912.108"
+ wire $ne$libresoc.v:125912$4781_Y
+ attribute \src "libresoc.v:125913.17-125913.110"
+ wire $ne$libresoc.v:125913$4782_Y
+ attribute \src "libresoc.v:125908.18-125908.105"
+ wire $not$libresoc.v:125908$4777_Y
+ attribute \src "libresoc.v:125909.18-125909.108"
+ wire $not$libresoc.v:125909$4778_Y
+ attribute \src "libresoc.v:125895.17-125895.107"
+ wire $or$libresoc.v:125895$4764_Y
+ attribute \src "libresoc.v:125897.18-125897.109"
+ wire $or$libresoc.v:125897$4766_Y
+ attribute \src "libresoc.v:125904.18-125904.110"
+ wire $or$libresoc.v:125904$4773_Y
+ attribute \src "libresoc.v:125906.18-125906.110"
+ wire $or$libresoc.v:125906$4775_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
wire width 3 output 8 \fast_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 9 \fast_a_ok
- attribute \src "libresoc.v:125672.7-125672.15"
+ attribute \src "libresoc.v:125497.7-125497.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
wire input 2 \sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $and $and$libresoc.v:126071$4781
+ cell $and $and$libresoc.v:125896$4765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$9
- connect \Y $and$libresoc.v:126071$4781_Y
+ connect \Y $and$libresoc.v:125896$4765_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $and $and$libresoc.v:126080$4790
+ cell $and $and$libresoc.v:125905$4774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \$25
- connect \Y $and$libresoc.v:126080$4790_Y
+ connect \Y $and$libresoc.v:125905$4774_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
- cell $and $and$libresoc.v:126085$4795
+ cell $and $and$libresoc.v:125910$4779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
connect \B \$35
- connect \Y $and$libresoc.v:126085$4795_Y
+ connect \Y $and$libresoc.v:125910$4779_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
- cell $eq $eq$libresoc.v:126073$4783
+ cell $eq $eq$libresoc.v:125898$4767
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:126073$4783_Y
+ connect \Y $eq$libresoc.v:125898$4767_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $eq $eq$libresoc.v:126074$4784
+ cell $eq $eq$libresoc.v:125899$4768
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:126074$4784_Y
+ connect \Y $eq$libresoc.v:125899$4768_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $eq $eq$libresoc.v:126075$4785
+ cell $eq $eq$libresoc.v:125900$4769
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:126075$4785_Y
+ connect \Y $eq$libresoc.v:125900$4769_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
- cell $eq $eq$libresoc.v:126076$4786
+ cell $eq $eq$libresoc.v:125901$4770
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126076$4786_Y
+ connect \Y $eq$libresoc.v:125901$4770_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
- cell $eq $eq$libresoc.v:126082$4792
+ cell $eq $eq$libresoc.v:125907$4776
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:126082$4792_Y
+ connect \Y $eq$libresoc.v:125907$4776_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
- cell $eq $eq$libresoc.v:126086$4796
+ cell $eq $eq$libresoc.v:125911$4780
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126086$4796_Y
+ connect \Y $eq$libresoc.v:125911$4780_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $ne $ne$libresoc.v:126077$4787
+ cell $ne $ne$libresoc.v:125902$4771
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:126077$4787_Y
+ connect \Y $ne$libresoc.v:125902$4771_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $ne $ne$libresoc.v:126078$4788
+ cell $ne $ne$libresoc.v:125903$4772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $ne$libresoc.v:126078$4788_Y
+ connect \Y $ne$libresoc.v:125903$4772_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $ne $ne$libresoc.v:126087$4797
+ cell $ne $ne$libresoc.v:125912$4781
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:126087$4797_Y
+ connect \Y $ne$libresoc.v:125912$4781_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $ne $ne$libresoc.v:126088$4798
+ cell $ne $ne$libresoc.v:125913$4782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $ne$libresoc.v:126088$4798_Y
+ connect \Y $ne$libresoc.v:125913$4782_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
- cell $not $not$libresoc.v:126083$4793
+ cell $not $not$libresoc.v:125908$4777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:126083$4793_Y
+ connect \Y $not$libresoc.v:125908$4777_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
- cell $not $not$libresoc.v:126084$4794
+ cell $not $not$libresoc.v:125909$4778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [5]
- connect \Y $not$libresoc.v:126084$4794_Y
+ connect \Y $not$libresoc.v:125909$4778_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $or $or$libresoc.v:126070$4780
+ cell $or $or$libresoc.v:125895$4764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $or$libresoc.v:126070$4780_Y
+ connect \Y $or$libresoc.v:125895$4764_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $or $or$libresoc.v:126072$4782
+ cell $or $or$libresoc.v:125897$4766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$11
- connect \Y $or$libresoc.v:126072$4782_Y
+ connect \Y $or$libresoc.v:125897$4766_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $or $or$libresoc.v:126079$4789
+ cell $or $or$libresoc.v:125904$4773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$21
connect \B \$23
- connect \Y $or$libresoc.v:126079$4789_Y
+ connect \Y $or$libresoc.v:125904$4773_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $or $or$libresoc.v:126081$4791
+ cell $or $or$libresoc.v:125906$4775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$17
connect \B \$27
- connect \Y $or$libresoc.v:126081$4791_Y
+ connect \Y $or$libresoc.v:125906$4775_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:126089.10-126095.4"
+ attribute \src "libresoc.v:125914.10-125920.4"
cell \sprmap \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:125672.7-125672.20"
- process $proc$libresoc.v:125672$4805
+ attribute \src "libresoc.v:125497.7-125497.20"
+ process $proc$libresoc.v:125497$4789
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126096.3-126111.6"
- process $proc$libresoc.v:126096$4799
+ attribute \src "libresoc.v:125921.3-125936.6"
+ process $proc$libresoc.v:125921$4783
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a[4:0] $2\reg_a[4:0]
- attribute \src "libresoc.v:126097.5-126097.29"
+ attribute \src "libresoc.v:125922.5-125922.29"
switch \initial
- attribute \src "libresoc.v:126097.9-126097.17"
+ attribute \src "libresoc.v:125922.9-125922.17"
case 1'1
case
end
sync always
update \reg_a $0\reg_a[4:0]
end
- attribute \src "libresoc.v:126112.3-126127.6"
- process $proc$libresoc.v:126112$4800
+ attribute \src "libresoc.v:125937.3-125952.6"
+ process $proc$libresoc.v:125937$4784
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:126113.5-126113.29"
+ attribute \src "libresoc.v:125938.5-125938.29"
switch \initial
- attribute \src "libresoc.v:126113.9-126113.17"
+ attribute \src "libresoc.v:125938.9-125938.17"
case 1'1
case
end
sync always
update \reg_a_ok $0\reg_a_ok[0:0]
end
- attribute \src "libresoc.v:126128.3-126163.6"
- process $proc$libresoc.v:126128$4801
+ attribute \src "libresoc.v:125953.3-125988.6"
+ process $proc$libresoc.v:125953$4785
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_a[2:0] $1\fast_a[2:0]
assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:126129.5-126129.29"
+ attribute \src "libresoc.v:125954.5-125954.29"
switch \initial
- attribute \src "libresoc.v:126129.9-126129.17"
+ attribute \src "libresoc.v:125954.9-125954.17"
case 1'1
case
end
update \fast_a $0\fast_a[2:0]
update \fast_a_ok $0\fast_a_ok[0:0]
end
- attribute \src "libresoc.v:126164.3-126182.6"
- process $proc$libresoc.v:126164$4802
+ attribute \src "libresoc.v:125989.3-126007.6"
+ process $proc$libresoc.v:125989$4786
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:126165.5-126165.29"
+ attribute \src "libresoc.v:125990.5-125990.29"
switch \initial
- attribute \src "libresoc.v:126165.9-126165.17"
+ attribute \src "libresoc.v:125990.9-125990.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:126183.3-126201.6"
- process $proc$libresoc.v:126183$4803
+ attribute \src "libresoc.v:126008.3-126026.6"
+ process $proc$libresoc.v:126008$4787
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:126184.5-126184.29"
+ attribute \src "libresoc.v:126009.5-126009.29"
switch \initial
- attribute \src "libresoc.v:126184.9-126184.17"
+ attribute \src "libresoc.v:126009.9-126009.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:126202.3-126221.6"
- process $proc$libresoc.v:126202$4804
+ attribute \src "libresoc.v:126027.3-126046.6"
+ process $proc$libresoc.v:126027$4788
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_a[9:0] $1\spr_a[9:0]
assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:126203.5-126203.29"
+ attribute \src "libresoc.v:126028.5-126028.29"
switch \initial
- attribute \src "libresoc.v:126203.9-126203.17"
+ attribute \src "libresoc.v:126028.9-126028.17"
case 1'1
case
end
update \spr_a $0\spr_a[9:0]
update \spr_a_ok $0\spr_a_ok[0:0]
end
- connect \$9 $or$libresoc.v:126070$4780_Y
- connect \$11 $and$libresoc.v:126071$4781_Y
- connect \$13 $or$libresoc.v:126072$4782_Y
- connect \$15 $eq$libresoc.v:126073$4783_Y
- connect \$17 $eq$libresoc.v:126074$4784_Y
- connect \$1 $eq$libresoc.v:126075$4785_Y
- connect \$19 $eq$libresoc.v:126076$4786_Y
- connect \$21 $ne$libresoc.v:126077$4787_Y
- connect \$23 $ne$libresoc.v:126078$4788_Y
- connect \$25 $or$libresoc.v:126079$4789_Y
- connect \$27 $and$libresoc.v:126080$4790_Y
- connect \$29 $or$libresoc.v:126081$4791_Y
- connect \$31 $eq$libresoc.v:126082$4792_Y
- connect \$33 $not$libresoc.v:126083$4793_Y
- connect \$35 $not$libresoc.v:126084$4794_Y
- connect \$37 $and$libresoc.v:126085$4795_Y
- connect \$3 $eq$libresoc.v:126086$4796_Y
- connect \$5 $ne$libresoc.v:126087$4797_Y
- connect \$7 $ne$libresoc.v:126088$4798_Y
+ connect \$9 $or$libresoc.v:125895$4764_Y
+ connect \$11 $and$libresoc.v:125896$4765_Y
+ connect \$13 $or$libresoc.v:125897$4766_Y
+ connect \$15 $eq$libresoc.v:125898$4767_Y
+ connect \$17 $eq$libresoc.v:125899$4768_Y
+ connect \$1 $eq$libresoc.v:125900$4769_Y
+ connect \$19 $eq$libresoc.v:125901$4770_Y
+ connect \$21 $ne$libresoc.v:125902$4771_Y
+ connect \$23 $ne$libresoc.v:125903$4772_Y
+ connect \$25 $or$libresoc.v:125904$4773_Y
+ connect \$27 $and$libresoc.v:125905$4774_Y
+ connect \$29 $or$libresoc.v:125906$4775_Y
+ connect \$31 $eq$libresoc.v:125907$4776_Y
+ connect \$33 $not$libresoc.v:125908$4777_Y
+ connect \$35 $not$libresoc.v:125909$4778_Y
+ connect \$37 $and$libresoc.v:125910$4779_Y
+ connect \$3 $eq$libresoc.v:125911$4780_Y
+ connect \$5 $ne$libresoc.v:125912$4781_Y
+ connect \$7 $ne$libresoc.v:125913$4782_Y
connect \rs \RS
connect \ra \RA
end
-attribute \src "libresoc.v:126228.1-126273.10"
+attribute \src "libresoc.v:126053.1-126098.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai"
attribute \generator "nMigen"
module \dec_ai
- attribute \src "libresoc.v:126262.3-126271.6"
+ attribute \src "libresoc.v:126087.3-126096.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:126229.7-126229.20"
+ attribute \src "libresoc.v:126054.7-126054.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126262.3-126271.6"
+ attribute \src "libresoc.v:126087.3-126096.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:126257.17-126257.107"
- wire $and$libresoc.v:126257$4806_Y
- attribute \src "libresoc.v:126260.17-126260.107"
- wire $and$libresoc.v:126260$4809_Y
- attribute \src "libresoc.v:126258.17-126258.111"
- wire $eq$libresoc.v:126258$4807_Y
- attribute \src "libresoc.v:126259.17-126259.108"
- wire $eq$libresoc.v:126259$4808_Y
- attribute \src "libresoc.v:126261.17-126261.110"
- wire $eq$libresoc.v:126261$4810_Y
+ attribute \src "libresoc.v:126082.17-126082.107"
+ wire $and$libresoc.v:126082$4790_Y
+ attribute \src "libresoc.v:126085.17-126085.107"
+ wire $and$libresoc.v:126085$4793_Y
+ attribute \src "libresoc.v:126083.17-126083.111"
+ wire $eq$libresoc.v:126083$4791_Y
+ attribute \src "libresoc.v:126084.17-126084.108"
+ wire $eq$libresoc.v:126084$4792_Y
+ attribute \src "libresoc.v:126086.17-126086.110"
+ wire $eq$libresoc.v:126086$4794_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire width 5 input 3 \ALU_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
wire output 2 \immz_out
- attribute \src "libresoc.v:126229.7-126229.15"
+ attribute \src "libresoc.v:126054.7-126054.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
wire input 4 \sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $and $and$libresoc.v:126257$4806
+ cell $and $and$libresoc.v:126082$4790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $and$libresoc.v:126257$4806_Y
+ connect \Y $and$libresoc.v:126082$4790_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $and $and$libresoc.v:126260$4809
+ cell $and $and$libresoc.v:126085$4793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:126260$4809_Y
+ connect \Y $and$libresoc.v:126085$4793_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126258$4807
+ cell $eq $eq$libresoc.v:126083$4791
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126258$4807_Y
+ connect \Y $eq$libresoc.v:126083$4791_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126259$4808
+ cell $eq $eq$libresoc.v:126084$4792
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:126259$4808_Y
+ connect \Y $eq$libresoc.v:126084$4792_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $eq $eq$libresoc.v:126261$4810
+ cell $eq $eq$libresoc.v:126086$4794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $eq$libresoc.v:126261$4810_Y
+ connect \Y $eq$libresoc.v:126086$4794_Y
end
- attribute \src "libresoc.v:126229.7-126229.20"
- process $proc$libresoc.v:126229$4812
+ attribute \src "libresoc.v:126054.7-126054.20"
+ process $proc$libresoc.v:126054$4796
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126262.3-126271.6"
- process $proc$libresoc.v:126262$4811
+ attribute \src "libresoc.v:126087.3-126096.6"
+ process $proc$libresoc.v:126087$4795
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:126263.5-126263.29"
+ attribute \src "libresoc.v:126088.5-126088.29"
switch \initial
- attribute \src "libresoc.v:126263.9-126263.17"
+ attribute \src "libresoc.v:126088.9-126088.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$9 $and$libresoc.v:126257$4806_Y
- connect \$1 $eq$libresoc.v:126258$4807_Y
- connect \$3 $eq$libresoc.v:126259$4808_Y
- connect \$5 $and$libresoc.v:126260$4809_Y
- connect \$7 $eq$libresoc.v:126261$4810_Y
+ connect \$9 $and$libresoc.v:126082$4790_Y
+ connect \$1 $eq$libresoc.v:126083$4791_Y
+ connect \$3 $eq$libresoc.v:126084$4792_Y
+ connect \$5 $and$libresoc.v:126085$4793_Y
+ connect \$7 $eq$libresoc.v:126086$4794_Y
connect \ra \ALU_RA
end
-attribute \src "libresoc.v:126277.1-126322.10"
+attribute \src "libresoc.v:126102.1-126147.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai"
attribute \generator "nMigen"
module \dec_ai$148
- attribute \src "libresoc.v:126311.3-126320.6"
+ attribute \src "libresoc.v:126136.3-126145.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:126278.7-126278.20"
+ attribute \src "libresoc.v:126103.7-126103.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126311.3-126320.6"
+ attribute \src "libresoc.v:126136.3-126145.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:126306.17-126306.107"
- wire $and$libresoc.v:126306$4813_Y
- attribute \src "libresoc.v:126309.17-126309.107"
- wire $and$libresoc.v:126309$4816_Y
- attribute \src "libresoc.v:126307.17-126307.111"
- wire $eq$libresoc.v:126307$4814_Y
- attribute \src "libresoc.v:126308.17-126308.108"
- wire $eq$libresoc.v:126308$4815_Y
- attribute \src "libresoc.v:126310.17-126310.110"
- wire $eq$libresoc.v:126310$4817_Y
+ attribute \src "libresoc.v:126131.17-126131.107"
+ wire $and$libresoc.v:126131$4797_Y
+ attribute \src "libresoc.v:126134.17-126134.107"
+ wire $and$libresoc.v:126134$4800_Y
+ attribute \src "libresoc.v:126132.17-126132.111"
+ wire $eq$libresoc.v:126132$4798_Y
+ attribute \src "libresoc.v:126133.17-126133.108"
+ wire $eq$libresoc.v:126133$4799_Y
+ attribute \src "libresoc.v:126135.17-126135.110"
+ wire $eq$libresoc.v:126135$4801_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire width 5 input 3 \LOGICAL_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
wire output 2 \immz_out
- attribute \src "libresoc.v:126278.7-126278.15"
+ attribute \src "libresoc.v:126103.7-126103.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
wire input 4 \sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $and $and$libresoc.v:126306$4813
+ cell $and $and$libresoc.v:126131$4797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $and$libresoc.v:126306$4813_Y
+ connect \Y $and$libresoc.v:126131$4797_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $and $and$libresoc.v:126309$4816
+ cell $and $and$libresoc.v:126134$4800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:126309$4816_Y
+ connect \Y $and$libresoc.v:126134$4800_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126307$4814
+ cell $eq $eq$libresoc.v:126132$4798
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126307$4814_Y
+ connect \Y $eq$libresoc.v:126132$4798_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126308$4815
+ cell $eq $eq$libresoc.v:126133$4799
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:126308$4815_Y
+ connect \Y $eq$libresoc.v:126133$4799_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $eq $eq$libresoc.v:126310$4817
+ cell $eq $eq$libresoc.v:126135$4801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $eq$libresoc.v:126310$4817_Y
+ connect \Y $eq$libresoc.v:126135$4801_Y
end
- attribute \src "libresoc.v:126278.7-126278.20"
- process $proc$libresoc.v:126278$4819
+ attribute \src "libresoc.v:126103.7-126103.20"
+ process $proc$libresoc.v:126103$4803
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126311.3-126320.6"
- process $proc$libresoc.v:126311$4818
+ attribute \src "libresoc.v:126136.3-126145.6"
+ process $proc$libresoc.v:126136$4802
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:126312.5-126312.29"
+ attribute \src "libresoc.v:126137.5-126137.29"
switch \initial
- attribute \src "libresoc.v:126312.9-126312.17"
+ attribute \src "libresoc.v:126137.9-126137.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$9 $and$libresoc.v:126306$4813_Y
- connect \$1 $eq$libresoc.v:126307$4814_Y
- connect \$3 $eq$libresoc.v:126308$4815_Y
- connect \$5 $and$libresoc.v:126309$4816_Y
- connect \$7 $eq$libresoc.v:126310$4817_Y
+ connect \$9 $and$libresoc.v:126131$4797_Y
+ connect \$1 $eq$libresoc.v:126132$4798_Y
+ connect \$3 $eq$libresoc.v:126133$4799_Y
+ connect \$5 $and$libresoc.v:126134$4800_Y
+ connect \$7 $eq$libresoc.v:126135$4801_Y
connect \ra \LOGICAL_RA
end
-attribute \src "libresoc.v:126326.1-126371.10"
+attribute \src "libresoc.v:126151.1-126196.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai"
attribute \generator "nMigen"
module \dec_ai$156
- attribute \src "libresoc.v:126360.3-126369.6"
+ attribute \src "libresoc.v:126185.3-126194.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:126327.7-126327.20"
+ attribute \src "libresoc.v:126152.7-126152.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126360.3-126369.6"
+ attribute \src "libresoc.v:126185.3-126194.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:126355.17-126355.107"
- wire $and$libresoc.v:126355$4820_Y
- attribute \src "libresoc.v:126358.17-126358.107"
- wire $and$libresoc.v:126358$4823_Y
- attribute \src "libresoc.v:126356.17-126356.111"
- wire $eq$libresoc.v:126356$4821_Y
- attribute \src "libresoc.v:126357.17-126357.108"
- wire $eq$libresoc.v:126357$4822_Y
- attribute \src "libresoc.v:126359.17-126359.110"
- wire $eq$libresoc.v:126359$4824_Y
+ attribute \src "libresoc.v:126180.17-126180.107"
+ wire $and$libresoc.v:126180$4804_Y
+ attribute \src "libresoc.v:126183.17-126183.107"
+ wire $and$libresoc.v:126183$4807_Y
+ attribute \src "libresoc.v:126181.17-126181.111"
+ wire $eq$libresoc.v:126181$4805_Y
+ attribute \src "libresoc.v:126182.17-126182.108"
+ wire $eq$libresoc.v:126182$4806_Y
+ attribute \src "libresoc.v:126184.17-126184.110"
+ wire $eq$libresoc.v:126184$4808_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire width 5 input 3 \DIV_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
wire output 2 \immz_out
- attribute \src "libresoc.v:126327.7-126327.15"
+ attribute \src "libresoc.v:126152.7-126152.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
wire input 4 \sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $and $and$libresoc.v:126355$4820
+ cell $and $and$libresoc.v:126180$4804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $and$libresoc.v:126355$4820_Y
+ connect \Y $and$libresoc.v:126180$4804_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $and $and$libresoc.v:126358$4823
+ cell $and $and$libresoc.v:126183$4807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:126358$4823_Y
+ connect \Y $and$libresoc.v:126183$4807_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126356$4821
+ cell $eq $eq$libresoc.v:126181$4805
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126356$4821_Y
+ connect \Y $eq$libresoc.v:126181$4805_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126357$4822
+ cell $eq $eq$libresoc.v:126182$4806
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:126357$4822_Y
+ connect \Y $eq$libresoc.v:126182$4806_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $eq $eq$libresoc.v:126359$4824
+ cell $eq $eq$libresoc.v:126184$4808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $eq$libresoc.v:126359$4824_Y
+ connect \Y $eq$libresoc.v:126184$4808_Y
end
- attribute \src "libresoc.v:126327.7-126327.20"
- process $proc$libresoc.v:126327$4826
+ attribute \src "libresoc.v:126152.7-126152.20"
+ process $proc$libresoc.v:126152$4810
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126360.3-126369.6"
- process $proc$libresoc.v:126360$4825
+ attribute \src "libresoc.v:126185.3-126194.6"
+ process $proc$libresoc.v:126185$4809
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:126361.5-126361.29"
+ attribute \src "libresoc.v:126186.5-126186.29"
switch \initial
- attribute \src "libresoc.v:126361.9-126361.17"
+ attribute \src "libresoc.v:126186.9-126186.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$9 $and$libresoc.v:126355$4820_Y
- connect \$1 $eq$libresoc.v:126356$4821_Y
- connect \$3 $eq$libresoc.v:126357$4822_Y
- connect \$5 $and$libresoc.v:126358$4823_Y
- connect \$7 $eq$libresoc.v:126359$4824_Y
+ connect \$9 $and$libresoc.v:126180$4804_Y
+ connect \$1 $eq$libresoc.v:126181$4805_Y
+ connect \$3 $eq$libresoc.v:126182$4806_Y
+ connect \$5 $and$libresoc.v:126183$4807_Y
+ connect \$7 $eq$libresoc.v:126184$4808_Y
connect \ra \DIV_RA
end
-attribute \src "libresoc.v:126375.1-126420.10"
+attribute \src "libresoc.v:126200.1-126245.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai"
attribute \generator "nMigen"
module \dec_ai$169
- attribute \src "libresoc.v:126409.3-126418.6"
+ attribute \src "libresoc.v:126234.3-126243.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:126376.7-126376.20"
+ attribute \src "libresoc.v:126201.7-126201.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126409.3-126418.6"
+ attribute \src "libresoc.v:126234.3-126243.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:126404.17-126404.107"
- wire $and$libresoc.v:126404$4827_Y
- attribute \src "libresoc.v:126407.17-126407.107"
- wire $and$libresoc.v:126407$4830_Y
- attribute \src "libresoc.v:126405.17-126405.111"
- wire $eq$libresoc.v:126405$4828_Y
- attribute \src "libresoc.v:126406.17-126406.108"
- wire $eq$libresoc.v:126406$4829_Y
- attribute \src "libresoc.v:126408.17-126408.110"
- wire $eq$libresoc.v:126408$4831_Y
+ attribute \src "libresoc.v:126229.17-126229.107"
+ wire $and$libresoc.v:126229$4811_Y
+ attribute \src "libresoc.v:126232.17-126232.107"
+ wire $and$libresoc.v:126232$4814_Y
+ attribute \src "libresoc.v:126230.17-126230.111"
+ wire $eq$libresoc.v:126230$4812_Y
+ attribute \src "libresoc.v:126231.17-126231.108"
+ wire $eq$libresoc.v:126231$4813_Y
+ attribute \src "libresoc.v:126233.17-126233.110"
+ wire $eq$libresoc.v:126233$4815_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire width 5 input 3 \LDST_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
wire output 2 \immz_out
- attribute \src "libresoc.v:126376.7-126376.15"
+ attribute \src "libresoc.v:126201.7-126201.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
wire input 4 \sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $and $and$libresoc.v:126404$4827
+ cell $and $and$libresoc.v:126229$4811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $and$libresoc.v:126404$4827_Y
+ connect \Y $and$libresoc.v:126229$4811_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $and $and$libresoc.v:126407$4830
+ cell $and $and$libresoc.v:126232$4814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:126407$4830_Y
+ connect \Y $and$libresoc.v:126232$4814_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126405$4828
+ cell $eq $eq$libresoc.v:126230$4812
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:126405$4828_Y
+ connect \Y $eq$libresoc.v:126230$4812_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
- cell $eq $eq$libresoc.v:126406$4829
+ cell $eq $eq$libresoc.v:126231$4813
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:126406$4829_Y
+ connect \Y $eq$libresoc.v:126231$4813_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
- cell $eq $eq$libresoc.v:126408$4831
+ cell $eq $eq$libresoc.v:126233$4815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sv_nz
connect \B 1'0
- connect \Y $eq$libresoc.v:126408$4831_Y
+ connect \Y $eq$libresoc.v:126233$4815_Y
end
- attribute \src "libresoc.v:126376.7-126376.20"
- process $proc$libresoc.v:126376$4833
+ attribute \src "libresoc.v:126201.7-126201.20"
+ process $proc$libresoc.v:126201$4817
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126409.3-126418.6"
- process $proc$libresoc.v:126409$4832
+ attribute \src "libresoc.v:126234.3-126243.6"
+ process $proc$libresoc.v:126234$4816
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:126410.5-126410.29"
+ attribute \src "libresoc.v:126235.5-126235.29"
switch \initial
- attribute \src "libresoc.v:126410.9-126410.17"
+ attribute \src "libresoc.v:126235.9-126235.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$9 $and$libresoc.v:126404$4827_Y
- connect \$1 $eq$libresoc.v:126405$4828_Y
- connect \$3 $eq$libresoc.v:126406$4829_Y
- connect \$5 $and$libresoc.v:126407$4830_Y
- connect \$7 $eq$libresoc.v:126408$4831_Y
+ connect \$9 $and$libresoc.v:126229$4811_Y
+ connect \$1 $eq$libresoc.v:126230$4812_Y
+ connect \$3 $eq$libresoc.v:126231$4813_Y
+ connect \$5 $and$libresoc.v:126232$4814_Y
+ connect \$7 $eq$libresoc.v:126233$4815_Y
connect \ra \LDST_RA
end
-attribute \src "libresoc.v:126424.1-126622.10"
+attribute \src "libresoc.v:126249.1-126447.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b"
attribute \generator "nMigen"
module \dec_b
- attribute \src "libresoc.v:126586.3-126603.6"
+ attribute \src "libresoc.v:126411.3-126428.6"
wire width 3 $0\fast_b[2:0]
- attribute \src "libresoc.v:126604.3-126621.6"
+ attribute \src "libresoc.v:126429.3-126446.6"
wire $0\fast_b_ok[0:0]
- attribute \src "libresoc.v:126425.7-126425.20"
+ attribute \src "libresoc.v:126250.7-126250.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126556.3-126570.6"
+ attribute \src "libresoc.v:126381.3-126395.6"
wire width 7 $0\reg_b[6:0]
- attribute \src "libresoc.v:126571.3-126585.6"
+ attribute \src "libresoc.v:126396.3-126410.6"
wire $0\reg_b_ok[0:0]
- attribute \src "libresoc.v:126586.3-126603.6"
+ attribute \src "libresoc.v:126411.3-126428.6"
wire width 3 $1\fast_b[2:0]
- attribute \src "libresoc.v:126604.3-126621.6"
+ attribute \src "libresoc.v:126429.3-126446.6"
wire $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:126556.3-126570.6"
+ attribute \src "libresoc.v:126381.3-126395.6"
wire width 7 $1\reg_b[6:0]
- attribute \src "libresoc.v:126571.3-126585.6"
+ attribute \src "libresoc.v:126396.3-126410.6"
wire $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:126586.3-126603.6"
+ attribute \src "libresoc.v:126411.3-126428.6"
wire width 3 $2\fast_b[2:0]
- attribute \src "libresoc.v:126604.3-126621.6"
+ attribute \src "libresoc.v:126429.3-126446.6"
wire $2\fast_b_ok[0:0]
- attribute \src "libresoc.v:126550.17-126550.117"
- wire $eq$libresoc.v:126550$4834_Y
- attribute \src "libresoc.v:126554.17-126554.117"
- wire $eq$libresoc.v:126554$4840_Y
- attribute \src "libresoc.v:126552.17-126552.100"
- wire width 7 $extend$libresoc.v:126552$4836_Y
- attribute \src "libresoc.v:126553.17-126553.100"
- wire width 7 $extend$libresoc.v:126553$4838_Y
- attribute \src "libresoc.v:126551.18-126551.108"
- wire $not$libresoc.v:126551$4835_Y
- attribute \src "libresoc.v:126555.17-126555.107"
- wire $not$libresoc.v:126555$4841_Y
- attribute \src "libresoc.v:126552.17-126552.100"
- wire width 7 $pos$libresoc.v:126552$4837_Y
- attribute \src "libresoc.v:126553.17-126553.100"
- wire width 7 $pos$libresoc.v:126553$4839_Y
+ attribute \src "libresoc.v:126375.17-126375.117"
+ wire $eq$libresoc.v:126375$4818_Y
+ attribute \src "libresoc.v:126379.17-126379.117"
+ wire $eq$libresoc.v:126379$4824_Y
+ attribute \src "libresoc.v:126377.17-126377.100"
+ wire width 7 $extend$libresoc.v:126377$4820_Y
+ attribute \src "libresoc.v:126378.17-126378.100"
+ wire width 7 $extend$libresoc.v:126378$4822_Y
+ attribute \src "libresoc.v:126376.18-126376.108"
+ wire $not$libresoc.v:126376$4819_Y
+ attribute \src "libresoc.v:126380.17-126380.107"
+ wire $not$libresoc.v:126380$4825_Y
+ attribute \src "libresoc.v:126377.17-126377.100"
+ wire width 7 $pos$libresoc.v:126377$4821_Y
+ attribute \src "libresoc.v:126378.17-126378.100"
+ wire width 7 $pos$libresoc.v:126378$4823_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 7 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
wire width 3 output 4 \fast_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \fast_b_ok
- attribute \src "libresoc.v:126425.7-126425.15"
+ attribute \src "libresoc.v:126250.7-126250.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193"
wire width 4 input 1 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
- cell $eq $eq$libresoc.v:126550$4834
+ cell $eq $eq$libresoc.v:126375$4818
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:126550$4834_Y
+ connect \Y $eq$libresoc.v:126375$4818_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
- cell $eq $eq$libresoc.v:126554$4840
+ cell $eq $eq$libresoc.v:126379$4824
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:126554$4840_Y
+ connect \Y $eq$libresoc.v:126379$4824_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:126552$4836
+ cell $pos $extend$libresoc.v:126377$4820
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \RB
- connect \Y $extend$libresoc.v:126552$4836_Y
+ connect \Y $extend$libresoc.v:126377$4820_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:126553$4838
+ cell $pos $extend$libresoc.v:126378$4822
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \RS
- connect \Y $extend$libresoc.v:126553$4838_Y
+ connect \Y $extend$libresoc.v:126378$4822_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
- cell $not $not$libresoc.v:126551$4835
+ cell $not $not$libresoc.v:126376$4819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:126551$4835_Y
+ connect \Y $not$libresoc.v:126376$4819_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
- cell $not $not$libresoc.v:126555$4841
+ cell $not $not$libresoc.v:126380$4825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:126555$4841_Y
+ connect \Y $not$libresoc.v:126380$4825_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:126552$4837
+ cell $pos $pos$libresoc.v:126377$4821
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:126552$4836_Y
- connect \Y $pos$libresoc.v:126552$4837_Y
+ connect \A $extend$libresoc.v:126377$4820_Y
+ connect \Y $pos$libresoc.v:126377$4821_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:126553$4839
+ cell $pos $pos$libresoc.v:126378$4823
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:126553$4838_Y
- connect \Y $pos$libresoc.v:126553$4839_Y
+ connect \A $extend$libresoc.v:126378$4822_Y
+ connect \Y $pos$libresoc.v:126378$4823_Y
end
- attribute \src "libresoc.v:126425.7-126425.20"
- process $proc$libresoc.v:126425$4846
+ attribute \src "libresoc.v:126250.7-126250.20"
+ process $proc$libresoc.v:126250$4830
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126556.3-126570.6"
- process $proc$libresoc.v:126556$4842
+ attribute \src "libresoc.v:126381.3-126395.6"
+ process $proc$libresoc.v:126381$4826
assign { } { }
assign { } { }
assign $0\reg_b[6:0] $1\reg_b[6:0]
- attribute \src "libresoc.v:126557.5-126557.29"
+ attribute \src "libresoc.v:126382.5-126382.29"
switch \initial
- attribute \src "libresoc.v:126557.9-126557.17"
+ attribute \src "libresoc.v:126382.9-126382.17"
case 1'1
case
end
sync always
update \reg_b $0\reg_b[6:0]
end
- attribute \src "libresoc.v:126571.3-126585.6"
- process $proc$libresoc.v:126571$4843
+ attribute \src "libresoc.v:126396.3-126410.6"
+ process $proc$libresoc.v:126396$4827
assign { } { }
assign { } { }
assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:126572.5-126572.29"
+ attribute \src "libresoc.v:126397.5-126397.29"
switch \initial
- attribute \src "libresoc.v:126572.9-126572.17"
+ attribute \src "libresoc.v:126397.9-126397.17"
case 1'1
case
end
sync always
update \reg_b_ok $0\reg_b_ok[0:0]
end
- attribute \src "libresoc.v:126586.3-126603.6"
- process $proc$libresoc.v:126586$4844
+ attribute \src "libresoc.v:126411.3-126428.6"
+ process $proc$libresoc.v:126411$4828
assign { } { }
assign { } { }
assign $0\fast_b[2:0] $1\fast_b[2:0]
- attribute \src "libresoc.v:126587.5-126587.29"
+ attribute \src "libresoc.v:126412.5-126412.29"
switch \initial
- attribute \src "libresoc.v:126587.9-126587.17"
+ attribute \src "libresoc.v:126412.9-126412.17"
case 1'1
case
end
sync always
update \fast_b $0\fast_b[2:0]
end
- attribute \src "libresoc.v:126604.3-126621.6"
- process $proc$libresoc.v:126604$4845
+ attribute \src "libresoc.v:126429.3-126446.6"
+ process $proc$libresoc.v:126429$4829
assign { } { }
assign { } { }
assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:126605.5-126605.29"
+ attribute \src "libresoc.v:126430.5-126430.29"
switch \initial
- attribute \src "libresoc.v:126605.9-126605.17"
+ attribute \src "libresoc.v:126430.9-126430.17"
case 1'1
case
end
sync always
update \fast_b_ok $0\fast_b_ok[0:0]
end
- connect \$9 $eq$libresoc.v:126550$4834_Y
- connect \$11 $not$libresoc.v:126551$4835_Y
- connect \$1 $pos$libresoc.v:126552$4837_Y
- connect \$3 $pos$libresoc.v:126553$4839_Y
- connect \$5 $eq$libresoc.v:126554$4840_Y
- connect \$7 $not$libresoc.v:126555$4841_Y
+ connect \$9 $eq$libresoc.v:126375$4818_Y
+ connect \$11 $not$libresoc.v:126376$4819_Y
+ connect \$1 $pos$libresoc.v:126377$4821_Y
+ connect \$3 $pos$libresoc.v:126378$4823_Y
+ connect \$5 $eq$libresoc.v:126379$4824_Y
+ connect \$7 $not$libresoc.v:126380$4825_Y
end
-attribute \src "libresoc.v:126626.1-126963.10"
+attribute \src "libresoc.v:126451.1-126788.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi"
attribute \generator "nMigen"
module \dec_bi
- attribute \src "libresoc.v:126893.3-126923.6"
+ attribute \src "libresoc.v:126718.3-126748.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:126924.3-126958.6"
+ attribute \src "libresoc.v:126749.3-126783.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:126715.3-126761.6"
+ attribute \src "libresoc.v:126540.3-126586.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:126762.3-126808.6"
+ attribute \src "libresoc.v:126587.3-126633.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:126627.7-126627.20"
+ attribute \src "libresoc.v:126452.7-126452.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126866.3-126892.6"
+ attribute \src "libresoc.v:126691.3-126717.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:126809.3-126823.6"
+ attribute \src "libresoc.v:126634.3-126648.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:126824.3-126842.6"
+ attribute \src "libresoc.v:126649.3-126667.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:126843.3-126865.6"
+ attribute \src "libresoc.v:126668.3-126690.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:126893.3-126923.6"
+ attribute \src "libresoc.v:126718.3-126748.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:126924.3-126958.6"
+ attribute \src "libresoc.v:126749.3-126783.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:126715.3-126761.6"
+ attribute \src "libresoc.v:126540.3-126586.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:126762.3-126808.6"
+ attribute \src "libresoc.v:126587.3-126633.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:126866.3-126892.6"
+ attribute \src "libresoc.v:126691.3-126717.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:126809.3-126823.6"
+ attribute \src "libresoc.v:126634.3-126648.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:126824.3-126842.6"
+ attribute \src "libresoc.v:126649.3-126667.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:126843.3-126865.6"
+ attribute \src "libresoc.v:126668.3-126690.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:126705.17-126705.104"
- wire width 64 $extend$libresoc.v:126705$4847_Y
- attribute \src "libresoc.v:126706.18-126706.107"
- wire width 64 $extend$libresoc.v:126706$4849_Y
- attribute \src "libresoc.v:126709.17-126709.104"
- wire width 64 $extend$libresoc.v:126709$4853_Y
- attribute \src "libresoc.v:126713.17-126713.102"
- wire width 64 $extend$libresoc.v:126713$4858_Y
- attribute \src "libresoc.v:126705.17-126705.104"
- wire width 64 $pos$libresoc.v:126705$4848_Y
- attribute \src "libresoc.v:126706.18-126706.107"
- wire width 64 $pos$libresoc.v:126706$4850_Y
- attribute \src "libresoc.v:126709.17-126709.104"
- wire width 64 $pos$libresoc.v:126709$4854_Y
- attribute \src "libresoc.v:126713.17-126713.102"
- wire width 64 $pos$libresoc.v:126713$4859_Y
- attribute \src "libresoc.v:126707.18-126707.114"
- wire width 47 $sshl$libresoc.v:126707$4851_Y
- attribute \src "libresoc.v:126708.18-126708.113"
- wire width 27 $sshl$libresoc.v:126708$4852_Y
- attribute \src "libresoc.v:126710.18-126710.113"
- wire width 17 $sshl$libresoc.v:126710$4855_Y
- attribute \src "libresoc.v:126711.18-126711.113"
- wire width 17 $sshl$libresoc.v:126711$4856_Y
- attribute \src "libresoc.v:126712.17-126712.109"
- wire width 47 $sshl$libresoc.v:126712$4857_Y
+ attribute \src "libresoc.v:126530.17-126530.104"
+ wire width 64 $extend$libresoc.v:126530$4831_Y
+ attribute \src "libresoc.v:126531.18-126531.107"
+ wire width 64 $extend$libresoc.v:126531$4833_Y
+ attribute \src "libresoc.v:126534.17-126534.104"
+ wire width 64 $extend$libresoc.v:126534$4837_Y
+ attribute \src "libresoc.v:126538.17-126538.102"
+ wire width 64 $extend$libresoc.v:126538$4842_Y
+ attribute \src "libresoc.v:126530.17-126530.104"
+ wire width 64 $pos$libresoc.v:126530$4832_Y
+ attribute \src "libresoc.v:126531.18-126531.107"
+ wire width 64 $pos$libresoc.v:126531$4834_Y
+ attribute \src "libresoc.v:126534.17-126534.104"
+ wire width 64 $pos$libresoc.v:126534$4838_Y
+ attribute \src "libresoc.v:126538.17-126538.102"
+ wire width 64 $pos$libresoc.v:126538$4843_Y
+ attribute \src "libresoc.v:126532.18-126532.114"
+ wire width 47 $sshl$libresoc.v:126532$4835_Y
+ attribute \src "libresoc.v:126533.18-126533.113"
+ wire width 27 $sshl$libresoc.v:126533$4836_Y
+ attribute \src "libresoc.v:126535.18-126535.113"
+ wire width 17 $sshl$libresoc.v:126535$4839_Y
+ attribute \src "libresoc.v:126536.18-126536.113"
+ wire width 17 $sshl$libresoc.v:126536$4840_Y
+ attribute \src "libresoc.v:126537.17-126537.109"
+ wire width 47 $sshl$libresoc.v:126537$4841_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:126627.7-126627.15"
+ attribute \src "libresoc.v:126452.7-126452.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:126705$4847
+ cell $pos $extend$libresoc.v:126530$4831
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \ALU_sh
- connect \Y $extend$libresoc.v:126705$4847_Y
+ connect \Y $extend$libresoc.v:126530$4831_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:126706$4849
+ cell $pos $extend$libresoc.v:126531$4833
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \ALU_SH32
- connect \Y $extend$libresoc.v:126706$4849_Y
+ connect \Y $extend$libresoc.v:126531$4833_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:126709$4853
+ cell $pos $extend$libresoc.v:126534$4837
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \ALU_UI
- connect \Y $extend$libresoc.v:126709$4853_Y
+ connect \Y $extend$libresoc.v:126534$4837_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:126713$4858
+ cell $pos $extend$libresoc.v:126538$4842
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:126713$4858_Y
+ connect \Y $extend$libresoc.v:126538$4842_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:126705$4848
+ cell $pos $pos$libresoc.v:126530$4832
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126705$4847_Y
- connect \Y $pos$libresoc.v:126705$4848_Y
+ connect \A $extend$libresoc.v:126530$4831_Y
+ connect \Y $pos$libresoc.v:126530$4832_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:126706$4850
+ cell $pos $pos$libresoc.v:126531$4834
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126706$4849_Y
- connect \Y $pos$libresoc.v:126706$4850_Y
+ connect \A $extend$libresoc.v:126531$4833_Y
+ connect \Y $pos$libresoc.v:126531$4834_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:126709$4854
+ cell $pos $pos$libresoc.v:126534$4838
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126709$4853_Y
- connect \Y $pos$libresoc.v:126709$4854_Y
+ connect \A $extend$libresoc.v:126534$4837_Y
+ connect \Y $pos$libresoc.v:126534$4838_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:126713$4859
+ cell $pos $pos$libresoc.v:126538$4843
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126713$4858_Y
- connect \Y $pos$libresoc.v:126713$4859_Y
+ connect \A $extend$libresoc.v:126538$4842_Y
+ connect \Y $pos$libresoc.v:126538$4843_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:126707$4851
+ cell $sshl $sshl$libresoc.v:126532$4835
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ALU_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:126707$4851_Y
+ connect \Y $sshl$libresoc.v:126532$4835_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:126708$4852
+ cell $sshl $sshl$libresoc.v:126533$4836
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \ALU_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:126708$4852_Y
+ connect \Y $sshl$libresoc.v:126533$4836_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:126710$4855
+ cell $sshl $sshl$libresoc.v:126535$4839
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \ALU_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:126710$4855_Y
+ connect \Y $sshl$libresoc.v:126535$4839_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:126711$4856
+ cell $sshl $sshl$libresoc.v:126536$4840
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \ALU_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:126711$4856_Y
+ connect \Y $sshl$libresoc.v:126536$4840_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:126712$4857
+ cell $sshl $sshl$libresoc.v:126537$4841
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:126712$4857_Y
+ connect \Y $sshl$libresoc.v:126537$4841_Y
end
- attribute \src "libresoc.v:126627.7-126627.20"
- process $proc$libresoc.v:126627$4868
+ attribute \src "libresoc.v:126452.7-126452.20"
+ process $proc$libresoc.v:126452$4852
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126715.3-126761.6"
- process $proc$libresoc.v:126715$4860
+ attribute \src "libresoc.v:126540.3-126586.6"
+ process $proc$libresoc.v:126540$4844
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:126716.5-126716.29"
+ attribute \src "libresoc.v:126541.5-126541.29"
switch \initial
- attribute \src "libresoc.v:126716.9-126716.17"
+ attribute \src "libresoc.v:126541.9-126541.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:126762.3-126808.6"
- process $proc$libresoc.v:126762$4861
+ attribute \src "libresoc.v:126587.3-126633.6"
+ process $proc$libresoc.v:126587$4845
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:126763.5-126763.29"
+ attribute \src "libresoc.v:126588.5-126588.29"
switch \initial
- attribute \src "libresoc.v:126763.9-126763.17"
+ attribute \src "libresoc.v:126588.9-126588.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:126809.3-126823.6"
- process $proc$libresoc.v:126809$4862
+ attribute \src "libresoc.v:126634.3-126648.6"
+ process $proc$libresoc.v:126634$4846
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:126810.5-126810.29"
+ attribute \src "libresoc.v:126635.5-126635.29"
switch \initial
- attribute \src "libresoc.v:126810.9-126810.17"
+ attribute \src "libresoc.v:126635.9-126635.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:126824.3-126842.6"
- process $proc$libresoc.v:126824$4863
+ attribute \src "libresoc.v:126649.3-126667.6"
+ process $proc$libresoc.v:126649$4847
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:126825.5-126825.29"
+ attribute \src "libresoc.v:126650.5-126650.29"
switch \initial
- attribute \src "libresoc.v:126825.9-126825.17"
+ attribute \src "libresoc.v:126650.9-126650.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:126843.3-126865.6"
- process $proc$libresoc.v:126843$4864
+ attribute \src "libresoc.v:126668.3-126690.6"
+ process $proc$libresoc.v:126668$4848
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:126844.5-126844.29"
+ attribute \src "libresoc.v:126669.5-126669.29"
switch \initial
- attribute \src "libresoc.v:126844.9-126844.17"
+ attribute \src "libresoc.v:126669.9-126669.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:126866.3-126892.6"
- process $proc$libresoc.v:126866$4865
+ attribute \src "libresoc.v:126691.3-126717.6"
+ process $proc$libresoc.v:126691$4849
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:126867.5-126867.29"
+ attribute \src "libresoc.v:126692.5-126692.29"
switch \initial
- attribute \src "libresoc.v:126867.9-126867.17"
+ attribute \src "libresoc.v:126692.9-126692.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:126893.3-126923.6"
- process $proc$libresoc.v:126893$4866
+ attribute \src "libresoc.v:126718.3-126748.6"
+ process $proc$libresoc.v:126718$4850
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:126894.5-126894.29"
+ attribute \src "libresoc.v:126719.5-126719.29"
switch \initial
- attribute \src "libresoc.v:126894.9-126894.17"
+ attribute \src "libresoc.v:126719.9-126719.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:126924.3-126958.6"
- process $proc$libresoc.v:126924$4867
+ attribute \src "libresoc.v:126749.3-126783.6"
+ process $proc$libresoc.v:126749$4851
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:126925.5-126925.29"
+ attribute \src "libresoc.v:126750.5-126750.29"
switch \initial
- attribute \src "libresoc.v:126925.9-126925.17"
+ attribute \src "libresoc.v:126750.9-126750.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:126705$4848_Y
- connect \$11 $pos$libresoc.v:126706$4850_Y
- connect \$14 $sshl$libresoc.v:126707$4851_Y
- connect \$17 $sshl$libresoc.v:126708$4852_Y
- connect \$1 $pos$libresoc.v:126709$4854_Y
- connect \$20 $sshl$libresoc.v:126710$4855_Y
- connect \$23 $sshl$libresoc.v:126711$4856_Y
- connect \$4 $sshl$libresoc.v:126712$4857_Y
- connect \$3 $pos$libresoc.v:126713$4859_Y
+ connect \$9 $pos$libresoc.v:126530$4832_Y
+ connect \$11 $pos$libresoc.v:126531$4834_Y
+ connect \$14 $sshl$libresoc.v:126532$4835_Y
+ connect \$17 $sshl$libresoc.v:126533$4836_Y
+ connect \$1 $pos$libresoc.v:126534$4838_Y
+ connect \$20 $sshl$libresoc.v:126535$4839_Y
+ connect \$23 $sshl$libresoc.v:126536$4840_Y
+ connect \$4 $sshl$libresoc.v:126537$4841_Y
+ connect \$3 $pos$libresoc.v:126538$4843_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:126967.1-127304.10"
+attribute \src "libresoc.v:126792.1-127129.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi"
attribute \generator "nMigen"
module \dec_bi$144
- attribute \src "libresoc.v:127234.3-127264.6"
+ attribute \src "libresoc.v:127059.3-127089.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:127265.3-127299.6"
+ attribute \src "libresoc.v:127090.3-127124.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:127056.3-127102.6"
+ attribute \src "libresoc.v:126881.3-126927.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:127103.3-127149.6"
+ attribute \src "libresoc.v:126928.3-126974.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:126968.7-126968.20"
+ attribute \src "libresoc.v:126793.7-126793.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127207.3-127233.6"
+ attribute \src "libresoc.v:127032.3-127058.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:127150.3-127164.6"
+ attribute \src "libresoc.v:126975.3-126989.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:127165.3-127183.6"
+ attribute \src "libresoc.v:126990.3-127008.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:127184.3-127206.6"
+ attribute \src "libresoc.v:127009.3-127031.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:127234.3-127264.6"
+ attribute \src "libresoc.v:127059.3-127089.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:127265.3-127299.6"
+ attribute \src "libresoc.v:127090.3-127124.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:127056.3-127102.6"
+ attribute \src "libresoc.v:126881.3-126927.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:127103.3-127149.6"
+ attribute \src "libresoc.v:126928.3-126974.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127207.3-127233.6"
+ attribute \src "libresoc.v:127032.3-127058.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:127150.3-127164.6"
+ attribute \src "libresoc.v:126975.3-126989.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:127165.3-127183.6"
+ attribute \src "libresoc.v:126990.3-127008.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:127184.3-127206.6"
+ attribute \src "libresoc.v:127009.3-127031.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:127046.17-127046.107"
- wire width 64 $extend$libresoc.v:127046$4869_Y
- attribute \src "libresoc.v:127047.18-127047.110"
- wire width 64 $extend$libresoc.v:127047$4871_Y
- attribute \src "libresoc.v:127050.17-127050.107"
- wire width 64 $extend$libresoc.v:127050$4875_Y
- attribute \src "libresoc.v:127054.17-127054.102"
- wire width 64 $extend$libresoc.v:127054$4880_Y
- attribute \src "libresoc.v:127046.17-127046.107"
- wire width 64 $pos$libresoc.v:127046$4870_Y
- attribute \src "libresoc.v:127047.18-127047.110"
- wire width 64 $pos$libresoc.v:127047$4872_Y
- attribute \src "libresoc.v:127050.17-127050.107"
- wire width 64 $pos$libresoc.v:127050$4876_Y
- attribute \src "libresoc.v:127054.17-127054.102"
- wire width 64 $pos$libresoc.v:127054$4881_Y
- attribute \src "libresoc.v:127048.18-127048.117"
- wire width 47 $sshl$libresoc.v:127048$4873_Y
- attribute \src "libresoc.v:127049.18-127049.116"
- wire width 27 $sshl$libresoc.v:127049$4874_Y
- attribute \src "libresoc.v:127051.18-127051.116"
- wire width 17 $sshl$libresoc.v:127051$4877_Y
- attribute \src "libresoc.v:127052.18-127052.116"
- wire width 17 $sshl$libresoc.v:127052$4878_Y
- attribute \src "libresoc.v:127053.17-127053.109"
- wire width 47 $sshl$libresoc.v:127053$4879_Y
+ attribute \src "libresoc.v:126871.17-126871.107"
+ wire width 64 $extend$libresoc.v:126871$4853_Y
+ attribute \src "libresoc.v:126872.18-126872.110"
+ wire width 64 $extend$libresoc.v:126872$4855_Y
+ attribute \src "libresoc.v:126875.17-126875.107"
+ wire width 64 $extend$libresoc.v:126875$4859_Y
+ attribute \src "libresoc.v:126879.17-126879.102"
+ wire width 64 $extend$libresoc.v:126879$4864_Y
+ attribute \src "libresoc.v:126871.17-126871.107"
+ wire width 64 $pos$libresoc.v:126871$4854_Y
+ attribute \src "libresoc.v:126872.18-126872.110"
+ wire width 64 $pos$libresoc.v:126872$4856_Y
+ attribute \src "libresoc.v:126875.17-126875.107"
+ wire width 64 $pos$libresoc.v:126875$4860_Y
+ attribute \src "libresoc.v:126879.17-126879.102"
+ wire width 64 $pos$libresoc.v:126879$4865_Y
+ attribute \src "libresoc.v:126873.18-126873.117"
+ wire width 47 $sshl$libresoc.v:126873$4857_Y
+ attribute \src "libresoc.v:126874.18-126874.116"
+ wire width 27 $sshl$libresoc.v:126874$4858_Y
+ attribute \src "libresoc.v:126876.18-126876.116"
+ wire width 17 $sshl$libresoc.v:126876$4861_Y
+ attribute \src "libresoc.v:126877.18-126877.116"
+ wire width 17 $sshl$libresoc.v:126877$4862_Y
+ attribute \src "libresoc.v:126878.17-126878.109"
+ wire width 47 $sshl$libresoc.v:126878$4863_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:126968.7-126968.15"
+ attribute \src "libresoc.v:126793.7-126793.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127046$4869
+ cell $pos $extend$libresoc.v:126871$4853
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \BRANCH_sh
- connect \Y $extend$libresoc.v:127046$4869_Y
+ connect \Y $extend$libresoc.v:126871$4853_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127047$4871
+ cell $pos $extend$libresoc.v:126872$4855
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \BRANCH_SH32
- connect \Y $extend$libresoc.v:127047$4871_Y
+ connect \Y $extend$libresoc.v:126872$4855_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127050$4875
+ cell $pos $extend$libresoc.v:126875$4859
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \BRANCH_UI
- connect \Y $extend$libresoc.v:127050$4875_Y
+ connect \Y $extend$libresoc.v:126875$4859_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:127054$4880
+ cell $pos $extend$libresoc.v:126879$4864
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:127054$4880_Y
+ connect \Y $extend$libresoc.v:126879$4864_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127046$4870
+ cell $pos $pos$libresoc.v:126871$4854
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127046$4869_Y
- connect \Y $pos$libresoc.v:127046$4870_Y
+ connect \A $extend$libresoc.v:126871$4853_Y
+ connect \Y $pos$libresoc.v:126871$4854_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127047$4872
+ cell $pos $pos$libresoc.v:126872$4856
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127047$4871_Y
- connect \Y $pos$libresoc.v:127047$4872_Y
+ connect \A $extend$libresoc.v:126872$4855_Y
+ connect \Y $pos$libresoc.v:126872$4856_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127050$4876
+ cell $pos $pos$libresoc.v:126875$4860
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127050$4875_Y
- connect \Y $pos$libresoc.v:127050$4876_Y
+ connect \A $extend$libresoc.v:126875$4859_Y
+ connect \Y $pos$libresoc.v:126875$4860_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:127054$4881
+ cell $pos $pos$libresoc.v:126879$4865
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127054$4880_Y
- connect \Y $pos$libresoc.v:127054$4881_Y
+ connect \A $extend$libresoc.v:126879$4864_Y
+ connect \Y $pos$libresoc.v:126879$4865_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:127048$4873
+ cell $sshl $sshl$libresoc.v:126873$4857
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \BRANCH_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127048$4873_Y
+ connect \Y $sshl$libresoc.v:126873$4857_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:127049$4874
+ cell $sshl $sshl$libresoc.v:126874$4858
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \BRANCH_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:127049$4874_Y
+ connect \Y $sshl$libresoc.v:126874$4858_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:127051$4877
+ cell $sshl $sshl$libresoc.v:126876$4861
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \BRANCH_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:127051$4877_Y
+ connect \Y $sshl$libresoc.v:126876$4861_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:127052$4878
+ cell $sshl $sshl$libresoc.v:126877$4862
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \BRANCH_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:127052$4878_Y
+ connect \Y $sshl$libresoc.v:126877$4862_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:127053$4879
+ cell $sshl $sshl$libresoc.v:126878$4863
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127053$4879_Y
+ connect \Y $sshl$libresoc.v:126878$4863_Y
end
- attribute \src "libresoc.v:126968.7-126968.20"
- process $proc$libresoc.v:126968$4890
+ attribute \src "libresoc.v:126793.7-126793.20"
+ process $proc$libresoc.v:126793$4874
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127056.3-127102.6"
- process $proc$libresoc.v:127056$4882
+ attribute \src "libresoc.v:126881.3-126927.6"
+ process $proc$libresoc.v:126881$4866
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:127057.5-127057.29"
+ attribute \src "libresoc.v:126882.5-126882.29"
switch \initial
- attribute \src "libresoc.v:127057.9-127057.17"
+ attribute \src "libresoc.v:126882.9-126882.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:127103.3-127149.6"
- process $proc$libresoc.v:127103$4883
+ attribute \src "libresoc.v:126928.3-126974.6"
+ process $proc$libresoc.v:126928$4867
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127104.5-127104.29"
+ attribute \src "libresoc.v:126929.5-126929.29"
switch \initial
- attribute \src "libresoc.v:127104.9-127104.17"
+ attribute \src "libresoc.v:126929.9-126929.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:127150.3-127164.6"
- process $proc$libresoc.v:127150$4884
+ attribute \src "libresoc.v:126975.3-126989.6"
+ process $proc$libresoc.v:126975$4868
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:127151.5-127151.29"
+ attribute \src "libresoc.v:126976.5-126976.29"
switch \initial
- attribute \src "libresoc.v:127151.9-127151.17"
+ attribute \src "libresoc.v:126976.9-126976.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:127165.3-127183.6"
- process $proc$libresoc.v:127165$4885
+ attribute \src "libresoc.v:126990.3-127008.6"
+ process $proc$libresoc.v:126990$4869
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:127166.5-127166.29"
+ attribute \src "libresoc.v:126991.5-126991.29"
switch \initial
- attribute \src "libresoc.v:127166.9-127166.17"
+ attribute \src "libresoc.v:126991.9-126991.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:127184.3-127206.6"
- process $proc$libresoc.v:127184$4886
+ attribute \src "libresoc.v:127009.3-127031.6"
+ process $proc$libresoc.v:127009$4870
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:127185.5-127185.29"
+ attribute \src "libresoc.v:127010.5-127010.29"
switch \initial
- attribute \src "libresoc.v:127185.9-127185.17"
+ attribute \src "libresoc.v:127010.9-127010.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:127207.3-127233.6"
- process $proc$libresoc.v:127207$4887
+ attribute \src "libresoc.v:127032.3-127058.6"
+ process $proc$libresoc.v:127032$4871
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:127208.5-127208.29"
+ attribute \src "libresoc.v:127033.5-127033.29"
switch \initial
- attribute \src "libresoc.v:127208.9-127208.17"
+ attribute \src "libresoc.v:127033.9-127033.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:127234.3-127264.6"
- process $proc$libresoc.v:127234$4888
+ attribute \src "libresoc.v:127059.3-127089.6"
+ process $proc$libresoc.v:127059$4872
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:127235.5-127235.29"
+ attribute \src "libresoc.v:127060.5-127060.29"
switch \initial
- attribute \src "libresoc.v:127235.9-127235.17"
+ attribute \src "libresoc.v:127060.9-127060.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:127265.3-127299.6"
- process $proc$libresoc.v:127265$4889
+ attribute \src "libresoc.v:127090.3-127124.6"
+ process $proc$libresoc.v:127090$4873
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:127266.5-127266.29"
+ attribute \src "libresoc.v:127091.5-127091.29"
switch \initial
- attribute \src "libresoc.v:127266.9-127266.17"
+ attribute \src "libresoc.v:127091.9-127091.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:127046$4870_Y
- connect \$11 $pos$libresoc.v:127047$4872_Y
- connect \$14 $sshl$libresoc.v:127048$4873_Y
- connect \$17 $sshl$libresoc.v:127049$4874_Y
- connect \$1 $pos$libresoc.v:127050$4876_Y
- connect \$20 $sshl$libresoc.v:127051$4877_Y
- connect \$23 $sshl$libresoc.v:127052$4878_Y
- connect \$4 $sshl$libresoc.v:127053$4879_Y
- connect \$3 $pos$libresoc.v:127054$4881_Y
+ connect \$9 $pos$libresoc.v:126871$4854_Y
+ connect \$11 $pos$libresoc.v:126872$4856_Y
+ connect \$14 $sshl$libresoc.v:126873$4857_Y
+ connect \$17 $sshl$libresoc.v:126874$4858_Y
+ connect \$1 $pos$libresoc.v:126875$4860_Y
+ connect \$20 $sshl$libresoc.v:126876$4861_Y
+ connect \$23 $sshl$libresoc.v:126877$4862_Y
+ connect \$4 $sshl$libresoc.v:126878$4863_Y
+ connect \$3 $pos$libresoc.v:126879$4865_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:127308.1-127645.10"
+attribute \src "libresoc.v:127133.1-127470.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi"
attribute \generator "nMigen"
module \dec_bi$149
- attribute \src "libresoc.v:127575.3-127605.6"
+ attribute \src "libresoc.v:127400.3-127430.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:127606.3-127640.6"
+ attribute \src "libresoc.v:127431.3-127465.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:127397.3-127443.6"
+ attribute \src "libresoc.v:127222.3-127268.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:127444.3-127490.6"
+ attribute \src "libresoc.v:127269.3-127315.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:127309.7-127309.20"
+ attribute \src "libresoc.v:127134.7-127134.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127548.3-127574.6"
+ attribute \src "libresoc.v:127373.3-127399.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:127491.3-127505.6"
+ attribute \src "libresoc.v:127316.3-127330.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:127506.3-127524.6"
+ attribute \src "libresoc.v:127331.3-127349.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:127525.3-127547.6"
+ attribute \src "libresoc.v:127350.3-127372.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:127575.3-127605.6"
+ attribute \src "libresoc.v:127400.3-127430.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:127606.3-127640.6"
+ attribute \src "libresoc.v:127431.3-127465.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:127397.3-127443.6"
+ attribute \src "libresoc.v:127222.3-127268.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:127444.3-127490.6"
+ attribute \src "libresoc.v:127269.3-127315.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127548.3-127574.6"
+ attribute \src "libresoc.v:127373.3-127399.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:127491.3-127505.6"
+ attribute \src "libresoc.v:127316.3-127330.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:127506.3-127524.6"
+ attribute \src "libresoc.v:127331.3-127349.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:127525.3-127547.6"
+ attribute \src "libresoc.v:127350.3-127372.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:127387.17-127387.108"
- wire width 64 $extend$libresoc.v:127387$4891_Y
- attribute \src "libresoc.v:127388.18-127388.111"
- wire width 64 $extend$libresoc.v:127388$4893_Y
- attribute \src "libresoc.v:127391.17-127391.108"
- wire width 64 $extend$libresoc.v:127391$4897_Y
- attribute \src "libresoc.v:127395.17-127395.102"
- wire width 64 $extend$libresoc.v:127395$4902_Y
- attribute \src "libresoc.v:127387.17-127387.108"
- wire width 64 $pos$libresoc.v:127387$4892_Y
- attribute \src "libresoc.v:127388.18-127388.111"
- wire width 64 $pos$libresoc.v:127388$4894_Y
- attribute \src "libresoc.v:127391.17-127391.108"
- wire width 64 $pos$libresoc.v:127391$4898_Y
- attribute \src "libresoc.v:127395.17-127395.102"
- wire width 64 $pos$libresoc.v:127395$4903_Y
- attribute \src "libresoc.v:127389.18-127389.118"
- wire width 47 $sshl$libresoc.v:127389$4895_Y
- attribute \src "libresoc.v:127390.18-127390.117"
- wire width 27 $sshl$libresoc.v:127390$4896_Y
- attribute \src "libresoc.v:127392.18-127392.117"
- wire width 17 $sshl$libresoc.v:127392$4899_Y
- attribute \src "libresoc.v:127393.18-127393.117"
- wire width 17 $sshl$libresoc.v:127393$4900_Y
- attribute \src "libresoc.v:127394.17-127394.109"
- wire width 47 $sshl$libresoc.v:127394$4901_Y
+ attribute \src "libresoc.v:127212.17-127212.108"
+ wire width 64 $extend$libresoc.v:127212$4875_Y
+ attribute \src "libresoc.v:127213.18-127213.111"
+ wire width 64 $extend$libresoc.v:127213$4877_Y
+ attribute \src "libresoc.v:127216.17-127216.108"
+ wire width 64 $extend$libresoc.v:127216$4881_Y
+ attribute \src "libresoc.v:127220.17-127220.102"
+ wire width 64 $extend$libresoc.v:127220$4886_Y
+ attribute \src "libresoc.v:127212.17-127212.108"
+ wire width 64 $pos$libresoc.v:127212$4876_Y
+ attribute \src "libresoc.v:127213.18-127213.111"
+ wire width 64 $pos$libresoc.v:127213$4878_Y
+ attribute \src "libresoc.v:127216.17-127216.108"
+ wire width 64 $pos$libresoc.v:127216$4882_Y
+ attribute \src "libresoc.v:127220.17-127220.102"
+ wire width 64 $pos$libresoc.v:127220$4887_Y
+ attribute \src "libresoc.v:127214.18-127214.118"
+ wire width 47 $sshl$libresoc.v:127214$4879_Y
+ attribute \src "libresoc.v:127215.18-127215.117"
+ wire width 27 $sshl$libresoc.v:127215$4880_Y
+ attribute \src "libresoc.v:127217.18-127217.117"
+ wire width 17 $sshl$libresoc.v:127217$4883_Y
+ attribute \src "libresoc.v:127218.18-127218.117"
+ wire width 17 $sshl$libresoc.v:127218$4884_Y
+ attribute \src "libresoc.v:127219.17-127219.109"
+ wire width 47 $sshl$libresoc.v:127219$4885_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:127309.7-127309.15"
+ attribute \src "libresoc.v:127134.7-127134.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127387$4891
+ cell $pos $extend$libresoc.v:127212$4875
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \LOGICAL_sh
- connect \Y $extend$libresoc.v:127387$4891_Y
+ connect \Y $extend$libresoc.v:127212$4875_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127388$4893
+ cell $pos $extend$libresoc.v:127213$4877
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \LOGICAL_SH32
- connect \Y $extend$libresoc.v:127388$4893_Y
+ connect \Y $extend$libresoc.v:127213$4877_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127391$4897
+ cell $pos $extend$libresoc.v:127216$4881
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \LOGICAL_UI
- connect \Y $extend$libresoc.v:127391$4897_Y
+ connect \Y $extend$libresoc.v:127216$4881_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:127395$4902
+ cell $pos $extend$libresoc.v:127220$4886
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:127395$4902_Y
+ connect \Y $extend$libresoc.v:127220$4886_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127387$4892
+ cell $pos $pos$libresoc.v:127212$4876
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127387$4891_Y
- connect \Y $pos$libresoc.v:127387$4892_Y
+ connect \A $extend$libresoc.v:127212$4875_Y
+ connect \Y $pos$libresoc.v:127212$4876_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127388$4894
+ cell $pos $pos$libresoc.v:127213$4878
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127388$4893_Y
- connect \Y $pos$libresoc.v:127388$4894_Y
+ connect \A $extend$libresoc.v:127213$4877_Y
+ connect \Y $pos$libresoc.v:127213$4878_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127391$4898
+ cell $pos $pos$libresoc.v:127216$4882
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127391$4897_Y
- connect \Y $pos$libresoc.v:127391$4898_Y
+ connect \A $extend$libresoc.v:127216$4881_Y
+ connect \Y $pos$libresoc.v:127216$4882_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:127395$4903
+ cell $pos $pos$libresoc.v:127220$4887
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127395$4902_Y
- connect \Y $pos$libresoc.v:127395$4903_Y
+ connect \A $extend$libresoc.v:127220$4886_Y
+ connect \Y $pos$libresoc.v:127220$4887_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:127389$4895
+ cell $sshl $sshl$libresoc.v:127214$4879
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \LOGICAL_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127389$4895_Y
+ connect \Y $sshl$libresoc.v:127214$4879_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:127390$4896
+ cell $sshl $sshl$libresoc.v:127215$4880
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \LOGICAL_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:127390$4896_Y
+ connect \Y $sshl$libresoc.v:127215$4880_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:127392$4899
+ cell $sshl $sshl$libresoc.v:127217$4883
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LOGICAL_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:127392$4899_Y
+ connect \Y $sshl$libresoc.v:127217$4883_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:127393$4900
+ cell $sshl $sshl$libresoc.v:127218$4884
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LOGICAL_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:127393$4900_Y
+ connect \Y $sshl$libresoc.v:127218$4884_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:127394$4901
+ cell $sshl $sshl$libresoc.v:127219$4885
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127394$4901_Y
+ connect \Y $sshl$libresoc.v:127219$4885_Y
end
- attribute \src "libresoc.v:127309.7-127309.20"
- process $proc$libresoc.v:127309$4912
+ attribute \src "libresoc.v:127134.7-127134.20"
+ process $proc$libresoc.v:127134$4896
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127397.3-127443.6"
- process $proc$libresoc.v:127397$4904
+ attribute \src "libresoc.v:127222.3-127268.6"
+ process $proc$libresoc.v:127222$4888
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:127398.5-127398.29"
+ attribute \src "libresoc.v:127223.5-127223.29"
switch \initial
- attribute \src "libresoc.v:127398.9-127398.17"
+ attribute \src "libresoc.v:127223.9-127223.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:127444.3-127490.6"
- process $proc$libresoc.v:127444$4905
+ attribute \src "libresoc.v:127269.3-127315.6"
+ process $proc$libresoc.v:127269$4889
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127445.5-127445.29"
+ attribute \src "libresoc.v:127270.5-127270.29"
switch \initial
- attribute \src "libresoc.v:127445.9-127445.17"
+ attribute \src "libresoc.v:127270.9-127270.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:127491.3-127505.6"
- process $proc$libresoc.v:127491$4906
+ attribute \src "libresoc.v:127316.3-127330.6"
+ process $proc$libresoc.v:127316$4890
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:127492.5-127492.29"
+ attribute \src "libresoc.v:127317.5-127317.29"
switch \initial
- attribute \src "libresoc.v:127492.9-127492.17"
+ attribute \src "libresoc.v:127317.9-127317.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:127506.3-127524.6"
- process $proc$libresoc.v:127506$4907
+ attribute \src "libresoc.v:127331.3-127349.6"
+ process $proc$libresoc.v:127331$4891
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:127507.5-127507.29"
+ attribute \src "libresoc.v:127332.5-127332.29"
switch \initial
- attribute \src "libresoc.v:127507.9-127507.17"
+ attribute \src "libresoc.v:127332.9-127332.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:127525.3-127547.6"
- process $proc$libresoc.v:127525$4908
+ attribute \src "libresoc.v:127350.3-127372.6"
+ process $proc$libresoc.v:127350$4892
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:127526.5-127526.29"
+ attribute \src "libresoc.v:127351.5-127351.29"
switch \initial
- attribute \src "libresoc.v:127526.9-127526.17"
+ attribute \src "libresoc.v:127351.9-127351.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:127548.3-127574.6"
- process $proc$libresoc.v:127548$4909
+ attribute \src "libresoc.v:127373.3-127399.6"
+ process $proc$libresoc.v:127373$4893
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:127549.5-127549.29"
+ attribute \src "libresoc.v:127374.5-127374.29"
switch \initial
- attribute \src "libresoc.v:127549.9-127549.17"
+ attribute \src "libresoc.v:127374.9-127374.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:127575.3-127605.6"
- process $proc$libresoc.v:127575$4910
+ attribute \src "libresoc.v:127400.3-127430.6"
+ process $proc$libresoc.v:127400$4894
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:127576.5-127576.29"
+ attribute \src "libresoc.v:127401.5-127401.29"
switch \initial
- attribute \src "libresoc.v:127576.9-127576.17"
+ attribute \src "libresoc.v:127401.9-127401.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:127606.3-127640.6"
- process $proc$libresoc.v:127606$4911
+ attribute \src "libresoc.v:127431.3-127465.6"
+ process $proc$libresoc.v:127431$4895
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:127607.5-127607.29"
+ attribute \src "libresoc.v:127432.5-127432.29"
switch \initial
- attribute \src "libresoc.v:127607.9-127607.17"
+ attribute \src "libresoc.v:127432.9-127432.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:127387$4892_Y
- connect \$11 $pos$libresoc.v:127388$4894_Y
- connect \$14 $sshl$libresoc.v:127389$4895_Y
- connect \$17 $sshl$libresoc.v:127390$4896_Y
- connect \$1 $pos$libresoc.v:127391$4898_Y
- connect \$20 $sshl$libresoc.v:127392$4899_Y
- connect \$23 $sshl$libresoc.v:127393$4900_Y
- connect \$4 $sshl$libresoc.v:127394$4901_Y
- connect \$3 $pos$libresoc.v:127395$4903_Y
+ connect \$9 $pos$libresoc.v:127212$4876_Y
+ connect \$11 $pos$libresoc.v:127213$4878_Y
+ connect \$14 $sshl$libresoc.v:127214$4879_Y
+ connect \$17 $sshl$libresoc.v:127215$4880_Y
+ connect \$1 $pos$libresoc.v:127216$4882_Y
+ connect \$20 $sshl$libresoc.v:127217$4883_Y
+ connect \$23 $sshl$libresoc.v:127218$4884_Y
+ connect \$4 $sshl$libresoc.v:127219$4885_Y
+ connect \$3 $pos$libresoc.v:127220$4887_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:127649.1-127986.10"
+attribute \src "libresoc.v:127474.1-127811.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi"
attribute \generator "nMigen"
module \dec_bi$157
- attribute \src "libresoc.v:127916.3-127946.6"
+ attribute \src "libresoc.v:127741.3-127771.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:127947.3-127981.6"
+ attribute \src "libresoc.v:127772.3-127806.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:127738.3-127784.6"
+ attribute \src "libresoc.v:127563.3-127609.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:127785.3-127831.6"
+ attribute \src "libresoc.v:127610.3-127656.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:127650.7-127650.20"
+ attribute \src "libresoc.v:127475.7-127475.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127889.3-127915.6"
+ attribute \src "libresoc.v:127714.3-127740.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:127832.3-127846.6"
+ attribute \src "libresoc.v:127657.3-127671.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:127847.3-127865.6"
+ attribute \src "libresoc.v:127672.3-127690.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:127866.3-127888.6"
+ attribute \src "libresoc.v:127691.3-127713.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:127916.3-127946.6"
+ attribute \src "libresoc.v:127741.3-127771.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:127947.3-127981.6"
+ attribute \src "libresoc.v:127772.3-127806.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:127738.3-127784.6"
+ attribute \src "libresoc.v:127563.3-127609.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:127785.3-127831.6"
+ attribute \src "libresoc.v:127610.3-127656.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127889.3-127915.6"
+ attribute \src "libresoc.v:127714.3-127740.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:127832.3-127846.6"
+ attribute \src "libresoc.v:127657.3-127671.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:127847.3-127865.6"
+ attribute \src "libresoc.v:127672.3-127690.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:127866.3-127888.6"
+ attribute \src "libresoc.v:127691.3-127713.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:127728.17-127728.104"
- wire width 64 $extend$libresoc.v:127728$4913_Y
- attribute \src "libresoc.v:127729.18-127729.107"
- wire width 64 $extend$libresoc.v:127729$4915_Y
- attribute \src "libresoc.v:127732.17-127732.104"
- wire width 64 $extend$libresoc.v:127732$4919_Y
- attribute \src "libresoc.v:127736.17-127736.102"
- wire width 64 $extend$libresoc.v:127736$4924_Y
- attribute \src "libresoc.v:127728.17-127728.104"
- wire width 64 $pos$libresoc.v:127728$4914_Y
- attribute \src "libresoc.v:127729.18-127729.107"
- wire width 64 $pos$libresoc.v:127729$4916_Y
- attribute \src "libresoc.v:127732.17-127732.104"
- wire width 64 $pos$libresoc.v:127732$4920_Y
- attribute \src "libresoc.v:127736.17-127736.102"
- wire width 64 $pos$libresoc.v:127736$4925_Y
- attribute \src "libresoc.v:127730.18-127730.114"
- wire width 47 $sshl$libresoc.v:127730$4917_Y
- attribute \src "libresoc.v:127731.18-127731.113"
- wire width 27 $sshl$libresoc.v:127731$4918_Y
- attribute \src "libresoc.v:127733.18-127733.113"
- wire width 17 $sshl$libresoc.v:127733$4921_Y
- attribute \src "libresoc.v:127734.18-127734.113"
- wire width 17 $sshl$libresoc.v:127734$4922_Y
- attribute \src "libresoc.v:127735.17-127735.109"
- wire width 47 $sshl$libresoc.v:127735$4923_Y
+ attribute \src "libresoc.v:127553.17-127553.104"
+ wire width 64 $extend$libresoc.v:127553$4897_Y
+ attribute \src "libresoc.v:127554.18-127554.107"
+ wire width 64 $extend$libresoc.v:127554$4899_Y
+ attribute \src "libresoc.v:127557.17-127557.104"
+ wire width 64 $extend$libresoc.v:127557$4903_Y
+ attribute \src "libresoc.v:127561.17-127561.102"
+ wire width 64 $extend$libresoc.v:127561$4908_Y
+ attribute \src "libresoc.v:127553.17-127553.104"
+ wire width 64 $pos$libresoc.v:127553$4898_Y
+ attribute \src "libresoc.v:127554.18-127554.107"
+ wire width 64 $pos$libresoc.v:127554$4900_Y
+ attribute \src "libresoc.v:127557.17-127557.104"
+ wire width 64 $pos$libresoc.v:127557$4904_Y
+ attribute \src "libresoc.v:127561.17-127561.102"
+ wire width 64 $pos$libresoc.v:127561$4909_Y
+ attribute \src "libresoc.v:127555.18-127555.114"
+ wire width 47 $sshl$libresoc.v:127555$4901_Y
+ attribute \src "libresoc.v:127556.18-127556.113"
+ wire width 27 $sshl$libresoc.v:127556$4902_Y
+ attribute \src "libresoc.v:127558.18-127558.113"
+ wire width 17 $sshl$libresoc.v:127558$4905_Y
+ attribute \src "libresoc.v:127559.18-127559.113"
+ wire width 17 $sshl$libresoc.v:127559$4906_Y
+ attribute \src "libresoc.v:127560.17-127560.109"
+ wire width 47 $sshl$libresoc.v:127560$4907_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:127650.7-127650.15"
+ attribute \src "libresoc.v:127475.7-127475.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127728$4913
+ cell $pos $extend$libresoc.v:127553$4897
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \DIV_sh
- connect \Y $extend$libresoc.v:127728$4913_Y
+ connect \Y $extend$libresoc.v:127553$4897_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127729$4915
+ cell $pos $extend$libresoc.v:127554$4899
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \DIV_SH32
- connect \Y $extend$libresoc.v:127729$4915_Y
+ connect \Y $extend$libresoc.v:127554$4899_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:127732$4919
+ cell $pos $extend$libresoc.v:127557$4903
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \DIV_UI
- connect \Y $extend$libresoc.v:127732$4919_Y
+ connect \Y $extend$libresoc.v:127557$4903_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:127736$4924
+ cell $pos $extend$libresoc.v:127561$4908
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:127736$4924_Y
+ connect \Y $extend$libresoc.v:127561$4908_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127728$4914
+ cell $pos $pos$libresoc.v:127553$4898
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127728$4913_Y
- connect \Y $pos$libresoc.v:127728$4914_Y
+ connect \A $extend$libresoc.v:127553$4897_Y
+ connect \Y $pos$libresoc.v:127553$4898_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127729$4916
+ cell $pos $pos$libresoc.v:127554$4900
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127729$4915_Y
- connect \Y $pos$libresoc.v:127729$4916_Y
+ connect \A $extend$libresoc.v:127554$4899_Y
+ connect \Y $pos$libresoc.v:127554$4900_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:127732$4920
+ cell $pos $pos$libresoc.v:127557$4904
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127732$4919_Y
- connect \Y $pos$libresoc.v:127732$4920_Y
+ connect \A $extend$libresoc.v:127557$4903_Y
+ connect \Y $pos$libresoc.v:127557$4904_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:127736$4925
+ cell $pos $pos$libresoc.v:127561$4909
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:127736$4924_Y
- connect \Y $pos$libresoc.v:127736$4925_Y
+ connect \A $extend$libresoc.v:127561$4908_Y
+ connect \Y $pos$libresoc.v:127561$4909_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:127730$4917
+ cell $sshl $sshl$libresoc.v:127555$4901
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \DIV_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127730$4917_Y
+ connect \Y $sshl$libresoc.v:127555$4901_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:127731$4918
+ cell $sshl $sshl$libresoc.v:127556$4902
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \DIV_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:127731$4918_Y
+ connect \Y $sshl$libresoc.v:127556$4902_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:127733$4921
+ cell $sshl $sshl$libresoc.v:127558$4905
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \DIV_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:127733$4921_Y
+ connect \Y $sshl$libresoc.v:127558$4905_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:127734$4922
+ cell $sshl $sshl$libresoc.v:127559$4906
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \DIV_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:127734$4922_Y
+ connect \Y $sshl$libresoc.v:127559$4906_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:127735$4923
+ cell $sshl $sshl$libresoc.v:127560$4907
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:127735$4923_Y
+ connect \Y $sshl$libresoc.v:127560$4907_Y
end
- attribute \src "libresoc.v:127650.7-127650.20"
- process $proc$libresoc.v:127650$4934
+ attribute \src "libresoc.v:127475.7-127475.20"
+ process $proc$libresoc.v:127475$4918
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127738.3-127784.6"
- process $proc$libresoc.v:127738$4926
+ attribute \src "libresoc.v:127563.3-127609.6"
+ process $proc$libresoc.v:127563$4910
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:127739.5-127739.29"
+ attribute \src "libresoc.v:127564.5-127564.29"
switch \initial
- attribute \src "libresoc.v:127739.9-127739.17"
+ attribute \src "libresoc.v:127564.9-127564.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:127785.3-127831.6"
- process $proc$libresoc.v:127785$4927
+ attribute \src "libresoc.v:127610.3-127656.6"
+ process $proc$libresoc.v:127610$4911
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:127786.5-127786.29"
+ attribute \src "libresoc.v:127611.5-127611.29"
switch \initial
- attribute \src "libresoc.v:127786.9-127786.17"
+ attribute \src "libresoc.v:127611.9-127611.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:127832.3-127846.6"
- process $proc$libresoc.v:127832$4928
+ attribute \src "libresoc.v:127657.3-127671.6"
+ process $proc$libresoc.v:127657$4912
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:127833.5-127833.29"
+ attribute \src "libresoc.v:127658.5-127658.29"
switch \initial
- attribute \src "libresoc.v:127833.9-127833.17"
+ attribute \src "libresoc.v:127658.9-127658.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:127847.3-127865.6"
- process $proc$libresoc.v:127847$4929
+ attribute \src "libresoc.v:127672.3-127690.6"
+ process $proc$libresoc.v:127672$4913
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:127848.5-127848.29"
+ attribute \src "libresoc.v:127673.5-127673.29"
switch \initial
- attribute \src "libresoc.v:127848.9-127848.17"
+ attribute \src "libresoc.v:127673.9-127673.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:127866.3-127888.6"
- process $proc$libresoc.v:127866$4930
+ attribute \src "libresoc.v:127691.3-127713.6"
+ process $proc$libresoc.v:127691$4914
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:127867.5-127867.29"
+ attribute \src "libresoc.v:127692.5-127692.29"
switch \initial
- attribute \src "libresoc.v:127867.9-127867.17"
+ attribute \src "libresoc.v:127692.9-127692.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:127889.3-127915.6"
- process $proc$libresoc.v:127889$4931
+ attribute \src "libresoc.v:127714.3-127740.6"
+ process $proc$libresoc.v:127714$4915
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:127890.5-127890.29"
+ attribute \src "libresoc.v:127715.5-127715.29"
switch \initial
- attribute \src "libresoc.v:127890.9-127890.17"
+ attribute \src "libresoc.v:127715.9-127715.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:127916.3-127946.6"
- process $proc$libresoc.v:127916$4932
+ attribute \src "libresoc.v:127741.3-127771.6"
+ process $proc$libresoc.v:127741$4916
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:127917.5-127917.29"
+ attribute \src "libresoc.v:127742.5-127742.29"
switch \initial
- attribute \src "libresoc.v:127917.9-127917.17"
+ attribute \src "libresoc.v:127742.9-127742.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:127947.3-127981.6"
- process $proc$libresoc.v:127947$4933
+ attribute \src "libresoc.v:127772.3-127806.6"
+ process $proc$libresoc.v:127772$4917
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:127948.5-127948.29"
+ attribute \src "libresoc.v:127773.5-127773.29"
switch \initial
- attribute \src "libresoc.v:127948.9-127948.17"
+ attribute \src "libresoc.v:127773.9-127773.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:127728$4914_Y
- connect \$11 $pos$libresoc.v:127729$4916_Y
- connect \$14 $sshl$libresoc.v:127730$4917_Y
- connect \$17 $sshl$libresoc.v:127731$4918_Y
- connect \$1 $pos$libresoc.v:127732$4920_Y
- connect \$20 $sshl$libresoc.v:127733$4921_Y
- connect \$23 $sshl$libresoc.v:127734$4922_Y
- connect \$4 $sshl$libresoc.v:127735$4923_Y
- connect \$3 $pos$libresoc.v:127736$4925_Y
+ connect \$9 $pos$libresoc.v:127553$4898_Y
+ connect \$11 $pos$libresoc.v:127554$4900_Y
+ connect \$14 $sshl$libresoc.v:127555$4901_Y
+ connect \$17 $sshl$libresoc.v:127556$4902_Y
+ connect \$1 $pos$libresoc.v:127557$4904_Y
+ connect \$20 $sshl$libresoc.v:127558$4905_Y
+ connect \$23 $sshl$libresoc.v:127559$4906_Y
+ connect \$4 $sshl$libresoc.v:127560$4907_Y
+ connect \$3 $pos$libresoc.v:127561$4909_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:127990.1-128327.10"
+attribute \src "libresoc.v:127815.1-128152.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi"
attribute \generator "nMigen"
module \dec_bi$161
- attribute \src "libresoc.v:128257.3-128287.6"
+ attribute \src "libresoc.v:128082.3-128112.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:128288.3-128322.6"
+ attribute \src "libresoc.v:128113.3-128147.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:128079.3-128125.6"
+ attribute \src "libresoc.v:127904.3-127950.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:128126.3-128172.6"
+ attribute \src "libresoc.v:127951.3-127997.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:127991.7-127991.20"
+ attribute \src "libresoc.v:127816.7-127816.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128230.3-128256.6"
+ attribute \src "libresoc.v:128055.3-128081.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:128173.3-128187.6"
+ attribute \src "libresoc.v:127998.3-128012.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:128188.3-128206.6"
+ attribute \src "libresoc.v:128013.3-128031.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:128207.3-128229.6"
+ attribute \src "libresoc.v:128032.3-128054.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:128257.3-128287.6"
+ attribute \src "libresoc.v:128082.3-128112.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:128288.3-128322.6"
+ attribute \src "libresoc.v:128113.3-128147.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:128079.3-128125.6"
+ attribute \src "libresoc.v:127904.3-127950.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:128126.3-128172.6"
+ attribute \src "libresoc.v:127951.3-127997.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128230.3-128256.6"
+ attribute \src "libresoc.v:128055.3-128081.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:128173.3-128187.6"
+ attribute \src "libresoc.v:127998.3-128012.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:128188.3-128206.6"
+ attribute \src "libresoc.v:128013.3-128031.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:128207.3-128229.6"
+ attribute \src "libresoc.v:128032.3-128054.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:128069.17-128069.104"
- wire width 64 $extend$libresoc.v:128069$4935_Y
- attribute \src "libresoc.v:128070.18-128070.107"
- wire width 64 $extend$libresoc.v:128070$4937_Y
- attribute \src "libresoc.v:128073.17-128073.104"
- wire width 64 $extend$libresoc.v:128073$4941_Y
- attribute \src "libresoc.v:128077.17-128077.102"
- wire width 64 $extend$libresoc.v:128077$4946_Y
- attribute \src "libresoc.v:128069.17-128069.104"
- wire width 64 $pos$libresoc.v:128069$4936_Y
- attribute \src "libresoc.v:128070.18-128070.107"
- wire width 64 $pos$libresoc.v:128070$4938_Y
- attribute \src "libresoc.v:128073.17-128073.104"
- wire width 64 $pos$libresoc.v:128073$4942_Y
- attribute \src "libresoc.v:128077.17-128077.102"
- wire width 64 $pos$libresoc.v:128077$4947_Y
- attribute \src "libresoc.v:128071.18-128071.114"
- wire width 47 $sshl$libresoc.v:128071$4939_Y
- attribute \src "libresoc.v:128072.18-128072.113"
- wire width 27 $sshl$libresoc.v:128072$4940_Y
- attribute \src "libresoc.v:128074.18-128074.113"
- wire width 17 $sshl$libresoc.v:128074$4943_Y
- attribute \src "libresoc.v:128075.18-128075.113"
- wire width 17 $sshl$libresoc.v:128075$4944_Y
- attribute \src "libresoc.v:128076.17-128076.109"
- wire width 47 $sshl$libresoc.v:128076$4945_Y
+ attribute \src "libresoc.v:127894.17-127894.104"
+ wire width 64 $extend$libresoc.v:127894$4919_Y
+ attribute \src "libresoc.v:127895.18-127895.107"
+ wire width 64 $extend$libresoc.v:127895$4921_Y
+ attribute \src "libresoc.v:127898.17-127898.104"
+ wire width 64 $extend$libresoc.v:127898$4925_Y
+ attribute \src "libresoc.v:127902.17-127902.102"
+ wire width 64 $extend$libresoc.v:127902$4930_Y
+ attribute \src "libresoc.v:127894.17-127894.104"
+ wire width 64 $pos$libresoc.v:127894$4920_Y
+ attribute \src "libresoc.v:127895.18-127895.107"
+ wire width 64 $pos$libresoc.v:127895$4922_Y
+ attribute \src "libresoc.v:127898.17-127898.104"
+ wire width 64 $pos$libresoc.v:127898$4926_Y
+ attribute \src "libresoc.v:127902.17-127902.102"
+ wire width 64 $pos$libresoc.v:127902$4931_Y
+ attribute \src "libresoc.v:127896.18-127896.114"
+ wire width 47 $sshl$libresoc.v:127896$4923_Y
+ attribute \src "libresoc.v:127897.18-127897.113"
+ wire width 27 $sshl$libresoc.v:127897$4924_Y
+ attribute \src "libresoc.v:127899.18-127899.113"
+ wire width 17 $sshl$libresoc.v:127899$4927_Y
+ attribute \src "libresoc.v:127900.18-127900.113"
+ wire width 17 $sshl$libresoc.v:127900$4928_Y
+ attribute \src "libresoc.v:127901.17-127901.109"
+ wire width 47 $sshl$libresoc.v:127901$4929_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:127991.7-127991.15"
+ attribute \src "libresoc.v:127816.7-127816.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128069$4935
+ cell $pos $extend$libresoc.v:127894$4919
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \MUL_sh
- connect \Y $extend$libresoc.v:128069$4935_Y
+ connect \Y $extend$libresoc.v:127894$4919_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128070$4937
+ cell $pos $extend$libresoc.v:127895$4921
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \MUL_SH32
- connect \Y $extend$libresoc.v:128070$4937_Y
+ connect \Y $extend$libresoc.v:127895$4921_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128073$4941
+ cell $pos $extend$libresoc.v:127898$4925
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \MUL_UI
- connect \Y $extend$libresoc.v:128073$4941_Y
+ connect \Y $extend$libresoc.v:127898$4925_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:128077$4946
+ cell $pos $extend$libresoc.v:127902$4930
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:128077$4946_Y
+ connect \Y $extend$libresoc.v:127902$4930_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128069$4936
+ cell $pos $pos$libresoc.v:127894$4920
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128069$4935_Y
- connect \Y $pos$libresoc.v:128069$4936_Y
+ connect \A $extend$libresoc.v:127894$4919_Y
+ connect \Y $pos$libresoc.v:127894$4920_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128070$4938
+ cell $pos $pos$libresoc.v:127895$4922
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128070$4937_Y
- connect \Y $pos$libresoc.v:128070$4938_Y
+ connect \A $extend$libresoc.v:127895$4921_Y
+ connect \Y $pos$libresoc.v:127895$4922_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128073$4942
+ cell $pos $pos$libresoc.v:127898$4926
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128073$4941_Y
- connect \Y $pos$libresoc.v:128073$4942_Y
+ connect \A $extend$libresoc.v:127898$4925_Y
+ connect \Y $pos$libresoc.v:127898$4926_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:128077$4947
+ cell $pos $pos$libresoc.v:127902$4931
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128077$4946_Y
- connect \Y $pos$libresoc.v:128077$4947_Y
+ connect \A $extend$libresoc.v:127902$4930_Y
+ connect \Y $pos$libresoc.v:127902$4931_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:128071$4939
+ cell $sshl $sshl$libresoc.v:127896$4923
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \MUL_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128071$4939_Y
+ connect \Y $sshl$libresoc.v:127896$4923_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:128072$4940
+ cell $sshl $sshl$libresoc.v:127897$4924
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \MUL_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:128072$4940_Y
+ connect \Y $sshl$libresoc.v:127897$4924_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:128074$4943
+ cell $sshl $sshl$libresoc.v:127899$4927
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \MUL_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:128074$4943_Y
+ connect \Y $sshl$libresoc.v:127899$4927_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:128075$4944
+ cell $sshl $sshl$libresoc.v:127900$4928
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \MUL_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:128075$4944_Y
+ connect \Y $sshl$libresoc.v:127900$4928_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:128076$4945
+ cell $sshl $sshl$libresoc.v:127901$4929
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128076$4945_Y
+ connect \Y $sshl$libresoc.v:127901$4929_Y
end
- attribute \src "libresoc.v:127991.7-127991.20"
- process $proc$libresoc.v:127991$4956
+ attribute \src "libresoc.v:127816.7-127816.20"
+ process $proc$libresoc.v:127816$4940
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128079.3-128125.6"
- process $proc$libresoc.v:128079$4948
+ attribute \src "libresoc.v:127904.3-127950.6"
+ process $proc$libresoc.v:127904$4932
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:128080.5-128080.29"
+ attribute \src "libresoc.v:127905.5-127905.29"
switch \initial
- attribute \src "libresoc.v:128080.9-128080.17"
+ attribute \src "libresoc.v:127905.9-127905.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:128126.3-128172.6"
- process $proc$libresoc.v:128126$4949
+ attribute \src "libresoc.v:127951.3-127997.6"
+ process $proc$libresoc.v:127951$4933
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128127.5-128127.29"
+ attribute \src "libresoc.v:127952.5-127952.29"
switch \initial
- attribute \src "libresoc.v:128127.9-128127.17"
+ attribute \src "libresoc.v:127952.9-127952.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:128173.3-128187.6"
- process $proc$libresoc.v:128173$4950
+ attribute \src "libresoc.v:127998.3-128012.6"
+ process $proc$libresoc.v:127998$4934
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:128174.5-128174.29"
+ attribute \src "libresoc.v:127999.5-127999.29"
switch \initial
- attribute \src "libresoc.v:128174.9-128174.17"
+ attribute \src "libresoc.v:127999.9-127999.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:128188.3-128206.6"
- process $proc$libresoc.v:128188$4951
+ attribute \src "libresoc.v:128013.3-128031.6"
+ process $proc$libresoc.v:128013$4935
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:128189.5-128189.29"
+ attribute \src "libresoc.v:128014.5-128014.29"
switch \initial
- attribute \src "libresoc.v:128189.9-128189.17"
+ attribute \src "libresoc.v:128014.9-128014.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:128207.3-128229.6"
- process $proc$libresoc.v:128207$4952
+ attribute \src "libresoc.v:128032.3-128054.6"
+ process $proc$libresoc.v:128032$4936
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:128208.5-128208.29"
+ attribute \src "libresoc.v:128033.5-128033.29"
switch \initial
- attribute \src "libresoc.v:128208.9-128208.17"
+ attribute \src "libresoc.v:128033.9-128033.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:128230.3-128256.6"
- process $proc$libresoc.v:128230$4953
+ attribute \src "libresoc.v:128055.3-128081.6"
+ process $proc$libresoc.v:128055$4937
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:128231.5-128231.29"
+ attribute \src "libresoc.v:128056.5-128056.29"
switch \initial
- attribute \src "libresoc.v:128231.9-128231.17"
+ attribute \src "libresoc.v:128056.9-128056.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:128257.3-128287.6"
- process $proc$libresoc.v:128257$4954
+ attribute \src "libresoc.v:128082.3-128112.6"
+ process $proc$libresoc.v:128082$4938
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:128258.5-128258.29"
+ attribute \src "libresoc.v:128083.5-128083.29"
switch \initial
- attribute \src "libresoc.v:128258.9-128258.17"
+ attribute \src "libresoc.v:128083.9-128083.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:128288.3-128322.6"
- process $proc$libresoc.v:128288$4955
+ attribute \src "libresoc.v:128113.3-128147.6"
+ process $proc$libresoc.v:128113$4939
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:128289.5-128289.29"
+ attribute \src "libresoc.v:128114.5-128114.29"
switch \initial
- attribute \src "libresoc.v:128289.9-128289.17"
+ attribute \src "libresoc.v:128114.9-128114.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:128069$4936_Y
- connect \$11 $pos$libresoc.v:128070$4938_Y
- connect \$14 $sshl$libresoc.v:128071$4939_Y
- connect \$17 $sshl$libresoc.v:128072$4940_Y
- connect \$1 $pos$libresoc.v:128073$4942_Y
- connect \$20 $sshl$libresoc.v:128074$4943_Y
- connect \$23 $sshl$libresoc.v:128075$4944_Y
- connect \$4 $sshl$libresoc.v:128076$4945_Y
- connect \$3 $pos$libresoc.v:128077$4947_Y
+ connect \$9 $pos$libresoc.v:127894$4920_Y
+ connect \$11 $pos$libresoc.v:127895$4922_Y
+ connect \$14 $sshl$libresoc.v:127896$4923_Y
+ connect \$17 $sshl$libresoc.v:127897$4924_Y
+ connect \$1 $pos$libresoc.v:127898$4926_Y
+ connect \$20 $sshl$libresoc.v:127899$4927_Y
+ connect \$23 $sshl$libresoc.v:127900$4928_Y
+ connect \$4 $sshl$libresoc.v:127901$4929_Y
+ connect \$3 $pos$libresoc.v:127902$4931_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:128331.1-128668.10"
+attribute \src "libresoc.v:128156.1-128493.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi"
attribute \generator "nMigen"
module \dec_bi$165
- attribute \src "libresoc.v:128598.3-128628.6"
+ attribute \src "libresoc.v:128423.3-128453.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:128629.3-128663.6"
+ attribute \src "libresoc.v:128454.3-128488.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:128420.3-128466.6"
+ attribute \src "libresoc.v:128245.3-128291.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:128467.3-128513.6"
+ attribute \src "libresoc.v:128292.3-128338.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:128332.7-128332.20"
+ attribute \src "libresoc.v:128157.7-128157.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128571.3-128597.6"
+ attribute \src "libresoc.v:128396.3-128422.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:128514.3-128528.6"
+ attribute \src "libresoc.v:128339.3-128353.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:128529.3-128547.6"
+ attribute \src "libresoc.v:128354.3-128372.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:128548.3-128570.6"
+ attribute \src "libresoc.v:128373.3-128395.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:128598.3-128628.6"
+ attribute \src "libresoc.v:128423.3-128453.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:128629.3-128663.6"
+ attribute \src "libresoc.v:128454.3-128488.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:128420.3-128466.6"
+ attribute \src "libresoc.v:128245.3-128291.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:128467.3-128513.6"
+ attribute \src "libresoc.v:128292.3-128338.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128571.3-128597.6"
+ attribute \src "libresoc.v:128396.3-128422.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:128514.3-128528.6"
+ attribute \src "libresoc.v:128339.3-128353.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:128529.3-128547.6"
+ attribute \src "libresoc.v:128354.3-128372.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:128548.3-128570.6"
+ attribute \src "libresoc.v:128373.3-128395.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:128410.17-128410.110"
- wire width 64 $extend$libresoc.v:128410$4957_Y
- attribute \src "libresoc.v:128411.18-128411.113"
- wire width 64 $extend$libresoc.v:128411$4959_Y
- attribute \src "libresoc.v:128414.17-128414.110"
- wire width 64 $extend$libresoc.v:128414$4963_Y
- attribute \src "libresoc.v:128418.17-128418.102"
- wire width 64 $extend$libresoc.v:128418$4968_Y
- attribute \src "libresoc.v:128410.17-128410.110"
- wire width 64 $pos$libresoc.v:128410$4958_Y
- attribute \src "libresoc.v:128411.18-128411.113"
- wire width 64 $pos$libresoc.v:128411$4960_Y
- attribute \src "libresoc.v:128414.17-128414.110"
- wire width 64 $pos$libresoc.v:128414$4964_Y
- attribute \src "libresoc.v:128418.17-128418.102"
- wire width 64 $pos$libresoc.v:128418$4969_Y
- attribute \src "libresoc.v:128412.18-128412.120"
- wire width 47 $sshl$libresoc.v:128412$4961_Y
- attribute \src "libresoc.v:128413.18-128413.119"
- wire width 27 $sshl$libresoc.v:128413$4962_Y
- attribute \src "libresoc.v:128415.18-128415.119"
- wire width 17 $sshl$libresoc.v:128415$4965_Y
- attribute \src "libresoc.v:128416.18-128416.119"
- wire width 17 $sshl$libresoc.v:128416$4966_Y
- attribute \src "libresoc.v:128417.17-128417.109"
- wire width 47 $sshl$libresoc.v:128417$4967_Y
+ attribute \src "libresoc.v:128235.17-128235.110"
+ wire width 64 $extend$libresoc.v:128235$4941_Y
+ attribute \src "libresoc.v:128236.18-128236.113"
+ wire width 64 $extend$libresoc.v:128236$4943_Y
+ attribute \src "libresoc.v:128239.17-128239.110"
+ wire width 64 $extend$libresoc.v:128239$4947_Y
+ attribute \src "libresoc.v:128243.17-128243.102"
+ wire width 64 $extend$libresoc.v:128243$4952_Y
+ attribute \src "libresoc.v:128235.17-128235.110"
+ wire width 64 $pos$libresoc.v:128235$4942_Y
+ attribute \src "libresoc.v:128236.18-128236.113"
+ wire width 64 $pos$libresoc.v:128236$4944_Y
+ attribute \src "libresoc.v:128239.17-128239.110"
+ wire width 64 $pos$libresoc.v:128239$4948_Y
+ attribute \src "libresoc.v:128243.17-128243.102"
+ wire width 64 $pos$libresoc.v:128243$4953_Y
+ attribute \src "libresoc.v:128237.18-128237.120"
+ wire width 47 $sshl$libresoc.v:128237$4945_Y
+ attribute \src "libresoc.v:128238.18-128238.119"
+ wire width 27 $sshl$libresoc.v:128238$4946_Y
+ attribute \src "libresoc.v:128240.18-128240.119"
+ wire width 17 $sshl$libresoc.v:128240$4949_Y
+ attribute \src "libresoc.v:128241.18-128241.119"
+ wire width 17 $sshl$libresoc.v:128241$4950_Y
+ attribute \src "libresoc.v:128242.17-128242.109"
+ wire width 47 $sshl$libresoc.v:128242$4951_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:128332.7-128332.15"
+ attribute \src "libresoc.v:128157.7-128157.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128410$4957
+ cell $pos $extend$libresoc.v:128235$4941
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_sh
- connect \Y $extend$libresoc.v:128410$4957_Y
+ connect \Y $extend$libresoc.v:128235$4941_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128411$4959
+ cell $pos $extend$libresoc.v:128236$4943
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_SH32
- connect \Y $extend$libresoc.v:128411$4959_Y
+ connect \Y $extend$libresoc.v:128236$4943_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128414$4963
+ cell $pos $extend$libresoc.v:128239$4947
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_UI
- connect \Y $extend$libresoc.v:128414$4963_Y
+ connect \Y $extend$libresoc.v:128239$4947_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:128418$4968
+ cell $pos $extend$libresoc.v:128243$4952
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:128418$4968_Y
+ connect \Y $extend$libresoc.v:128243$4952_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128410$4958
+ cell $pos $pos$libresoc.v:128235$4942
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128410$4957_Y
- connect \Y $pos$libresoc.v:128410$4958_Y
+ connect \A $extend$libresoc.v:128235$4941_Y
+ connect \Y $pos$libresoc.v:128235$4942_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128411$4960
+ cell $pos $pos$libresoc.v:128236$4944
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128411$4959_Y
- connect \Y $pos$libresoc.v:128411$4960_Y
+ connect \A $extend$libresoc.v:128236$4943_Y
+ connect \Y $pos$libresoc.v:128236$4944_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128414$4964
+ cell $pos $pos$libresoc.v:128239$4948
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128414$4963_Y
- connect \Y $pos$libresoc.v:128414$4964_Y
+ connect \A $extend$libresoc.v:128239$4947_Y
+ connect \Y $pos$libresoc.v:128239$4948_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:128418$4969
+ cell $pos $pos$libresoc.v:128243$4953
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128418$4968_Y
- connect \Y $pos$libresoc.v:128418$4969_Y
+ connect \A $extend$libresoc.v:128243$4952_Y
+ connect \Y $pos$libresoc.v:128243$4953_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:128412$4961
+ cell $sshl $sshl$libresoc.v:128237$4945
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \SHIFT_ROT_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128412$4961_Y
+ connect \Y $sshl$libresoc.v:128237$4945_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:128413$4962
+ cell $sshl $sshl$libresoc.v:128238$4946
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \SHIFT_ROT_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:128413$4962_Y
+ connect \Y $sshl$libresoc.v:128238$4946_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:128415$4965
+ cell $sshl $sshl$libresoc.v:128240$4949
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \SHIFT_ROT_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:128415$4965_Y
+ connect \Y $sshl$libresoc.v:128240$4949_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:128416$4966
+ cell $sshl $sshl$libresoc.v:128241$4950
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \SHIFT_ROT_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:128416$4966_Y
+ connect \Y $sshl$libresoc.v:128241$4950_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:128417$4967
+ cell $sshl $sshl$libresoc.v:128242$4951
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128417$4967_Y
+ connect \Y $sshl$libresoc.v:128242$4951_Y
end
- attribute \src "libresoc.v:128332.7-128332.20"
- process $proc$libresoc.v:128332$4978
+ attribute \src "libresoc.v:128157.7-128157.20"
+ process $proc$libresoc.v:128157$4962
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128420.3-128466.6"
- process $proc$libresoc.v:128420$4970
+ attribute \src "libresoc.v:128245.3-128291.6"
+ process $proc$libresoc.v:128245$4954
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:128421.5-128421.29"
+ attribute \src "libresoc.v:128246.5-128246.29"
switch \initial
- attribute \src "libresoc.v:128421.9-128421.17"
+ attribute \src "libresoc.v:128246.9-128246.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:128467.3-128513.6"
- process $proc$libresoc.v:128467$4971
+ attribute \src "libresoc.v:128292.3-128338.6"
+ process $proc$libresoc.v:128292$4955
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128468.5-128468.29"
+ attribute \src "libresoc.v:128293.5-128293.29"
switch \initial
- attribute \src "libresoc.v:128468.9-128468.17"
+ attribute \src "libresoc.v:128293.9-128293.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:128514.3-128528.6"
- process $proc$libresoc.v:128514$4972
+ attribute \src "libresoc.v:128339.3-128353.6"
+ process $proc$libresoc.v:128339$4956
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:128515.5-128515.29"
+ attribute \src "libresoc.v:128340.5-128340.29"
switch \initial
- attribute \src "libresoc.v:128515.9-128515.17"
+ attribute \src "libresoc.v:128340.9-128340.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:128529.3-128547.6"
- process $proc$libresoc.v:128529$4973
+ attribute \src "libresoc.v:128354.3-128372.6"
+ process $proc$libresoc.v:128354$4957
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:128530.5-128530.29"
+ attribute \src "libresoc.v:128355.5-128355.29"
switch \initial
- attribute \src "libresoc.v:128530.9-128530.17"
+ attribute \src "libresoc.v:128355.9-128355.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:128548.3-128570.6"
- process $proc$libresoc.v:128548$4974
+ attribute \src "libresoc.v:128373.3-128395.6"
+ process $proc$libresoc.v:128373$4958
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:128549.5-128549.29"
+ attribute \src "libresoc.v:128374.5-128374.29"
switch \initial
- attribute \src "libresoc.v:128549.9-128549.17"
+ attribute \src "libresoc.v:128374.9-128374.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:128571.3-128597.6"
- process $proc$libresoc.v:128571$4975
+ attribute \src "libresoc.v:128396.3-128422.6"
+ process $proc$libresoc.v:128396$4959
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:128572.5-128572.29"
+ attribute \src "libresoc.v:128397.5-128397.29"
switch \initial
- attribute \src "libresoc.v:128572.9-128572.17"
+ attribute \src "libresoc.v:128397.9-128397.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:128598.3-128628.6"
- process $proc$libresoc.v:128598$4976
+ attribute \src "libresoc.v:128423.3-128453.6"
+ process $proc$libresoc.v:128423$4960
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:128599.5-128599.29"
+ attribute \src "libresoc.v:128424.5-128424.29"
switch \initial
- attribute \src "libresoc.v:128599.9-128599.17"
+ attribute \src "libresoc.v:128424.9-128424.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:128629.3-128663.6"
- process $proc$libresoc.v:128629$4977
+ attribute \src "libresoc.v:128454.3-128488.6"
+ process $proc$libresoc.v:128454$4961
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:128630.5-128630.29"
+ attribute \src "libresoc.v:128455.5-128455.29"
switch \initial
- attribute \src "libresoc.v:128630.9-128630.17"
+ attribute \src "libresoc.v:128455.9-128455.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:128410$4958_Y
- connect \$11 $pos$libresoc.v:128411$4960_Y
- connect \$14 $sshl$libresoc.v:128412$4961_Y
- connect \$17 $sshl$libresoc.v:128413$4962_Y
- connect \$1 $pos$libresoc.v:128414$4964_Y
- connect \$20 $sshl$libresoc.v:128415$4965_Y
- connect \$23 $sshl$libresoc.v:128416$4966_Y
- connect \$4 $sshl$libresoc.v:128417$4967_Y
- connect \$3 $pos$libresoc.v:128418$4969_Y
+ connect \$9 $pos$libresoc.v:128235$4942_Y
+ connect \$11 $pos$libresoc.v:128236$4944_Y
+ connect \$14 $sshl$libresoc.v:128237$4945_Y
+ connect \$17 $sshl$libresoc.v:128238$4946_Y
+ connect \$1 $pos$libresoc.v:128239$4948_Y
+ connect \$20 $sshl$libresoc.v:128240$4949_Y
+ connect \$23 $sshl$libresoc.v:128241$4950_Y
+ connect \$4 $sshl$libresoc.v:128242$4951_Y
+ connect \$3 $pos$libresoc.v:128243$4953_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:128672.1-129009.10"
+attribute \src "libresoc.v:128497.1-128834.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi"
attribute \generator "nMigen"
module \dec_bi$170
- attribute \src "libresoc.v:128939.3-128969.6"
+ attribute \src "libresoc.v:128764.3-128794.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:128970.3-129004.6"
+ attribute \src "libresoc.v:128795.3-128829.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:128761.3-128807.6"
+ attribute \src "libresoc.v:128586.3-128632.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:128808.3-128854.6"
+ attribute \src "libresoc.v:128633.3-128679.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:128673.7-128673.20"
+ attribute \src "libresoc.v:128498.7-128498.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128912.3-128938.6"
+ attribute \src "libresoc.v:128737.3-128763.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:128855.3-128869.6"
+ attribute \src "libresoc.v:128680.3-128694.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:128870.3-128888.6"
+ attribute \src "libresoc.v:128695.3-128713.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:128889.3-128911.6"
+ attribute \src "libresoc.v:128714.3-128736.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:128939.3-128969.6"
+ attribute \src "libresoc.v:128764.3-128794.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:128970.3-129004.6"
+ attribute \src "libresoc.v:128795.3-128829.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:128761.3-128807.6"
+ attribute \src "libresoc.v:128586.3-128632.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:128808.3-128854.6"
+ attribute \src "libresoc.v:128633.3-128679.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128912.3-128938.6"
+ attribute \src "libresoc.v:128737.3-128763.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:128855.3-128869.6"
+ attribute \src "libresoc.v:128680.3-128694.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:128870.3-128888.6"
+ attribute \src "libresoc.v:128695.3-128713.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:128889.3-128911.6"
+ attribute \src "libresoc.v:128714.3-128736.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:128751.17-128751.105"
- wire width 64 $extend$libresoc.v:128751$4979_Y
- attribute \src "libresoc.v:128752.18-128752.108"
- wire width 64 $extend$libresoc.v:128752$4981_Y
- attribute \src "libresoc.v:128755.17-128755.105"
- wire width 64 $extend$libresoc.v:128755$4985_Y
- attribute \src "libresoc.v:128759.17-128759.102"
- wire width 64 $extend$libresoc.v:128759$4990_Y
- attribute \src "libresoc.v:128751.17-128751.105"
- wire width 64 $pos$libresoc.v:128751$4980_Y
- attribute \src "libresoc.v:128752.18-128752.108"
- wire width 64 $pos$libresoc.v:128752$4982_Y
- attribute \src "libresoc.v:128755.17-128755.105"
- wire width 64 $pos$libresoc.v:128755$4986_Y
- attribute \src "libresoc.v:128759.17-128759.102"
- wire width 64 $pos$libresoc.v:128759$4991_Y
- attribute \src "libresoc.v:128753.18-128753.115"
- wire width 47 $sshl$libresoc.v:128753$4983_Y
- attribute \src "libresoc.v:128754.18-128754.114"
- wire width 27 $sshl$libresoc.v:128754$4984_Y
- attribute \src "libresoc.v:128756.18-128756.114"
- wire width 17 $sshl$libresoc.v:128756$4987_Y
- attribute \src "libresoc.v:128757.18-128757.114"
- wire width 17 $sshl$libresoc.v:128757$4988_Y
- attribute \src "libresoc.v:128758.17-128758.109"
- wire width 47 $sshl$libresoc.v:128758$4989_Y
+ attribute \src "libresoc.v:128576.17-128576.105"
+ wire width 64 $extend$libresoc.v:128576$4963_Y
+ attribute \src "libresoc.v:128577.18-128577.108"
+ wire width 64 $extend$libresoc.v:128577$4965_Y
+ attribute \src "libresoc.v:128580.17-128580.105"
+ wire width 64 $extend$libresoc.v:128580$4969_Y
+ attribute \src "libresoc.v:128584.17-128584.102"
+ wire width 64 $extend$libresoc.v:128584$4974_Y
+ attribute \src "libresoc.v:128576.17-128576.105"
+ wire width 64 $pos$libresoc.v:128576$4964_Y
+ attribute \src "libresoc.v:128577.18-128577.108"
+ wire width 64 $pos$libresoc.v:128577$4966_Y
+ attribute \src "libresoc.v:128580.17-128580.105"
+ wire width 64 $pos$libresoc.v:128580$4970_Y
+ attribute \src "libresoc.v:128584.17-128584.102"
+ wire width 64 $pos$libresoc.v:128584$4975_Y
+ attribute \src "libresoc.v:128578.18-128578.115"
+ wire width 47 $sshl$libresoc.v:128578$4967_Y
+ attribute \src "libresoc.v:128579.18-128579.114"
+ wire width 27 $sshl$libresoc.v:128579$4968_Y
+ attribute \src "libresoc.v:128581.18-128581.114"
+ wire width 17 $sshl$libresoc.v:128581$4971_Y
+ attribute \src "libresoc.v:128582.18-128582.114"
+ wire width 17 $sshl$libresoc.v:128582$4972_Y
+ attribute \src "libresoc.v:128583.17-128583.109"
+ wire width 47 $sshl$libresoc.v:128583$4973_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:128673.7-128673.15"
+ attribute \src "libresoc.v:128498.7-128498.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128751$4979
+ cell $pos $extend$libresoc.v:128576$4963
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \LDST_sh
- connect \Y $extend$libresoc.v:128751$4979_Y
+ connect \Y $extend$libresoc.v:128576$4963_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128752$4981
+ cell $pos $extend$libresoc.v:128577$4965
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \LDST_SH32
- connect \Y $extend$libresoc.v:128752$4981_Y
+ connect \Y $extend$libresoc.v:128577$4965_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $extend$libresoc.v:128755$4985
+ cell $pos $extend$libresoc.v:128580$4969
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \LDST_UI
- connect \Y $extend$libresoc.v:128755$4985_Y
+ connect \Y $extend$libresoc.v:128580$4969_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $extend$libresoc.v:128759$4990
+ cell $pos $extend$libresoc.v:128584$4974
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:128759$4990_Y
+ connect \Y $extend$libresoc.v:128584$4974_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128751$4980
+ cell $pos $pos$libresoc.v:128576$4964
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128751$4979_Y
- connect \Y $pos$libresoc.v:128751$4980_Y
+ connect \A $extend$libresoc.v:128576$4963_Y
+ connect \Y $pos$libresoc.v:128576$4964_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128752$4982
+ cell $pos $pos$libresoc.v:128577$4966
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128752$4981_Y
- connect \Y $pos$libresoc.v:128752$4982_Y
+ connect \A $extend$libresoc.v:128577$4965_Y
+ connect \Y $pos$libresoc.v:128577$4966_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
- cell $pos $pos$libresoc.v:128755$4986
+ cell $pos $pos$libresoc.v:128580$4970
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128755$4985_Y
- connect \Y $pos$libresoc.v:128755$4986_Y
+ connect \A $extend$libresoc.v:128580$4969_Y
+ connect \Y $pos$libresoc.v:128580$4970_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $pos $pos$libresoc.v:128759$4991
+ cell $pos $pos$libresoc.v:128584$4975
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:128759$4990_Y
- connect \Y $pos$libresoc.v:128759$4991_Y
+ connect \A $extend$libresoc.v:128584$4974_Y
+ connect \Y $pos$libresoc.v:128584$4975_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
- cell $sshl $sshl$libresoc.v:128753$4983
+ cell $sshl $sshl$libresoc.v:128578$4967
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \LDST_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128753$4983_Y
+ connect \Y $sshl$libresoc.v:128578$4967_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:128754$4984
+ cell $sshl $sshl$libresoc.v:128579$4968
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \LDST_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:128754$4984_Y
+ connect \Y $sshl$libresoc.v:128579$4968_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:128756$4987
+ cell $sshl $sshl$libresoc.v:128581$4971
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LDST_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:128756$4987_Y
+ connect \Y $sshl$libresoc.v:128581$4971_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
- cell $sshl $sshl$libresoc.v:128757$4988
+ cell $sshl $sshl$libresoc.v:128582$4972
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LDST_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:128757$4988_Y
+ connect \Y $sshl$libresoc.v:128582$4972_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
- cell $sshl $sshl$libresoc.v:128758$4989
+ cell $sshl $sshl$libresoc.v:128583$4973
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:128758$4989_Y
+ connect \Y $sshl$libresoc.v:128583$4973_Y
end
- attribute \src "libresoc.v:128673.7-128673.20"
- process $proc$libresoc.v:128673$5000
+ attribute \src "libresoc.v:128498.7-128498.20"
+ process $proc$libresoc.v:128498$4984
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128761.3-128807.6"
- process $proc$libresoc.v:128761$4992
+ attribute \src "libresoc.v:128586.3-128632.6"
+ process $proc$libresoc.v:128586$4976
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:128762.5-128762.29"
+ attribute \src "libresoc.v:128587.5-128587.29"
switch \initial
- attribute \src "libresoc.v:128762.9-128762.17"
+ attribute \src "libresoc.v:128587.9-128587.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:128808.3-128854.6"
- process $proc$libresoc.v:128808$4993
+ attribute \src "libresoc.v:128633.3-128679.6"
+ process $proc$libresoc.v:128633$4977
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:128809.5-128809.29"
+ attribute \src "libresoc.v:128634.5-128634.29"
switch \initial
- attribute \src "libresoc.v:128809.9-128809.17"
+ attribute \src "libresoc.v:128634.9-128634.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:128855.3-128869.6"
- process $proc$libresoc.v:128855$4994
+ attribute \src "libresoc.v:128680.3-128694.6"
+ process $proc$libresoc.v:128680$4978
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:128856.5-128856.29"
+ attribute \src "libresoc.v:128681.5-128681.29"
switch \initial
- attribute \src "libresoc.v:128856.9-128856.17"
+ attribute \src "libresoc.v:128681.9-128681.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:128870.3-128888.6"
- process $proc$libresoc.v:128870$4995
+ attribute \src "libresoc.v:128695.3-128713.6"
+ process $proc$libresoc.v:128695$4979
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:128871.5-128871.29"
+ attribute \src "libresoc.v:128696.5-128696.29"
switch \initial
- attribute \src "libresoc.v:128871.9-128871.17"
+ attribute \src "libresoc.v:128696.9-128696.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:128889.3-128911.6"
- process $proc$libresoc.v:128889$4996
+ attribute \src "libresoc.v:128714.3-128736.6"
+ process $proc$libresoc.v:128714$4980
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:128890.5-128890.29"
+ attribute \src "libresoc.v:128715.5-128715.29"
switch \initial
- attribute \src "libresoc.v:128890.9-128890.17"
+ attribute \src "libresoc.v:128715.9-128715.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:128912.3-128938.6"
- process $proc$libresoc.v:128912$4997
+ attribute \src "libresoc.v:128737.3-128763.6"
+ process $proc$libresoc.v:128737$4981
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:128913.5-128913.29"
+ attribute \src "libresoc.v:128738.5-128738.29"
switch \initial
- attribute \src "libresoc.v:128913.9-128913.17"
+ attribute \src "libresoc.v:128738.9-128738.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:128939.3-128969.6"
- process $proc$libresoc.v:128939$4998
+ attribute \src "libresoc.v:128764.3-128794.6"
+ process $proc$libresoc.v:128764$4982
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:128940.5-128940.29"
+ attribute \src "libresoc.v:128765.5-128765.29"
switch \initial
- attribute \src "libresoc.v:128940.9-128940.17"
+ attribute \src "libresoc.v:128765.9-128765.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:128970.3-129004.6"
- process $proc$libresoc.v:128970$4999
+ attribute \src "libresoc.v:128795.3-128829.6"
+ process $proc$libresoc.v:128795$4983
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:128971.5-128971.29"
+ attribute \src "libresoc.v:128796.5-128796.29"
switch \initial
- attribute \src "libresoc.v:128971.9-128971.17"
+ attribute \src "libresoc.v:128796.9-128796.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:128751$4980_Y
- connect \$11 $pos$libresoc.v:128752$4982_Y
- connect \$14 $sshl$libresoc.v:128753$4983_Y
- connect \$17 $sshl$libresoc.v:128754$4984_Y
- connect \$1 $pos$libresoc.v:128755$4986_Y
- connect \$20 $sshl$libresoc.v:128756$4987_Y
- connect \$23 $sshl$libresoc.v:128757$4988_Y
- connect \$4 $sshl$libresoc.v:128758$4989_Y
- connect \$3 $pos$libresoc.v:128759$4991_Y
+ connect \$9 $pos$libresoc.v:128576$4964_Y
+ connect \$11 $pos$libresoc.v:128577$4966_Y
+ connect \$14 $sshl$libresoc.v:128578$4967_Y
+ connect \$17 $sshl$libresoc.v:128579$4968_Y
+ connect \$1 $pos$libresoc.v:128580$4970_Y
+ connect \$20 $sshl$libresoc.v:128581$4971_Y
+ connect \$23 $sshl$libresoc.v:128582$4972_Y
+ connect \$4 $sshl$libresoc.v:128583$4973_Y
+ connect \$3 $pos$libresoc.v:128584$4975_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:129013.1-129061.10"
+attribute \src "libresoc.v:128838.1-128886.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c"
attribute \generator "nMigen"
module \dec_c
- attribute \src "libresoc.v:129014.7-129014.20"
+ attribute \src "libresoc.v:128839.7-128839.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129031.3-129045.6"
+ attribute \src "libresoc.v:128856.3-128870.6"
wire width 5 $0\reg_c[4:0]
- attribute \src "libresoc.v:129046.3-129060.6"
+ attribute \src "libresoc.v:128871.3-128885.6"
wire $0\reg_c_ok[0:0]
- attribute \src "libresoc.v:129031.3-129045.6"
+ attribute \src "libresoc.v:128856.3-128870.6"
wire width 5 $1\reg_c[4:0]
- attribute \src "libresoc.v:129046.3-129060.6"
+ attribute \src "libresoc.v:128871.3-128885.6"
wire $1\reg_c_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 4 \RB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 3 \RS
- attribute \src "libresoc.v:129014.7-129014.15"
+ attribute \src "libresoc.v:128839.7-128839.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 5 output 1 \reg_c
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:129014.7-129014.20"
- process $proc$libresoc.v:129014$5003
+ attribute \src "libresoc.v:128839.7-128839.20"
+ process $proc$libresoc.v:128839$4987
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129031.3-129045.6"
- process $proc$libresoc.v:129031$5001
+ attribute \src "libresoc.v:128856.3-128870.6"
+ process $proc$libresoc.v:128856$4985
assign { } { }
assign { } { }
assign $0\reg_c[4:0] $1\reg_c[4:0]
- attribute \src "libresoc.v:129032.5-129032.29"
+ attribute \src "libresoc.v:128857.5-128857.29"
switch \initial
- attribute \src "libresoc.v:129032.9-129032.17"
+ attribute \src "libresoc.v:128857.9-128857.17"
case 1'1
case
end
sync always
update \reg_c $0\reg_c[4:0]
end
- attribute \src "libresoc.v:129046.3-129060.6"
- process $proc$libresoc.v:129046$5002
+ attribute \src "libresoc.v:128871.3-128885.6"
+ process $proc$libresoc.v:128871$4986
assign { } { }
assign { } { }
assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0]
- attribute \src "libresoc.v:129047.5-129047.29"
+ attribute \src "libresoc.v:128872.5-128872.29"
switch \initial
- attribute \src "libresoc.v:129047.9-129047.17"
+ attribute \src "libresoc.v:128872.9-128872.17"
case 1'1
case
end
update \reg_c_ok $0\reg_c_ok[0:0]
end
end
-attribute \src "libresoc.v:129065.1-129601.10"
+attribute \src "libresoc.v:128890.1-129426.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in"
attribute \generator "nMigen"
module \dec_cr_in
- attribute \src "libresoc.v:129421.3-129455.6"
+ attribute \src "libresoc.v:129246.3-129280.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:129456.3-129486.6"
+ attribute \src "libresoc.v:129281.3-129311.6"
wire width 3 $0\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:129254.3-129284.6"
+ attribute \src "libresoc.v:129079.3-129109.6"
wire $0\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:129487.3-129517.6"
+ attribute \src "libresoc.v:129312.3-129342.6"
wire width 3 $0\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:129332.3-129362.6"
+ attribute \src "libresoc.v:129157.3-129187.6"
wire $0\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:129219.3-129253.6"
+ attribute \src "libresoc.v:129044.3-129078.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129285.3-129331.6"
+ attribute \src "libresoc.v:129110.3-129156.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:129363.3-129401.6"
+ attribute \src "libresoc.v:129188.3-129226.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129066.7-129066.20"
+ attribute \src "libresoc.v:128891.7-128891.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129518.3-129556.6"
+ attribute \src "libresoc.v:129343.3-129381.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:129557.3-129600.6"
+ attribute \src "libresoc.v:129382.3-129425.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:129402.3-129420.6"
+ attribute \src "libresoc.v:129227.3-129245.6"
wire width 2 $0\sv_override[1:0]
- attribute \src "libresoc.v:129421.3-129455.6"
+ attribute \src "libresoc.v:129246.3-129280.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:129456.3-129486.6"
+ attribute \src "libresoc.v:129281.3-129311.6"
wire width 3 $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:129254.3-129284.6"
+ attribute \src "libresoc.v:129079.3-129109.6"
wire $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:129487.3-129517.6"
+ attribute \src "libresoc.v:129312.3-129342.6"
wire width 3 $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:129332.3-129362.6"
+ attribute \src "libresoc.v:129157.3-129187.6"
wire $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:129219.3-129253.6"
+ attribute \src "libresoc.v:129044.3-129078.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129285.3-129331.6"
+ attribute \src "libresoc.v:129110.3-129156.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:129363.3-129401.6"
+ attribute \src "libresoc.v:129188.3-129226.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129518.3-129556.6"
+ attribute \src "libresoc.v:129343.3-129381.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:129557.3-129600.6"
+ attribute \src "libresoc.v:129382.3-129425.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:129402.3-129420.6"
+ attribute \src "libresoc.v:129227.3-129245.6"
wire width 2 $1\sv_override[1:0]
- attribute \src "libresoc.v:129285.3-129331.6"
+ attribute \src "libresoc.v:129110.3-129156.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:129557.3-129600.6"
+ attribute \src "libresoc.v:129382.3-129425.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:129212.17-129212.112"
- wire $and$libresoc.v:129212$5005_Y
- attribute \src "libresoc.v:129214.17-129214.112"
- wire $and$libresoc.v:129214$5007_Y
- attribute \src "libresoc.v:129211.17-129211.117"
- wire $eq$libresoc.v:129211$5004_Y
- attribute \src "libresoc.v:129213.17-129213.117"
- wire $eq$libresoc.v:129213$5006_Y
+ attribute \src "libresoc.v:129037.17-129037.112"
+ wire $and$libresoc.v:129037$4989_Y
+ attribute \src "libresoc.v:129039.17-129039.112"
+ wire $and$libresoc.v:129039$4991_Y
+ attribute \src "libresoc.v:129036.17-129036.117"
+ wire $eq$libresoc.v:129036$4988_Y
+ attribute \src "libresoc.v:129038.17-129038.117"
+ wire $eq$libresoc.v:129038$4990_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
wire width 8 output 3 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \cr_fxm_ok
- attribute \src "libresoc.v:129066.7-129066.15"
+ attribute \src "libresoc.v:128891.7-128891.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522"
wire width 32 input 1 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527"
wire width 2 \sv_override
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
- cell $and $and$libresoc.v:129212$5005
+ cell $and $and$libresoc.v:129037$4989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \move_one
- connect \Y $and$libresoc.v:129212$5005_Y
+ connect \Y $and$libresoc.v:129037$4989_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
- cell $and $and$libresoc.v:129214$5007
+ cell $and $and$libresoc.v:129039$4991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \move_one
- connect \Y $and$libresoc.v:129214$5007_Y
+ connect \Y $and$libresoc.v:129039$4991_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
- cell $eq $eq$libresoc.v:129211$5004
+ cell $eq $eq$libresoc.v:129036$4988
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:129211$5004_Y
+ connect \Y $eq$libresoc.v:129036$4988_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
- cell $eq $eq$libresoc.v:129213$5006
+ cell $eq $eq$libresoc.v:129038$4990
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:129213$5006_Y
+ connect \Y $eq$libresoc.v:129038$4990_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:129215.9-129218.4"
+ attribute \src "libresoc.v:129040.9-129043.4"
cell \ppick \ppick
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:129066.7-129066.20"
- process $proc$libresoc.v:129066$5019
+ attribute \src "libresoc.v:128891.7-128891.20"
+ process $proc$libresoc.v:128891$5003
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129219.3-129253.6"
- process $proc$libresoc.v:129219$5008
+ attribute \src "libresoc.v:129044.3-129078.6"
+ process $proc$libresoc.v:129044$4992
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129220.5-129220.29"
+ attribute \src "libresoc.v:129045.5-129045.29"
switch \initial
- attribute \src "libresoc.v:129220.9-129220.17"
+ attribute \src "libresoc.v:129045.9-129045.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:129254.3-129284.6"
- process $proc$libresoc.v:129254$5009
+ attribute \src "libresoc.v:129079.3-129109.6"
+ process $proc$libresoc.v:129079$4993
assign { } { }
assign { } { }
assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:129255.5-129255.29"
+ attribute \src "libresoc.v:129080.5-129080.29"
switch \initial
- attribute \src "libresoc.v:129255.9-129255.17"
+ attribute \src "libresoc.v:129080.9-129080.17"
case 1'1
case
end
sync always
update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0]
end
- attribute \src "libresoc.v:129285.3-129331.6"
- process $proc$libresoc.v:129285$5010
+ attribute \src "libresoc.v:129110.3-129156.6"
+ process $proc$libresoc.v:129110$4994
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:129286.5-129286.29"
+ attribute \src "libresoc.v:129111.5-129111.29"
switch \initial
- attribute \src "libresoc.v:129286.9-129286.17"
+ attribute \src "libresoc.v:129111.9-129111.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- attribute \src "libresoc.v:129332.3-129362.6"
- process $proc$libresoc.v:129332$5011
+ attribute \src "libresoc.v:129157.3-129187.6"
+ process $proc$libresoc.v:129157$4995
assign { } { }
assign { } { }
assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:129333.5-129333.29"
+ attribute \src "libresoc.v:129158.5-129158.29"
switch \initial
- attribute \src "libresoc.v:129333.9-129333.17"
+ attribute \src "libresoc.v:129158.9-129158.17"
case 1'1
case
end
sync always
update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0]
end
- attribute \src "libresoc.v:129363.3-129401.6"
- process $proc$libresoc.v:129363$5012
+ attribute \src "libresoc.v:129188.3-129226.6"
+ process $proc$libresoc.v:129188$4996
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129364.5-129364.29"
+ attribute \src "libresoc.v:129189.5-129189.29"
switch \initial
- attribute \src "libresoc.v:129364.9-129364.17"
+ attribute \src "libresoc.v:129189.9-129189.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:129402.3-129420.6"
- process $proc$libresoc.v:129402$5013
+ attribute \src "libresoc.v:129227.3-129245.6"
+ process $proc$libresoc.v:129227$4997
assign { } { }
assign { } { }
assign $0\sv_override[1:0] $1\sv_override[1:0]
- attribute \src "libresoc.v:129403.5-129403.29"
+ attribute \src "libresoc.v:129228.5-129228.29"
switch \initial
- attribute \src "libresoc.v:129403.9-129403.17"
+ attribute \src "libresoc.v:129228.9-129228.17"
case 1'1
case
end
sync always
update \sv_override $0\sv_override[1:0]
end
- attribute \src "libresoc.v:129421.3-129455.6"
- process $proc$libresoc.v:129421$5014
+ attribute \src "libresoc.v:129246.3-129280.6"
+ process $proc$libresoc.v:129246$4998
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:129422.5-129422.29"
+ attribute \src "libresoc.v:129247.5-129247.29"
switch \initial
- attribute \src "libresoc.v:129422.9-129422.17"
+ attribute \src "libresoc.v:129247.9-129247.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:129456.3-129486.6"
- process $proc$libresoc.v:129456$5015
+ attribute \src "libresoc.v:129281.3-129311.6"
+ process $proc$libresoc.v:129281$4999
assign { } { }
assign { } { }
assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:129457.5-129457.29"
+ attribute \src "libresoc.v:129282.5-129282.29"
switch \initial
- attribute \src "libresoc.v:129457.9-129457.17"
+ attribute \src "libresoc.v:129282.9-129282.17"
case 1'1
case
end
sync always
update \cr_bitfield_b $0\cr_bitfield_b[2:0]
end
- attribute \src "libresoc.v:129487.3-129517.6"
- process $proc$libresoc.v:129487$5016
+ attribute \src "libresoc.v:129312.3-129342.6"
+ process $proc$libresoc.v:129312$5000
assign { } { }
assign { } { }
assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:129488.5-129488.29"
+ attribute \src "libresoc.v:129313.5-129313.29"
switch \initial
- attribute \src "libresoc.v:129488.9-129488.17"
+ attribute \src "libresoc.v:129313.9-129313.17"
case 1'1
case
end
sync always
update \cr_bitfield_o $0\cr_bitfield_o[2:0]
end
- attribute \src "libresoc.v:129518.3-129556.6"
- process $proc$libresoc.v:129518$5017
+ attribute \src "libresoc.v:129343.3-129381.6"
+ process $proc$libresoc.v:129343$5001
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:129519.5-129519.29"
+ attribute \src "libresoc.v:129344.5-129344.29"
switch \initial
- attribute \src "libresoc.v:129519.9-129519.17"
+ attribute \src "libresoc.v:129344.9-129344.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:129557.3-129600.6"
- process $proc$libresoc.v:129557$5018
+ attribute \src "libresoc.v:129382.3-129425.6"
+ process $proc$libresoc.v:129382$5002
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:129558.5-129558.29"
+ attribute \src "libresoc.v:129383.5-129383.29"
switch \initial
- attribute \src "libresoc.v:129558.9-129558.17"
+ attribute \src "libresoc.v:129383.9-129383.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- connect \$1 $eq$libresoc.v:129211$5004_Y
- connect \$3 $and$libresoc.v:129212$5005_Y
- connect \$5 $eq$libresoc.v:129213$5006_Y
- connect \$7 $and$libresoc.v:129214$5007_Y
+ connect \$1 $eq$libresoc.v:129036$4988_Y
+ connect \$3 $and$libresoc.v:129037$4989_Y
+ connect \$5 $eq$libresoc.v:129038$4990_Y
+ connect \$7 $and$libresoc.v:129039$4991_Y
end
-attribute \src "libresoc.v:129605.1-129967.10"
+attribute \src "libresoc.v:129430.1-129792.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out"
attribute \generator "nMigen"
module \dec_cr_out
- attribute \src "libresoc.v:129813.3-129839.6"
+ attribute \src "libresoc.v:129638.3-129664.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:129736.3-129762.6"
+ attribute \src "libresoc.v:129561.3-129587.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129912.3-129966.6"
+ attribute \src "libresoc.v:129737.3-129791.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:129763.3-129793.6"
+ attribute \src "libresoc.v:129588.3-129618.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129606.7-129606.20"
+ attribute \src "libresoc.v:129431.7-129431.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129840.3-129870.6"
+ attribute \src "libresoc.v:129665.3-129695.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:129871.3-129911.6"
+ attribute \src "libresoc.v:129696.3-129736.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:129794.3-129812.6"
+ attribute \src "libresoc.v:129619.3-129637.6"
wire width 2 $0\sv_override[1:0]
- attribute \src "libresoc.v:129813.3-129839.6"
+ attribute \src "libresoc.v:129638.3-129664.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:129736.3-129762.6"
+ attribute \src "libresoc.v:129561.3-129587.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129912.3-129966.6"
+ attribute \src "libresoc.v:129737.3-129791.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:129763.3-129793.6"
+ attribute \src "libresoc.v:129588.3-129618.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129840.3-129870.6"
+ attribute \src "libresoc.v:129665.3-129695.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:129871.3-129911.6"
+ attribute \src "libresoc.v:129696.3-129736.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:129794.3-129812.6"
+ attribute \src "libresoc.v:129619.3-129637.6"
wire width 2 $1\sv_override[1:0]
- attribute \src "libresoc.v:129912.3-129966.6"
+ attribute \src "libresoc.v:129737.3-129791.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:129871.3-129911.6"
+ attribute \src "libresoc.v:129696.3-129736.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:129912.3-129966.6"
+ attribute \src "libresoc.v:129737.3-129791.6"
wire width 8 $3\cr_fxm[7:0]
- attribute \src "libresoc.v:129871.3-129911.6"
+ attribute \src "libresoc.v:129696.3-129736.6"
wire width 8 $3\ppick_i[7:0]
- attribute \src "libresoc.v:129912.3-129966.6"
+ attribute \src "libresoc.v:129737.3-129791.6"
wire width 8 $4\cr_fxm[7:0]
- attribute \src "libresoc.v:129729.17-129729.117"
- wire $eq$libresoc.v:129729$5020_Y
- attribute \src "libresoc.v:129730.17-129730.117"
- wire $eq$libresoc.v:129730$5021_Y
+ attribute \src "libresoc.v:129554.17-129554.117"
+ wire $eq$libresoc.v:129554$5004_Y
+ attribute \src "libresoc.v:129555.17-129555.117"
+ wire $eq$libresoc.v:129555$5005_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
wire width 8 output 4 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \cr_fxm_ok
- attribute \src "libresoc.v:129606.7-129606.15"
+ attribute \src "libresoc.v:129431.7-129431.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597"
wire width 32 input 1 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600"
wire width 2 \sv_override
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
- cell $eq $eq$libresoc.v:129729$5020
+ cell $eq $eq$libresoc.v:129554$5004
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:129729$5020_Y
+ connect \Y $eq$libresoc.v:129554$5004_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
- cell $eq $eq$libresoc.v:129730$5021
+ cell $eq $eq$libresoc.v:129555$5005
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:129730$5021_Y
+ connect \Y $eq$libresoc.v:129555$5005_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:129731.15-129735.4"
+ attribute \src "libresoc.v:129556.15-129560.4"
cell \ppick$175 \ppick
connect \en_o \ppick_en_o
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:129606.7-129606.20"
- process $proc$libresoc.v:129606$5029
+ attribute \src "libresoc.v:129431.7-129431.20"
+ process $proc$libresoc.v:129431$5013
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129736.3-129762.6"
- process $proc$libresoc.v:129736$5022
+ attribute \src "libresoc.v:129561.3-129587.6"
+ process $proc$libresoc.v:129561$5006
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:129737.5-129737.29"
+ attribute \src "libresoc.v:129562.5-129562.29"
switch \initial
- attribute \src "libresoc.v:129737.9-129737.17"
+ attribute \src "libresoc.v:129562.9-129562.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:129763.3-129793.6"
- process $proc$libresoc.v:129763$5023
+ attribute \src "libresoc.v:129588.3-129618.6"
+ process $proc$libresoc.v:129588$5007
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:129764.5-129764.29"
+ attribute \src "libresoc.v:129589.5-129589.29"
switch \initial
- attribute \src "libresoc.v:129764.9-129764.17"
+ attribute \src "libresoc.v:129589.9-129589.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:129794.3-129812.6"
- process $proc$libresoc.v:129794$5024
+ attribute \src "libresoc.v:129619.3-129637.6"
+ process $proc$libresoc.v:129619$5008
assign { } { }
assign { } { }
assign $0\sv_override[1:0] $1\sv_override[1:0]
- attribute \src "libresoc.v:129795.5-129795.29"
+ attribute \src "libresoc.v:129620.5-129620.29"
switch \initial
- attribute \src "libresoc.v:129795.9-129795.17"
+ attribute \src "libresoc.v:129620.9-129620.17"
case 1'1
case
end
sync always
update \sv_override $0\sv_override[1:0]
end
- attribute \src "libresoc.v:129813.3-129839.6"
- process $proc$libresoc.v:129813$5025
+ attribute \src "libresoc.v:129638.3-129664.6"
+ process $proc$libresoc.v:129638$5009
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:129814.5-129814.29"
+ attribute \src "libresoc.v:129639.5-129639.29"
switch \initial
- attribute \src "libresoc.v:129814.9-129814.17"
+ attribute \src "libresoc.v:129639.9-129639.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:129840.3-129870.6"
- process $proc$libresoc.v:129840$5026
+ attribute \src "libresoc.v:129665.3-129695.6"
+ process $proc$libresoc.v:129665$5010
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:129841.5-129841.29"
+ attribute \src "libresoc.v:129666.5-129666.29"
switch \initial
- attribute \src "libresoc.v:129841.9-129841.17"
+ attribute \src "libresoc.v:129666.9-129666.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:129871.3-129911.6"
- process $proc$libresoc.v:129871$5027
+ attribute \src "libresoc.v:129696.3-129736.6"
+ process $proc$libresoc.v:129696$5011
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:129872.5-129872.29"
+ attribute \src "libresoc.v:129697.5-129697.29"
switch \initial
- attribute \src "libresoc.v:129872.9-129872.17"
+ attribute \src "libresoc.v:129697.9-129697.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- attribute \src "libresoc.v:129912.3-129966.6"
- process $proc$libresoc.v:129912$5028
+ attribute \src "libresoc.v:129737.3-129791.6"
+ process $proc$libresoc.v:129737$5012
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:129913.5-129913.29"
+ attribute \src "libresoc.v:129738.5-129738.29"
switch \initial
- attribute \src "libresoc.v:129913.9-129913.17"
+ attribute \src "libresoc.v:129738.9-129738.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- connect \$1 $eq$libresoc.v:129729$5020_Y
- connect \$3 $eq$libresoc.v:129730$5021_Y
+ connect \$1 $eq$libresoc.v:129554$5004_Y
+ connect \$3 $eq$libresoc.v:129555$5005_Y
end
-attribute \src "libresoc.v:129971.1-130488.10"
+attribute \src "libresoc.v:129796.1-130313.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o"
attribute \generator "nMigen"
module \dec_o
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:129972.7-129972.20"
+ attribute \src "libresoc.v:129797.7-129797.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130343.3-130357.6"
+ attribute \src "libresoc.v:130168.3-130182.6"
wire width 5 $0\reg_o[4:0]
- attribute \src "libresoc.v:130358.3-130372.6"
+ attribute \src "libresoc.v:130183.3-130197.6"
wire $0\reg_o_ok[0:0]
- attribute \src "libresoc.v:130373.3-130391.6"
+ attribute \src "libresoc.v:130198.3-130216.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:130392.3-130415.6"
+ attribute \src "libresoc.v:130217.3-130240.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:130343.3-130357.6"
+ attribute \src "libresoc.v:130168.3-130182.6"
wire width 5 $1\reg_o[4:0]
- attribute \src "libresoc.v:130358.3-130372.6"
+ attribute \src "libresoc.v:130183.3-130197.6"
wire $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:130373.3-130391.6"
+ attribute \src "libresoc.v:130198.3-130216.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:130392.3-130415.6"
+ attribute \src "libresoc.v:130217.3-130240.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire width 3 $2\fast_o[2:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire $2\fast_o_ok[0:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire width 10 $2\spr_o[9:0]
- attribute \src "libresoc.v:130416.3-130440.6"
+ attribute \src "libresoc.v:130241.3-130265.6"
wire $2\spr_o_ok[0:0]
- attribute \src "libresoc.v:130392.3-130415.6"
+ attribute \src "libresoc.v:130217.3-130240.6"
wire width 10 $2\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire width 3 $3\fast_o[2:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire width 3 $4\fast_o[2:0]
- attribute \src "libresoc.v:130441.3-130487.6"
+ attribute \src "libresoc.v:130266.3-130312.6"
wire $4\fast_o_ok[0:0]
- attribute \src "libresoc.v:130332.17-130332.117"
- wire $eq$libresoc.v:130332$5030_Y
- attribute \src "libresoc.v:130333.17-130333.117"
- wire $eq$libresoc.v:130333$5031_Y
- attribute \src "libresoc.v:130334.17-130334.117"
- wire $eq$libresoc.v:130334$5032_Y
- attribute \src "libresoc.v:130335.17-130335.104"
- wire $not$libresoc.v:130335$5033_Y
+ attribute \src "libresoc.v:130157.17-130157.117"
+ wire $eq$libresoc.v:130157$5014_Y
+ attribute \src "libresoc.v:130158.17-130158.117"
+ wire $eq$libresoc.v:130158$5015_Y
+ attribute \src "libresoc.v:130159.17-130159.117"
+ wire $eq$libresoc.v:130159$5016_Y
+ attribute \src "libresoc.v:130160.17-130160.104"
+ wire $not$libresoc.v:130160$5017_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
wire width 3 output 7 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 8 \fast_o_ok
- attribute \src "libresoc.v:129972.7-129972.15"
+ attribute \src "libresoc.v:129797.7-129797.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \sprmap_spr_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
- cell $eq $eq$libresoc.v:130332$5030
+ cell $eq $eq$libresoc.v:130157$5014
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:130332$5030_Y
+ connect \Y $eq$libresoc.v:130157$5014_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
- cell $eq $eq$libresoc.v:130333$5031
+ cell $eq $eq$libresoc.v:130158$5015
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:130333$5031_Y
+ connect \Y $eq$libresoc.v:130158$5015_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
- cell $eq $eq$libresoc.v:130334$5032
+ cell $eq $eq$libresoc.v:130159$5016
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:130334$5032_Y
+ connect \Y $eq$libresoc.v:130159$5016_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
- cell $not $not$libresoc.v:130335$5033
+ cell $not $not$libresoc.v:130160$5017
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:130335$5033_Y
+ connect \Y $not$libresoc.v:130160$5017_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130336.16-130342.4"
+ attribute \src "libresoc.v:130161.16-130167.4"
cell \sprmap$174 \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:129972.7-129972.20"
- process $proc$libresoc.v:129972$5040
+ attribute \src "libresoc.v:129797.7-129797.20"
+ process $proc$libresoc.v:129797$5024
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:130343.3-130357.6"
- process $proc$libresoc.v:130343$5034
+ attribute \src "libresoc.v:130168.3-130182.6"
+ process $proc$libresoc.v:130168$5018
assign { } { }
assign { } { }
assign $0\reg_o[4:0] $1\reg_o[4:0]
- attribute \src "libresoc.v:130344.5-130344.29"
+ attribute \src "libresoc.v:130169.5-130169.29"
switch \initial
- attribute \src "libresoc.v:130344.9-130344.17"
+ attribute \src "libresoc.v:130169.9-130169.17"
case 1'1
case
end
sync always
update \reg_o $0\reg_o[4:0]
end
- attribute \src "libresoc.v:130358.3-130372.6"
- process $proc$libresoc.v:130358$5035
+ attribute \src "libresoc.v:130183.3-130197.6"
+ process $proc$libresoc.v:130183$5019
assign { } { }
assign { } { }
assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:130359.5-130359.29"
+ attribute \src "libresoc.v:130184.5-130184.29"
switch \initial
- attribute \src "libresoc.v:130359.9-130359.17"
+ attribute \src "libresoc.v:130184.9-130184.17"
case 1'1
case
end
sync always
update \reg_o_ok $0\reg_o_ok[0:0]
end
- attribute \src "libresoc.v:130373.3-130391.6"
- process $proc$libresoc.v:130373$5036
+ attribute \src "libresoc.v:130198.3-130216.6"
+ process $proc$libresoc.v:130198$5020
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:130374.5-130374.29"
+ attribute \src "libresoc.v:130199.5-130199.29"
switch \initial
- attribute \src "libresoc.v:130374.9-130374.17"
+ attribute \src "libresoc.v:130199.9-130199.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:130392.3-130415.6"
- process $proc$libresoc.v:130392$5037
+ attribute \src "libresoc.v:130217.3-130240.6"
+ process $proc$libresoc.v:130217$5021
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:130393.5-130393.29"
+ attribute \src "libresoc.v:130218.5-130218.29"
switch \initial
- attribute \src "libresoc.v:130393.9-130393.17"
+ attribute \src "libresoc.v:130218.9-130218.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:130416.3-130440.6"
- process $proc$libresoc.v:130416$5038
+ attribute \src "libresoc.v:130241.3-130265.6"
+ process $proc$libresoc.v:130241$5022
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:130417.5-130417.29"
+ attribute \src "libresoc.v:130242.5-130242.29"
switch \initial
- attribute \src "libresoc.v:130417.9-130417.17"
+ attribute \src "libresoc.v:130242.9-130242.17"
case 1'1
case
end
update \spr_o $0\spr_o[9:0]
update \spr_o_ok $0\spr_o_ok[0:0]
end
- attribute \src "libresoc.v:130441.3-130487.6"
- process $proc$libresoc.v:130441$5039
+ attribute \src "libresoc.v:130266.3-130312.6"
+ process $proc$libresoc.v:130266$5023
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $3\fast_o[2:0]
assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:130442.5-130442.29"
+ attribute \src "libresoc.v:130267.5-130267.29"
switch \initial
- attribute \src "libresoc.v:130442.9-130442.17"
+ attribute \src "libresoc.v:130267.9-130267.17"
case 1'1
case
end
update \fast_o $0\fast_o[2:0]
update \fast_o_ok $0\fast_o_ok[0:0]
end
- connect \$1 $eq$libresoc.v:130332$5030_Y
- connect \$3 $eq$libresoc.v:130333$5031_Y
- connect \$5 $eq$libresoc.v:130334$5032_Y
- connect \$7 $not$libresoc.v:130335$5033_Y
+ connect \$1 $eq$libresoc.v:130157$5014_Y
+ connect \$3 $eq$libresoc.v:130158$5015_Y
+ connect \$5 $eq$libresoc.v:130159$5016_Y
+ connect \$7 $not$libresoc.v:130160$5017_Y
end
-attribute \src "libresoc.v:130492.1-130660.10"
+attribute \src "libresoc.v:130317.1-130485.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2"
attribute \generator "nMigen"
module \dec_o2
- attribute \src "libresoc.v:130620.3-130639.6"
+ attribute \src "libresoc.v:130445.3-130464.6"
wire width 3 $0\fast_o2[2:0]
- attribute \src "libresoc.v:130640.3-130659.6"
+ attribute \src "libresoc.v:130465.3-130484.6"
wire $0\fast_o2_ok[0:0]
- attribute \src "libresoc.v:130493.7-130493.20"
+ attribute \src "libresoc.v:130318.7-130318.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130600.3-130609.6"
+ attribute \src "libresoc.v:130425.3-130434.6"
wire width 5 $0\reg_o2[4:0]
- attribute \src "libresoc.v:130610.3-130619.6"
+ attribute \src "libresoc.v:130435.3-130444.6"
wire $0\reg_o2_ok[0:0]
- attribute \src "libresoc.v:130620.3-130639.6"
+ attribute \src "libresoc.v:130445.3-130464.6"
wire width 3 $1\fast_o2[2:0]
- attribute \src "libresoc.v:130640.3-130659.6"
+ attribute \src "libresoc.v:130465.3-130484.6"
wire $1\fast_o2_ok[0:0]
- attribute \src "libresoc.v:130600.3-130609.6"
+ attribute \src "libresoc.v:130425.3-130434.6"
wire width 5 $1\reg_o2[4:0]
- attribute \src "libresoc.v:130610.3-130619.6"
+ attribute \src "libresoc.v:130435.3-130444.6"
wire $1\reg_o2_ok[0:0]
- attribute \src "libresoc.v:130620.3-130639.6"
+ attribute \src "libresoc.v:130445.3-130464.6"
wire width 3 $2\fast_o2[2:0]
- attribute \src "libresoc.v:130640.3-130659.6"
+ attribute \src "libresoc.v:130465.3-130484.6"
wire $2\fast_o2_ok[0:0]
- attribute \src "libresoc.v:130598.17-130598.108"
- wire $eq$libresoc.v:130598$5041_Y
- attribute \src "libresoc.v:130599.17-130599.108"
- wire $eq$libresoc.v:130599$5042_Y
+ attribute \src "libresoc.v:130423.17-130423.108"
+ wire $eq$libresoc.v:130423$5025_Y
+ attribute \src "libresoc.v:130424.17-130424.108"
+ wire $eq$libresoc.v:130424$5026_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
wire width 3 output 4 \fast_o2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \fast_o2_ok
- attribute \src "libresoc.v:130493.7-130493.15"
+ attribute \src "libresoc.v:130318.7-130318.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 input 6 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
- cell $eq $eq$libresoc.v:130598$5041
+ cell $eq $eq$libresoc.v:130423$5025
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd
connect \B 2'01
- connect \Y $eq$libresoc.v:130598$5041_Y
+ connect \Y $eq$libresoc.v:130423$5025_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
- cell $eq $eq$libresoc.v:130599$5042
+ cell $eq $eq$libresoc.v:130424$5026
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd
connect \B 2'01
- connect \Y $eq$libresoc.v:130599$5042_Y
+ connect \Y $eq$libresoc.v:130424$5026_Y
end
- attribute \src "libresoc.v:130493.7-130493.20"
- process $proc$libresoc.v:130493$5047
+ attribute \src "libresoc.v:130318.7-130318.20"
+ process $proc$libresoc.v:130318$5031
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:130600.3-130609.6"
- process $proc$libresoc.v:130600$5043
+ attribute \src "libresoc.v:130425.3-130434.6"
+ process $proc$libresoc.v:130425$5027
assign { } { }
assign { } { }
assign $0\reg_o2[4:0] $1\reg_o2[4:0]
- attribute \src "libresoc.v:130601.5-130601.29"
+ attribute \src "libresoc.v:130426.5-130426.29"
switch \initial
- attribute \src "libresoc.v:130601.9-130601.17"
+ attribute \src "libresoc.v:130426.9-130426.17"
case 1'1
case
end
sync always
update \reg_o2 $0\reg_o2[4:0]
end
- attribute \src "libresoc.v:130610.3-130619.6"
- process $proc$libresoc.v:130610$5044
+ attribute \src "libresoc.v:130435.3-130444.6"
+ process $proc$libresoc.v:130435$5028
assign { } { }
assign { } { }
assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0]
- attribute \src "libresoc.v:130611.5-130611.29"
+ attribute \src "libresoc.v:130436.5-130436.29"
switch \initial
- attribute \src "libresoc.v:130611.9-130611.17"
+ attribute \src "libresoc.v:130436.9-130436.17"
case 1'1
case
end
sync always
update \reg_o2_ok $0\reg_o2_ok[0:0]
end
- attribute \src "libresoc.v:130620.3-130639.6"
- process $proc$libresoc.v:130620$5045
+ attribute \src "libresoc.v:130445.3-130464.6"
+ process $proc$libresoc.v:130445$5029
assign { } { }
assign { } { }
assign $0\fast_o2[2:0] $1\fast_o2[2:0]
- attribute \src "libresoc.v:130621.5-130621.29"
+ attribute \src "libresoc.v:130446.5-130446.29"
switch \initial
- attribute \src "libresoc.v:130621.9-130621.17"
+ attribute \src "libresoc.v:130446.9-130446.17"
case 1'1
case
end
sync always
update \fast_o2 $0\fast_o2[2:0]
end
- attribute \src "libresoc.v:130640.3-130659.6"
- process $proc$libresoc.v:130640$5046
+ attribute \src "libresoc.v:130465.3-130484.6"
+ process $proc$libresoc.v:130465$5030
assign { } { }
assign { } { }
assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0]
- attribute \src "libresoc.v:130641.5-130641.29"
+ attribute \src "libresoc.v:130466.5-130466.29"
switch \initial
- attribute \src "libresoc.v:130641.9-130641.17"
+ attribute \src "libresoc.v:130466.9-130466.17"
case 1'1
case
end
sync always
update \fast_o2_ok $0\fast_o2_ok[0:0]
end
- connect \$1 $eq$libresoc.v:130598$5041_Y
- connect \$3 $eq$libresoc.v:130599$5042_Y
+ connect \$1 $eq$libresoc.v:130423$5025_Y
+ connect \$3 $eq$libresoc.v:130424$5026_Y
end
-attribute \src "libresoc.v:130664.1-130799.10"
+attribute \src "libresoc.v:130489.1-130624.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe"
attribute \generator "nMigen"
module \dec_oe
- attribute \src "libresoc.v:130665.7-130665.20"
+ attribute \src "libresoc.v:130490.7-130490.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130757.3-130777.6"
+ attribute \src "libresoc.v:130582.3-130602.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:130778.3-130798.6"
+ attribute \src "libresoc.v:130603.3-130623.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:130757.3-130777.6"
+ attribute \src "libresoc.v:130582.3-130602.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:130778.3-130798.6"
+ attribute \src "libresoc.v:130603.3-130623.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:130757.3-130777.6"
+ attribute \src "libresoc.v:130582.3-130602.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:130778.3-130798.6"
+ attribute \src "libresoc.v:130603.3-130623.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \ALU_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \ALU_internal_op
- attribute \src "libresoc.v:130665.7-130665.15"
+ attribute \src "libresoc.v:130490.7-130490.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:130665.7-130665.20"
- process $proc$libresoc.v:130665$5050
+ attribute \src "libresoc.v:130490.7-130490.20"
+ process $proc$libresoc.v:130490$5034
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:130757.3-130777.6"
- process $proc$libresoc.v:130757$5048
+ attribute \src "libresoc.v:130582.3-130602.6"
+ process $proc$libresoc.v:130582$5032
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:130758.5-130758.29"
+ attribute \src "libresoc.v:130583.5-130583.29"
switch \initial
- attribute \src "libresoc.v:130758.9-130758.17"
+ attribute \src "libresoc.v:130583.9-130583.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:130778.3-130798.6"
- process $proc$libresoc.v:130778$5049
+ attribute \src "libresoc.v:130603.3-130623.6"
+ process $proc$libresoc.v:130603$5033
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:130779.5-130779.29"
+ attribute \src "libresoc.v:130604.5-130604.29"
switch \initial
- attribute \src "libresoc.v:130779.9-130779.17"
+ attribute \src "libresoc.v:130604.9-130604.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:130803.1-130936.10"
+attribute \src "libresoc.v:130628.1-130761.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe"
attribute \generator "nMigen"
module \dec_oe$140
- attribute \src "libresoc.v:130804.7-130804.20"
+ attribute \src "libresoc.v:130629.7-130629.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130894.3-130914.6"
+ attribute \src "libresoc.v:130719.3-130739.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:130915.3-130935.6"
+ attribute \src "libresoc.v:130740.3-130760.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:130894.3-130914.6"
+ attribute \src "libresoc.v:130719.3-130739.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:130915.3-130935.6"
+ attribute \src "libresoc.v:130740.3-130760.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:130894.3-130914.6"
+ attribute \src "libresoc.v:130719.3-130739.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:130915.3-130935.6"
+ attribute \src "libresoc.v:130740.3-130760.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 2 \CR_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \CR_internal_op
- attribute \src "libresoc.v:130804.7-130804.15"
+ attribute \src "libresoc.v:130629.7-130629.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:130804.7-130804.20"
- process $proc$libresoc.v:130804$5053
+ attribute \src "libresoc.v:130629.7-130629.20"
+ process $proc$libresoc.v:130629$5037
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:130894.3-130914.6"
- process $proc$libresoc.v:130894$5051
+ attribute \src "libresoc.v:130719.3-130739.6"
+ process $proc$libresoc.v:130719$5035
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:130895.5-130895.29"
+ attribute \src "libresoc.v:130720.5-130720.29"
switch \initial
- attribute \src "libresoc.v:130895.9-130895.17"
+ attribute \src "libresoc.v:130720.9-130720.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:130915.3-130935.6"
- process $proc$libresoc.v:130915$5052
+ attribute \src "libresoc.v:130740.3-130760.6"
+ process $proc$libresoc.v:130740$5036
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:130916.5-130916.29"
+ attribute \src "libresoc.v:130741.5-130741.29"
switch \initial
- attribute \src "libresoc.v:130916.9-130916.17"
+ attribute \src "libresoc.v:130741.9-130741.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:130940.1-131073.10"
+attribute \src "libresoc.v:130765.1-130898.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe"
attribute \generator "nMigen"
module \dec_oe$143
- attribute \src "libresoc.v:130941.7-130941.20"
+ attribute \src "libresoc.v:130766.7-130766.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131031.3-131051.6"
+ attribute \src "libresoc.v:130856.3-130876.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131052.3-131072.6"
+ attribute \src "libresoc.v:130877.3-130897.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131031.3-131051.6"
+ attribute \src "libresoc.v:130856.3-130876.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131052.3-131072.6"
+ attribute \src "libresoc.v:130877.3-130897.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131031.3-131051.6"
+ attribute \src "libresoc.v:130856.3-130876.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131052.3-131072.6"
+ attribute \src "libresoc.v:130877.3-130897.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 2 \BRANCH_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \BRANCH_internal_op
- attribute \src "libresoc.v:130941.7-130941.15"
+ attribute \src "libresoc.v:130766.7-130766.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:130941.7-130941.20"
- process $proc$libresoc.v:130941$5056
+ attribute \src "libresoc.v:130766.7-130766.20"
+ process $proc$libresoc.v:130766$5040
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131031.3-131051.6"
- process $proc$libresoc.v:131031$5054
+ attribute \src "libresoc.v:130856.3-130876.6"
+ process $proc$libresoc.v:130856$5038
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131032.5-131032.29"
+ attribute \src "libresoc.v:130857.5-130857.29"
switch \initial
- attribute \src "libresoc.v:131032.9-131032.17"
+ attribute \src "libresoc.v:130857.9-130857.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131052.3-131072.6"
- process $proc$libresoc.v:131052$5055
+ attribute \src "libresoc.v:130877.3-130897.6"
+ process $proc$libresoc.v:130877$5039
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131053.5-131053.29"
+ attribute \src "libresoc.v:130878.5-130878.29"
switch \initial
- attribute \src "libresoc.v:131053.9-131053.17"
+ attribute \src "libresoc.v:130878.9-130878.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131077.1-131212.10"
+attribute \src "libresoc.v:130902.1-131037.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe"
attribute \generator "nMigen"
module \dec_oe$147
- attribute \src "libresoc.v:131078.7-131078.20"
+ attribute \src "libresoc.v:130903.7-130903.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131170.3-131190.6"
+ attribute \src "libresoc.v:130995.3-131015.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131191.3-131211.6"
+ attribute \src "libresoc.v:131016.3-131036.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131170.3-131190.6"
+ attribute \src "libresoc.v:130995.3-131015.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131191.3-131211.6"
+ attribute \src "libresoc.v:131016.3-131036.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131170.3-131190.6"
+ attribute \src "libresoc.v:130995.3-131015.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131191.3-131211.6"
+ attribute \src "libresoc.v:131016.3-131036.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \LOGICAL_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \LOGICAL_internal_op
- attribute \src "libresoc.v:131078.7-131078.15"
+ attribute \src "libresoc.v:130903.7-130903.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131078.7-131078.20"
- process $proc$libresoc.v:131078$5059
+ attribute \src "libresoc.v:130903.7-130903.20"
+ process $proc$libresoc.v:130903$5043
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131170.3-131190.6"
- process $proc$libresoc.v:131170$5057
+ attribute \src "libresoc.v:130995.3-131015.6"
+ process $proc$libresoc.v:130995$5041
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131171.5-131171.29"
+ attribute \src "libresoc.v:130996.5-130996.29"
switch \initial
- attribute \src "libresoc.v:131171.9-131171.17"
+ attribute \src "libresoc.v:130996.9-130996.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131191.3-131211.6"
- process $proc$libresoc.v:131191$5058
+ attribute \src "libresoc.v:131016.3-131036.6"
+ process $proc$libresoc.v:131016$5042
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131192.5-131192.29"
+ attribute \src "libresoc.v:131017.5-131017.29"
switch \initial
- attribute \src "libresoc.v:131192.9-131192.17"
+ attribute \src "libresoc.v:131017.9-131017.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131216.1-131349.10"
+attribute \src "libresoc.v:131041.1-131174.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe"
attribute \generator "nMigen"
module \dec_oe$152
- attribute \src "libresoc.v:131217.7-131217.20"
+ attribute \src "libresoc.v:131042.7-131042.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131307.3-131327.6"
+ attribute \src "libresoc.v:131132.3-131152.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131328.3-131348.6"
+ attribute \src "libresoc.v:131153.3-131173.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131307.3-131327.6"
+ attribute \src "libresoc.v:131132.3-131152.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131328.3-131348.6"
+ attribute \src "libresoc.v:131153.3-131173.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131307.3-131327.6"
+ attribute \src "libresoc.v:131132.3-131152.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131328.3-131348.6"
+ attribute \src "libresoc.v:131153.3-131173.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 2 \SPR_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \SPR_internal_op
- attribute \src "libresoc.v:131217.7-131217.15"
+ attribute \src "libresoc.v:131042.7-131042.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:131217.7-131217.20"
- process $proc$libresoc.v:131217$5062
+ attribute \src "libresoc.v:131042.7-131042.20"
+ process $proc$libresoc.v:131042$5046
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131307.3-131327.6"
- process $proc$libresoc.v:131307$5060
+ attribute \src "libresoc.v:131132.3-131152.6"
+ process $proc$libresoc.v:131132$5044
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131308.5-131308.29"
+ attribute \src "libresoc.v:131133.5-131133.29"
switch \initial
- attribute \src "libresoc.v:131308.9-131308.17"
+ attribute \src "libresoc.v:131133.9-131133.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131328.3-131348.6"
- process $proc$libresoc.v:131328$5061
+ attribute \src "libresoc.v:131153.3-131173.6"
+ process $proc$libresoc.v:131153$5045
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131329.5-131329.29"
+ attribute \src "libresoc.v:131154.5-131154.29"
switch \initial
- attribute \src "libresoc.v:131329.9-131329.17"
+ attribute \src "libresoc.v:131154.9-131154.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131353.1-131488.10"
+attribute \src "libresoc.v:131178.1-131313.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe"
attribute \generator "nMigen"
module \dec_oe$155
- attribute \src "libresoc.v:131354.7-131354.20"
+ attribute \src "libresoc.v:131179.7-131179.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131446.3-131466.6"
+ attribute \src "libresoc.v:131271.3-131291.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131467.3-131487.6"
+ attribute \src "libresoc.v:131292.3-131312.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131446.3-131466.6"
+ attribute \src "libresoc.v:131271.3-131291.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131467.3-131487.6"
+ attribute \src "libresoc.v:131292.3-131312.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131446.3-131466.6"
+ attribute \src "libresoc.v:131271.3-131291.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131467.3-131487.6"
+ attribute \src "libresoc.v:131292.3-131312.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \DIV_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \DIV_internal_op
- attribute \src "libresoc.v:131354.7-131354.15"
+ attribute \src "libresoc.v:131179.7-131179.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131354.7-131354.20"
- process $proc$libresoc.v:131354$5065
+ attribute \src "libresoc.v:131179.7-131179.20"
+ process $proc$libresoc.v:131179$5049
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131446.3-131466.6"
- process $proc$libresoc.v:131446$5063
+ attribute \src "libresoc.v:131271.3-131291.6"
+ process $proc$libresoc.v:131271$5047
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131447.5-131447.29"
+ attribute \src "libresoc.v:131272.5-131272.29"
switch \initial
- attribute \src "libresoc.v:131447.9-131447.17"
+ attribute \src "libresoc.v:131272.9-131272.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131467.3-131487.6"
- process $proc$libresoc.v:131467$5064
+ attribute \src "libresoc.v:131292.3-131312.6"
+ process $proc$libresoc.v:131292$5048
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131468.5-131468.29"
+ attribute \src "libresoc.v:131293.5-131293.29"
switch \initial
- attribute \src "libresoc.v:131468.9-131468.17"
+ attribute \src "libresoc.v:131293.9-131293.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131492.1-131627.10"
+attribute \src "libresoc.v:131317.1-131452.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe"
attribute \generator "nMigen"
module \dec_oe$160
- attribute \src "libresoc.v:131493.7-131493.20"
+ attribute \src "libresoc.v:131318.7-131318.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131585.3-131605.6"
+ attribute \src "libresoc.v:131410.3-131430.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131606.3-131626.6"
+ attribute \src "libresoc.v:131431.3-131451.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131585.3-131605.6"
+ attribute \src "libresoc.v:131410.3-131430.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131606.3-131626.6"
+ attribute \src "libresoc.v:131431.3-131451.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131585.3-131605.6"
+ attribute \src "libresoc.v:131410.3-131430.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131606.3-131626.6"
+ attribute \src "libresoc.v:131431.3-131451.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \MUL_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \MUL_internal_op
- attribute \src "libresoc.v:131493.7-131493.15"
+ attribute \src "libresoc.v:131318.7-131318.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131493.7-131493.20"
- process $proc$libresoc.v:131493$5068
+ attribute \src "libresoc.v:131318.7-131318.20"
+ process $proc$libresoc.v:131318$5052
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131585.3-131605.6"
- process $proc$libresoc.v:131585$5066
+ attribute \src "libresoc.v:131410.3-131430.6"
+ process $proc$libresoc.v:131410$5050
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131586.5-131586.29"
+ attribute \src "libresoc.v:131411.5-131411.29"
switch \initial
- attribute \src "libresoc.v:131586.9-131586.17"
+ attribute \src "libresoc.v:131411.9-131411.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131606.3-131626.6"
- process $proc$libresoc.v:131606$5067
+ attribute \src "libresoc.v:131431.3-131451.6"
+ process $proc$libresoc.v:131431$5051
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131607.5-131607.29"
+ attribute \src "libresoc.v:131432.5-131432.29"
switch \initial
- attribute \src "libresoc.v:131607.9-131607.17"
+ attribute \src "libresoc.v:131432.9-131432.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131631.1-131766.10"
+attribute \src "libresoc.v:131456.1-131591.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe"
attribute \generator "nMigen"
module \dec_oe$164
- attribute \src "libresoc.v:131632.7-131632.20"
+ attribute \src "libresoc.v:131457.7-131457.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131724.3-131744.6"
+ attribute \src "libresoc.v:131549.3-131569.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131745.3-131765.6"
+ attribute \src "libresoc.v:131570.3-131590.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131724.3-131744.6"
+ attribute \src "libresoc.v:131549.3-131569.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131745.3-131765.6"
+ attribute \src "libresoc.v:131570.3-131590.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131724.3-131744.6"
+ attribute \src "libresoc.v:131549.3-131569.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131745.3-131765.6"
+ attribute \src "libresoc.v:131570.3-131590.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \SHIFT_ROT_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \SHIFT_ROT_internal_op
- attribute \src "libresoc.v:131632.7-131632.15"
+ attribute \src "libresoc.v:131457.7-131457.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131632.7-131632.20"
- process $proc$libresoc.v:131632$5071
+ attribute \src "libresoc.v:131457.7-131457.20"
+ process $proc$libresoc.v:131457$5055
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131724.3-131744.6"
- process $proc$libresoc.v:131724$5069
+ attribute \src "libresoc.v:131549.3-131569.6"
+ process $proc$libresoc.v:131549$5053
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131725.5-131725.29"
+ attribute \src "libresoc.v:131550.5-131550.29"
switch \initial
- attribute \src "libresoc.v:131725.9-131725.17"
+ attribute \src "libresoc.v:131550.9-131550.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131745.3-131765.6"
- process $proc$libresoc.v:131745$5070
+ attribute \src "libresoc.v:131570.3-131590.6"
+ process $proc$libresoc.v:131570$5054
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131746.5-131746.29"
+ attribute \src "libresoc.v:131571.5-131571.29"
switch \initial
- attribute \src "libresoc.v:131746.9-131746.17"
+ attribute \src "libresoc.v:131571.9-131571.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131770.1-131905.10"
+attribute \src "libresoc.v:131595.1-131730.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe"
attribute \generator "nMigen"
module \dec_oe$168
- attribute \src "libresoc.v:131771.7-131771.20"
+ attribute \src "libresoc.v:131596.7-131596.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131863.3-131883.6"
+ attribute \src "libresoc.v:131688.3-131708.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:131884.3-131904.6"
+ attribute \src "libresoc.v:131709.3-131729.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:131863.3-131883.6"
+ attribute \src "libresoc.v:131688.3-131708.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:131884.3-131904.6"
+ attribute \src "libresoc.v:131709.3-131729.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:131863.3-131883.6"
+ attribute \src "libresoc.v:131688.3-131708.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:131884.3-131904.6"
+ attribute \src "libresoc.v:131709.3-131729.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \LDST_OE
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \LDST_internal_op
- attribute \src "libresoc.v:131771.7-131771.15"
+ attribute \src "libresoc.v:131596.7-131596.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131771.7-131771.20"
- process $proc$libresoc.v:131771$5074
+ attribute \src "libresoc.v:131596.7-131596.20"
+ process $proc$libresoc.v:131596$5058
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131863.3-131883.6"
- process $proc$libresoc.v:131863$5072
+ attribute \src "libresoc.v:131688.3-131708.6"
+ process $proc$libresoc.v:131688$5056
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:131864.5-131864.29"
+ attribute \src "libresoc.v:131689.5-131689.29"
switch \initial
- attribute \src "libresoc.v:131864.9-131864.17"
+ attribute \src "libresoc.v:131689.9-131689.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:131884.3-131904.6"
- process $proc$libresoc.v:131884$5073
+ attribute \src "libresoc.v:131709.3-131729.6"
+ process $proc$libresoc.v:131709$5057
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:131885.5-131885.29"
+ attribute \src "libresoc.v:131710.5-131710.29"
switch \initial
- attribute \src "libresoc.v:131885.9-131885.17"
+ attribute \src "libresoc.v:131710.9-131710.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:131909.1-132044.10"
+attribute \src "libresoc.v:131734.1-131869.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe"
attribute \generator "nMigen"
module \dec_oe$173
- attribute \src "libresoc.v:131910.7-131910.20"
+ attribute \src "libresoc.v:131735.7-131735.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132002.3-132022.6"
+ attribute \src "libresoc.v:131827.3-131847.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:132023.3-132043.6"
+ attribute \src "libresoc.v:131848.3-131868.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:132002.3-132022.6"
+ attribute \src "libresoc.v:131827.3-131847.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:132023.3-132043.6"
+ attribute \src "libresoc.v:131848.3-131868.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:132002.3-132022.6"
+ attribute \src "libresoc.v:131827.3-131847.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:132023.3-132043.6"
+ attribute \src "libresoc.v:131848.3-131868.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 4 \OE
- attribute \src "libresoc.v:131910.7-131910.15"
+ attribute \src "libresoc.v:131735.7-131735.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:131910.7-131910.20"
- process $proc$libresoc.v:131910$5077
+ attribute \src "libresoc.v:131735.7-131735.20"
+ process $proc$libresoc.v:131735$5061
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132002.3-132022.6"
- process $proc$libresoc.v:132002$5075
+ attribute \src "libresoc.v:131827.3-131847.6"
+ process $proc$libresoc.v:131827$5059
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:132003.5-132003.29"
+ attribute \src "libresoc.v:131828.5-131828.29"
switch \initial
- attribute \src "libresoc.v:132003.9-132003.17"
+ attribute \src "libresoc.v:131828.9-131828.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:132023.3-132043.6"
- process $proc$libresoc.v:132023$5076
+ attribute \src "libresoc.v:131848.3-131868.6"
+ process $proc$libresoc.v:131848$5060
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:132024.5-132024.29"
+ attribute \src "libresoc.v:131849.5-131849.29"
switch \initial
- attribute \src "libresoc.v:132024.9-132024.17"
+ attribute \src "libresoc.v:131849.9-131849.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:132048.1-132102.10"
+attribute \src "libresoc.v:131873.1-131927.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc"
attribute \generator "nMigen"
module \dec_rc
- attribute \src "libresoc.v:132049.7-132049.20"
+ attribute \src "libresoc.v:131874.7-131874.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132064.3-132082.6"
+ attribute \src "libresoc.v:131889.3-131907.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132083.3-132101.6"
+ attribute \src "libresoc.v:131908.3-131926.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132064.3-132082.6"
+ attribute \src "libresoc.v:131889.3-131907.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132083.3-132101.6"
+ attribute \src "libresoc.v:131908.3-131926.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \ALU_Rc
- attribute \src "libresoc.v:132049.7-132049.15"
+ attribute \src "libresoc.v:131874.7-131874.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132049.7-132049.20"
- process $proc$libresoc.v:132049$5080
+ attribute \src "libresoc.v:131874.7-131874.20"
+ process $proc$libresoc.v:131874$5064
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132064.3-132082.6"
- process $proc$libresoc.v:132064$5078
+ attribute \src "libresoc.v:131889.3-131907.6"
+ process $proc$libresoc.v:131889$5062
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132065.5-132065.29"
+ attribute \src "libresoc.v:131890.5-131890.29"
switch \initial
- attribute \src "libresoc.v:132065.9-132065.17"
+ attribute \src "libresoc.v:131890.9-131890.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132083.3-132101.6"
- process $proc$libresoc.v:132083$5079
+ attribute \src "libresoc.v:131908.3-131926.6"
+ process $proc$libresoc.v:131908$5063
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132084.5-132084.29"
+ attribute \src "libresoc.v:131909.5-131909.29"
switch \initial
- attribute \src "libresoc.v:132084.9-132084.17"
+ attribute \src "libresoc.v:131909.9-131909.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132106.1-132158.10"
+attribute \src "libresoc.v:131931.1-131983.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc"
attribute \generator "nMigen"
module \dec_rc$139
- attribute \src "libresoc.v:132107.7-132107.20"
+ attribute \src "libresoc.v:131932.7-131932.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132120.3-132138.6"
+ attribute \src "libresoc.v:131945.3-131963.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132139.3-132157.6"
+ attribute \src "libresoc.v:131964.3-131982.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132120.3-132138.6"
+ attribute \src "libresoc.v:131945.3-131963.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132139.3-132157.6"
+ attribute \src "libresoc.v:131964.3-131982.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 1 \CR_Rc
- attribute \src "libresoc.v:132107.7-132107.15"
+ attribute \src "libresoc.v:131932.7-131932.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:132107.7-132107.20"
- process $proc$libresoc.v:132107$5083
+ attribute \src "libresoc.v:131932.7-131932.20"
+ process $proc$libresoc.v:131932$5067
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132120.3-132138.6"
- process $proc$libresoc.v:132120$5081
+ attribute \src "libresoc.v:131945.3-131963.6"
+ process $proc$libresoc.v:131945$5065
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132121.5-132121.29"
+ attribute \src "libresoc.v:131946.5-131946.29"
switch \initial
- attribute \src "libresoc.v:132121.9-132121.17"
+ attribute \src "libresoc.v:131946.9-131946.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132139.3-132157.6"
- process $proc$libresoc.v:132139$5082
+ attribute \src "libresoc.v:131964.3-131982.6"
+ process $proc$libresoc.v:131964$5066
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132140.5-132140.29"
+ attribute \src "libresoc.v:131965.5-131965.29"
switch \initial
- attribute \src "libresoc.v:132140.9-132140.17"
+ attribute \src "libresoc.v:131965.9-131965.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132162.1-132214.10"
+attribute \src "libresoc.v:131987.1-132039.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc"
attribute \generator "nMigen"
module \dec_rc$142
- attribute \src "libresoc.v:132163.7-132163.20"
+ attribute \src "libresoc.v:131988.7-131988.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132176.3-132194.6"
+ attribute \src "libresoc.v:132001.3-132019.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132195.3-132213.6"
+ attribute \src "libresoc.v:132020.3-132038.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132176.3-132194.6"
+ attribute \src "libresoc.v:132001.3-132019.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132195.3-132213.6"
+ attribute \src "libresoc.v:132020.3-132038.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 1 \BRANCH_Rc
- attribute \src "libresoc.v:132163.7-132163.15"
+ attribute \src "libresoc.v:131988.7-131988.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:132163.7-132163.20"
- process $proc$libresoc.v:132163$5086
+ attribute \src "libresoc.v:131988.7-131988.20"
+ process $proc$libresoc.v:131988$5070
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132176.3-132194.6"
- process $proc$libresoc.v:132176$5084
+ attribute \src "libresoc.v:132001.3-132019.6"
+ process $proc$libresoc.v:132001$5068
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132177.5-132177.29"
+ attribute \src "libresoc.v:132002.5-132002.29"
switch \initial
- attribute \src "libresoc.v:132177.9-132177.17"
+ attribute \src "libresoc.v:132002.9-132002.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132195.3-132213.6"
- process $proc$libresoc.v:132195$5085
+ attribute \src "libresoc.v:132020.3-132038.6"
+ process $proc$libresoc.v:132020$5069
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132196.5-132196.29"
+ attribute \src "libresoc.v:132021.5-132021.29"
switch \initial
- attribute \src "libresoc.v:132196.9-132196.17"
+ attribute \src "libresoc.v:132021.9-132021.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132218.1-132272.10"
+attribute \src "libresoc.v:132043.1-132097.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc"
attribute \generator "nMigen"
module \dec_rc$146
- attribute \src "libresoc.v:132219.7-132219.20"
+ attribute \src "libresoc.v:132044.7-132044.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132234.3-132252.6"
+ attribute \src "libresoc.v:132059.3-132077.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132253.3-132271.6"
+ attribute \src "libresoc.v:132078.3-132096.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132234.3-132252.6"
+ attribute \src "libresoc.v:132059.3-132077.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132253.3-132271.6"
+ attribute \src "libresoc.v:132078.3-132096.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \LOGICAL_Rc
- attribute \src "libresoc.v:132219.7-132219.15"
+ attribute \src "libresoc.v:132044.7-132044.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132219.7-132219.20"
- process $proc$libresoc.v:132219$5089
+ attribute \src "libresoc.v:132044.7-132044.20"
+ process $proc$libresoc.v:132044$5073
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132234.3-132252.6"
- process $proc$libresoc.v:132234$5087
+ attribute \src "libresoc.v:132059.3-132077.6"
+ process $proc$libresoc.v:132059$5071
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132235.5-132235.29"
+ attribute \src "libresoc.v:132060.5-132060.29"
switch \initial
- attribute \src "libresoc.v:132235.9-132235.17"
+ attribute \src "libresoc.v:132060.9-132060.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132253.3-132271.6"
- process $proc$libresoc.v:132253$5088
+ attribute \src "libresoc.v:132078.3-132096.6"
+ process $proc$libresoc.v:132078$5072
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132254.5-132254.29"
+ attribute \src "libresoc.v:132079.5-132079.29"
switch \initial
- attribute \src "libresoc.v:132254.9-132254.17"
+ attribute \src "libresoc.v:132079.9-132079.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132276.1-132328.10"
+attribute \src "libresoc.v:132101.1-132153.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc"
attribute \generator "nMigen"
module \dec_rc$151
- attribute \src "libresoc.v:132277.7-132277.20"
+ attribute \src "libresoc.v:132102.7-132102.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132290.3-132308.6"
+ attribute \src "libresoc.v:132115.3-132133.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132309.3-132327.6"
+ attribute \src "libresoc.v:132134.3-132152.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132290.3-132308.6"
+ attribute \src "libresoc.v:132115.3-132133.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132309.3-132327.6"
+ attribute \src "libresoc.v:132134.3-132152.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 1 \SPR_Rc
- attribute \src "libresoc.v:132277.7-132277.15"
+ attribute \src "libresoc.v:132102.7-132102.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:132277.7-132277.20"
- process $proc$libresoc.v:132277$5092
+ attribute \src "libresoc.v:132102.7-132102.20"
+ process $proc$libresoc.v:132102$5076
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132290.3-132308.6"
- process $proc$libresoc.v:132290$5090
+ attribute \src "libresoc.v:132115.3-132133.6"
+ process $proc$libresoc.v:132115$5074
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132291.5-132291.29"
+ attribute \src "libresoc.v:132116.5-132116.29"
switch \initial
- attribute \src "libresoc.v:132291.9-132291.17"
+ attribute \src "libresoc.v:132116.9-132116.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132309.3-132327.6"
- process $proc$libresoc.v:132309$5091
+ attribute \src "libresoc.v:132134.3-132152.6"
+ process $proc$libresoc.v:132134$5075
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132310.5-132310.29"
+ attribute \src "libresoc.v:132135.5-132135.29"
switch \initial
- attribute \src "libresoc.v:132310.9-132310.17"
+ attribute \src "libresoc.v:132135.9-132135.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132332.1-132386.10"
+attribute \src "libresoc.v:132157.1-132211.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc"
attribute \generator "nMigen"
module \dec_rc$154
- attribute \src "libresoc.v:132333.7-132333.20"
+ attribute \src "libresoc.v:132158.7-132158.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132348.3-132366.6"
+ attribute \src "libresoc.v:132173.3-132191.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132367.3-132385.6"
+ attribute \src "libresoc.v:132192.3-132210.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132348.3-132366.6"
+ attribute \src "libresoc.v:132173.3-132191.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132367.3-132385.6"
+ attribute \src "libresoc.v:132192.3-132210.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \DIV_Rc
- attribute \src "libresoc.v:132333.7-132333.15"
+ attribute \src "libresoc.v:132158.7-132158.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132333.7-132333.20"
- process $proc$libresoc.v:132333$5095
+ attribute \src "libresoc.v:132158.7-132158.20"
+ process $proc$libresoc.v:132158$5079
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132348.3-132366.6"
- process $proc$libresoc.v:132348$5093
+ attribute \src "libresoc.v:132173.3-132191.6"
+ process $proc$libresoc.v:132173$5077
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132349.5-132349.29"
+ attribute \src "libresoc.v:132174.5-132174.29"
switch \initial
- attribute \src "libresoc.v:132349.9-132349.17"
+ attribute \src "libresoc.v:132174.9-132174.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132367.3-132385.6"
- process $proc$libresoc.v:132367$5094
+ attribute \src "libresoc.v:132192.3-132210.6"
+ process $proc$libresoc.v:132192$5078
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132368.5-132368.29"
+ attribute \src "libresoc.v:132193.5-132193.29"
switch \initial
- attribute \src "libresoc.v:132368.9-132368.17"
+ attribute \src "libresoc.v:132193.9-132193.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132390.1-132444.10"
+attribute \src "libresoc.v:132215.1-132269.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc"
attribute \generator "nMigen"
module \dec_rc$159
- attribute \src "libresoc.v:132391.7-132391.20"
+ attribute \src "libresoc.v:132216.7-132216.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132406.3-132424.6"
+ attribute \src "libresoc.v:132231.3-132249.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132425.3-132443.6"
+ attribute \src "libresoc.v:132250.3-132268.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132406.3-132424.6"
+ attribute \src "libresoc.v:132231.3-132249.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132425.3-132443.6"
+ attribute \src "libresoc.v:132250.3-132268.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \MUL_Rc
- attribute \src "libresoc.v:132391.7-132391.15"
+ attribute \src "libresoc.v:132216.7-132216.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132391.7-132391.20"
- process $proc$libresoc.v:132391$5098
+ attribute \src "libresoc.v:132216.7-132216.20"
+ process $proc$libresoc.v:132216$5082
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132406.3-132424.6"
- process $proc$libresoc.v:132406$5096
+ attribute \src "libresoc.v:132231.3-132249.6"
+ process $proc$libresoc.v:132231$5080
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132407.5-132407.29"
+ attribute \src "libresoc.v:132232.5-132232.29"
switch \initial
- attribute \src "libresoc.v:132407.9-132407.17"
+ attribute \src "libresoc.v:132232.9-132232.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132425.3-132443.6"
- process $proc$libresoc.v:132425$5097
+ attribute \src "libresoc.v:132250.3-132268.6"
+ process $proc$libresoc.v:132250$5081
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132426.5-132426.29"
+ attribute \src "libresoc.v:132251.5-132251.29"
switch \initial
- attribute \src "libresoc.v:132426.9-132426.17"
+ attribute \src "libresoc.v:132251.9-132251.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132448.1-132502.10"
+attribute \src "libresoc.v:132273.1-132327.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc"
attribute \generator "nMigen"
module \dec_rc$163
- attribute \src "libresoc.v:132449.7-132449.20"
+ attribute \src "libresoc.v:132274.7-132274.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132464.3-132482.6"
+ attribute \src "libresoc.v:132289.3-132307.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132483.3-132501.6"
+ attribute \src "libresoc.v:132308.3-132326.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132464.3-132482.6"
+ attribute \src "libresoc.v:132289.3-132307.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132483.3-132501.6"
+ attribute \src "libresoc.v:132308.3-132326.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \SHIFT_ROT_Rc
- attribute \src "libresoc.v:132449.7-132449.15"
+ attribute \src "libresoc.v:132274.7-132274.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132449.7-132449.20"
- process $proc$libresoc.v:132449$5101
+ attribute \src "libresoc.v:132274.7-132274.20"
+ process $proc$libresoc.v:132274$5085
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132464.3-132482.6"
- process $proc$libresoc.v:132464$5099
+ attribute \src "libresoc.v:132289.3-132307.6"
+ process $proc$libresoc.v:132289$5083
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132465.5-132465.29"
+ attribute \src "libresoc.v:132290.5-132290.29"
switch \initial
- attribute \src "libresoc.v:132465.9-132465.17"
+ attribute \src "libresoc.v:132290.9-132290.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132483.3-132501.6"
- process $proc$libresoc.v:132483$5100
+ attribute \src "libresoc.v:132308.3-132326.6"
+ process $proc$libresoc.v:132308$5084
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132484.5-132484.29"
+ attribute \src "libresoc.v:132309.5-132309.29"
switch \initial
- attribute \src "libresoc.v:132484.9-132484.17"
+ attribute \src "libresoc.v:132309.9-132309.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132506.1-132560.10"
+attribute \src "libresoc.v:132331.1-132385.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc"
attribute \generator "nMigen"
module \dec_rc$167
- attribute \src "libresoc.v:132507.7-132507.20"
+ attribute \src "libresoc.v:132332.7-132332.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132522.3-132540.6"
+ attribute \src "libresoc.v:132347.3-132365.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132541.3-132559.6"
+ attribute \src "libresoc.v:132366.3-132384.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132522.3-132540.6"
+ attribute \src "libresoc.v:132347.3-132365.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132541.3-132559.6"
+ attribute \src "libresoc.v:132366.3-132384.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \LDST_Rc
- attribute \src "libresoc.v:132507.7-132507.15"
+ attribute \src "libresoc.v:132332.7-132332.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132507.7-132507.20"
- process $proc$libresoc.v:132507$5104
+ attribute \src "libresoc.v:132332.7-132332.20"
+ process $proc$libresoc.v:132332$5088
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132522.3-132540.6"
- process $proc$libresoc.v:132522$5102
+ attribute \src "libresoc.v:132347.3-132365.6"
+ process $proc$libresoc.v:132347$5086
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132523.5-132523.29"
+ attribute \src "libresoc.v:132348.5-132348.29"
switch \initial
- attribute \src "libresoc.v:132523.9-132523.17"
+ attribute \src "libresoc.v:132348.9-132348.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132541.3-132559.6"
- process $proc$libresoc.v:132541$5103
+ attribute \src "libresoc.v:132366.3-132384.6"
+ process $proc$libresoc.v:132366$5087
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132542.5-132542.29"
+ attribute \src "libresoc.v:132367.5-132367.29"
switch \initial
- attribute \src "libresoc.v:132542.9-132542.17"
+ attribute \src "libresoc.v:132367.9-132367.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132564.1-132618.10"
+attribute \src "libresoc.v:132389.1-132443.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc"
attribute \generator "nMigen"
module \dec_rc$172
- attribute \src "libresoc.v:132565.7-132565.20"
+ attribute \src "libresoc.v:132390.7-132390.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:132580.3-132598.6"
+ attribute \src "libresoc.v:132405.3-132423.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:132599.3-132617.6"
+ attribute \src "libresoc.v:132424.3-132442.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:132580.3-132598.6"
+ attribute \src "libresoc.v:132405.3-132423.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:132599.3-132617.6"
+ attribute \src "libresoc.v:132424.3-132442.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire input 3 \Rc
- attribute \src "libresoc.v:132565.7-132565.15"
+ attribute \src "libresoc.v:132390.7-132390.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:132565.7-132565.20"
- process $proc$libresoc.v:132565$5107
+ attribute \src "libresoc.v:132390.7-132390.20"
+ process $proc$libresoc.v:132390$5091
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132580.3-132598.6"
- process $proc$libresoc.v:132580$5105
+ attribute \src "libresoc.v:132405.3-132423.6"
+ process $proc$libresoc.v:132405$5089
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:132581.5-132581.29"
+ attribute \src "libresoc.v:132406.5-132406.29"
switch \initial
- attribute \src "libresoc.v:132581.9-132581.17"
+ attribute \src "libresoc.v:132406.9-132406.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:132599.3-132617.6"
- process $proc$libresoc.v:132599$5106
+ attribute \src "libresoc.v:132424.3-132442.6"
+ process $proc$libresoc.v:132424$5090
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:132600.5-132600.29"
+ attribute \src "libresoc.v:132425.5-132425.29"
switch \initial
- attribute \src "libresoc.v:132600.9-132600.17"
+ attribute \src "libresoc.v:132425.9-132425.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:132622.1-133866.10"
+attribute \src "libresoc.v:132447.1-133691.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0"
attribute \generator "nMigen"
module \div0
- attribute \src "libresoc.v:133423.3-133424.25"
+ attribute \src "libresoc.v:133248.3-133249.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247
- attribute \src "libresoc.v:133395.3-133396.75"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5231
+ attribute \src "libresoc.v:133220.3-133221.75"
wire width 4 $0\alu_div0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248
- attribute \src "libresoc.v:133365.3-133366.73"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5232
+ attribute \src "libresoc.v:133190.3-133191.73"
wire width 14 $0\alu_div0_logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249
- attribute \src "libresoc.v:133367.3-133368.87"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233
+ attribute \src "libresoc.v:133192.3-133193.87"
wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250
- attribute \src "libresoc.v:133369.3-133370.83"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234
+ attribute \src "libresoc.v:133194.3-133195.83"
wire $0\alu_div0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251
- attribute \src "libresoc.v:133383.3-133384.81"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5235
+ attribute \src "libresoc.v:133208.3-133209.81"
wire width 2 $0\alu_div0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252
- attribute \src "libresoc.v:133397.3-133398.67"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5236
+ attribute \src "libresoc.v:133222.3-133223.67"
wire width 32 $0\alu_div0_logical_op__insn[31:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253
- attribute \src "libresoc.v:133363.3-133364.77"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5237
+ attribute \src "libresoc.v:133188.3-133189.77"
wire width 7 $0\alu_div0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254
- attribute \src "libresoc.v:133379.3-133380.77"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__invert_in$next[0:0]$5238
+ attribute \src "libresoc.v:133204.3-133205.77"
wire $0\alu_div0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255
- attribute \src "libresoc.v:133385.3-133386.79"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__invert_out$next[0:0]$5239
+ attribute \src "libresoc.v:133210.3-133211.79"
wire $0\alu_div0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256
- attribute \src "libresoc.v:133391.3-133392.75"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5240
+ attribute \src "libresoc.v:133216.3-133217.75"
wire $0\alu_div0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257
- attribute \src "libresoc.v:133393.3-133394.77"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__is_signed$next[0:0]$5241
+ attribute \src "libresoc.v:133218.3-133219.77"
wire $0\alu_div0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258
- attribute \src "libresoc.v:133375.3-133376.71"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5242
+ attribute \src "libresoc.v:133200.3-133201.71"
wire $0\alu_div0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259
- attribute \src "libresoc.v:133377.3-133378.71"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5243
+ attribute \src "libresoc.v:133202.3-133203.71"
wire $0\alu_div0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260
- attribute \src "libresoc.v:133389.3-133390.83"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__output_carry$next[0:0]$5244
+ attribute \src "libresoc.v:133214.3-133215.83"
wire $0\alu_div0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261
- attribute \src "libresoc.v:133373.3-133374.71"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5245
+ attribute \src "libresoc.v:133198.3-133199.71"
wire $0\alu_div0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262
- attribute \src "libresoc.v:133371.3-133372.71"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5246
+ attribute \src "libresoc.v:133196.3-133197.71"
wire $0\alu_div0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263
- attribute \src "libresoc.v:133387.3-133388.77"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5247
+ attribute \src "libresoc.v:133212.3-133213.77"
wire $0\alu_div0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264
- attribute \src "libresoc.v:133381.3-133382.71"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $0\alu_div0_logical_op__zero_a$next[0:0]$5248
+ attribute \src "libresoc.v:133206.3-133207.71"
wire $0\alu_div0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:133421.3-133422.40"
+ attribute \src "libresoc.v:133246.3-133247.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:133776.3-133784.6"
- wire $0\alu_l_r_alu$next[0:0]$5334
- attribute \src "libresoc.v:133337.3-133338.39"
+ attribute \src "libresoc.v:133601.3-133609.6"
+ wire $0\alu_l_r_alu$next[0:0]$5318
+ attribute \src "libresoc.v:133162.3-133163.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:133767.3-133775.6"
- wire $0\alui_l_r_alui$next[0:0]$5331
- attribute \src "libresoc.v:133339.3-133340.43"
+ attribute \src "libresoc.v:133592.3-133600.6"
+ wire $0\alui_l_r_alui$next[0:0]$5315
+ attribute \src "libresoc.v:133164.3-133165.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:133649.3-133670.6"
- wire width 64 $0\data_r0__o$next[63:0]$5290
- attribute \src "libresoc.v:133359.3-133360.37"
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire width 64 $0\data_r0__o$next[63:0]$5274
+ attribute \src "libresoc.v:133184.3-133185.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:133649.3-133670.6"
- wire $0\data_r0__o_ok$next[0:0]$5291
- attribute \src "libresoc.v:133361.3-133362.43"
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire $0\data_r0__o_ok$next[0:0]$5275
+ attribute \src "libresoc.v:133186.3-133187.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:133671.3-133692.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$5298
- attribute \src "libresoc.v:133355.3-133356.43"
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$5282
+ attribute \src "libresoc.v:133180.3-133181.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:133671.3-133692.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$5299
- attribute \src "libresoc.v:133357.3-133358.49"
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$5283
+ attribute \src "libresoc.v:133182.3-133183.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:133693.3-133714.6"
- wire width 2 $0\data_r2__xer_ov$next[1:0]$5306
- attribute \src "libresoc.v:133351.3-133352.47"
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire width 2 $0\data_r2__xer_ov$next[1:0]$5290
+ attribute \src "libresoc.v:133176.3-133177.47"
wire width 2 $0\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:133693.3-133714.6"
- wire $0\data_r2__xer_ov_ok$next[0:0]$5307
- attribute \src "libresoc.v:133353.3-133354.53"
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire $0\data_r2__xer_ov_ok$next[0:0]$5291
+ attribute \src "libresoc.v:133178.3-133179.53"
wire $0\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $0\data_r3__xer_so$next[0:0]$5314
- attribute \src "libresoc.v:133347.3-133348.47"
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $0\data_r3__xer_so$next[0:0]$5298
+ attribute \src "libresoc.v:133172.3-133173.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$5315
- attribute \src "libresoc.v:133349.3-133350.53"
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$5299
+ attribute \src "libresoc.v:133174.3-133175.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:133785.3-133794.6"
+ attribute \src "libresoc.v:133610.3-133619.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:133795.3-133804.6"
+ attribute \src "libresoc.v:133620.3-133629.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:133805.3-133814.6"
+ attribute \src "libresoc.v:133630.3-133639.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:133815.3-133824.6"
+ attribute \src "libresoc.v:133640.3-133649.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:132623.7-132623.20"
+ attribute \src "libresoc.v:132448.7-132448.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:133565.3-133573.6"
- wire $0\opc_l_r_opc$next[0:0]$5232
- attribute \src "libresoc.v:133407.3-133408.39"
+ attribute \src "libresoc.v:133390.3-133398.6"
+ wire $0\opc_l_r_opc$next[0:0]$5216
+ attribute \src "libresoc.v:133232.3-133233.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:133556.3-133564.6"
- wire $0\opc_l_s_opc$next[0:0]$5229
- attribute \src "libresoc.v:133409.3-133410.39"
+ attribute \src "libresoc.v:133381.3-133389.6"
+ wire $0\opc_l_s_opc$next[0:0]$5213
+ attribute \src "libresoc.v:133234.3-133235.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:133825.3-133833.6"
- wire width 4 $0\prev_wr_go$next[3:0]$5341
- attribute \src "libresoc.v:133419.3-133420.37"
+ attribute \src "libresoc.v:133650.3-133658.6"
+ wire width 4 $0\prev_wr_go$next[3:0]$5325
+ attribute \src "libresoc.v:133244.3-133245.37"
wire width 4 $0\prev_wr_go[3:0]
- attribute \src "libresoc.v:133510.3-133519.6"
+ attribute \src "libresoc.v:133335.3-133344.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:133601.3-133609.6"
- wire width 4 $0\req_l_r_req$next[3:0]$5244
- attribute \src "libresoc.v:133399.3-133400.39"
+ attribute \src "libresoc.v:133426.3-133434.6"
+ wire width 4 $0\req_l_r_req$next[3:0]$5228
+ attribute \src "libresoc.v:133224.3-133225.39"
wire width 4 $0\req_l_r_req[3:0]
- attribute \src "libresoc.v:133592.3-133600.6"
- wire width 4 $0\req_l_s_req$next[3:0]$5241
- attribute \src "libresoc.v:133401.3-133402.39"
+ attribute \src "libresoc.v:133417.3-133425.6"
+ wire width 4 $0\req_l_s_req$next[3:0]$5225
+ attribute \src "libresoc.v:133226.3-133227.39"
wire width 4 $0\req_l_s_req[3:0]
- attribute \src "libresoc.v:133529.3-133537.6"
- wire $0\rok_l_r_rdok$next[0:0]$5220
- attribute \src "libresoc.v:133415.3-133416.41"
+ attribute \src "libresoc.v:133354.3-133362.6"
+ wire $0\rok_l_r_rdok$next[0:0]$5204
+ attribute \src "libresoc.v:133240.3-133241.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:133520.3-133528.6"
- wire $0\rok_l_s_rdok$next[0:0]$5217
- attribute \src "libresoc.v:133417.3-133418.41"
+ attribute \src "libresoc.v:133345.3-133353.6"
+ wire $0\rok_l_s_rdok$next[0:0]$5201
+ attribute \src "libresoc.v:133242.3-133243.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:133547.3-133555.6"
- wire $0\rst_l_r_rst$next[0:0]$5226
- attribute \src "libresoc.v:133411.3-133412.39"
+ attribute \src "libresoc.v:133372.3-133380.6"
+ wire $0\rst_l_r_rst$next[0:0]$5210
+ attribute \src "libresoc.v:133236.3-133237.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:133538.3-133546.6"
- wire $0\rst_l_s_rst$next[0:0]$5223
- attribute \src "libresoc.v:133413.3-133414.39"
+ attribute \src "libresoc.v:133363.3-133371.6"
+ wire $0\rst_l_s_rst$next[0:0]$5207
+ attribute \src "libresoc.v:133238.3-133239.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:133583.3-133591.6"
- wire width 3 $0\src_l_r_src$next[2:0]$5238
- attribute \src "libresoc.v:133403.3-133404.39"
+ attribute \src "libresoc.v:133408.3-133416.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$5222
+ attribute \src "libresoc.v:133228.3-133229.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:133574.3-133582.6"
- wire width 3 $0\src_l_s_src$next[2:0]$5235
- attribute \src "libresoc.v:133405.3-133406.39"
+ attribute \src "libresoc.v:133399.3-133407.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$5219
+ attribute \src "libresoc.v:133230.3-133231.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:133737.3-133746.6"
- wire width 64 $0\src_r0$next[63:0]$5322
- attribute \src "libresoc.v:133345.3-133346.29"
+ attribute \src "libresoc.v:133562.3-133571.6"
+ wire width 64 $0\src_r0$next[63:0]$5306
+ attribute \src "libresoc.v:133170.3-133171.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:133747.3-133756.6"
- wire width 64 $0\src_r1$next[63:0]$5325
- attribute \src "libresoc.v:133343.3-133344.29"
+ attribute \src "libresoc.v:133572.3-133581.6"
+ wire width 64 $0\src_r1$next[63:0]$5309
+ attribute \src "libresoc.v:133168.3-133169.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:133757.3-133766.6"
- wire $0\src_r2$next[0:0]$5328
- attribute \src "libresoc.v:133341.3-133342.29"
+ attribute \src "libresoc.v:133582.3-133591.6"
+ wire $0\src_r2$next[0:0]$5312
+ attribute \src "libresoc.v:133166.3-133167.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:132753.7-132753.24"
+ attribute \src "libresoc.v:132578.7-132578.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265
- attribute \src "libresoc.v:132763.13-132763.49"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5249
+ attribute \src "libresoc.v:132588.13-132588.49"
wire width 4 $1\alu_div0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266
- attribute \src "libresoc.v:132782.14-132782.53"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250
+ attribute \src "libresoc.v:132607.14-132607.53"
wire width 14 $1\alu_div0_logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267
- attribute \src "libresoc.v:132786.14-132786.72"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251
+ attribute \src "libresoc.v:132611.14-132611.72"
wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268
- attribute \src "libresoc.v:132790.7-132790.47"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252
+ attribute \src "libresoc.v:132615.7-132615.47"
wire $1\alu_div0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269
- attribute \src "libresoc.v:132798.13-132798.52"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5253
+ attribute \src "libresoc.v:132623.13-132623.52"
wire width 2 $1\alu_div0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270
- attribute \src "libresoc.v:132802.14-132802.47"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5254
+ attribute \src "libresoc.v:132627.14-132627.47"
wire width 32 $1\alu_div0_logical_op__insn[31:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271
- attribute \src "libresoc.v:132881.13-132881.51"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5255
+ attribute \src "libresoc.v:132706.13-132706.51"
wire width 7 $1\alu_div0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272
- attribute \src "libresoc.v:132885.7-132885.44"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__invert_in$next[0:0]$5256
+ attribute \src "libresoc.v:132710.7-132710.44"
wire $1\alu_div0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273
- attribute \src "libresoc.v:132889.7-132889.45"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__invert_out$next[0:0]$5257
+ attribute \src "libresoc.v:132714.7-132714.45"
wire $1\alu_div0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274
- attribute \src "libresoc.v:132893.7-132893.43"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5258
+ attribute \src "libresoc.v:132718.7-132718.43"
wire $1\alu_div0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275
- attribute \src "libresoc.v:132897.7-132897.44"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__is_signed$next[0:0]$5259
+ attribute \src "libresoc.v:132722.7-132722.44"
wire $1\alu_div0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276
- attribute \src "libresoc.v:132901.7-132901.41"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5260
+ attribute \src "libresoc.v:132726.7-132726.41"
wire $1\alu_div0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277
- attribute \src "libresoc.v:132905.7-132905.41"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5261
+ attribute \src "libresoc.v:132730.7-132730.41"
wire $1\alu_div0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278
- attribute \src "libresoc.v:132909.7-132909.47"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__output_carry$next[0:0]$5262
+ attribute \src "libresoc.v:132734.7-132734.47"
wire $1\alu_div0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279
- attribute \src "libresoc.v:132913.7-132913.41"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5263
+ attribute \src "libresoc.v:132738.7-132738.41"
wire $1\alu_div0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280
- attribute \src "libresoc.v:132917.7-132917.41"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5264
+ attribute \src "libresoc.v:132742.7-132742.41"
wire $1\alu_div0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281
- attribute \src "libresoc.v:132921.7-132921.44"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5265
+ attribute \src "libresoc.v:132746.7-132746.44"
wire $1\alu_div0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282
- attribute \src "libresoc.v:132925.7-132925.41"
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $1\alu_div0_logical_op__zero_a$next[0:0]$5266
+ attribute \src "libresoc.v:132750.7-132750.41"
wire $1\alu_div0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:132951.7-132951.26"
+ attribute \src "libresoc.v:132776.7-132776.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:133776.3-133784.6"
- wire $1\alu_l_r_alu$next[0:0]$5335
- attribute \src "libresoc.v:132959.7-132959.25"
+ attribute \src "libresoc.v:133601.3-133609.6"
+ wire $1\alu_l_r_alu$next[0:0]$5319
+ attribute \src "libresoc.v:132784.7-132784.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:133767.3-133775.6"
- wire $1\alui_l_r_alui$next[0:0]$5332
- attribute \src "libresoc.v:132971.7-132971.27"
+ attribute \src "libresoc.v:133592.3-133600.6"
+ wire $1\alui_l_r_alui$next[0:0]$5316
+ attribute \src "libresoc.v:132796.7-132796.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:133649.3-133670.6"
- wire width 64 $1\data_r0__o$next[63:0]$5292
- attribute \src "libresoc.v:133005.14-133005.47"
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire width 64 $1\data_r0__o$next[63:0]$5276
+ attribute \src "libresoc.v:132830.14-132830.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:133649.3-133670.6"
- wire $1\data_r0__o_ok$next[0:0]$5293
- attribute \src "libresoc.v:133009.7-133009.27"
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire $1\data_r0__o_ok$next[0:0]$5277
+ attribute \src "libresoc.v:132834.7-132834.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:133671.3-133692.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$5300
- attribute \src "libresoc.v:133013.13-133013.33"
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$5284
+ attribute \src "libresoc.v:132838.13-132838.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:133671.3-133692.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$5301
- attribute \src "libresoc.v:133017.7-133017.30"
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$5285
+ attribute \src "libresoc.v:132842.7-132842.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:133693.3-133714.6"
- wire width 2 $1\data_r2__xer_ov$next[1:0]$5308
- attribute \src "libresoc.v:133021.13-133021.35"
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire width 2 $1\data_r2__xer_ov$next[1:0]$5292
+ attribute \src "libresoc.v:132846.13-132846.35"
wire width 2 $1\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:133693.3-133714.6"
- wire $1\data_r2__xer_ov_ok$next[0:0]$5309
- attribute \src "libresoc.v:133025.7-133025.32"
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire $1\data_r2__xer_ov_ok$next[0:0]$5293
+ attribute \src "libresoc.v:132850.7-132850.32"
wire $1\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $1\data_r3__xer_so$next[0:0]$5316
- attribute \src "libresoc.v:133029.7-133029.29"
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $1\data_r3__xer_so$next[0:0]$5300
+ attribute \src "libresoc.v:132854.7-132854.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$5317
- attribute \src "libresoc.v:133033.7-133033.32"
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$5301
+ attribute \src "libresoc.v:132858.7-132858.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:133785.3-133794.6"
+ attribute \src "libresoc.v:133610.3-133619.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:133795.3-133804.6"
+ attribute \src "libresoc.v:133620.3-133629.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:133805.3-133814.6"
+ attribute \src "libresoc.v:133630.3-133639.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:133815.3-133824.6"
+ attribute \src "libresoc.v:133640.3-133649.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:133565.3-133573.6"
- wire $1\opc_l_r_opc$next[0:0]$5233
- attribute \src "libresoc.v:133053.7-133053.25"
+ attribute \src "libresoc.v:133390.3-133398.6"
+ wire $1\opc_l_r_opc$next[0:0]$5217
+ attribute \src "libresoc.v:132878.7-132878.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:133556.3-133564.6"
- wire $1\opc_l_s_opc$next[0:0]$5230
- attribute \src "libresoc.v:133057.7-133057.25"
+ attribute \src "libresoc.v:133381.3-133389.6"
+ wire $1\opc_l_s_opc$next[0:0]$5214
+ attribute \src "libresoc.v:132882.7-132882.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:133825.3-133833.6"
- wire width 4 $1\prev_wr_go$next[3:0]$5342
- attribute \src "libresoc.v:133191.13-133191.30"
+ attribute \src "libresoc.v:133650.3-133658.6"
+ wire width 4 $1\prev_wr_go$next[3:0]$5326
+ attribute \src "libresoc.v:133016.13-133016.30"
wire width 4 $1\prev_wr_go[3:0]
- attribute \src "libresoc.v:133510.3-133519.6"
+ attribute \src "libresoc.v:133335.3-133344.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:133601.3-133609.6"
- wire width 4 $1\req_l_r_req$next[3:0]$5245
- attribute \src "libresoc.v:133199.13-133199.31"
+ attribute \src "libresoc.v:133426.3-133434.6"
+ wire width 4 $1\req_l_r_req$next[3:0]$5229
+ attribute \src "libresoc.v:133024.13-133024.31"
wire width 4 $1\req_l_r_req[3:0]
- attribute \src "libresoc.v:133592.3-133600.6"
- wire width 4 $1\req_l_s_req$next[3:0]$5242
- attribute \src "libresoc.v:133203.13-133203.31"
+ attribute \src "libresoc.v:133417.3-133425.6"
+ wire width 4 $1\req_l_s_req$next[3:0]$5226
+ attribute \src "libresoc.v:133028.13-133028.31"
wire width 4 $1\req_l_s_req[3:0]
- attribute \src "libresoc.v:133529.3-133537.6"
- wire $1\rok_l_r_rdok$next[0:0]$5221
- attribute \src "libresoc.v:133215.7-133215.26"
+ attribute \src "libresoc.v:133354.3-133362.6"
+ wire $1\rok_l_r_rdok$next[0:0]$5205
+ attribute \src "libresoc.v:133040.7-133040.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:133520.3-133528.6"
- wire $1\rok_l_s_rdok$next[0:0]$5218
- attribute \src "libresoc.v:133219.7-133219.26"
+ attribute \src "libresoc.v:133345.3-133353.6"
+ wire $1\rok_l_s_rdok$next[0:0]$5202
+ attribute \src "libresoc.v:133044.7-133044.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:133547.3-133555.6"
- wire $1\rst_l_r_rst$next[0:0]$5227
- attribute \src "libresoc.v:133223.7-133223.25"
+ attribute \src "libresoc.v:133372.3-133380.6"
+ wire $1\rst_l_r_rst$next[0:0]$5211
+ attribute \src "libresoc.v:133048.7-133048.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:133538.3-133546.6"
- wire $1\rst_l_s_rst$next[0:0]$5224
- attribute \src "libresoc.v:133227.7-133227.25"
+ attribute \src "libresoc.v:133363.3-133371.6"
+ wire $1\rst_l_s_rst$next[0:0]$5208
+ attribute \src "libresoc.v:133052.7-133052.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:133583.3-133591.6"
- wire width 3 $1\src_l_r_src$next[2:0]$5239
- attribute \src "libresoc.v:133241.13-133241.31"
+ attribute \src "libresoc.v:133408.3-133416.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$5223
+ attribute \src "libresoc.v:133066.13-133066.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:133574.3-133582.6"
- wire width 3 $1\src_l_s_src$next[2:0]$5236
- attribute \src "libresoc.v:133245.13-133245.31"
+ attribute \src "libresoc.v:133399.3-133407.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$5220
+ attribute \src "libresoc.v:133070.13-133070.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:133737.3-133746.6"
- wire width 64 $1\src_r0$next[63:0]$5323
- attribute \src "libresoc.v:133253.14-133253.43"
+ attribute \src "libresoc.v:133562.3-133571.6"
+ wire width 64 $1\src_r0$next[63:0]$5307
+ attribute \src "libresoc.v:133078.14-133078.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:133747.3-133756.6"
- wire width 64 $1\src_r1$next[63:0]$5326
- attribute \src "libresoc.v:133257.14-133257.43"
+ attribute \src "libresoc.v:133572.3-133581.6"
+ wire width 64 $1\src_r1$next[63:0]$5310
+ attribute \src "libresoc.v:133082.14-133082.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:133757.3-133766.6"
- wire $1\src_r2$next[0:0]$5329
- attribute \src "libresoc.v:133261.7-133261.20"
+ attribute \src "libresoc.v:133582.3-133591.6"
+ wire $1\src_r2$next[0:0]$5313
+ attribute \src "libresoc.v:133086.7-133086.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:133610.3-133648.6"
- wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287
- attribute \src "libresoc.v:133610.3-133648.6"
- wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288
- attribute \src "libresoc.v:133649.3-133670.6"
- wire width 64 $2\data_r0__o$next[63:0]$5294
- attribute \src "libresoc.v:133649.3-133670.6"
- wire $2\data_r0__o_ok$next[0:0]$5295
- attribute \src "libresoc.v:133671.3-133692.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$5302
- attribute \src "libresoc.v:133671.3-133692.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$5303
- attribute \src "libresoc.v:133693.3-133714.6"
- wire width 2 $2\data_r2__xer_ov$next[1:0]$5310
- attribute \src "libresoc.v:133693.3-133714.6"
- wire $2\data_r2__xer_ov_ok$next[0:0]$5311
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $2\data_r3__xer_so$next[0:0]$5318
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$5319
- attribute \src "libresoc.v:133649.3-133670.6"
- wire $3\data_r0__o_ok$next[0:0]$5296
- attribute \src "libresoc.v:133671.3-133692.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$5304
- attribute \src "libresoc.v:133693.3-133714.6"
- wire $3\data_r2__xer_ov_ok$next[0:0]$5312
- attribute \src "libresoc.v:133715.3-133736.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$5320
- attribute \src "libresoc.v:133276.19-133276.133"
- wire width 3 $and$libresoc.v:133276$5110_Y
- attribute \src "libresoc.v:133278.19-133278.115"
- wire width 3 $and$libresoc.v:133278$5112_Y
- attribute \src "libresoc.v:133279.18-133279.110"
- wire $and$libresoc.v:133279$5113_Y
- attribute \src "libresoc.v:133280.19-133280.125"
- wire $and$libresoc.v:133280$5114_Y
- attribute \src "libresoc.v:133281.19-133281.125"
- wire $and$libresoc.v:133281$5115_Y
- attribute \src "libresoc.v:133282.19-133282.125"
- wire $and$libresoc.v:133282$5116_Y
- attribute \src "libresoc.v:133283.19-133283.125"
- wire $and$libresoc.v:133283$5117_Y
- attribute \src "libresoc.v:133284.19-133284.149"
- wire width 4 $and$libresoc.v:133284$5118_Y
- attribute \src "libresoc.v:133285.19-133285.121"
- wire width 4 $and$libresoc.v:133285$5119_Y
- attribute \src "libresoc.v:133286.19-133286.127"
- wire $and$libresoc.v:133286$5120_Y
- attribute \src "libresoc.v:133287.19-133287.127"
- wire $and$libresoc.v:133287$5121_Y
- attribute \src "libresoc.v:133288.19-133288.127"
- wire $and$libresoc.v:133288$5122_Y
- attribute \src "libresoc.v:133289.19-133289.127"
- wire $and$libresoc.v:133289$5123_Y
- attribute \src "libresoc.v:133291.18-133291.98"
- wire $and$libresoc.v:133291$5125_Y
- attribute \src "libresoc.v:133293.18-133293.100"
- wire $and$libresoc.v:133293$5127_Y
- attribute \src "libresoc.v:133294.18-133294.160"
- wire width 4 $and$libresoc.v:133294$5128_Y
- attribute \src "libresoc.v:133296.18-133296.119"
- wire width 4 $and$libresoc.v:133296$5130_Y
- attribute \src "libresoc.v:133299.17-133299.123"
- wire $and$libresoc.v:133299$5133_Y
- attribute \src "libresoc.v:133300.18-133300.116"
- wire $and$libresoc.v:133300$5134_Y
- attribute \src "libresoc.v:133305.18-133305.113"
- wire $and$libresoc.v:133305$5139_Y
- attribute \src "libresoc.v:133306.18-133306.125"
- wire width 4 $and$libresoc.v:133306$5140_Y
- attribute \src "libresoc.v:133308.18-133308.112"
- wire $and$libresoc.v:133308$5142_Y
- attribute \src "libresoc.v:133310.18-133310.126"
- wire $and$libresoc.v:133310$5144_Y
- attribute \src "libresoc.v:133311.18-133311.126"
- wire $and$libresoc.v:133311$5145_Y
- attribute \src "libresoc.v:133312.18-133312.117"
- wire $and$libresoc.v:133312$5146_Y
- attribute \src "libresoc.v:133318.18-133318.130"
- wire $and$libresoc.v:133318$5152_Y
- attribute \src "libresoc.v:133319.18-133319.124"
- wire width 4 $and$libresoc.v:133319$5153_Y
- attribute \src "libresoc.v:133321.18-133321.116"
- wire $and$libresoc.v:133321$5155_Y
- attribute \src "libresoc.v:133322.18-133322.119"
- wire $and$libresoc.v:133322$5156_Y
- attribute \src "libresoc.v:133323.18-133323.121"
- wire $and$libresoc.v:133323$5157_Y
- attribute \src "libresoc.v:133324.18-133324.121"
- wire $and$libresoc.v:133324$5158_Y
- attribute \src "libresoc.v:133334.18-133334.134"
- wire $and$libresoc.v:133334$5168_Y
- attribute \src "libresoc.v:133335.18-133335.132"
- wire $and$libresoc.v:133335$5169_Y
- attribute \src "libresoc.v:133336.18-133336.149"
- wire width 3 $and$libresoc.v:133336$5170_Y
- attribute \src "libresoc.v:133307.18-133307.113"
- wire $eq$libresoc.v:133307$5141_Y
- attribute \src "libresoc.v:133309.18-133309.119"
- wire $eq$libresoc.v:133309$5143_Y
- attribute \src "libresoc.v:133274.19-133274.130"
- wire $not$libresoc.v:133274$5108_Y
- attribute \src "libresoc.v:133275.19-133275.136"
- wire $not$libresoc.v:133275$5109_Y
- attribute \src "libresoc.v:133277.19-133277.115"
- wire width 3 $not$libresoc.v:133277$5111_Y
- attribute \src "libresoc.v:133290.18-133290.97"
- wire $not$libresoc.v:133290$5124_Y
- attribute \src "libresoc.v:133292.18-133292.99"
- wire $not$libresoc.v:133292$5126_Y
- attribute \src "libresoc.v:133295.18-133295.113"
- wire width 4 $not$libresoc.v:133295$5129_Y
- attribute \src "libresoc.v:133298.18-133298.106"
- wire $not$libresoc.v:133298$5132_Y
- attribute \src "libresoc.v:133304.18-133304.120"
- wire $not$libresoc.v:133304$5138_Y
- attribute \src "libresoc.v:133315.17-133315.113"
- wire width 3 $not$libresoc.v:133315$5149_Y
- attribute \src "libresoc.v:133303.18-133303.112"
- wire $or$libresoc.v:133303$5137_Y
- attribute \src "libresoc.v:133313.18-133313.122"
- wire $or$libresoc.v:133313$5147_Y
- attribute \src "libresoc.v:133314.18-133314.124"
- wire $or$libresoc.v:133314$5148_Y
- attribute \src "libresoc.v:133316.18-133316.168"
- wire width 4 $or$libresoc.v:133316$5150_Y
- attribute \src "libresoc.v:133317.18-133317.155"
- wire width 3 $or$libresoc.v:133317$5151_Y
- attribute \src "libresoc.v:133320.18-133320.120"
- wire width 4 $or$libresoc.v:133320$5154_Y
- attribute \src "libresoc.v:133326.17-133326.117"
- wire width 3 $or$libresoc.v:133326$5160_Y
- attribute \src "libresoc.v:133331.17-133331.104"
- wire $reduce_and$libresoc.v:133331$5165_Y
- attribute \src "libresoc.v:133297.18-133297.106"
- wire $reduce_or$libresoc.v:133297$5131_Y
- attribute \src "libresoc.v:133301.18-133301.113"
- wire $reduce_or$libresoc.v:133301$5135_Y
- attribute \src "libresoc.v:133302.18-133302.112"
- wire $reduce_or$libresoc.v:133302$5136_Y
- attribute \src "libresoc.v:133325.18-133325.158"
- wire $ternary$libresoc.v:133325$5159_Y
- attribute \src "libresoc.v:133327.18-133327.159"
- wire width 64 $ternary$libresoc.v:133327$5161_Y
- attribute \src "libresoc.v:133328.18-133328.164"
- wire $ternary$libresoc.v:133328$5162_Y
- attribute \src "libresoc.v:133329.18-133329.180"
- wire width 64 $ternary$libresoc.v:133329$5163_Y
- attribute \src "libresoc.v:133330.18-133330.115"
- wire width 64 $ternary$libresoc.v:133330$5164_Y
- attribute \src "libresoc.v:133332.18-133332.125"
- wire width 64 $ternary$libresoc.v:133332$5166_Y
- attribute \src "libresoc.v:133333.18-133333.118"
- wire $ternary$libresoc.v:133333$5167_Y
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5269
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5270
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5271
+ attribute \src "libresoc.v:133435.3-133473.6"
+ wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5272
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire width 64 $2\data_r0__o$next[63:0]$5278
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire $2\data_r0__o_ok$next[0:0]$5279
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$5286
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$5287
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire width 2 $2\data_r2__xer_ov$next[1:0]$5294
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire $2\data_r2__xer_ov_ok$next[0:0]$5295
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $2\data_r3__xer_so$next[0:0]$5302
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$5303
+ attribute \src "libresoc.v:133474.3-133495.6"
+ wire $3\data_r0__o_ok$next[0:0]$5280
+ attribute \src "libresoc.v:133496.3-133517.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$5288
+ attribute \src "libresoc.v:133518.3-133539.6"
+ wire $3\data_r2__xer_ov_ok$next[0:0]$5296
+ attribute \src "libresoc.v:133540.3-133561.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$5304
+ attribute \src "libresoc.v:133101.19-133101.133"
+ wire width 3 $and$libresoc.v:133101$5094_Y
+ attribute \src "libresoc.v:133103.19-133103.115"
+ wire width 3 $and$libresoc.v:133103$5096_Y
+ attribute \src "libresoc.v:133104.18-133104.110"
+ wire $and$libresoc.v:133104$5097_Y
+ attribute \src "libresoc.v:133105.19-133105.125"
+ wire $and$libresoc.v:133105$5098_Y
+ attribute \src "libresoc.v:133106.19-133106.125"
+ wire $and$libresoc.v:133106$5099_Y
+ attribute \src "libresoc.v:133107.19-133107.125"
+ wire $and$libresoc.v:133107$5100_Y
+ attribute \src "libresoc.v:133108.19-133108.125"
+ wire $and$libresoc.v:133108$5101_Y
+ attribute \src "libresoc.v:133109.19-133109.149"
+ wire width 4 $and$libresoc.v:133109$5102_Y
+ attribute \src "libresoc.v:133110.19-133110.121"
+ wire width 4 $and$libresoc.v:133110$5103_Y
+ attribute \src "libresoc.v:133111.19-133111.127"
+ wire $and$libresoc.v:133111$5104_Y
+ attribute \src "libresoc.v:133112.19-133112.127"
+ wire $and$libresoc.v:133112$5105_Y
+ attribute \src "libresoc.v:133113.19-133113.127"
+ wire $and$libresoc.v:133113$5106_Y
+ attribute \src "libresoc.v:133114.19-133114.127"
+ wire $and$libresoc.v:133114$5107_Y
+ attribute \src "libresoc.v:133116.18-133116.98"
+ wire $and$libresoc.v:133116$5109_Y
+ attribute \src "libresoc.v:133118.18-133118.100"
+ wire $and$libresoc.v:133118$5111_Y
+ attribute \src "libresoc.v:133119.18-133119.160"
+ wire width 4 $and$libresoc.v:133119$5112_Y
+ attribute \src "libresoc.v:133121.18-133121.119"
+ wire width 4 $and$libresoc.v:133121$5114_Y
+ attribute \src "libresoc.v:133124.17-133124.123"
+ wire $and$libresoc.v:133124$5117_Y
+ attribute \src "libresoc.v:133125.18-133125.116"
+ wire $and$libresoc.v:133125$5118_Y
+ attribute \src "libresoc.v:133130.18-133130.113"
+ wire $and$libresoc.v:133130$5123_Y
+ attribute \src "libresoc.v:133131.18-133131.125"
+ wire width 4 $and$libresoc.v:133131$5124_Y
+ attribute \src "libresoc.v:133133.18-133133.112"
+ wire $and$libresoc.v:133133$5126_Y
+ attribute \src "libresoc.v:133135.18-133135.126"
+ wire $and$libresoc.v:133135$5128_Y
+ attribute \src "libresoc.v:133136.18-133136.126"
+ wire $and$libresoc.v:133136$5129_Y
+ attribute \src "libresoc.v:133137.18-133137.117"
+ wire $and$libresoc.v:133137$5130_Y
+ attribute \src "libresoc.v:133143.18-133143.130"
+ wire $and$libresoc.v:133143$5136_Y
+ attribute \src "libresoc.v:133144.18-133144.124"
+ wire width 4 $and$libresoc.v:133144$5137_Y
+ attribute \src "libresoc.v:133146.18-133146.116"
+ wire $and$libresoc.v:133146$5139_Y
+ attribute \src "libresoc.v:133147.18-133147.119"
+ wire $and$libresoc.v:133147$5140_Y
+ attribute \src "libresoc.v:133148.18-133148.121"
+ wire $and$libresoc.v:133148$5141_Y
+ attribute \src "libresoc.v:133149.18-133149.121"
+ wire $and$libresoc.v:133149$5142_Y
+ attribute \src "libresoc.v:133159.18-133159.134"
+ wire $and$libresoc.v:133159$5152_Y
+ attribute \src "libresoc.v:133160.18-133160.132"
+ wire $and$libresoc.v:133160$5153_Y
+ attribute \src "libresoc.v:133161.18-133161.149"
+ wire width 3 $and$libresoc.v:133161$5154_Y
+ attribute \src "libresoc.v:133132.18-133132.113"
+ wire $eq$libresoc.v:133132$5125_Y
+ attribute \src "libresoc.v:133134.18-133134.119"
+ wire $eq$libresoc.v:133134$5127_Y
+ attribute \src "libresoc.v:133099.19-133099.130"
+ wire $not$libresoc.v:133099$5092_Y
+ attribute \src "libresoc.v:133100.19-133100.136"
+ wire $not$libresoc.v:133100$5093_Y
+ attribute \src "libresoc.v:133102.19-133102.115"
+ wire width 3 $not$libresoc.v:133102$5095_Y
+ attribute \src "libresoc.v:133115.18-133115.97"
+ wire $not$libresoc.v:133115$5108_Y
+ attribute \src "libresoc.v:133117.18-133117.99"
+ wire $not$libresoc.v:133117$5110_Y
+ attribute \src "libresoc.v:133120.18-133120.113"
+ wire width 4 $not$libresoc.v:133120$5113_Y
+ attribute \src "libresoc.v:133123.18-133123.106"
+ wire $not$libresoc.v:133123$5116_Y
+ attribute \src "libresoc.v:133129.18-133129.120"
+ wire $not$libresoc.v:133129$5122_Y
+ attribute \src "libresoc.v:133140.17-133140.113"
+ wire width 3 $not$libresoc.v:133140$5133_Y
+ attribute \src "libresoc.v:133128.18-133128.112"
+ wire $or$libresoc.v:133128$5121_Y
+ attribute \src "libresoc.v:133138.18-133138.122"
+ wire $or$libresoc.v:133138$5131_Y
+ attribute \src "libresoc.v:133139.18-133139.124"
+ wire $or$libresoc.v:133139$5132_Y
+ attribute \src "libresoc.v:133141.18-133141.168"
+ wire width 4 $or$libresoc.v:133141$5134_Y
+ attribute \src "libresoc.v:133142.18-133142.155"
+ wire width 3 $or$libresoc.v:133142$5135_Y
+ attribute \src "libresoc.v:133145.18-133145.120"
+ wire width 4 $or$libresoc.v:133145$5138_Y
+ attribute \src "libresoc.v:133151.17-133151.117"
+ wire width 3 $or$libresoc.v:133151$5144_Y
+ attribute \src "libresoc.v:133156.17-133156.104"
+ wire $reduce_and$libresoc.v:133156$5149_Y
+ attribute \src "libresoc.v:133122.18-133122.106"
+ wire $reduce_or$libresoc.v:133122$5115_Y
+ attribute \src "libresoc.v:133126.18-133126.113"
+ wire $reduce_or$libresoc.v:133126$5119_Y
+ attribute \src "libresoc.v:133127.18-133127.112"
+ wire $reduce_or$libresoc.v:133127$5120_Y
+ attribute \src "libresoc.v:133150.18-133150.158"
+ wire $ternary$libresoc.v:133150$5143_Y
+ attribute \src "libresoc.v:133152.18-133152.159"
+ wire width 64 $ternary$libresoc.v:133152$5145_Y
+ attribute \src "libresoc.v:133153.18-133153.164"
+ wire $ternary$libresoc.v:133153$5146_Y
+ attribute \src "libresoc.v:133154.18-133154.180"
+ wire width 64 $ternary$libresoc.v:133154$5147_Y
+ attribute \src "libresoc.v:133155.18-133155.115"
+ wire width 64 $ternary$libresoc.v:133155$5148_Y
+ attribute \src "libresoc.v:133157.18-133157.125"
+ wire width 64 $ternary$libresoc.v:133157$5150_Y
+ attribute \src "libresoc.v:133158.18-133158.118"
+ wire $ternary$libresoc.v:133158$5151_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 32 \cr_a_ok
wire width 2 output 35 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire output 37 \dest4_o
- attribute \src "libresoc.v:132623.7-132623.15"
+ attribute \src "libresoc.v:132448.7-132448.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 25 \src1_i
+ wire width 64 input 26 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 26 \src2_i
+ wire width 64 input 25 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 27 \src3_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 36 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:133276$5110
+ cell $and $and$libresoc.v:133101$5094
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$98
connect \B { 1'1 \$102 \$100 }
- connect \Y $and$libresoc.v:133276$5110_Y
+ connect \Y $and$libresoc.v:133101$5094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:133278$5112
+ cell $and $and$libresoc.v:133103$5096
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$104
connect \B \$106
- connect \Y $and$libresoc.v:133278$5112_Y
+ connect \Y $and$libresoc.v:133103$5096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:133279$5113
+ cell $and $and$libresoc.v:133104$5097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:133279$5113_Y
+ connect \Y $and$libresoc.v:133104$5097_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:133280$5114
+ cell $and $and$libresoc.v:133105$5098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:133280$5114_Y
+ connect \Y $and$libresoc.v:133105$5098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:133281$5115
+ cell $and $and$libresoc.v:133106$5099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:133281$5115_Y
+ connect \Y $and$libresoc.v:133106$5099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:133282$5116
+ cell $and $and$libresoc.v:133107$5100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:133282$5116_Y
+ connect \Y $and$libresoc.v:133107$5100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:133283$5117
+ cell $and $and$libresoc.v:133108$5101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:133283$5117_Y
+ connect \Y $and$libresoc.v:133108$5101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:133284$5118
+ cell $and $and$libresoc.v:133109$5102
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B { \$110 \$112 \$114 \$116 }
- connect \Y $and$libresoc.v:133284$5118_Y
+ connect \Y $and$libresoc.v:133109$5102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:133285$5119
+ cell $and $and$libresoc.v:133110$5103
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$118
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:133285$5119_Y
+ connect \Y $and$libresoc.v:133110$5103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:133286$5120
+ cell $and $and$libresoc.v:133111$5104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133286$5120_Y
+ connect \Y $and$libresoc.v:133111$5104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:133287$5121
+ cell $and $and$libresoc.v:133112$5105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133287$5121_Y
+ connect \Y $and$libresoc.v:133112$5105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:133288$5122
+ cell $and $and$libresoc.v:133113$5106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133288$5122_Y
+ connect \Y $and$libresoc.v:133113$5106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:133289$5123
+ cell $and $and$libresoc.v:133114$5107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133289$5123_Y
+ connect \Y $and$libresoc.v:133114$5107_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:133291$5125
+ cell $and $and$libresoc.v:133116$5109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:133291$5125_Y
+ connect \Y $and$libresoc.v:133116$5109_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:133293$5127
+ cell $and $and$libresoc.v:133118$5111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:133293$5127_Y
+ connect \Y $and$libresoc.v:133118$5111_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:133294$5128
+ cell $and $and$libresoc.v:133119$5112
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:133294$5128_Y
+ connect \Y $and$libresoc.v:133119$5112_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:133296$5130
+ cell $and $and$libresoc.v:133121$5114
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:133296$5130_Y
+ connect \Y $and$libresoc.v:133121$5114_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:133299$5133
+ cell $and $and$libresoc.v:133124$5117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:133299$5133_Y
+ connect \Y $and$libresoc.v:133124$5117_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:133300$5134
+ cell $and $and$libresoc.v:133125$5118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:133300$5134_Y
+ connect \Y $and$libresoc.v:133125$5118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:133305$5139
+ cell $and $and$libresoc.v:133130$5123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:133305$5139_Y
+ connect \Y $and$libresoc.v:133130$5123_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:133306$5140
+ cell $and $and$libresoc.v:133131$5124
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:133306$5140_Y
+ connect \Y $and$libresoc.v:133131$5124_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:133308$5142
+ cell $and $and$libresoc.v:133133$5126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:133308$5142_Y
+ connect \Y $and$libresoc.v:133133$5126_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:133310$5144
+ cell $and $and$libresoc.v:133135$5128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_div0_n_ready_i
- connect \Y $and$libresoc.v:133310$5144_Y
+ connect \Y $and$libresoc.v:133135$5128_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:133311$5145
+ cell $and $and$libresoc.v:133136$5129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_div0_n_valid_o
- connect \Y $and$libresoc.v:133311$5145_Y
+ connect \Y $and$libresoc.v:133136$5129_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:133312$5146
+ cell $and $and$libresoc.v:133137$5130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133312$5146_Y
+ connect \Y $and$libresoc.v:133137$5130_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:133318$5152
+ cell $and $and$libresoc.v:133143$5136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133318$5152_Y
+ connect \Y $and$libresoc.v:133143$5136_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:133319$5153
+ cell $and $and$libresoc.v:133144$5137
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:133319$5153_Y
+ connect \Y $and$libresoc.v:133144$5137_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:133321$5155
+ cell $and $and$libresoc.v:133146$5139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133321$5155_Y
+ connect \Y $and$libresoc.v:133146$5139_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:133322$5156
+ cell $and $and$libresoc.v:133147$5140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133322$5156_Y
+ connect \Y $and$libresoc.v:133147$5140_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:133323$5157
+ cell $and $and$libresoc.v:133148$5141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133323$5157_Y
+ connect \Y $and$libresoc.v:133148$5141_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:133324$5158
+ cell $and $and$libresoc.v:133149$5142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:133324$5158_Y
+ connect \Y $and$libresoc.v:133149$5142_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:133334$5168
+ cell $and $and$libresoc.v:133159$5152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:133334$5168_Y
+ connect \Y $and$libresoc.v:133159$5152_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:133335$5169
+ cell $and $and$libresoc.v:133160$5153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:133335$5169_Y
+ connect \Y $and$libresoc.v:133160$5153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:133336$5170
+ cell $and $and$libresoc.v:133161$5154
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:133336$5170_Y
+ connect \Y $and$libresoc.v:133161$5154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:133307$5141
+ cell $eq $eq$libresoc.v:133132$5125
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:133307$5141_Y
+ connect \Y $eq$libresoc.v:133132$5125_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:133309$5143
+ cell $eq $eq$libresoc.v:133134$5127
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:133309$5143_Y
+ connect \Y $eq$libresoc.v:133134$5127_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:133274$5108
+ cell $not $not$libresoc.v:133099$5092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_logical_op__zero_a
- connect \Y $not$libresoc.v:133274$5108_Y
+ connect \Y $not$libresoc.v:133099$5092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:133275$5109
+ cell $not $not$libresoc.v:133100$5093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_logical_op__imm_data__ok
- connect \Y $not$libresoc.v:133275$5109_Y
+ connect \Y $not$libresoc.v:133100$5093_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:133277$5111
+ cell $not $not$libresoc.v:133102$5095
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:133277$5111_Y
+ connect \Y $not$libresoc.v:133102$5095_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:133290$5124
+ cell $not $not$libresoc.v:133115$5108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:133290$5124_Y
+ connect \Y $not$libresoc.v:133115$5108_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:133292$5126
+ cell $not $not$libresoc.v:133117$5110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:133292$5126_Y
+ connect \Y $not$libresoc.v:133117$5110_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:133295$5129
+ cell $not $not$libresoc.v:133120$5113
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:133295$5129_Y
+ connect \Y $not$libresoc.v:133120$5113_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:133298$5132
+ cell $not $not$libresoc.v:133123$5116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:133298$5132_Y
+ connect \Y $not$libresoc.v:133123$5116_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:133304$5138
+ cell $not $not$libresoc.v:133129$5122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_n_ready_i
- connect \Y $not$libresoc.v:133304$5138_Y
+ connect \Y $not$libresoc.v:133129$5122_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:133315$5149
+ cell $not $not$libresoc.v:133140$5133
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:133315$5149_Y
+ connect \Y $not$libresoc.v:133140$5133_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:133303$5137
+ cell $or $or$libresoc.v:133128$5121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:133303$5137_Y
+ connect \Y $or$libresoc.v:133128$5121_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:133313$5147
+ cell $or $or$libresoc.v:133138$5131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:133313$5147_Y
+ connect \Y $or$libresoc.v:133138$5131_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:133314$5148
+ cell $or $or$libresoc.v:133139$5132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:133314$5148_Y
+ connect \Y $or$libresoc.v:133139$5132_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:133316$5150
+ cell $or $or$libresoc.v:133141$5134
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:133316$5150_Y
+ connect \Y $or$libresoc.v:133141$5134_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:133317$5151
+ cell $or $or$libresoc.v:133142$5135
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:133317$5151_Y
+ connect \Y $or$libresoc.v:133142$5135_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:133320$5154
+ cell $or $or$libresoc.v:133145$5138
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:133320$5154_Y
+ connect \Y $or$libresoc.v:133145$5138_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:133326$5160
+ cell $or $or$libresoc.v:133151$5144
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:133326$5160_Y
+ connect \Y $or$libresoc.v:133151$5144_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:133331$5165
+ cell $reduce_and $reduce_and$libresoc.v:133156$5149
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:133331$5165_Y
+ connect \Y $reduce_and$libresoc.v:133156$5149_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:133297$5131
+ cell $reduce_or $reduce_or$libresoc.v:133122$5115
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:133297$5131_Y
+ connect \Y $reduce_or$libresoc.v:133122$5115_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:133301$5135
+ cell $reduce_or $reduce_or$libresoc.v:133126$5119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:133301$5135_Y
+ connect \Y $reduce_or$libresoc.v:133126$5119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:133302$5136
+ cell $reduce_or $reduce_or$libresoc.v:133127$5120
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:133302$5136_Y
+ connect \Y $reduce_or$libresoc.v:133127$5120_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:133325$5159
+ cell $mux $ternary$libresoc.v:133150$5143
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \alu_div0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:133325$5159_Y
+ connect \Y $ternary$libresoc.v:133150$5143_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:133327$5161
+ cell $mux $ternary$libresoc.v:133152$5145
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \alu_div0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:133327$5161_Y
+ connect \Y $ternary$libresoc.v:133152$5145_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:133328$5162
+ cell $mux $ternary$libresoc.v:133153$5146
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_div0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:133328$5162_Y
+ connect \Y $ternary$libresoc.v:133153$5146_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:133329$5163
+ cell $mux $ternary$libresoc.v:133154$5147
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_div0_logical_op__imm_data__data
connect \S \alu_div0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:133329$5163_Y
+ connect \Y $ternary$libresoc.v:133154$5147_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:133330$5164
+ cell $mux $ternary$libresoc.v:133155$5148
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:133330$5164_Y
+ connect \Y $ternary$libresoc.v:133155$5148_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:133332$5166
+ cell $mux $ternary$libresoc.v:133157$5150
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm$85
connect \S \src_sel$82
- connect \Y $ternary$libresoc.v:133332$5166_Y
+ connect \Y $ternary$libresoc.v:133157$5150_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:133333$5167
+ cell $mux $ternary$libresoc.v:133158$5151
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:133333$5167_Y
+ connect \Y $ternary$libresoc.v:133158$5151_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133425.12-133461.4"
+ attribute \src "libresoc.v:133250.12-133286.4"
cell \alu_div0 \alu_div0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133462.14-133468.4"
+ attribute \src "libresoc.v:133287.14-133293.4"
cell \alu_l$90 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133469.15-133475.4"
+ attribute \src "libresoc.v:133294.15-133300.4"
cell \alui_l$89 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133476.14-133482.4"
+ attribute \src "libresoc.v:133301.14-133307.4"
cell \opc_l$85 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133483.14-133489.4"
+ attribute \src "libresoc.v:133308.14-133314.4"
cell \req_l$86 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133490.14-133496.4"
+ attribute \src "libresoc.v:133315.14-133321.4"
cell \rok_l$88 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133497.14-133502.4"
+ attribute \src "libresoc.v:133322.14-133327.4"
cell \rst_l$87 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133503.14-133509.4"
+ attribute \src "libresoc.v:133328.14-133334.4"
cell \src_l$84 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:132623.7-132623.20"
- process $proc$libresoc.v:132623$5343
+ attribute \src "libresoc.v:132448.7-132448.20"
+ process $proc$libresoc.v:132448$5327
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:132753.7-132753.24"
- process $proc$libresoc.v:132753$5344
+ attribute \src "libresoc.v:132578.7-132578.24"
+ process $proc$libresoc.v:132578$5328
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:132763.13-132763.49"
- process $proc$libresoc.v:132763$5345
+ attribute \src "libresoc.v:132588.13-132588.49"
+ process $proc$libresoc.v:132588$5329
assign { } { }
assign $1\alu_div0_logical_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:132782.14-132782.53"
- process $proc$libresoc.v:132782$5346
+ attribute \src "libresoc.v:132607.14-132607.53"
+ process $proc$libresoc.v:132607$5330
assign { } { }
assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:132786.14-132786.72"
- process $proc$libresoc.v:132786$5347
+ attribute \src "libresoc.v:132611.14-132611.72"
+ process $proc$libresoc.v:132611$5331
assign { } { }
assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:132790.7-132790.47"
- process $proc$libresoc.v:132790$5348
+ attribute \src "libresoc.v:132615.7-132615.47"
+ process $proc$libresoc.v:132615$5332
assign { } { }
assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:132798.13-132798.52"
- process $proc$libresoc.v:132798$5349
+ attribute \src "libresoc.v:132623.13-132623.52"
+ process $proc$libresoc.v:132623$5333
assign { } { }
assign $1\alu_div0_logical_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:132802.14-132802.47"
- process $proc$libresoc.v:132802$5350
+ attribute \src "libresoc.v:132627.14-132627.47"
+ process $proc$libresoc.v:132627$5334
assign { } { }
assign $1\alu_div0_logical_op__insn[31:0] 0
sync always
sync init
update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:132881.13-132881.51"
- process $proc$libresoc.v:132881$5351
+ attribute \src "libresoc.v:132706.13-132706.51"
+ process $proc$libresoc.v:132706$5335
assign { } { }
assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:132885.7-132885.44"
- process $proc$libresoc.v:132885$5352
+ attribute \src "libresoc.v:132710.7-132710.44"
+ process $proc$libresoc.v:132710$5336
assign { } { }
assign $1\alu_div0_logical_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:132889.7-132889.45"
- process $proc$libresoc.v:132889$5353
+ attribute \src "libresoc.v:132714.7-132714.45"
+ process $proc$libresoc.v:132714$5337
assign { } { }
assign $1\alu_div0_logical_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:132893.7-132893.43"
- process $proc$libresoc.v:132893$5354
+ attribute \src "libresoc.v:132718.7-132718.43"
+ process $proc$libresoc.v:132718$5338
assign { } { }
assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:132897.7-132897.44"
- process $proc$libresoc.v:132897$5355
+ attribute \src "libresoc.v:132722.7-132722.44"
+ process $proc$libresoc.v:132722$5339
assign { } { }
assign $1\alu_div0_logical_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:132901.7-132901.41"
- process $proc$libresoc.v:132901$5356
+ attribute \src "libresoc.v:132726.7-132726.41"
+ process $proc$libresoc.v:132726$5340
assign { } { }
assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:132905.7-132905.41"
- process $proc$libresoc.v:132905$5357
+ attribute \src "libresoc.v:132730.7-132730.41"
+ process $proc$libresoc.v:132730$5341
assign { } { }
assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:132909.7-132909.47"
- process $proc$libresoc.v:132909$5358
+ attribute \src "libresoc.v:132734.7-132734.47"
+ process $proc$libresoc.v:132734$5342
assign { } { }
assign $1\alu_div0_logical_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:132913.7-132913.41"
- process $proc$libresoc.v:132913$5359
+ attribute \src "libresoc.v:132738.7-132738.41"
+ process $proc$libresoc.v:132738$5343
assign { } { }
assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:132917.7-132917.41"
- process $proc$libresoc.v:132917$5360
+ attribute \src "libresoc.v:132742.7-132742.41"
+ process $proc$libresoc.v:132742$5344
assign { } { }
assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:132921.7-132921.44"
- process $proc$libresoc.v:132921$5361
+ attribute \src "libresoc.v:132746.7-132746.44"
+ process $proc$libresoc.v:132746$5345
assign { } { }
assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:132925.7-132925.41"
- process $proc$libresoc.v:132925$5362
+ attribute \src "libresoc.v:132750.7-132750.41"
+ process $proc$libresoc.v:132750$5346
assign { } { }
assign $1\alu_div0_logical_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:132951.7-132951.26"
- process $proc$libresoc.v:132951$5363
+ attribute \src "libresoc.v:132776.7-132776.26"
+ process $proc$libresoc.v:132776$5347
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:132959.7-132959.25"
- process $proc$libresoc.v:132959$5364
+ attribute \src "libresoc.v:132784.7-132784.25"
+ process $proc$libresoc.v:132784$5348
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:132971.7-132971.27"
- process $proc$libresoc.v:132971$5365
+ attribute \src "libresoc.v:132796.7-132796.27"
+ process $proc$libresoc.v:132796$5349
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:133005.14-133005.47"
- process $proc$libresoc.v:133005$5366
+ attribute \src "libresoc.v:132830.14-132830.47"
+ process $proc$libresoc.v:132830$5350
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:133009.7-133009.27"
- process $proc$libresoc.v:133009$5367
+ attribute \src "libresoc.v:132834.7-132834.27"
+ process $proc$libresoc.v:132834$5351
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:133013.13-133013.33"
- process $proc$libresoc.v:133013$5368
+ attribute \src "libresoc.v:132838.13-132838.33"
+ process $proc$libresoc.v:132838$5352
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:133017.7-133017.30"
- process $proc$libresoc.v:133017$5369
+ attribute \src "libresoc.v:132842.7-132842.30"
+ process $proc$libresoc.v:132842$5353
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:133021.13-133021.35"
- process $proc$libresoc.v:133021$5370
+ attribute \src "libresoc.v:132846.13-132846.35"
+ process $proc$libresoc.v:132846$5354
assign { } { }
assign $1\data_r2__xer_ov[1:0] 2'00
sync always
sync init
update \data_r2__xer_ov $1\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:133025.7-133025.32"
- process $proc$libresoc.v:133025$5371
+ attribute \src "libresoc.v:132850.7-132850.32"
+ process $proc$libresoc.v:132850$5355
assign { } { }
assign $1\data_r2__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:133029.7-133029.29"
- process $proc$libresoc.v:133029$5372
+ attribute \src "libresoc.v:132854.7-132854.29"
+ process $proc$libresoc.v:132854$5356
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:133033.7-133033.32"
- process $proc$libresoc.v:133033$5373
+ attribute \src "libresoc.v:132858.7-132858.32"
+ process $proc$libresoc.v:132858$5357
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:133053.7-133053.25"
- process $proc$libresoc.v:133053$5374
+ attribute \src "libresoc.v:132878.7-132878.25"
+ process $proc$libresoc.v:132878$5358
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:133057.7-133057.25"
- process $proc$libresoc.v:133057$5375
+ attribute \src "libresoc.v:132882.7-132882.25"
+ process $proc$libresoc.v:132882$5359
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:133191.13-133191.30"
- process $proc$libresoc.v:133191$5376
+ attribute \src "libresoc.v:133016.13-133016.30"
+ process $proc$libresoc.v:133016$5360
assign { } { }
assign $1\prev_wr_go[3:0] 4'0000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:133199.13-133199.31"
- process $proc$libresoc.v:133199$5377
+ attribute \src "libresoc.v:133024.13-133024.31"
+ process $proc$libresoc.v:133024$5361
assign { } { }
assign $1\req_l_r_req[3:0] 4'1111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:133203.13-133203.31"
- process $proc$libresoc.v:133203$5378
+ attribute \src "libresoc.v:133028.13-133028.31"
+ process $proc$libresoc.v:133028$5362
assign { } { }
assign $1\req_l_s_req[3:0] 4'0000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:133215.7-133215.26"
- process $proc$libresoc.v:133215$5379
+ attribute \src "libresoc.v:133040.7-133040.26"
+ process $proc$libresoc.v:133040$5363
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:133219.7-133219.26"
- process $proc$libresoc.v:133219$5380
+ attribute \src "libresoc.v:133044.7-133044.26"
+ process $proc$libresoc.v:133044$5364
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:133223.7-133223.25"
- process $proc$libresoc.v:133223$5381
+ attribute \src "libresoc.v:133048.7-133048.25"
+ process $proc$libresoc.v:133048$5365
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:133227.7-133227.25"
- process $proc$libresoc.v:133227$5382
+ attribute \src "libresoc.v:133052.7-133052.25"
+ process $proc$libresoc.v:133052$5366
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:133241.13-133241.31"
- process $proc$libresoc.v:133241$5383
+ attribute \src "libresoc.v:133066.13-133066.31"
+ process $proc$libresoc.v:133066$5367
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:133245.13-133245.31"
- process $proc$libresoc.v:133245$5384
+ attribute \src "libresoc.v:133070.13-133070.31"
+ process $proc$libresoc.v:133070$5368
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:133253.14-133253.43"
- process $proc$libresoc.v:133253$5385
+ attribute \src "libresoc.v:133078.14-133078.43"
+ process $proc$libresoc.v:133078$5369
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:133257.14-133257.43"
- process $proc$libresoc.v:133257$5386
+ attribute \src "libresoc.v:133082.14-133082.43"
+ process $proc$libresoc.v:133082$5370
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:133261.7-133261.20"
- process $proc$libresoc.v:133261$5387
+ attribute \src "libresoc.v:133086.7-133086.20"
+ process $proc$libresoc.v:133086$5371
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:133337.3-133338.39"
- process $proc$libresoc.v:133337$5171
+ attribute \src "libresoc.v:133162.3-133163.39"
+ process $proc$libresoc.v:133162$5155
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:133339.3-133340.43"
- process $proc$libresoc.v:133339$5172
+ attribute \src "libresoc.v:133164.3-133165.43"
+ process $proc$libresoc.v:133164$5156
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:133341.3-133342.29"
- process $proc$libresoc.v:133341$5173
+ attribute \src "libresoc.v:133166.3-133167.29"
+ process $proc$libresoc.v:133166$5157
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:133343.3-133344.29"
- process $proc$libresoc.v:133343$5174
+ attribute \src "libresoc.v:133168.3-133169.29"
+ process $proc$libresoc.v:133168$5158
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:133345.3-133346.29"
- process $proc$libresoc.v:133345$5175
+ attribute \src "libresoc.v:133170.3-133171.29"
+ process $proc$libresoc.v:133170$5159
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:133347.3-133348.47"
- process $proc$libresoc.v:133347$5176
+ attribute \src "libresoc.v:133172.3-133173.47"
+ process $proc$libresoc.v:133172$5160
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:133349.3-133350.53"
- process $proc$libresoc.v:133349$5177
+ attribute \src "libresoc.v:133174.3-133175.53"
+ process $proc$libresoc.v:133174$5161
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:133351.3-133352.47"
- process $proc$libresoc.v:133351$5178
+ attribute \src "libresoc.v:133176.3-133177.47"
+ process $proc$libresoc.v:133176$5162
assign { } { }
assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next
sync posedge \coresync_clk
update \data_r2__xer_ov $0\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:133353.3-133354.53"
- process $proc$libresoc.v:133353$5179
+ attribute \src "libresoc.v:133178.3-133179.53"
+ process $proc$libresoc.v:133178$5163
assign { } { }
assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:133355.3-133356.43"
- process $proc$libresoc.v:133355$5180
+ attribute \src "libresoc.v:133180.3-133181.43"
+ process $proc$libresoc.v:133180$5164
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:133357.3-133358.49"
- process $proc$libresoc.v:133357$5181
+ attribute \src "libresoc.v:133182.3-133183.49"
+ process $proc$libresoc.v:133182$5165
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:133359.3-133360.37"
- process $proc$libresoc.v:133359$5182
+ attribute \src "libresoc.v:133184.3-133185.37"
+ process $proc$libresoc.v:133184$5166
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:133361.3-133362.43"
- process $proc$libresoc.v:133361$5183
+ attribute \src "libresoc.v:133186.3-133187.43"
+ process $proc$libresoc.v:133186$5167
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:133363.3-133364.77"
- process $proc$libresoc.v:133363$5184
+ attribute \src "libresoc.v:133188.3-133189.77"
+ process $proc$libresoc.v:133188$5168
assign { } { }
assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next
sync posedge \coresync_clk
update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:133365.3-133366.73"
- process $proc$libresoc.v:133365$5185
+ attribute \src "libresoc.v:133190.3-133191.73"
+ process $proc$libresoc.v:133190$5169
assign { } { }
assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next
sync posedge \coresync_clk
update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:133367.3-133368.87"
- process $proc$libresoc.v:133367$5186
+ attribute \src "libresoc.v:133192.3-133193.87"
+ process $proc$libresoc.v:133192$5170
assign { } { }
assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:133369.3-133370.83"
- process $proc$libresoc.v:133369$5187
+ attribute \src "libresoc.v:133194.3-133195.83"
+ process $proc$libresoc.v:133194$5171
assign { } { }
assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:133371.3-133372.71"
- process $proc$libresoc.v:133371$5188
+ attribute \src "libresoc.v:133196.3-133197.71"
+ process $proc$libresoc.v:133196$5172
assign { } { }
assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next
sync posedge \coresync_clk
update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:133373.3-133374.71"
- process $proc$libresoc.v:133373$5189
+ attribute \src "libresoc.v:133198.3-133199.71"
+ process $proc$libresoc.v:133198$5173
assign { } { }
assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:133375.3-133376.71"
- process $proc$libresoc.v:133375$5190
+ attribute \src "libresoc.v:133200.3-133201.71"
+ process $proc$libresoc.v:133200$5174
assign { } { }
assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next
sync posedge \coresync_clk
update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:133377.3-133378.71"
- process $proc$libresoc.v:133377$5191
+ attribute \src "libresoc.v:133202.3-133203.71"
+ process $proc$libresoc.v:133202$5175
assign { } { }
assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:133379.3-133380.77"
- process $proc$libresoc.v:133379$5192
+ attribute \src "libresoc.v:133204.3-133205.77"
+ process $proc$libresoc.v:133204$5176
assign { } { }
assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next
sync posedge \coresync_clk
update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:133381.3-133382.71"
- process $proc$libresoc.v:133381$5193
+ attribute \src "libresoc.v:133206.3-133207.71"
+ process $proc$libresoc.v:133206$5177
assign { } { }
assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next
sync posedge \coresync_clk
update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:133383.3-133384.81"
- process $proc$libresoc.v:133383$5194
+ attribute \src "libresoc.v:133208.3-133209.81"
+ process $proc$libresoc.v:133208$5178
assign { } { }
assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next
sync posedge \coresync_clk
update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:133385.3-133386.79"
- process $proc$libresoc.v:133385$5195
+ attribute \src "libresoc.v:133210.3-133211.79"
+ process $proc$libresoc.v:133210$5179
assign { } { }
assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next
sync posedge \coresync_clk
update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:133387.3-133388.77"
- process $proc$libresoc.v:133387$5196
+ attribute \src "libresoc.v:133212.3-133213.77"
+ process $proc$libresoc.v:133212$5180
assign { } { }
assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next
sync posedge \coresync_clk
update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:133389.3-133390.83"
- process $proc$libresoc.v:133389$5197
+ attribute \src "libresoc.v:133214.3-133215.83"
+ process $proc$libresoc.v:133214$5181
assign { } { }
assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next
sync posedge \coresync_clk
update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:133391.3-133392.75"
- process $proc$libresoc.v:133391$5198
+ attribute \src "libresoc.v:133216.3-133217.75"
+ process $proc$libresoc.v:133216$5182
assign { } { }
assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next
sync posedge \coresync_clk
update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:133393.3-133394.77"
- process $proc$libresoc.v:133393$5199
+ attribute \src "libresoc.v:133218.3-133219.77"
+ process $proc$libresoc.v:133218$5183
assign { } { }
assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next
sync posedge \coresync_clk
update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:133395.3-133396.75"
- process $proc$libresoc.v:133395$5200
+ attribute \src "libresoc.v:133220.3-133221.75"
+ process $proc$libresoc.v:133220$5184
assign { } { }
assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next
sync posedge \coresync_clk
update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:133397.3-133398.67"
- process $proc$libresoc.v:133397$5201
+ attribute \src "libresoc.v:133222.3-133223.67"
+ process $proc$libresoc.v:133222$5185
assign { } { }
assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next
sync posedge \coresync_clk
update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:133399.3-133400.39"
- process $proc$libresoc.v:133399$5202
+ attribute \src "libresoc.v:133224.3-133225.39"
+ process $proc$libresoc.v:133224$5186
assign { } { }
assign $0\req_l_r_req[3:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:133401.3-133402.39"
- process $proc$libresoc.v:133401$5203
+ attribute \src "libresoc.v:133226.3-133227.39"
+ process $proc$libresoc.v:133226$5187
assign { } { }
assign $0\req_l_s_req[3:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:133403.3-133404.39"
- process $proc$libresoc.v:133403$5204
+ attribute \src "libresoc.v:133228.3-133229.39"
+ process $proc$libresoc.v:133228$5188
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:133405.3-133406.39"
- process $proc$libresoc.v:133405$5205
+ attribute \src "libresoc.v:133230.3-133231.39"
+ process $proc$libresoc.v:133230$5189
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:133407.3-133408.39"
- process $proc$libresoc.v:133407$5206
+ attribute \src "libresoc.v:133232.3-133233.39"
+ process $proc$libresoc.v:133232$5190
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:133409.3-133410.39"
- process $proc$libresoc.v:133409$5207
+ attribute \src "libresoc.v:133234.3-133235.39"
+ process $proc$libresoc.v:133234$5191
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:133411.3-133412.39"
- process $proc$libresoc.v:133411$5208
+ attribute \src "libresoc.v:133236.3-133237.39"
+ process $proc$libresoc.v:133236$5192
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:133413.3-133414.39"
- process $proc$libresoc.v:133413$5209
+ attribute \src "libresoc.v:133238.3-133239.39"
+ process $proc$libresoc.v:133238$5193
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:133415.3-133416.41"
- process $proc$libresoc.v:133415$5210
+ attribute \src "libresoc.v:133240.3-133241.41"
+ process $proc$libresoc.v:133240$5194
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:133417.3-133418.41"
- process $proc$libresoc.v:133417$5211
+ attribute \src "libresoc.v:133242.3-133243.41"
+ process $proc$libresoc.v:133242$5195
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:133419.3-133420.37"
- process $proc$libresoc.v:133419$5212
+ attribute \src "libresoc.v:133244.3-133245.37"
+ process $proc$libresoc.v:133244$5196
assign { } { }
assign $0\prev_wr_go[3:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:133421.3-133422.40"
- process $proc$libresoc.v:133421$5213
+ attribute \src "libresoc.v:133246.3-133247.40"
+ process $proc$libresoc.v:133246$5197
assign { } { }
assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:133423.3-133424.25"
- process $proc$libresoc.v:133423$5214
+ attribute \src "libresoc.v:133248.3-133249.25"
+ process $proc$libresoc.v:133248$5198
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:133510.3-133519.6"
- process $proc$libresoc.v:133510$5215
+ attribute \src "libresoc.v:133335.3-133344.6"
+ process $proc$libresoc.v:133335$5199
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:133511.5-133511.29"
+ attribute \src "libresoc.v:133336.5-133336.29"
switch \initial
- attribute \src "libresoc.v:133511.9-133511.17"
+ attribute \src "libresoc.v:133336.9-133336.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:133520.3-133528.6"
- process $proc$libresoc.v:133520$5216
+ attribute \src "libresoc.v:133345.3-133353.6"
+ process $proc$libresoc.v:133345$5200
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218
- attribute \src "libresoc.v:133521.5-133521.29"
+ assign $0\rok_l_s_rdok$next[0:0]$5201 $1\rok_l_s_rdok$next[0:0]$5202
+ attribute \src "libresoc.v:133346.5-133346.29"
switch \initial
- attribute \src "libresoc.v:133521.9-133521.17"
+ attribute \src "libresoc.v:133346.9-133346.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$5218 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$5202 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$5218 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$5202 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5201
end
- attribute \src "libresoc.v:133529.3-133537.6"
- process $proc$libresoc.v:133529$5219
+ attribute \src "libresoc.v:133354.3-133362.6"
+ process $proc$libresoc.v:133354$5203
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221
- attribute \src "libresoc.v:133530.5-133530.29"
+ assign $0\rok_l_r_rdok$next[0:0]$5204 $1\rok_l_r_rdok$next[0:0]$5205
+ attribute \src "libresoc.v:133355.5-133355.29"
switch \initial
- attribute \src "libresoc.v:133530.9-133530.17"
+ attribute \src "libresoc.v:133355.9-133355.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$5221 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$5205 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$5221 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$5205 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5204
end
- attribute \src "libresoc.v:133538.3-133546.6"
- process $proc$libresoc.v:133538$5222
+ attribute \src "libresoc.v:133363.3-133371.6"
+ process $proc$libresoc.v:133363$5206
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224
- attribute \src "libresoc.v:133539.5-133539.29"
+ assign $0\rst_l_s_rst$next[0:0]$5207 $1\rst_l_s_rst$next[0:0]$5208
+ attribute \src "libresoc.v:133364.5-133364.29"
switch \initial
- attribute \src "libresoc.v:133539.9-133539.17"
+ attribute \src "libresoc.v:133364.9-133364.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$5224 1'0
+ assign $1\rst_l_s_rst$next[0:0]$5208 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$5224 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$5208 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5207
end
- attribute \src "libresoc.v:133547.3-133555.6"
- process $proc$libresoc.v:133547$5225
+ attribute \src "libresoc.v:133372.3-133380.6"
+ process $proc$libresoc.v:133372$5209
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227
- attribute \src "libresoc.v:133548.5-133548.29"
+ assign $0\rst_l_r_rst$next[0:0]$5210 $1\rst_l_r_rst$next[0:0]$5211
+ attribute \src "libresoc.v:133373.5-133373.29"
switch \initial
- attribute \src "libresoc.v:133548.9-133548.17"
+ attribute \src "libresoc.v:133373.9-133373.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$5227 1'1
+ assign $1\rst_l_r_rst$next[0:0]$5211 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$5227 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$5211 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5210
end
- attribute \src "libresoc.v:133556.3-133564.6"
- process $proc$libresoc.v:133556$5228
+ attribute \src "libresoc.v:133381.3-133389.6"
+ process $proc$libresoc.v:133381$5212
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230
- attribute \src "libresoc.v:133557.5-133557.29"
+ assign $0\opc_l_s_opc$next[0:0]$5213 $1\opc_l_s_opc$next[0:0]$5214
+ attribute \src "libresoc.v:133382.5-133382.29"
switch \initial
- attribute \src "libresoc.v:133557.9-133557.17"
+ attribute \src "libresoc.v:133382.9-133382.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$5230 1'0
+ assign $1\opc_l_s_opc$next[0:0]$5214 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$5230 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$5214 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5213
end
- attribute \src "libresoc.v:133565.3-133573.6"
- process $proc$libresoc.v:133565$5231
+ attribute \src "libresoc.v:133390.3-133398.6"
+ process $proc$libresoc.v:133390$5215
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233
- attribute \src "libresoc.v:133566.5-133566.29"
+ assign $0\opc_l_r_opc$next[0:0]$5216 $1\opc_l_r_opc$next[0:0]$5217
+ attribute \src "libresoc.v:133391.5-133391.29"
switch \initial
- attribute \src "libresoc.v:133566.9-133566.17"
+ attribute \src "libresoc.v:133391.9-133391.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$5233 1'1
+ assign $1\opc_l_r_opc$next[0:0]$5217 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$5233 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$5217 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5216
end
- attribute \src "libresoc.v:133574.3-133582.6"
- process $proc$libresoc.v:133574$5234
+ attribute \src "libresoc.v:133399.3-133407.6"
+ process $proc$libresoc.v:133399$5218
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236
- attribute \src "libresoc.v:133575.5-133575.29"
+ assign $0\src_l_s_src$next[2:0]$5219 $1\src_l_s_src$next[2:0]$5220
+ attribute \src "libresoc.v:133400.5-133400.29"
switch \initial
- attribute \src "libresoc.v:133575.9-133575.17"
+ attribute \src "libresoc.v:133400.9-133400.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$5236 3'000
+ assign $1\src_l_s_src$next[2:0]$5220 3'000
case
- assign $1\src_l_s_src$next[2:0]$5236 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$5220 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5219
end
- attribute \src "libresoc.v:133583.3-133591.6"
- process $proc$libresoc.v:133583$5237
+ attribute \src "libresoc.v:133408.3-133416.6"
+ process $proc$libresoc.v:133408$5221
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239
- attribute \src "libresoc.v:133584.5-133584.29"
+ assign $0\src_l_r_src$next[2:0]$5222 $1\src_l_r_src$next[2:0]$5223
+ attribute \src "libresoc.v:133409.5-133409.29"
switch \initial
- attribute \src "libresoc.v:133584.9-133584.17"
+ attribute \src "libresoc.v:133409.9-133409.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$5239 3'111
+ assign $1\src_l_r_src$next[2:0]$5223 3'111
case
- assign $1\src_l_r_src$next[2:0]$5239 \reset_r
+ assign $1\src_l_r_src$next[2:0]$5223 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5222
end
- attribute \src "libresoc.v:133592.3-133600.6"
- process $proc$libresoc.v:133592$5240
+ attribute \src "libresoc.v:133417.3-133425.6"
+ process $proc$libresoc.v:133417$5224
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242
- attribute \src "libresoc.v:133593.5-133593.29"
+ assign $0\req_l_s_req$next[3:0]$5225 $1\req_l_s_req$next[3:0]$5226
+ attribute \src "libresoc.v:133418.5-133418.29"
switch \initial
- attribute \src "libresoc.v:133593.9-133593.17"
+ attribute \src "libresoc.v:133418.9-133418.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[3:0]$5242 4'0000
+ assign $1\req_l_s_req$next[3:0]$5226 4'0000
case
- assign $1\req_l_s_req$next[3:0]$5242 \$66
+ assign $1\req_l_s_req$next[3:0]$5226 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241
+ update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5225
end
- attribute \src "libresoc.v:133601.3-133609.6"
- process $proc$libresoc.v:133601$5243
+ attribute \src "libresoc.v:133426.3-133434.6"
+ process $proc$libresoc.v:133426$5227
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245
- attribute \src "libresoc.v:133602.5-133602.29"
+ assign $0\req_l_r_req$next[3:0]$5228 $1\req_l_r_req$next[3:0]$5229
+ attribute \src "libresoc.v:133427.5-133427.29"
switch \initial
- attribute \src "libresoc.v:133602.9-133602.17"
+ attribute \src "libresoc.v:133427.9-133427.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[3:0]$5245 4'1111
+ assign $1\req_l_r_req$next[3:0]$5229 4'1111
case
- assign $1\req_l_r_req$next[3:0]$5245 \$68
+ assign $1\req_l_r_req$next[3:0]$5229 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244
+ update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5228
end
- attribute \src "libresoc.v:133610.3-133648.6"
- process $proc$libresoc.v:133610$5246
+ attribute \src "libresoc.v:133435.3-133473.6"
+ process $proc$libresoc.v:133435$5230
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__data_len$next[3:0]$5247 $1\alu_div0_logical_op__data_len$next[3:0]$5265
- assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266
+ assign $0\alu_div0_logical_op__data_len$next[3:0]$5231 $1\alu_div0_logical_op__data_len$next[3:0]$5249
+ assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__input_carry$next[1:0]$5251 $1\alu_div0_logical_op__input_carry$next[1:0]$5269
- assign $0\alu_div0_logical_op__insn$next[31:0]$5252 $1\alu_div0_logical_op__insn$next[31:0]$5270
- assign $0\alu_div0_logical_op__insn_type$next[6:0]$5253 $1\alu_div0_logical_op__insn_type$next[6:0]$5271
- assign $0\alu_div0_logical_op__invert_in$next[0:0]$5254 $1\alu_div0_logical_op__invert_in$next[0:0]$5272
- assign $0\alu_div0_logical_op__invert_out$next[0:0]$5255 $1\alu_div0_logical_op__invert_out$next[0:0]$5273
- assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274
- assign $0\alu_div0_logical_op__is_signed$next[0:0]$5257 $1\alu_div0_logical_op__is_signed$next[0:0]$5275
+ assign $0\alu_div0_logical_op__input_carry$next[1:0]$5235 $1\alu_div0_logical_op__input_carry$next[1:0]$5253
+ assign $0\alu_div0_logical_op__insn$next[31:0]$5236 $1\alu_div0_logical_op__insn$next[31:0]$5254
+ assign $0\alu_div0_logical_op__insn_type$next[6:0]$5237 $1\alu_div0_logical_op__insn_type$next[6:0]$5255
+ assign $0\alu_div0_logical_op__invert_in$next[0:0]$5238 $1\alu_div0_logical_op__invert_in$next[0:0]$5256
+ assign $0\alu_div0_logical_op__invert_out$next[0:0]$5239 $1\alu_div0_logical_op__invert_out$next[0:0]$5257
+ assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258
+ assign $0\alu_div0_logical_op__is_signed$next[0:0]$5241 $1\alu_div0_logical_op__is_signed$next[0:0]$5259
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__output_carry$next[0:0]$5260 $1\alu_div0_logical_op__output_carry$next[0:0]$5278
+ assign $0\alu_div0_logical_op__output_carry$next[0:0]$5244 $1\alu_div0_logical_op__output_carry$next[0:0]$5262
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281
- assign $0\alu_div0_logical_op__zero_a$next[0:0]$5264 $1\alu_div0_logical_op__zero_a$next[0:0]$5282
- assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283
- assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284
- assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 $2\alu_div0_logical_op__oe__oe$next[0:0]$5285
- assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286
- assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287
- assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288
- attribute \src "libresoc.v:133611.5-133611.29"
+ assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265
+ assign $0\alu_div0_logical_op__zero_a$next[0:0]$5248 $1\alu_div0_logical_op__zero_a$next[0:0]$5266
+ assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267
+ assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268
+ assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 $2\alu_div0_logical_op__oe__oe$next[0:0]$5269
+ assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 $2\alu_div0_logical_op__oe__ok$next[0:0]$5270
+ assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 $2\alu_div0_logical_op__rc__ok$next[0:0]$5271
+ assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 $2\alu_div0_logical_op__rc__rc$next[0:0]$5272
+ attribute \src "libresoc.v:133436.5-133436.29"
switch \initial
- attribute \src "libresoc.v:133611.9-133611.17"
+ attribute \src "libresoc.v:133436.9-133436.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_div0_logical_op__insn$next[31:0]$5270 $1\alu_div0_logical_op__data_len$next[3:0]$5265 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
+ assign { $1\alu_div0_logical_op__insn$next[31:0]$5254 $1\alu_div0_logical_op__data_len$next[3:0]$5249 $1\alu_div0_logical_op__is_signed$next[0:0]$5259 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 $1\alu_div0_logical_op__output_carry$next[0:0]$5262 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 $1\alu_div0_logical_op__invert_out$next[0:0]$5257 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 $1\alu_div0_logical_op__zero_a$next[0:0]$5266 $1\alu_div0_logical_op__invert_in$next[0:0]$5256 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
case
- assign $1\alu_div0_logical_op__data_len$next[3:0]$5265 \alu_div0_logical_op__data_len
- assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 \alu_div0_logical_op__fn_unit
- assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 \alu_div0_logical_op__imm_data__data
- assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 \alu_div0_logical_op__imm_data__ok
- assign $1\alu_div0_logical_op__input_carry$next[1:0]$5269 \alu_div0_logical_op__input_carry
- assign $1\alu_div0_logical_op__insn$next[31:0]$5270 \alu_div0_logical_op__insn
- assign $1\alu_div0_logical_op__insn_type$next[6:0]$5271 \alu_div0_logical_op__insn_type
- assign $1\alu_div0_logical_op__invert_in$next[0:0]$5272 \alu_div0_logical_op__invert_in
- assign $1\alu_div0_logical_op__invert_out$next[0:0]$5273 \alu_div0_logical_op__invert_out
- assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 \alu_div0_logical_op__is_32bit
- assign $1\alu_div0_logical_op__is_signed$next[0:0]$5275 \alu_div0_logical_op__is_signed
- assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 \alu_div0_logical_op__oe__oe
- assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 \alu_div0_logical_op__oe__ok
- assign $1\alu_div0_logical_op__output_carry$next[0:0]$5278 \alu_div0_logical_op__output_carry
- assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 \alu_div0_logical_op__rc__ok
- assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 \alu_div0_logical_op__rc__rc
- assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 \alu_div0_logical_op__write_cr0
- assign $1\alu_div0_logical_op__zero_a$next[0:0]$5282 \alu_div0_logical_op__zero_a
+ assign $1\alu_div0_logical_op__data_len$next[3:0]$5249 \alu_div0_logical_op__data_len
+ assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 \alu_div0_logical_op__fn_unit
+ assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 \alu_div0_logical_op__imm_data__data
+ assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 \alu_div0_logical_op__imm_data__ok
+ assign $1\alu_div0_logical_op__input_carry$next[1:0]$5253 \alu_div0_logical_op__input_carry
+ assign $1\alu_div0_logical_op__insn$next[31:0]$5254 \alu_div0_logical_op__insn
+ assign $1\alu_div0_logical_op__insn_type$next[6:0]$5255 \alu_div0_logical_op__insn_type
+ assign $1\alu_div0_logical_op__invert_in$next[0:0]$5256 \alu_div0_logical_op__invert_in
+ assign $1\alu_div0_logical_op__invert_out$next[0:0]$5257 \alu_div0_logical_op__invert_out
+ assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 \alu_div0_logical_op__is_32bit
+ assign $1\alu_div0_logical_op__is_signed$next[0:0]$5259 \alu_div0_logical_op__is_signed
+ assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 \alu_div0_logical_op__oe__oe
+ assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 \alu_div0_logical_op__oe__ok
+ assign $1\alu_div0_logical_op__output_carry$next[0:0]$5262 \alu_div0_logical_op__output_carry
+ assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 \alu_div0_logical_op__rc__ok
+ assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 \alu_div0_logical_op__rc__rc
+ assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 \alu_div0_logical_op__write_cr0
+ assign $1\alu_div0_logical_op__zero_a$next[0:0]$5266 \alu_div0_logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 1'0
- assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 1'0
- assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 1'0
- assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 1'0
- assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 1'0
+ assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 1'0
+ assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 1'0
+ assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 1'0
+ assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 1'0
+ assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 1'0
case
- assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267
- assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268
- assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276
- assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277
- assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279
- assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280
+ assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251
+ assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252
+ assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260
+ assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261
+ assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263
+ assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264
end
sync always
- update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5247
- update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5248
- update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249
- update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250
- update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5251
- update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5252
- update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5253
- update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5254
- update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5255
- update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5256
- update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5257
- update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5258
- update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5259
- update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5260
- update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5261
- update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5262
- update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263
- update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264
+ update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5231
+ update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5232
+ update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233
+ update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234
+ update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5235
+ update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5236
+ update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5237
+ update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5238
+ update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5239
+ update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5240
+ update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5241
+ update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5242
+ update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5243
+ update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5244
+ update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5245
+ update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5246
+ update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5247
+ update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5248
end
- attribute \src "libresoc.v:133649.3-133670.6"
- process $proc$libresoc.v:133649$5289
+ attribute \src "libresoc.v:133474.3-133495.6"
+ process $proc$libresoc.v:133474$5273
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294
+ assign $0\data_r0__o$next[63:0]$5274 $2\data_r0__o$next[63:0]$5278
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296
- attribute \src "libresoc.v:133650.5-133650.29"
+ assign $0\data_r0__o_ok$next[0:0]$5275 $3\data_r0__o_ok$next[0:0]$5280
+ attribute \src "libresoc.v:133475.5-133475.29"
switch \initial
- attribute \src "libresoc.v:133650.9-133650.17"
+ attribute \src "libresoc.v:133475.9-133475.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$5293 $1\data_r0__o$next[63:0]$5292 } { \o_ok \alu_div0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$5277 $1\data_r0__o$next[63:0]$5276 } { \o_ok \alu_div0_o }
case
- assign $1\data_r0__o$next[63:0]$5292 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$5293 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$5276 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$5277 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o$next[63:0]$5294 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$5279 $2\data_r0__o$next[63:0]$5278 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$5294 $1\data_r0__o$next[63:0]$5292
- assign $2\data_r0__o_ok$next[0:0]$5295 $1\data_r0__o_ok$next[0:0]$5293
+ assign $2\data_r0__o$next[63:0]$5278 $1\data_r0__o$next[63:0]$5276
+ assign $2\data_r0__o_ok$next[0:0]$5279 $1\data_r0__o_ok$next[0:0]$5277
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$5296 1'0
+ assign $3\data_r0__o_ok$next[0:0]$5280 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$5296 $2\data_r0__o_ok$next[0:0]$5295
+ assign $3\data_r0__o_ok$next[0:0]$5280 $2\data_r0__o_ok$next[0:0]$5279
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$5290
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$5274
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5275
end
- attribute \src "libresoc.v:133671.3-133692.6"
- process $proc$libresoc.v:133671$5297
+ attribute \src "libresoc.v:133496.3-133517.6"
+ process $proc$libresoc.v:133496$5281
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302
+ assign $0\data_r1__cr_a$next[3:0]$5282 $2\data_r1__cr_a$next[3:0]$5286
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304
- attribute \src "libresoc.v:133672.5-133672.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$5283 $3\data_r1__cr_a_ok$next[0:0]$5288
+ attribute \src "libresoc.v:133497.5-133497.29"
switch \initial
- attribute \src "libresoc.v:133672.9-133672.17"
+ attribute \src "libresoc.v:133497.9-133497.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$5301 $1\data_r1__cr_a$next[3:0]$5300 } { \cr_a_ok \alu_div0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$5285 $1\data_r1__cr_a$next[3:0]$5284 } { \cr_a_ok \alu_div0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$5300 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$5301 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$5284 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$5285 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a$next[3:0]$5302 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$5287 $2\data_r1__cr_a$next[3:0]$5286 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$5302 $1\data_r1__cr_a$next[3:0]$5300
- assign $2\data_r1__cr_a_ok$next[0:0]$5303 $1\data_r1__cr_a_ok$next[0:0]$5301
+ assign $2\data_r1__cr_a$next[3:0]$5286 $1\data_r1__cr_a$next[3:0]$5284
+ assign $2\data_r1__cr_a_ok$next[0:0]$5287 $1\data_r1__cr_a_ok$next[0:0]$5285
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$5304 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$5288 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$5304 $2\data_r1__cr_a_ok$next[0:0]$5303
+ assign $3\data_r1__cr_a_ok$next[0:0]$5288 $2\data_r1__cr_a_ok$next[0:0]$5287
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5282
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5283
end
- attribute \src "libresoc.v:133693.3-133714.6"
- process $proc$libresoc.v:133693$5305
+ attribute \src "libresoc.v:133518.3-133539.6"
+ process $proc$libresoc.v:133518$5289
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310
+ assign $0\data_r2__xer_ov$next[1:0]$5290 $2\data_r2__xer_ov$next[1:0]$5294
assign { } { }
- assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312
- attribute \src "libresoc.v:133694.5-133694.29"
+ assign $0\data_r2__xer_ov_ok$next[0:0]$5291 $3\data_r2__xer_ov_ok$next[0:0]$5296
+ attribute \src "libresoc.v:133519.5-133519.29"
switch \initial
- attribute \src "libresoc.v:133694.9-133694.17"
+ attribute \src "libresoc.v:133519.9-133519.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ov_ok$next[0:0]$5309 $1\data_r2__xer_ov$next[1:0]$5308 } { \xer_ov_ok \alu_div0_xer_ov }
+ assign { $1\data_r2__xer_ov_ok$next[0:0]$5293 $1\data_r2__xer_ov$next[1:0]$5292 } { \xer_ov_ok \alu_div0_xer_ov }
case
- assign $1\data_r2__xer_ov$next[1:0]$5308 \data_r2__xer_ov
- assign $1\data_r2__xer_ov_ok$next[0:0]$5309 \data_r2__xer_ov_ok
+ assign $1\data_r2__xer_ov$next[1:0]$5292 \data_r2__xer_ov
+ assign $1\data_r2__xer_ov_ok$next[0:0]$5293 \data_r2__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov$next[1:0]$5310 } 3'000
+ assign { $2\data_r2__xer_ov_ok$next[0:0]$5295 $2\data_r2__xer_ov$next[1:0]$5294 } 3'000
case
- assign $2\data_r2__xer_ov$next[1:0]$5310 $1\data_r2__xer_ov$next[1:0]$5308
- assign $2\data_r2__xer_ov_ok$next[0:0]$5311 $1\data_r2__xer_ov_ok$next[0:0]$5309
+ assign $2\data_r2__xer_ov$next[1:0]$5294 $1\data_r2__xer_ov$next[1:0]$5292
+ assign $2\data_r2__xer_ov_ok$next[0:0]$5295 $1\data_r2__xer_ov_ok$next[0:0]$5293
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ov_ok$next[0:0]$5312 1'0
+ assign $3\data_r2__xer_ov_ok$next[0:0]$5296 1'0
case
- assign $3\data_r2__xer_ov_ok$next[0:0]$5312 $2\data_r2__xer_ov_ok$next[0:0]$5311
+ assign $3\data_r2__xer_ov_ok$next[0:0]$5296 $2\data_r2__xer_ov_ok$next[0:0]$5295
end
sync always
- update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306
- update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307
+ update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5290
+ update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5291
end
- attribute \src "libresoc.v:133715.3-133736.6"
- process $proc$libresoc.v:133715$5313
+ attribute \src "libresoc.v:133540.3-133561.6"
+ process $proc$libresoc.v:133540$5297
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318
+ assign $0\data_r3__xer_so$next[0:0]$5298 $2\data_r3__xer_so$next[0:0]$5302
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320
- attribute \src "libresoc.v:133716.5-133716.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$5299 $3\data_r3__xer_so_ok$next[0:0]$5304
+ attribute \src "libresoc.v:133541.5-133541.29"
switch \initial
- attribute \src "libresoc.v:133716.9-133716.17"
+ attribute \src "libresoc.v:133541.9-133541.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5316 } { \xer_so_ok \alu_div0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$5301 $1\data_r3__xer_so$next[0:0]$5300 } { \xer_so_ok \alu_div0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$5316 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$5317 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$5300 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$5301 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so$next[0:0]$5318 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$5303 $2\data_r3__xer_so$next[0:0]$5302 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$5318 $1\data_r3__xer_so$next[0:0]$5316
- assign $2\data_r3__xer_so_ok$next[0:0]$5319 $1\data_r3__xer_so_ok$next[0:0]$5317
+ assign $2\data_r3__xer_so$next[0:0]$5302 $1\data_r3__xer_so$next[0:0]$5300
+ assign $2\data_r3__xer_so_ok$next[0:0]$5303 $1\data_r3__xer_so_ok$next[0:0]$5301
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$5320 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$5304 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$5320 $2\data_r3__xer_so_ok$next[0:0]$5319
+ assign $3\data_r3__xer_so_ok$next[0:0]$5304 $2\data_r3__xer_so_ok$next[0:0]$5303
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5298
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5299
end
- attribute \src "libresoc.v:133737.3-133746.6"
- process $proc$libresoc.v:133737$5321
+ attribute \src "libresoc.v:133562.3-133571.6"
+ process $proc$libresoc.v:133562$5305
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323
- attribute \src "libresoc.v:133738.5-133738.29"
+ assign $0\src_r0$next[63:0]$5306 $1\src_r0$next[63:0]$5307
+ attribute \src "libresoc.v:133563.5-133563.29"
switch \initial
- attribute \src "libresoc.v:133738.9-133738.17"
+ attribute \src "libresoc.v:133563.9-133563.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$5323 \src_or_imm
+ assign $1\src_r0$next[63:0]$5307 \src_or_imm
case
- assign $1\src_r0$next[63:0]$5323 \src_r0
+ assign $1\src_r0$next[63:0]$5307 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$5322
+ update \src_r0$next $0\src_r0$next[63:0]$5306
end
- attribute \src "libresoc.v:133747.3-133756.6"
- process $proc$libresoc.v:133747$5324
+ attribute \src "libresoc.v:133572.3-133581.6"
+ process $proc$libresoc.v:133572$5308
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326
- attribute \src "libresoc.v:133748.5-133748.29"
+ assign $0\src_r1$next[63:0]$5309 $1\src_r1$next[63:0]$5310
+ attribute \src "libresoc.v:133573.5-133573.29"
switch \initial
- attribute \src "libresoc.v:133748.9-133748.17"
+ attribute \src "libresoc.v:133573.9-133573.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$5326 \src_or_imm$85
+ assign $1\src_r1$next[63:0]$5310 \src_or_imm$85
case
- assign $1\src_r1$next[63:0]$5326 \src_r1
+ assign $1\src_r1$next[63:0]$5310 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$5325
+ update \src_r1$next $0\src_r1$next[63:0]$5309
end
- attribute \src "libresoc.v:133757.3-133766.6"
- process $proc$libresoc.v:133757$5327
+ attribute \src "libresoc.v:133582.3-133591.6"
+ process $proc$libresoc.v:133582$5311
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329
- attribute \src "libresoc.v:133758.5-133758.29"
+ assign $0\src_r2$next[0:0]$5312 $1\src_r2$next[0:0]$5313
+ attribute \src "libresoc.v:133583.5-133583.29"
switch \initial
- attribute \src "libresoc.v:133758.9-133758.17"
+ attribute \src "libresoc.v:133583.9-133583.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$5329 \src3_i
+ assign $1\src_r2$next[0:0]$5313 \src3_i
case
- assign $1\src_r2$next[0:0]$5329 \src_r2
+ assign $1\src_r2$next[0:0]$5313 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$5328
+ update \src_r2$next $0\src_r2$next[0:0]$5312
end
- attribute \src "libresoc.v:133767.3-133775.6"
- process $proc$libresoc.v:133767$5330
+ attribute \src "libresoc.v:133592.3-133600.6"
+ process $proc$libresoc.v:133592$5314
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332
- attribute \src "libresoc.v:133768.5-133768.29"
+ assign $0\alui_l_r_alui$next[0:0]$5315 $1\alui_l_r_alui$next[0:0]$5316
+ attribute \src "libresoc.v:133593.5-133593.29"
switch \initial
- attribute \src "libresoc.v:133768.9-133768.17"
+ attribute \src "libresoc.v:133593.9-133593.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$5332 1'1
+ assign $1\alui_l_r_alui$next[0:0]$5316 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$5332 \$94
+ assign $1\alui_l_r_alui$next[0:0]$5316 \$94
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5315
end
- attribute \src "libresoc.v:133776.3-133784.6"
- process $proc$libresoc.v:133776$5333
+ attribute \src "libresoc.v:133601.3-133609.6"
+ process $proc$libresoc.v:133601$5317
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335
- attribute \src "libresoc.v:133777.5-133777.29"
+ assign $0\alu_l_r_alu$next[0:0]$5318 $1\alu_l_r_alu$next[0:0]$5319
+ attribute \src "libresoc.v:133602.5-133602.29"
switch \initial
- attribute \src "libresoc.v:133777.9-133777.17"
+ attribute \src "libresoc.v:133602.9-133602.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$5335 1'1
+ assign $1\alu_l_r_alu$next[0:0]$5319 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$5335 \$96
+ assign $1\alu_l_r_alu$next[0:0]$5319 \$96
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5334
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5318
end
- attribute \src "libresoc.v:133785.3-133794.6"
- process $proc$libresoc.v:133785$5336
+ attribute \src "libresoc.v:133610.3-133619.6"
+ process $proc$libresoc.v:133610$5320
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:133786.5-133786.29"
+ attribute \src "libresoc.v:133611.5-133611.29"
switch \initial
- attribute \src "libresoc.v:133786.9-133786.17"
+ attribute \src "libresoc.v:133611.9-133611.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:133795.3-133804.6"
- process $proc$libresoc.v:133795$5337
+ attribute \src "libresoc.v:133620.3-133629.6"
+ process $proc$libresoc.v:133620$5321
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:133796.5-133796.29"
+ attribute \src "libresoc.v:133621.5-133621.29"
switch \initial
- attribute \src "libresoc.v:133796.9-133796.17"
+ attribute \src "libresoc.v:133621.9-133621.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:133805.3-133814.6"
- process $proc$libresoc.v:133805$5338
+ attribute \src "libresoc.v:133630.3-133639.6"
+ process $proc$libresoc.v:133630$5322
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:133806.5-133806.29"
+ attribute \src "libresoc.v:133631.5-133631.29"
switch \initial
- attribute \src "libresoc.v:133806.9-133806.17"
+ attribute \src "libresoc.v:133631.9-133631.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:133815.3-133824.6"
- process $proc$libresoc.v:133815$5339
+ attribute \src "libresoc.v:133640.3-133649.6"
+ process $proc$libresoc.v:133640$5323
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:133816.5-133816.29"
+ attribute \src "libresoc.v:133641.5-133641.29"
switch \initial
- attribute \src "libresoc.v:133816.9-133816.17"
+ attribute \src "libresoc.v:133641.9-133641.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:133825.3-133833.6"
- process $proc$libresoc.v:133825$5340
+ attribute \src "libresoc.v:133650.3-133658.6"
+ process $proc$libresoc.v:133650$5324
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[3:0]$5341 $1\prev_wr_go$next[3:0]$5342
- attribute \src "libresoc.v:133826.5-133826.29"
+ assign $0\prev_wr_go$next[3:0]$5325 $1\prev_wr_go$next[3:0]$5326
+ attribute \src "libresoc.v:133651.5-133651.29"
switch \initial
- attribute \src "libresoc.v:133826.9-133826.17"
+ attribute \src "libresoc.v:133651.9-133651.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[3:0]$5342 4'0000
- case
- assign $1\prev_wr_go$next[3:0]$5342 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5341
- end
- connect \$100 $not$libresoc.v:133274$5108_Y
- connect \$102 $not$libresoc.v:133275$5109_Y
- connect \$104 $and$libresoc.v:133276$5110_Y
- connect \$106 $not$libresoc.v:133277$5111_Y
- connect \$108 $and$libresoc.v:133278$5112_Y
- connect \$10 $and$libresoc.v:133279$5113_Y
- connect \$110 $and$libresoc.v:133280$5114_Y
- connect \$112 $and$libresoc.v:133281$5115_Y
- connect \$114 $and$libresoc.v:133282$5116_Y
- connect \$116 $and$libresoc.v:133283$5117_Y
- connect \$118 $and$libresoc.v:133284$5118_Y
- connect \$120 $and$libresoc.v:133285$5119_Y
- connect \$122 $and$libresoc.v:133286$5120_Y
- connect \$124 $and$libresoc.v:133287$5121_Y
- connect \$126 $and$libresoc.v:133288$5122_Y
- connect \$128 $and$libresoc.v:133289$5123_Y
- connect \$12 $not$libresoc.v:133290$5124_Y
- connect \$14 $and$libresoc.v:133291$5125_Y
- connect \$16 $not$libresoc.v:133292$5126_Y
- connect \$18 $and$libresoc.v:133293$5127_Y
- connect \$20 $and$libresoc.v:133294$5128_Y
- connect \$24 $not$libresoc.v:133295$5129_Y
- connect \$26 $and$libresoc.v:133296$5130_Y
- connect \$23 $reduce_or$libresoc.v:133297$5131_Y
- connect \$22 $not$libresoc.v:133298$5132_Y
- connect \$2 $and$libresoc.v:133299$5133_Y
- connect \$30 $and$libresoc.v:133300$5134_Y
- connect \$32 $reduce_or$libresoc.v:133301$5135_Y
- connect \$34 $reduce_or$libresoc.v:133302$5136_Y
- connect \$36 $or$libresoc.v:133303$5137_Y
- connect \$38 $not$libresoc.v:133304$5138_Y
- connect \$40 $and$libresoc.v:133305$5139_Y
- connect \$42 $and$libresoc.v:133306$5140_Y
- connect \$44 $eq$libresoc.v:133307$5141_Y
- connect \$46 $and$libresoc.v:133308$5142_Y
- connect \$48 $eq$libresoc.v:133309$5143_Y
- connect \$50 $and$libresoc.v:133310$5144_Y
- connect \$52 $and$libresoc.v:133311$5145_Y
- connect \$54 $and$libresoc.v:133312$5146_Y
- connect \$56 $or$libresoc.v:133313$5147_Y
- connect \$58 $or$libresoc.v:133314$5148_Y
- connect \$5 $not$libresoc.v:133315$5149_Y
- connect \$60 $or$libresoc.v:133316$5150_Y
- connect \$62 $or$libresoc.v:133317$5151_Y
- connect \$64 $and$libresoc.v:133318$5152_Y
- connect \$66 $and$libresoc.v:133319$5153_Y
- connect \$68 $or$libresoc.v:133320$5154_Y
- connect \$70 $and$libresoc.v:133321$5155_Y
- connect \$72 $and$libresoc.v:133322$5156_Y
- connect \$74 $and$libresoc.v:133323$5157_Y
- connect \$76 $and$libresoc.v:133324$5158_Y
- connect \$78 $ternary$libresoc.v:133325$5159_Y
- connect \$7 $or$libresoc.v:133326$5160_Y
- connect \$80 $ternary$libresoc.v:133327$5161_Y
- connect \$83 $ternary$libresoc.v:133328$5162_Y
- connect \$86 $ternary$libresoc.v:133329$5163_Y
- connect \$88 $ternary$libresoc.v:133330$5164_Y
- connect \$4 $reduce_and$libresoc.v:133331$5165_Y
- connect \$90 $ternary$libresoc.v:133332$5166_Y
- connect \$92 $ternary$libresoc.v:133333$5167_Y
- connect \$94 $and$libresoc.v:133334$5168_Y
- connect \$96 $and$libresoc.v:133335$5169_Y
- connect \$98 $and$libresoc.v:133336$5170_Y
+ assign $1\prev_wr_go$next[3:0]$5326 4'0000
+ case
+ assign $1\prev_wr_go$next[3:0]$5326 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5325
+ end
+ connect \$100 $not$libresoc.v:133099$5092_Y
+ connect \$102 $not$libresoc.v:133100$5093_Y
+ connect \$104 $and$libresoc.v:133101$5094_Y
+ connect \$106 $not$libresoc.v:133102$5095_Y
+ connect \$108 $and$libresoc.v:133103$5096_Y
+ connect \$10 $and$libresoc.v:133104$5097_Y
+ connect \$110 $and$libresoc.v:133105$5098_Y
+ connect \$112 $and$libresoc.v:133106$5099_Y
+ connect \$114 $and$libresoc.v:133107$5100_Y
+ connect \$116 $and$libresoc.v:133108$5101_Y
+ connect \$118 $and$libresoc.v:133109$5102_Y
+ connect \$120 $and$libresoc.v:133110$5103_Y
+ connect \$122 $and$libresoc.v:133111$5104_Y
+ connect \$124 $and$libresoc.v:133112$5105_Y
+ connect \$126 $and$libresoc.v:133113$5106_Y
+ connect \$128 $and$libresoc.v:133114$5107_Y
+ connect \$12 $not$libresoc.v:133115$5108_Y
+ connect \$14 $and$libresoc.v:133116$5109_Y
+ connect \$16 $not$libresoc.v:133117$5110_Y
+ connect \$18 $and$libresoc.v:133118$5111_Y
+ connect \$20 $and$libresoc.v:133119$5112_Y
+ connect \$24 $not$libresoc.v:133120$5113_Y
+ connect \$26 $and$libresoc.v:133121$5114_Y
+ connect \$23 $reduce_or$libresoc.v:133122$5115_Y
+ connect \$22 $not$libresoc.v:133123$5116_Y
+ connect \$2 $and$libresoc.v:133124$5117_Y
+ connect \$30 $and$libresoc.v:133125$5118_Y
+ connect \$32 $reduce_or$libresoc.v:133126$5119_Y
+ connect \$34 $reduce_or$libresoc.v:133127$5120_Y
+ connect \$36 $or$libresoc.v:133128$5121_Y
+ connect \$38 $not$libresoc.v:133129$5122_Y
+ connect \$40 $and$libresoc.v:133130$5123_Y
+ connect \$42 $and$libresoc.v:133131$5124_Y
+ connect \$44 $eq$libresoc.v:133132$5125_Y
+ connect \$46 $and$libresoc.v:133133$5126_Y
+ connect \$48 $eq$libresoc.v:133134$5127_Y
+ connect \$50 $and$libresoc.v:133135$5128_Y
+ connect \$52 $and$libresoc.v:133136$5129_Y
+ connect \$54 $and$libresoc.v:133137$5130_Y
+ connect \$56 $or$libresoc.v:133138$5131_Y
+ connect \$58 $or$libresoc.v:133139$5132_Y
+ connect \$5 $not$libresoc.v:133140$5133_Y
+ connect \$60 $or$libresoc.v:133141$5134_Y
+ connect \$62 $or$libresoc.v:133142$5135_Y
+ connect \$64 $and$libresoc.v:133143$5136_Y
+ connect \$66 $and$libresoc.v:133144$5137_Y
+ connect \$68 $or$libresoc.v:133145$5138_Y
+ connect \$70 $and$libresoc.v:133146$5139_Y
+ connect \$72 $and$libresoc.v:133147$5140_Y
+ connect \$74 $and$libresoc.v:133148$5141_Y
+ connect \$76 $and$libresoc.v:133149$5142_Y
+ connect \$78 $ternary$libresoc.v:133150$5143_Y
+ connect \$7 $or$libresoc.v:133151$5144_Y
+ connect \$80 $ternary$libresoc.v:133152$5145_Y
+ connect \$83 $ternary$libresoc.v:133153$5146_Y
+ connect \$86 $ternary$libresoc.v:133154$5147_Y
+ connect \$88 $ternary$libresoc.v:133155$5148_Y
+ connect \$4 $reduce_and$libresoc.v:133156$5149_Y
+ connect \$90 $ternary$libresoc.v:133157$5150_Y
+ connect \$92 $ternary$libresoc.v:133158$5151_Y
+ connect \$94 $and$libresoc.v:133159$5152_Y
+ connect \$96 $and$libresoc.v:133160$5153_Y
+ connect \$98 $and$libresoc.v:133161$5154_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$120
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:133870.1-133879.10"
+attribute \src "libresoc.v:133695.1-133704.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init"
attribute \generator "nMigen"
connect \o_dividend_quotient \dividend
connect \o_q_bits_known 7'0000000
end
-attribute \src "libresoc.v:133883.1-133965.10"
+attribute \src "libresoc.v:133708.1-133790.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next"
attribute \generator "nMigen"
module \div_state_next
- attribute \src "libresoc.v:133884.7-133884.20"
+ attribute \src "libresoc.v:133709.7-133709.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:133949.3-133960.6"
+ attribute \src "libresoc.v:133774.3-133785.6"
wire width 128 $0\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:133937.3-133948.6"
+ attribute \src "libresoc.v:133762.3-133773.6"
wire width 7 $0\o_q_bits_known[6:0]
- attribute \src "libresoc.v:133925.3-133936.6"
+ attribute \src "libresoc.v:133750.3-133761.6"
wire width 128 $0\value[127:0]
- attribute \src "libresoc.v:133949.3-133960.6"
+ attribute \src "libresoc.v:133774.3-133785.6"
wire width 128 $1\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:133937.3-133948.6"
+ attribute \src "libresoc.v:133762.3-133773.6"
wire width 7 $1\o_q_bits_known[6:0]
- attribute \src "libresoc.v:133925.3-133936.6"
+ attribute \src "libresoc.v:133750.3-133761.6"
wire width 128 $1\value[127:0]
- attribute \src "libresoc.v:133919.18-133919.106"
- wire width 8 $add$libresoc.v:133919$5388_Y
- attribute \src "libresoc.v:133920.18-133920.109"
- wire $ge$libresoc.v:133920$5389_Y
- attribute \src "libresoc.v:133924.17-133924.108"
- wire $ge$libresoc.v:133924$5393_Y
- attribute \src "libresoc.v:133923.17-133923.101"
- wire $not$libresoc.v:133923$5392_Y
- attribute \src "libresoc.v:133921.17-133921.101"
- wire width 127 $sshl$libresoc.v:133921$5390_Y
- attribute \src "libresoc.v:133922.17-133922.109"
- wire width 129 $sub$libresoc.v:133922$5391_Y
+ attribute \src "libresoc.v:133744.18-133744.106"
+ wire width 8 $add$libresoc.v:133744$5372_Y
+ attribute \src "libresoc.v:133745.18-133745.109"
+ wire $ge$libresoc.v:133745$5373_Y
+ attribute \src "libresoc.v:133749.17-133749.108"
+ wire $ge$libresoc.v:133749$5377_Y
+ attribute \src "libresoc.v:133748.17-133748.101"
+ wire $not$libresoc.v:133748$5376_Y
+ attribute \src "libresoc.v:133746.17-133746.101"
+ wire width 127 $sshl$libresoc.v:133746$5374_Y
+ attribute \src "libresoc.v:133747.17-133747.109"
+ wire width 129 $sub$libresoc.v:133747$5375_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
wire width 129 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81"
wire width 128 input 3 \i_dividend_quotient
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103"
wire width 7 input 2 \i_q_bits_known
- attribute \src "libresoc.v:133884.7-133884.15"
+ attribute \src "libresoc.v:133709.7-133709.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68"
wire \next_quotient_bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71"
wire width 128 \value
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81"
- cell $add $add$libresoc.v:133919$5388
+ cell $add $add$libresoc.v:133744$5372
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \i_q_bits_known
connect \B 1'1
- connect \Y $add$libresoc.v:133919$5388_Y
+ connect \Y $add$libresoc.v:133744$5372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:133920$5389
+ cell $ge $ge$libresoc.v:133745$5373
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i_q_bits_known
connect \B 7'1000000
- connect \Y $ge$libresoc.v:133920$5389_Y
+ connect \Y $ge$libresoc.v:133745$5373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:133924$5393
+ cell $ge $ge$libresoc.v:133749$5377
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i_q_bits_known
connect \B 7'1000000
- connect \Y $ge$libresoc.v:133924$5393_Y
+ connect \Y $ge$libresoc.v:133749$5377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70"
- cell $not $not$libresoc.v:133923$5392
+ cell $not $not$libresoc.v:133748$5376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \difference [127]
- connect \Y $not$libresoc.v:133923$5392_Y
+ connect \Y $not$libresoc.v:133748$5376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
- cell $sshl $sshl$libresoc.v:133921$5390
+ cell $sshl $sshl$libresoc.v:133746$5374
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 127
connect \A \divisor
connect \B 6'111111
- connect \Y $sshl$libresoc.v:133921$5390_Y
+ connect \Y $sshl$libresoc.v:133746$5374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
- cell $sub $sub$libresoc.v:133922$5391
+ cell $sub $sub$libresoc.v:133747$5375
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \B_SIGNED 0
parameter \Y_WIDTH 129
connect \A \i_dividend_quotient
connect \B \$2
- connect \Y $sub$libresoc.v:133922$5391_Y
+ connect \Y $sub$libresoc.v:133747$5375_Y
end
- attribute \src "libresoc.v:133884.7-133884.20"
- process $proc$libresoc.v:133884$5397
+ attribute \src "libresoc.v:133709.7-133709.20"
+ process $proc$libresoc.v:133709$5381
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:133925.3-133936.6"
- process $proc$libresoc.v:133925$5394
+ attribute \src "libresoc.v:133750.3-133761.6"
+ process $proc$libresoc.v:133750$5378
assign { } { }
assign $0\value[127:0] $1\value[127:0]
- attribute \src "libresoc.v:133926.5-133926.29"
+ attribute \src "libresoc.v:133751.5-133751.29"
switch \initial
- attribute \src "libresoc.v:133926.9-133926.17"
+ attribute \src "libresoc.v:133751.9-133751.17"
case 1'1
case
end
sync always
update \value $0\value[127:0]
end
- attribute \src "libresoc.v:133937.3-133948.6"
- process $proc$libresoc.v:133937$5395
+ attribute \src "libresoc.v:133762.3-133773.6"
+ process $proc$libresoc.v:133762$5379
assign { } { }
assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0]
- attribute \src "libresoc.v:133938.5-133938.29"
+ attribute \src "libresoc.v:133763.5-133763.29"
switch \initial
- attribute \src "libresoc.v:133938.9-133938.17"
+ attribute \src "libresoc.v:133763.9-133763.17"
case 1'1
case
end
sync always
update \o_q_bits_known $0\o_q_bits_known[6:0]
end
- attribute \src "libresoc.v:133949.3-133960.6"
- process $proc$libresoc.v:133949$5396
+ attribute \src "libresoc.v:133774.3-133785.6"
+ process $proc$libresoc.v:133774$5380
assign { } { }
assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:133950.5-133950.29"
+ attribute \src "libresoc.v:133775.5-133775.29"
switch \initial
- attribute \src "libresoc.v:133950.9-133950.17"
+ attribute \src "libresoc.v:133775.9-133775.17"
case 1'1
case
end
sync always
update \o_dividend_quotient $0\o_dividend_quotient[127:0]
end
- connect \$11 $add$libresoc.v:133919$5388_Y
- connect \$13 $ge$libresoc.v:133920$5389_Y
- connect \$2 $sshl$libresoc.v:133921$5390_Y
- connect \$4 $sub$libresoc.v:133922$5391_Y
- connect \$6 $not$libresoc.v:133923$5392_Y
- connect \$8 $ge$libresoc.v:133924$5393_Y
+ connect \$11 $add$libresoc.v:133744$5372_Y
+ connect \$13 $ge$libresoc.v:133745$5373_Y
+ connect \$2 $sshl$libresoc.v:133746$5374_Y
+ connect \$4 $sub$libresoc.v:133747$5375_Y
+ connect \$6 $not$libresoc.v:133748$5376_Y
+ connect \$8 $ge$libresoc.v:133749$5377_Y
connect \$1 \$4
connect \$10 \$11
connect \next_quotient_bit \$6
connect \difference \$4 [127:0]
end
-attribute \src "libresoc.v:133969.1-134212.10"
+attribute \src "libresoc.v:133794.1-134037.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy"
attribute \generator "nMigen"
connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \muxid$1 \muxid
end
-attribute \src "libresoc.v:134216.1-134387.10"
+attribute \src "libresoc.v:134041.1-134172.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fast"
attribute \generator "nMigen"
module \fast
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 3 $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 3 $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414
- attribute \src "libresoc.v:134305.3-134311.6"
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 3 $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 3 $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398
+ attribute \src "libresoc.v:134114.3-134119.6"
wire width 3 $0\_0_[2:0]
- attribute \src "libresoc.v:134305.3-134311.6"
+ attribute \src "libresoc.v:134114.3-134119.6"
wire width 3 $0\_1_[2:0]
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 3 $0\_2_[2:0]
- attribute \src "libresoc.v:134217.7-134217.20"
+ attribute \src "libresoc.v:134042.7-134042.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:134368.3-134377.6"
+ attribute \src "libresoc.v:134154.3-134163.6"
wire width 64 $0\issue__data_o[63:0]
- attribute \src "libresoc.v:134340.3-134348.6"
- wire $0\ren_delay$10$next[0:0]$5434
- attribute \src "libresoc.v:134317.3-134318.43"
- wire $0\ren_delay$10[0:0]$5427
- attribute \src "libresoc.v:134268.7-134268.28"
- wire $0\ren_delay$10[0:0]$5452
- attribute \src "libresoc.v:134359.3-134367.6"
- wire $0\ren_delay$11$next[0:0]$5438
- attribute \src "libresoc.v:134315.3-134316.43"
- wire $0\ren_delay$11[0:0]$5425
- attribute \src "libresoc.v:134272.7-134272.28"
- wire $0\ren_delay$11[0:0]$5454
- attribute \src "libresoc.v:134321.3-134329.6"
- wire $0\ren_delay$next[0:0]$5430
- attribute \src "libresoc.v:134319.3-134320.35"
+ attribute \src "libresoc.v:134145.3-134153.6"
+ wire $0\ren_delay$8$next[0:0]$5415
+ attribute \src "libresoc.v:134122.3-134123.41"
+ wire $0\ren_delay$8[0:0]$5408
+ attribute \src "libresoc.v:134089.7-134089.27"
+ wire $0\ren_delay$8[0:0]$5429
+ attribute \src "libresoc.v:134126.3-134134.6"
+ wire $0\ren_delay$next[0:0]$5411
+ attribute \src "libresoc.v:134124.3-134125.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:134330.3-134339.6"
+ attribute \src "libresoc.v:134135.3-134144.6"
wire width 64 $0\src1__data_o[63:0]
- attribute \src "libresoc.v:134349.3-134358.6"
- wire width 64 $0\src2__data_o[63:0]
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 3 $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 3 $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419
- attribute \src "libresoc.v:134305.3-134311.6"
- wire width 64 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420
- attribute \src "libresoc.v:134368.3-134377.6"
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 3 $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 3 $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403
+ attribute \src "libresoc.v:134114.3-134119.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404
+ attribute \src "libresoc.v:134154.3-134163.6"
wire width 64 $1\issue__data_o[63:0]
- attribute \src "libresoc.v:134340.3-134348.6"
- wire $1\ren_delay$10$next[0:0]$5435
- attribute \src "libresoc.v:134359.3-134367.6"
- wire $1\ren_delay$11$next[0:0]$5439
- attribute \src "libresoc.v:134321.3-134329.6"
- wire $1\ren_delay$next[0:0]$5431
- attribute \src "libresoc.v:134266.7-134266.23"
+ attribute \src "libresoc.v:134145.3-134153.6"
+ wire $1\ren_delay$8$next[0:0]$5416
+ attribute \src "libresoc.v:134126.3-134134.6"
+ wire $1\ren_delay$next[0:0]$5412
+ attribute \src "libresoc.v:134087.7-134087.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:134330.3-134339.6"
+ attribute \src "libresoc.v:134135.3-134144.6"
wire width 64 $1\src1__data_o[63:0]
- attribute \src "libresoc.v:134349.3-134358.6"
- wire width 64 $1\src2__data_o[63:0]
- attribute \src "libresoc.v:134312.26-134312.32"
- wire width 64 $memrd$\memory$libresoc.v:134312$5421_DATA
- attribute \src "libresoc.v:134313.30-134313.36"
- wire width 64 $memrd$\memory$libresoc.v:134313$5422_DATA
- attribute \src "libresoc.v:134314.30-134314.36"
- wire width 64 $memrd$\memory$libresoc.v:134314$5423_DATA
+ attribute \src "libresoc.v:134120.26-134120.32"
+ wire width 64 $memrd$\memory$libresoc.v:134120$5405_DATA
+ attribute \src "libresoc.v:134121.30-134121.36"
+ wire width 64 $memrd$\memory$libresoc.v:134121$5406_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 3 $memwr$\memory$libresoc.v:134309$5406_ADDR
+ wire width 3 $memwr$\memory$libresoc.v:134117$5390_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:134309$5406_DATA
+ wire width 64 $memwr$\memory$libresoc.v:134117$5390_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:134309$5406_EN
+ wire width 64 $memwr$\memory$libresoc.v:134117$5390_EN
attribute \src "libresoc.v:0.0-0.0"
- wire width 3 $memwr$\memory$libresoc.v:134310$5407_ADDR
+ wire width 3 $memwr$\memory$libresoc.v:134118$5391_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:134310$5407_DATA
+ wire width 64 $memwr$\memory$libresoc.v:134118$5391_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:134310$5407_EN
- attribute \src "libresoc.v:134302.13-134302.16"
+ wire width 64 $memwr$\memory$libresoc.v:134118$5391_EN
+ attribute \src "libresoc.v:134112.13-134112.16"
wire width 3 \_0_
- attribute \src "libresoc.v:134303.13-134303.16"
+ attribute \src "libresoc.v:134113.13-134113.16"
wire width 3 \_1_
- attribute \src "libresoc.v:134304.13-134304.16"
- wire width 3 \_2_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 17 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 14 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 3 input 15 \dest1__addr
+ wire width 3 input 12 \dest1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 input 14 \dest1__data_i
+ wire width 64 input 11 \dest1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 16 \dest1__wen
- attribute \src "libresoc.v:134217.7-134217.15"
+ wire input 13 \dest1__wen
+ attribute \src "libresoc.v:134042.7-134042.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 2 \issue__addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 3 \memory_r_addr$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 3 \memory_r_addr$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 64 \memory_r_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 64 \memory_r_data$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 64 \memory_r_data$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire width 3 \memory_w_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
- wire width 3 \memory_w_addr$8
+ wire width 3 \memory_w_addr$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire width 64 \memory_w_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
- wire width 64 \memory_w_data$9
+ wire width 64 \memory_w_data$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire \memory_w_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
- wire \memory_w_en$7
+ wire \memory_w_en$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
wire \ren_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$10$next
+ wire \ren_delay$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$11$next
+ wire \ren_delay$8$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
wire \ren_delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 8 \src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \src1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 3 input 12 \src2__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 output 11 \src2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 13 \src2__ren
- attribute \src "libresoc.v:134291.14-134291.20"
+ attribute \src "libresoc.v:134101.14-134101.20"
memory width 64 size 8 \memory
- attribute \src "libresoc.v:134293.5-134293.37"
- cell $meminit $meminit$\memory$libresoc.v:134293$5441
+ attribute \src "libresoc.v:134103.5-134103.37"
+ cell $meminit $meminit$\memory$libresoc.v:134103$5418
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5441
+ parameter \PRIORITY 5418
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134294.5-134294.37"
- cell $meminit $meminit$\memory$libresoc.v:134294$5442
+ attribute \src "libresoc.v:134104.5-134104.37"
+ cell $meminit $meminit$\memory$libresoc.v:134104$5419
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5442
+ parameter \PRIORITY 5419
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134295.5-134295.37"
- cell $meminit $meminit$\memory$libresoc.v:134295$5443
+ attribute \src "libresoc.v:134105.5-134105.37"
+ cell $meminit $meminit$\memory$libresoc.v:134105$5420
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5443
+ parameter \PRIORITY 5420
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134296.5-134296.37"
- cell $meminit $meminit$\memory$libresoc.v:134296$5444
+ attribute \src "libresoc.v:134106.5-134106.37"
+ cell $meminit $meminit$\memory$libresoc.v:134106$5421
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5444
+ parameter \PRIORITY 5421
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134297.5-134297.37"
- cell $meminit $meminit$\memory$libresoc.v:134297$5445
+ attribute \src "libresoc.v:134107.5-134107.37"
+ cell $meminit $meminit$\memory$libresoc.v:134107$5422
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5445
+ parameter \PRIORITY 5422
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134298.5-134298.37"
- cell $meminit $meminit$\memory$libresoc.v:134298$5446
+ attribute \src "libresoc.v:134108.5-134108.37"
+ cell $meminit $meminit$\memory$libresoc.v:134108$5423
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5446
+ parameter \PRIORITY 5423
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134299.5-134299.37"
- cell $meminit $meminit$\memory$libresoc.v:134299$5447
+ attribute \src "libresoc.v:134109.5-134109.37"
+ cell $meminit $meminit$\memory$libresoc.v:134109$5424
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5447
+ parameter \PRIORITY 5424
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134300.5-134300.37"
- cell $meminit $meminit$\memory$libresoc.v:134300$5448
+ attribute \src "libresoc.v:134110.5-134110.37"
+ cell $meminit $meminit$\memory$libresoc.v:134110$5425
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5448
+ parameter \PRIORITY 5425
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134312.26-134312.32"
- cell $memrd $memrd$\memory$libresoc.v:134312$5421
+ attribute \src "libresoc.v:134120.26-134120.32"
+ cell $memrd $memrd$\memory$libresoc.v:134120$5405
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:134312$5421_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134120$5405_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:134313.30-134313.36"
- cell $memrd $memrd$\memory$libresoc.v:134313$5422
+ attribute \src "libresoc.v:134121.30-134121.36"
+ cell $memrd $memrd$\memory$libresoc.v:134121$5406
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_1_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:134313$5422_DATA
- connect \EN 1'x
- end
- attribute \src "libresoc.v:134314.30-134314.36"
- cell $memrd $memrd$\memory$libresoc.v:134314$5423
- parameter \ABITS 3
- parameter \CLK_ENABLE 0
- parameter \CLK_POLARITY 0
- parameter \MEMID "\\memory"
- parameter \TRANSPARENT 0
- parameter \WIDTH 64
- connect \ADDR \_2_
- connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:134314$5423_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134121$5406_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$5455
+ process $proc$libresoc.v:0$5430
sync always
sync init
end
- attribute \src "libresoc.v:134217.7-134217.20"
- process $proc$libresoc.v:134217$5449
+ attribute \src "libresoc.v:134042.7-134042.20"
+ process $proc$libresoc.v:134042$5426
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:134266.7-134266.23"
- process $proc$libresoc.v:134266$5450
+ attribute \src "libresoc.v:134087.7-134087.23"
+ process $proc$libresoc.v:134087$5427
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:134268.7-134268.28"
- process $proc$libresoc.v:134268$5451
- assign { } { }
- assign $0\ren_delay$10[0:0]$5452 1'0
- sync always
- sync init
- update \ren_delay$10 $0\ren_delay$10[0:0]$5452
- end
- attribute \src "libresoc.v:134272.7-134272.28"
- process $proc$libresoc.v:134272$5453
+ attribute \src "libresoc.v:134089.7-134089.27"
+ process $proc$libresoc.v:134089$5428
assign { } { }
- assign $0\ren_delay$11[0:0]$5454 1'0
+ assign $0\ren_delay$8[0:0]$5429 1'0
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[0:0]$5454
+ update \ren_delay$8 $0\ren_delay$8[0:0]$5429
end
- attribute \src "libresoc.v:134305.3-134311.6"
- process $proc$libresoc.v:134305$5408
- assign { } { }
+ attribute \src "libresoc.v:134114.3-134119.6"
+ process $proc$libresoc.v:134114$5392
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\_0_[2:0] \memory_r_addr
assign $0\_1_[2:0] \memory_r_addr$3
- assign $0\_2_[2:0] \memory_r_addr$5
- assign $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409 $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415
- assign $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416
- assign $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417
- assign $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412 $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418
- assign $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419
- assign $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420
- attribute \src "libresoc.v:134309.5-134309.61"
+ assign $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393 $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399
+ assign $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400
+ assign $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401
+ assign $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396 $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402
+ assign $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403
+ assign $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404
+ attribute \src "libresoc.v:134117.5-134117.61"
switch \memory_w_en
- attribute \src "libresoc.v:134309.9-134309.20"
+ attribute \src "libresoc.v:134117.9-134117.20"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 \memory_w_addr
- assign $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 \memory_w_data
- assign $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 \memory_w_addr
+ assign $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 \memory_w_data
+ assign $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 64'1111111111111111111111111111111111111111111111111111111111111111
case
- assign $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 3'xxx
- assign $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 3'xxx
+ assign $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:134310.5-134310.73"
- switch \memory_w_en$7
- attribute \src "libresoc.v:134310.9-134310.23"
+ attribute \src "libresoc.v:134118.5-134118.73"
+ switch \memory_w_en$5
+ attribute \src "libresoc.v:134118.9-134118.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 \memory_w_addr$8
- assign $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 \memory_w_data$9
- assign $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 \memory_w_addr$6
+ assign $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 \memory_w_data$7
+ assign $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 64'1111111111111111111111111111111111111111111111111111111111111111
case
- assign $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 3'xxx
- assign $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 3'xxx
+ assign $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \coresync_clk
update \_0_ $0\_0_[2:0]
update \_1_ $0\_1_[2:0]
- update \_2_ $0\_2_[2:0]
- update $memwr$\memory$libresoc.v:134309$5406_ADDR $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409
- update $memwr$\memory$libresoc.v:134309$5406_DATA $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410
- update $memwr$\memory$libresoc.v:134309$5406_EN $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411
- update $memwr$\memory$libresoc.v:134310$5407_ADDR $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412
- update $memwr$\memory$libresoc.v:134310$5407_DATA $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413
- update $memwr$\memory$libresoc.v:134310$5407_EN $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414
- attribute \src "libresoc.v:134309.22-134309.60"
- memwr \memory $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 0'
- attribute \src "libresoc.v:134310.26-134310.71"
- memwr \memory $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 1'1
- end
- attribute \src "libresoc.v:134315.3-134316.43"
- process $proc$libresoc.v:134315$5424
- assign { } { }
- assign $0\ren_delay$11[0:0]$5425 \ren_delay$11$next
- sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[0:0]$5425
+ update $memwr$\memory$libresoc.v:134117$5390_ADDR $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393
+ update $memwr$\memory$libresoc.v:134117$5390_DATA $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394
+ update $memwr$\memory$libresoc.v:134117$5390_EN $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395
+ update $memwr$\memory$libresoc.v:134118$5391_ADDR $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396
+ update $memwr$\memory$libresoc.v:134118$5391_DATA $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397
+ update $memwr$\memory$libresoc.v:134118$5391_EN $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398
+ attribute \src "libresoc.v:134117.22-134117.60"
+ memwr \memory $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 0'
+ attribute \src "libresoc.v:134118.26-134118.71"
+ memwr \memory $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 1'1
end
- attribute \src "libresoc.v:134317.3-134318.43"
- process $proc$libresoc.v:134317$5426
+ attribute \src "libresoc.v:134122.3-134123.41"
+ process $proc$libresoc.v:134122$5407
assign { } { }
- assign $0\ren_delay$10[0:0]$5427 \ren_delay$10$next
+ assign $0\ren_delay$8[0:0]$5408 \ren_delay$8$next
sync posedge \coresync_clk
- update \ren_delay$10 $0\ren_delay$10[0:0]$5427
+ update \ren_delay$8 $0\ren_delay$8[0:0]$5408
end
- attribute \src "libresoc.v:134319.3-134320.35"
- process $proc$libresoc.v:134319$5428
+ attribute \src "libresoc.v:134124.3-134125.35"
+ process $proc$libresoc.v:134124$5409
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:134321.3-134329.6"
- process $proc$libresoc.v:134321$5429
+ attribute \src "libresoc.v:134126.3-134134.6"
+ process $proc$libresoc.v:134126$5410
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$5430 $1\ren_delay$next[0:0]$5431
- attribute \src "libresoc.v:134322.5-134322.29"
+ assign $0\ren_delay$next[0:0]$5411 $1\ren_delay$next[0:0]$5412
+ attribute \src "libresoc.v:134127.5-134127.29"
switch \initial
- attribute \src "libresoc.v:134322.9-134322.17"
+ attribute \src "libresoc.v:134127.9-134127.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$5431 1'0
+ assign $1\ren_delay$next[0:0]$5412 1'0
case
- assign $1\ren_delay$next[0:0]$5431 \src1__ren
+ assign $1\ren_delay$next[0:0]$5412 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$5430
+ update \ren_delay$next $0\ren_delay$next[0:0]$5411
end
- attribute \src "libresoc.v:134330.3-134339.6"
- process $proc$libresoc.v:134330$5432
+ attribute \src "libresoc.v:134135.3-134144.6"
+ process $proc$libresoc.v:134135$5413
assign { } { }
assign { } { }
assign $0\src1__data_o[63:0] $1\src1__data_o[63:0]
- attribute \src "libresoc.v:134331.5-134331.29"
+ attribute \src "libresoc.v:134136.5-134136.29"
switch \initial
- attribute \src "libresoc.v:134331.9-134331.17"
+ attribute \src "libresoc.v:134136.9-134136.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[63:0]
end
- attribute \src "libresoc.v:134340.3-134348.6"
- process $proc$libresoc.v:134340$5433
- assign { } { }
- assign { } { }
- assign $0\ren_delay$10$next[0:0]$5434 $1\ren_delay$10$next[0:0]$5435
- attribute \src "libresoc.v:134341.5-134341.29"
- switch \initial
- attribute \src "libresoc.v:134341.9-134341.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ren_delay$10$next[0:0]$5435 1'0
- case
- assign $1\ren_delay$10$next[0:0]$5435 \src2__ren
- end
- sync always
- update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5434
- end
- attribute \src "libresoc.v:134349.3-134358.6"
- process $proc$libresoc.v:134349$5436
- assign { } { }
- assign { } { }
- assign $0\src2__data_o[63:0] $1\src2__data_o[63:0]
- attribute \src "libresoc.v:134350.5-134350.29"
- switch \initial
- attribute \src "libresoc.v:134350.9-134350.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$10
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\src2__data_o[63:0] \memory_r_data$4
- case
- assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \src2__data_o $0\src2__data_o[63:0]
- end
- attribute \src "libresoc.v:134359.3-134367.6"
- process $proc$libresoc.v:134359$5437
+ attribute \src "libresoc.v:134145.3-134153.6"
+ process $proc$libresoc.v:134145$5414
assign { } { }
assign { } { }
- assign $0\ren_delay$11$next[0:0]$5438 $1\ren_delay$11$next[0:0]$5439
- attribute \src "libresoc.v:134360.5-134360.29"
+ assign $0\ren_delay$8$next[0:0]$5415 $1\ren_delay$8$next[0:0]$5416
+ attribute \src "libresoc.v:134146.5-134146.29"
switch \initial
- attribute \src "libresoc.v:134360.9-134360.17"
+ attribute \src "libresoc.v:134146.9-134146.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$11$next[0:0]$5439 1'0
+ assign $1\ren_delay$8$next[0:0]$5416 1'0
case
- assign $1\ren_delay$11$next[0:0]$5439 \issue__ren
+ assign $1\ren_delay$8$next[0:0]$5416 \issue__ren
end
sync always
- update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5438
+ update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5415
end
- attribute \src "libresoc.v:134368.3-134377.6"
- process $proc$libresoc.v:134368$5440
+ attribute \src "libresoc.v:134154.3-134163.6"
+ process $proc$libresoc.v:134154$5417
assign { } { }
assign { } { }
assign $0\issue__data_o[63:0] $1\issue__data_o[63:0]
- attribute \src "libresoc.v:134369.5-134369.29"
+ attribute \src "libresoc.v:134155.5-134155.29"
switch \initial
- attribute \src "libresoc.v:134369.9-134369.17"
+ attribute \src "libresoc.v:134155.9-134155.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$11
+ switch \ren_delay$8
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\issue__data_o[63:0] \memory_r_data$6
+ assign $1\issue__data_o[63:0] \memory_r_data$4
case
assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \issue__data_o $0\issue__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:134312$5421_DATA
- connect \memory_r_data$4 $memrd$\memory$libresoc.v:134313$5422_DATA
- connect \memory_r_data$6 $memrd$\memory$libresoc.v:134314$5423_DATA
- connect \memory_w_data$9 \issue__data_i
- connect \memory_w_en$7 \issue__wen
- connect \memory_w_addr$8 \issue__addr$1
+ connect \memory_r_data $memrd$\memory$libresoc.v:134120$5405_DATA
+ connect \memory_r_data$4 $memrd$\memory$libresoc.v:134121$5406_DATA
+ connect \memory_w_data$7 \issue__data_i
+ connect \memory_w_en$5 \issue__wen
+ connect \memory_w_addr$6 \issue__addr$1
connect \memory_w_data \dest1__data_i
connect \memory_w_en \dest1__wen
connect \memory_w_addr \dest1__addr
- connect \memory_r_addr$5 \issue__addr
- connect \memory_r_addr$3 \src2__addr
+ connect \memory_r_addr$3 \issue__addr
connect \memory_r_addr \src1__addr
end
-attribute \src "libresoc.v:134391.1-136341.10"
+attribute \src "libresoc.v:134176.1-136126.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus"
attribute \generator "nMigen"
module \fus
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 330 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 257 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 input 169 \cu_rd__go_i$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 6 input 172 \cu_rd__go_i$38
+ wire width 3 input 172 \cu_rd__go_i$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 input 175 \cu_rd__go_i$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 input 178 \cu_rd__go_i$44
+ wire width 5 input 178 \cu_rd__go_i$44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 5 input 181 \cu_rd__go_i$47
+ wire width 3 input 181 \cu_rd__go_i$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 input 184 \cu_rd__go_i$50
+ wire width 6 input 190 \cu_rd__go_i$54
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 input 209 \cu_rd__go_i$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 output 168 \cu_rd__rel_o$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 6 output 171 \cu_rd__rel_o$37
+ wire width 3 output 171 \cu_rd__rel_o$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 output 174 \cu_rd__rel_o$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 output 177 \cu_rd__rel_o$43
+ wire width 5 output 177 \cu_rd__rel_o$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 5 output 180 \cu_rd__rel_o$46
+ wire width 3 output 180 \cu_rd__rel_o$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
- wire width 3 output 183 \cu_rd__rel_o$49
+ wire width 6 output 189 \cu_rd__rel_o$53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire width 3 output 208 \cu_rd__rel_o$69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 309 \spr1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 161 \src1_i
+ wire width 64 input 185 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 164 \src1_i$30
+ wire width 64 input 186 \src1_i$50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 167 \src1_i$33
+ wire width 64 input 187 \src1_i$51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 170 \src1_i$36
+ wire width 64 input 188 \src1_i$52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 173 \src1_i$39
+ wire width 64 input 191 \src1_i$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 176 \src1_i$42
+ wire width 64 input 192 \src1_i$56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 179 \src1_i$45
+ wire width 64 input 193 \src1_i$57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 182 \src1_i$48
+ wire width 64 input 194 \src1_i$58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 185 \src1_i$51
+ wire width 64 input 195 \src1_i$59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 213 \src1_i$74
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 186 \src2_i
+ wire width 64 input 161 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 187 \src2_i$52
+ wire width 64 input 164 \src2_i$30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 188 \src2_i$53
+ wire width 64 input 167 \src2_i$33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 189 \src2_i$54
+ wire width 64 input 170 \src2_i$36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 190 \src2_i$55
+ wire width 64 input 173 \src2_i$39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 191 \src2_i$56
+ wire width 64 input 176 \src2_i$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 192 \src2_i$57
+ wire width 64 input 179 \src2_i$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 193 \src2_i$58
+ wire width 64 input 182 \src2_i$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 216 \src2_i$77
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 218 \src2_i$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 194 \src3_i
+ wire width 64 input 183 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 195 \src3_i$59
+ wire width 64 input 184 \src3_i$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 196 \src3_i$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 286 \xer_so_ok$131
attribute \module_not_derived 1
- attribute \src "libresoc.v:135973.8-136015.4"
+ attribute \src "libresoc.v:135758.8-135800.4"
cell \alu0 \alu0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136016.11-136043.4"
+ attribute \src "libresoc.v:135801.11-135828.4"
cell \branch0 \branch0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src3_i \src3_i$71
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136044.7-136069.4"
+ attribute \src "libresoc.v:135829.7-135854.4"
cell \cr0 \cr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
- connect \src1_i \src1_i$30
- connect \src2_i \src2_i$52
+ connect \src1_i \src1_i$50
+ connect \src2_i \src2_i$30
connect \src3_i \src3_i$67
connect \src4_i \src4_i$68
connect \src5_i \src5_i$72
connect \src6_i \src6_i$73
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136070.8-136109.4"
+ attribute \src "libresoc.v:135855.8-135894.4"
cell \div0 \div0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cr_a_ok \cr_a_ok$112
connect \cu_busy_o \cu_busy_o$17
connect \cu_issue_i \cu_issue_i$16
- connect \cu_rd__go_i \cu_rd__go_i$41
- connect \cu_rd__rel_o \cu_rd__rel_o$40
+ connect \cu_rd__go_i \cu_rd__go_i$38
+ connect \cu_rd__rel_o \cu_rd__rel_o$37
connect \cu_rdmaskn_i \cu_rdmaskn_i$18
connect \cu_wr__go_i \cu_wr__go_i$94
connect \cu_wr__rel_o \cu_wr__rel_o$93
connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc
connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0
connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a
- connect \src1_i \src1_i$42
- connect \src2_i \src2_i$55
+ connect \src1_i \src1_i$56
+ connect \src2_i \src2_i$39
connect \src3_i \src3_i$62
connect \xer_ov_ok \xer_ov_ok$125
connect \xer_so_ok \xer_so_ok$130
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136110.9-136164.4"
+ attribute \src "libresoc.v:135895.9-135949.4"
cell \ldst0 \ldst0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cu_ad__rel_o \cu_ad__rel_o
connect \cu_busy_o \cu_busy_o$26
connect \cu_issue_i \cu_issue_i$25
- connect \cu_rd__go_i \cu_rd__go_i$50
- connect \cu_rd__rel_o \cu_rd__rel_o$49
+ connect \cu_rd__go_i \cu_rd__go_i$47
+ connect \cu_rd__rel_o \cu_rd__rel_o$46
connect \cu_rdmaskn_i \cu_rdmaskn_i$27
connect \cu_st__go_i \cu_st__go_i
connect \cu_st__rel_o \cu_st__rel_o
connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc
connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
- connect \src1_i \src1_i$51
- connect \src2_i \src2_i$58
- connect \src3_i \src3_i$59
+ connect \src1_i \src1_i$59
+ connect \src2_i \src2_i$48
+ connect \src3_i \src3_i$49
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136165.12-136200.4"
+ attribute \src "libresoc.v:135950.12-135985.4"
cell \logical0 \logical0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc
connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
- connect \src1_i \src1_i$36
- connect \src2_i \src2_i$54
+ connect \src1_i \src1_i$52
+ connect \src2_i \src2_i$36
connect \src3_i \src3_i$61
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136201.8-136234.4"
+ attribute \src "libresoc.v:135986.8-136019.4"
cell \mul0 \mul0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cr_a_ok \cr_a_ok$113
connect \cu_busy_o \cu_busy_o$20
connect \cu_issue_i \cu_issue_i$19
- connect \cu_rd__go_i \cu_rd__go_i$44
- connect \cu_rd__rel_o \cu_rd__rel_o$43
+ connect \cu_rd__go_i \cu_rd__go_i$41
+ connect \cu_rd__rel_o \cu_rd__rel_o$40
connect \cu_rdmaskn_i \cu_rdmaskn_i$21
connect \cu_wr__go_i \cu_wr__go_i$97
connect \cu_wr__rel_o \cu_wr__rel_o$96
connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok
connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc
connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
- connect \src1_i \src1_i$45
- connect \src2_i \src2_i$56
+ connect \src1_i \src1_i$57
+ connect \src2_i \src2_i$42
connect \src3_i \src3_i$63
connect \xer_ov_ok \xer_ov_ok$126
connect \xer_so_ok \xer_so_ok$131
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136235.13-136273.4"
+ attribute \src "libresoc.v:136020.13-136058.4"
cell \shiftrot0 \shiftrot0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cr_a_ok \cr_a_ok$114
connect \cu_busy_o \cu_busy_o$23
connect \cu_issue_i \cu_issue_i$22
- connect \cu_rd__go_i \cu_rd__go_i$47
- connect \cu_rd__rel_o \cu_rd__rel_o$46
+ connect \cu_rd__go_i \cu_rd__go_i$44
+ connect \cu_rd__rel_o \cu_rd__rel_o$43
connect \cu_rdmaskn_i \cu_rdmaskn_i$24
connect \cu_wr__go_i \cu_wr__go_i$100
connect \cu_wr__rel_o \cu_wr__rel_o$99
connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok
connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc
connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0
- connect \src1_i \src1_i$48
- connect \src2_i \src2_i$57
+ connect \src1_i \src1_i$58
+ connect \src2_i \src2_i$45
connect \src3_i \src3_i
connect \src4_i \src4_i$64
connect \src5_i \src5_i
connect \xer_ca_ok \xer_ca_ok$121
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136274.8-136306.4"
+ attribute \src "libresoc.v:136059.8-136091.4"
cell \spr0 \spr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cu_busy_o \cu_busy_o$14
connect \cu_issue_i \cu_issue_i$13
- connect \cu_rd__go_i \cu_rd__go_i$38
- connect \cu_rd__rel_o \cu_rd__rel_o$37
+ connect \cu_rd__go_i \cu_rd__go_i$54
+ connect \cu_rd__rel_o \cu_rd__rel_o$53
connect \cu_rdmaskn_i \cu_rdmaskn_i$15
connect \cu_wr__go_i \cu_wr__go_i$91
connect \cu_wr__rel_o \cu_wr__rel_o$90
connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
connect \spr1_ok \spr1_ok
- connect \src1_i \src1_i$39
+ connect \src1_i \src1_i$55
connect \src2_i \src2_i$79
connect \src3_i \src3_i$76
connect \src4_i \src4_i
connect \xer_so_ok \xer_so_ok$129
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:136307.9-136340.4"
+ attribute \src "libresoc.v:136092.9-136125.4"
cell \trap0 \trap0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
- connect \src1_i \src1_i$33
- connect \src2_i \src2_i$53
+ connect \src1_i \src1_i$51
+ connect \src2_i \src2_i$33
connect \src3_i \src3_i$75
connect \src4_i \src4_i$78
end
end
-attribute \src "libresoc.v:136345.1-136403.10"
+attribute \src "libresoc.v:136130.1-136188.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l"
attribute \generator "nMigen"
module \idx_l
- attribute \src "libresoc.v:136346.7-136346.20"
+ attribute \src "libresoc.v:136131.7-136131.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:136391.3-136399.6"
- wire $0\q_int$next[0:0]$5466
- attribute \src "libresoc.v:136389.3-136390.27"
+ attribute \src "libresoc.v:136176.3-136184.6"
+ wire $0\q_int$next[0:0]$5441
+ attribute \src "libresoc.v:136174.3-136175.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:136391.3-136399.6"
- wire $1\q_int$next[0:0]$5467
- attribute \src "libresoc.v:136370.7-136370.19"
+ attribute \src "libresoc.v:136176.3-136184.6"
+ wire $1\q_int$next[0:0]$5442
+ attribute \src "libresoc.v:136155.7-136155.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:136381.17-136381.96"
- wire $and$libresoc.v:136381$5456_Y
- attribute \src "libresoc.v:136386.17-136386.96"
- wire $and$libresoc.v:136386$5461_Y
- attribute \src "libresoc.v:136383.18-136383.95"
- wire $not$libresoc.v:136383$5458_Y
- attribute \src "libresoc.v:136385.17-136385.94"
- wire $not$libresoc.v:136385$5460_Y
- attribute \src "libresoc.v:136388.17-136388.94"
- wire $not$libresoc.v:136388$5463_Y
- attribute \src "libresoc.v:136382.18-136382.100"
- wire $or$libresoc.v:136382$5457_Y
- attribute \src "libresoc.v:136384.18-136384.101"
- wire $or$libresoc.v:136384$5459_Y
- attribute \src "libresoc.v:136387.17-136387.99"
- wire $or$libresoc.v:136387$5462_Y
+ attribute \src "libresoc.v:136166.17-136166.96"
+ wire $and$libresoc.v:136166$5431_Y
+ attribute \src "libresoc.v:136171.17-136171.96"
+ wire $and$libresoc.v:136171$5436_Y
+ attribute \src "libresoc.v:136168.18-136168.95"
+ wire $not$libresoc.v:136168$5433_Y
+ attribute \src "libresoc.v:136170.17-136170.94"
+ wire $not$libresoc.v:136170$5435_Y
+ attribute \src "libresoc.v:136173.17-136173.94"
+ wire $not$libresoc.v:136173$5438_Y
+ attribute \src "libresoc.v:136167.18-136167.100"
+ wire $or$libresoc.v:136167$5432_Y
+ attribute \src "libresoc.v:136169.18-136169.101"
+ wire $or$libresoc.v:136169$5434_Y
+ attribute \src "libresoc.v:136172.17-136172.99"
+ wire $or$libresoc.v:136172$5437_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:136346.7-136346.15"
+ attribute \src "libresoc.v:136131.7-136131.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire output 2 \q_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:136381$5456
+ cell $and $and$libresoc.v:136166$5431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:136381$5456_Y
+ connect \Y $and$libresoc.v:136166$5431_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:136386$5461
+ cell $and $and$libresoc.v:136171$5436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:136386$5461_Y
+ connect \Y $and$libresoc.v:136171$5436_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:136383$5458
+ cell $not $not$libresoc.v:136168$5433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_idx_l
- connect \Y $not$libresoc.v:136383$5458_Y
+ connect \Y $not$libresoc.v:136168$5433_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:136385$5460
+ cell $not $not$libresoc.v:136170$5435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_idx_l
- connect \Y $not$libresoc.v:136385$5460_Y
+ connect \Y $not$libresoc.v:136170$5435_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:136388$5463
+ cell $not $not$libresoc.v:136173$5438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_idx_l
- connect \Y $not$libresoc.v:136388$5463_Y
+ connect \Y $not$libresoc.v:136173$5438_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:136382$5457
+ cell $or $or$libresoc.v:136167$5432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_idx_l
- connect \Y $or$libresoc.v:136382$5457_Y
+ connect \Y $or$libresoc.v:136167$5432_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:136384$5459
+ cell $or $or$libresoc.v:136169$5434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_idx_l
connect \B \q_int
- connect \Y $or$libresoc.v:136384$5459_Y
+ connect \Y $or$libresoc.v:136169$5434_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:136387$5462
+ cell $or $or$libresoc.v:136172$5437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_idx_l
- connect \Y $or$libresoc.v:136387$5462_Y
+ connect \Y $or$libresoc.v:136172$5437_Y
end
- attribute \src "libresoc.v:136346.7-136346.20"
- process $proc$libresoc.v:136346$5468
+ attribute \src "libresoc.v:136131.7-136131.20"
+ process $proc$libresoc.v:136131$5443
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:136370.7-136370.19"
- process $proc$libresoc.v:136370$5469
+ attribute \src "libresoc.v:136155.7-136155.19"
+ process $proc$libresoc.v:136155$5444
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:136389.3-136390.27"
- process $proc$libresoc.v:136389$5464
+ attribute \src "libresoc.v:136174.3-136175.27"
+ process $proc$libresoc.v:136174$5439
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:136391.3-136399.6"
- process $proc$libresoc.v:136391$5465
+ attribute \src "libresoc.v:136176.3-136184.6"
+ process $proc$libresoc.v:136176$5440
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$5466 $1\q_int$next[0:0]$5467
- attribute \src "libresoc.v:136392.5-136392.29"
+ assign $0\q_int$next[0:0]$5441 $1\q_int$next[0:0]$5442
+ attribute \src "libresoc.v:136177.5-136177.29"
switch \initial
- attribute \src "libresoc.v:136392.9-136392.17"
+ attribute \src "libresoc.v:136177.9-136177.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$5467 1'0
+ assign $1\q_int$next[0:0]$5442 1'0
case
- assign $1\q_int$next[0:0]$5467 \$5
+ assign $1\q_int$next[0:0]$5442 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$5466
+ update \q_int$next $0\q_int$next[0:0]$5441
end
- connect \$9 $and$libresoc.v:136381$5456_Y
- connect \$11 $or$libresoc.v:136382$5457_Y
- connect \$13 $not$libresoc.v:136383$5458_Y
- connect \$15 $or$libresoc.v:136384$5459_Y
- connect \$1 $not$libresoc.v:136385$5460_Y
- connect \$3 $and$libresoc.v:136386$5461_Y
- connect \$5 $or$libresoc.v:136387$5462_Y
- connect \$7 $not$libresoc.v:136388$5463_Y
+ connect \$9 $and$libresoc.v:136166$5431_Y
+ connect \$11 $or$libresoc.v:136167$5432_Y
+ connect \$13 $not$libresoc.v:136168$5433_Y
+ connect \$15 $or$libresoc.v:136169$5434_Y
+ connect \$1 $not$libresoc.v:136170$5435_Y
+ connect \$3 $and$libresoc.v:136171$5436_Y
+ connect \$5 $or$libresoc.v:136172$5437_Y
+ connect \$7 $not$libresoc.v:136173$5438_Y
connect \qlq_idx_l \$15
connect \qn_idx_l \$13
connect \q_idx_l \$11
end
-attribute \src "libresoc.v:136407.1-136786.10"
+attribute \src "libresoc.v:136192.1-136571.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.imem"
attribute \generator "nMigen"
module \imem
- attribute \src "libresoc.v:136738.3-136747.6"
+ attribute \src "libresoc.v:136523.3-136532.6"
wire $0\a_busy_o[0:0]
- attribute \src "libresoc.v:136718.3-136737.6"
- wire width 45 $0\f_badaddr_o$next[44:0]$5538
- attribute \src "libresoc.v:136549.3-136550.39"
+ attribute \src "libresoc.v:136503.3-136522.6"
+ wire width 45 $0\f_badaddr_o$next[44:0]$5513
+ attribute \src "libresoc.v:136334.3-136335.39"
wire width 45 $0\f_badaddr_o[44:0]
- attribute \src "libresoc.v:136748.3-136765.6"
+ attribute \src "libresoc.v:136533.3-136550.6"
wire $0\f_busy_o[0:0]
- attribute \src "libresoc.v:136695.3-136717.6"
- wire $0\f_fetch_err_o$next[0:0]$5533
- attribute \src "libresoc.v:136551.3-136552.43"
+ attribute \src "libresoc.v:136480.3-136502.6"
+ wire $0\f_fetch_err_o$next[0:0]$5508
+ attribute \src "libresoc.v:136336.3-136337.43"
wire $0\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:136766.3-136783.6"
+ attribute \src "libresoc.v:136551.3-136568.6"
wire width 64 $0\f_instr_o[63:0]
- attribute \src "libresoc.v:136672.3-136694.6"
- wire width 45 $0\ibus__adr$next[44:0]$5528
- attribute \src "libresoc.v:136553.3-136554.35"
+ attribute \src "libresoc.v:136457.3-136479.6"
+ wire width 45 $0\ibus__adr$next[44:0]$5503
+ attribute \src "libresoc.v:136338.3-136339.35"
wire width 45 $0\ibus__adr[44:0]
- attribute \src "libresoc.v:136563.3-136590.6"
- wire $0\ibus__cyc$next[0:0]$5504
- attribute \src "libresoc.v:136561.3-136562.35"
+ attribute \src "libresoc.v:136348.3-136375.6"
+ wire $0\ibus__cyc$next[0:0]$5479
+ attribute \src "libresoc.v:136346.3-136347.35"
wire $0\ibus__cyc[0:0]
- attribute \src "libresoc.v:136619.3-136646.6"
- wire width 8 $0\ibus__sel$next[7:0]$5516
- attribute \src "libresoc.v:136557.3-136558.35"
+ attribute \src "libresoc.v:136404.3-136431.6"
+ wire width 8 $0\ibus__sel$next[7:0]$5491
+ attribute \src "libresoc.v:136342.3-136343.35"
wire width 8 $0\ibus__sel[7:0]
- attribute \src "libresoc.v:136591.3-136618.6"
- wire $0\ibus__stb$next[0:0]$5510
- attribute \src "libresoc.v:136559.3-136560.35"
+ attribute \src "libresoc.v:136376.3-136403.6"
+ wire $0\ibus__stb$next[0:0]$5485
+ attribute \src "libresoc.v:136344.3-136345.35"
wire $0\ibus__stb[0:0]
- attribute \src "libresoc.v:136647.3-136671.6"
- wire width 64 $0\ibus_rdata$next[63:0]$5522
- attribute \src "libresoc.v:136555.3-136556.37"
+ attribute \src "libresoc.v:136432.3-136456.6"
+ wire width 64 $0\ibus_rdata$next[63:0]$5497
+ attribute \src "libresoc.v:136340.3-136341.37"
wire width 64 $0\ibus_rdata[63:0]
- attribute \src "libresoc.v:136408.7-136408.20"
+ attribute \src "libresoc.v:136193.7-136193.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:136738.3-136747.6"
+ attribute \src "libresoc.v:136523.3-136532.6"
wire $1\a_busy_o[0:0]
- attribute \src "libresoc.v:136718.3-136737.6"
- wire width 45 $1\f_badaddr_o$next[44:0]$5539
- attribute \src "libresoc.v:136472.14-136472.44"
+ attribute \src "libresoc.v:136503.3-136522.6"
+ wire width 45 $1\f_badaddr_o$next[44:0]$5514
+ attribute \src "libresoc.v:136257.14-136257.44"
wire width 45 $1\f_badaddr_o[44:0]
- attribute \src "libresoc.v:136748.3-136765.6"
+ attribute \src "libresoc.v:136533.3-136550.6"
wire $1\f_busy_o[0:0]
- attribute \src "libresoc.v:136695.3-136717.6"
- wire $1\f_fetch_err_o$next[0:0]$5534
- attribute \src "libresoc.v:136479.7-136479.27"
+ attribute \src "libresoc.v:136480.3-136502.6"
+ wire $1\f_fetch_err_o$next[0:0]$5509
+ attribute \src "libresoc.v:136264.7-136264.27"
wire $1\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:136766.3-136783.6"
+ attribute \src "libresoc.v:136551.3-136568.6"
wire width 64 $1\f_instr_o[63:0]
- attribute \src "libresoc.v:136672.3-136694.6"
- wire width 45 $1\ibus__adr$next[44:0]$5529
- attribute \src "libresoc.v:136493.14-136493.42"
+ attribute \src "libresoc.v:136457.3-136479.6"
+ wire width 45 $1\ibus__adr$next[44:0]$5504
+ attribute \src "libresoc.v:136278.14-136278.42"
wire width 45 $1\ibus__adr[44:0]
- attribute \src "libresoc.v:136563.3-136590.6"
- wire $1\ibus__cyc$next[0:0]$5505
- attribute \src "libresoc.v:136498.7-136498.23"
+ attribute \src "libresoc.v:136348.3-136375.6"
+ wire $1\ibus__cyc$next[0:0]$5480
+ attribute \src "libresoc.v:136283.7-136283.23"
wire $1\ibus__cyc[0:0]
- attribute \src "libresoc.v:136619.3-136646.6"
- wire width 8 $1\ibus__sel$next[7:0]$5517
- attribute \src "libresoc.v:136507.13-136507.30"
+ attribute \src "libresoc.v:136404.3-136431.6"
+ wire width 8 $1\ibus__sel$next[7:0]$5492
+ attribute \src "libresoc.v:136292.13-136292.30"
wire width 8 $1\ibus__sel[7:0]
- attribute \src "libresoc.v:136591.3-136618.6"
- wire $1\ibus__stb$next[0:0]$5511
- attribute \src "libresoc.v:136512.7-136512.23"
+ attribute \src "libresoc.v:136376.3-136403.6"
+ wire $1\ibus__stb$next[0:0]$5486
+ attribute \src "libresoc.v:136297.7-136297.23"
wire $1\ibus__stb[0:0]
- attribute \src "libresoc.v:136647.3-136671.6"
- wire width 64 $1\ibus_rdata$next[63:0]$5523
- attribute \src "libresoc.v:136516.14-136516.47"
+ attribute \src "libresoc.v:136432.3-136456.6"
+ wire width 64 $1\ibus_rdata$next[63:0]$5498
+ attribute \src "libresoc.v:136301.14-136301.47"
wire width 64 $1\ibus_rdata[63:0]
- attribute \src "libresoc.v:136718.3-136737.6"
- wire width 45 $2\f_badaddr_o$next[44:0]$5540
- attribute \src "libresoc.v:136748.3-136765.6"
+ attribute \src "libresoc.v:136503.3-136522.6"
+ wire width 45 $2\f_badaddr_o$next[44:0]$5515
+ attribute \src "libresoc.v:136533.3-136550.6"
wire $2\f_busy_o[0:0]
- attribute \src "libresoc.v:136695.3-136717.6"
- wire $2\f_fetch_err_o$next[0:0]$5535
- attribute \src "libresoc.v:136766.3-136783.6"
+ attribute \src "libresoc.v:136480.3-136502.6"
+ wire $2\f_fetch_err_o$next[0:0]$5510
+ attribute \src "libresoc.v:136551.3-136568.6"
wire width 64 $2\f_instr_o[63:0]
- attribute \src "libresoc.v:136672.3-136694.6"
- wire width 45 $2\ibus__adr$next[44:0]$5530
- attribute \src "libresoc.v:136563.3-136590.6"
- wire $2\ibus__cyc$next[0:0]$5506
- attribute \src "libresoc.v:136619.3-136646.6"
- wire width 8 $2\ibus__sel$next[7:0]$5518
- attribute \src "libresoc.v:136591.3-136618.6"
- wire $2\ibus__stb$next[0:0]$5512
- attribute \src "libresoc.v:136647.3-136671.6"
- wire width 64 $2\ibus_rdata$next[63:0]$5524
- attribute \src "libresoc.v:136718.3-136737.6"
- wire width 45 $3\f_badaddr_o$next[44:0]$5541
- attribute \src "libresoc.v:136695.3-136717.6"
- wire $3\f_fetch_err_o$next[0:0]$5536
- attribute \src "libresoc.v:136672.3-136694.6"
- wire width 45 $3\ibus__adr$next[44:0]$5531
- attribute \src "libresoc.v:136563.3-136590.6"
- wire $3\ibus__cyc$next[0:0]$5507
- attribute \src "libresoc.v:136619.3-136646.6"
- wire width 8 $3\ibus__sel$next[7:0]$5519
- attribute \src "libresoc.v:136591.3-136618.6"
- wire $3\ibus__stb$next[0:0]$5513
- attribute \src "libresoc.v:136647.3-136671.6"
- wire width 64 $3\ibus_rdata$next[63:0]$5525
- attribute \src "libresoc.v:136563.3-136590.6"
- wire $4\ibus__cyc$next[0:0]$5508
- attribute \src "libresoc.v:136619.3-136646.6"
- wire width 8 $4\ibus__sel$next[7:0]$5520
- attribute \src "libresoc.v:136591.3-136618.6"
- wire $4\ibus__stb$next[0:0]$5514
- attribute \src "libresoc.v:136647.3-136671.6"
- wire width 64 $4\ibus_rdata$next[63:0]$5526
- attribute \src "libresoc.v:136525.18-136525.110"
- wire $and$libresoc.v:136525$5472_Y
- attribute \src "libresoc.v:136531.18-136531.110"
- wire $and$libresoc.v:136531$5478_Y
- attribute \src "libresoc.v:136536.18-136536.110"
- wire $and$libresoc.v:136536$5483_Y
- attribute \src "libresoc.v:136539.17-136539.108"
- wire $and$libresoc.v:136539$5486_Y
- attribute \src "libresoc.v:136542.18-136542.110"
- wire $and$libresoc.v:136542$5489_Y
- attribute \src "libresoc.v:136543.18-136543.115"
- wire $and$libresoc.v:136543$5490_Y
- attribute \src "libresoc.v:136545.18-136545.115"
- wire $and$libresoc.v:136545$5492_Y
- attribute \src "libresoc.v:136524.18-136524.105"
- wire $not$libresoc.v:136524$5471_Y
- attribute \src "libresoc.v:136527.18-136527.105"
- wire $not$libresoc.v:136527$5474_Y
- attribute \src "libresoc.v:136528.17-136528.104"
- wire $not$libresoc.v:136528$5475_Y
- attribute \src "libresoc.v:136530.18-136530.105"
- wire $not$libresoc.v:136530$5477_Y
- attribute \src "libresoc.v:136533.18-136533.105"
- wire $not$libresoc.v:136533$5480_Y
- attribute \src "libresoc.v:136535.18-136535.105"
- wire $not$libresoc.v:136535$5482_Y
- attribute \src "libresoc.v:136538.18-136538.105"
- wire $not$libresoc.v:136538$5485_Y
- attribute \src "libresoc.v:136541.18-136541.105"
- wire $not$libresoc.v:136541$5488_Y
- attribute \src "libresoc.v:136544.18-136544.105"
- wire $not$libresoc.v:136544$5491_Y
- attribute \src "libresoc.v:136546.18-136546.105"
- wire $not$libresoc.v:136546$5493_Y
- attribute \src "libresoc.v:136548.17-136548.104"
- wire $not$libresoc.v:136548$5495_Y
- attribute \src "libresoc.v:136523.17-136523.103"
- wire $or$libresoc.v:136523$5470_Y
- attribute \src "libresoc.v:136526.18-136526.115"
- wire $or$libresoc.v:136526$5473_Y
- attribute \src "libresoc.v:136529.18-136529.106"
- wire $or$libresoc.v:136529$5476_Y
- attribute \src "libresoc.v:136532.18-136532.115"
- wire $or$libresoc.v:136532$5479_Y
- attribute \src "libresoc.v:136534.18-136534.106"
- wire $or$libresoc.v:136534$5481_Y
- attribute \src "libresoc.v:136537.18-136537.115"
- wire $or$libresoc.v:136537$5484_Y
- attribute \src "libresoc.v:136540.18-136540.106"
- wire $or$libresoc.v:136540$5487_Y
- attribute \src "libresoc.v:136547.17-136547.114"
- wire $or$libresoc.v:136547$5494_Y
+ attribute \src "libresoc.v:136457.3-136479.6"
+ wire width 45 $2\ibus__adr$next[44:0]$5505
+ attribute \src "libresoc.v:136348.3-136375.6"
+ wire $2\ibus__cyc$next[0:0]$5481
+ attribute \src "libresoc.v:136404.3-136431.6"
+ wire width 8 $2\ibus__sel$next[7:0]$5493
+ attribute \src "libresoc.v:136376.3-136403.6"
+ wire $2\ibus__stb$next[0:0]$5487
+ attribute \src "libresoc.v:136432.3-136456.6"
+ wire width 64 $2\ibus_rdata$next[63:0]$5499
+ attribute \src "libresoc.v:136503.3-136522.6"
+ wire width 45 $3\f_badaddr_o$next[44:0]$5516
+ attribute \src "libresoc.v:136480.3-136502.6"
+ wire $3\f_fetch_err_o$next[0:0]$5511
+ attribute \src "libresoc.v:136457.3-136479.6"
+ wire width 45 $3\ibus__adr$next[44:0]$5506
+ attribute \src "libresoc.v:136348.3-136375.6"
+ wire $3\ibus__cyc$next[0:0]$5482
+ attribute \src "libresoc.v:136404.3-136431.6"
+ wire width 8 $3\ibus__sel$next[7:0]$5494
+ attribute \src "libresoc.v:136376.3-136403.6"
+ wire $3\ibus__stb$next[0:0]$5488
+ attribute \src "libresoc.v:136432.3-136456.6"
+ wire width 64 $3\ibus_rdata$next[63:0]$5500
+ attribute \src "libresoc.v:136348.3-136375.6"
+ wire $4\ibus__cyc$next[0:0]$5483
+ attribute \src "libresoc.v:136404.3-136431.6"
+ wire width 8 $4\ibus__sel$next[7:0]$5495
+ attribute \src "libresoc.v:136376.3-136403.6"
+ wire $4\ibus__stb$next[0:0]$5489
+ attribute \src "libresoc.v:136432.3-136456.6"
+ wire width 64 $4\ibus_rdata$next[63:0]$5501
+ attribute \src "libresoc.v:136310.18-136310.110"
+ wire $and$libresoc.v:136310$5447_Y
+ attribute \src "libresoc.v:136316.18-136316.110"
+ wire $and$libresoc.v:136316$5453_Y
+ attribute \src "libresoc.v:136321.18-136321.110"
+ wire $and$libresoc.v:136321$5458_Y
+ attribute \src "libresoc.v:136324.17-136324.108"
+ wire $and$libresoc.v:136324$5461_Y
+ attribute \src "libresoc.v:136327.18-136327.110"
+ wire $and$libresoc.v:136327$5464_Y
+ attribute \src "libresoc.v:136328.18-136328.115"
+ wire $and$libresoc.v:136328$5465_Y
+ attribute \src "libresoc.v:136330.18-136330.115"
+ wire $and$libresoc.v:136330$5467_Y
+ attribute \src "libresoc.v:136309.18-136309.105"
+ wire $not$libresoc.v:136309$5446_Y
+ attribute \src "libresoc.v:136312.18-136312.105"
+ wire $not$libresoc.v:136312$5449_Y
+ attribute \src "libresoc.v:136313.17-136313.104"
+ wire $not$libresoc.v:136313$5450_Y
+ attribute \src "libresoc.v:136315.18-136315.105"
+ wire $not$libresoc.v:136315$5452_Y
+ attribute \src "libresoc.v:136318.18-136318.105"
+ wire $not$libresoc.v:136318$5455_Y
+ attribute \src "libresoc.v:136320.18-136320.105"
+ wire $not$libresoc.v:136320$5457_Y
+ attribute \src "libresoc.v:136323.18-136323.105"
+ wire $not$libresoc.v:136323$5460_Y
+ attribute \src "libresoc.v:136326.18-136326.105"
+ wire $not$libresoc.v:136326$5463_Y
+ attribute \src "libresoc.v:136329.18-136329.105"
+ wire $not$libresoc.v:136329$5466_Y
+ attribute \src "libresoc.v:136331.18-136331.105"
+ wire $not$libresoc.v:136331$5468_Y
+ attribute \src "libresoc.v:136333.17-136333.104"
+ wire $not$libresoc.v:136333$5470_Y
+ attribute \src "libresoc.v:136308.17-136308.103"
+ wire $or$libresoc.v:136308$5445_Y
+ attribute \src "libresoc.v:136311.18-136311.115"
+ wire $or$libresoc.v:136311$5448_Y
+ attribute \src "libresoc.v:136314.18-136314.106"
+ wire $or$libresoc.v:136314$5451_Y
+ attribute \src "libresoc.v:136317.18-136317.115"
+ wire $or$libresoc.v:136317$5454_Y
+ attribute \src "libresoc.v:136319.18-136319.106"
+ wire $or$libresoc.v:136319$5456_Y
+ attribute \src "libresoc.v:136322.18-136322.115"
+ wire $or$libresoc.v:136322$5459_Y
+ attribute \src "libresoc.v:136325.18-136325.106"
+ wire $or$libresoc.v:136325$5462_Y
+ attribute \src "libresoc.v:136332.17-136332.114"
+ wire $or$libresoc.v:136332$5469_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
wire \a_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
wire input 3 \a_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 15 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
wire width 45 \f_badaddr_o
wire width 64 \ibus_rdata
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69"
wire width 64 \ibus_rdata$next
- attribute \src "libresoc.v:136408.7-136408.15"
+ attribute \src "libresoc.v:136193.7-136193.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire input 7 \wb_icache_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:136525$5472
+ cell $and $and$libresoc.v:136310$5447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$11
- connect \Y $and$libresoc.v:136525$5472_Y
+ connect \Y $and$libresoc.v:136310$5447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:136531$5478
+ cell $and $and$libresoc.v:136316$5453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$21
- connect \Y $and$libresoc.v:136531$5478_Y
+ connect \Y $and$libresoc.v:136316$5453_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:136536$5483
+ cell $and $and$libresoc.v:136321$5458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$31
- connect \Y $and$libresoc.v:136536$5483_Y
+ connect \Y $and$libresoc.v:136321$5458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:136539$5486
+ cell $and $and$libresoc.v:136324$5461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$1
- connect \Y $and$libresoc.v:136539$5486_Y
+ connect \Y $and$libresoc.v:136324$5461_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:136542$5489
+ cell $and $and$libresoc.v:136327$5464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$41
- connect \Y $and$libresoc.v:136542$5489_Y
+ connect \Y $and$libresoc.v:136327$5464_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
- cell $and $and$libresoc.v:136543$5490
+ cell $and $and$libresoc.v:136328$5465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:136543$5490_Y
+ connect \Y $and$libresoc.v:136328$5465_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
- cell $and $and$libresoc.v:136545$5492
+ cell $and $and$libresoc.v:136330$5467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:136545$5492_Y
+ connect \Y $and$libresoc.v:136330$5467_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:136524$5471
+ cell $not $not$libresoc.v:136309$5446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:136524$5471_Y
+ connect \Y $not$libresoc.v:136309$5446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:136527$5474
+ cell $not $not$libresoc.v:136312$5449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:136527$5474_Y
+ connect \Y $not$libresoc.v:136312$5449_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:136528$5475
+ cell $not $not$libresoc.v:136313$5450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:136528$5475_Y
+ connect \Y $not$libresoc.v:136313$5450_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:136530$5477
+ cell $not $not$libresoc.v:136315$5452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:136530$5477_Y
+ connect \Y $not$libresoc.v:136315$5452_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:136533$5480
+ cell $not $not$libresoc.v:136318$5455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:136533$5480_Y
+ connect \Y $not$libresoc.v:136318$5455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:136535$5482
+ cell $not $not$libresoc.v:136320$5457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:136535$5482_Y
+ connect \Y $not$libresoc.v:136320$5457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:136538$5485
+ cell $not $not$libresoc.v:136323$5460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:136538$5485_Y
+ connect \Y $not$libresoc.v:136323$5460_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:136541$5488
+ cell $not $not$libresoc.v:136326$5463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:136541$5488_Y
+ connect \Y $not$libresoc.v:136326$5463_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
- cell $not $not$libresoc.v:136544$5491
+ cell $not $not$libresoc.v:136329$5466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:136544$5491_Y
+ connect \Y $not$libresoc.v:136329$5466_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
- cell $not $not$libresoc.v:136546$5493
+ cell $not $not$libresoc.v:136331$5468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:136546$5493_Y
+ connect \Y $not$libresoc.v:136331$5468_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:136548$5495
+ cell $not $not$libresoc.v:136333$5470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:136548$5495_Y
+ connect \Y $not$libresoc.v:136333$5470_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136523$5470
+ cell $or $or$libresoc.v:136308$5445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $or$libresoc.v:136523$5470_Y
+ connect \Y $or$libresoc.v:136308$5445_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136526$5473
+ cell $or $or$libresoc.v:136311$5448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:136526$5473_Y
+ connect \Y $or$libresoc.v:136311$5448_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136529$5476
+ cell $or $or$libresoc.v:136314$5451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \$17
- connect \Y $or$libresoc.v:136529$5476_Y
+ connect \Y $or$libresoc.v:136314$5451_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136532$5479
+ cell $or $or$libresoc.v:136317$5454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:136532$5479_Y
+ connect \Y $or$libresoc.v:136317$5454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136534$5481
+ cell $or $or$libresoc.v:136319$5456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$25
connect \B \$27
- connect \Y $or$libresoc.v:136534$5481_Y
+ connect \Y $or$libresoc.v:136319$5456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136537$5484
+ cell $or $or$libresoc.v:136322$5459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:136537$5484_Y
+ connect \Y $or$libresoc.v:136322$5459_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136540$5487
+ cell $or $or$libresoc.v:136325$5462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$35
connect \B \$37
- connect \Y $or$libresoc.v:136540$5487_Y
+ connect \Y $or$libresoc.v:136325$5462_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:136547$5494
+ cell $or $or$libresoc.v:136332$5469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:136547$5494_Y
+ connect \Y $or$libresoc.v:136332$5469_Y
end
- attribute \src "libresoc.v:136408.7-136408.20"
- process $proc$libresoc.v:136408$5545
+ attribute \src "libresoc.v:136193.7-136193.20"
+ process $proc$libresoc.v:136193$5520
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:136472.14-136472.44"
- process $proc$libresoc.v:136472$5546
+ attribute \src "libresoc.v:136257.14-136257.44"
+ process $proc$libresoc.v:136257$5521
assign { } { }
assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \f_badaddr_o $1\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:136479.7-136479.27"
- process $proc$libresoc.v:136479$5547
+ attribute \src "libresoc.v:136264.7-136264.27"
+ process $proc$libresoc.v:136264$5522
assign { } { }
assign $1\f_fetch_err_o[0:0] 1'0
sync always
sync init
update \f_fetch_err_o $1\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:136493.14-136493.42"
- process $proc$libresoc.v:136493$5548
+ attribute \src "libresoc.v:136278.14-136278.42"
+ process $proc$libresoc.v:136278$5523
assign { } { }
assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \ibus__adr $1\ibus__adr[44:0]
end
- attribute \src "libresoc.v:136498.7-136498.23"
- process $proc$libresoc.v:136498$5549
+ attribute \src "libresoc.v:136283.7-136283.23"
+ process $proc$libresoc.v:136283$5524
assign { } { }
assign $1\ibus__cyc[0:0] 1'0
sync always
sync init
update \ibus__cyc $1\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:136507.13-136507.30"
- process $proc$libresoc.v:136507$5550
+ attribute \src "libresoc.v:136292.13-136292.30"
+ process $proc$libresoc.v:136292$5525
assign { } { }
assign $1\ibus__sel[7:0] 8'00000000
sync always
sync init
update \ibus__sel $1\ibus__sel[7:0]
end
- attribute \src "libresoc.v:136512.7-136512.23"
- process $proc$libresoc.v:136512$5551
+ attribute \src "libresoc.v:136297.7-136297.23"
+ process $proc$libresoc.v:136297$5526
assign { } { }
assign $1\ibus__stb[0:0] 1'0
sync always
sync init
update \ibus__stb $1\ibus__stb[0:0]
end
- attribute \src "libresoc.v:136516.14-136516.47"
- process $proc$libresoc.v:136516$5552
+ attribute \src "libresoc.v:136301.14-136301.47"
+ process $proc$libresoc.v:136301$5527
assign { } { }
assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ibus_rdata $1\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:136549.3-136550.39"
- process $proc$libresoc.v:136549$5496
+ attribute \src "libresoc.v:136334.3-136335.39"
+ process $proc$libresoc.v:136334$5471
assign { } { }
assign $0\f_badaddr_o[44:0] \f_badaddr_o$next
sync posedge \clk
update \f_badaddr_o $0\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:136551.3-136552.43"
- process $proc$libresoc.v:136551$5497
+ attribute \src "libresoc.v:136336.3-136337.43"
+ process $proc$libresoc.v:136336$5472
assign { } { }
assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next
sync posedge \clk
update \f_fetch_err_o $0\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:136553.3-136554.35"
- process $proc$libresoc.v:136553$5498
+ attribute \src "libresoc.v:136338.3-136339.35"
+ process $proc$libresoc.v:136338$5473
assign { } { }
assign $0\ibus__adr[44:0] \ibus__adr$next
sync posedge \clk
update \ibus__adr $0\ibus__adr[44:0]
end
- attribute \src "libresoc.v:136555.3-136556.37"
- process $proc$libresoc.v:136555$5499
+ attribute \src "libresoc.v:136340.3-136341.37"
+ process $proc$libresoc.v:136340$5474
assign { } { }
assign $0\ibus_rdata[63:0] \ibus_rdata$next
sync posedge \clk
update \ibus_rdata $0\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:136557.3-136558.35"
- process $proc$libresoc.v:136557$5500
+ attribute \src "libresoc.v:136342.3-136343.35"
+ process $proc$libresoc.v:136342$5475
assign { } { }
assign $0\ibus__sel[7:0] \ibus__sel$next
sync posedge \clk
update \ibus__sel $0\ibus__sel[7:0]
end
- attribute \src "libresoc.v:136559.3-136560.35"
- process $proc$libresoc.v:136559$5501
+ attribute \src "libresoc.v:136344.3-136345.35"
+ process $proc$libresoc.v:136344$5476
assign { } { }
assign $0\ibus__stb[0:0] \ibus__stb$next
sync posedge \clk
update \ibus__stb $0\ibus__stb[0:0]
end
- attribute \src "libresoc.v:136561.3-136562.35"
- process $proc$libresoc.v:136561$5502
+ attribute \src "libresoc.v:136346.3-136347.35"
+ process $proc$libresoc.v:136346$5477
assign { } { }
assign $0\ibus__cyc[0:0] \ibus__cyc$next
sync posedge \clk
update \ibus__cyc $0\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:136563.3-136590.6"
- process $proc$libresoc.v:136563$5503
+ attribute \src "libresoc.v:136348.3-136375.6"
+ process $proc$libresoc.v:136348$5478
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__cyc$next[0:0]$5504 $4\ibus__cyc$next[0:0]$5508
- attribute \src "libresoc.v:136564.5-136564.29"
+ assign $0\ibus__cyc$next[0:0]$5479 $4\ibus__cyc$next[0:0]$5483
+ attribute \src "libresoc.v:136349.5-136349.29"
switch \initial
- attribute \src "libresoc.v:136564.9-136564.17"
+ attribute \src "libresoc.v:136349.9-136349.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__cyc$next[0:0]$5505 $2\ibus__cyc$next[0:0]$5506
+ assign $1\ibus__cyc$next[0:0]$5480 $2\ibus__cyc$next[0:0]$5481
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$3 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__cyc$next[0:0]$5506 $3\ibus__cyc$next[0:0]$5507
+ assign $2\ibus__cyc$next[0:0]$5481 $3\ibus__cyc$next[0:0]$5482
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__cyc$next[0:0]$5507 1'0
+ assign $3\ibus__cyc$next[0:0]$5482 1'0
case
- assign $3\ibus__cyc$next[0:0]$5507 \ibus__cyc
+ assign $3\ibus__cyc$next[0:0]$5482 \ibus__cyc
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__cyc$next[0:0]$5506 1'1
+ assign $2\ibus__cyc$next[0:0]$5481 1'1
case
- assign $2\ibus__cyc$next[0:0]$5506 \ibus__cyc
+ assign $2\ibus__cyc$next[0:0]$5481 \ibus__cyc
end
case
- assign $1\ibus__cyc$next[0:0]$5505 \ibus__cyc
+ assign $1\ibus__cyc$next[0:0]$5480 \ibus__cyc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__cyc$next[0:0]$5508 1'0
+ assign $4\ibus__cyc$next[0:0]$5483 1'0
case
- assign $4\ibus__cyc$next[0:0]$5508 $1\ibus__cyc$next[0:0]$5505
+ assign $4\ibus__cyc$next[0:0]$5483 $1\ibus__cyc$next[0:0]$5480
end
sync always
- update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5504
+ update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5479
end
- attribute \src "libresoc.v:136591.3-136618.6"
- process $proc$libresoc.v:136591$5509
+ attribute \src "libresoc.v:136376.3-136403.6"
+ process $proc$libresoc.v:136376$5484
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__stb$next[0:0]$5510 $4\ibus__stb$next[0:0]$5514
- attribute \src "libresoc.v:136592.5-136592.29"
+ assign $0\ibus__stb$next[0:0]$5485 $4\ibus__stb$next[0:0]$5489
+ attribute \src "libresoc.v:136377.5-136377.29"
switch \initial
- attribute \src "libresoc.v:136592.9-136592.17"
+ attribute \src "libresoc.v:136377.9-136377.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__stb$next[0:0]$5511 $2\ibus__stb$next[0:0]$5512
+ assign $1\ibus__stb$next[0:0]$5486 $2\ibus__stb$next[0:0]$5487
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$13 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__stb$next[0:0]$5512 $3\ibus__stb$next[0:0]$5513
+ assign $2\ibus__stb$next[0:0]$5487 $3\ibus__stb$next[0:0]$5488
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__stb$next[0:0]$5513 1'0
+ assign $3\ibus__stb$next[0:0]$5488 1'0
case
- assign $3\ibus__stb$next[0:0]$5513 \ibus__stb
+ assign $3\ibus__stb$next[0:0]$5488 \ibus__stb
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__stb$next[0:0]$5512 1'1
+ assign $2\ibus__stb$next[0:0]$5487 1'1
case
- assign $2\ibus__stb$next[0:0]$5512 \ibus__stb
+ assign $2\ibus__stb$next[0:0]$5487 \ibus__stb
end
case
- assign $1\ibus__stb$next[0:0]$5511 \ibus__stb
+ assign $1\ibus__stb$next[0:0]$5486 \ibus__stb
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__stb$next[0:0]$5514 1'0
+ assign $4\ibus__stb$next[0:0]$5489 1'0
case
- assign $4\ibus__stb$next[0:0]$5514 $1\ibus__stb$next[0:0]$5511
+ assign $4\ibus__stb$next[0:0]$5489 $1\ibus__stb$next[0:0]$5486
end
sync always
- update \ibus__stb$next $0\ibus__stb$next[0:0]$5510
+ update \ibus__stb$next $0\ibus__stb$next[0:0]$5485
end
- attribute \src "libresoc.v:136619.3-136646.6"
- process $proc$libresoc.v:136619$5515
+ attribute \src "libresoc.v:136404.3-136431.6"
+ process $proc$libresoc.v:136404$5490
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__sel$next[7:0]$5516 $4\ibus__sel$next[7:0]$5520
- attribute \src "libresoc.v:136620.5-136620.29"
+ assign $0\ibus__sel$next[7:0]$5491 $4\ibus__sel$next[7:0]$5495
+ attribute \src "libresoc.v:136405.5-136405.29"
switch \initial
- attribute \src "libresoc.v:136620.9-136620.17"
+ attribute \src "libresoc.v:136405.9-136405.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__sel$next[7:0]$5517 $2\ibus__sel$next[7:0]$5518
+ assign $1\ibus__sel$next[7:0]$5492 $2\ibus__sel$next[7:0]$5493
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$23 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__sel$next[7:0]$5518 $3\ibus__sel$next[7:0]$5519
+ assign $2\ibus__sel$next[7:0]$5493 $3\ibus__sel$next[7:0]$5494
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$29
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__sel$next[7:0]$5519 8'00000000
+ assign $3\ibus__sel$next[7:0]$5494 8'00000000
case
- assign $3\ibus__sel$next[7:0]$5519 \ibus__sel
+ assign $3\ibus__sel$next[7:0]$5494 \ibus__sel
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__sel$next[7:0]$5518 8'11111111
+ assign $2\ibus__sel$next[7:0]$5493 8'11111111
case
- assign $2\ibus__sel$next[7:0]$5518 \ibus__sel
+ assign $2\ibus__sel$next[7:0]$5493 \ibus__sel
end
case
- assign $1\ibus__sel$next[7:0]$5517 \ibus__sel
+ assign $1\ibus__sel$next[7:0]$5492 \ibus__sel
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__sel$next[7:0]$5520 8'00000000
+ assign $4\ibus__sel$next[7:0]$5495 8'00000000
case
- assign $4\ibus__sel$next[7:0]$5520 $1\ibus__sel$next[7:0]$5517
+ assign $4\ibus__sel$next[7:0]$5495 $1\ibus__sel$next[7:0]$5492
end
sync always
- update \ibus__sel$next $0\ibus__sel$next[7:0]$5516
+ update \ibus__sel$next $0\ibus__sel$next[7:0]$5491
end
- attribute \src "libresoc.v:136647.3-136671.6"
- process $proc$libresoc.v:136647$5521
+ attribute \src "libresoc.v:136432.3-136456.6"
+ process $proc$libresoc.v:136432$5496
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus_rdata$next[63:0]$5522 $4\ibus_rdata$next[63:0]$5526
- attribute \src "libresoc.v:136648.5-136648.29"
+ assign $0\ibus_rdata$next[63:0]$5497 $4\ibus_rdata$next[63:0]$5501
+ attribute \src "libresoc.v:136433.5-136433.29"
switch \initial
- attribute \src "libresoc.v:136648.9-136648.17"
+ attribute \src "libresoc.v:136433.9-136433.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus_rdata$next[63:0]$5523 $2\ibus_rdata$next[63:0]$5524
+ assign $1\ibus_rdata$next[63:0]$5498 $2\ibus_rdata$next[63:0]$5499
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$33 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus_rdata$next[63:0]$5524 $3\ibus_rdata$next[63:0]$5525
+ assign $2\ibus_rdata$next[63:0]$5499 $3\ibus_rdata$next[63:0]$5500
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$39
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus_rdata$next[63:0]$5525 \ibus__dat_r
+ assign $3\ibus_rdata$next[63:0]$5500 \ibus__dat_r
case
- assign $3\ibus_rdata$next[63:0]$5525 \ibus_rdata
+ assign $3\ibus_rdata$next[63:0]$5500 \ibus_rdata
end
case
- assign $2\ibus_rdata$next[63:0]$5524 \ibus_rdata
+ assign $2\ibus_rdata$next[63:0]$5499 \ibus_rdata
end
case
- assign $1\ibus_rdata$next[63:0]$5523 \ibus_rdata
+ assign $1\ibus_rdata$next[63:0]$5498 \ibus_rdata
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus_rdata$next[63:0]$5526 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $4\ibus_rdata$next[63:0]$5501 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $4\ibus_rdata$next[63:0]$5526 $1\ibus_rdata$next[63:0]$5523
+ assign $4\ibus_rdata$next[63:0]$5501 $1\ibus_rdata$next[63:0]$5498
end
sync always
- update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5522
+ update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5497
end
- attribute \src "libresoc.v:136672.3-136694.6"
- process $proc$libresoc.v:136672$5527
+ attribute \src "libresoc.v:136457.3-136479.6"
+ process $proc$libresoc.v:136457$5502
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__adr$next[44:0]$5528 $3\ibus__adr$next[44:0]$5531
- attribute \src "libresoc.v:136673.5-136673.29"
+ assign $0\ibus__adr$next[44:0]$5503 $3\ibus__adr$next[44:0]$5506
+ attribute \src "libresoc.v:136458.5-136458.29"
switch \initial
- attribute \src "libresoc.v:136673.9-136673.17"
+ attribute \src "libresoc.v:136458.9-136458.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__adr$next[44:0]$5529 $2\ibus__adr$next[44:0]$5530
+ assign $1\ibus__adr$next[44:0]$5504 $2\ibus__adr$next[44:0]$5505
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$43 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\ibus__adr$next[44:0]$5530 \ibus__adr
+ assign $2\ibus__adr$next[44:0]$5505 \ibus__adr
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__adr$next[44:0]$5530 \a_pc_i [47:3]
+ assign $2\ibus__adr$next[44:0]$5505 \a_pc_i [47:3]
case
- assign $2\ibus__adr$next[44:0]$5530 \ibus__adr
+ assign $2\ibus__adr$next[44:0]$5505 \ibus__adr
end
case
- assign $1\ibus__adr$next[44:0]$5529 \ibus__adr
+ assign $1\ibus__adr$next[44:0]$5504 \ibus__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__adr$next[44:0]$5531 45'000000000000000000000000000000000000000000000
+ assign $3\ibus__adr$next[44:0]$5506 45'000000000000000000000000000000000000000000000
case
- assign $3\ibus__adr$next[44:0]$5531 $1\ibus__adr$next[44:0]$5529
+ assign $3\ibus__adr$next[44:0]$5506 $1\ibus__adr$next[44:0]$5504
end
sync always
- update \ibus__adr$next $0\ibus__adr$next[44:0]$5528
+ update \ibus__adr$next $0\ibus__adr$next[44:0]$5503
end
- attribute \src "libresoc.v:136695.3-136717.6"
- process $proc$libresoc.v:136695$5532
+ attribute \src "libresoc.v:136480.3-136502.6"
+ process $proc$libresoc.v:136480$5507
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_fetch_err_o$next[0:0]$5533 $3\f_fetch_err_o$next[0:0]$5536
- attribute \src "libresoc.v:136696.5-136696.29"
+ assign $0\f_fetch_err_o$next[0:0]$5508 $3\f_fetch_err_o$next[0:0]$5511
+ attribute \src "libresoc.v:136481.5-136481.29"
switch \initial
- attribute \src "libresoc.v:136696.9-136696.17"
+ attribute \src "libresoc.v:136481.9-136481.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\f_fetch_err_o$next[0:0]$5534 $2\f_fetch_err_o$next[0:0]$5535
+ assign $1\f_fetch_err_o$next[0:0]$5509 $2\f_fetch_err_o$next[0:0]$5510
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
switch { \$47 \$45 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\f_fetch_err_o$next[0:0]$5535 1'1
+ assign $2\f_fetch_err_o$next[0:0]$5510 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\f_fetch_err_o$next[0:0]$5535 1'0
+ assign $2\f_fetch_err_o$next[0:0]$5510 1'0
case
- assign $2\f_fetch_err_o$next[0:0]$5535 \f_fetch_err_o
+ assign $2\f_fetch_err_o$next[0:0]$5510 \f_fetch_err_o
end
case
- assign $1\f_fetch_err_o$next[0:0]$5534 \f_fetch_err_o
+ assign $1\f_fetch_err_o$next[0:0]$5509 \f_fetch_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\f_fetch_err_o$next[0:0]$5536 1'0
+ assign $3\f_fetch_err_o$next[0:0]$5511 1'0
case
- assign $3\f_fetch_err_o$next[0:0]$5536 $1\f_fetch_err_o$next[0:0]$5534
+ assign $3\f_fetch_err_o$next[0:0]$5511 $1\f_fetch_err_o$next[0:0]$5509
end
sync always
- update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5533
+ update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5508
end
- attribute \src "libresoc.v:136718.3-136737.6"
- process $proc$libresoc.v:136718$5537
+ attribute \src "libresoc.v:136503.3-136522.6"
+ process $proc$libresoc.v:136503$5512
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_badaddr_o$next[44:0]$5538 $3\f_badaddr_o$next[44:0]$5541
- attribute \src "libresoc.v:136719.5-136719.29"
+ assign $0\f_badaddr_o$next[44:0]$5513 $3\f_badaddr_o$next[44:0]$5516
+ attribute \src "libresoc.v:136504.5-136504.29"
switch \initial
- attribute \src "libresoc.v:136719.9-136719.17"
+ attribute \src "libresoc.v:136504.9-136504.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\f_badaddr_o$next[44:0]$5539 $2\f_badaddr_o$next[44:0]$5540
+ assign $1\f_badaddr_o$next[44:0]$5514 $2\f_badaddr_o$next[44:0]$5515
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
switch { \$51 \$49 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\f_badaddr_o$next[44:0]$5540 \ibus__adr
+ assign $2\f_badaddr_o$next[44:0]$5515 \ibus__adr
case
- assign $2\f_badaddr_o$next[44:0]$5540 \f_badaddr_o
+ assign $2\f_badaddr_o$next[44:0]$5515 \f_badaddr_o
end
case
- assign $1\f_badaddr_o$next[44:0]$5539 \f_badaddr_o
+ assign $1\f_badaddr_o$next[44:0]$5514 \f_badaddr_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\f_badaddr_o$next[44:0]$5541 45'000000000000000000000000000000000000000000000
+ assign $3\f_badaddr_o$next[44:0]$5516 45'000000000000000000000000000000000000000000000
case
- assign $3\f_badaddr_o$next[44:0]$5541 $1\f_badaddr_o$next[44:0]$5539
+ assign $3\f_badaddr_o$next[44:0]$5516 $1\f_badaddr_o$next[44:0]$5514
end
sync always
- update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5538
+ update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5513
end
- attribute \src "libresoc.v:136738.3-136747.6"
- process $proc$libresoc.v:136738$5542
+ attribute \src "libresoc.v:136523.3-136532.6"
+ process $proc$libresoc.v:136523$5517
assign { } { }
assign { } { }
assign $0\a_busy_o[0:0] $1\a_busy_o[0:0]
- attribute \src "libresoc.v:136739.5-136739.29"
+ attribute \src "libresoc.v:136524.5-136524.29"
switch \initial
- attribute \src "libresoc.v:136739.9-136739.17"
+ attribute \src "libresoc.v:136524.9-136524.17"
case 1'1
case
end
sync always
update \a_busy_o $0\a_busy_o[0:0]
end
- attribute \src "libresoc.v:136748.3-136765.6"
- process $proc$libresoc.v:136748$5543
+ attribute \src "libresoc.v:136533.3-136550.6"
+ process $proc$libresoc.v:136533$5518
assign { } { }
assign { } { }
assign $0\f_busy_o[0:0] $1\f_busy_o[0:0]
- attribute \src "libresoc.v:136749.5-136749.29"
+ attribute \src "libresoc.v:136534.5-136534.29"
switch \initial
- attribute \src "libresoc.v:136749.9-136749.17"
+ attribute \src "libresoc.v:136534.9-136534.17"
case 1'1
case
end
sync always
update \f_busy_o $0\f_busy_o[0:0]
end
- attribute \src "libresoc.v:136766.3-136783.6"
- process $proc$libresoc.v:136766$5544
+ attribute \src "libresoc.v:136551.3-136568.6"
+ process $proc$libresoc.v:136551$5519
assign { } { }
assign { } { }
assign $0\f_instr_o[63:0] $1\f_instr_o[63:0]
- attribute \src "libresoc.v:136767.5-136767.29"
+ attribute \src "libresoc.v:136552.5-136552.29"
switch \initial
- attribute \src "libresoc.v:136767.9-136767.17"
+ attribute \src "libresoc.v:136552.9-136552.17"
case 1'1
case
end
sync always
update \f_instr_o $0\f_instr_o[63:0]
end
- connect \$9 $or$libresoc.v:136523$5470_Y
- connect \$11 $not$libresoc.v:136524$5471_Y
- connect \$13 $and$libresoc.v:136525$5472_Y
- connect \$15 $or$libresoc.v:136526$5473_Y
- connect \$17 $not$libresoc.v:136527$5474_Y
- connect \$1 $not$libresoc.v:136528$5475_Y
- connect \$19 $or$libresoc.v:136529$5476_Y
- connect \$21 $not$libresoc.v:136530$5477_Y
- connect \$23 $and$libresoc.v:136531$5478_Y
- connect \$25 $or$libresoc.v:136532$5479_Y
- connect \$27 $not$libresoc.v:136533$5480_Y
- connect \$29 $or$libresoc.v:136534$5481_Y
- connect \$31 $not$libresoc.v:136535$5482_Y
- connect \$33 $and$libresoc.v:136536$5483_Y
- connect \$35 $or$libresoc.v:136537$5484_Y
- connect \$37 $not$libresoc.v:136538$5485_Y
- connect \$3 $and$libresoc.v:136539$5486_Y
- connect \$39 $or$libresoc.v:136540$5487_Y
- connect \$41 $not$libresoc.v:136541$5488_Y
- connect \$43 $and$libresoc.v:136542$5489_Y
- connect \$45 $and$libresoc.v:136543$5490_Y
- connect \$47 $not$libresoc.v:136544$5491_Y
- connect \$49 $and$libresoc.v:136545$5492_Y
- connect \$51 $not$libresoc.v:136546$5493_Y
- connect \$5 $or$libresoc.v:136547$5494_Y
- connect \$7 $not$libresoc.v:136548$5495_Y
+ connect \$9 $or$libresoc.v:136308$5445_Y
+ connect \$11 $not$libresoc.v:136309$5446_Y
+ connect \$13 $and$libresoc.v:136310$5447_Y
+ connect \$15 $or$libresoc.v:136311$5448_Y
+ connect \$17 $not$libresoc.v:136312$5449_Y
+ connect \$1 $not$libresoc.v:136313$5450_Y
+ connect \$19 $or$libresoc.v:136314$5451_Y
+ connect \$21 $not$libresoc.v:136315$5452_Y
+ connect \$23 $and$libresoc.v:136316$5453_Y
+ connect \$25 $or$libresoc.v:136317$5454_Y
+ connect \$27 $not$libresoc.v:136318$5455_Y
+ connect \$29 $or$libresoc.v:136319$5456_Y
+ connect \$31 $not$libresoc.v:136320$5457_Y
+ connect \$33 $and$libresoc.v:136321$5458_Y
+ connect \$35 $or$libresoc.v:136322$5459_Y
+ connect \$37 $not$libresoc.v:136323$5460_Y
+ connect \$3 $and$libresoc.v:136324$5461_Y
+ connect \$39 $or$libresoc.v:136325$5462_Y
+ connect \$41 $not$libresoc.v:136326$5463_Y
+ connect \$43 $and$libresoc.v:136327$5464_Y
+ connect \$45 $and$libresoc.v:136328$5465_Y
+ connect \$47 $not$libresoc.v:136329$5466_Y
+ connect \$49 $and$libresoc.v:136330$5467_Y
+ connect \$51 $not$libresoc.v:136331$5468_Y
+ connect \$5 $or$libresoc.v:136332$5469_Y
+ connect \$7 $not$libresoc.v:136333$5470_Y
connect \a_stall_i 1'0
connect \f_stall_i 1'0
end
-attribute \src "libresoc.v:136790.1-137117.10"
+attribute \src "libresoc.v:136575.1-136902.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input"
attribute \generator "nMigen"
module \input
- attribute \src "libresoc.v:137080.3-137091.6"
+ attribute \src "libresoc.v:136865.3-136876.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:136791.7-136791.20"
+ attribute \src "libresoc.v:136576.7-136576.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:137092.3-137110.6"
- wire width 2 $0\xer_ca$23[1:0]$5556
- attribute \src "libresoc.v:137080.3-137091.6"
+ attribute \src "libresoc.v:136877.3-136895.6"
+ wire width 2 $0\xer_ca$23[1:0]$5531
+ attribute \src "libresoc.v:136865.3-136876.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:137092.3-137110.6"
- wire width 2 $1\xer_ca$23[1:0]$5557
- attribute \src "libresoc.v:137079.18-137079.100"
- wire width 64 $not$libresoc.v:137079$5553_Y
+ attribute \src "libresoc.v:136877.3-136895.6"
+ wire width 2 $1\xer_ca$23[1:0]$5532
+ attribute \src "libresoc.v:136864.18-136864.100"
+ wire width 64 $not$libresoc.v:136864$5528_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire output 33 \alu_op__zero_a$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:136791.7-136791.15"
+ attribute \src "libresoc.v:136576.7-136576.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 46 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 44 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:137079$5553
+ cell $not $not$libresoc.v:136864$5528
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:137079$5553_Y
+ connect \Y $not$libresoc.v:136864$5528_Y
end
- attribute \src "libresoc.v:136791.7-136791.20"
- process $proc$libresoc.v:136791$5558
+ attribute \src "libresoc.v:136576.7-136576.20"
+ process $proc$libresoc.v:136576$5533
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:137080.3-137091.6"
- process $proc$libresoc.v:137080$5554
+ attribute \src "libresoc.v:136865.3-136876.6"
+ process $proc$libresoc.v:136865$5529
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:137081.5-137081.29"
+ attribute \src "libresoc.v:136866.5-136866.29"
switch \initial
- attribute \src "libresoc.v:137081.9-137081.17"
+ attribute \src "libresoc.v:136866.9-136866.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:137092.3-137110.6"
- process $proc$libresoc.v:137092$5555
+ attribute \src "libresoc.v:136877.3-136895.6"
+ process $proc$libresoc.v:136877$5530
assign { } { }
assign { } { }
- assign $0\xer_ca$23[1:0]$5556 $1\xer_ca$23[1:0]$5557
- attribute \src "libresoc.v:137093.5-137093.29"
+ assign $0\xer_ca$23[1:0]$5531 $1\xer_ca$23[1:0]$5532
+ attribute \src "libresoc.v:136878.5-136878.29"
switch \initial
- attribute \src "libresoc.v:137093.9-137093.17"
+ attribute \src "libresoc.v:136878.9-136878.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\xer_ca$23[1:0]$5557 2'00
+ assign $1\xer_ca$23[1:0]$5532 2'00
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\xer_ca$23[1:0]$5557 2'11
+ assign $1\xer_ca$23[1:0]$5532 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\xer_ca$23[1:0]$5557 \xer_ca
+ assign $1\xer_ca$23[1:0]$5532 \xer_ca
case
- assign $1\xer_ca$23[1:0]$5557 2'00
+ assign $1\xer_ca$23[1:0]$5532 2'00
end
sync always
- update \xer_ca$23 $0\xer_ca$23[1:0]$5556
+ update \xer_ca$23 $0\xer_ca$23[1:0]$5531
end
- connect \$24 $not$libresoc.v:137079$5553_Y
+ connect \$24 $not$libresoc.v:136864$5528_Y
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \b \rb
connect \ra$20 \a
end
-attribute \src "libresoc.v:137121.1-137449.10"
+attribute \src "libresoc.v:136906.1-137234.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input"
attribute \generator "nMigen"
module \input$113
- attribute \src "libresoc.v:137411.3-137422.6"
+ attribute \src "libresoc.v:137196.3-137207.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:137122.7-137122.20"
+ attribute \src "libresoc.v:136907.7-136907.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:137423.3-137441.6"
- wire width 2 $0\xer_ca$23[1:0]$5562
- attribute \src "libresoc.v:137411.3-137422.6"
+ attribute \src "libresoc.v:137208.3-137226.6"
+ wire width 2 $0\xer_ca$23[1:0]$5537
+ attribute \src "libresoc.v:137196.3-137207.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:137423.3-137441.6"
- wire width 2 $1\xer_ca$23[1:0]$5563
- attribute \src "libresoc.v:137410.18-137410.100"
- wire width 64 $not$libresoc.v:137410$5559_Y
+ attribute \src "libresoc.v:137208.3-137226.6"
+ wire width 2 $1\xer_ca$23[1:0]$5538
+ attribute \src "libresoc.v:137195.18-137195.100"
+ wire width 64 $not$libresoc.v:137195$5534_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:137122.7-137122.15"
+ attribute \src "libresoc.v:136907.7-136907.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 46 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 44 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:137410$5559
+ cell $not $not$libresoc.v:137195$5534
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:137410$5559_Y
+ connect \Y $not$libresoc.v:137195$5534_Y
end
- attribute \src "libresoc.v:137122.7-137122.20"
- process $proc$libresoc.v:137122$5564
+ attribute \src "libresoc.v:136907.7-136907.20"
+ process $proc$libresoc.v:136907$5539
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:137411.3-137422.6"
- process $proc$libresoc.v:137411$5560
+ attribute \src "libresoc.v:137196.3-137207.6"
+ process $proc$libresoc.v:137196$5535
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:137412.5-137412.29"
+ attribute \src "libresoc.v:137197.5-137197.29"
switch \initial
- attribute \src "libresoc.v:137412.9-137412.17"
+ attribute \src "libresoc.v:137197.9-137197.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:137423.3-137441.6"
- process $proc$libresoc.v:137423$5561
+ attribute \src "libresoc.v:137208.3-137226.6"
+ process $proc$libresoc.v:137208$5536
assign { } { }
assign { } { }
- assign $0\xer_ca$23[1:0]$5562 $1\xer_ca$23[1:0]$5563
- attribute \src "libresoc.v:137424.5-137424.29"
+ assign $0\xer_ca$23[1:0]$5537 $1\xer_ca$23[1:0]$5538
+ attribute \src "libresoc.v:137209.5-137209.29"
switch \initial
- attribute \src "libresoc.v:137424.9-137424.17"
+ attribute \src "libresoc.v:137209.9-137209.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\xer_ca$23[1:0]$5563 2'00
+ assign $1\xer_ca$23[1:0]$5538 2'00
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\xer_ca$23[1:0]$5563 2'11
+ assign $1\xer_ca$23[1:0]$5538 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\xer_ca$23[1:0]$5563 \xer_ca
+ assign $1\xer_ca$23[1:0]$5538 \xer_ca
case
- assign $1\xer_ca$23[1:0]$5563 2'00
+ assign $1\xer_ca$23[1:0]$5538 2'00
end
sync always
- update \xer_ca$23 $0\xer_ca$23[1:0]$5562
+ update \xer_ca$23 $0\xer_ca$23[1:0]$5537
end
- connect \$24 $not$libresoc.v:137410$5559_Y
+ connect \$24 $not$libresoc.v:137195$5534_Y
connect \rc$21 \rc
connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \muxid$1 \muxid
connect \b \rb
connect \ra$19 \a
end
-attribute \src "libresoc.v:137453.1-137756.10"
+attribute \src "libresoc.v:137238.1-137541.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input"
attribute \generator "nMigen"
module \input$50
- attribute \src "libresoc.v:137738.3-137749.6"
+ attribute \src "libresoc.v:137523.3-137534.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:137454.7-137454.20"
+ attribute \src "libresoc.v:137239.7-137239.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:137738.3-137749.6"
+ attribute \src "libresoc.v:137523.3-137534.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:137737.18-137737.100"
- wire width 64 $not$libresoc.v:137737$5565_Y
+ attribute \src "libresoc.v:137522.18-137522.100"
+ wire width 64 $not$libresoc.v:137522$5540_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43"
wire width 64 \$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:137454.7-137454.15"
+ attribute \src "libresoc.v:137239.7-137239.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 43 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43"
- cell $not $not$libresoc.v:137737$5565
+ cell $not $not$libresoc.v:137522$5540
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \rb
- connect \Y $not$libresoc.v:137737$5565_Y
+ connect \Y $not$libresoc.v:137522$5540_Y
end
- attribute \src "libresoc.v:137454.7-137454.20"
- process $proc$libresoc.v:137454$5567
+ attribute \src "libresoc.v:137239.7-137239.20"
+ process $proc$libresoc.v:137239$5542
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:137738.3-137749.6"
- process $proc$libresoc.v:137738$5566
+ attribute \src "libresoc.v:137523.3-137534.6"
+ process $proc$libresoc.v:137523$5541
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:137739.5-137739.29"
+ attribute \src "libresoc.v:137524.5-137524.29"
switch \initial
- attribute \src "libresoc.v:137739.9-137739.17"
+ attribute \src "libresoc.v:137524.9-137524.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- connect \$23 $not$libresoc.v:137737$5565_Y
+ connect \$23 $not$libresoc.v:137522$5540_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \ra$20 \a
connect \a \ra
end
-attribute \src "libresoc.v:137760.1-138063.10"
+attribute \src "libresoc.v:137545.1-137848.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input"
attribute \generator "nMigen"
module \input$78
- attribute \src "libresoc.v:138045.3-138056.6"
+ attribute \src "libresoc.v:137830.3-137841.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:137761.7-137761.20"
+ attribute \src "libresoc.v:137546.7-137546.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:138045.3-138056.6"
+ attribute \src "libresoc.v:137830.3-137841.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:138044.18-138044.100"
- wire width 64 $not$libresoc.v:138044$5568_Y
+ attribute \src "libresoc.v:137829.18-137829.100"
+ wire width 64 $not$libresoc.v:137829$5543_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:137761.7-137761.15"
+ attribute \src "libresoc.v:137546.7-137546.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 43 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:138044$5568
+ cell $not $not$libresoc.v:137829$5543
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:138044$5568_Y
+ connect \Y $not$libresoc.v:137829$5543_Y
end
- attribute \src "libresoc.v:137761.7-137761.20"
- process $proc$libresoc.v:137761$5570
+ attribute \src "libresoc.v:137546.7-137546.20"
+ process $proc$libresoc.v:137546$5545
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:138045.3-138056.6"
- process $proc$libresoc.v:138045$5569
+ attribute \src "libresoc.v:137830.3-137841.6"
+ process $proc$libresoc.v:137830$5544
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:138046.5-138046.29"
+ attribute \src "libresoc.v:137831.5-137831.29"
switch \initial
- attribute \src "libresoc.v:138046.9-138046.17"
+ attribute \src "libresoc.v:137831.9-137831.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- connect \$23 $not$libresoc.v:138044$5568_Y
+ connect \$23 $not$libresoc.v:137829$5543_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \b \rb
connect \ra$20 \a
end
-attribute \src "libresoc.v:138067.1-138323.10"
+attribute \src "libresoc.v:137852.1-138108.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input"
attribute \generator "nMigen"
connect \ra$14 \a
connect \a \ra
end
-attribute \src "libresoc.v:138327.1-138587.10"
+attribute \src "libresoc.v:138112.1-138251.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.int"
attribute \generator "nMigen"
module \int
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 5 $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 64 $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 64 $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607
- attribute \src "libresoc.v:138459.3-138466.6"
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 5 $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582
+ attribute \src "libresoc.v:138197.3-138201.6"
wire width 5 $0\_0_[4:0]
- attribute \src "libresoc.v:138459.3-138466.6"
+ attribute \src "libresoc.v:138197.3-138201.6"
wire width 5 $0\_1_[4:0]
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 5 $0\_2_[4:0]
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 5 $0\_3_[4:0]
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 5 $0\_4_[4:0]
- attribute \src "libresoc.v:138519.3-138528.6"
+ attribute \src "libresoc.v:138217.3-138226.6"
wire width 64 $0\dmi__data_o[63:0]
- attribute \src "libresoc.v:138328.7-138328.20"
+ attribute \src "libresoc.v:138113.7-138113.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:138500.3-138509.6"
- wire width 64 $0\pred__data_o[63:0]
- attribute \src "libresoc.v:138539.3-138547.6"
- wire $0\ren_delay$10$next[0:0]$5638
- attribute \src "libresoc.v:138478.3-138479.43"
- wire $0\ren_delay$10[0:0]$5623
- attribute \src "libresoc.v:138381.7-138381.28"
- wire $0\ren_delay$10[0:0]$5680
- attribute \src "libresoc.v:138558.3-138566.6"
- wire $0\ren_delay$11$next[0:0]$5642
- attribute \src "libresoc.v:138476.3-138477.43"
- wire $0\ren_delay$11[0:0]$5621
- attribute \src "libresoc.v:138385.7-138385.28"
- wire $0\ren_delay$11[0:0]$5682
- attribute \src "libresoc.v:138491.3-138499.6"
- wire $0\ren_delay$12$next[0:0]$5629
- attribute \src "libresoc.v:138474.3-138475.43"
- wire $0\ren_delay$12[0:0]$5619
- attribute \src "libresoc.v:138389.7-138389.28"
- wire $0\ren_delay$12[0:0]$5684
- attribute \src "libresoc.v:138510.3-138518.6"
- wire $0\ren_delay$13$next[0:0]$5633
- attribute \src "libresoc.v:138472.3-138473.43"
- wire $0\ren_delay$13[0:0]$5617
- attribute \src "libresoc.v:138393.7-138393.28"
- wire $0\ren_delay$13[0:0]$5686
- attribute \src "libresoc.v:138482.3-138490.6"
- wire $0\ren_delay$next[0:0]$5626
- attribute \src "libresoc.v:138480.3-138481.35"
+ attribute \src "libresoc.v:138227.3-138235.6"
+ wire $0\ren_delay$4$next[0:0]$5596
+ attribute \src "libresoc.v:138204.3-138205.41"
+ wire $0\ren_delay$4[0:0]$5589
+ attribute \src "libresoc.v:138148.7-138148.27"
+ wire $0\ren_delay$4[0:0]$5634
+ attribute \src "libresoc.v:138208.3-138216.6"
+ wire $0\ren_delay$next[0:0]$5592
+ attribute \src "libresoc.v:138206.3-138207.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:138529.3-138538.6"
- wire width 64 $0\src1__data_o[63:0]
- attribute \src "libresoc.v:138548.3-138557.6"
- wire width 64 $0\src2__data_o[63:0]
- attribute \src "libresoc.v:138567.3-138576.6"
- wire width 64 $0\src3__data_o[63:0]
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 5 $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 64 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609
- attribute \src "libresoc.v:138459.3-138466.6"
- wire width 64 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610
- attribute \src "libresoc.v:138519.3-138528.6"
+ attribute \src "libresoc.v:138236.3-138245.6"
+ wire width 64 $0\src__data_o[63:0]
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 5 $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584
+ attribute \src "libresoc.v:138197.3-138201.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585
+ attribute \src "libresoc.v:138217.3-138226.6"
wire width 64 $1\dmi__data_o[63:0]
- attribute \src "libresoc.v:138500.3-138509.6"
- wire width 64 $1\pred__data_o[63:0]
- attribute \src "libresoc.v:138539.3-138547.6"
- wire $1\ren_delay$10$next[0:0]$5639
- attribute \src "libresoc.v:138558.3-138566.6"
- wire $1\ren_delay$11$next[0:0]$5643
- attribute \src "libresoc.v:138491.3-138499.6"
- wire $1\ren_delay$12$next[0:0]$5630
- attribute \src "libresoc.v:138510.3-138518.6"
- wire $1\ren_delay$13$next[0:0]$5634
- attribute \src "libresoc.v:138482.3-138490.6"
- wire $1\ren_delay$next[0:0]$5627
- attribute \src "libresoc.v:138379.7-138379.23"
+ attribute \src "libresoc.v:138227.3-138235.6"
+ wire $1\ren_delay$4$next[0:0]$5597
+ attribute \src "libresoc.v:138208.3-138216.6"
+ wire $1\ren_delay$next[0:0]$5593
+ attribute \src "libresoc.v:138146.7-138146.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:138529.3-138538.6"
- wire width 64 $1\src1__data_o[63:0]
- attribute \src "libresoc.v:138548.3-138557.6"
- wire width 64 $1\src2__data_o[63:0]
- attribute \src "libresoc.v:138567.3-138576.6"
- wire width 64 $1\src3__data_o[63:0]
- attribute \src "libresoc.v:138467.26-138467.32"
- wire width 64 $memrd$\memory$libresoc.v:138467$5611_DATA
- attribute \src "libresoc.v:138468.30-138468.36"
- wire width 64 $memrd$\memory$libresoc.v:138468$5612_DATA
- attribute \src "libresoc.v:138469.30-138469.36"
- wire width 64 $memrd$\memory$libresoc.v:138469$5613_DATA
- attribute \src "libresoc.v:138470.30-138470.36"
- wire width 64 $memrd$\memory$libresoc.v:138470$5614_DATA
- attribute \src "libresoc.v:138471.30-138471.36"
- wire width 64 $memrd$\memory$libresoc.v:138471$5615_DATA
+ attribute \src "libresoc.v:138236.3-138245.6"
+ wire width 64 $1\src__data_o[63:0]
+ attribute \src "libresoc.v:138202.26-138202.32"
+ wire width 64 $memrd$\memory$libresoc.v:138202$5586_DATA
+ attribute \src "libresoc.v:138203.30-138203.36"
+ wire width 64 $memrd$\memory$libresoc.v:138203$5587_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 5 $memwr$\memory$libresoc.v:138465$5603_ADDR
+ wire width 5 $memwr$\memory$libresoc.v:138200$5578_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:138465$5603_DATA
+ wire width 64 $memwr$\memory$libresoc.v:138200$5578_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:138465$5603_EN
- attribute \src "libresoc.v:138454.13-138454.16"
+ wire width 64 $memwr$\memory$libresoc.v:138200$5578_EN
+ attribute \src "libresoc.v:138195.13-138195.16"
wire width 5 \_0_
- attribute \src "libresoc.v:138455.13-138455.16"
+ attribute \src "libresoc.v:138196.13-138196.16"
wire width 5 \_1_
- attribute \src "libresoc.v:138456.13-138456.16"
- wire width 5 \_2_
- attribute \src "libresoc.v:138457.13-138457.16"
- wire width 5 \_3_
- attribute \src "libresoc.v:138458.13-138458.16"
- wire width 5 \_4_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 17 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 11 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 input 15 \dest1__addr
+ wire width 5 input 9 \dest1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 input 14 \dest1__data_i
+ wire width 64 input 8 \dest1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 16 \dest1__wen
+ wire input 10 \dest1__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 5 input 2 \dmi__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 4 \dmi__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 3 \dmi__ren
- attribute \src "libresoc.v:138328.7-138328.15"
+ attribute \src "libresoc.v:138113.7-138113.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 5 \memory_r_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 5 \memory_r_addr$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 5 \memory_r_addr$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 5 \memory_r_addr$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 5 \memory_r_addr$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 64 \memory_r_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 64 \memory_r_data$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 64 \memory_r_data$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 64 \memory_r_data$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 64 \memory_r_data$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire width 5 \memory_w_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire width 64 \memory_w_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire \memory_w_en
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 \pred__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \pred__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire \pred__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
wire \ren_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$11$next
+ wire \ren_delay$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$12$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
- wire \ren_delay$13$next
+ wire \ren_delay$4$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
wire \ren_delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 input 6 \src1__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 output 5 \src1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 7 \src1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 input 9 \src2__addr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 output 8 \src2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \src2__ren
+ wire width 5 input 6 \src__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 5 input 12 \src3__addr
+ wire width 64 output 5 \src__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 output 11 \src3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 13 \src3__ren
- attribute \src "libresoc.v:138419.14-138419.20"
+ wire input 7 \src__ren
+ attribute \src "libresoc.v:138160.14-138160.20"
memory width 64 size 32 \memory
- attribute \src "libresoc.v:138421.5-138421.37"
- cell $meminit $meminit$\memory$libresoc.v:138421$5645
+ attribute \src "libresoc.v:138162.5-138162.37"
+ cell $meminit $meminit$\memory$libresoc.v:138162$5599
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5645
+ parameter \PRIORITY 5599
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138422.5-138422.37"
- cell $meminit $meminit$\memory$libresoc.v:138422$5646
+ attribute \src "libresoc.v:138163.5-138163.37"
+ cell $meminit $meminit$\memory$libresoc.v:138163$5600
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5646
+ parameter \PRIORITY 5600
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138423.5-138423.37"
- cell $meminit $meminit$\memory$libresoc.v:138423$5647
+ attribute \src "libresoc.v:138164.5-138164.37"
+ cell $meminit $meminit$\memory$libresoc.v:138164$5601
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5647
+ parameter \PRIORITY 5601
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138424.5-138424.37"
- cell $meminit $meminit$\memory$libresoc.v:138424$5648
+ attribute \src "libresoc.v:138165.5-138165.37"
+ cell $meminit $meminit$\memory$libresoc.v:138165$5602
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5648
+ parameter \PRIORITY 5602
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138425.5-138425.37"
- cell $meminit $meminit$\memory$libresoc.v:138425$5649
+ attribute \src "libresoc.v:138166.5-138166.37"
+ cell $meminit $meminit$\memory$libresoc.v:138166$5603
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5649
+ parameter \PRIORITY 5603
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138426.5-138426.37"
- cell $meminit $meminit$\memory$libresoc.v:138426$5650
+ attribute \src "libresoc.v:138167.5-138167.37"
+ cell $meminit $meminit$\memory$libresoc.v:138167$5604
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5650
+ parameter \PRIORITY 5604
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138427.5-138427.37"
- cell $meminit $meminit$\memory$libresoc.v:138427$5651
+ attribute \src "libresoc.v:138168.5-138168.37"
+ cell $meminit $meminit$\memory$libresoc.v:138168$5605
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5651
+ parameter \PRIORITY 5605
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138428.5-138428.37"
- cell $meminit $meminit$\memory$libresoc.v:138428$5652
+ attribute \src "libresoc.v:138169.5-138169.37"
+ cell $meminit $meminit$\memory$libresoc.v:138169$5606
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5652
+ parameter \PRIORITY 5606
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138429.5-138429.37"
- cell $meminit $meminit$\memory$libresoc.v:138429$5653
+ attribute \src "libresoc.v:138170.5-138170.37"
+ cell $meminit $meminit$\memory$libresoc.v:138170$5607
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5653
+ parameter \PRIORITY 5607
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 8
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138430.5-138430.37"
- cell $meminit $meminit$\memory$libresoc.v:138430$5654
+ attribute \src "libresoc.v:138171.5-138171.37"
+ cell $meminit $meminit$\memory$libresoc.v:138171$5608
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5654
+ parameter \PRIORITY 5608
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 9
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138431.5-138431.38"
- cell $meminit $meminit$\memory$libresoc.v:138431$5655
+ attribute \src "libresoc.v:138172.5-138172.38"
+ cell $meminit $meminit$\memory$libresoc.v:138172$5609
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5655
+ parameter \PRIORITY 5609
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 10
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138432.5-138432.38"
- cell $meminit $meminit$\memory$libresoc.v:138432$5656
+ attribute \src "libresoc.v:138173.5-138173.38"
+ cell $meminit $meminit$\memory$libresoc.v:138173$5610
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5656
+ parameter \PRIORITY 5610
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 11
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138433.5-138433.38"
- cell $meminit $meminit$\memory$libresoc.v:138433$5657
+ attribute \src "libresoc.v:138174.5-138174.38"
+ cell $meminit $meminit$\memory$libresoc.v:138174$5611
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5657
+ parameter \PRIORITY 5611
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 12
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138434.5-138434.38"
- cell $meminit $meminit$\memory$libresoc.v:138434$5658
+ attribute \src "libresoc.v:138175.5-138175.38"
+ cell $meminit $meminit$\memory$libresoc.v:138175$5612
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5658
+ parameter \PRIORITY 5612
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 13
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138435.5-138435.38"
- cell $meminit $meminit$\memory$libresoc.v:138435$5659
+ attribute \src "libresoc.v:138176.5-138176.38"
+ cell $meminit $meminit$\memory$libresoc.v:138176$5613
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5659
+ parameter \PRIORITY 5613
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 14
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138436.5-138436.38"
- cell $meminit $meminit$\memory$libresoc.v:138436$5660
+ attribute \src "libresoc.v:138177.5-138177.38"
+ cell $meminit $meminit$\memory$libresoc.v:138177$5614
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5660
+ parameter \PRIORITY 5614
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 15
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138437.5-138437.38"
- cell $meminit $meminit$\memory$libresoc.v:138437$5661
+ attribute \src "libresoc.v:138178.5-138178.38"
+ cell $meminit $meminit$\memory$libresoc.v:138178$5615
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5661
+ parameter \PRIORITY 5615
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 16
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138438.5-138438.38"
- cell $meminit $meminit$\memory$libresoc.v:138438$5662
+ attribute \src "libresoc.v:138179.5-138179.38"
+ cell $meminit $meminit$\memory$libresoc.v:138179$5616
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5662
+ parameter \PRIORITY 5616
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 17
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138439.5-138439.38"
- cell $meminit $meminit$\memory$libresoc.v:138439$5663
+ attribute \src "libresoc.v:138180.5-138180.38"
+ cell $meminit $meminit$\memory$libresoc.v:138180$5617
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5663
+ parameter \PRIORITY 5617
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 18
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138440.5-138440.38"
- cell $meminit $meminit$\memory$libresoc.v:138440$5664
+ attribute \src "libresoc.v:138181.5-138181.38"
+ cell $meminit $meminit$\memory$libresoc.v:138181$5618
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5664
+ parameter \PRIORITY 5618
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 19
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138441.5-138441.38"
- cell $meminit $meminit$\memory$libresoc.v:138441$5665
+ attribute \src "libresoc.v:138182.5-138182.38"
+ cell $meminit $meminit$\memory$libresoc.v:138182$5619
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5665
+ parameter \PRIORITY 5619
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 20
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138442.5-138442.38"
- cell $meminit $meminit$\memory$libresoc.v:138442$5666
+ attribute \src "libresoc.v:138183.5-138183.38"
+ cell $meminit $meminit$\memory$libresoc.v:138183$5620
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5666
+ parameter \PRIORITY 5620
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 21
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138443.5-138443.38"
- cell $meminit $meminit$\memory$libresoc.v:138443$5667
+ attribute \src "libresoc.v:138184.5-138184.38"
+ cell $meminit $meminit$\memory$libresoc.v:138184$5621
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5667
+ parameter \PRIORITY 5621
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 22
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138444.5-138444.38"
- cell $meminit $meminit$\memory$libresoc.v:138444$5668
+ attribute \src "libresoc.v:138185.5-138185.38"
+ cell $meminit $meminit$\memory$libresoc.v:138185$5622
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5668
+ parameter \PRIORITY 5622
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 23
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138445.5-138445.38"
- cell $meminit $meminit$\memory$libresoc.v:138445$5669
+ attribute \src "libresoc.v:138186.5-138186.38"
+ cell $meminit $meminit$\memory$libresoc.v:138186$5623
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5669
+ parameter \PRIORITY 5623
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 24
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138446.5-138446.38"
- cell $meminit $meminit$\memory$libresoc.v:138446$5670
+ attribute \src "libresoc.v:138187.5-138187.38"
+ cell $meminit $meminit$\memory$libresoc.v:138187$5624
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5670
+ parameter \PRIORITY 5624
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 25
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138447.5-138447.38"
- cell $meminit $meminit$\memory$libresoc.v:138447$5671
+ attribute \src "libresoc.v:138188.5-138188.38"
+ cell $meminit $meminit$\memory$libresoc.v:138188$5625
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5671
+ parameter \PRIORITY 5625
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 26
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138448.5-138448.38"
- cell $meminit $meminit$\memory$libresoc.v:138448$5672
+ attribute \src "libresoc.v:138189.5-138189.38"
+ cell $meminit $meminit$\memory$libresoc.v:138189$5626
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5672
+ parameter \PRIORITY 5626
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 27
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138449.5-138449.38"
- cell $meminit $meminit$\memory$libresoc.v:138449$5673
+ attribute \src "libresoc.v:138190.5-138190.38"
+ cell $meminit $meminit$\memory$libresoc.v:138190$5627
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5673
+ parameter \PRIORITY 5627
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 28
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138450.5-138450.38"
- cell $meminit $meminit$\memory$libresoc.v:138450$5674
+ attribute \src "libresoc.v:138191.5-138191.38"
+ cell $meminit $meminit$\memory$libresoc.v:138191$5628
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5674
+ parameter \PRIORITY 5628
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 29
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138451.5-138451.38"
- cell $meminit $meminit$\memory$libresoc.v:138451$5675
+ attribute \src "libresoc.v:138192.5-138192.38"
+ cell $meminit $meminit$\memory$libresoc.v:138192$5629
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5675
+ parameter \PRIORITY 5629
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 30
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138452.5-138452.38"
- cell $meminit $meminit$\memory$libresoc.v:138452$5676
+ attribute \src "libresoc.v:138193.5-138193.38"
+ cell $meminit $meminit$\memory$libresoc.v:138193$5630
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5676
+ parameter \PRIORITY 5630
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 31
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:138467.26-138467.32"
- cell $memrd $memrd$\memory$libresoc.v:138467$5611
+ attribute \src "libresoc.v:138202.26-138202.32"
+ cell $memrd $memrd$\memory$libresoc.v:138202$5586
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:138467$5611_DATA
+ connect \DATA $memrd$\memory$libresoc.v:138202$5586_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:138468.30-138468.36"
- cell $memrd $memrd$\memory$libresoc.v:138468$5612
+ attribute \src "libresoc.v:138203.30-138203.36"
+ cell $memrd $memrd$\memory$libresoc.v:138203$5587
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_1_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:138468$5612_DATA
- connect \EN 1'x
- end
- attribute \src "libresoc.v:138469.30-138469.36"
- cell $memrd $memrd$\memory$libresoc.v:138469$5613
- parameter \ABITS 5
- parameter \CLK_ENABLE 0
- parameter \CLK_POLARITY 0
- parameter \MEMID "\\memory"
- parameter \TRANSPARENT 0
- parameter \WIDTH 64
- connect \ADDR \_2_
- connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:138469$5613_DATA
- connect \EN 1'x
- end
- attribute \src "libresoc.v:138470.30-138470.36"
- cell $memrd $memrd$\memory$libresoc.v:138470$5614
- parameter \ABITS 5
- parameter \CLK_ENABLE 0
- parameter \CLK_POLARITY 0
- parameter \MEMID "\\memory"
- parameter \TRANSPARENT 0
- parameter \WIDTH 64
- connect \ADDR \_3_
- connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:138470$5614_DATA
- connect \EN 1'x
- end
- attribute \src "libresoc.v:138471.30-138471.36"
- cell $memrd $memrd$\memory$libresoc.v:138471$5615
- parameter \ABITS 5
- parameter \CLK_ENABLE 0
- parameter \CLK_POLARITY 0
- parameter \MEMID "\\memory"
- parameter \TRANSPARENT 0
- parameter \WIDTH 64
- connect \ADDR \_4_
- connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:138471$5615_DATA
+ connect \DATA $memrd$\memory$libresoc.v:138203$5587_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$5687
+ process $proc$libresoc.v:0$5635
sync always
sync init
end
- attribute \src "libresoc.v:138328.7-138328.20"
- process $proc$libresoc.v:138328$5677
+ attribute \src "libresoc.v:138113.7-138113.20"
+ process $proc$libresoc.v:138113$5631
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:138379.7-138379.23"
- process $proc$libresoc.v:138379$5678
+ attribute \src "libresoc.v:138146.7-138146.23"
+ process $proc$libresoc.v:138146$5632
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:138381.7-138381.28"
- process $proc$libresoc.v:138381$5679
- assign { } { }
- assign $0\ren_delay$10[0:0]$5680 1'0
- sync always
- sync init
- update \ren_delay$10 $0\ren_delay$10[0:0]$5680
- end
- attribute \src "libresoc.v:138385.7-138385.28"
- process $proc$libresoc.v:138385$5681
+ attribute \src "libresoc.v:138148.7-138148.27"
+ process $proc$libresoc.v:138148$5633
assign { } { }
- assign $0\ren_delay$11[0:0]$5682 1'0
+ assign $0\ren_delay$4[0:0]$5634 1'0
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[0:0]$5682
+ update \ren_delay$4 $0\ren_delay$4[0:0]$5634
end
- attribute \src "libresoc.v:138389.7-138389.28"
- process $proc$libresoc.v:138389$5683
- assign { } { }
- assign $0\ren_delay$12[0:0]$5684 1'0
- sync always
- sync init
- update \ren_delay$12 $0\ren_delay$12[0:0]$5684
- end
- attribute \src "libresoc.v:138393.7-138393.28"
- process $proc$libresoc.v:138393$5685
- assign { } { }
- assign $0\ren_delay$13[0:0]$5686 1'0
- sync always
- sync init
- update \ren_delay$13 $0\ren_delay$13[0:0]$5686
- end
- attribute \src "libresoc.v:138459.3-138466.6"
- process $proc$libresoc.v:138459$5604
- assign { } { }
- assign { } { }
- assign { } { }
+ attribute \src "libresoc.v:138197.3-138201.6"
+ process $proc$libresoc.v:138197$5579
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\_0_[4:0] \memory_r_addr
assign $0\_1_[4:0] \memory_r_addr$2
- assign $0\_2_[4:0] \memory_r_addr$4
- assign $0\_3_[4:0] \memory_r_addr$6
- assign $0\_4_[4:0] \memory_r_addr$8
- assign $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605 $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608
- assign $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609
- assign $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610
- attribute \src "libresoc.v:138465.5-138465.61"
+ assign $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580 $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583
+ assign $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584
+ assign $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585
+ attribute \src "libresoc.v:138200.5-138200.61"
switch \memory_w_en
- attribute \src "libresoc.v:138465.9-138465.20"
+ attribute \src "libresoc.v:138200.9-138200.20"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 \memory_w_addr
- assign $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 \memory_w_data
- assign $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 \memory_w_addr
+ assign $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 \memory_w_data
+ assign $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 64'1111111111111111111111111111111111111111111111111111111111111111
case
- assign $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 5'xxxxx
- assign $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 5'xxxxx
+ assign $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \coresync_clk
update \_0_ $0\_0_[4:0]
update \_1_ $0\_1_[4:0]
- update \_2_ $0\_2_[4:0]
- update \_3_ $0\_3_[4:0]
- update \_4_ $0\_4_[4:0]
- update $memwr$\memory$libresoc.v:138465$5603_ADDR $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605
- update $memwr$\memory$libresoc.v:138465$5603_DATA $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606
- update $memwr$\memory$libresoc.v:138465$5603_EN $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607
- attribute \src "libresoc.v:138465.22-138465.60"
- memwr \memory $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 0'
- end
- attribute \src "libresoc.v:138472.3-138473.43"
- process $proc$libresoc.v:138472$5616
- assign { } { }
- assign $0\ren_delay$13[0:0]$5617 \ren_delay$13$next
- sync posedge \coresync_clk
- update \ren_delay$13 $0\ren_delay$13[0:0]$5617
- end
- attribute \src "libresoc.v:138474.3-138475.43"
- process $proc$libresoc.v:138474$5618
- assign { } { }
- assign $0\ren_delay$12[0:0]$5619 \ren_delay$12$next
- sync posedge \coresync_clk
- update \ren_delay$12 $0\ren_delay$12[0:0]$5619
- end
- attribute \src "libresoc.v:138476.3-138477.43"
- process $proc$libresoc.v:138476$5620
- assign { } { }
- assign $0\ren_delay$11[0:0]$5621 \ren_delay$11$next
- sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[0:0]$5621
+ update $memwr$\memory$libresoc.v:138200$5578_ADDR $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580
+ update $memwr$\memory$libresoc.v:138200$5578_DATA $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581
+ update $memwr$\memory$libresoc.v:138200$5578_EN $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582
+ attribute \src "libresoc.v:138200.22-138200.60"
+ memwr \memory $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 0'
end
- attribute \src "libresoc.v:138478.3-138479.43"
- process $proc$libresoc.v:138478$5622
+ attribute \src "libresoc.v:138204.3-138205.41"
+ process $proc$libresoc.v:138204$5588
assign { } { }
- assign $0\ren_delay$10[0:0]$5623 \ren_delay$10$next
+ assign $0\ren_delay$4[0:0]$5589 \ren_delay$4$next
sync posedge \coresync_clk
- update \ren_delay$10 $0\ren_delay$10[0:0]$5623
+ update \ren_delay$4 $0\ren_delay$4[0:0]$5589
end
- attribute \src "libresoc.v:138480.3-138481.35"
- process $proc$libresoc.v:138480$5624
+ attribute \src "libresoc.v:138206.3-138207.35"
+ process $proc$libresoc.v:138206$5590
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:138482.3-138490.6"
- process $proc$libresoc.v:138482$5625
- assign { } { }
- assign { } { }
- assign $0\ren_delay$next[0:0]$5626 $1\ren_delay$next[0:0]$5627
- attribute \src "libresoc.v:138483.5-138483.29"
- switch \initial
- attribute \src "libresoc.v:138483.9-138483.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ren_delay$next[0:0]$5627 1'0
- case
- assign $1\ren_delay$next[0:0]$5627 \src1__ren
- end
- sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$5626
- end
- attribute \src "libresoc.v:138491.3-138499.6"
- process $proc$libresoc.v:138491$5628
- assign { } { }
- assign { } { }
- assign $0\ren_delay$12$next[0:0]$5629 $1\ren_delay$12$next[0:0]$5630
- attribute \src "libresoc.v:138492.5-138492.29"
- switch \initial
- attribute \src "libresoc.v:138492.9-138492.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ren_delay$12$next[0:0]$5630 1'0
- case
- assign $1\ren_delay$12$next[0:0]$5630 \pred__ren
- end
- sync always
- update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5629
- end
- attribute \src "libresoc.v:138500.3-138509.6"
- process $proc$libresoc.v:138500$5631
- assign { } { }
- assign { } { }
- assign $0\pred__data_o[63:0] $1\pred__data_o[63:0]
- attribute \src "libresoc.v:138501.5-138501.29"
- switch \initial
- attribute \src "libresoc.v:138501.9-138501.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$12
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\pred__data_o[63:0] \memory_r_data$7
- case
- assign $1\pred__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \pred__data_o $0\pred__data_o[63:0]
- end
- attribute \src "libresoc.v:138510.3-138518.6"
- process $proc$libresoc.v:138510$5632
+ attribute \src "libresoc.v:138208.3-138216.6"
+ process $proc$libresoc.v:138208$5591
assign { } { }
assign { } { }
- assign $0\ren_delay$13$next[0:0]$5633 $1\ren_delay$13$next[0:0]$5634
- attribute \src "libresoc.v:138511.5-138511.29"
+ assign $0\ren_delay$next[0:0]$5592 $1\ren_delay$next[0:0]$5593
+ attribute \src "libresoc.v:138209.5-138209.29"
switch \initial
- attribute \src "libresoc.v:138511.9-138511.17"
+ attribute \src "libresoc.v:138209.9-138209.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$13$next[0:0]$5634 1'0
+ assign $1\ren_delay$next[0:0]$5593 1'0
case
- assign $1\ren_delay$13$next[0:0]$5634 \dmi__ren
+ assign $1\ren_delay$next[0:0]$5593 \dmi__ren
end
sync always
- update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5633
+ update \ren_delay$next $0\ren_delay$next[0:0]$5592
end
- attribute \src "libresoc.v:138519.3-138528.6"
- process $proc$libresoc.v:138519$5635
+ attribute \src "libresoc.v:138217.3-138226.6"
+ process $proc$libresoc.v:138217$5594
assign { } { }
assign { } { }
assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0]
- attribute \src "libresoc.v:138520.5-138520.29"
+ attribute \src "libresoc.v:138218.5-138218.29"
switch \initial
- attribute \src "libresoc.v:138520.9-138520.17"
+ attribute \src "libresoc.v:138218.9-138218.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$13
+ switch \ren_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi__data_o[63:0] \memory_r_data$9
+ assign $1\dmi__data_o[63:0] \memory_r_data
case
assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \dmi__data_o $0\dmi__data_o[63:0]
end
- attribute \src "libresoc.v:138529.3-138538.6"
- process $proc$libresoc.v:138529$5636
- assign { } { }
- assign { } { }
- assign $0\src1__data_o[63:0] $1\src1__data_o[63:0]
- attribute \src "libresoc.v:138530.5-138530.29"
- switch \initial
- attribute \src "libresoc.v:138530.9-138530.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\src1__data_o[63:0] \memory_r_data
- case
- assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \src1__data_o $0\src1__data_o[63:0]
- end
- attribute \src "libresoc.v:138539.3-138547.6"
- process $proc$libresoc.v:138539$5637
+ attribute \src "libresoc.v:138227.3-138235.6"
+ process $proc$libresoc.v:138227$5595
assign { } { }
assign { } { }
- assign $0\ren_delay$10$next[0:0]$5638 $1\ren_delay$10$next[0:0]$5639
- attribute \src "libresoc.v:138540.5-138540.29"
+ assign $0\ren_delay$4$next[0:0]$5596 $1\ren_delay$4$next[0:0]$5597
+ attribute \src "libresoc.v:138228.5-138228.29"
switch \initial
- attribute \src "libresoc.v:138540.9-138540.17"
+ attribute \src "libresoc.v:138228.9-138228.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$10$next[0:0]$5639 1'0
+ assign $1\ren_delay$4$next[0:0]$5597 1'0
case
- assign $1\ren_delay$10$next[0:0]$5639 \src2__ren
+ assign $1\ren_delay$4$next[0:0]$5597 \src__ren
end
sync always
- update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5638
+ update \ren_delay$4$next $0\ren_delay$4$next[0:0]$5596
end
- attribute \src "libresoc.v:138548.3-138557.6"
- process $proc$libresoc.v:138548$5640
+ attribute \src "libresoc.v:138236.3-138245.6"
+ process $proc$libresoc.v:138236$5598
assign { } { }
assign { } { }
- assign $0\src2__data_o[63:0] $1\src2__data_o[63:0]
- attribute \src "libresoc.v:138549.5-138549.29"
+ assign $0\src__data_o[63:0] $1\src__data_o[63:0]
+ attribute \src "libresoc.v:138237.5-138237.29"
switch \initial
- attribute \src "libresoc.v:138549.9-138549.17"
+ attribute \src "libresoc.v:138237.9-138237.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$10
+ switch \ren_delay$4
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src2__data_o[63:0] \memory_r_data$3
+ assign $1\src__data_o[63:0] \memory_r_data$3
case
- assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\src__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \src2__data_o $0\src2__data_o[63:0]
+ update \src__data_o $0\src__data_o[63:0]
end
- attribute \src "libresoc.v:138558.3-138566.6"
- process $proc$libresoc.v:138558$5641
- assign { } { }
- assign { } { }
- assign $0\ren_delay$11$next[0:0]$5642 $1\ren_delay$11$next[0:0]$5643
- attribute \src "libresoc.v:138559.5-138559.29"
- switch \initial
- attribute \src "libresoc.v:138559.9-138559.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ren_delay$11$next[0:0]$5643 1'0
- case
- assign $1\ren_delay$11$next[0:0]$5643 \src3__ren
- end
- sync always
- update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5642
- end
- attribute \src "libresoc.v:138567.3-138576.6"
- process $proc$libresoc.v:138567$5644
- assign { } { }
- assign { } { }
- assign $0\src3__data_o[63:0] $1\src3__data_o[63:0]
- attribute \src "libresoc.v:138568.5-138568.29"
- switch \initial
- attribute \src "libresoc.v:138568.9-138568.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245"
- switch \ren_delay$11
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\src3__data_o[63:0] \memory_r_data$5
- case
- assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \src3__data_o $0\src3__data_o[63:0]
- end
- connect \memory_r_data $memrd$\memory$libresoc.v:138467$5611_DATA
- connect \memory_r_data$3 $memrd$\memory$libresoc.v:138468$5612_DATA
- connect \memory_r_data$5 $memrd$\memory$libresoc.v:138469$5613_DATA
- connect \memory_r_data$7 $memrd$\memory$libresoc.v:138470$5614_DATA
- connect \memory_r_data$9 $memrd$\memory$libresoc.v:138471$5615_DATA
- connect \pred__addr 5'00000
- connect \pred__ren 1'0
+ connect \memory_r_data $memrd$\memory$libresoc.v:138202$5586_DATA
+ connect \memory_r_data$3 $memrd$\memory$libresoc.v:138203$5587_DATA
connect \memory_w_data \dest1__data_i
connect \memory_w_en \dest1__wen
connect \memory_w_addr \dest1__addr
- connect \memory_r_addr$8 \dmi__addr
- connect \memory_r_addr$6 5'00000
- connect \memory_r_addr$4 \src3__addr
- connect \memory_r_addr$2 \src2__addr
- connect \memory_r_addr \src1__addr
+ connect \memory_r_addr$2 \src__addr
+ connect \memory_r_addr \dmi__addr
end
-attribute \src "libresoc.v:138591.1-141161.10"
+attribute \src "libresoc.v:138255.1-140825.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.jtag"
attribute \generator "nMigen"
module \jtag
- attribute \src "libresoc.v:140575.3-140601.6"
+ attribute \src "libresoc.v:140239.3-140265.6"
wire $0\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:140223.3-140238.6"
+ attribute \src "libresoc.v:139887.3-139902.6"
wire $0\TAP_tdo[0:0]
- attribute \src "libresoc.v:140756.3-140800.6"
- wire width 4 $0\dmi0__addr_i$next[3:0]$6075
- attribute \src "libresoc.v:140126.3-140127.41"
+ attribute \src "libresoc.v:140420.3-140464.6"
+ wire width 4 $0\dmi0__addr_i$next[3:0]$6023
+ attribute \src "libresoc.v:139790.3-139791.41"
wire width 4 $0\dmi0__addr_i[3:0]
- attribute \src "libresoc.v:140854.3-140880.6"
- wire width 64 $0\dmi0__din$next[63:0]$6088
- attribute \src "libresoc.v:140122.3-140123.35"
+ attribute \src "libresoc.v:140518.3-140544.6"
+ wire width 64 $0\dmi0__din$next[63:0]$6036
+ attribute \src "libresoc.v:139786.3-139787.35"
wire width 64 $0\dmi0__din[63:0]
- attribute \src "libresoc.v:140425.3-140441.6"
- wire $0\dmi0_addrsr__oe$next[0:0]$6012
- attribute \src "libresoc.v:140154.3-140155.47"
+ attribute \src "libresoc.v:140089.3-140105.6"
+ wire $0\dmi0_addrsr__oe$next[0:0]$5960
+ attribute \src "libresoc.v:139818.3-139819.47"
wire $0\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:140442.3-140462.6"
- wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6016
- attribute \src "libresoc.v:140152.3-140153.47"
+ attribute \src "libresoc.v:140106.3-140126.6"
+ wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5964
+ attribute \src "libresoc.v:139816.3-139817.47"
wire width 8 $0\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:140407.3-140415.6"
- wire $0\dmi0_addrsr_update_core$next[0:0]$6006
- attribute \src "libresoc.v:140158.3-140159.63"
+ attribute \src "libresoc.v:140071.3-140079.6"
+ wire $0\dmi0_addrsr_update_core$next[0:0]$5954
+ attribute \src "libresoc.v:139822.3-139823.63"
wire $0\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:140416.3-140424.6"
- wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6009
- attribute \src "libresoc.v:140156.3-140157.73"
+ attribute \src "libresoc.v:140080.3-140088.6"
+ wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5957
+ attribute \src "libresoc.v:139820.3-139821.73"
wire $0\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:140881.3-140909.6"
- wire width 64 $0\dmi0_datasr__i$next[63:0]$6093
- attribute \src "libresoc.v:140120.3-140121.45"
+ attribute \src "libresoc.v:140545.3-140573.6"
+ wire width 64 $0\dmi0_datasr__i$next[63:0]$6041
+ attribute \src "libresoc.v:139784.3-139785.45"
wire width 64 $0\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:140481.3-140497.6"
- wire width 2 $0\dmi0_datasr__oe$next[1:0]$6027
- attribute \src "libresoc.v:140146.3-140147.47"
+ attribute \src "libresoc.v:140145.3-140161.6"
+ wire width 2 $0\dmi0_datasr__oe$next[1:0]$5975
+ attribute \src "libresoc.v:139810.3-139811.47"
wire width 2 $0\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:140498.3-140518.6"
- wire width 64 $0\dmi0_datasr_reg$next[63:0]$6031
- attribute \src "libresoc.v:140144.3-140145.47"
+ attribute \src "libresoc.v:140162.3-140182.6"
+ wire width 64 $0\dmi0_datasr_reg$next[63:0]$5979
+ attribute \src "libresoc.v:139808.3-139809.47"
wire width 64 $0\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:140463.3-140471.6"
- wire $0\dmi0_datasr_update_core$next[0:0]$6021
- attribute \src "libresoc.v:140150.3-140151.63"
+ attribute \src "libresoc.v:140127.3-140135.6"
+ wire $0\dmi0_datasr_update_core$next[0:0]$5969
+ attribute \src "libresoc.v:139814.3-139815.63"
wire $0\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:140472.3-140480.6"
- wire $0\dmi0_datasr_update_core_prev$next[0:0]$6024
- attribute \src "libresoc.v:140148.3-140149.73"
+ attribute \src "libresoc.v:140136.3-140144.6"
+ wire $0\dmi0_datasr_update_core_prev$next[0:0]$5972
+ attribute \src "libresoc.v:139812.3-139813.73"
wire $0\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $0\fsm_state$455$next[2:0]$6081
- attribute \src "libresoc.v:140124.3-140125.45"
- wire width 3 $0\fsm_state$455[2:0]$5927
- attribute \src "libresoc.v:139189.13-139189.35"
- wire width 3 $0\fsm_state$455[2:0]$6130
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $0\fsm_state$next[2:0]$6058
- attribute \src "libresoc.v:140132.3-140133.35"
+ attribute \src "libresoc.v:140465.3-140517.6"
+ wire width 3 $0\fsm_state$455$next[2:0]$6029
+ attribute \src "libresoc.v:139788.3-139789.45"
+ wire width 3 $0\fsm_state$455[2:0]$5875
+ attribute \src "libresoc.v:138853.13-138853.35"
+ wire width 3 $0\fsm_state$455[2:0]$6078
+ attribute \src "libresoc.v:140311.3-140363.6"
+ wire width 3 $0\fsm_state$next[2:0]$6006
+ attribute \src "libresoc.v:139796.3-139797.35"
wire width 3 $0\fsm_state[2:0]
- attribute \src "libresoc.v:138592.7-138592.20"
+ attribute \src "libresoc.v:138256.7-138256.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:140959.3-140979.6"
- wire width 130 $0\io_bd$next[129:0]$6113
- attribute \src "libresoc.v:140184.3-140185.27"
+ attribute \src "libresoc.v:140623.3-140643.6"
+ wire width 130 $0\io_bd$next[129:0]$6061
+ attribute \src "libresoc.v:139848.3-139849.27"
wire width 130 $0\io_bd[129:0]
- attribute \src "libresoc.v:140941.3-140958.6"
- wire width 130 $0\io_sr$next[129:0]$6109
- attribute \src "libresoc.v:140186.3-140187.27"
+ attribute \src "libresoc.v:140605.3-140622.6"
+ wire width 130 $0\io_sr$next[129:0]$6057
+ attribute \src "libresoc.v:139850.3-139851.27"
wire width 130 $0\io_sr[129:0]
- attribute \src "libresoc.v:140602.3-140646.6"
- wire width 29 $0\jtag_wb__adr$next[28:0]$6052
- attribute \src "libresoc.v:140134.3-140135.41"
+ attribute \src "libresoc.v:140266.3-140310.6"
+ wire width 29 $0\jtag_wb__adr$next[28:0]$6000
+ attribute \src "libresoc.v:139798.3-139799.41"
wire width 29 $0\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:140700.3-140726.6"
- wire width 64 $0\jtag_wb__dat_w$next[63:0]$6065
- attribute \src "libresoc.v:140130.3-140131.45"
+ attribute \src "libresoc.v:140364.3-140390.6"
+ wire width 64 $0\jtag_wb__dat_w$next[63:0]$6013
+ attribute \src "libresoc.v:139794.3-139795.45"
wire width 64 $0\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:140313.3-140329.6"
- wire $0\jtag_wb_addrsr__oe$next[0:0]$5982
- attribute \src "libresoc.v:140170.3-140171.53"
+ attribute \src "libresoc.v:139977.3-139993.6"
+ wire $0\jtag_wb_addrsr__oe$next[0:0]$5930
+ attribute \src "libresoc.v:139834.3-139835.53"
wire $0\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:140330.3-140350.6"
- wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5986
- attribute \src "libresoc.v:140168.3-140169.53"
+ attribute \src "libresoc.v:139994.3-140014.6"
+ wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5934
+ attribute \src "libresoc.v:139832.3-139833.53"
wire width 29 $0\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:140295.3-140303.6"
- wire $0\jtag_wb_addrsr_update_core$next[0:0]$5976
- attribute \src "libresoc.v:140174.3-140175.69"
+ attribute \src "libresoc.v:139959.3-139967.6"
+ wire $0\jtag_wb_addrsr_update_core$next[0:0]$5924
+ attribute \src "libresoc.v:139838.3-139839.69"
wire $0\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:140304.3-140312.6"
- wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979
- attribute \src "libresoc.v:140172.3-140173.79"
+ attribute \src "libresoc.v:139968.3-139976.6"
+ wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927
+ attribute \src "libresoc.v:139836.3-139837.79"
wire $0\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:140727.3-140755.6"
- wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6070
- attribute \src "libresoc.v:140128.3-140129.51"
+ attribute \src "libresoc.v:140391.3-140419.6"
+ wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6018
+ attribute \src "libresoc.v:139792.3-139793.51"
wire width 64 $0\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:140369.3-140385.6"
- wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5997
- attribute \src "libresoc.v:140162.3-140163.53"
+ attribute \src "libresoc.v:140033.3-140049.6"
+ wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5945
+ attribute \src "libresoc.v:139826.3-139827.53"
wire width 2 $0\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:140386.3-140406.6"
- wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6001
- attribute \src "libresoc.v:140160.3-140161.53"
+ attribute \src "libresoc.v:140050.3-140070.6"
+ wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5949
+ attribute \src "libresoc.v:139824.3-139825.53"
wire width 64 $0\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:140351.3-140359.6"
- wire $0\jtag_wb_datasr_update_core$next[0:0]$5991
- attribute \src "libresoc.v:140166.3-140167.69"
+ attribute \src "libresoc.v:140015.3-140023.6"
+ wire $0\jtag_wb_datasr_update_core$next[0:0]$5939
+ attribute \src "libresoc.v:139830.3-139831.69"
wire $0\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:140360.3-140368.6"
- wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994
- attribute \src "libresoc.v:140164.3-140165.79"
+ attribute \src "libresoc.v:140024.3-140032.6"
+ wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942
+ attribute \src "libresoc.v:139828.3-139829.79"
wire $0\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:140257.3-140273.6"
- wire $0\sr0__oe$next[0:0]$5967
- attribute \src "libresoc.v:140178.3-140179.31"
+ attribute \src "libresoc.v:139921.3-139937.6"
+ wire $0\sr0__oe$next[0:0]$5915
+ attribute \src "libresoc.v:139842.3-139843.31"
wire $0\sr0__oe[0:0]
- attribute \src "libresoc.v:140274.3-140294.6"
- wire width 3 $0\sr0_reg$next[2:0]$5971
- attribute \src "libresoc.v:140176.3-140177.31"
+ attribute \src "libresoc.v:139938.3-139958.6"
+ wire width 3 $0\sr0_reg$next[2:0]$5919
+ attribute \src "libresoc.v:139840.3-139841.31"
wire width 3 $0\sr0_reg[2:0]
- attribute \src "libresoc.v:140239.3-140247.6"
- wire $0\sr0_update_core$next[0:0]$5961
- attribute \src "libresoc.v:140182.3-140183.47"
+ attribute \src "libresoc.v:139903.3-139911.6"
+ wire $0\sr0_update_core$next[0:0]$5909
+ attribute \src "libresoc.v:139846.3-139847.47"
wire $0\sr0_update_core[0:0]
- attribute \src "libresoc.v:140248.3-140256.6"
- wire $0\sr0_update_core_prev$next[0:0]$5964
- attribute \src "libresoc.v:140180.3-140181.57"
+ attribute \src "libresoc.v:139912.3-139920.6"
+ wire $0\sr0_update_core_prev$next[0:0]$5912
+ attribute \src "libresoc.v:139844.3-139845.57"
wire $0\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:140931.3-140940.6"
+ attribute \src "libresoc.v:140595.3-140604.6"
wire width 3 $0\sr5__i[2:0]
- attribute \src "libresoc.v:140537.3-140553.6"
- wire $0\sr5__oe$next[0:0]$6042
- attribute \src "libresoc.v:140138.3-140139.31"
+ attribute \src "libresoc.v:140201.3-140217.6"
+ wire $0\sr5__oe$next[0:0]$5990
+ attribute \src "libresoc.v:139802.3-139803.31"
wire $0\sr5__oe[0:0]
- attribute \src "libresoc.v:140554.3-140574.6"
- wire width 3 $0\sr5_reg$next[2:0]$6046
- attribute \src "libresoc.v:140136.3-140137.31"
+ attribute \src "libresoc.v:140218.3-140238.6"
+ wire width 3 $0\sr5_reg$next[2:0]$5994
+ attribute \src "libresoc.v:139800.3-139801.31"
wire width 3 $0\sr5_reg[2:0]
- attribute \src "libresoc.v:140519.3-140527.6"
- wire $0\sr5_update_core$next[0:0]$6036
- attribute \src "libresoc.v:140142.3-140143.47"
+ attribute \src "libresoc.v:140183.3-140191.6"
+ wire $0\sr5_update_core$next[0:0]$5984
+ attribute \src "libresoc.v:139806.3-139807.47"
wire $0\sr5_update_core[0:0]
- attribute \src "libresoc.v:140528.3-140536.6"
- wire $0\sr5_update_core_prev$next[0:0]$6039
- attribute \src "libresoc.v:140140.3-140141.57"
+ attribute \src "libresoc.v:140192.3-140200.6"
+ wire $0\sr5_update_core_prev$next[0:0]$5987
+ attribute \src "libresoc.v:139804.3-139805.57"
wire $0\sr5_update_core_prev[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $0\wb_dcache_en$next[0:0]$6098
- attribute \src "libresoc.v:140116.3-140117.41"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $0\wb_dcache_en$next[0:0]$6046
+ attribute \src "libresoc.v:139780.3-139781.41"
wire $0\wb_dcache_en[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $0\wb_icache_en$next[0:0]$6099
- attribute \src "libresoc.v:140114.3-140115.41"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $0\wb_icache_en$next[0:0]$6047
+ attribute \src "libresoc.v:139778.3-139779.41"
wire $0\wb_icache_en[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $0\wb_sram_en$next[0:0]$6100
- attribute \src "libresoc.v:140118.3-140119.37"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $0\wb_sram_en$next[0:0]$6048
+ attribute \src "libresoc.v:139782.3-139783.37"
wire $0\wb_sram_en[0:0]
- attribute \src "libresoc.v:140575.3-140601.6"
+ attribute \src "libresoc.v:140239.3-140265.6"
wire $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:140223.3-140238.6"
+ attribute \src "libresoc.v:139887.3-139902.6"
wire $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:140756.3-140800.6"
- wire width 4 $1\dmi0__addr_i$next[3:0]$6076
- attribute \src "libresoc.v:139102.13-139102.32"
+ attribute \src "libresoc.v:140420.3-140464.6"
+ wire width 4 $1\dmi0__addr_i$next[3:0]$6024
+ attribute \src "libresoc.v:138766.13-138766.32"
wire width 4 $1\dmi0__addr_i[3:0]
- attribute \src "libresoc.v:140854.3-140880.6"
- wire width 64 $1\dmi0__din$next[63:0]$6089
- attribute \src "libresoc.v:139107.14-139107.46"
+ attribute \src "libresoc.v:140518.3-140544.6"
+ wire width 64 $1\dmi0__din$next[63:0]$6037
+ attribute \src "libresoc.v:138771.14-138771.46"
wire width 64 $1\dmi0__din[63:0]
- attribute \src "libresoc.v:140425.3-140441.6"
- wire $1\dmi0_addrsr__oe$next[0:0]$6013
- attribute \src "libresoc.v:139121.7-139121.29"
+ attribute \src "libresoc.v:140089.3-140105.6"
+ wire $1\dmi0_addrsr__oe$next[0:0]$5961
+ attribute \src "libresoc.v:138785.7-138785.29"
wire $1\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:140442.3-140462.6"
- wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6017
- attribute \src "libresoc.v:139129.13-139129.36"
+ attribute \src "libresoc.v:140106.3-140126.6"
+ wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5965
+ attribute \src "libresoc.v:138793.13-138793.36"
wire width 8 $1\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:140407.3-140415.6"
- wire $1\dmi0_addrsr_update_core$next[0:0]$6007
- attribute \src "libresoc.v:139137.7-139137.37"
+ attribute \src "libresoc.v:140071.3-140079.6"
+ wire $1\dmi0_addrsr_update_core$next[0:0]$5955
+ attribute \src "libresoc.v:138801.7-138801.37"
wire $1\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:140416.3-140424.6"
- wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6010
- attribute \src "libresoc.v:139141.7-139141.42"
+ attribute \src "libresoc.v:140080.3-140088.6"
+ wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5958
+ attribute \src "libresoc.v:138805.7-138805.42"
wire $1\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:140881.3-140909.6"
- wire width 64 $1\dmi0_datasr__i$next[63:0]$6094
- attribute \src "libresoc.v:139145.14-139145.51"
+ attribute \src "libresoc.v:140545.3-140573.6"
+ wire width 64 $1\dmi0_datasr__i$next[63:0]$6042
+ attribute \src "libresoc.v:138809.14-138809.51"
wire width 64 $1\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:140481.3-140497.6"
- wire width 2 $1\dmi0_datasr__oe$next[1:0]$6028
- attribute \src "libresoc.v:139151.13-139151.35"
+ attribute \src "libresoc.v:140145.3-140161.6"
+ wire width 2 $1\dmi0_datasr__oe$next[1:0]$5976
+ attribute \src "libresoc.v:138815.13-138815.35"
wire width 2 $1\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:140498.3-140518.6"
- wire width 64 $1\dmi0_datasr_reg$next[63:0]$6032
- attribute \src "libresoc.v:139159.14-139159.52"
+ attribute \src "libresoc.v:140162.3-140182.6"
+ wire width 64 $1\dmi0_datasr_reg$next[63:0]$5980
+ attribute \src "libresoc.v:138823.14-138823.52"
wire width 64 $1\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:140463.3-140471.6"
- wire $1\dmi0_datasr_update_core$next[0:0]$6022
- attribute \src "libresoc.v:139167.7-139167.37"
+ attribute \src "libresoc.v:140127.3-140135.6"
+ wire $1\dmi0_datasr_update_core$next[0:0]$5970
+ attribute \src "libresoc.v:138831.7-138831.37"
wire $1\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:140472.3-140480.6"
- wire $1\dmi0_datasr_update_core_prev$next[0:0]$6025
- attribute \src "libresoc.v:139171.7-139171.42"
+ attribute \src "libresoc.v:140136.3-140144.6"
+ wire $1\dmi0_datasr_update_core_prev$next[0:0]$5973
+ attribute \src "libresoc.v:138835.7-138835.42"
wire $1\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $1\fsm_state$455$next[2:0]$6082
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $1\fsm_state$next[2:0]$6059
- attribute \src "libresoc.v:139187.13-139187.29"
+ attribute \src "libresoc.v:140465.3-140517.6"
+ wire width 3 $1\fsm_state$455$next[2:0]$6030
+ attribute \src "libresoc.v:140311.3-140363.6"
+ wire width 3 $1\fsm_state$next[2:0]$6007
+ attribute \src "libresoc.v:138851.13-138851.29"
wire width 3 $1\fsm_state[2:0]
- attribute \src "libresoc.v:140959.3-140979.6"
- wire width 130 $1\io_bd$next[129:0]$6114
- attribute \src "libresoc.v:139387.15-139387.61"
+ attribute \src "libresoc.v:140623.3-140643.6"
+ wire width 130 $1\io_bd$next[129:0]$6062
+ attribute \src "libresoc.v:139051.15-139051.61"
wire width 130 $1\io_bd[129:0]
- attribute \src "libresoc.v:140941.3-140958.6"
- wire width 130 $1\io_sr$next[129:0]$6110
- attribute \src "libresoc.v:139399.15-139399.61"
+ attribute \src "libresoc.v:140605.3-140622.6"
+ wire width 130 $1\io_sr$next[129:0]$6058
+ attribute \src "libresoc.v:139063.15-139063.61"
wire width 130 $1\io_sr[129:0]
- attribute \src "libresoc.v:140602.3-140646.6"
- wire width 29 $1\jtag_wb__adr$next[28:0]$6053
- attribute \src "libresoc.v:139408.14-139408.41"
+ attribute \src "libresoc.v:140266.3-140310.6"
+ wire width 29 $1\jtag_wb__adr$next[28:0]$6001
+ attribute \src "libresoc.v:139072.14-139072.41"
wire width 29 $1\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:140700.3-140726.6"
- wire width 64 $1\jtag_wb__dat_w$next[63:0]$6066
- attribute \src "libresoc.v:139417.14-139417.51"
+ attribute \src "libresoc.v:140364.3-140390.6"
+ wire width 64 $1\jtag_wb__dat_w$next[63:0]$6014
+ attribute \src "libresoc.v:139081.14-139081.51"
wire width 64 $1\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:140313.3-140329.6"
- wire $1\jtag_wb_addrsr__oe$next[0:0]$5983
- attribute \src "libresoc.v:139431.7-139431.32"
+ attribute \src "libresoc.v:139977.3-139993.6"
+ wire $1\jtag_wb_addrsr__oe$next[0:0]$5931
+ attribute \src "libresoc.v:139095.7-139095.32"
wire $1\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:140330.3-140350.6"
- wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5987
- attribute \src "libresoc.v:139439.14-139439.47"
+ attribute \src "libresoc.v:139994.3-140014.6"
+ wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5935
+ attribute \src "libresoc.v:139103.14-139103.47"
wire width 29 $1\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:140295.3-140303.6"
- wire $1\jtag_wb_addrsr_update_core$next[0:0]$5977
- attribute \src "libresoc.v:139447.7-139447.40"
+ attribute \src "libresoc.v:139959.3-139967.6"
+ wire $1\jtag_wb_addrsr_update_core$next[0:0]$5925
+ attribute \src "libresoc.v:139111.7-139111.40"
wire $1\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:140304.3-140312.6"
- wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980
- attribute \src "libresoc.v:139451.7-139451.45"
+ attribute \src "libresoc.v:139968.3-139976.6"
+ wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928
+ attribute \src "libresoc.v:139115.7-139115.45"
wire $1\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:140727.3-140755.6"
- wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6071
- attribute \src "libresoc.v:139455.14-139455.54"
+ attribute \src "libresoc.v:140391.3-140419.6"
+ wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6019
+ attribute \src "libresoc.v:139119.14-139119.54"
wire width 64 $1\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:140369.3-140385.6"
- wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5998
- attribute \src "libresoc.v:139461.13-139461.38"
+ attribute \src "libresoc.v:140033.3-140049.6"
+ wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5946
+ attribute \src "libresoc.v:139125.13-139125.38"
wire width 2 $1\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:140386.3-140406.6"
- wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6002
- attribute \src "libresoc.v:139469.14-139469.55"
+ attribute \src "libresoc.v:140050.3-140070.6"
+ wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5950
+ attribute \src "libresoc.v:139133.14-139133.55"
wire width 64 $1\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:140351.3-140359.6"
- wire $1\jtag_wb_datasr_update_core$next[0:0]$5992
- attribute \src "libresoc.v:139477.7-139477.40"
+ attribute \src "libresoc.v:140015.3-140023.6"
+ wire $1\jtag_wb_datasr_update_core$next[0:0]$5940
+ attribute \src "libresoc.v:139141.7-139141.40"
wire $1\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:140360.3-140368.6"
- wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995
- attribute \src "libresoc.v:139481.7-139481.45"
+ attribute \src "libresoc.v:140024.3-140032.6"
+ wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943
+ attribute \src "libresoc.v:139145.7-139145.45"
wire $1\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:140257.3-140273.6"
- wire $1\sr0__oe$next[0:0]$5968
- attribute \src "libresoc.v:139815.7-139815.21"
+ attribute \src "libresoc.v:139921.3-139937.6"
+ wire $1\sr0__oe$next[0:0]$5916
+ attribute \src "libresoc.v:139479.7-139479.21"
wire $1\sr0__oe[0:0]
- attribute \src "libresoc.v:140274.3-140294.6"
- wire width 3 $1\sr0_reg$next[2:0]$5972
- attribute \src "libresoc.v:139823.13-139823.27"
+ attribute \src "libresoc.v:139938.3-139958.6"
+ wire width 3 $1\sr0_reg$next[2:0]$5920
+ attribute \src "libresoc.v:139487.13-139487.27"
wire width 3 $1\sr0_reg[2:0]
- attribute \src "libresoc.v:140239.3-140247.6"
- wire $1\sr0_update_core$next[0:0]$5962
- attribute \src "libresoc.v:139831.7-139831.29"
+ attribute \src "libresoc.v:139903.3-139911.6"
+ wire $1\sr0_update_core$next[0:0]$5910
+ attribute \src "libresoc.v:139495.7-139495.29"
wire $1\sr0_update_core[0:0]
- attribute \src "libresoc.v:140248.3-140256.6"
- wire $1\sr0_update_core_prev$next[0:0]$5965
- attribute \src "libresoc.v:139835.7-139835.34"
+ attribute \src "libresoc.v:139912.3-139920.6"
+ wire $1\sr0_update_core_prev$next[0:0]$5913
+ attribute \src "libresoc.v:139499.7-139499.34"
wire $1\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:140931.3-140940.6"
+ attribute \src "libresoc.v:140595.3-140604.6"
wire width 3 $1\sr5__i[2:0]
- attribute \src "libresoc.v:140537.3-140553.6"
- wire $1\sr5__oe$next[0:0]$6043
- attribute \src "libresoc.v:139845.7-139845.21"
+ attribute \src "libresoc.v:140201.3-140217.6"
+ wire $1\sr5__oe$next[0:0]$5991
+ attribute \src "libresoc.v:139509.7-139509.21"
wire $1\sr5__oe[0:0]
- attribute \src "libresoc.v:140554.3-140574.6"
- wire width 3 $1\sr5_reg$next[2:0]$6047
- attribute \src "libresoc.v:139853.13-139853.27"
+ attribute \src "libresoc.v:140218.3-140238.6"
+ wire width 3 $1\sr5_reg$next[2:0]$5995
+ attribute \src "libresoc.v:139517.13-139517.27"
wire width 3 $1\sr5_reg[2:0]
- attribute \src "libresoc.v:140519.3-140527.6"
- wire $1\sr5_update_core$next[0:0]$6037
- attribute \src "libresoc.v:139861.7-139861.29"
+ attribute \src "libresoc.v:140183.3-140191.6"
+ wire $1\sr5_update_core$next[0:0]$5985
+ attribute \src "libresoc.v:139525.7-139525.29"
wire $1\sr5_update_core[0:0]
- attribute \src "libresoc.v:140528.3-140536.6"
- wire $1\sr5_update_core_prev$next[0:0]$6040
- attribute \src "libresoc.v:139865.7-139865.34"
+ attribute \src "libresoc.v:140192.3-140200.6"
+ wire $1\sr5_update_core_prev$next[0:0]$5988
+ attribute \src "libresoc.v:139529.7-139529.34"
wire $1\sr5_update_core_prev[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $1\wb_dcache_en$next[0:0]$6101
- attribute \src "libresoc.v:139870.7-139870.26"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $1\wb_dcache_en$next[0:0]$6049
+ attribute \src "libresoc.v:139534.7-139534.26"
wire $1\wb_dcache_en[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $1\wb_icache_en$next[0:0]$6102
- attribute \src "libresoc.v:139875.7-139875.26"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $1\wb_icache_en$next[0:0]$6050
+ attribute \src "libresoc.v:139539.7-139539.26"
wire $1\wb_icache_en[0:0]
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $1\wb_sram_en$next[0:0]$6103
- attribute \src "libresoc.v:139879.7-139879.24"
+ attribute \src "libresoc.v:140574.3-140594.6"
+ wire $1\wb_sram_en$next[0:0]$6051
+ attribute \src "libresoc.v:139543.7-139543.24"
wire $1\wb_sram_en[0:0]
- attribute \src "libresoc.v:140756.3-140800.6"
- wire width 4 $2\dmi0__addr_i$next[3:0]$6077
- attribute \src "libresoc.v:140854.3-140880.6"
- wire width 64 $2\dmi0__din$next[63:0]$6090
- attribute \src "libresoc.v:140425.3-140441.6"
- wire $2\dmi0_addrsr__oe$next[0:0]$6014
- attribute \src "libresoc.v:140442.3-140462.6"
- wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6018
- attribute \src "libresoc.v:140881.3-140909.6"
- wire width 64 $2\dmi0_datasr__i$next[63:0]$6095
- attribute \src "libresoc.v:140481.3-140497.6"
- wire width 2 $2\dmi0_datasr__oe$next[1:0]$6029
- attribute \src "libresoc.v:140498.3-140518.6"
- wire width 64 $2\dmi0_datasr_reg$next[63:0]$6033
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $2\fsm_state$455$next[2:0]$6083
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $2\fsm_state$next[2:0]$6060
- attribute \src "libresoc.v:140959.3-140979.6"
- wire width 130 $2\io_bd$next[129:0]$6115
- attribute \src "libresoc.v:140941.3-140958.6"
- wire width 130 $2\io_sr$next[129:0]$6111
- attribute \src "libresoc.v:140602.3-140646.6"
- wire width 29 $2\jtag_wb__adr$next[28:0]$6054
- attribute \src "libresoc.v:140700.3-140726.6"
- wire width 64 $2\jtag_wb__dat_w$next[63:0]$6067
- attribute \src "libresoc.v:140313.3-140329.6"
- wire $2\jtag_wb_addrsr__oe$next[0:0]$5984
- attribute \src "libresoc.v:140330.3-140350.6"
- wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5988
- attribute \src "libresoc.v:140727.3-140755.6"
- wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6072
- attribute \src "libresoc.v:140369.3-140385.6"
- wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5999
- attribute \src "libresoc.v:140386.3-140406.6"
- wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6003
- attribute \src "libresoc.v:140257.3-140273.6"
- wire $2\sr0__oe$next[0:0]$5969
- attribute \src "libresoc.v:140274.3-140294.6"
- wire width 3 $2\sr0_reg$next[2:0]$5973
- attribute \src "libresoc.v:140537.3-140553.6"
- wire $2\sr5__oe$next[0:0]$6044
- attribute \src "libresoc.v:140554.3-140574.6"
- wire width 3 $2\sr5_reg$next[2:0]$6048
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $2\wb_dcache_en$next[0:0]$6104
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $2\wb_icache_en$next[0:0]$6105
- attribute \src "libresoc.v:140910.3-140930.6"
- wire $2\wb_sram_en$next[0:0]$6106
- attribute \src "libresoc.v:140756.3-140800.6"
- wire width 4 $3\dmi0__addr_i$next[3:0]$6078
- attribute \src "libresoc.v:140854.3-140880.6"
- wire width 64 $3\dmi0__din$next[63:0]$6091
- attribute \src "libresoc.v:140442.3-140462.6"
- wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6019
- attribute \src "libresoc.v:140881.3-140909.6"
- wire width 64 $3\dmi0_datasr__i$next[63:0]$6096
- attribute \src "libresoc.v:140498.3-140518.6"
- wire width 64 $3\dmi0_datasr_reg$next[63:0]$6034
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $3\fsm_state$455$next[2:0]$6084
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $3\fsm_state$next[2:0]$6061
- attribute \src "libresoc.v:140602.3-140646.6"
- wire width 29 $3\jtag_wb__adr$next[28:0]$6055
- attribute \src "libresoc.v:140700.3-140726.6"
- wire width 64 $3\jtag_wb__dat_w$next[63:0]$6068
- attribute \src "libresoc.v:140330.3-140350.6"
- wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5989
- attribute \src "libresoc.v:140727.3-140755.6"
- wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6073
- attribute \src "libresoc.v:140386.3-140406.6"
- wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6004
- attribute \src "libresoc.v:140274.3-140294.6"
- wire width 3 $3\sr0_reg$next[2:0]$5974
- attribute \src "libresoc.v:140554.3-140574.6"
- wire width 3 $3\sr5_reg$next[2:0]$6049
- attribute \src "libresoc.v:140756.3-140800.6"
- wire width 4 $4\dmi0__addr_i$next[3:0]$6079
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $4\fsm_state$455$next[2:0]$6085
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $4\fsm_state$next[2:0]$6062
- attribute \src "libresoc.v:140602.3-140646.6"
- wire width 29 $4\jtag_wb__adr$next[28:0]$6056
- attribute \src "libresoc.v:140801.3-140853.6"
- wire width 3 $5\fsm_state$455$next[2:0]$6086
- attribute \src "libresoc.v:140647.3-140699.6"
- wire width 3 $5\fsm_state$next[2:0]$6063
- attribute \src "libresoc.v:140076.19-140076.112"
- wire width 30 $add$libresoc.v:140076$5882_Y
- attribute \src "libresoc.v:140077.19-140077.112"
- wire width 30 $add$libresoc.v:140077$5883_Y
- attribute \src "libresoc.v:140084.19-140084.112"
- wire width 5 $add$libresoc.v:140084$5891_Y
- attribute \src "libresoc.v:140085.19-140085.112"
- wire width 5 $add$libresoc.v:140085$5892_Y
- attribute \src "libresoc.v:139926.18-139926.112"
- wire $and$libresoc.v:139926$5732_Y
- attribute \src "libresoc.v:139993.18-139993.108"
- wire $and$libresoc.v:139993$5799_Y
- attribute \src "libresoc.v:140004.18-140004.110"
- wire $and$libresoc.v:140004$5810_Y
- attribute \src "libresoc.v:140006.19-140006.110"
- wire $and$libresoc.v:140006$5812_Y
- attribute \src "libresoc.v:140009.19-140009.114"
- wire $and$libresoc.v:140009$5815_Y
- attribute \src "libresoc.v:140011.19-140011.112"
- wire $and$libresoc.v:140011$5817_Y
- attribute \src "libresoc.v:140013.19-140013.113"
- wire $and$libresoc.v:140013$5819_Y
- attribute \src "libresoc.v:140016.19-140016.121"
- wire $and$libresoc.v:140016$5822_Y
- attribute \src "libresoc.v:140019.19-140019.114"
- wire $and$libresoc.v:140019$5825_Y
- attribute \src "libresoc.v:140021.19-140021.112"
- wire $and$libresoc.v:140021$5827_Y
- attribute \src "libresoc.v:140023.19-140023.113"
- wire $and$libresoc.v:140023$5829_Y
- attribute \src "libresoc.v:140025.19-140025.132"
- wire $and$libresoc.v:140025$5831_Y
- attribute \src "libresoc.v:140030.19-140030.114"
- wire $and$libresoc.v:140030$5836_Y
- attribute \src "libresoc.v:140032.19-140032.112"
- wire $and$libresoc.v:140032$5838_Y
- attribute \src "libresoc.v:140034.19-140034.113"
- wire $and$libresoc.v:140034$5840_Y
- attribute \src "libresoc.v:140036.19-140036.132"
- wire $and$libresoc.v:140036$5842_Y
- attribute \src "libresoc.v:140040.19-140040.114"
- wire $and$libresoc.v:140040$5846_Y
- attribute \src "libresoc.v:140042.19-140042.112"
- wire $and$libresoc.v:140042$5848_Y
- attribute \src "libresoc.v:140044.19-140044.113"
- wire $and$libresoc.v:140044$5850_Y
- attribute \src "libresoc.v:140046.19-140046.129"
- wire $and$libresoc.v:140046$5852_Y
- attribute \src "libresoc.v:140052.19-140052.114"
- wire $and$libresoc.v:140052$5858_Y
- attribute \src "libresoc.v:140054.19-140054.112"
- wire $and$libresoc.v:140054$5860_Y
- attribute \src "libresoc.v:140056.19-140056.113"
- wire $and$libresoc.v:140056$5862_Y
- attribute \src "libresoc.v:140058.19-140058.129"
- wire $and$libresoc.v:140058$5864_Y
- attribute \src "libresoc.v:140062.19-140062.114"
- wire $and$libresoc.v:140062$5868_Y
- attribute \src "libresoc.v:140064.19-140064.112"
- wire $and$libresoc.v:140064$5870_Y
- attribute \src "libresoc.v:140066.19-140066.113"
- wire $and$libresoc.v:140066$5872_Y
- attribute \src "libresoc.v:140068.19-140068.121"
- wire $and$libresoc.v:140068$5874_Y
- attribute \src "libresoc.v:140071.18-140071.108"
- wire $and$libresoc.v:140071$5877_Y
- attribute \src "libresoc.v:140081.18-140081.111"
- wire $and$libresoc.v:140081$5888_Y
- attribute \src "libresoc.v:140103.17-140103.106"
- wire $and$libresoc.v:140103$5910_Y
- attribute \src "libresoc.v:139882.17-139882.110"
- wire $eq$libresoc.v:139882$5688_Y
- attribute \src "libresoc.v:139893.18-139893.111"
- wire $eq$libresoc.v:139893$5699_Y
- attribute \src "libresoc.v:139904.18-139904.111"
- wire $eq$libresoc.v:139904$5710_Y
- attribute \src "libresoc.v:139937.17-139937.110"
- wire $eq$libresoc.v:139937$5743_Y
- attribute \src "libresoc.v:139938.18-139938.111"
- wire $eq$libresoc.v:139938$5744_Y
- attribute \src "libresoc.v:139949.18-139949.111"
- wire $eq$libresoc.v:139949$5755_Y
- attribute \src "libresoc.v:139971.18-139971.111"
- wire $eq$libresoc.v:139971$5777_Y
- attribute \src "libresoc.v:140000.19-140000.112"
- wire $eq$libresoc.v:140000$5806_Y
- attribute \src "libresoc.v:140001.19-140001.112"
- wire $eq$libresoc.v:140001$5807_Y
- attribute \src "libresoc.v:140003.19-140003.112"
- wire $eq$libresoc.v:140003$5809_Y
- attribute \src "libresoc.v:140007.19-140007.112"
- wire $eq$libresoc.v:140007$5813_Y
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- wire $ternary$libresoc.v:140104$5911_Y
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- wire $ternary$libresoc.v:140105$5912_Y
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- wire $ternary$libresoc.v:140106$5913_Y
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- wire $ternary$libresoc.v:140107$5914_Y
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- wire $ternary$libresoc.v:140108$5915_Y
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- wire $ternary$libresoc.v:140109$5916_Y
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- wire $ternary$libresoc.v:140110$5917_Y
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- wire $ternary$libresoc.v:140111$5918_Y
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- wire $ternary$libresoc.v:140112$5919_Y
- attribute \src "libresoc.v:140113.18-140113.133"
- wire $ternary$libresoc.v:140113$5920_Y
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+ wire width 64 $2\dmi0__din$next[63:0]$6038
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+ wire width 64 $2\dmi0_datasr__i$next[63:0]$6043
+ attribute \src "libresoc.v:140145.3-140161.6"
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+ attribute \src "libresoc.v:140162.3-140182.6"
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+ wire width 3 $2\fsm_state$next[2:0]$6008
+ attribute \src "libresoc.v:140623.3-140643.6"
+ wire width 130 $2\io_bd$next[129:0]$6063
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+ attribute \src "libresoc.v:140266.3-140310.6"
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+ attribute \src "libresoc.v:139977.3-139993.6"
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+ attribute \src "libresoc.v:140033.3-140049.6"
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+ attribute \src "libresoc.v:140050.3-140070.6"
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+ wire width 3 $3\sr0_reg$next[2:0]$5922
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+ wire width 29 $4\jtag_wb__adr$next[28:0]$6004
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+ wire $and$libresoc.v:139710$5800_Y
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+ wire $and$libresoc.v:139718$5808_Y
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+ wire $and$libresoc.v:139720$5810_Y
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+ wire $and$libresoc.v:139726$5816_Y
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+ wire $and$libresoc.v:139730$5820_Y
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+ wire $and$libresoc.v:139732$5822_Y
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+ wire $and$libresoc.v:139735$5825_Y
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+ wire $and$libresoc.v:139745$5836_Y
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+ wire $and$libresoc.v:139767$5858_Y
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+ wire $eq$libresoc.v:139557$5647_Y
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+ wire $eq$libresoc.v:139568$5658_Y
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+ wire $eq$libresoc.v:139601$5691_Y
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+ wire $eq$libresoc.v:139602$5692_Y
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+ wire $eq$libresoc.v:139613$5703_Y
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+ wire $eq$libresoc.v:139635$5725_Y
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+ wire $eq$libresoc.v:139664$5754_Y
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+ wire $eq$libresoc.v:139665$5755_Y
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+ wire $eq$libresoc.v:139667$5757_Y
+ attribute \src "libresoc.v:139671.19-139671.112"
+ wire $eq$libresoc.v:139671$5761_Y
+ attribute \src "libresoc.v:139679.18-139679.111"
+ wire $eq$libresoc.v:139679$5769_Y
+ attribute \src "libresoc.v:139681.19-139681.112"
+ wire $eq$libresoc.v:139681$5771_Y
+ attribute \src "libresoc.v:139690.18-139690.111"
+ wire $eq$libresoc.v:139690$5780_Y
+ attribute \src "libresoc.v:139691.19-139691.112"
+ wire $eq$libresoc.v:139691$5781_Y
+ attribute \src "libresoc.v:139692.19-139692.112"
+ wire $eq$libresoc.v:139692$5782_Y
+ attribute \src "libresoc.v:139702.19-139702.112"
+ wire $eq$libresoc.v:139702$5792_Y
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+ wire $eq$libresoc.v:139711$5801_Y
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+ wire $eq$libresoc.v:139712$5802_Y
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+ wire $eq$libresoc.v:139713$5803_Y
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+ wire $eq$libresoc.v:139714$5804_Y
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+ wire $eq$libresoc.v:139723$5813_Y
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+ wire $eq$libresoc.v:139733$5823_Y
+ attribute \src "libresoc.v:139736.19-139736.110"
+ wire $eq$libresoc.v:139736$5826_Y
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+ wire $eq$libresoc.v:139737$5827_Y
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+ wire $eq$libresoc.v:139739$5829_Y
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+ wire $eq$libresoc.v:139743$5834_Y
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+ wire $eq$libresoc.v:139744$5835_Y
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+ wire $eq$libresoc.v:139747$5838_Y
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+ wire $eq$libresoc.v:139750$5841_Y
+ attribute \src "libresoc.v:139751.18-139751.111"
+ wire $eq$libresoc.v:139751$5842_Y
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+ wire width 8 $extend$libresoc.v:139742$5832_Y
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+ wire $ne$libresoc.v:139672$5762_Y
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+ wire $ne$libresoc.v:139674$5764_Y
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+ wire $ne$libresoc.v:139676$5766_Y
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+ wire $ne$libresoc.v:139682$5772_Y
+ attribute \src "libresoc.v:139684.19-139684.120"
+ wire $ne$libresoc.v:139684$5774_Y
+ attribute \src "libresoc.v:139686.19-139686.120"
+ wire $ne$libresoc.v:139686$5776_Y
+ attribute \src "libresoc.v:139693.19-139693.120"
+ wire $ne$libresoc.v:139693$5783_Y
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+ wire $ne$libresoc.v:139695$5785_Y
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+ wire $ne$libresoc.v:139697$5787_Y
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+ wire $ne$libresoc.v:139703$5793_Y
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+ wire $ne$libresoc.v:139705$5795_Y
+ attribute \src "libresoc.v:139707.19-139707.117"
+ wire $ne$libresoc.v:139707$5797_Y
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+ wire $ne$libresoc.v:139715$5805_Y
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+ wire $ne$libresoc.v:139717$5807_Y
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+ wire $ne$libresoc.v:139719$5809_Y
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+ wire $ne$libresoc.v:139725$5815_Y
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+ wire $ne$libresoc.v:139727$5817_Y
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+ wire $ne$libresoc.v:139729$5819_Y
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+ wire $not$libresoc.v:139678$5768_Y
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+ wire $not$libresoc.v:139688$5778_Y
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+ wire $not$libresoc.v:139699$5789_Y
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+ wire $not$libresoc.v:139709$5799_Y
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+ wire $not$libresoc.v:139721$5811_Y
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+ wire $not$libresoc.v:139731$5821_Y
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+ wire $not$libresoc.v:139734$5824_Y
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+ wire $or$libresoc.v:139579$5669_Y
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+ wire $or$libresoc.v:139624$5714_Y
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+ wire $or$libresoc.v:139646$5736_Y
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+ wire $or$libresoc.v:139666$5756_Y
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+ wire $or$libresoc.v:139669$5759_Y
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+ wire $or$libresoc.v:139701$5791_Y
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+ wire $or$libresoc.v:139724$5814_Y
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+ wire $or$libresoc.v:139738$5828_Y
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+ wire $or$libresoc.v:139746$5837_Y
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+ wire $ternary$libresoc.v:139549$5639_Y
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+ wire $ternary$libresoc.v:139551$5641_Y
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+ wire $ternary$libresoc.v:139552$5642_Y
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+ wire $ternary$libresoc.v:139553$5643_Y
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+ wire $ternary$libresoc.v:139554$5644_Y
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+ wire $ternary$libresoc.v:139555$5645_Y
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+ wire $ternary$libresoc.v:139556$5646_Y
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+ wire $ternary$libresoc.v:139558$5648_Y
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+ wire $ternary$libresoc.v:139559$5649_Y
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+ wire $ternary$libresoc.v:139560$5650_Y
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+ wire $ternary$libresoc.v:139561$5651_Y
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+ wire $ternary$libresoc.v:139562$5652_Y
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+ wire $ternary$libresoc.v:139563$5653_Y
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+ wire $ternary$libresoc.v:139564$5654_Y
+ attribute \src "libresoc.v:139565.19-139565.133"
+ wire $ternary$libresoc.v:139565$5655_Y
+ attribute \src "libresoc.v:139566.19-139566.133"
+ wire $ternary$libresoc.v:139566$5656_Y
+ attribute \src "libresoc.v:139567.19-139567.132"
+ wire $ternary$libresoc.v:139567$5657_Y
+ attribute \src "libresoc.v:139569.19-139569.133"
+ wire $ternary$libresoc.v:139569$5659_Y
+ attribute \src "libresoc.v:139570.19-139570.133"
+ wire $ternary$libresoc.v:139570$5660_Y
+ attribute \src "libresoc.v:139571.19-139571.132"
+ wire $ternary$libresoc.v:139571$5661_Y
+ attribute \src "libresoc.v:139572.19-139572.133"
+ wire $ternary$libresoc.v:139572$5662_Y
+ attribute \src "libresoc.v:139573.19-139573.133"
+ wire $ternary$libresoc.v:139573$5663_Y
+ attribute \src "libresoc.v:139574.19-139574.132"
+ wire $ternary$libresoc.v:139574$5664_Y
+ attribute \src "libresoc.v:139575.19-139575.133"
+ wire $ternary$libresoc.v:139575$5665_Y
+ attribute \src "libresoc.v:139576.19-139576.134"
+ wire $ternary$libresoc.v:139576$5666_Y
+ attribute \src "libresoc.v:139577.19-139577.135"
+ wire $ternary$libresoc.v:139577$5667_Y
+ attribute \src "libresoc.v:139578.19-139578.135"
+ wire $ternary$libresoc.v:139578$5668_Y
+ attribute \src "libresoc.v:139580.19-139580.136"
+ wire $ternary$libresoc.v:139580$5670_Y
+ attribute \src "libresoc.v:139581.19-139581.134"
+ wire $ternary$libresoc.v:139581$5671_Y
+ attribute \src "libresoc.v:139582.19-139582.133"
+ wire $ternary$libresoc.v:139582$5672_Y
+ attribute \src "libresoc.v:139583.19-139583.134"
+ wire $ternary$libresoc.v:139583$5673_Y
+ attribute \src "libresoc.v:139584.19-139584.133"
+ wire $ternary$libresoc.v:139584$5674_Y
+ attribute \src "libresoc.v:139585.19-139585.133"
+ wire $ternary$libresoc.v:139585$5675_Y
+ attribute \src "libresoc.v:139586.19-139586.134"
+ wire $ternary$libresoc.v:139586$5676_Y
+ attribute \src "libresoc.v:139587.19-139587.133"
+ wire $ternary$libresoc.v:139587$5677_Y
+ attribute \src "libresoc.v:139588.19-139588.134"
+ wire $ternary$libresoc.v:139588$5678_Y
+ attribute \src "libresoc.v:139589.19-139589.134"
+ wire $ternary$libresoc.v:139589$5679_Y
+ attribute \src "libresoc.v:139591.19-139591.133"
+ wire $ternary$libresoc.v:139591$5681_Y
+ attribute \src "libresoc.v:139592.19-139592.134"
+ wire $ternary$libresoc.v:139592$5682_Y
+ attribute \src "libresoc.v:139593.19-139593.134"
+ wire $ternary$libresoc.v:139593$5683_Y
+ attribute \src "libresoc.v:139594.19-139594.133"
+ wire $ternary$libresoc.v:139594$5684_Y
+ attribute \src "libresoc.v:139595.19-139595.134"
+ wire $ternary$libresoc.v:139595$5685_Y
+ attribute \src "libresoc.v:139596.19-139596.134"
+ wire $ternary$libresoc.v:139596$5686_Y
+ attribute \src "libresoc.v:139597.19-139597.133"
+ wire $ternary$libresoc.v:139597$5687_Y
+ attribute \src "libresoc.v:139598.19-139598.134"
+ wire $ternary$libresoc.v:139598$5688_Y
+ attribute \src "libresoc.v:139599.19-139599.134"
+ wire $ternary$libresoc.v:139599$5689_Y
+ attribute \src "libresoc.v:139600.19-139600.133"
+ wire $ternary$libresoc.v:139600$5690_Y
+ attribute \src "libresoc.v:139603.19-139603.134"
+ wire $ternary$libresoc.v:139603$5693_Y
+ attribute \src "libresoc.v:139604.19-139604.134"
+ wire $ternary$libresoc.v:139604$5694_Y
+ attribute \src "libresoc.v:139605.19-139605.133"
+ wire $ternary$libresoc.v:139605$5695_Y
+ attribute \src "libresoc.v:139606.19-139606.134"
+ wire $ternary$libresoc.v:139606$5696_Y
+ attribute \src "libresoc.v:139607.19-139607.134"
+ wire $ternary$libresoc.v:139607$5697_Y
+ attribute \src "libresoc.v:139608.19-139608.133"
+ wire $ternary$libresoc.v:139608$5698_Y
+ attribute \src "libresoc.v:139609.19-139609.134"
+ wire $ternary$libresoc.v:139609$5699_Y
+ attribute \src "libresoc.v:139610.19-139610.134"
+ wire $ternary$libresoc.v:139610$5700_Y
+ attribute \src "libresoc.v:139611.19-139611.133"
+ wire $ternary$libresoc.v:139611$5701_Y
+ attribute \src "libresoc.v:139612.19-139612.134"
+ wire $ternary$libresoc.v:139612$5702_Y
+ attribute \src "libresoc.v:139614.19-139614.132"
+ wire $ternary$libresoc.v:139614$5704_Y
+ attribute \src "libresoc.v:139615.19-139615.132"
+ wire $ternary$libresoc.v:139615$5705_Y
+ attribute \src "libresoc.v:139616.19-139616.132"
+ wire $ternary$libresoc.v:139616$5706_Y
+ attribute \src "libresoc.v:139617.19-139617.132"
+ wire $ternary$libresoc.v:139617$5707_Y
+ attribute \src "libresoc.v:139618.19-139618.132"
+ wire $ternary$libresoc.v:139618$5708_Y
+ attribute \src "libresoc.v:139619.19-139619.132"
+ wire $ternary$libresoc.v:139619$5709_Y
+ attribute \src "libresoc.v:139620.19-139620.132"
+ wire $ternary$libresoc.v:139620$5710_Y
+ attribute \src "libresoc.v:139621.19-139621.132"
+ wire $ternary$libresoc.v:139621$5711_Y
+ attribute \src "libresoc.v:139622.19-139622.132"
+ wire $ternary$libresoc.v:139622$5712_Y
+ attribute \src "libresoc.v:139623.19-139623.132"
+ wire $ternary$libresoc.v:139623$5713_Y
+ attribute \src "libresoc.v:139625.19-139625.133"
+ wire $ternary$libresoc.v:139625$5715_Y
+ attribute \src "libresoc.v:139626.19-139626.133"
+ wire $ternary$libresoc.v:139626$5716_Y
+ attribute \src "libresoc.v:139627.19-139627.134"
+ wire $ternary$libresoc.v:139627$5717_Y
+ attribute \src "libresoc.v:139628.19-139628.132"
+ wire $ternary$libresoc.v:139628$5718_Y
+ attribute \src "libresoc.v:139629.19-139629.134"
+ wire $ternary$libresoc.v:139629$5719_Y
+ attribute \src "libresoc.v:139630.19-139630.134"
+ wire $ternary$libresoc.v:139630$5720_Y
+ attribute \src "libresoc.v:139631.19-139631.134"
+ wire $ternary$libresoc.v:139631$5721_Y
+ attribute \src "libresoc.v:139632.19-139632.134"
+ wire $ternary$libresoc.v:139632$5722_Y
+ attribute \src "libresoc.v:139633.19-139633.134"
+ wire $ternary$libresoc.v:139633$5723_Y
+ attribute \src "libresoc.v:139634.19-139634.134"
+ wire $ternary$libresoc.v:139634$5724_Y
+ attribute \src "libresoc.v:139636.19-139636.134"
+ wire $ternary$libresoc.v:139636$5726_Y
+ attribute \src "libresoc.v:139637.19-139637.134"
+ wire $ternary$libresoc.v:139637$5727_Y
+ attribute \src "libresoc.v:139638.19-139638.135"
+ wire $ternary$libresoc.v:139638$5728_Y
+ attribute \src "libresoc.v:139639.19-139639.134"
+ wire $ternary$libresoc.v:139639$5729_Y
+ attribute \src "libresoc.v:139640.19-139640.135"
+ wire $ternary$libresoc.v:139640$5730_Y
+ attribute \src "libresoc.v:139641.19-139641.135"
+ wire $ternary$libresoc.v:139641$5731_Y
+ attribute \src "libresoc.v:139642.19-139642.134"
+ wire $ternary$libresoc.v:139642$5732_Y
+ attribute \src "libresoc.v:139643.19-139643.135"
+ wire $ternary$libresoc.v:139643$5733_Y
+ attribute \src "libresoc.v:139644.19-139644.136"
+ wire $ternary$libresoc.v:139644$5734_Y
+ attribute \src "libresoc.v:139645.19-139645.135"
+ wire $ternary$libresoc.v:139645$5735_Y
+ attribute \src "libresoc.v:139647.19-139647.136"
+ wire $ternary$libresoc.v:139647$5737_Y
+ attribute \src "libresoc.v:139648.19-139648.136"
+ wire $ternary$libresoc.v:139648$5738_Y
+ attribute \src "libresoc.v:139649.19-139649.135"
+ wire $ternary$libresoc.v:139649$5739_Y
+ attribute \src "libresoc.v:139650.19-139650.136"
+ wire $ternary$libresoc.v:139650$5740_Y
+ attribute \src "libresoc.v:139651.19-139651.136"
+ wire $ternary$libresoc.v:139651$5741_Y
+ attribute \src "libresoc.v:139652.19-139652.135"
+ wire $ternary$libresoc.v:139652$5742_Y
+ attribute \src "libresoc.v:139653.19-139653.136"
+ wire $ternary$libresoc.v:139653$5743_Y
+ attribute \src "libresoc.v:139654.19-139654.136"
+ wire $ternary$libresoc.v:139654$5744_Y
+ attribute \src "libresoc.v:139655.19-139655.135"
+ wire $ternary$libresoc.v:139655$5745_Y
+ attribute \src "libresoc.v:139656.19-139656.136"
+ wire $ternary$libresoc.v:139656$5746_Y
+ attribute \src "libresoc.v:139658.19-139658.136"
+ wire $ternary$libresoc.v:139658$5748_Y
+ attribute \src "libresoc.v:139659.19-139659.135"
+ wire $ternary$libresoc.v:139659$5749_Y
+ attribute \src "libresoc.v:139660.19-139660.136"
+ wire $ternary$libresoc.v:139660$5750_Y
+ attribute \src "libresoc.v:139661.19-139661.136"
+ wire $ternary$libresoc.v:139661$5751_Y
+ attribute \src "libresoc.v:139662.19-139662.135"
+ wire $ternary$libresoc.v:139662$5752_Y
+ attribute \src "libresoc.v:139663.19-139663.136"
+ wire $ternary$libresoc.v:139663$5753_Y
+ attribute \src "libresoc.v:139752.18-139752.130"
+ wire $ternary$libresoc.v:139752$5843_Y
+ attribute \src "libresoc.v:139753.18-139753.130"
+ wire $ternary$libresoc.v:139753$5844_Y
+ attribute \src "libresoc.v:139754.18-139754.130"
+ wire $ternary$libresoc.v:139754$5845_Y
+ attribute \src "libresoc.v:139755.18-139755.131"
+ wire $ternary$libresoc.v:139755$5846_Y
+ attribute \src "libresoc.v:139757.18-139757.130"
+ wire $ternary$libresoc.v:139757$5848_Y
+ attribute \src "libresoc.v:139758.18-139758.131"
+ wire $ternary$libresoc.v:139758$5849_Y
+ attribute \src "libresoc.v:139759.18-139759.131"
+ wire $ternary$libresoc.v:139759$5850_Y
+ attribute \src "libresoc.v:139760.18-139760.130"
+ wire $ternary$libresoc.v:139760$5851_Y
+ attribute \src "libresoc.v:139761.18-139761.131"
+ wire $ternary$libresoc.v:139761$5852_Y
+ attribute \src "libresoc.v:139762.18-139762.132"
+ wire $ternary$libresoc.v:139762$5853_Y
+ attribute \src "libresoc.v:139763.18-139763.132"
+ wire $ternary$libresoc.v:139763$5854_Y
+ attribute \src "libresoc.v:139764.18-139764.133"
+ wire $ternary$libresoc.v:139764$5855_Y
+ attribute \src "libresoc.v:139765.18-139765.133"
+ wire $ternary$libresoc.v:139765$5856_Y
+ attribute \src "libresoc.v:139766.18-139766.132"
+ wire $ternary$libresoc.v:139766$5857_Y
+ attribute \src "libresoc.v:139768.18-139768.133"
+ wire $ternary$libresoc.v:139768$5859_Y
+ attribute \src "libresoc.v:139769.18-139769.133"
+ wire $ternary$libresoc.v:139769$5860_Y
+ attribute \src "libresoc.v:139770.18-139770.132"
+ wire $ternary$libresoc.v:139770$5861_Y
+ attribute \src "libresoc.v:139771.18-139771.133"
+ wire $ternary$libresoc.v:139771$5862_Y
+ attribute \src "libresoc.v:139772.18-139772.133"
+ wire $ternary$libresoc.v:139772$5863_Y
+ attribute \src "libresoc.v:139773.18-139773.132"
+ wire $ternary$libresoc.v:139773$5864_Y
+ attribute \src "libresoc.v:139774.18-139774.133"
+ wire $ternary$libresoc.v:139774$5865_Y
+ attribute \src "libresoc.v:139775.18-139775.133"
+ wire $ternary$libresoc.v:139775$5866_Y
+ attribute \src "libresoc.v:139776.18-139776.132"
+ wire $ternary$libresoc.v:139776$5867_Y
+ attribute \src "libresoc.v:139777.18-139777.133"
+ wire $ternary$libresoc.v:139777$5868_Y
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
wire \$1
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
wire width 4 \_irblock_ir
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
wire \_irblock_tdo
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 282 \clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire input 6 \dmi0__ack_o
wire output 190 \gpio_s7__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 191 \gpio_s7__pad__oe
- attribute \src "libresoc.v:138592.7-138592.15"
+ attribute \src "libresoc.v:138256.7-138256.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549"
wire width 130 \io_bd
wire \posjtag_clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
wire \posjtag_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 94 \sdr_a_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95"
wire \wb_sram_en$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761"
- cell $add $add$libresoc.v:140076$5882
+ cell $add $add$libresoc.v:139740$5830
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:140076$5882_Y
+ connect \Y $add$libresoc.v:139740$5830_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786"
- cell $add $add$libresoc.v:140077$5883
+ cell $add $add$libresoc.v:139741$5831
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:140077$5883_Y
+ connect \Y $add$libresoc.v:139741$5831_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494"
- cell $add $add$libresoc.v:140084$5891
+ cell $add $add$libresoc.v:139748$5839
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0__addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:140084$5891_Y
+ connect \Y $add$libresoc.v:139748$5839_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518"
- cell $add $add$libresoc.v:140085$5892
+ cell $add $add$libresoc.v:139749$5840
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0__addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:140085$5892_Y
+ connect \Y $add$libresoc.v:139749$5840_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
- cell $and $and$libresoc.v:139926$5732
+ cell $and $and$libresoc.v:139590$5680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:139926$5732_Y
+ connect \Y $and$libresoc.v:139590$5680_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:139993$5799
+ cell $and $and$libresoc.v:139657$5747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$27
- connect \Y $and$libresoc.v:139993$5799_Y
+ connect \Y $and$libresoc.v:139657$5747_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402"
- cell $and $and$libresoc.v:140004$5810
+ cell $and $and$libresoc.v:139668$5758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140004$5810_Y
+ connect \Y $and$libresoc.v:139668$5758_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:140006$5812
+ cell $and $and$libresoc.v:139670$5760
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$319
- connect \Y $and$libresoc.v:140006$5812_Y
+ connect \Y $and$libresoc.v:139670$5760_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140009$5815
+ cell $and $and$libresoc.v:139673$5763
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$325
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140009$5815_Y
+ connect \Y $and$libresoc.v:139673$5763_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140011$5817
+ cell $and $and$libresoc.v:139675$5765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$329
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140011$5817_Y
+ connect \Y $and$libresoc.v:139675$5765_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140013$5819
+ cell $and $and$libresoc.v:139677$5767
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$333
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140013$5819_Y
+ connect \Y $and$libresoc.v:139677$5767_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140016$5822
+ cell $and $and$libresoc.v:139680$5770
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_update_core_prev
connect \B \$337
- connect \Y $and$libresoc.v:140016$5822_Y
+ connect \Y $and$libresoc.v:139680$5770_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140019$5825
+ cell $and $and$libresoc.v:139683$5773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$343
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140019$5825_Y
+ connect \Y $and$libresoc.v:139683$5773_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140021$5827
+ cell $and $and$libresoc.v:139685$5775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$347
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140021$5827_Y
+ connect \Y $and$libresoc.v:139685$5775_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140023$5829
+ cell $and $and$libresoc.v:139687$5777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$351
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140023$5829_Y
+ connect \Y $and$libresoc.v:139687$5777_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140025$5831
+ cell $and $and$libresoc.v:139689$5779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core_prev
connect \B \$355
- connect \Y $and$libresoc.v:140025$5831_Y
+ connect \Y $and$libresoc.v:139689$5779_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140030$5836
+ cell $and $and$libresoc.v:139694$5784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$363
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140030$5836_Y
+ connect \Y $and$libresoc.v:139694$5784_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140032$5838
+ cell $and $and$libresoc.v:139696$5786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$367
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140032$5838_Y
+ connect \Y $and$libresoc.v:139696$5786_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140034$5840
+ cell $and $and$libresoc.v:139698$5788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$371
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140034$5840_Y
+ connect \Y $and$libresoc.v:139698$5788_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140036$5842
+ cell $and $and$libresoc.v:139700$5790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core_prev
connect \B \$375
- connect \Y $and$libresoc.v:140036$5842_Y
+ connect \Y $and$libresoc.v:139700$5790_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140040$5846
+ cell $and $and$libresoc.v:139704$5794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$381
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140040$5846_Y
+ connect \Y $and$libresoc.v:139704$5794_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140042$5848
+ cell $and $and$libresoc.v:139706$5796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$385
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140042$5848_Y
+ connect \Y $and$libresoc.v:139706$5796_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140044$5850
+ cell $and $and$libresoc.v:139708$5798
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$389
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140044$5850_Y
+ connect \Y $and$libresoc.v:139708$5798_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140046$5852
+ cell $and $and$libresoc.v:139710$5800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core_prev
connect \B \$393
- connect \Y $and$libresoc.v:140046$5852_Y
+ connect \Y $and$libresoc.v:139710$5800_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140052$5858
+ cell $and $and$libresoc.v:139716$5806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$401
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140052$5858_Y
+ connect \Y $and$libresoc.v:139716$5806_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140054$5860
+ cell $and $and$libresoc.v:139718$5808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$405
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140054$5860_Y
+ connect \Y $and$libresoc.v:139718$5808_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140056$5862
+ cell $and $and$libresoc.v:139720$5810
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$409
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140056$5862_Y
+ connect \Y $and$libresoc.v:139720$5810_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140058$5864
+ cell $and $and$libresoc.v:139722$5812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core_prev
connect \B \$413
- connect \Y $and$libresoc.v:140058$5864_Y
+ connect \Y $and$libresoc.v:139722$5812_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:140062$5868
+ cell $and $and$libresoc.v:139726$5816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$419
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:140062$5868_Y
+ connect \Y $and$libresoc.v:139726$5816_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:140064$5870
+ cell $and $and$libresoc.v:139728$5818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$423
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:140064$5870_Y
+ connect \Y $and$libresoc.v:139728$5818_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:140066$5872
+ cell $and $and$libresoc.v:139730$5820
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$427
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140066$5872_Y
+ connect \Y $and$libresoc.v:139730$5820_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:140068$5874
+ cell $and $and$libresoc.v:139732$5822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_update_core_prev
connect \B \$431
- connect \Y $and$libresoc.v:140068$5874_Y
+ connect \Y $and$libresoc.v:139732$5822_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:140071$5877
+ cell $and $and$libresoc.v:139735$5825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$41
- connect \Y $and$libresoc.v:140071$5877_Y
+ connect \Y $and$libresoc.v:139735$5825_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403"
- cell $and $and$libresoc.v:140081$5888
+ cell $and $and$libresoc.v:139745$5836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \_fsm_update
- connect \Y $and$libresoc.v:140081$5888_Y
+ connect \Y $and$libresoc.v:139745$5836_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $and $and$libresoc.v:140103$5910
+ cell $and $and$libresoc.v:139767$5858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$5
- connect \Y $and$libresoc.v:140103$5910_Y
+ connect \Y $and$libresoc.v:139767$5858_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:139882$5688
+ cell $eq $eq$libresoc.v:139546$5636
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1111
- connect \Y $eq$libresoc.v:139882$5688_Y
+ connect \Y $eq$libresoc.v:139546$5636_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:139893$5699
+ cell $eq $eq$libresoc.v:139557$5647
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:139893$5699_Y
+ connect \Y $eq$libresoc.v:139557$5647_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:139904$5710
+ cell $eq $eq$libresoc.v:139568$5658
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:139904$5710_Y
+ connect \Y $eq$libresoc.v:139568$5658_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $eq $eq$libresoc.v:139937$5743
+ cell $eq $eq$libresoc.v:139601$5691
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'1
- connect \Y $eq$libresoc.v:139937$5743_Y
+ connect \Y $eq$libresoc.v:139601$5691_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:139938$5744
+ cell $eq $eq$libresoc.v:139602$5692
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:139938$5744_Y
+ connect \Y $eq$libresoc.v:139602$5692_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:139949$5755
+ cell $eq $eq$libresoc.v:139613$5703
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:139949$5755_Y
+ connect \Y $eq$libresoc.v:139613$5703_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:139971$5777
+ cell $eq $eq$libresoc.v:139635$5725
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:139971$5777_Y
+ connect \Y $eq$libresoc.v:139635$5725_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:140000$5806
+ cell $eq $eq$libresoc.v:139664$5754
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:140000$5806_Y
+ connect \Y $eq$libresoc.v:139664$5754_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:140001$5807
+ cell $eq $eq$libresoc.v:139665$5755
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:140001$5807_Y
+ connect \Y $eq$libresoc.v:139665$5755_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:140003$5809
+ cell $eq $eq$libresoc.v:139667$5757
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:140003$5809_Y
+ connect \Y $eq$libresoc.v:139667$5757_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140007$5813
+ cell $eq $eq$libresoc.v:139671$5761
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'100
- connect \Y $eq$libresoc.v:140007$5813_Y
+ connect \Y $eq$libresoc.v:139671$5761_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:140015$5821
+ cell $eq $eq$libresoc.v:139679$5769
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:140015$5821_Y
+ connect \Y $eq$libresoc.v:139679$5769_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140017$5823
+ cell $eq $eq$libresoc.v:139681$5771
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'101
- connect \Y $eq$libresoc.v:140017$5823_Y
+ connect \Y $eq$libresoc.v:139681$5771_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:140026$5832
+ cell $eq $eq$libresoc.v:139690$5780
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:140026$5832_Y
+ connect \Y $eq$libresoc.v:139690$5780_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140027$5833
+ cell $eq $eq$libresoc.v:139691$5781
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'110
- connect \Y $eq$libresoc.v:140027$5833_Y
+ connect \Y $eq$libresoc.v:139691$5781_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140028$5834
+ cell $eq $eq$libresoc.v:139692$5782
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'111
- connect \Y $eq$libresoc.v:140028$5834_Y
+ connect \Y $eq$libresoc.v:139692$5782_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140038$5844
+ cell $eq $eq$libresoc.v:139702$5792
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1000
- connect \Y $eq$libresoc.v:140038$5844_Y
+ connect \Y $eq$libresoc.v:139702$5792_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140047$5853
+ cell $eq $eq$libresoc.v:139711$5801
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1001
- connect \Y $eq$libresoc.v:140047$5853_Y
+ connect \Y $eq$libresoc.v:139711$5801_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $eq $eq$libresoc.v:140048$5854
+ cell $eq $eq$libresoc.v:139712$5802
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1111
- connect \Y $eq$libresoc.v:140048$5854_Y
+ connect \Y $eq$libresoc.v:139712$5802_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:140049$5855
+ cell $eq $eq$libresoc.v:139713$5803
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:140049$5855_Y
+ connect \Y $eq$libresoc.v:139713$5803_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140050$5856
+ cell $eq $eq$libresoc.v:139714$5804
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1010
- connect \Y $eq$libresoc.v:140050$5856_Y
+ connect \Y $eq$libresoc.v:139714$5804_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:140059$5865
+ cell $eq $eq$libresoc.v:139723$5813
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1011
- connect \Y $eq$libresoc.v:140059$5865_Y
+ connect \Y $eq$libresoc.v:139723$5813_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
- cell $eq $eq$libresoc.v:140069$5875
+ cell $eq $eq$libresoc.v:139733$5823
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'0
- connect \Y $eq$libresoc.v:140069$5875_Y
+ connect \Y $eq$libresoc.v:139733$5823_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $eq $eq$libresoc.v:140072$5878
+ cell $eq $eq$libresoc.v:139736$5826
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'1
- connect \Y $eq$libresoc.v:140072$5878_Y
+ connect \Y $eq$libresoc.v:139736$5826_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $eq $eq$libresoc.v:140073$5879
+ cell $eq $eq$libresoc.v:139737$5827
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:140073$5879_Y
+ connect \Y $eq$libresoc.v:139737$5827_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792"
- cell $eq $eq$libresoc.v:140075$5881
+ cell $eq $eq$libresoc.v:139739$5829
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:140075$5881_Y
+ connect \Y $eq$libresoc.v:139739$5829_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $eq $eq$libresoc.v:140079$5886
+ cell $eq $eq$libresoc.v:139743$5834
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$455
connect \B 1'1
- connect \Y $eq$libresoc.v:140079$5886_Y
+ connect \Y $eq$libresoc.v:139743$5834_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $eq $eq$libresoc.v:140080$5887
+ cell $eq $eq$libresoc.v:139744$5835
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$455
connect \B 2'10
- connect \Y $eq$libresoc.v:140080$5887_Y
+ connect \Y $eq$libresoc.v:139744$5835_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524"
- cell $eq $eq$libresoc.v:140083$5890
+ cell $eq $eq$libresoc.v:139747$5838
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$455
connect \B 2'10
- connect \Y $eq$libresoc.v:140083$5890_Y
+ connect \Y $eq$libresoc.v:139747$5838_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404"
- cell $eq $eq$libresoc.v:140086$5893
+ cell $eq $eq$libresoc.v:139750$5841
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:140086$5893_Y
+ connect \Y $eq$libresoc.v:139750$5841_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405"
- cell $eq $eq$libresoc.v:140087$5894
+ cell $eq $eq$libresoc.v:139751$5842
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:140087$5894_Y
+ connect \Y $eq$libresoc.v:139751$5842_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- cell $pos $extend$libresoc.v:140078$5884
+ cell $pos $extend$libresoc.v:139742$5832
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \dmi0__addr_i
- connect \Y $extend$libresoc.v:140078$5884_Y
+ connect \Y $extend$libresoc.v:139742$5832_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140008$5814
+ cell $ne $ne$libresoc.v:139672$5762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140008$5814_Y
+ connect \Y $ne$libresoc.v:139672$5762_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140010$5816
+ cell $ne $ne$libresoc.v:139674$5764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140010$5816_Y
+ connect \Y $ne$libresoc.v:139674$5764_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140012$5818
+ cell $ne $ne$libresoc.v:139676$5766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140012$5818_Y
+ connect \Y $ne$libresoc.v:139676$5766_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140018$5824
+ cell $ne $ne$libresoc.v:139682$5772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140018$5824_Y
+ connect \Y $ne$libresoc.v:139682$5772_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140020$5826
+ cell $ne $ne$libresoc.v:139684$5774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140020$5826_Y
+ connect \Y $ne$libresoc.v:139684$5774_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140022$5828
+ cell $ne $ne$libresoc.v:139686$5776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140022$5828_Y
+ connect \Y $ne$libresoc.v:139686$5776_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140029$5835
+ cell $ne $ne$libresoc.v:139693$5783
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140029$5835_Y
+ connect \Y $ne$libresoc.v:139693$5783_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140031$5837
+ cell $ne $ne$libresoc.v:139695$5785
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140031$5837_Y
+ connect \Y $ne$libresoc.v:139695$5785_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140033$5839
+ cell $ne $ne$libresoc.v:139697$5787
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140033$5839_Y
+ connect \Y $ne$libresoc.v:139697$5787_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140039$5845
+ cell $ne $ne$libresoc.v:139703$5793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140039$5845_Y
+ connect \Y $ne$libresoc.v:139703$5793_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140041$5847
+ cell $ne $ne$libresoc.v:139705$5795
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140041$5847_Y
+ connect \Y $ne$libresoc.v:139705$5795_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140043$5849
+ cell $ne $ne$libresoc.v:139707$5797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140043$5849_Y
+ connect \Y $ne$libresoc.v:139707$5797_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140051$5857
+ cell $ne $ne$libresoc.v:139715$5805
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140051$5857_Y
+ connect \Y $ne$libresoc.v:139715$5805_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140053$5859
+ cell $ne $ne$libresoc.v:139717$5807
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140053$5859_Y
+ connect \Y $ne$libresoc.v:139717$5807_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140055$5861
+ cell $ne $ne$libresoc.v:139719$5809
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140055$5861_Y
+ connect \Y $ne$libresoc.v:139719$5809_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:140061$5867
+ cell $ne $ne$libresoc.v:139725$5815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140061$5867_Y
+ connect \Y $ne$libresoc.v:139725$5815_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:140063$5869
+ cell $ne $ne$libresoc.v:139727$5817
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140063$5869_Y
+ connect \Y $ne$libresoc.v:139727$5817_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:140065$5871
+ cell $ne $ne$libresoc.v:139729$5819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:140065$5871_Y
+ connect \Y $ne$libresoc.v:139729$5819_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140014$5820
+ cell $not $not$libresoc.v:139678$5768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sr0_update_core
- connect \Y $not$libresoc.v:140014$5820_Y
+ connect \Y $not$libresoc.v:139678$5768_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140024$5830
+ cell $not $not$libresoc.v:139688$5778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core
- connect \Y $not$libresoc.v:140024$5830_Y
+ connect \Y $not$libresoc.v:139688$5778_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140035$5841
+ cell $not $not$libresoc.v:139699$5789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core
- connect \Y $not$libresoc.v:140035$5841_Y
+ connect \Y $not$libresoc.v:139699$5789_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140045$5851
+ cell $not $not$libresoc.v:139709$5799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core
- connect \Y $not$libresoc.v:140045$5851_Y
+ connect \Y $not$libresoc.v:139709$5799_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140057$5863
+ cell $not $not$libresoc.v:139721$5811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core
- connect \Y $not$libresoc.v:140057$5863_Y
+ connect \Y $not$libresoc.v:139721$5811_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:140067$5873
+ cell $not $not$libresoc.v:139731$5821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sr5_update_core
- connect \Y $not$libresoc.v:140067$5873_Y
+ connect \Y $not$libresoc.v:139731$5821_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
- cell $not $not$libresoc.v:140070$5876
+ cell $not $not$libresoc.v:139734$5824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$436
- connect \Y $not$libresoc.v:140070$5876_Y
+ connect \Y $not$libresoc.v:139734$5824_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:139915$5721
+ cell $or $or$libresoc.v:139579$5669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$11
connect \B \$13
- connect \Y $or$libresoc.v:139915$5721_Y
+ connect \Y $or$libresoc.v:139579$5669_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:139960$5766
+ cell $or $or$libresoc.v:139624$5714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \$21
- connect \Y $or$libresoc.v:139960$5766_Y
+ connect \Y $or$libresoc.v:139624$5714_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:139982$5788
+ cell $or $or$libresoc.v:139646$5736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $or$libresoc.v:139982$5788_Y
+ connect \Y $or$libresoc.v:139646$5736_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:140002$5808
+ cell $or $or$libresoc.v:139666$5756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$311
connect \B \$313
- connect \Y $or$libresoc.v:140002$5808_Y
+ connect \Y $or$libresoc.v:139666$5756_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:140005$5811
+ cell $or $or$libresoc.v:139669$5759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$315
connect \B \$317
- connect \Y $or$libresoc.v:140005$5811_Y
+ connect \Y $or$libresoc.v:139669$5759_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:140037$5843
+ cell $or $or$libresoc.v:139701$5791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:140037$5843_Y
+ connect \Y $or$libresoc.v:139701$5791_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:140060$5866
+ cell $or $or$libresoc.v:139724$5814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$37
connect \B \$39
- connect \Y $or$libresoc.v:140060$5866_Y
+ connect \Y $or$libresoc.v:139724$5814_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $or $or$libresoc.v:140074$5880
+ cell $or $or$libresoc.v:139738$5828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$439
connect \B \$441
- connect \Y $or$libresoc.v:140074$5880_Y
+ connect \Y $or$libresoc.v:139738$5828_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $or $or$libresoc.v:140082$5889
+ cell $or $or$libresoc.v:139746$5837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$456
connect \B \$458
- connect \Y $or$libresoc.v:140082$5889_Y
+ connect \Y $or$libresoc.v:139746$5837_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $or $or$libresoc.v:140092$5899
+ cell $or $or$libresoc.v:139756$5847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $or$libresoc.v:140092$5899_Y
+ connect \Y $or$libresoc.v:139756$5847_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- cell $pos $pos$libresoc.v:140078$5885
+ cell $pos $pos$libresoc.v:139742$5833
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:140078$5884_Y
- connect \Y $pos$libresoc.v:140078$5885_Y
+ connect \A $extend$libresoc.v:139742$5832_Y
+ connect \Y $pos$libresoc.v:139742$5833_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139883$5689
+ cell $mux $ternary$libresoc.v:139547$5637
parameter \WIDTH 1
connect \A \gpio_e15__pad__i
connect \B \io_bd [24]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139883$5689_Y
+ connect \Y $ternary$libresoc.v:139547$5637_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139884$5690
+ cell $mux $ternary$libresoc.v:139548$5638
parameter \WIDTH 1
connect \A \gpio_e15__core__o
connect \B \io_bd [25]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139884$5690_Y
+ connect \Y $ternary$libresoc.v:139548$5638_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139885$5691
+ cell $mux $ternary$libresoc.v:139549$5639
parameter \WIDTH 1
connect \A \gpio_e15__core__oe
connect \B \io_bd [26]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139885$5691_Y
+ connect \Y $ternary$libresoc.v:139549$5639_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139886$5692
+ cell $mux $ternary$libresoc.v:139550$5640
parameter \WIDTH 1
connect \A \gpio_s0__pad__i
connect \B \io_bd [27]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139886$5692_Y
+ connect \Y $ternary$libresoc.v:139550$5640_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139887$5693
+ cell $mux $ternary$libresoc.v:139551$5641
parameter \WIDTH 1
connect \A \gpio_s0__core__o
connect \B \io_bd [28]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139887$5693_Y
+ connect \Y $ternary$libresoc.v:139551$5641_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139888$5694
+ cell $mux $ternary$libresoc.v:139552$5642
parameter \WIDTH 1
connect \A \gpio_s0__core__oe
connect \B \io_bd [29]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139888$5694_Y
+ connect \Y $ternary$libresoc.v:139552$5642_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139889$5695
+ cell $mux $ternary$libresoc.v:139553$5643
parameter \WIDTH 1
connect \A \gpio_s1__pad__i
connect \B \io_bd [30]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139889$5695_Y
+ connect \Y $ternary$libresoc.v:139553$5643_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139890$5696
+ cell $mux $ternary$libresoc.v:139554$5644
parameter \WIDTH 1
connect \A \gpio_s1__core__o
connect \B \io_bd [31]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139890$5696_Y
+ connect \Y $ternary$libresoc.v:139554$5644_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139891$5697
+ cell $mux $ternary$libresoc.v:139555$5645
parameter \WIDTH 1
connect \A \gpio_s1__core__oe
connect \B \io_bd [32]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139891$5697_Y
+ connect \Y $ternary$libresoc.v:139555$5645_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139892$5698
+ cell $mux $ternary$libresoc.v:139556$5646
parameter \WIDTH 1
connect \A \gpio_s2__pad__i
connect \B \io_bd [33]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139892$5698_Y
+ connect \Y $ternary$libresoc.v:139556$5646_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139894$5700
+ cell $mux $ternary$libresoc.v:139558$5648
parameter \WIDTH 1
connect \A \gpio_s2__core__o
connect \B \io_bd [34]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139894$5700_Y
+ connect \Y $ternary$libresoc.v:139558$5648_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139895$5701
+ cell $mux $ternary$libresoc.v:139559$5649
parameter \WIDTH 1
connect \A \gpio_s2__core__oe
connect \B \io_bd [35]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139895$5701_Y
+ connect \Y $ternary$libresoc.v:139559$5649_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139896$5702
+ cell $mux $ternary$libresoc.v:139560$5650
parameter \WIDTH 1
connect \A \gpio_s3__pad__i
connect \B \io_bd [36]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139896$5702_Y
+ connect \Y $ternary$libresoc.v:139560$5650_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139897$5703
+ cell $mux $ternary$libresoc.v:139561$5651
parameter \WIDTH 1
connect \A \gpio_s3__core__o
connect \B \io_bd [37]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139897$5703_Y
+ connect \Y $ternary$libresoc.v:139561$5651_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139898$5704
+ cell $mux $ternary$libresoc.v:139562$5652
parameter \WIDTH 1
connect \A \gpio_s3__core__oe
connect \B \io_bd [38]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139898$5704_Y
+ connect \Y $ternary$libresoc.v:139562$5652_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139899$5705
+ cell $mux $ternary$libresoc.v:139563$5653
parameter \WIDTH 1
connect \A \gpio_s4__pad__i
connect \B \io_bd [39]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139899$5705_Y
+ connect \Y $ternary$libresoc.v:139563$5653_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139900$5706
+ cell $mux $ternary$libresoc.v:139564$5654
parameter \WIDTH 1
connect \A \gpio_s4__core__o
connect \B \io_bd [40]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139900$5706_Y
+ connect \Y $ternary$libresoc.v:139564$5654_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139901$5707
+ cell $mux $ternary$libresoc.v:139565$5655
parameter \WIDTH 1
connect \A \gpio_s4__core__oe
connect \B \io_bd [41]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139901$5707_Y
+ connect \Y $ternary$libresoc.v:139565$5655_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139902$5708
+ cell $mux $ternary$libresoc.v:139566$5656
parameter \WIDTH 1
connect \A \gpio_s5__pad__i
connect \B \io_bd [42]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139902$5708_Y
+ connect \Y $ternary$libresoc.v:139566$5656_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139903$5709
+ cell $mux $ternary$libresoc.v:139567$5657
parameter \WIDTH 1
connect \A \gpio_s5__core__o
connect \B \io_bd [43]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139903$5709_Y
+ connect \Y $ternary$libresoc.v:139567$5657_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139905$5711
+ cell $mux $ternary$libresoc.v:139569$5659
parameter \WIDTH 1
connect \A \gpio_s5__core__oe
connect \B \io_bd [44]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139905$5711_Y
+ connect \Y $ternary$libresoc.v:139569$5659_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139906$5712
+ cell $mux $ternary$libresoc.v:139570$5660
parameter \WIDTH 1
connect \A \gpio_s6__pad__i
connect \B \io_bd [45]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139906$5712_Y
+ connect \Y $ternary$libresoc.v:139570$5660_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139907$5713
+ cell $mux $ternary$libresoc.v:139571$5661
parameter \WIDTH 1
connect \A \gpio_s6__core__o
connect \B \io_bd [46]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139907$5713_Y
+ connect \Y $ternary$libresoc.v:139571$5661_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139908$5714
+ cell $mux $ternary$libresoc.v:139572$5662
parameter \WIDTH 1
connect \A \gpio_s6__core__oe
connect \B \io_bd [47]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139908$5714_Y
+ connect \Y $ternary$libresoc.v:139572$5662_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139909$5715
+ cell $mux $ternary$libresoc.v:139573$5663
parameter \WIDTH 1
connect \A \gpio_s7__pad__i
connect \B \io_bd [48]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139909$5715_Y
+ connect \Y $ternary$libresoc.v:139573$5663_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139910$5716
+ cell $mux $ternary$libresoc.v:139574$5664
parameter \WIDTH 1
connect \A \gpio_s7__core__o
connect \B \io_bd [49]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139910$5716_Y
+ connect \Y $ternary$libresoc.v:139574$5664_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139911$5717
+ cell $mux $ternary$libresoc.v:139575$5665
parameter \WIDTH 1
connect \A \gpio_s7__core__oe
connect \B \io_bd [50]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139911$5717_Y
+ connect \Y $ternary$libresoc.v:139575$5665_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139912$5718
+ cell $mux $ternary$libresoc.v:139576$5666
parameter \WIDTH 1
connect \A \mspi0_clk__core__o
connect \B \io_bd [51]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139912$5718_Y
+ connect \Y $ternary$libresoc.v:139576$5666_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139913$5719
+ cell $mux $ternary$libresoc.v:139577$5667
parameter \WIDTH 1
connect \A \mspi0_cs_n__core__o
connect \B \io_bd [52]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139913$5719_Y
+ connect \Y $ternary$libresoc.v:139577$5667_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139914$5720
+ cell $mux $ternary$libresoc.v:139578$5668
parameter \WIDTH 1
connect \A \mspi0_mosi__core__o
connect \B \io_bd [53]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139914$5720_Y
+ connect \Y $ternary$libresoc.v:139578$5668_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:139916$5722
+ cell $mux $ternary$libresoc.v:139580$5670
parameter \WIDTH 1
connect \A \mspi0_miso__pad__i
connect \B \io_bd [54]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139916$5722_Y
+ connect \Y $ternary$libresoc.v:139580$5670_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139917$5723
+ cell $mux $ternary$libresoc.v:139581$5671
parameter \WIDTH 1
connect \A \mtwi_sda__pad__i
connect \B \io_bd [55]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139917$5723_Y
+ connect \Y $ternary$libresoc.v:139581$5671_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139918$5724
+ cell $mux $ternary$libresoc.v:139582$5672
parameter \WIDTH 1
connect \A \mtwi_sda__core__o
connect \B \io_bd [56]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139918$5724_Y
+ connect \Y $ternary$libresoc.v:139582$5672_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139919$5725
+ cell $mux $ternary$libresoc.v:139583$5673
parameter \WIDTH 1
connect \A \mtwi_sda__core__oe
connect \B \io_bd [57]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139919$5725_Y
+ connect \Y $ternary$libresoc.v:139583$5673_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139920$5726
+ cell $mux $ternary$libresoc.v:139584$5674
parameter \WIDTH 1
connect \A \mtwi_scl__core__o
connect \B \io_bd [58]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139920$5726_Y
+ connect \Y $ternary$libresoc.v:139584$5674_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139921$5727
+ cell $mux $ternary$libresoc.v:139585$5675
parameter \WIDTH 1
connect \A \sdr_dm_0__core__o
connect \B \io_bd [59]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139921$5727_Y
+ connect \Y $ternary$libresoc.v:139585$5675_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139922$5728
+ cell $mux $ternary$libresoc.v:139586$5676
parameter \WIDTH 1
connect \A \sdr_dq_0__pad__i
connect \B \io_bd [60]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139922$5728_Y
+ connect \Y $ternary$libresoc.v:139586$5676_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139923$5729
+ cell $mux $ternary$libresoc.v:139587$5677
parameter \WIDTH 1
connect \A \sdr_dq_0__core__o
connect \B \io_bd [61]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139923$5729_Y
+ connect \Y $ternary$libresoc.v:139587$5677_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139924$5730
+ cell $mux $ternary$libresoc.v:139588$5678
parameter \WIDTH 1
connect \A \sdr_dq_0__core__oe
connect \B \io_bd [62]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139924$5730_Y
+ connect \Y $ternary$libresoc.v:139588$5678_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139925$5731
+ cell $mux $ternary$libresoc.v:139589$5679
parameter \WIDTH 1
connect \A \sdr_dq_1__pad__i
connect \B \io_bd [63]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139925$5731_Y
+ connect \Y $ternary$libresoc.v:139589$5679_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139927$5733
+ cell $mux $ternary$libresoc.v:139591$5681
parameter \WIDTH 1
connect \A \sdr_dq_1__core__o
connect \B \io_bd [64]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139927$5733_Y
+ connect \Y $ternary$libresoc.v:139591$5681_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139928$5734
+ cell $mux $ternary$libresoc.v:139592$5682
parameter \WIDTH 1
connect \A \sdr_dq_1__core__oe
connect \B \io_bd [65]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139928$5734_Y
+ connect \Y $ternary$libresoc.v:139592$5682_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139929$5735
+ cell $mux $ternary$libresoc.v:139593$5683
parameter \WIDTH 1
connect \A \sdr_dq_2__pad__i
connect \B \io_bd [66]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139929$5735_Y
+ connect \Y $ternary$libresoc.v:139593$5683_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139930$5736
+ cell $mux $ternary$libresoc.v:139594$5684
parameter \WIDTH 1
connect \A \sdr_dq_2__core__o
connect \B \io_bd [67]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139930$5736_Y
+ connect \Y $ternary$libresoc.v:139594$5684_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139931$5737
+ cell $mux $ternary$libresoc.v:139595$5685
parameter \WIDTH 1
connect \A \sdr_dq_2__core__oe
connect \B \io_bd [68]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139931$5737_Y
+ connect \Y $ternary$libresoc.v:139595$5685_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139932$5738
+ cell $mux $ternary$libresoc.v:139596$5686
parameter \WIDTH 1
connect \A \sdr_dq_3__pad__i
connect \B \io_bd [69]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139932$5738_Y
+ connect \Y $ternary$libresoc.v:139596$5686_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139933$5739
+ cell $mux $ternary$libresoc.v:139597$5687
parameter \WIDTH 1
connect \A \sdr_dq_3__core__o
connect \B \io_bd [70]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139933$5739_Y
+ connect \Y $ternary$libresoc.v:139597$5687_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139934$5740
+ cell $mux $ternary$libresoc.v:139598$5688
parameter \WIDTH 1
connect \A \sdr_dq_3__core__oe
connect \B \io_bd [71]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139934$5740_Y
+ connect \Y $ternary$libresoc.v:139598$5688_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139935$5741
+ cell $mux $ternary$libresoc.v:139599$5689
parameter \WIDTH 1
connect \A \sdr_dq_4__pad__i
connect \B \io_bd [72]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139935$5741_Y
+ connect \Y $ternary$libresoc.v:139599$5689_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139936$5742
+ cell $mux $ternary$libresoc.v:139600$5690
parameter \WIDTH 1
connect \A \sdr_dq_4__core__o
connect \B \io_bd [73]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139936$5742_Y
+ connect \Y $ternary$libresoc.v:139600$5690_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139939$5745
+ cell $mux $ternary$libresoc.v:139603$5693
parameter \WIDTH 1
connect \A \sdr_dq_4__core__oe
connect \B \io_bd [74]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139939$5745_Y
+ connect \Y $ternary$libresoc.v:139603$5693_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139940$5746
+ cell $mux $ternary$libresoc.v:139604$5694
parameter \WIDTH 1
connect \A \sdr_dq_5__pad__i
connect \B \io_bd [75]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139940$5746_Y
+ connect \Y $ternary$libresoc.v:139604$5694_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139941$5747
+ cell $mux $ternary$libresoc.v:139605$5695
parameter \WIDTH 1
connect \A \sdr_dq_5__core__o
connect \B \io_bd [76]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139941$5747_Y
+ connect \Y $ternary$libresoc.v:139605$5695_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139942$5748
+ cell $mux $ternary$libresoc.v:139606$5696
parameter \WIDTH 1
connect \A \sdr_dq_5__core__oe
connect \B \io_bd [77]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139942$5748_Y
+ connect \Y $ternary$libresoc.v:139606$5696_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139943$5749
+ cell $mux $ternary$libresoc.v:139607$5697
parameter \WIDTH 1
connect \A \sdr_dq_6__pad__i
connect \B \io_bd [78]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139943$5749_Y
+ connect \Y $ternary$libresoc.v:139607$5697_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139944$5750
+ cell $mux $ternary$libresoc.v:139608$5698
parameter \WIDTH 1
connect \A \sdr_dq_6__core__o
connect \B \io_bd [79]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139944$5750_Y
+ connect \Y $ternary$libresoc.v:139608$5698_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139945$5751
+ cell $mux $ternary$libresoc.v:139609$5699
parameter \WIDTH 1
connect \A \sdr_dq_6__core__oe
connect \B \io_bd [80]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139945$5751_Y
+ connect \Y $ternary$libresoc.v:139609$5699_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139946$5752
+ cell $mux $ternary$libresoc.v:139610$5700
parameter \WIDTH 1
connect \A \sdr_dq_7__pad__i
connect \B \io_bd [81]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139946$5752_Y
+ connect \Y $ternary$libresoc.v:139610$5700_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139947$5753
+ cell $mux $ternary$libresoc.v:139611$5701
parameter \WIDTH 1
connect \A \sdr_dq_7__core__o
connect \B \io_bd [82]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139947$5753_Y
+ connect \Y $ternary$libresoc.v:139611$5701_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139948$5754
+ cell $mux $ternary$libresoc.v:139612$5702
parameter \WIDTH 1
connect \A \sdr_dq_7__core__oe
connect \B \io_bd [83]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139948$5754_Y
+ connect \Y $ternary$libresoc.v:139612$5702_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139950$5756
+ cell $mux $ternary$libresoc.v:139614$5704
parameter \WIDTH 1
connect \A \sdr_a_0__core__o
connect \B \io_bd [84]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139950$5756_Y
+ connect \Y $ternary$libresoc.v:139614$5704_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139951$5757
+ cell $mux $ternary$libresoc.v:139615$5705
parameter \WIDTH 1
connect \A \sdr_a_1__core__o
connect \B \io_bd [85]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139951$5757_Y
+ connect \Y $ternary$libresoc.v:139615$5705_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139952$5758
+ cell $mux $ternary$libresoc.v:139616$5706
parameter \WIDTH 1
connect \A \sdr_a_2__core__o
connect \B \io_bd [86]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139952$5758_Y
+ connect \Y $ternary$libresoc.v:139616$5706_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139953$5759
+ cell $mux $ternary$libresoc.v:139617$5707
parameter \WIDTH 1
connect \A \sdr_a_3__core__o
connect \B \io_bd [87]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139953$5759_Y
+ connect \Y $ternary$libresoc.v:139617$5707_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139954$5760
+ cell $mux $ternary$libresoc.v:139618$5708
parameter \WIDTH 1
connect \A \sdr_a_4__core__o
connect \B \io_bd [88]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139954$5760_Y
+ connect \Y $ternary$libresoc.v:139618$5708_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139955$5761
+ cell $mux $ternary$libresoc.v:139619$5709
parameter \WIDTH 1
connect \A \sdr_a_5__core__o
connect \B \io_bd [89]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139955$5761_Y
+ connect \Y $ternary$libresoc.v:139619$5709_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139956$5762
+ cell $mux $ternary$libresoc.v:139620$5710
parameter \WIDTH 1
connect \A \sdr_a_6__core__o
connect \B \io_bd [90]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139956$5762_Y
+ connect \Y $ternary$libresoc.v:139620$5710_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139957$5763
+ cell $mux $ternary$libresoc.v:139621$5711
parameter \WIDTH 1
connect \A \sdr_a_7__core__o
connect \B \io_bd [91]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139957$5763_Y
+ connect \Y $ternary$libresoc.v:139621$5711_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139958$5764
+ cell $mux $ternary$libresoc.v:139622$5712
parameter \WIDTH 1
connect \A \sdr_a_8__core__o
connect \B \io_bd [92]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139958$5764_Y
+ connect \Y $ternary$libresoc.v:139622$5712_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139959$5765
+ cell $mux $ternary$libresoc.v:139623$5713
parameter \WIDTH 1
connect \A \sdr_a_9__core__o
connect \B \io_bd [93]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139959$5765_Y
+ connect \Y $ternary$libresoc.v:139623$5713_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139961$5767
+ cell $mux $ternary$libresoc.v:139625$5715
parameter \WIDTH 1
connect \A \sdr_ba_0__core__o
connect \B \io_bd [94]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139961$5767_Y
+ connect \Y $ternary$libresoc.v:139625$5715_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139962$5768
+ cell $mux $ternary$libresoc.v:139626$5716
parameter \WIDTH 1
connect \A \sdr_ba_1__core__o
connect \B \io_bd [95]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139962$5768_Y
+ connect \Y $ternary$libresoc.v:139626$5716_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139963$5769
+ cell $mux $ternary$libresoc.v:139627$5717
parameter \WIDTH 1
connect \A \sdr_clock__core__o
connect \B \io_bd [96]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139963$5769_Y
+ connect \Y $ternary$libresoc.v:139627$5717_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139964$5770
+ cell $mux $ternary$libresoc.v:139628$5718
parameter \WIDTH 1
connect \A \sdr_cke__core__o
connect \B \io_bd [97]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139964$5770_Y
+ connect \Y $ternary$libresoc.v:139628$5718_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139965$5771
+ cell $mux $ternary$libresoc.v:139629$5719
parameter \WIDTH 1
connect \A \sdr_ras_n__core__o
connect \B \io_bd [98]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139965$5771_Y
+ connect \Y $ternary$libresoc.v:139629$5719_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139966$5772
+ cell $mux $ternary$libresoc.v:139630$5720
parameter \WIDTH 1
connect \A \sdr_cas_n__core__o
connect \B \io_bd [99]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139966$5772_Y
+ connect \Y $ternary$libresoc.v:139630$5720_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139967$5773
+ cell $mux $ternary$libresoc.v:139631$5721
parameter \WIDTH 1
connect \A \sdr_we_n__core__o
connect \B \io_bd [100]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139967$5773_Y
+ connect \Y $ternary$libresoc.v:139631$5721_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139968$5774
+ cell $mux $ternary$libresoc.v:139632$5722
parameter \WIDTH 1
connect \A \sdr_cs_n__core__o
connect \B \io_bd [101]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139968$5774_Y
+ connect \Y $ternary$libresoc.v:139632$5722_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139969$5775
+ cell $mux $ternary$libresoc.v:139633$5723
parameter \WIDTH 1
connect \A \sdr_a_10__core__o
connect \B \io_bd [102]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139969$5775_Y
+ connect \Y $ternary$libresoc.v:139633$5723_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139970$5776
+ cell $mux $ternary$libresoc.v:139634$5724
parameter \WIDTH 1
connect \A \sdr_a_11__core__o
connect \B \io_bd [103]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139970$5776_Y
+ connect \Y $ternary$libresoc.v:139634$5724_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139972$5778
+ cell $mux $ternary$libresoc.v:139636$5726
parameter \WIDTH 1
connect \A \sdr_a_12__core__o
connect \B \io_bd [104]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139972$5778_Y
+ connect \Y $ternary$libresoc.v:139636$5726_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:139973$5779
+ cell $mux $ternary$libresoc.v:139637$5727
parameter \WIDTH 1
connect \A \sdr_dm_1__core__o
connect \B \io_bd [105]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139973$5779_Y
+ connect \Y $ternary$libresoc.v:139637$5727_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139974$5780
+ cell $mux $ternary$libresoc.v:139638$5728
parameter \WIDTH 1
connect \A \sdr_dq_8__pad__i
connect \B \io_bd [106]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139974$5780_Y
+ connect \Y $ternary$libresoc.v:139638$5728_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139975$5781
+ cell $mux $ternary$libresoc.v:139639$5729
parameter \WIDTH 1
connect \A \sdr_dq_8__core__o
connect \B \io_bd [107]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139975$5781_Y
+ connect \Y $ternary$libresoc.v:139639$5729_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139976$5782
+ cell $mux $ternary$libresoc.v:139640$5730
parameter \WIDTH 1
connect \A \sdr_dq_8__core__oe
connect \B \io_bd [108]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139976$5782_Y
+ connect \Y $ternary$libresoc.v:139640$5730_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139977$5783
+ cell $mux $ternary$libresoc.v:139641$5731
parameter \WIDTH 1
connect \A \sdr_dq_9__pad__i
connect \B \io_bd [109]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139977$5783_Y
+ connect \Y $ternary$libresoc.v:139641$5731_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139978$5784
+ cell $mux $ternary$libresoc.v:139642$5732
parameter \WIDTH 1
connect \A \sdr_dq_9__core__o
connect \B \io_bd [110]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139978$5784_Y
+ connect \Y $ternary$libresoc.v:139642$5732_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139979$5785
+ cell $mux $ternary$libresoc.v:139643$5733
parameter \WIDTH 1
connect \A \sdr_dq_9__core__oe
connect \B \io_bd [111]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139979$5785_Y
+ connect \Y $ternary$libresoc.v:139643$5733_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139980$5786
+ cell $mux $ternary$libresoc.v:139644$5734
parameter \WIDTH 1
connect \A \sdr_dq_10__pad__i
connect \B \io_bd [112]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139980$5786_Y
+ connect \Y $ternary$libresoc.v:139644$5734_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139981$5787
+ cell $mux $ternary$libresoc.v:139645$5735
parameter \WIDTH 1
connect \A \sdr_dq_10__core__o
connect \B \io_bd [113]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139981$5787_Y
+ connect \Y $ternary$libresoc.v:139645$5735_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139983$5789
+ cell $mux $ternary$libresoc.v:139647$5737
parameter \WIDTH 1
connect \A \sdr_dq_10__core__oe
connect \B \io_bd [114]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139983$5789_Y
+ connect \Y $ternary$libresoc.v:139647$5737_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139984$5790
+ cell $mux $ternary$libresoc.v:139648$5738
parameter \WIDTH 1
connect \A \sdr_dq_11__pad__i
connect \B \io_bd [115]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139984$5790_Y
+ connect \Y $ternary$libresoc.v:139648$5738_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139985$5791
+ cell $mux $ternary$libresoc.v:139649$5739
parameter \WIDTH 1
connect \A \sdr_dq_11__core__o
connect \B \io_bd [116]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139985$5791_Y
+ connect \Y $ternary$libresoc.v:139649$5739_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139986$5792
+ cell $mux $ternary$libresoc.v:139650$5740
parameter \WIDTH 1
connect \A \sdr_dq_11__core__oe
connect \B \io_bd [117]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139986$5792_Y
+ connect \Y $ternary$libresoc.v:139650$5740_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139987$5793
+ cell $mux $ternary$libresoc.v:139651$5741
parameter \WIDTH 1
connect \A \sdr_dq_12__pad__i
connect \B \io_bd [118]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139987$5793_Y
+ connect \Y $ternary$libresoc.v:139651$5741_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139988$5794
+ cell $mux $ternary$libresoc.v:139652$5742
parameter \WIDTH 1
connect \A \sdr_dq_12__core__o
connect \B \io_bd [119]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139988$5794_Y
+ connect \Y $ternary$libresoc.v:139652$5742_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139989$5795
+ cell $mux $ternary$libresoc.v:139653$5743
parameter \WIDTH 1
connect \A \sdr_dq_12__core__oe
connect \B \io_bd [120]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139989$5795_Y
+ connect \Y $ternary$libresoc.v:139653$5743_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139990$5796
+ cell $mux $ternary$libresoc.v:139654$5744
parameter \WIDTH 1
connect \A \sdr_dq_13__pad__i
connect \B \io_bd [121]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139990$5796_Y
+ connect \Y $ternary$libresoc.v:139654$5744_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139991$5797
+ cell $mux $ternary$libresoc.v:139655$5745
parameter \WIDTH 1
connect \A \sdr_dq_13__core__o
connect \B \io_bd [122]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139991$5797_Y
+ connect \Y $ternary$libresoc.v:139655$5745_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139992$5798
+ cell $mux $ternary$libresoc.v:139656$5746
parameter \WIDTH 1
connect \A \sdr_dq_13__core__oe
connect \B \io_bd [123]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139992$5798_Y
+ connect \Y $ternary$libresoc.v:139656$5746_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139994$5800
+ cell $mux $ternary$libresoc.v:139658$5748
parameter \WIDTH 1
connect \A \sdr_dq_14__pad__i
connect \B \io_bd [124]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139994$5800_Y
+ connect \Y $ternary$libresoc.v:139658$5748_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139995$5801
+ cell $mux $ternary$libresoc.v:139659$5749
parameter \WIDTH 1
connect \A \sdr_dq_14__core__o
connect \B \io_bd [125]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139995$5801_Y
+ connect \Y $ternary$libresoc.v:139659$5749_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139996$5802
+ cell $mux $ternary$libresoc.v:139660$5750
parameter \WIDTH 1
connect \A \sdr_dq_14__core__oe
connect \B \io_bd [126]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139996$5802_Y
+ connect \Y $ternary$libresoc.v:139660$5750_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:139997$5803
+ cell $mux $ternary$libresoc.v:139661$5751
parameter \WIDTH 1
connect \A \sdr_dq_15__pad__i
connect \B \io_bd [127]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:139997$5803_Y
+ connect \Y $ternary$libresoc.v:139661$5751_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:139998$5804
+ cell $mux $ternary$libresoc.v:139662$5752
parameter \WIDTH 1
connect \A \sdr_dq_15__core__o
connect \B \io_bd [128]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139998$5804_Y
+ connect \Y $ternary$libresoc.v:139662$5752_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:139999$5805
+ cell $mux $ternary$libresoc.v:139663$5753
parameter \WIDTH 1
connect \A \sdr_dq_15__core__oe
connect \B \io_bd [129]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:139999$5805_Y
+ connect \Y $ternary$libresoc.v:139663$5753_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:140088$5895
+ cell $mux $ternary$libresoc.v:139752$5843
parameter \WIDTH 1
connect \A \eint_0__pad__i
connect \B \io_bd [0]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140088$5895_Y
+ connect \Y $ternary$libresoc.v:139752$5843_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:140089$5896
+ cell $mux $ternary$libresoc.v:139753$5844
parameter \WIDTH 1
connect \A \eint_1__pad__i
connect \B \io_bd [1]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140089$5896_Y
+ connect \Y $ternary$libresoc.v:139753$5844_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:140090$5897
+ cell $mux $ternary$libresoc.v:139754$5845
parameter \WIDTH 1
connect \A \eint_2__pad__i
connect \B \io_bd [2]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140090$5897_Y
+ connect \Y $ternary$libresoc.v:139754$5845_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140091$5898
+ cell $mux $ternary$libresoc.v:139755$5846
parameter \WIDTH 1
connect \A \gpio_e8__pad__i
connect \B \io_bd [3]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140091$5898_Y
+ connect \Y $ternary$libresoc.v:139755$5846_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140093$5900
+ cell $mux $ternary$libresoc.v:139757$5848
parameter \WIDTH 1
connect \A \gpio_e8__core__o
connect \B \io_bd [4]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140093$5900_Y
+ connect \Y $ternary$libresoc.v:139757$5848_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140094$5901
+ cell $mux $ternary$libresoc.v:139758$5849
parameter \WIDTH 1
connect \A \gpio_e8__core__oe
connect \B \io_bd [5]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140094$5901_Y
+ connect \Y $ternary$libresoc.v:139758$5849_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140095$5902
+ cell $mux $ternary$libresoc.v:139759$5850
parameter \WIDTH 1
connect \A \gpio_e9__pad__i
connect \B \io_bd [6]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140095$5902_Y
+ connect \Y $ternary$libresoc.v:139759$5850_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140096$5903
+ cell $mux $ternary$libresoc.v:139760$5851
parameter \WIDTH 1
connect \A \gpio_e9__core__o
connect \B \io_bd [7]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140096$5903_Y
+ connect \Y $ternary$libresoc.v:139760$5851_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140097$5904
+ cell $mux $ternary$libresoc.v:139761$5852
parameter \WIDTH 1
connect \A \gpio_e9__core__oe
connect \B \io_bd [8]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140097$5904_Y
+ connect \Y $ternary$libresoc.v:139761$5852_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140098$5905
+ cell $mux $ternary$libresoc.v:139762$5853
parameter \WIDTH 1
connect \A \gpio_e10__pad__i
connect \B \io_bd [9]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140098$5905_Y
+ connect \Y $ternary$libresoc.v:139762$5853_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140099$5906
+ cell $mux $ternary$libresoc.v:139763$5854
parameter \WIDTH 1
connect \A \gpio_e10__core__o
connect \B \io_bd [10]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140099$5906_Y
+ connect \Y $ternary$libresoc.v:139763$5854_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140100$5907
+ cell $mux $ternary$libresoc.v:139764$5855
parameter \WIDTH 1
connect \A \gpio_e10__core__oe
connect \B \io_bd [11]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140100$5907_Y
+ connect \Y $ternary$libresoc.v:139764$5855_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140101$5908
+ cell $mux $ternary$libresoc.v:139765$5856
parameter \WIDTH 1
connect \A \gpio_e11__pad__i
connect \B \io_bd [12]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140101$5908_Y
+ connect \Y $ternary$libresoc.v:139765$5856_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140102$5909
+ cell $mux $ternary$libresoc.v:139766$5857
parameter \WIDTH 1
connect \A \gpio_e11__core__o
connect \B \io_bd [13]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140102$5909_Y
+ connect \Y $ternary$libresoc.v:139766$5857_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140104$5911
+ cell $mux $ternary$libresoc.v:139768$5859
parameter \WIDTH 1
connect \A \gpio_e11__core__oe
connect \B \io_bd [14]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140104$5911_Y
+ connect \Y $ternary$libresoc.v:139768$5859_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140105$5912
+ cell $mux $ternary$libresoc.v:139769$5860
parameter \WIDTH 1
connect \A \gpio_e12__pad__i
connect \B \io_bd [15]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140105$5912_Y
+ connect \Y $ternary$libresoc.v:139769$5860_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140106$5913
+ cell $mux $ternary$libresoc.v:139770$5861
parameter \WIDTH 1
connect \A \gpio_e12__core__o
connect \B \io_bd [16]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140106$5913_Y
+ connect \Y $ternary$libresoc.v:139770$5861_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140107$5914
+ cell $mux $ternary$libresoc.v:139771$5862
parameter \WIDTH 1
connect \A \gpio_e12__core__oe
connect \B \io_bd [17]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140107$5914_Y
+ connect \Y $ternary$libresoc.v:139771$5862_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140108$5915
+ cell $mux $ternary$libresoc.v:139772$5863
parameter \WIDTH 1
connect \A \gpio_e13__pad__i
connect \B \io_bd [18]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140108$5915_Y
+ connect \Y $ternary$libresoc.v:139772$5863_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140109$5916
+ cell $mux $ternary$libresoc.v:139773$5864
parameter \WIDTH 1
connect \A \gpio_e13__core__o
connect \B \io_bd [19]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140109$5916_Y
+ connect \Y $ternary$libresoc.v:139773$5864_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140110$5917
+ cell $mux $ternary$libresoc.v:139774$5865
parameter \WIDTH 1
connect \A \gpio_e13__core__oe
connect \B \io_bd [20]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140110$5917_Y
+ connect \Y $ternary$libresoc.v:139774$5865_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:140111$5918
+ cell $mux $ternary$libresoc.v:139775$5866
parameter \WIDTH 1
connect \A \gpio_e14__pad__i
connect \B \io_bd [21]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:140111$5918_Y
+ connect \Y $ternary$libresoc.v:139775$5866_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:140112$5919
+ cell $mux $ternary$libresoc.v:139776$5867
parameter \WIDTH 1
connect \A \gpio_e14__core__o
connect \B \io_bd [22]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140112$5919_Y
+ connect \Y $ternary$libresoc.v:139776$5867_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:140113$5920
+ cell $mux $ternary$libresoc.v:139777$5868
parameter \WIDTH 1
connect \A \gpio_e14__core__oe
connect \B \io_bd [23]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:140113$5920_Y
+ connect \Y $ternary$libresoc.v:139777$5868_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140188.8-140200.4"
+ attribute \src "libresoc.v:139852.8-139864.4"
cell \_fsm \_fsm
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tms \TAP_bus__tms
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140201.12-140211.4"
+ attribute \src "libresoc.v:139865.12-139875.4"
cell \_idblock \_idblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \TAP_id_tdo \_idblock_TAP_id_tdo
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140212.12-140222.4"
+ attribute \src "libresoc.v:139876.12-139886.4"
cell \_irblock \_irblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \capture \_fsm_capture
connect \tdo \_irblock_tdo
connect \update \_fsm_update
end
- attribute \src "libresoc.v:138592.7-138592.20"
- process $proc$libresoc.v:138592$6116
+ attribute \src "libresoc.v:138256.7-138256.20"
+ process $proc$libresoc.v:138256$6064
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:139102.13-139102.32"
- process $proc$libresoc.v:139102$6117
+ attribute \src "libresoc.v:138766.13-138766.32"
+ process $proc$libresoc.v:138766$6065
assign { } { }
assign $1\dmi0__addr_i[3:0] 4'0000
sync always
sync init
update \dmi0__addr_i $1\dmi0__addr_i[3:0]
end
- attribute \src "libresoc.v:139107.14-139107.46"
- process $proc$libresoc.v:139107$6118
+ attribute \src "libresoc.v:138771.14-138771.46"
+ process $proc$libresoc.v:138771$6066
assign { } { }
assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0__din $1\dmi0__din[63:0]
end
- attribute \src "libresoc.v:139121.7-139121.29"
- process $proc$libresoc.v:139121$6119
+ attribute \src "libresoc.v:138785.7-138785.29"
+ process $proc$libresoc.v:138785$6067
assign { } { }
assign $1\dmi0_addrsr__oe[0:0] 1'0
sync always
sync init
update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:139129.13-139129.36"
- process $proc$libresoc.v:139129$6120
+ attribute \src "libresoc.v:138793.13-138793.36"
+ process $proc$libresoc.v:138793$6068
assign { } { }
assign $1\dmi0_addrsr_reg[7:0] 8'00000000
sync always
sync init
update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:139137.7-139137.37"
- process $proc$libresoc.v:139137$6121
+ attribute \src "libresoc.v:138801.7-138801.37"
+ process $proc$libresoc.v:138801$6069
assign { } { }
assign $1\dmi0_addrsr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:139141.7-139141.42"
- process $proc$libresoc.v:139141$6122
+ attribute \src "libresoc.v:138805.7-138805.42"
+ process $proc$libresoc.v:138805$6070
assign { } { }
assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139145.14-139145.51"
- process $proc$libresoc.v:139145$6123
+ attribute \src "libresoc.v:138809.14-138809.51"
+ process $proc$libresoc.v:138809$6071
assign { } { }
assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr__i $1\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:139151.13-139151.35"
- process $proc$libresoc.v:139151$6124
+ attribute \src "libresoc.v:138815.13-138815.35"
+ process $proc$libresoc.v:138815$6072
assign { } { }
assign $1\dmi0_datasr__oe[1:0] 2'00
sync always
sync init
update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:139159.14-139159.52"
- process $proc$libresoc.v:139159$6125
+ attribute \src "libresoc.v:138823.14-138823.52"
+ process $proc$libresoc.v:138823$6073
assign { } { }
assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:139167.7-139167.37"
- process $proc$libresoc.v:139167$6126
+ attribute \src "libresoc.v:138831.7-138831.37"
+ process $proc$libresoc.v:138831$6074
assign { } { }
assign $1\dmi0_datasr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:139171.7-139171.42"
- process $proc$libresoc.v:139171$6127
+ attribute \src "libresoc.v:138835.7-138835.42"
+ process $proc$libresoc.v:138835$6075
assign { } { }
assign $1\dmi0_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139187.13-139187.29"
- process $proc$libresoc.v:139187$6128
+ attribute \src "libresoc.v:138851.13-138851.29"
+ process $proc$libresoc.v:138851$6076
assign { } { }
assign $1\fsm_state[2:0] 3'000
sync always
sync init
update \fsm_state $1\fsm_state[2:0]
end
- attribute \src "libresoc.v:139189.13-139189.35"
- process $proc$libresoc.v:139189$6129
+ attribute \src "libresoc.v:138853.13-138853.35"
+ process $proc$libresoc.v:138853$6077
assign { } { }
- assign $0\fsm_state$455[2:0]$6130 3'000
+ assign $0\fsm_state$455[2:0]$6078 3'000
sync always
sync init
- update \fsm_state$455 $0\fsm_state$455[2:0]$6130
+ update \fsm_state$455 $0\fsm_state$455[2:0]$6078
end
- attribute \src "libresoc.v:139387.15-139387.61"
- process $proc$libresoc.v:139387$6131
+ attribute \src "libresoc.v:139051.15-139051.61"
+ process $proc$libresoc.v:139051$6079
assign { } { }
assign $1\io_bd[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \io_bd $1\io_bd[129:0]
end
- attribute \src "libresoc.v:139399.15-139399.61"
- process $proc$libresoc.v:139399$6132
+ attribute \src "libresoc.v:139063.15-139063.61"
+ process $proc$libresoc.v:139063$6080
assign { } { }
assign $1\io_sr[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \io_sr $1\io_sr[129:0]
end
- attribute \src "libresoc.v:139408.14-139408.41"
- process $proc$libresoc.v:139408$6133
+ attribute \src "libresoc.v:139072.14-139072.41"
+ process $proc$libresoc.v:139072$6081
assign { } { }
assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb__adr $1\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:139417.14-139417.51"
- process $proc$libresoc.v:139417$6134
+ attribute \src "libresoc.v:139081.14-139081.51"
+ process $proc$libresoc.v:139081$6082
assign { } { }
assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:139431.7-139431.32"
- process $proc$libresoc.v:139431$6135
+ attribute \src "libresoc.v:139095.7-139095.32"
+ process $proc$libresoc.v:139095$6083
assign { } { }
assign $1\jtag_wb_addrsr__oe[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:139439.14-139439.47"
- process $proc$libresoc.v:139439$6136
+ attribute \src "libresoc.v:139103.14-139103.47"
+ process $proc$libresoc.v:139103$6084
assign { } { }
assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:139447.7-139447.40"
- process $proc$libresoc.v:139447$6137
+ attribute \src "libresoc.v:139111.7-139111.40"
+ process $proc$libresoc.v:139111$6085
assign { } { }
assign $1\jtag_wb_addrsr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:139451.7-139451.45"
- process $proc$libresoc.v:139451$6138
+ attribute \src "libresoc.v:139115.7-139115.45"
+ process $proc$libresoc.v:139115$6086
assign { } { }
assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139455.14-139455.54"
- process $proc$libresoc.v:139455$6139
+ attribute \src "libresoc.v:139119.14-139119.54"
+ process $proc$libresoc.v:139119$6087
assign { } { }
assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:139461.13-139461.38"
- process $proc$libresoc.v:139461$6140
+ attribute \src "libresoc.v:139125.13-139125.38"
+ process $proc$libresoc.v:139125$6088
assign { } { }
assign $1\jtag_wb_datasr__oe[1:0] 2'00
sync always
sync init
update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:139469.14-139469.55"
- process $proc$libresoc.v:139469$6141
+ attribute \src "libresoc.v:139133.14-139133.55"
+ process $proc$libresoc.v:139133$6089
assign { } { }
assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:139477.7-139477.40"
- process $proc$libresoc.v:139477$6142
+ attribute \src "libresoc.v:139141.7-139141.40"
+ process $proc$libresoc.v:139141$6090
assign { } { }
assign $1\jtag_wb_datasr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:139481.7-139481.45"
- process $proc$libresoc.v:139481$6143
+ attribute \src "libresoc.v:139145.7-139145.45"
+ process $proc$libresoc.v:139145$6091
assign { } { }
assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139815.7-139815.21"
- process $proc$libresoc.v:139815$6144
+ attribute \src "libresoc.v:139479.7-139479.21"
+ process $proc$libresoc.v:139479$6092
assign { } { }
assign $1\sr0__oe[0:0] 1'0
sync always
sync init
update \sr0__oe $1\sr0__oe[0:0]
end
- attribute \src "libresoc.v:139823.13-139823.27"
- process $proc$libresoc.v:139823$6145
+ attribute \src "libresoc.v:139487.13-139487.27"
+ process $proc$libresoc.v:139487$6093
assign { } { }
assign $1\sr0_reg[2:0] 3'000
sync always
sync init
update \sr0_reg $1\sr0_reg[2:0]
end
- attribute \src "libresoc.v:139831.7-139831.29"
- process $proc$libresoc.v:139831$6146
+ attribute \src "libresoc.v:139495.7-139495.29"
+ process $proc$libresoc.v:139495$6094
assign { } { }
assign $1\sr0_update_core[0:0] 1'0
sync always
sync init
update \sr0_update_core $1\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:139835.7-139835.34"
- process $proc$libresoc.v:139835$6147
+ attribute \src "libresoc.v:139499.7-139499.34"
+ process $proc$libresoc.v:139499$6095
assign { } { }
assign $1\sr0_update_core_prev[0:0] 1'0
sync always
sync init
update \sr0_update_core_prev $1\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139845.7-139845.21"
- process $proc$libresoc.v:139845$6148
+ attribute \src "libresoc.v:139509.7-139509.21"
+ process $proc$libresoc.v:139509$6096
assign { } { }
assign $1\sr5__oe[0:0] 1'0
sync always
sync init
update \sr5__oe $1\sr5__oe[0:0]
end
- attribute \src "libresoc.v:139853.13-139853.27"
- process $proc$libresoc.v:139853$6149
+ attribute \src "libresoc.v:139517.13-139517.27"
+ process $proc$libresoc.v:139517$6097
assign { } { }
assign $1\sr5_reg[2:0] 3'000
sync always
sync init
update \sr5_reg $1\sr5_reg[2:0]
end
- attribute \src "libresoc.v:139861.7-139861.29"
- process $proc$libresoc.v:139861$6150
+ attribute \src "libresoc.v:139525.7-139525.29"
+ process $proc$libresoc.v:139525$6098
assign { } { }
assign $1\sr5_update_core[0:0] 1'0
sync always
sync init
update \sr5_update_core $1\sr5_update_core[0:0]
end
- attribute \src "libresoc.v:139865.7-139865.34"
- process $proc$libresoc.v:139865$6151
+ attribute \src "libresoc.v:139529.7-139529.34"
+ process $proc$libresoc.v:139529$6099
assign { } { }
assign $1\sr5_update_core_prev[0:0] 1'0
sync always
sync init
update \sr5_update_core_prev $1\sr5_update_core_prev[0:0]
end
- attribute \src "libresoc.v:139870.7-139870.26"
- process $proc$libresoc.v:139870$6152
+ attribute \src "libresoc.v:139534.7-139534.26"
+ process $proc$libresoc.v:139534$6100
assign { } { }
assign $1\wb_dcache_en[0:0] 1'1
sync always
sync init
update \wb_dcache_en $1\wb_dcache_en[0:0]
end
- attribute \src "libresoc.v:139875.7-139875.26"
- process $proc$libresoc.v:139875$6153
+ attribute \src "libresoc.v:139539.7-139539.26"
+ process $proc$libresoc.v:139539$6101
assign { } { }
assign $1\wb_icache_en[0:0] 1'1
sync always
sync init
update \wb_icache_en $1\wb_icache_en[0:0]
end
- attribute \src "libresoc.v:139879.7-139879.24"
- process $proc$libresoc.v:139879$6154
+ attribute \src "libresoc.v:139543.7-139543.24"
+ process $proc$libresoc.v:139543$6102
assign { } { }
assign $1\wb_sram_en[0:0] 1'1
sync always
sync init
update \wb_sram_en $1\wb_sram_en[0:0]
end
- attribute \src "libresoc.v:140114.3-140115.41"
- process $proc$libresoc.v:140114$5921
+ attribute \src "libresoc.v:139778.3-139779.41"
+ process $proc$libresoc.v:139778$5869
assign { } { }
assign $0\wb_icache_en[0:0] \wb_icache_en$next
sync posedge \clk
update \wb_icache_en $0\wb_icache_en[0:0]
end
- attribute \src "libresoc.v:140116.3-140117.41"
- process $proc$libresoc.v:140116$5922
+ attribute \src "libresoc.v:139780.3-139781.41"
+ process $proc$libresoc.v:139780$5870
assign { } { }
assign $0\wb_dcache_en[0:0] \wb_dcache_en$next
sync posedge \clk
update \wb_dcache_en $0\wb_dcache_en[0:0]
end
- attribute \src "libresoc.v:140118.3-140119.37"
- process $proc$libresoc.v:140118$5923
+ attribute \src "libresoc.v:139782.3-139783.37"
+ process $proc$libresoc.v:139782$5871
assign { } { }
assign $0\wb_sram_en[0:0] \wb_sram_en$next
sync posedge \clk
update \wb_sram_en $0\wb_sram_en[0:0]
end
- attribute \src "libresoc.v:140120.3-140121.45"
- process $proc$libresoc.v:140120$5924
+ attribute \src "libresoc.v:139784.3-139785.45"
+ process $proc$libresoc.v:139784$5872
assign { } { }
assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next
sync posedge \clk
update \dmi0_datasr__i $0\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:140122.3-140123.35"
- process $proc$libresoc.v:140122$5925
+ attribute \src "libresoc.v:139786.3-139787.35"
+ process $proc$libresoc.v:139786$5873
assign { } { }
assign $0\dmi0__din[63:0] \dmi0__din$next
sync posedge \clk
update \dmi0__din $0\dmi0__din[63:0]
end
- attribute \src "libresoc.v:140124.3-140125.45"
- process $proc$libresoc.v:140124$5926
+ attribute \src "libresoc.v:139788.3-139789.45"
+ process $proc$libresoc.v:139788$5874
assign { } { }
- assign $0\fsm_state$455[2:0]$5927 \fsm_state$455$next
+ assign $0\fsm_state$455[2:0]$5875 \fsm_state$455$next
sync posedge \clk
- update \fsm_state$455 $0\fsm_state$455[2:0]$5927
+ update \fsm_state$455 $0\fsm_state$455[2:0]$5875
end
- attribute \src "libresoc.v:140126.3-140127.41"
- process $proc$libresoc.v:140126$5928
+ attribute \src "libresoc.v:139790.3-139791.41"
+ process $proc$libresoc.v:139790$5876
assign { } { }
assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next
sync posedge \clk
update \dmi0__addr_i $0\dmi0__addr_i[3:0]
end
- attribute \src "libresoc.v:140128.3-140129.51"
- process $proc$libresoc.v:140128$5929
+ attribute \src "libresoc.v:139792.3-139793.51"
+ process $proc$libresoc.v:139792$5877
assign { } { }
assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next
sync posedge \clk
update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:140130.3-140131.45"
- process $proc$libresoc.v:140130$5930
+ attribute \src "libresoc.v:139794.3-139795.45"
+ process $proc$libresoc.v:139794$5878
assign { } { }
assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next
sync posedge \clk
update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:140132.3-140133.35"
- process $proc$libresoc.v:140132$5931
+ attribute \src "libresoc.v:139796.3-139797.35"
+ process $proc$libresoc.v:139796$5879
assign { } { }
assign $0\fsm_state[2:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[2:0]
end
- attribute \src "libresoc.v:140134.3-140135.41"
- process $proc$libresoc.v:140134$5932
+ attribute \src "libresoc.v:139798.3-139799.41"
+ process $proc$libresoc.v:139798$5880
assign { } { }
assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next
sync posedge \clk
update \jtag_wb__adr $0\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:140136.3-140137.31"
- process $proc$libresoc.v:140136$5933
+ attribute \src "libresoc.v:139800.3-139801.31"
+ process $proc$libresoc.v:139800$5881
assign { } { }
assign $0\sr5_reg[2:0] \sr5_reg$next
sync posedge \posjtag_clk
update \sr5_reg $0\sr5_reg[2:0]
end
- attribute \src "libresoc.v:140138.3-140139.31"
- process $proc$libresoc.v:140138$5934
+ attribute \src "libresoc.v:139802.3-139803.31"
+ process $proc$libresoc.v:139802$5882
assign { } { }
assign $0\sr5__oe[0:0] \sr5__oe$next
sync posedge \clk
update \sr5__oe $0\sr5__oe[0:0]
end
- attribute \src "libresoc.v:140140.3-140141.57"
- process $proc$libresoc.v:140140$5935
+ attribute \src "libresoc.v:139804.3-139805.57"
+ process $proc$libresoc.v:139804$5883
assign { } { }
assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next
sync posedge \clk
update \sr5_update_core_prev $0\sr5_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140142.3-140143.47"
- process $proc$libresoc.v:140142$5936
+ attribute \src "libresoc.v:139806.3-139807.47"
+ process $proc$libresoc.v:139806$5884
assign { } { }
assign $0\sr5_update_core[0:0] \sr5_update_core$next
sync posedge \clk
update \sr5_update_core $0\sr5_update_core[0:0]
end
- attribute \src "libresoc.v:140144.3-140145.47"
- process $proc$libresoc.v:140144$5937
+ attribute \src "libresoc.v:139808.3-139809.47"
+ process $proc$libresoc.v:139808$5885
assign { } { }
assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next
sync posedge \posjtag_clk
update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:140146.3-140147.47"
- process $proc$libresoc.v:140146$5938
+ attribute \src "libresoc.v:139810.3-139811.47"
+ process $proc$libresoc.v:139810$5886
assign { } { }
assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next
sync posedge \clk
update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:140148.3-140149.73"
- process $proc$libresoc.v:140148$5939
+ attribute \src "libresoc.v:139812.3-139813.73"
+ process $proc$libresoc.v:139812$5887
assign { } { }
assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next
sync posedge \clk
update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140150.3-140151.63"
- process $proc$libresoc.v:140150$5940
+ attribute \src "libresoc.v:139814.3-139815.63"
+ process $proc$libresoc.v:139814$5888
assign { } { }
assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next
sync posedge \clk
update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:140152.3-140153.47"
- process $proc$libresoc.v:140152$5941
+ attribute \src "libresoc.v:139816.3-139817.47"
+ process $proc$libresoc.v:139816$5889
assign { } { }
assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next
sync posedge \posjtag_clk
update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:140154.3-140155.47"
- process $proc$libresoc.v:140154$5942
+ attribute \src "libresoc.v:139818.3-139819.47"
+ process $proc$libresoc.v:139818$5890
assign { } { }
assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next
sync posedge \clk
update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:140156.3-140157.73"
- process $proc$libresoc.v:140156$5943
+ attribute \src "libresoc.v:139820.3-139821.73"
+ process $proc$libresoc.v:139820$5891
assign { } { }
assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next
sync posedge \clk
update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140158.3-140159.63"
- process $proc$libresoc.v:140158$5944
+ attribute \src "libresoc.v:139822.3-139823.63"
+ process $proc$libresoc.v:139822$5892
assign { } { }
assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next
sync posedge \clk
update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:140160.3-140161.53"
- process $proc$libresoc.v:140160$5945
+ attribute \src "libresoc.v:139824.3-139825.53"
+ process $proc$libresoc.v:139824$5893
assign { } { }
assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:140162.3-140163.53"
- process $proc$libresoc.v:140162$5946
+ attribute \src "libresoc.v:139826.3-139827.53"
+ process $proc$libresoc.v:139826$5894
assign { } { }
assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next
sync posedge \clk
update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:140164.3-140165.79"
- process $proc$libresoc.v:140164$5947
+ attribute \src "libresoc.v:139828.3-139829.79"
+ process $proc$libresoc.v:139828$5895
assign { } { }
assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next
sync posedge \clk
update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140166.3-140167.69"
- process $proc$libresoc.v:140166$5948
+ attribute \src "libresoc.v:139830.3-139831.69"
+ process $proc$libresoc.v:139830$5896
assign { } { }
assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next
sync posedge \clk
update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:140168.3-140169.53"
- process $proc$libresoc.v:140168$5949
+ attribute \src "libresoc.v:139832.3-139833.53"
+ process $proc$libresoc.v:139832$5897
assign { } { }
assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:140170.3-140171.53"
- process $proc$libresoc.v:140170$5950
+ attribute \src "libresoc.v:139834.3-139835.53"
+ process $proc$libresoc.v:139834$5898
assign { } { }
assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next
sync posedge \clk
update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:140172.3-140173.79"
- process $proc$libresoc.v:140172$5951
+ attribute \src "libresoc.v:139836.3-139837.79"
+ process $proc$libresoc.v:139836$5899
assign { } { }
assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next
sync posedge \clk
update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140174.3-140175.69"
- process $proc$libresoc.v:140174$5952
+ attribute \src "libresoc.v:139838.3-139839.69"
+ process $proc$libresoc.v:139838$5900
assign { } { }
assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next
sync posedge \clk
update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:140176.3-140177.31"
- process $proc$libresoc.v:140176$5953
+ attribute \src "libresoc.v:139840.3-139841.31"
+ process $proc$libresoc.v:139840$5901
assign { } { }
assign $0\sr0_reg[2:0] \sr0_reg$next
sync posedge \posjtag_clk
update \sr0_reg $0\sr0_reg[2:0]
end
- attribute \src "libresoc.v:140178.3-140179.31"
- process $proc$libresoc.v:140178$5954
+ attribute \src "libresoc.v:139842.3-139843.31"
+ process $proc$libresoc.v:139842$5902
assign { } { }
assign $0\sr0__oe[0:0] \sr0__oe$next
sync posedge \clk
update \sr0__oe $0\sr0__oe[0:0]
end
- attribute \src "libresoc.v:140180.3-140181.57"
- process $proc$libresoc.v:140180$5955
+ attribute \src "libresoc.v:139844.3-139845.57"
+ process $proc$libresoc.v:139844$5903
assign { } { }
assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next
sync posedge \clk
update \sr0_update_core_prev $0\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:140182.3-140183.47"
- process $proc$libresoc.v:140182$5956
+ attribute \src "libresoc.v:139846.3-139847.47"
+ process $proc$libresoc.v:139846$5904
assign { } { }
assign $0\sr0_update_core[0:0] \sr0_update_core$next
sync posedge \clk
update \sr0_update_core $0\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:140184.3-140185.27"
- process $proc$libresoc.v:140184$5957
+ attribute \src "libresoc.v:139848.3-139849.27"
+ process $proc$libresoc.v:139848$5905
assign { } { }
assign $0\io_bd[129:0] \io_bd$next
sync negedge \negjtag_clk
update \io_bd $0\io_bd[129:0]
end
- attribute \src "libresoc.v:140186.3-140187.27"
- process $proc$libresoc.v:140186$5958
+ attribute \src "libresoc.v:139850.3-139851.27"
+ process $proc$libresoc.v:139850$5906
assign { } { }
assign $0\io_sr[129:0] \io_sr$next
sync posedge \posjtag_clk
update \io_sr $0\io_sr[129:0]
end
- attribute \src "libresoc.v:140223.3-140238.6"
- process $proc$libresoc.v:140223$5959
+ attribute \src "libresoc.v:139887.3-139902.6"
+ process $proc$libresoc.v:139887$5907
assign { } { }
assign { } { }
assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:140224.5-140224.29"
+ attribute \src "libresoc.v:139888.5-139888.29"
switch \initial
- attribute \src "libresoc.v:140224.9-140224.17"
+ attribute \src "libresoc.v:139888.9-139888.17"
case 1'1
case
end
sync always
update \TAP_tdo $0\TAP_tdo[0:0]
end
- attribute \src "libresoc.v:140239.3-140247.6"
- process $proc$libresoc.v:140239$5960
+ attribute \src "libresoc.v:139903.3-139911.6"
+ process $proc$libresoc.v:139903$5908
assign { } { }
assign { } { }
- assign $0\sr0_update_core$next[0:0]$5961 $1\sr0_update_core$next[0:0]$5962
- attribute \src "libresoc.v:140240.5-140240.29"
+ assign $0\sr0_update_core$next[0:0]$5909 $1\sr0_update_core$next[0:0]$5910
+ attribute \src "libresoc.v:139904.5-139904.29"
switch \initial
- attribute \src "libresoc.v:140240.9-140240.17"
+ attribute \src "libresoc.v:139904.9-139904.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core$next[0:0]$5962 1'0
+ assign $1\sr0_update_core$next[0:0]$5910 1'0
case
- assign $1\sr0_update_core$next[0:0]$5962 \sr0_update
+ assign $1\sr0_update_core$next[0:0]$5910 \sr0_update
end
sync always
- update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5961
+ update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5909
end
- attribute \src "libresoc.v:140248.3-140256.6"
- process $proc$libresoc.v:140248$5963
+ attribute \src "libresoc.v:139912.3-139920.6"
+ process $proc$libresoc.v:139912$5911
assign { } { }
assign { } { }
- assign $0\sr0_update_core_prev$next[0:0]$5964 $1\sr0_update_core_prev$next[0:0]$5965
- attribute \src "libresoc.v:140249.5-140249.29"
+ assign $0\sr0_update_core_prev$next[0:0]$5912 $1\sr0_update_core_prev$next[0:0]$5913
+ attribute \src "libresoc.v:139913.5-139913.29"
switch \initial
- attribute \src "libresoc.v:140249.9-140249.17"
+ attribute \src "libresoc.v:139913.9-139913.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core_prev$next[0:0]$5965 1'0
+ assign $1\sr0_update_core_prev$next[0:0]$5913 1'0
case
- assign $1\sr0_update_core_prev$next[0:0]$5965 \sr0_update_core
+ assign $1\sr0_update_core_prev$next[0:0]$5913 \sr0_update_core
end
sync always
- update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5964
+ update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5912
end
- attribute \src "libresoc.v:140257.3-140273.6"
- process $proc$libresoc.v:140257$5966
+ attribute \src "libresoc.v:139921.3-139937.6"
+ process $proc$libresoc.v:139921$5914
assign { } { }
assign { } { }
- assign $0\sr0__oe$next[0:0]$5967 $2\sr0__oe$next[0:0]$5969
- attribute \src "libresoc.v:140258.5-140258.29"
+ assign $0\sr0__oe$next[0:0]$5915 $2\sr0__oe$next[0:0]$5917
+ attribute \src "libresoc.v:139922.5-139922.29"
switch \initial
- attribute \src "libresoc.v:140258.9-140258.17"
+ attribute \src "libresoc.v:139922.9-139922.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0__oe$next[0:0]$5968 \sr0_isir
+ assign $1\sr0__oe$next[0:0]$5916 \sr0_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\sr0__oe$next[0:0]$5968 1'0
+ assign $1\sr0__oe$next[0:0]$5916 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0__oe$next[0:0]$5969 1'0
+ assign $2\sr0__oe$next[0:0]$5917 1'0
case
- assign $2\sr0__oe$next[0:0]$5969 $1\sr0__oe$next[0:0]$5968
+ assign $2\sr0__oe$next[0:0]$5917 $1\sr0__oe$next[0:0]$5916
end
sync always
- update \sr0__oe$next $0\sr0__oe$next[0:0]$5967
+ update \sr0__oe$next $0\sr0__oe$next[0:0]$5915
end
- attribute \src "libresoc.v:140274.3-140294.6"
- process $proc$libresoc.v:140274$5970
+ attribute \src "libresoc.v:139938.3-139958.6"
+ process $proc$libresoc.v:139938$5918
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr0_reg$next[2:0]$5971 $3\sr0_reg$next[2:0]$5974
- attribute \src "libresoc.v:140275.5-140275.29"
+ assign $0\sr0_reg$next[2:0]$5919 $3\sr0_reg$next[2:0]$5922
+ attribute \src "libresoc.v:139939.5-139939.29"
switch \initial
- attribute \src "libresoc.v:140275.9-140275.17"
+ attribute \src "libresoc.v:139939.9-139939.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_reg$next[2:0]$5972 { \TAP_bus__tdi \sr0_reg [2:1] }
+ assign $1\sr0_reg$next[2:0]$5920 { \TAP_bus__tdi \sr0_reg [2:1] }
case
- assign $1\sr0_reg$next[2:0]$5972 \sr0_reg
+ assign $1\sr0_reg$next[2:0]$5920 \sr0_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \sr0_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0_reg$next[2:0]$5973 \sr0__i
+ assign $2\sr0_reg$next[2:0]$5921 \sr0__i
case
- assign $2\sr0_reg$next[2:0]$5973 $1\sr0_reg$next[2:0]$5972
+ assign $2\sr0_reg$next[2:0]$5921 $1\sr0_reg$next[2:0]$5920
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sr0_reg$next[2:0]$5974 3'000
+ assign $3\sr0_reg$next[2:0]$5922 3'000
case
- assign $3\sr0_reg$next[2:0]$5974 $2\sr0_reg$next[2:0]$5973
+ assign $3\sr0_reg$next[2:0]$5922 $2\sr0_reg$next[2:0]$5921
end
sync always
- update \sr0_reg$next $0\sr0_reg$next[2:0]$5971
+ update \sr0_reg$next $0\sr0_reg$next[2:0]$5919
end
- attribute \src "libresoc.v:140295.3-140303.6"
- process $proc$libresoc.v:140295$5975
+ attribute \src "libresoc.v:139959.3-139967.6"
+ process $proc$libresoc.v:139959$5923
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core$next[0:0]$5976 $1\jtag_wb_addrsr_update_core$next[0:0]$5977
- attribute \src "libresoc.v:140296.5-140296.29"
+ assign $0\jtag_wb_addrsr_update_core$next[0:0]$5924 $1\jtag_wb_addrsr_update_core$next[0:0]$5925
+ attribute \src "libresoc.v:139960.5-139960.29"
switch \initial
- attribute \src "libresoc.v:140296.9-140296.17"
+ attribute \src "libresoc.v:139960.9-139960.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$5977 1'0
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 1'0
case
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$5977 \jtag_wb_addrsr_update
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 \jtag_wb_addrsr_update
end
sync always
- update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5976
+ update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5924
end
- attribute \src "libresoc.v:140304.3-140312.6"
- process $proc$libresoc.v:140304$5978
+ attribute \src "libresoc.v:139968.3-139976.6"
+ process $proc$libresoc.v:139968$5926
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980
- attribute \src "libresoc.v:140305.5-140305.29"
+ assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928
+ attribute \src "libresoc.v:139969.5-139969.29"
switch \initial
- attribute \src "libresoc.v:140305.9-140305.17"
+ attribute \src "libresoc.v:139969.9-139969.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 1'0
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 1'0
case
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 \jtag_wb_addrsr_update_core
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 \jtag_wb_addrsr_update_core
end
sync always
- update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979
+ update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927
end
- attribute \src "libresoc.v:140313.3-140329.6"
- process $proc$libresoc.v:140313$5981
+ attribute \src "libresoc.v:139977.3-139993.6"
+ process $proc$libresoc.v:139977$5929
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr__oe$next[0:0]$5982 $2\jtag_wb_addrsr__oe$next[0:0]$5984
- attribute \src "libresoc.v:140314.5-140314.29"
+ assign $0\jtag_wb_addrsr__oe$next[0:0]$5930 $2\jtag_wb_addrsr__oe$next[0:0]$5932
+ attribute \src "libresoc.v:139978.5-139978.29"
switch \initial
- attribute \src "libresoc.v:140314.9-140314.17"
+ attribute \src "libresoc.v:139978.9-139978.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$5983 \jtag_wb_addrsr_isir
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 \jtag_wb_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$5983 1'0
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr__oe$next[0:0]$5984 1'0
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 1'0
case
- assign $2\jtag_wb_addrsr__oe$next[0:0]$5984 $1\jtag_wb_addrsr__oe$next[0:0]$5983
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 $1\jtag_wb_addrsr__oe$next[0:0]$5931
end
sync always
- update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5982
+ update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5930
end
- attribute \src "libresoc.v:140330.3-140350.6"
- process $proc$libresoc.v:140330$5985
+ attribute \src "libresoc.v:139994.3-140014.6"
+ process $proc$libresoc.v:139994$5933
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_reg$next[28:0]$5986 $3\jtag_wb_addrsr_reg$next[28:0]$5989
- attribute \src "libresoc.v:140331.5-140331.29"
+ assign $0\jtag_wb_addrsr_reg$next[28:0]$5934 $3\jtag_wb_addrsr_reg$next[28:0]$5937
+ attribute \src "libresoc.v:139995.5-139995.29"
switch \initial
- attribute \src "libresoc.v:140331.9-140331.17"
+ attribute \src "libresoc.v:139995.9-139995.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_reg$next[28:0]$5987 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
case
- assign $1\jtag_wb_addrsr_reg$next[28:0]$5987 \jtag_wb_addrsr_reg
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 \jtag_wb_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \jtag_wb_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr_reg$next[28:0]$5988 \jtag_wb_addrsr__i
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 \jtag_wb_addrsr__i
case
- assign $2\jtag_wb_addrsr_reg$next[28:0]$5988 $1\jtag_wb_addrsr_reg$next[28:0]$5987
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 $1\jtag_wb_addrsr_reg$next[28:0]$5935
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_addrsr_reg$next[28:0]$5989 29'00000000000000000000000000000
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 29'00000000000000000000000000000
case
- assign $3\jtag_wb_addrsr_reg$next[28:0]$5989 $2\jtag_wb_addrsr_reg$next[28:0]$5988
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 $2\jtag_wb_addrsr_reg$next[28:0]$5936
end
sync always
- update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5986
+ update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5934
end
- attribute \src "libresoc.v:140351.3-140359.6"
- process $proc$libresoc.v:140351$5990
+ attribute \src "libresoc.v:140015.3-140023.6"
+ process $proc$libresoc.v:140015$5938
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core$next[0:0]$5991 $1\jtag_wb_datasr_update_core$next[0:0]$5992
- attribute \src "libresoc.v:140352.5-140352.29"
+ assign $0\jtag_wb_datasr_update_core$next[0:0]$5939 $1\jtag_wb_datasr_update_core$next[0:0]$5940
+ attribute \src "libresoc.v:140016.5-140016.29"
switch \initial
- attribute \src "libresoc.v:140352.9-140352.17"
+ attribute \src "libresoc.v:140016.9-140016.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core$next[0:0]$5992 1'0
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 1'0
case
- assign $1\jtag_wb_datasr_update_core$next[0:0]$5992 \jtag_wb_datasr_update
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 \jtag_wb_datasr_update
end
sync always
- update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5991
+ update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5939
end
- attribute \src "libresoc.v:140360.3-140368.6"
- process $proc$libresoc.v:140360$5993
+ attribute \src "libresoc.v:140024.3-140032.6"
+ process $proc$libresoc.v:140024$5941
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995
- attribute \src "libresoc.v:140361.5-140361.29"
+ assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943
+ attribute \src "libresoc.v:140025.5-140025.29"
switch \initial
- attribute \src "libresoc.v:140361.9-140361.17"
+ attribute \src "libresoc.v:140025.9-140025.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 1'0
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 1'0
case
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 \jtag_wb_datasr_update_core
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 \jtag_wb_datasr_update_core
end
sync always
- update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994
+ update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942
end
- attribute \src "libresoc.v:140369.3-140385.6"
- process $proc$libresoc.v:140369$5996
+ attribute \src "libresoc.v:140033.3-140049.6"
+ process $proc$libresoc.v:140033$5944
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__oe$next[1:0]$5997 $2\jtag_wb_datasr__oe$next[1:0]$5999
- attribute \src "libresoc.v:140370.5-140370.29"
+ assign $0\jtag_wb_datasr__oe$next[1:0]$5945 $2\jtag_wb_datasr__oe$next[1:0]$5947
+ attribute \src "libresoc.v:140034.5-140034.29"
switch \initial
- attribute \src "libresoc.v:140370.9-140370.17"
+ attribute \src "libresoc.v:140034.9-140034.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$5998 \jtag_wb_datasr_isir
+ assign $1\jtag_wb_datasr__oe$next[1:0]$5946 \jtag_wb_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$5998 2'00
+ assign $1\jtag_wb_datasr__oe$next[1:0]$5946 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__oe$next[1:0]$5999 2'00
+ assign $2\jtag_wb_datasr__oe$next[1:0]$5947 2'00
case
- assign $2\jtag_wb_datasr__oe$next[1:0]$5999 $1\jtag_wb_datasr__oe$next[1:0]$5998
+ assign $2\jtag_wb_datasr__oe$next[1:0]$5947 $1\jtag_wb_datasr__oe$next[1:0]$5946
end
sync always
- update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5997
+ update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5945
end
- attribute \src "libresoc.v:140386.3-140406.6"
- process $proc$libresoc.v:140386$6000
+ attribute \src "libresoc.v:140050.3-140070.6"
+ process $proc$libresoc.v:140050$5948
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_reg$next[63:0]$6001 $3\jtag_wb_datasr_reg$next[63:0]$6004
- attribute \src "libresoc.v:140387.5-140387.29"
+ assign $0\jtag_wb_datasr_reg$next[63:0]$5949 $3\jtag_wb_datasr_reg$next[63:0]$5952
+ attribute \src "libresoc.v:140051.5-140051.29"
switch \initial
- attribute \src "libresoc.v:140387.9-140387.17"
+ attribute \src "libresoc.v:140051.9-140051.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_reg$next[63:0]$6002 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
+ assign $1\jtag_wb_datasr_reg$next[63:0]$5950 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
case
- assign $1\jtag_wb_datasr_reg$next[63:0]$6002 \jtag_wb_datasr_reg
+ assign $1\jtag_wb_datasr_reg$next[63:0]$5950 \jtag_wb_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \jtag_wb_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr_reg$next[63:0]$6003 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr_reg$next[63:0]$5951 \jtag_wb_datasr__i
case
- assign $2\jtag_wb_datasr_reg$next[63:0]$6003 $1\jtag_wb_datasr_reg$next[63:0]$6002
+ assign $2\jtag_wb_datasr_reg$next[63:0]$5951 $1\jtag_wb_datasr_reg$next[63:0]$5950
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr_reg$next[63:0]$6004 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr_reg$next[63:0]$5952 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr_reg$next[63:0]$6004 $2\jtag_wb_datasr_reg$next[63:0]$6003
+ assign $3\jtag_wb_datasr_reg$next[63:0]$5952 $2\jtag_wb_datasr_reg$next[63:0]$5951
end
sync always
- update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6001
+ update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5949
end
- attribute \src "libresoc.v:140407.3-140415.6"
- process $proc$libresoc.v:140407$6005
+ attribute \src "libresoc.v:140071.3-140079.6"
+ process $proc$libresoc.v:140071$5953
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core$next[0:0]$6006 $1\dmi0_addrsr_update_core$next[0:0]$6007
- attribute \src "libresoc.v:140408.5-140408.29"
+ assign $0\dmi0_addrsr_update_core$next[0:0]$5954 $1\dmi0_addrsr_update_core$next[0:0]$5955
+ attribute \src "libresoc.v:140072.5-140072.29"
switch \initial
- attribute \src "libresoc.v:140408.9-140408.17"
+ attribute \src "libresoc.v:140072.9-140072.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core$next[0:0]$6007 1'0
+ assign $1\dmi0_addrsr_update_core$next[0:0]$5955 1'0
case
- assign $1\dmi0_addrsr_update_core$next[0:0]$6007 \dmi0_addrsr_update
+ assign $1\dmi0_addrsr_update_core$next[0:0]$5955 \dmi0_addrsr_update
end
sync always
- update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6006
+ update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5954
end
- attribute \src "libresoc.v:140416.3-140424.6"
- process $proc$libresoc.v:140416$6008
+ attribute \src "libresoc.v:140080.3-140088.6"
+ process $proc$libresoc.v:140080$5956
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6009 $1\dmi0_addrsr_update_core_prev$next[0:0]$6010
- attribute \src "libresoc.v:140417.5-140417.29"
+ assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 $1\dmi0_addrsr_update_core_prev$next[0:0]$5958
+ attribute \src "libresoc.v:140081.5-140081.29"
switch \initial
- attribute \src "libresoc.v:140417.9-140417.17"
+ attribute \src "libresoc.v:140081.9-140081.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 1'0
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 1'0
case
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 \dmi0_addrsr_update_core
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 \dmi0_addrsr_update_core
end
sync always
- update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6009
+ update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5957
end
- attribute \src "libresoc.v:140425.3-140441.6"
- process $proc$libresoc.v:140425$6011
+ attribute \src "libresoc.v:140089.3-140105.6"
+ process $proc$libresoc.v:140089$5959
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr__oe$next[0:0]$6012 $2\dmi0_addrsr__oe$next[0:0]$6014
- attribute \src "libresoc.v:140426.5-140426.29"
+ assign $0\dmi0_addrsr__oe$next[0:0]$5960 $2\dmi0_addrsr__oe$next[0:0]$5962
+ attribute \src "libresoc.v:140090.5-140090.29"
switch \initial
- attribute \src "libresoc.v:140426.9-140426.17"
+ attribute \src "libresoc.v:140090.9-140090.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$6013 \dmi0_addrsr_isir
+ assign $1\dmi0_addrsr__oe$next[0:0]$5961 \dmi0_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$6013 1'0
+ assign $1\dmi0_addrsr__oe$next[0:0]$5961 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr__oe$next[0:0]$6014 1'0
+ assign $2\dmi0_addrsr__oe$next[0:0]$5962 1'0
case
- assign $2\dmi0_addrsr__oe$next[0:0]$6014 $1\dmi0_addrsr__oe$next[0:0]$6013
+ assign $2\dmi0_addrsr__oe$next[0:0]$5962 $1\dmi0_addrsr__oe$next[0:0]$5961
end
sync always
- update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6012
+ update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5960
end
- attribute \src "libresoc.v:140442.3-140462.6"
- process $proc$libresoc.v:140442$6015
+ attribute \src "libresoc.v:140106.3-140126.6"
+ process $proc$libresoc.v:140106$5963
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_reg$next[7:0]$6016 $3\dmi0_addrsr_reg$next[7:0]$6019
- attribute \src "libresoc.v:140443.5-140443.29"
+ assign $0\dmi0_addrsr_reg$next[7:0]$5964 $3\dmi0_addrsr_reg$next[7:0]$5967
+ attribute \src "libresoc.v:140107.5-140107.29"
switch \initial
- attribute \src "libresoc.v:140443.9-140443.17"
+ attribute \src "libresoc.v:140107.9-140107.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_reg$next[7:0]$6017 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
+ assign $1\dmi0_addrsr_reg$next[7:0]$5965 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
case
- assign $1\dmi0_addrsr_reg$next[7:0]$6017 \dmi0_addrsr_reg
+ assign $1\dmi0_addrsr_reg$next[7:0]$5965 \dmi0_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \dmi0_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr_reg$next[7:0]$6018 \dmi0_addrsr__i
+ assign $2\dmi0_addrsr_reg$next[7:0]$5966 \dmi0_addrsr__i
case
- assign $2\dmi0_addrsr_reg$next[7:0]$6018 $1\dmi0_addrsr_reg$next[7:0]$6017
+ assign $2\dmi0_addrsr_reg$next[7:0]$5966 $1\dmi0_addrsr_reg$next[7:0]$5965
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_addrsr_reg$next[7:0]$6019 8'00000000
+ assign $3\dmi0_addrsr_reg$next[7:0]$5967 8'00000000
case
- assign $3\dmi0_addrsr_reg$next[7:0]$6019 $2\dmi0_addrsr_reg$next[7:0]$6018
+ assign $3\dmi0_addrsr_reg$next[7:0]$5967 $2\dmi0_addrsr_reg$next[7:0]$5966
end
sync always
- update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6016
+ update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5964
end
- attribute \src "libresoc.v:140463.3-140471.6"
- process $proc$libresoc.v:140463$6020
+ attribute \src "libresoc.v:140127.3-140135.6"
+ process $proc$libresoc.v:140127$5968
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core$next[0:0]$6021 $1\dmi0_datasr_update_core$next[0:0]$6022
- attribute \src "libresoc.v:140464.5-140464.29"
+ assign $0\dmi0_datasr_update_core$next[0:0]$5969 $1\dmi0_datasr_update_core$next[0:0]$5970
+ attribute \src "libresoc.v:140128.5-140128.29"
switch \initial
- attribute \src "libresoc.v:140464.9-140464.17"
+ attribute \src "libresoc.v:140128.9-140128.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_update_core$next[0:0]$6022 1'0
+ assign $1\dmi0_datasr_update_core$next[0:0]$5970 1'0
case
- assign $1\dmi0_datasr_update_core$next[0:0]$6022 \dmi0_datasr_update
+ assign $1\dmi0_datasr_update_core$next[0:0]$5970 \dmi0_datasr_update
end
sync always
- update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6021
+ update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5969
end
- attribute \src "libresoc.v:140472.3-140480.6"
- process $proc$libresoc.v:140472$6023
+ attribute \src "libresoc.v:140136.3-140144.6"
+ process $proc$libresoc.v:140136$5971
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core_prev$next[0:0]$6024 $1\dmi0_datasr_update_core_prev$next[0:0]$6025
- attribute \src "libresoc.v:140473.5-140473.29"
+ assign $0\dmi0_datasr_update_core_prev$next[0:0]$5972 $1\dmi0_datasr_update_core_prev$next[0:0]$5973
+ attribute \src "libresoc.v:140137.5-140137.29"
switch \initial
- attribute \src "libresoc.v:140473.9-140473.17"
+ attribute \src "libresoc.v:140137.9-140137.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$6025 1'0
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 1'0
case
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$6025 \dmi0_datasr_update_core
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 \dmi0_datasr_update_core
end
sync always
- update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6024
+ update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5972
end
- attribute \src "libresoc.v:140481.3-140497.6"
- process $proc$libresoc.v:140481$6026
+ attribute \src "libresoc.v:140145.3-140161.6"
+ process $proc$libresoc.v:140145$5974
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__oe$next[1:0]$6027 $2\dmi0_datasr__oe$next[1:0]$6029
- attribute \src "libresoc.v:140482.5-140482.29"
+ assign $0\dmi0_datasr__oe$next[1:0]$5975 $2\dmi0_datasr__oe$next[1:0]$5977
+ attribute \src "libresoc.v:140146.5-140146.29"
switch \initial
- attribute \src "libresoc.v:140482.9-140482.17"
+ attribute \src "libresoc.v:140146.9-140146.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$6028 \dmi0_datasr_isir
+ assign $1\dmi0_datasr__oe$next[1:0]$5976 \dmi0_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$6028 2'00
+ assign $1\dmi0_datasr__oe$next[1:0]$5976 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__oe$next[1:0]$6029 2'00
+ assign $2\dmi0_datasr__oe$next[1:0]$5977 2'00
case
- assign $2\dmi0_datasr__oe$next[1:0]$6029 $1\dmi0_datasr__oe$next[1:0]$6028
+ assign $2\dmi0_datasr__oe$next[1:0]$5977 $1\dmi0_datasr__oe$next[1:0]$5976
end
sync always
- update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6027
+ update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5975
end
- attribute \src "libresoc.v:140498.3-140518.6"
- process $proc$libresoc.v:140498$6030
+ attribute \src "libresoc.v:140162.3-140182.6"
+ process $proc$libresoc.v:140162$5978
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_reg$next[63:0]$6031 $3\dmi0_datasr_reg$next[63:0]$6034
- attribute \src "libresoc.v:140499.5-140499.29"
+ assign $0\dmi0_datasr_reg$next[63:0]$5979 $3\dmi0_datasr_reg$next[63:0]$5982
+ attribute \src "libresoc.v:140163.5-140163.29"
switch \initial
- attribute \src "libresoc.v:140499.9-140499.17"
+ attribute \src "libresoc.v:140163.9-140163.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_reg$next[63:0]$6032 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
+ assign $1\dmi0_datasr_reg$next[63:0]$5980 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
case
- assign $1\dmi0_datasr_reg$next[63:0]$6032 \dmi0_datasr_reg
+ assign $1\dmi0_datasr_reg$next[63:0]$5980 \dmi0_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \dmi0_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr_reg$next[63:0]$6033 \dmi0_datasr__i
+ assign $2\dmi0_datasr_reg$next[63:0]$5981 \dmi0_datasr__i
case
- assign $2\dmi0_datasr_reg$next[63:0]$6033 $1\dmi0_datasr_reg$next[63:0]$6032
+ assign $2\dmi0_datasr_reg$next[63:0]$5981 $1\dmi0_datasr_reg$next[63:0]$5980
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr_reg$next[63:0]$6034 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr_reg$next[63:0]$5982 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr_reg$next[63:0]$6034 $2\dmi0_datasr_reg$next[63:0]$6033
+ assign $3\dmi0_datasr_reg$next[63:0]$5982 $2\dmi0_datasr_reg$next[63:0]$5981
end
sync always
- update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6031
+ update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5979
end
- attribute \src "libresoc.v:140519.3-140527.6"
- process $proc$libresoc.v:140519$6035
+ attribute \src "libresoc.v:140183.3-140191.6"
+ process $proc$libresoc.v:140183$5983
assign { } { }
assign { } { }
- assign $0\sr5_update_core$next[0:0]$6036 $1\sr5_update_core$next[0:0]$6037
- attribute \src "libresoc.v:140520.5-140520.29"
+ assign $0\sr5_update_core$next[0:0]$5984 $1\sr5_update_core$next[0:0]$5985
+ attribute \src "libresoc.v:140184.5-140184.29"
switch \initial
- attribute \src "libresoc.v:140520.9-140520.17"
+ attribute \src "libresoc.v:140184.9-140184.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_update_core$next[0:0]$6037 1'0
+ assign $1\sr5_update_core$next[0:0]$5985 1'0
case
- assign $1\sr5_update_core$next[0:0]$6037 \sr5_update
+ assign $1\sr5_update_core$next[0:0]$5985 \sr5_update
end
sync always
- update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6036
+ update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5984
end
- attribute \src "libresoc.v:140528.3-140536.6"
- process $proc$libresoc.v:140528$6038
+ attribute \src "libresoc.v:140192.3-140200.6"
+ process $proc$libresoc.v:140192$5986
assign { } { }
assign { } { }
- assign $0\sr5_update_core_prev$next[0:0]$6039 $1\sr5_update_core_prev$next[0:0]$6040
- attribute \src "libresoc.v:140529.5-140529.29"
+ assign $0\sr5_update_core_prev$next[0:0]$5987 $1\sr5_update_core_prev$next[0:0]$5988
+ attribute \src "libresoc.v:140193.5-140193.29"
switch \initial
- attribute \src "libresoc.v:140529.9-140529.17"
+ attribute \src "libresoc.v:140193.9-140193.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_update_core_prev$next[0:0]$6040 1'0
+ assign $1\sr5_update_core_prev$next[0:0]$5988 1'0
case
- assign $1\sr5_update_core_prev$next[0:0]$6040 \sr5_update_core
+ assign $1\sr5_update_core_prev$next[0:0]$5988 \sr5_update_core
end
sync always
- update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6039
+ update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5987
end
- attribute \src "libresoc.v:140537.3-140553.6"
- process $proc$libresoc.v:140537$6041
+ attribute \src "libresoc.v:140201.3-140217.6"
+ process $proc$libresoc.v:140201$5989
assign { } { }
assign { } { }
- assign $0\sr5__oe$next[0:0]$6042 $2\sr5__oe$next[0:0]$6044
- attribute \src "libresoc.v:140538.5-140538.29"
+ assign $0\sr5__oe$next[0:0]$5990 $2\sr5__oe$next[0:0]$5992
+ attribute \src "libresoc.v:140202.5-140202.29"
switch \initial
- attribute \src "libresoc.v:140538.9-140538.17"
+ attribute \src "libresoc.v:140202.9-140202.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5__oe$next[0:0]$6043 \sr5_isir
+ assign $1\sr5__oe$next[0:0]$5991 \sr5_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\sr5__oe$next[0:0]$6043 1'0
+ assign $1\sr5__oe$next[0:0]$5991 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr5__oe$next[0:0]$6044 1'0
+ assign $2\sr5__oe$next[0:0]$5992 1'0
case
- assign $2\sr5__oe$next[0:0]$6044 $1\sr5__oe$next[0:0]$6043
+ assign $2\sr5__oe$next[0:0]$5992 $1\sr5__oe$next[0:0]$5991
end
sync always
- update \sr5__oe$next $0\sr5__oe$next[0:0]$6042
+ update \sr5__oe$next $0\sr5__oe$next[0:0]$5990
end
- attribute \src "libresoc.v:140554.3-140574.6"
- process $proc$libresoc.v:140554$6045
+ attribute \src "libresoc.v:140218.3-140238.6"
+ process $proc$libresoc.v:140218$5993
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr5_reg$next[2:0]$6046 $3\sr5_reg$next[2:0]$6049
- attribute \src "libresoc.v:140555.5-140555.29"
+ assign $0\sr5_reg$next[2:0]$5994 $3\sr5_reg$next[2:0]$5997
+ attribute \src "libresoc.v:140219.5-140219.29"
switch \initial
- attribute \src "libresoc.v:140555.9-140555.17"
+ attribute \src "libresoc.v:140219.9-140219.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_reg$next[2:0]$6047 { \TAP_bus__tdi \sr5_reg [2:1] }
+ assign $1\sr5_reg$next[2:0]$5995 { \TAP_bus__tdi \sr5_reg [2:1] }
case
- assign $1\sr5_reg$next[2:0]$6047 \sr5_reg
+ assign $1\sr5_reg$next[2:0]$5995 \sr5_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \sr5_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr5_reg$next[2:0]$6048 \sr5__i
+ assign $2\sr5_reg$next[2:0]$5996 \sr5__i
case
- assign $2\sr5_reg$next[2:0]$6048 $1\sr5_reg$next[2:0]$6047
+ assign $2\sr5_reg$next[2:0]$5996 $1\sr5_reg$next[2:0]$5995
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sr5_reg$next[2:0]$6049 3'000
+ assign $3\sr5_reg$next[2:0]$5997 3'000
case
- assign $3\sr5_reg$next[2:0]$6049 $2\sr5_reg$next[2:0]$6048
+ assign $3\sr5_reg$next[2:0]$5997 $2\sr5_reg$next[2:0]$5996
end
sync always
- update \sr5_reg$next $0\sr5_reg$next[2:0]$6046
+ update \sr5_reg$next $0\sr5_reg$next[2:0]$5994
end
- attribute \src "libresoc.v:140575.3-140601.6"
- process $proc$libresoc.v:140575$6050
+ attribute \src "libresoc.v:140239.3-140265.6"
+ process $proc$libresoc.v:140239$5998
assign { } { }
assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:140576.5-140576.29"
+ attribute \src "libresoc.v:140240.5-140240.29"
switch \initial
- attribute \src "libresoc.v:140576.9-140576.17"
+ attribute \src "libresoc.v:140240.9-140240.17"
case 1'1
case
end
sync always
update \TAP_bus__tdo $0\TAP_bus__tdo[0:0]
end
- attribute \src "libresoc.v:140602.3-140646.6"
- process $proc$libresoc.v:140602$6051
+ attribute \src "libresoc.v:140266.3-140310.6"
+ process $proc$libresoc.v:140266$5999
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__adr$next[28:0]$6052 $4\jtag_wb__adr$next[28:0]$6056
- attribute \src "libresoc.v:140603.5-140603.29"
+ assign $0\jtag_wb__adr$next[28:0]$6000 $4\jtag_wb__adr$next[28:0]$6004
+ attribute \src "libresoc.v:140267.5-140267.29"
switch \initial
- attribute \src "libresoc.v:140603.9-140603.17"
+ attribute \src "libresoc.v:140267.9-140267.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$6053 $2\jtag_wb__adr$next[28:0]$6054
+ assign $1\jtag_wb__adr$next[28:0]$6001 $2\jtag_wb__adr$next[28:0]$6002
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$6054 \jtag_wb_addrsr__o
+ assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb_addrsr__o
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$6054 \$447 [28:0]
+ assign $2\jtag_wb__adr$next[28:0]$6002 \$447 [28:0]
case
- assign $2\jtag_wb__adr$next[28:0]$6054 \jtag_wb__adr
+ assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb__adr
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$6053 $3\jtag_wb__adr$next[28:0]$6055
+ assign $1\jtag_wb__adr$next[28:0]$6001 $3\jtag_wb__adr$next[28:0]$6003
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__adr$next[28:0]$6055 \$450 [28:0]
+ assign $3\jtag_wb__adr$next[28:0]$6003 \$450 [28:0]
case
- assign $3\jtag_wb__adr$next[28:0]$6055 \jtag_wb__adr
+ assign $3\jtag_wb__adr$next[28:0]$6003 \jtag_wb__adr
end
case
- assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\jtag_wb__adr$next[28:0]$6056 29'00000000000000000000000000000
+ assign $4\jtag_wb__adr$next[28:0]$6004 29'00000000000000000000000000000
case
- assign $4\jtag_wb__adr$next[28:0]$6056 $1\jtag_wb__adr$next[28:0]$6053
+ assign $4\jtag_wb__adr$next[28:0]$6004 $1\jtag_wb__adr$next[28:0]$6001
end
sync always
- update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6052
+ update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6000
end
- attribute \src "libresoc.v:140647.3-140699.6"
- process $proc$libresoc.v:140647$6057
+ attribute \src "libresoc.v:140311.3-140363.6"
+ process $proc$libresoc.v:140311$6005
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[2:0]$6058 $5\fsm_state$next[2:0]$6063
- attribute \src "libresoc.v:140648.5-140648.29"
+ assign $0\fsm_state$next[2:0]$6006 $5\fsm_state$next[2:0]$6011
+ attribute \src "libresoc.v:140312.5-140312.29"
switch \initial
- attribute \src "libresoc.v:140648.9-140648.17"
+ attribute \src "libresoc.v:140312.9-140312.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$next[2:0]$6059 $2\fsm_state$next[2:0]$6060
+ assign $1\fsm_state$next[2:0]$6007 $2\fsm_state$next[2:0]$6008
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$next[2:0]$6060 3'001
+ assign $2\fsm_state$next[2:0]$6008 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$next[2:0]$6060 3'001
+ assign $2\fsm_state$next[2:0]$6008 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$next[2:0]$6060 3'010
+ assign $2\fsm_state$next[2:0]$6008 3'010
case
- assign $2\fsm_state$next[2:0]$6060 \fsm_state
+ assign $2\fsm_state$next[2:0]$6008 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$next[2:0]$6059 3'011
+ assign $1\fsm_state$next[2:0]$6007 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$next[2:0]$6059 $3\fsm_state$next[2:0]$6061
+ assign $1\fsm_state$next[2:0]$6007 $3\fsm_state$next[2:0]$6009
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$next[2:0]$6061 3'000
+ assign $3\fsm_state$next[2:0]$6009 3'000
case
- assign $3\fsm_state$next[2:0]$6061 \fsm_state
+ assign $3\fsm_state$next[2:0]$6009 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$next[2:0]$6059 3'100
+ assign $1\fsm_state$next[2:0]$6007 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$next[2:0]$6059 $4\fsm_state$next[2:0]$6062
+ assign $1\fsm_state$next[2:0]$6007 $4\fsm_state$next[2:0]$6010
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[2:0]$6062 3'001
+ assign $4\fsm_state$next[2:0]$6010 3'001
case
- assign $4\fsm_state$next[2:0]$6062 \fsm_state
+ assign $4\fsm_state$next[2:0]$6010 \fsm_state
end
case
- assign $1\fsm_state$next[2:0]$6059 \fsm_state
+ assign $1\fsm_state$next[2:0]$6007 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[2:0]$6063 3'000
+ assign $5\fsm_state$next[2:0]$6011 3'000
case
- assign $5\fsm_state$next[2:0]$6063 $1\fsm_state$next[2:0]$6059
+ assign $5\fsm_state$next[2:0]$6011 $1\fsm_state$next[2:0]$6007
end
sync always
- update \fsm_state$next $0\fsm_state$next[2:0]$6058
+ update \fsm_state$next $0\fsm_state$next[2:0]$6006
end
- attribute \src "libresoc.v:140700.3-140726.6"
- process $proc$libresoc.v:140700$6064
+ attribute \src "libresoc.v:140364.3-140390.6"
+ process $proc$libresoc.v:140364$6012
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__dat_w$next[63:0]$6065 $3\jtag_wb__dat_w$next[63:0]$6068
- attribute \src "libresoc.v:140701.5-140701.29"
+ assign $0\jtag_wb__dat_w$next[63:0]$6013 $3\jtag_wb__dat_w$next[63:0]$6016
+ attribute \src "libresoc.v:140365.5-140365.29"
switch \initial
- attribute \src "libresoc.v:140701.9-140701.17"
+ attribute \src "libresoc.v:140365.9-140365.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__dat_w$next[63:0]$6066 $2\jtag_wb__dat_w$next[63:0]$6067
+ assign $1\jtag_wb__dat_w$next[63:0]$6014 $2\jtag_wb__dat_w$next[63:0]$6015
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb_datasr__o
+ assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb_datasr__o
case
- assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w
end
case
- assign $1\jtag_wb__dat_w$next[63:0]$6066 \jtag_wb__dat_w
+ assign $1\jtag_wb__dat_w$next[63:0]$6014 \jtag_wb__dat_w
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__dat_w$next[63:0]$6068 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb__dat_w$next[63:0]$6016 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb__dat_w$next[63:0]$6068 $1\jtag_wb__dat_w$next[63:0]$6066
+ assign $3\jtag_wb__dat_w$next[63:0]$6016 $1\jtag_wb__dat_w$next[63:0]$6014
end
sync always
- update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6065
+ update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6013
end
- attribute \src "libresoc.v:140727.3-140755.6"
- process $proc$libresoc.v:140727$6069
+ attribute \src "libresoc.v:140391.3-140419.6"
+ process $proc$libresoc.v:140391$6017
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__i$next[63:0]$6070 $3\jtag_wb_datasr__i$next[63:0]$6073
- attribute \src "libresoc.v:140728.5-140728.29"
+ assign $0\jtag_wb_datasr__i$next[63:0]$6018 $3\jtag_wb_datasr__i$next[63:0]$6021
+ attribute \src "libresoc.v:140392.5-140392.29"
switch \initial
- attribute \src "libresoc.v:140728.9-140728.17"
+ attribute \src "libresoc.v:140392.9-140392.17"
case 1'1
case
end
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i
+ assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i
+ assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\jtag_wb_datasr__i$next[63:0]$6071 $2\jtag_wb_datasr__i$next[63:0]$6072
+ assign $1\jtag_wb_datasr__i$next[63:0]$6019 $2\jtag_wb_datasr__i$next[63:0]$6020
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__i$next[63:0]$6072 \jtag_wb__dat_r
+ assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb__dat_r
case
- assign $2\jtag_wb_datasr__i$next[63:0]$6072 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb_datasr__i
end
case
- assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i
+ assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr__i$next[63:0]$6073 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr__i$next[63:0]$6021 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr__i$next[63:0]$6073 $1\jtag_wb_datasr__i$next[63:0]$6071
+ assign $3\jtag_wb_datasr__i$next[63:0]$6021 $1\jtag_wb_datasr__i$next[63:0]$6019
end
sync always
- update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6070
+ update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6018
end
- attribute \src "libresoc.v:140756.3-140800.6"
- process $proc$libresoc.v:140756$6074
+ attribute \src "libresoc.v:140420.3-140464.6"
+ process $proc$libresoc.v:140420$6022
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0__addr_i$next[3:0]$6075 $4\dmi0__addr_i$next[3:0]$6079
- attribute \src "libresoc.v:140757.5-140757.29"
+ assign $0\dmi0__addr_i$next[3:0]$6023 $4\dmi0__addr_i$next[3:0]$6027
+ attribute \src "libresoc.v:140421.5-140421.29"
switch \initial
- attribute \src "libresoc.v:140757.9-140757.17"
+ attribute \src "libresoc.v:140421.9-140421.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0__addr_i$next[3:0]$6076 $2\dmi0__addr_i$next[3:0]$6077
+ assign $1\dmi0__addr_i$next[3:0]$6024 $2\dmi0__addr_i$next[3:0]$6025
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\dmi0__addr_i$next[3:0]$6077 \dmi0_addrsr__o [3:0]
+ assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0_addrsr__o [3:0]
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\dmi0__addr_i$next[3:0]$6077 \$464 [3:0]
+ assign $2\dmi0__addr_i$next[3:0]$6025 \$464 [3:0]
case
- assign $2\dmi0__addr_i$next[3:0]$6077 \dmi0__addr_i
+ assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0__addr_i
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i
+ assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i
+ assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i
+ assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\dmi0__addr_i$next[3:0]$6076 $3\dmi0__addr_i$next[3:0]$6078
+ assign $1\dmi0__addr_i$next[3:0]$6024 $3\dmi0__addr_i$next[3:0]$6026
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0__addr_i$next[3:0]$6078 \$467 [3:0]
+ assign $3\dmi0__addr_i$next[3:0]$6026 \$467 [3:0]
case
- assign $3\dmi0__addr_i$next[3:0]$6078 \dmi0__addr_i
+ assign $3\dmi0__addr_i$next[3:0]$6026 \dmi0__addr_i
end
case
- assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i
+ assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dmi0__addr_i$next[3:0]$6079 4'0000
+ assign $4\dmi0__addr_i$next[3:0]$6027 4'0000
case
- assign $4\dmi0__addr_i$next[3:0]$6079 $1\dmi0__addr_i$next[3:0]$6076
+ assign $4\dmi0__addr_i$next[3:0]$6027 $1\dmi0__addr_i$next[3:0]$6024
end
sync always
- update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6075
+ update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6023
end
- attribute \src "libresoc.v:140801.3-140853.6"
- process $proc$libresoc.v:140801$6080
+ attribute \src "libresoc.v:140465.3-140517.6"
+ process $proc$libresoc.v:140465$6028
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$455$next[2:0]$6081 $5\fsm_state$455$next[2:0]$6086
- attribute \src "libresoc.v:140802.5-140802.29"
+ assign $0\fsm_state$455$next[2:0]$6029 $5\fsm_state$455$next[2:0]$6034
+ attribute \src "libresoc.v:140466.5-140466.29"
switch \initial
- attribute \src "libresoc.v:140802.9-140802.17"
+ attribute \src "libresoc.v:140466.9-140466.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$455$next[2:0]$6082 $2\fsm_state$455$next[2:0]$6083
+ assign $1\fsm_state$455$next[2:0]$6030 $2\fsm_state$455$next[2:0]$6031
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$455$next[2:0]$6083 3'001
+ assign $2\fsm_state$455$next[2:0]$6031 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$455$next[2:0]$6083 3'001
+ assign $2\fsm_state$455$next[2:0]$6031 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$455$next[2:0]$6083 3'010
+ assign $2\fsm_state$455$next[2:0]$6031 3'010
case
- assign $2\fsm_state$455$next[2:0]$6083 \fsm_state$455
+ assign $2\fsm_state$455$next[2:0]$6031 \fsm_state$455
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$455$next[2:0]$6082 3'011
+ assign $1\fsm_state$455$next[2:0]$6030 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$455$next[2:0]$6082 $3\fsm_state$455$next[2:0]$6084
+ assign $1\fsm_state$455$next[2:0]$6030 $3\fsm_state$455$next[2:0]$6032
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$455$next[2:0]$6084 3'000
+ assign $3\fsm_state$455$next[2:0]$6032 3'000
case
- assign $3\fsm_state$455$next[2:0]$6084 \fsm_state$455
+ assign $3\fsm_state$455$next[2:0]$6032 \fsm_state$455
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$455$next[2:0]$6082 3'100
+ assign $1\fsm_state$455$next[2:0]$6030 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$455$next[2:0]$6082 $4\fsm_state$455$next[2:0]$6085
+ assign $1\fsm_state$455$next[2:0]$6030 $4\fsm_state$455$next[2:0]$6033
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$455$next[2:0]$6085 3'001
+ assign $4\fsm_state$455$next[2:0]$6033 3'001
case
- assign $4\fsm_state$455$next[2:0]$6085 \fsm_state$455
+ assign $4\fsm_state$455$next[2:0]$6033 \fsm_state$455
end
case
- assign $1\fsm_state$455$next[2:0]$6082 \fsm_state$455
+ assign $1\fsm_state$455$next[2:0]$6030 \fsm_state$455
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$455$next[2:0]$6086 3'000
+ assign $5\fsm_state$455$next[2:0]$6034 3'000
case
- assign $5\fsm_state$455$next[2:0]$6086 $1\fsm_state$455$next[2:0]$6082
+ assign $5\fsm_state$455$next[2:0]$6034 $1\fsm_state$455$next[2:0]$6030
end
sync always
- update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6081
+ update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6029
end
- attribute \src "libresoc.v:140854.3-140880.6"
- process $proc$libresoc.v:140854$6087
+ attribute \src "libresoc.v:140518.3-140544.6"
+ process $proc$libresoc.v:140518$6035
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0__din$next[63:0]$6088 $3\dmi0__din$next[63:0]$6091
- attribute \src "libresoc.v:140855.5-140855.29"
+ assign $0\dmi0__din$next[63:0]$6036 $3\dmi0__din$next[63:0]$6039
+ attribute \src "libresoc.v:140519.5-140519.29"
switch \initial
- attribute \src "libresoc.v:140855.9-140855.17"
+ attribute \src "libresoc.v:140519.9-140519.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0__din$next[63:0]$6089 $2\dmi0__din$next[63:0]$6090
+ assign $1\dmi0__din$next[63:0]$6037 $2\dmi0__din$next[63:0]$6038
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\dmi0__din$next[63:0]$6090 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6038 \dmi0__din
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\dmi0__din$next[63:0]$6090 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6038 \dmi0__din
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\dmi0__din$next[63:0]$6090 \dmi0_datasr__o
+ assign $2\dmi0__din$next[63:0]$6038 \dmi0_datasr__o
case
- assign $2\dmi0__din$next[63:0]$6090 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6038 \dmi0__din
end
case
- assign $1\dmi0__din$next[63:0]$6089 \dmi0__din
+ assign $1\dmi0__din$next[63:0]$6037 \dmi0__din
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0__din$next[63:0]$6091 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0__din$next[63:0]$6039 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0__din$next[63:0]$6091 $1\dmi0__din$next[63:0]$6089
+ assign $3\dmi0__din$next[63:0]$6039 $1\dmi0__din$next[63:0]$6037
end
sync always
- update \dmi0__din$next $0\dmi0__din$next[63:0]$6088
+ update \dmi0__din$next $0\dmi0__din$next[63:0]$6036
end
- attribute \src "libresoc.v:140881.3-140909.6"
- process $proc$libresoc.v:140881$6092
+ attribute \src "libresoc.v:140545.3-140573.6"
+ process $proc$libresoc.v:140545$6040
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__i$next[63:0]$6093 $3\dmi0_datasr__i$next[63:0]$6096
- attribute \src "libresoc.v:140882.5-140882.29"
+ assign $0\dmi0_datasr__i$next[63:0]$6041 $3\dmi0_datasr__i$next[63:0]$6044
+ attribute \src "libresoc.v:140546.5-140546.29"
switch \initial
- attribute \src "libresoc.v:140882.9-140882.17"
+ attribute \src "libresoc.v:140546.9-140546.17"
case 1'1
case
end
switch \fsm_state$455
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i
+ assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i
+ assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\dmi0_datasr__i$next[63:0]$6094 $2\dmi0_datasr__i$next[63:0]$6095
+ assign $1\dmi0_datasr__i$next[63:0]$6042 $2\dmi0_datasr__i$next[63:0]$6043
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__i$next[63:0]$6095 \dmi0__dout
+ assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0__dout
case
- assign $2\dmi0_datasr__i$next[63:0]$6095 \dmi0_datasr__i
+ assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0_datasr__i
end
case
- assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i
+ assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr__i$next[63:0]$6096 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr__i$next[63:0]$6044 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr__i$next[63:0]$6096 $1\dmi0_datasr__i$next[63:0]$6094
+ assign $3\dmi0_datasr__i$next[63:0]$6044 $1\dmi0_datasr__i$next[63:0]$6042
end
sync always
- update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6093
+ update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6041
end
- attribute \src "libresoc.v:140910.3-140930.6"
- process $proc$libresoc.v:140910$6097
+ attribute \src "libresoc.v:140574.3-140594.6"
+ process $proc$libresoc.v:140574$6045
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\wb_dcache_en$next[0:0]$6098 $2\wb_dcache_en$next[0:0]$6104
- assign $0\wb_icache_en$next[0:0]$6099 $2\wb_icache_en$next[0:0]$6105
- assign $0\wb_sram_en$next[0:0]$6100 $2\wb_sram_en$next[0:0]$6106
- attribute \src "libresoc.v:140911.5-140911.29"
+ assign $0\wb_dcache_en$next[0:0]$6046 $2\wb_dcache_en$next[0:0]$6052
+ assign $0\wb_icache_en$next[0:0]$6047 $2\wb_icache_en$next[0:0]$6053
+ assign $0\wb_sram_en$next[0:0]$6048 $2\wb_sram_en$next[0:0]$6054
+ attribute \src "libresoc.v:140575.5-140575.29"
switch \initial
- attribute \src "libresoc.v:140911.9-140911.17"
+ attribute \src "libresoc.v:140575.9-140575.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\wb_sram_en$next[0:0]$6103 $1\wb_dcache_en$next[0:0]$6101 $1\wb_icache_en$next[0:0]$6102 } \sr5__o
+ assign { $1\wb_sram_en$next[0:0]$6051 $1\wb_dcache_en$next[0:0]$6049 $1\wb_icache_en$next[0:0]$6050 } \sr5__o
case
- assign $1\wb_dcache_en$next[0:0]$6101 \wb_dcache_en
- assign $1\wb_icache_en$next[0:0]$6102 \wb_icache_en
- assign $1\wb_sram_en$next[0:0]$6103 \wb_sram_en
+ assign $1\wb_dcache_en$next[0:0]$6049 \wb_dcache_en
+ assign $1\wb_icache_en$next[0:0]$6050 \wb_icache_en
+ assign $1\wb_sram_en$next[0:0]$6051 \wb_sram_en
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\wb_icache_en$next[0:0]$6105 1'1
- assign $2\wb_dcache_en$next[0:0]$6104 1'1
- assign $2\wb_sram_en$next[0:0]$6106 1'1
+ assign $2\wb_icache_en$next[0:0]$6053 1'1
+ assign $2\wb_dcache_en$next[0:0]$6052 1'1
+ assign $2\wb_sram_en$next[0:0]$6054 1'1
case
- assign $2\wb_dcache_en$next[0:0]$6104 $1\wb_dcache_en$next[0:0]$6101
- assign $2\wb_icache_en$next[0:0]$6105 $1\wb_icache_en$next[0:0]$6102
- assign $2\wb_sram_en$next[0:0]$6106 $1\wb_sram_en$next[0:0]$6103
+ assign $2\wb_dcache_en$next[0:0]$6052 $1\wb_dcache_en$next[0:0]$6049
+ assign $2\wb_icache_en$next[0:0]$6053 $1\wb_icache_en$next[0:0]$6050
+ assign $2\wb_sram_en$next[0:0]$6054 $1\wb_sram_en$next[0:0]$6051
end
sync always
- update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6098
- update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6099
- update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6100
+ update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6046
+ update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6047
+ update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6048
end
- attribute \src "libresoc.v:140931.3-140940.6"
- process $proc$libresoc.v:140931$6107
+ attribute \src "libresoc.v:140595.3-140604.6"
+ process $proc$libresoc.v:140595$6055
assign { } { }
assign { } { }
assign $0\sr5__i[2:0] $1\sr5__i[2:0]
- attribute \src "libresoc.v:140932.5-140932.29"
+ attribute \src "libresoc.v:140596.5-140596.29"
switch \initial
- attribute \src "libresoc.v:140932.9-140932.17"
+ attribute \src "libresoc.v:140596.9-140596.17"
case 1'1
case
end
sync always
update \sr5__i $0\sr5__i[2:0]
end
- attribute \src "libresoc.v:140941.3-140958.6"
- process $proc$libresoc.v:140941$6108
+ attribute \src "libresoc.v:140605.3-140622.6"
+ process $proc$libresoc.v:140605$6056
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_sr$next[129:0]$6109 $2\io_sr$next[129:0]$6111
- attribute \src "libresoc.v:140942.5-140942.29"
+ assign $0\io_sr$next[129:0]$6057 $2\io_sr$next[129:0]$6059
+ attribute \src "libresoc.v:140606.5-140606.29"
switch \initial
- attribute \src "libresoc.v:140942.9-140942.17"
+ attribute \src "libresoc.v:140606.9-140606.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $1\io_sr$next[129:0]$6110 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i }
+ assign $1\io_sr$next[129:0]$6058 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i }
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $1\io_sr$next[129:0]$6110 { \io_sr [128:0] \TAP_bus__tdi }
+ assign $1\io_sr$next[129:0]$6058 { \io_sr [128:0] \TAP_bus__tdi }
case
- assign $1\io_sr$next[129:0]$6110 \io_sr
+ assign $1\io_sr$next[129:0]$6058 \io_sr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_sr$next[129:0]$6111 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $2\io_sr$next[129:0]$6059 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\io_sr$next[129:0]$6111 $1\io_sr$next[129:0]$6110
+ assign $2\io_sr$next[129:0]$6059 $1\io_sr$next[129:0]$6058
end
sync always
- update \io_sr$next $0\io_sr$next[129:0]$6109
+ update \io_sr$next $0\io_sr$next[129:0]$6057
end
- attribute \src "libresoc.v:140959.3-140979.6"
- process $proc$libresoc.v:140959$6112
+ attribute \src "libresoc.v:140623.3-140643.6"
+ process $proc$libresoc.v:140623$6060
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_bd$next[129:0]$6113 $2\io_bd$next[129:0]$6115
- attribute \src "libresoc.v:140960.5-140960.29"
+ assign $0\io_bd$next[129:0]$6061 $2\io_bd$next[129:0]$6063
+ attribute \src "libresoc.v:140624.5-140624.29"
switch \initial
- attribute \src "libresoc.v:140960.9-140960.17"
+ attribute \src "libresoc.v:140624.9-140624.17"
case 1'1
case
end
switch { \io_update \io_shift \io_capture }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $1\io_bd$next[129:0]$6114 \io_bd
+ assign $1\io_bd$next[129:0]$6062 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $1\io_bd$next[129:0]$6114 \io_bd
+ assign $1\io_bd$next[129:0]$6062 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $1\io_bd$next[129:0]$6114 \io_sr
+ assign $1\io_bd$next[129:0]$6062 \io_sr
case
- assign $1\io_bd$next[129:0]$6114 \io_bd
+ assign $1\io_bd$next[129:0]$6062 \io_bd
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \negjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_bd$next[129:0]$6115 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- case
- assign $2\io_bd$next[129:0]$6115 $1\io_bd$next[129:0]$6114
- end
- sync always
- update \io_bd$next $0\io_bd$next[129:0]$6113
- end
- connect \$9 $eq$libresoc.v:139882$5688_Y
- connect \$99 $ternary$libresoc.v:139883$5689_Y
- connect \$101 $ternary$libresoc.v:139884$5690_Y
- connect \$103 $ternary$libresoc.v:139885$5691_Y
- connect \$105 $ternary$libresoc.v:139886$5692_Y
- connect \$107 $ternary$libresoc.v:139887$5693_Y
- connect \$109 $ternary$libresoc.v:139888$5694_Y
- connect \$111 $ternary$libresoc.v:139889$5695_Y
- connect \$113 $ternary$libresoc.v:139890$5696_Y
- connect \$115 $ternary$libresoc.v:139891$5697_Y
- connect \$117 $ternary$libresoc.v:139892$5698_Y
- connect \$11 $eq$libresoc.v:139893$5699_Y
- connect \$119 $ternary$libresoc.v:139894$5700_Y
- connect \$121 $ternary$libresoc.v:139895$5701_Y
- connect \$123 $ternary$libresoc.v:139896$5702_Y
- connect \$125 $ternary$libresoc.v:139897$5703_Y
- connect \$127 $ternary$libresoc.v:139898$5704_Y
- connect \$129 $ternary$libresoc.v:139899$5705_Y
- connect \$131 $ternary$libresoc.v:139900$5706_Y
- connect \$133 $ternary$libresoc.v:139901$5707_Y
- connect \$135 $ternary$libresoc.v:139902$5708_Y
- connect \$137 $ternary$libresoc.v:139903$5709_Y
- connect \$13 $eq$libresoc.v:139904$5710_Y
- connect \$139 $ternary$libresoc.v:139905$5711_Y
- connect \$141 $ternary$libresoc.v:139906$5712_Y
- connect \$143 $ternary$libresoc.v:139907$5713_Y
- connect \$145 $ternary$libresoc.v:139908$5714_Y
- connect \$147 $ternary$libresoc.v:139909$5715_Y
- connect \$149 $ternary$libresoc.v:139910$5716_Y
- connect \$151 $ternary$libresoc.v:139911$5717_Y
- connect \$153 $ternary$libresoc.v:139912$5718_Y
- connect \$155 $ternary$libresoc.v:139913$5719_Y
- connect \$157 $ternary$libresoc.v:139914$5720_Y
- connect \$15 $or$libresoc.v:139915$5721_Y
- connect \$159 $ternary$libresoc.v:139916$5722_Y
- connect \$161 $ternary$libresoc.v:139917$5723_Y
- connect \$163 $ternary$libresoc.v:139918$5724_Y
- connect \$165 $ternary$libresoc.v:139919$5725_Y
- connect \$167 $ternary$libresoc.v:139920$5726_Y
- connect \$169 $ternary$libresoc.v:139921$5727_Y
- connect \$171 $ternary$libresoc.v:139922$5728_Y
- connect \$173 $ternary$libresoc.v:139923$5729_Y
- connect \$175 $ternary$libresoc.v:139924$5730_Y
- connect \$177 $ternary$libresoc.v:139925$5731_Y
- connect \$17 $and$libresoc.v:139926$5732_Y
- connect \$179 $ternary$libresoc.v:139927$5733_Y
- connect \$181 $ternary$libresoc.v:139928$5734_Y
- connect \$183 $ternary$libresoc.v:139929$5735_Y
- connect \$185 $ternary$libresoc.v:139930$5736_Y
- connect \$187 $ternary$libresoc.v:139931$5737_Y
- connect \$189 $ternary$libresoc.v:139932$5738_Y
- connect \$191 $ternary$libresoc.v:139933$5739_Y
- connect \$193 $ternary$libresoc.v:139934$5740_Y
- connect \$195 $ternary$libresoc.v:139935$5741_Y
- connect \$197 $ternary$libresoc.v:139936$5742_Y
- connect \$1 $eq$libresoc.v:139937$5743_Y
- connect \$19 $eq$libresoc.v:139938$5744_Y
- connect \$199 $ternary$libresoc.v:139939$5745_Y
- connect \$201 $ternary$libresoc.v:139940$5746_Y
- connect \$203 $ternary$libresoc.v:139941$5747_Y
- connect \$205 $ternary$libresoc.v:139942$5748_Y
- connect \$207 $ternary$libresoc.v:139943$5749_Y
- connect \$209 $ternary$libresoc.v:139944$5750_Y
- connect \$211 $ternary$libresoc.v:139945$5751_Y
- connect \$213 $ternary$libresoc.v:139946$5752_Y
- connect \$215 $ternary$libresoc.v:139947$5753_Y
- connect \$217 $ternary$libresoc.v:139948$5754_Y
- connect \$21 $eq$libresoc.v:139949$5755_Y
- connect \$219 $ternary$libresoc.v:139950$5756_Y
- connect \$221 $ternary$libresoc.v:139951$5757_Y
- connect \$223 $ternary$libresoc.v:139952$5758_Y
- connect \$225 $ternary$libresoc.v:139953$5759_Y
- connect \$227 $ternary$libresoc.v:139954$5760_Y
- connect \$229 $ternary$libresoc.v:139955$5761_Y
- connect \$231 $ternary$libresoc.v:139956$5762_Y
- connect \$233 $ternary$libresoc.v:139957$5763_Y
- connect \$235 $ternary$libresoc.v:139958$5764_Y
- connect \$237 $ternary$libresoc.v:139959$5765_Y
- connect \$23 $or$libresoc.v:139960$5766_Y
- connect \$239 $ternary$libresoc.v:139961$5767_Y
- connect \$241 $ternary$libresoc.v:139962$5768_Y
- connect \$243 $ternary$libresoc.v:139963$5769_Y
- connect \$245 $ternary$libresoc.v:139964$5770_Y
- connect \$247 $ternary$libresoc.v:139965$5771_Y
- connect \$249 $ternary$libresoc.v:139966$5772_Y
- connect \$251 $ternary$libresoc.v:139967$5773_Y
- connect \$253 $ternary$libresoc.v:139968$5774_Y
- connect \$255 $ternary$libresoc.v:139969$5775_Y
- connect \$257 $ternary$libresoc.v:139970$5776_Y
- connect \$25 $eq$libresoc.v:139971$5777_Y
- connect \$259 $ternary$libresoc.v:139972$5778_Y
- connect \$261 $ternary$libresoc.v:139973$5779_Y
- connect \$263 $ternary$libresoc.v:139974$5780_Y
- connect \$265 $ternary$libresoc.v:139975$5781_Y
- connect \$267 $ternary$libresoc.v:139976$5782_Y
- connect \$269 $ternary$libresoc.v:139977$5783_Y
- connect \$271 $ternary$libresoc.v:139978$5784_Y
- connect \$273 $ternary$libresoc.v:139979$5785_Y
- connect \$275 $ternary$libresoc.v:139980$5786_Y
- connect \$277 $ternary$libresoc.v:139981$5787_Y
- connect \$27 $or$libresoc.v:139982$5788_Y
- connect \$279 $ternary$libresoc.v:139983$5789_Y
- connect \$281 $ternary$libresoc.v:139984$5790_Y
- connect \$283 $ternary$libresoc.v:139985$5791_Y
- connect \$285 $ternary$libresoc.v:139986$5792_Y
- connect \$287 $ternary$libresoc.v:139987$5793_Y
- connect \$289 $ternary$libresoc.v:139988$5794_Y
- connect \$291 $ternary$libresoc.v:139989$5795_Y
- connect \$293 $ternary$libresoc.v:139990$5796_Y
- connect \$295 $ternary$libresoc.v:139991$5797_Y
- connect \$297 $ternary$libresoc.v:139992$5798_Y
- connect \$29 $and$libresoc.v:139993$5799_Y
- connect \$299 $ternary$libresoc.v:139994$5800_Y
- connect \$301 $ternary$libresoc.v:139995$5801_Y
- connect \$303 $ternary$libresoc.v:139996$5802_Y
- connect \$305 $ternary$libresoc.v:139997$5803_Y
- connect \$307 $ternary$libresoc.v:139998$5804_Y
- connect \$309 $ternary$libresoc.v:139999$5805_Y
- connect \$311 $eq$libresoc.v:140000$5806_Y
- connect \$313 $eq$libresoc.v:140001$5807_Y
- connect \$315 $or$libresoc.v:140002$5808_Y
- connect \$317 $eq$libresoc.v:140003$5809_Y
- connect \$31 $and$libresoc.v:140004$5810_Y
- connect \$319 $or$libresoc.v:140005$5811_Y
- connect \$321 $and$libresoc.v:140006$5812_Y
- connect \$323 $eq$libresoc.v:140007$5813_Y
- connect \$325 $ne$libresoc.v:140008$5814_Y
- connect \$327 $and$libresoc.v:140009$5815_Y
- connect \$329 $ne$libresoc.v:140010$5816_Y
- connect \$331 $and$libresoc.v:140011$5817_Y
- connect \$333 $ne$libresoc.v:140012$5818_Y
- connect \$335 $and$libresoc.v:140013$5819_Y
- connect \$337 $not$libresoc.v:140014$5820_Y
- connect \$33 $eq$libresoc.v:140015$5821_Y
- connect \$339 $and$libresoc.v:140016$5822_Y
- connect \$341 $eq$libresoc.v:140017$5823_Y
- connect \$343 $ne$libresoc.v:140018$5824_Y
- connect \$345 $and$libresoc.v:140019$5825_Y
- connect \$347 $ne$libresoc.v:140020$5826_Y
- connect \$349 $and$libresoc.v:140021$5827_Y
- connect \$351 $ne$libresoc.v:140022$5828_Y
- connect \$353 $and$libresoc.v:140023$5829_Y
- connect \$355 $not$libresoc.v:140024$5830_Y
- connect \$357 $and$libresoc.v:140025$5831_Y
- connect \$35 $eq$libresoc.v:140026$5832_Y
- connect \$359 $eq$libresoc.v:140027$5833_Y
- connect \$361 $eq$libresoc.v:140028$5834_Y
- connect \$363 $ne$libresoc.v:140029$5835_Y
- connect \$365 $and$libresoc.v:140030$5836_Y
- connect \$367 $ne$libresoc.v:140031$5837_Y
- connect \$369 $and$libresoc.v:140032$5838_Y
- connect \$371 $ne$libresoc.v:140033$5839_Y
- connect \$373 $and$libresoc.v:140034$5840_Y
- connect \$375 $not$libresoc.v:140035$5841_Y
- connect \$377 $and$libresoc.v:140036$5842_Y
- connect \$37 $or$libresoc.v:140037$5843_Y
- connect \$379 $eq$libresoc.v:140038$5844_Y
- connect \$381 $ne$libresoc.v:140039$5845_Y
- connect \$383 $and$libresoc.v:140040$5846_Y
- connect \$385 $ne$libresoc.v:140041$5847_Y
- connect \$387 $and$libresoc.v:140042$5848_Y
- connect \$389 $ne$libresoc.v:140043$5849_Y
- connect \$391 $and$libresoc.v:140044$5850_Y
- connect \$393 $not$libresoc.v:140045$5851_Y
- connect \$395 $and$libresoc.v:140046$5852_Y
- connect \$397 $eq$libresoc.v:140047$5853_Y
- connect \$3 $eq$libresoc.v:140048$5854_Y
- connect \$39 $eq$libresoc.v:140049$5855_Y
- connect \$399 $eq$libresoc.v:140050$5856_Y
- connect \$401 $ne$libresoc.v:140051$5857_Y
- connect \$403 $and$libresoc.v:140052$5858_Y
- connect \$405 $ne$libresoc.v:140053$5859_Y
- connect \$407 $and$libresoc.v:140054$5860_Y
- connect \$409 $ne$libresoc.v:140055$5861_Y
- connect \$411 $and$libresoc.v:140056$5862_Y
- connect \$413 $not$libresoc.v:140057$5863_Y
- connect \$415 $and$libresoc.v:140058$5864_Y
- connect \$417 $eq$libresoc.v:140059$5865_Y
- connect \$41 $or$libresoc.v:140060$5866_Y
- connect \$419 $ne$libresoc.v:140061$5867_Y
- connect \$421 $and$libresoc.v:140062$5868_Y
- connect \$423 $ne$libresoc.v:140063$5869_Y
- connect \$425 $and$libresoc.v:140064$5870_Y
- connect \$427 $ne$libresoc.v:140065$5871_Y
- connect \$429 $and$libresoc.v:140066$5872_Y
- connect \$431 $not$libresoc.v:140067$5873_Y
- connect \$433 $and$libresoc.v:140068$5874_Y
- connect \$436 $eq$libresoc.v:140069$5875_Y
- connect \$435 $not$libresoc.v:140070$5876_Y
- connect \$43 $and$libresoc.v:140071$5877_Y
- connect \$439 $eq$libresoc.v:140072$5878_Y
- connect \$441 $eq$libresoc.v:140073$5879_Y
- connect \$443 $or$libresoc.v:140074$5880_Y
- connect \$445 $eq$libresoc.v:140075$5881_Y
- connect \$448 $add$libresoc.v:140076$5882_Y
- connect \$451 $add$libresoc.v:140077$5883_Y
- connect \$453 $pos$libresoc.v:140078$5885_Y
- connect \$456 $eq$libresoc.v:140079$5886_Y
- connect \$458 $eq$libresoc.v:140080$5887_Y
- connect \$45 $and$libresoc.v:140081$5888_Y
- connect \$460 $or$libresoc.v:140082$5889_Y
- connect \$462 $eq$libresoc.v:140083$5890_Y
- connect \$465 $add$libresoc.v:140084$5891_Y
- connect \$468 $add$libresoc.v:140085$5892_Y
- connect \$47 $eq$libresoc.v:140086$5893_Y
- connect \$49 $eq$libresoc.v:140087$5894_Y
- connect \$51 $ternary$libresoc.v:140088$5895_Y
- connect \$53 $ternary$libresoc.v:140089$5896_Y
- connect \$55 $ternary$libresoc.v:140090$5897_Y
- connect \$57 $ternary$libresoc.v:140091$5898_Y
- connect \$5 $or$libresoc.v:140092$5899_Y
- connect \$59 $ternary$libresoc.v:140093$5900_Y
- connect \$61 $ternary$libresoc.v:140094$5901_Y
- connect \$63 $ternary$libresoc.v:140095$5902_Y
- connect \$65 $ternary$libresoc.v:140096$5903_Y
- connect \$67 $ternary$libresoc.v:140097$5904_Y
- connect \$69 $ternary$libresoc.v:140098$5905_Y
- connect \$71 $ternary$libresoc.v:140099$5906_Y
- connect \$73 $ternary$libresoc.v:140100$5907_Y
- connect \$75 $ternary$libresoc.v:140101$5908_Y
- connect \$77 $ternary$libresoc.v:140102$5909_Y
- connect \$7 $and$libresoc.v:140103$5910_Y
- connect \$79 $ternary$libresoc.v:140104$5911_Y
- connect \$81 $ternary$libresoc.v:140105$5912_Y
- connect \$83 $ternary$libresoc.v:140106$5913_Y
- connect \$85 $ternary$libresoc.v:140107$5914_Y
- connect \$87 $ternary$libresoc.v:140108$5915_Y
- connect \$89 $ternary$libresoc.v:140109$5916_Y
- connect \$91 $ternary$libresoc.v:140110$5917_Y
- connect \$93 $ternary$libresoc.v:140111$5918_Y
- connect \$95 $ternary$libresoc.v:140112$5919_Y
- connect \$97 $ternary$libresoc.v:140113$5920_Y
+ assign $2\io_bd$next[129:0]$6063 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ case
+ assign $2\io_bd$next[129:0]$6063 $1\io_bd$next[129:0]$6062
+ end
+ sync always
+ update \io_bd$next $0\io_bd$next[129:0]$6061
+ end
+ connect \$9 $eq$libresoc.v:139546$5636_Y
+ connect \$99 $ternary$libresoc.v:139547$5637_Y
+ connect \$101 $ternary$libresoc.v:139548$5638_Y
+ connect \$103 $ternary$libresoc.v:139549$5639_Y
+ connect \$105 $ternary$libresoc.v:139550$5640_Y
+ connect \$107 $ternary$libresoc.v:139551$5641_Y
+ connect \$109 $ternary$libresoc.v:139552$5642_Y
+ connect \$111 $ternary$libresoc.v:139553$5643_Y
+ connect \$113 $ternary$libresoc.v:139554$5644_Y
+ connect \$115 $ternary$libresoc.v:139555$5645_Y
+ connect \$117 $ternary$libresoc.v:139556$5646_Y
+ connect \$11 $eq$libresoc.v:139557$5647_Y
+ connect \$119 $ternary$libresoc.v:139558$5648_Y
+ connect \$121 $ternary$libresoc.v:139559$5649_Y
+ connect \$123 $ternary$libresoc.v:139560$5650_Y
+ connect \$125 $ternary$libresoc.v:139561$5651_Y
+ connect \$127 $ternary$libresoc.v:139562$5652_Y
+ connect \$129 $ternary$libresoc.v:139563$5653_Y
+ connect \$131 $ternary$libresoc.v:139564$5654_Y
+ connect \$133 $ternary$libresoc.v:139565$5655_Y
+ connect \$135 $ternary$libresoc.v:139566$5656_Y
+ connect \$137 $ternary$libresoc.v:139567$5657_Y
+ connect \$13 $eq$libresoc.v:139568$5658_Y
+ connect \$139 $ternary$libresoc.v:139569$5659_Y
+ connect \$141 $ternary$libresoc.v:139570$5660_Y
+ connect \$143 $ternary$libresoc.v:139571$5661_Y
+ connect \$145 $ternary$libresoc.v:139572$5662_Y
+ connect \$147 $ternary$libresoc.v:139573$5663_Y
+ connect \$149 $ternary$libresoc.v:139574$5664_Y
+ connect \$151 $ternary$libresoc.v:139575$5665_Y
+ connect \$153 $ternary$libresoc.v:139576$5666_Y
+ connect \$155 $ternary$libresoc.v:139577$5667_Y
+ connect \$157 $ternary$libresoc.v:139578$5668_Y
+ connect \$15 $or$libresoc.v:139579$5669_Y
+ connect \$159 $ternary$libresoc.v:139580$5670_Y
+ connect \$161 $ternary$libresoc.v:139581$5671_Y
+ connect \$163 $ternary$libresoc.v:139582$5672_Y
+ connect \$165 $ternary$libresoc.v:139583$5673_Y
+ connect \$167 $ternary$libresoc.v:139584$5674_Y
+ connect \$169 $ternary$libresoc.v:139585$5675_Y
+ connect \$171 $ternary$libresoc.v:139586$5676_Y
+ connect \$173 $ternary$libresoc.v:139587$5677_Y
+ connect \$175 $ternary$libresoc.v:139588$5678_Y
+ connect \$177 $ternary$libresoc.v:139589$5679_Y
+ connect \$17 $and$libresoc.v:139590$5680_Y
+ connect \$179 $ternary$libresoc.v:139591$5681_Y
+ connect \$181 $ternary$libresoc.v:139592$5682_Y
+ connect \$183 $ternary$libresoc.v:139593$5683_Y
+ connect \$185 $ternary$libresoc.v:139594$5684_Y
+ connect \$187 $ternary$libresoc.v:139595$5685_Y
+ connect \$189 $ternary$libresoc.v:139596$5686_Y
+ connect \$191 $ternary$libresoc.v:139597$5687_Y
+ connect \$193 $ternary$libresoc.v:139598$5688_Y
+ connect \$195 $ternary$libresoc.v:139599$5689_Y
+ connect \$197 $ternary$libresoc.v:139600$5690_Y
+ connect \$1 $eq$libresoc.v:139601$5691_Y
+ connect \$19 $eq$libresoc.v:139602$5692_Y
+ connect \$199 $ternary$libresoc.v:139603$5693_Y
+ connect \$201 $ternary$libresoc.v:139604$5694_Y
+ connect \$203 $ternary$libresoc.v:139605$5695_Y
+ connect \$205 $ternary$libresoc.v:139606$5696_Y
+ connect \$207 $ternary$libresoc.v:139607$5697_Y
+ connect \$209 $ternary$libresoc.v:139608$5698_Y
+ connect \$211 $ternary$libresoc.v:139609$5699_Y
+ connect \$213 $ternary$libresoc.v:139610$5700_Y
+ connect \$215 $ternary$libresoc.v:139611$5701_Y
+ connect \$217 $ternary$libresoc.v:139612$5702_Y
+ connect \$21 $eq$libresoc.v:139613$5703_Y
+ connect \$219 $ternary$libresoc.v:139614$5704_Y
+ connect \$221 $ternary$libresoc.v:139615$5705_Y
+ connect \$223 $ternary$libresoc.v:139616$5706_Y
+ connect \$225 $ternary$libresoc.v:139617$5707_Y
+ connect \$227 $ternary$libresoc.v:139618$5708_Y
+ connect \$229 $ternary$libresoc.v:139619$5709_Y
+ connect \$231 $ternary$libresoc.v:139620$5710_Y
+ connect \$233 $ternary$libresoc.v:139621$5711_Y
+ connect \$235 $ternary$libresoc.v:139622$5712_Y
+ connect \$237 $ternary$libresoc.v:139623$5713_Y
+ connect \$23 $or$libresoc.v:139624$5714_Y
+ connect \$239 $ternary$libresoc.v:139625$5715_Y
+ connect \$241 $ternary$libresoc.v:139626$5716_Y
+ connect \$243 $ternary$libresoc.v:139627$5717_Y
+ connect \$245 $ternary$libresoc.v:139628$5718_Y
+ connect \$247 $ternary$libresoc.v:139629$5719_Y
+ connect \$249 $ternary$libresoc.v:139630$5720_Y
+ connect \$251 $ternary$libresoc.v:139631$5721_Y
+ connect \$253 $ternary$libresoc.v:139632$5722_Y
+ connect \$255 $ternary$libresoc.v:139633$5723_Y
+ connect \$257 $ternary$libresoc.v:139634$5724_Y
+ connect \$25 $eq$libresoc.v:139635$5725_Y
+ connect \$259 $ternary$libresoc.v:139636$5726_Y
+ connect \$261 $ternary$libresoc.v:139637$5727_Y
+ connect \$263 $ternary$libresoc.v:139638$5728_Y
+ connect \$265 $ternary$libresoc.v:139639$5729_Y
+ connect \$267 $ternary$libresoc.v:139640$5730_Y
+ connect \$269 $ternary$libresoc.v:139641$5731_Y
+ connect \$271 $ternary$libresoc.v:139642$5732_Y
+ connect \$273 $ternary$libresoc.v:139643$5733_Y
+ connect \$275 $ternary$libresoc.v:139644$5734_Y
+ connect \$277 $ternary$libresoc.v:139645$5735_Y
+ connect \$27 $or$libresoc.v:139646$5736_Y
+ connect \$279 $ternary$libresoc.v:139647$5737_Y
+ connect \$281 $ternary$libresoc.v:139648$5738_Y
+ connect \$283 $ternary$libresoc.v:139649$5739_Y
+ connect \$285 $ternary$libresoc.v:139650$5740_Y
+ connect \$287 $ternary$libresoc.v:139651$5741_Y
+ connect \$289 $ternary$libresoc.v:139652$5742_Y
+ connect \$291 $ternary$libresoc.v:139653$5743_Y
+ connect \$293 $ternary$libresoc.v:139654$5744_Y
+ connect \$295 $ternary$libresoc.v:139655$5745_Y
+ connect \$297 $ternary$libresoc.v:139656$5746_Y
+ connect \$29 $and$libresoc.v:139657$5747_Y
+ connect \$299 $ternary$libresoc.v:139658$5748_Y
+ connect \$301 $ternary$libresoc.v:139659$5749_Y
+ connect \$303 $ternary$libresoc.v:139660$5750_Y
+ connect \$305 $ternary$libresoc.v:139661$5751_Y
+ connect \$307 $ternary$libresoc.v:139662$5752_Y
+ connect \$309 $ternary$libresoc.v:139663$5753_Y
+ connect \$311 $eq$libresoc.v:139664$5754_Y
+ connect \$313 $eq$libresoc.v:139665$5755_Y
+ connect \$315 $or$libresoc.v:139666$5756_Y
+ connect \$317 $eq$libresoc.v:139667$5757_Y
+ connect \$31 $and$libresoc.v:139668$5758_Y
+ connect \$319 $or$libresoc.v:139669$5759_Y
+ connect \$321 $and$libresoc.v:139670$5760_Y
+ connect \$323 $eq$libresoc.v:139671$5761_Y
+ connect \$325 $ne$libresoc.v:139672$5762_Y
+ connect \$327 $and$libresoc.v:139673$5763_Y
+ connect \$329 $ne$libresoc.v:139674$5764_Y
+ connect \$331 $and$libresoc.v:139675$5765_Y
+ connect \$333 $ne$libresoc.v:139676$5766_Y
+ connect \$335 $and$libresoc.v:139677$5767_Y
+ connect \$337 $not$libresoc.v:139678$5768_Y
+ connect \$33 $eq$libresoc.v:139679$5769_Y
+ connect \$339 $and$libresoc.v:139680$5770_Y
+ connect \$341 $eq$libresoc.v:139681$5771_Y
+ connect \$343 $ne$libresoc.v:139682$5772_Y
+ connect \$345 $and$libresoc.v:139683$5773_Y
+ connect \$347 $ne$libresoc.v:139684$5774_Y
+ connect \$349 $and$libresoc.v:139685$5775_Y
+ connect \$351 $ne$libresoc.v:139686$5776_Y
+ connect \$353 $and$libresoc.v:139687$5777_Y
+ connect \$355 $not$libresoc.v:139688$5778_Y
+ connect \$357 $and$libresoc.v:139689$5779_Y
+ connect \$35 $eq$libresoc.v:139690$5780_Y
+ connect \$359 $eq$libresoc.v:139691$5781_Y
+ connect \$361 $eq$libresoc.v:139692$5782_Y
+ connect \$363 $ne$libresoc.v:139693$5783_Y
+ connect \$365 $and$libresoc.v:139694$5784_Y
+ connect \$367 $ne$libresoc.v:139695$5785_Y
+ connect \$369 $and$libresoc.v:139696$5786_Y
+ connect \$371 $ne$libresoc.v:139697$5787_Y
+ connect \$373 $and$libresoc.v:139698$5788_Y
+ connect \$375 $not$libresoc.v:139699$5789_Y
+ connect \$377 $and$libresoc.v:139700$5790_Y
+ connect \$37 $or$libresoc.v:139701$5791_Y
+ connect \$379 $eq$libresoc.v:139702$5792_Y
+ connect \$381 $ne$libresoc.v:139703$5793_Y
+ connect \$383 $and$libresoc.v:139704$5794_Y
+ connect \$385 $ne$libresoc.v:139705$5795_Y
+ connect \$387 $and$libresoc.v:139706$5796_Y
+ connect \$389 $ne$libresoc.v:139707$5797_Y
+ connect \$391 $and$libresoc.v:139708$5798_Y
+ connect \$393 $not$libresoc.v:139709$5799_Y
+ connect \$395 $and$libresoc.v:139710$5800_Y
+ connect \$397 $eq$libresoc.v:139711$5801_Y
+ connect \$3 $eq$libresoc.v:139712$5802_Y
+ connect \$39 $eq$libresoc.v:139713$5803_Y
+ connect \$399 $eq$libresoc.v:139714$5804_Y
+ connect \$401 $ne$libresoc.v:139715$5805_Y
+ connect \$403 $and$libresoc.v:139716$5806_Y
+ connect \$405 $ne$libresoc.v:139717$5807_Y
+ connect \$407 $and$libresoc.v:139718$5808_Y
+ connect \$409 $ne$libresoc.v:139719$5809_Y
+ connect \$411 $and$libresoc.v:139720$5810_Y
+ connect \$413 $not$libresoc.v:139721$5811_Y
+ connect \$415 $and$libresoc.v:139722$5812_Y
+ connect \$417 $eq$libresoc.v:139723$5813_Y
+ connect \$41 $or$libresoc.v:139724$5814_Y
+ connect \$419 $ne$libresoc.v:139725$5815_Y
+ connect \$421 $and$libresoc.v:139726$5816_Y
+ connect \$423 $ne$libresoc.v:139727$5817_Y
+ connect \$425 $and$libresoc.v:139728$5818_Y
+ connect \$427 $ne$libresoc.v:139729$5819_Y
+ connect \$429 $and$libresoc.v:139730$5820_Y
+ connect \$431 $not$libresoc.v:139731$5821_Y
+ connect \$433 $and$libresoc.v:139732$5822_Y
+ connect \$436 $eq$libresoc.v:139733$5823_Y
+ connect \$435 $not$libresoc.v:139734$5824_Y
+ connect \$43 $and$libresoc.v:139735$5825_Y
+ connect \$439 $eq$libresoc.v:139736$5826_Y
+ connect \$441 $eq$libresoc.v:139737$5827_Y
+ connect \$443 $or$libresoc.v:139738$5828_Y
+ connect \$445 $eq$libresoc.v:139739$5829_Y
+ connect \$448 $add$libresoc.v:139740$5830_Y
+ connect \$451 $add$libresoc.v:139741$5831_Y
+ connect \$453 $pos$libresoc.v:139742$5833_Y
+ connect \$456 $eq$libresoc.v:139743$5834_Y
+ connect \$458 $eq$libresoc.v:139744$5835_Y
+ connect \$45 $and$libresoc.v:139745$5836_Y
+ connect \$460 $or$libresoc.v:139746$5837_Y
+ connect \$462 $eq$libresoc.v:139747$5838_Y
+ connect \$465 $add$libresoc.v:139748$5839_Y
+ connect \$468 $add$libresoc.v:139749$5840_Y
+ connect \$47 $eq$libresoc.v:139750$5841_Y
+ connect \$49 $eq$libresoc.v:139751$5842_Y
+ connect \$51 $ternary$libresoc.v:139752$5843_Y
+ connect \$53 $ternary$libresoc.v:139753$5844_Y
+ connect \$55 $ternary$libresoc.v:139754$5845_Y
+ connect \$57 $ternary$libresoc.v:139755$5846_Y
+ connect \$5 $or$libresoc.v:139756$5847_Y
+ connect \$59 $ternary$libresoc.v:139757$5848_Y
+ connect \$61 $ternary$libresoc.v:139758$5849_Y
+ connect \$63 $ternary$libresoc.v:139759$5850_Y
+ connect \$65 $ternary$libresoc.v:139760$5851_Y
+ connect \$67 $ternary$libresoc.v:139761$5852_Y
+ connect \$69 $ternary$libresoc.v:139762$5853_Y
+ connect \$71 $ternary$libresoc.v:139763$5854_Y
+ connect \$73 $ternary$libresoc.v:139764$5855_Y
+ connect \$75 $ternary$libresoc.v:139765$5856_Y
+ connect \$77 $ternary$libresoc.v:139766$5857_Y
+ connect \$7 $and$libresoc.v:139767$5858_Y
+ connect \$79 $ternary$libresoc.v:139768$5859_Y
+ connect \$81 $ternary$libresoc.v:139769$5860_Y
+ connect \$83 $ternary$libresoc.v:139770$5861_Y
+ connect \$85 $ternary$libresoc.v:139771$5862_Y
+ connect \$87 $ternary$libresoc.v:139772$5863_Y
+ connect \$89 $ternary$libresoc.v:139773$5864_Y
+ connect \$91 $ternary$libresoc.v:139774$5865_Y
+ connect \$93 $ternary$libresoc.v:139775$5866_Y
+ connect \$95 $ternary$libresoc.v:139776$5867_Y
+ connect \$97 $ternary$libresoc.v:139777$5868_Y
connect \$447 \$448
connect \$450 \$451
connect \$464 \$465
connect \_idblock_id_bypass \$9
connect \_idblock_select_id \$7
end
-attribute \src "libresoc.v:141165.1-141354.10"
+attribute \src "libresoc.v:140829.1-141018.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0"
attribute \generator "nMigen"
module \l0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 23 \dbus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
wire input 21 \wb_dcache_en
attribute \module_not_derived 1
- attribute \src "libresoc.v:141270.12-141304.4"
+ attribute \src "libresoc.v:140934.12-140968.4"
cell \l0$130 \l0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:141305.9-141327.4"
+ attribute \src "libresoc.v:140969.9-140991.4"
cell \lsmem \lsmem
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \x_valid_i \pimem_x_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:141328.9-141352.4"
+ attribute \src "libresoc.v:140992.9-141016.4"
cell \pimem \pimem
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
end
connect \pimem_ldst_port0_exc_$signal 1'0
end
-attribute \src "libresoc.v:141358.1-141766.10"
+attribute \src "libresoc.v:141022.1-141430.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0"
attribute \generator "nMigen"
module \l0$130
- attribute \src "libresoc.v:141621.3-141635.6"
- wire $0\idx_l$23$next[0:0]$6194
- attribute \src "libresoc.v:141521.3-141522.35"
- wire $0\idx_l$23[0:0]$6161
- attribute \src "libresoc.v:141379.7-141379.24"
- wire $0\idx_l$23[0:0]$6216
- attribute \src "libresoc.v:141676.3-141685.6"
+ attribute \src "libresoc.v:141285.3-141299.6"
+ wire $0\idx_l$23$next[0:0]$6142
+ attribute \src "libresoc.v:141185.3-141186.35"
+ wire $0\idx_l$23[0:0]$6109
+ attribute \src "libresoc.v:141043.7-141043.24"
+ wire $0\idx_l$23[0:0]$6164
+ attribute \src "libresoc.v:141340.3-141349.6"
wire $0\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:141666.3-141675.6"
+ attribute \src "libresoc.v:141330.3-141339.6"
wire $0\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:141359.7-141359.20"
+ attribute \src "libresoc.v:141023.7-141023.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:141542.3-141551.6"
- wire width 48 $0\ldst_port0_addr_i$12[47:0]$6163
- attribute \src "libresoc.v:141552.3-141561.6"
- wire $0\ldst_port0_addr_i_ok$13[0:0]$6166
- attribute \src "libresoc.v:141594.3-141603.6"
+ attribute \src "libresoc.v:141206.3-141215.6"
+ wire width 48 $0\ldst_port0_addr_i$12[47:0]$6111
+ attribute \src "libresoc.v:141216.3-141225.6"
+ wire $0\ldst_port0_addr_i_ok$13[0:0]$6114
+ attribute \src "libresoc.v:141258.3-141267.6"
wire $0\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:141584.3-141593.6"
+ attribute \src "libresoc.v:141248.3-141257.6"
wire $0\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:141656.3-141665.6"
+ attribute \src "libresoc.v:141320.3-141329.6"
wire $0\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:141731.3-141740.6"
- wire width 4 $0\ldst_port0_data_len$11[3:0]$6211
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$1[0:0]$6178
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$2[0:0]$6179
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$3[0:0]$6180
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$4[0:0]$6181
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$5[0:0]$6182
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$6[0:0]$6183
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal$7[0:0]$6184
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $0\ldst_port0_exc_$signal[0:0]$6177
- attribute \src "libresoc.v:141741.3-141750.6"
+ attribute \src "libresoc.v:141395.3-141404.6"
+ wire width 4 $0\ldst_port0_data_len$11[3:0]$6159
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$1[0:0]$6126
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$2[0:0]$6127
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$3[0:0]$6128
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$4[0:0]$6129
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$5[0:0]$6130
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$6[0:0]$6131
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal$7[0:0]$6132
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $0\ldst_port0_exc_$signal[0:0]$6125
+ attribute \src "libresoc.v:141405.3-141414.6"
wire $0\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:141711.3-141720.6"
- wire $0\ldst_port0_is_ld_i$8[0:0]$6205
- attribute \src "libresoc.v:141721.3-141730.6"
- wire $0\ldst_port0_is_st_i$9[0:0]$6208
- attribute \src "libresoc.v:141573.3-141583.6"
+ attribute \src "libresoc.v:141375.3-141384.6"
+ wire $0\ldst_port0_is_ld_i$8[0:0]$6153
+ attribute \src "libresoc.v:141385.3-141394.6"
+ wire $0\ldst_port0_is_st_i$9[0:0]$6156
+ attribute \src "libresoc.v:141237.3-141247.6"
wire width 64 $0\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:141573.3-141583.6"
+ attribute \src "libresoc.v:141237.3-141247.6"
wire $0\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:141646.3-141655.6"
+ attribute \src "libresoc.v:141310.3-141319.6"
wire $0\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:141636.3-141645.6"
+ attribute \src "libresoc.v:141300.3-141309.6"
wire $0\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:141562.3-141572.6"
- wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6169
- attribute \src "libresoc.v:141562.3-141572.6"
- wire $0\ldst_port0_st_data_i_ok$17[0:0]$6170
- attribute \src "libresoc.v:141519.3-141520.36"
+ attribute \src "libresoc.v:141226.3-141236.6"
+ wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6117
+ attribute \src "libresoc.v:141226.3-141236.6"
+ wire $0\ldst_port0_st_data_i_ok$17[0:0]$6118
+ attribute \src "libresoc.v:141183.3-141184.36"
wire $0\reset_delay[0:0]
- attribute \src "libresoc.v:141701.3-141710.6"
+ attribute \src "libresoc.v:141365.3-141374.6"
wire $0\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:141686.3-141700.6"
+ attribute \src "libresoc.v:141350.3-141364.6"
wire $0\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:141621.3-141635.6"
- wire $1\idx_l$23$next[0:0]$6195
- attribute \src "libresoc.v:141676.3-141685.6"
+ attribute \src "libresoc.v:141285.3-141299.6"
+ wire $1\idx_l$23$next[0:0]$6143
+ attribute \src "libresoc.v:141340.3-141349.6"
wire $1\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:141666.3-141675.6"
+ attribute \src "libresoc.v:141330.3-141339.6"
wire $1\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:141542.3-141551.6"
- wire width 48 $1\ldst_port0_addr_i$12[47:0]$6164
- attribute \src "libresoc.v:141552.3-141561.6"
- wire $1\ldst_port0_addr_i_ok$13[0:0]$6167
- attribute \src "libresoc.v:141594.3-141603.6"
+ attribute \src "libresoc.v:141206.3-141215.6"
+ wire width 48 $1\ldst_port0_addr_i$12[47:0]$6112
+ attribute \src "libresoc.v:141216.3-141225.6"
+ wire $1\ldst_port0_addr_i_ok$13[0:0]$6115
+ attribute \src "libresoc.v:141258.3-141267.6"
wire $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:141584.3-141593.6"
+ attribute \src "libresoc.v:141248.3-141257.6"
wire $1\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:141656.3-141665.6"
+ attribute \src "libresoc.v:141320.3-141329.6"
wire $1\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:141731.3-141740.6"
- wire width 4 $1\ldst_port0_data_len$11[3:0]$6212
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$1[0:0]$6186
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$2[0:0]$6187
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$3[0:0]$6188
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$4[0:0]$6189
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$5[0:0]$6190
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$6[0:0]$6191
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal$7[0:0]$6192
- attribute \src "libresoc.v:141604.3-141620.6"
- wire $1\ldst_port0_exc_$signal[0:0]$6185
- attribute \src "libresoc.v:141741.3-141750.6"
+ attribute \src "libresoc.v:141395.3-141404.6"
+ wire width 4 $1\ldst_port0_data_len$11[3:0]$6160
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$1[0:0]$6134
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$2[0:0]$6135
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$3[0:0]$6136
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$4[0:0]$6137
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$5[0:0]$6138
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$6[0:0]$6139
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal$7[0:0]$6140
+ attribute \src "libresoc.v:141268.3-141284.6"
+ wire $1\ldst_port0_exc_$signal[0:0]$6133
+ attribute \src "libresoc.v:141405.3-141414.6"
wire $1\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:141711.3-141720.6"
- wire $1\ldst_port0_is_ld_i$8[0:0]$6206
- attribute \src "libresoc.v:141721.3-141730.6"
- wire $1\ldst_port0_is_st_i$9[0:0]$6209
- attribute \src "libresoc.v:141573.3-141583.6"
+ attribute \src "libresoc.v:141375.3-141384.6"
+ wire $1\ldst_port0_is_ld_i$8[0:0]$6154
+ attribute \src "libresoc.v:141385.3-141394.6"
+ wire $1\ldst_port0_is_st_i$9[0:0]$6157
+ attribute \src "libresoc.v:141237.3-141247.6"
wire width 64 $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:141573.3-141583.6"
+ attribute \src "libresoc.v:141237.3-141247.6"
wire $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:141646.3-141655.6"
+ attribute \src "libresoc.v:141310.3-141319.6"
wire $1\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:141636.3-141645.6"
+ attribute \src "libresoc.v:141300.3-141309.6"
wire $1\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:141562.3-141572.6"
- wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6171
- attribute \src "libresoc.v:141562.3-141572.6"
- wire $1\ldst_port0_st_data_i_ok$17[0:0]$6172
- attribute \src "libresoc.v:141506.7-141506.25"
+ attribute \src "libresoc.v:141226.3-141236.6"
+ wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6119
+ attribute \src "libresoc.v:141226.3-141236.6"
+ wire $1\ldst_port0_st_data_i_ok$17[0:0]$6120
+ attribute \src "libresoc.v:141170.7-141170.25"
wire $1\reset_delay[0:0]
- attribute \src "libresoc.v:141701.3-141710.6"
+ attribute \src "libresoc.v:141365.3-141374.6"
wire $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:141686.3-141700.6"
+ attribute \src "libresoc.v:141350.3-141364.6"
wire $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:141621.3-141635.6"
- wire $2\idx_l$23$next[0:0]$6196
- attribute \src "libresoc.v:141686.3-141700.6"
+ attribute \src "libresoc.v:141285.3-141299.6"
+ wire $2\idx_l$23$next[0:0]$6144
+ attribute \src "libresoc.v:141350.3-141364.6"
wire $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:141517.18-141517.103"
- wire $not$libresoc.v:141517$6157_Y
- attribute \src "libresoc.v:141518.18-141518.118"
- wire $not$libresoc.v:141518$6158_Y
- attribute \src "libresoc.v:141515.18-141515.134"
- wire $or$libresoc.v:141515$6155_Y
- attribute \src "libresoc.v:141516.18-141516.120"
- wire $ternary$libresoc.v:141516$6156_Y
+ attribute \src "libresoc.v:141181.18-141181.103"
+ wire $not$libresoc.v:141181$6105_Y
+ attribute \src "libresoc.v:141182.18-141182.118"
+ wire $not$libresoc.v:141182$6106_Y
+ attribute \src "libresoc.v:141179.18-141179.134"
+ wire $or$libresoc.v:141179$6103_Y
+ attribute \src "libresoc.v:141180.18-141180.120"
+ wire $ternary$libresoc.v:141180$6104_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262"
wire \$20
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
wire width 96 \$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136"
wire width 96 \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
wire \idx_l$23
wire \idx_l_r_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \idx_l_s_idx_l
- attribute \src "libresoc.v:141359.7-141359.15"
+ attribute \src "libresoc.v:141023.7-141023.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 96 input 6 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \reset_l_s_reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278"
- cell $not $not$libresoc.v:141517$6157
+ cell $not $not$libresoc.v:141181$6105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pick_n
- connect \Y $not$libresoc.v:141517$6157_Y
+ connect \Y $not$libresoc.v:141181$6105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288"
- cell $not $not$libresoc.v:141518$6158
+ cell $not $not$libresoc.v:141182$6106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o$10
- connect \Y $not$libresoc.v:141518$6158_Y
+ connect \Y $not$libresoc.v:141182$6106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262"
- cell $or $or$libresoc.v:141515$6155
+ cell $or $or$libresoc.v:141179$6103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:141515$6155_Y
+ connect \Y $or$libresoc.v:141179$6103_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:141516$6156
+ cell $mux $ternary$libresoc.v:141180$6104
parameter \WIDTH 1
connect \A \idx_l$23
connect \B \pick_o
connect \S \idx_l_q_idx_l
- connect \Y $ternary$libresoc.v:141516$6156_Y
+ connect \Y $ternary$libresoc.v:141180$6104_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:141523.9-141529.4"
+ attribute \src "libresoc.v:141187.9-141193.4"
cell \idx_l \idx_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_idx_l \idx_l_s_idx_l
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:141530.8-141534.4"
+ attribute \src "libresoc.v:141194.8-141198.4"
cell \pick \pick
connect \i \pick_i
connect \n \pick_n
connect \o \pick_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:141535.17-141541.4"
+ attribute \src "libresoc.v:141199.17-141205.4"
cell \reset_l$131 \reset_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_reset \reset_l_r_reset
connect \s_reset \reset_l_s_reset
end
- attribute \src "libresoc.v:141359.7-141359.20"
- process $proc$libresoc.v:141359$6214
+ attribute \src "libresoc.v:141023.7-141023.20"
+ process $proc$libresoc.v:141023$6162
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:141379.7-141379.24"
- process $proc$libresoc.v:141379$6215
+ attribute \src "libresoc.v:141043.7-141043.24"
+ process $proc$libresoc.v:141043$6163
assign { } { }
- assign $0\idx_l$23[0:0]$6216 1'0
+ assign $0\idx_l$23[0:0]$6164 1'0
sync always
sync init
- update \idx_l$23 $0\idx_l$23[0:0]$6216
+ update \idx_l$23 $0\idx_l$23[0:0]$6164
end
- attribute \src "libresoc.v:141506.7-141506.25"
- process $proc$libresoc.v:141506$6217
+ attribute \src "libresoc.v:141170.7-141170.25"
+ process $proc$libresoc.v:141170$6165
assign { } { }
assign $1\reset_delay[0:0] 1'0
sync always
sync init
update \reset_delay $1\reset_delay[0:0]
end
- attribute \src "libresoc.v:141519.3-141520.36"
- process $proc$libresoc.v:141519$6159
+ attribute \src "libresoc.v:141183.3-141184.36"
+ process $proc$libresoc.v:141183$6107
assign { } { }
assign $0\reset_delay[0:0] \reset_l_q_reset
sync posedge \coresync_clk
update \reset_delay $0\reset_delay[0:0]
end
- attribute \src "libresoc.v:141521.3-141522.35"
- process $proc$libresoc.v:141521$6160
+ attribute \src "libresoc.v:141185.3-141186.35"
+ process $proc$libresoc.v:141185$6108
assign { } { }
- assign $0\idx_l$23[0:0]$6161 \idx_l$23$next
+ assign $0\idx_l$23[0:0]$6109 \idx_l$23$next
sync posedge \coresync_clk
- update \idx_l$23 $0\idx_l$23[0:0]$6161
+ update \idx_l$23 $0\idx_l$23[0:0]$6109
end
- attribute \src "libresoc.v:141542.3-141551.6"
- process $proc$libresoc.v:141542$6162
+ attribute \src "libresoc.v:141206.3-141215.6"
+ process $proc$libresoc.v:141206$6110
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i$12[47:0]$6163 $1\ldst_port0_addr_i$12[47:0]$6164
- attribute \src "libresoc.v:141543.5-141543.29"
+ assign $0\ldst_port0_addr_i$12[47:0]$6111 $1\ldst_port0_addr_i$12[47:0]$6112
+ attribute \src "libresoc.v:141207.5-141207.29"
switch \initial
- attribute \src "libresoc.v:141543.9-141543.17"
+ attribute \src "libresoc.v:141207.9-141207.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i$12[47:0]$6164 \$32 [47:0]
+ assign $1\ldst_port0_addr_i$12[47:0]$6112 \$32 [47:0]
case
- assign $1\ldst_port0_addr_i$12[47:0]$6164 48'000000000000000000000000000000000000000000000000
+ assign $1\ldst_port0_addr_i$12[47:0]$6112 48'000000000000000000000000000000000000000000000000
end
sync always
- update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6163
+ update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6111
end
- attribute \src "libresoc.v:141552.3-141561.6"
- process $proc$libresoc.v:141552$6165
+ attribute \src "libresoc.v:141216.3-141225.6"
+ process $proc$libresoc.v:141216$6113
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i_ok$13[0:0]$6166 $1\ldst_port0_addr_i_ok$13[0:0]$6167
- attribute \src "libresoc.v:141553.5-141553.29"
+ assign $0\ldst_port0_addr_i_ok$13[0:0]$6114 $1\ldst_port0_addr_i_ok$13[0:0]$6115
+ attribute \src "libresoc.v:141217.5-141217.29"
switch \initial
- attribute \src "libresoc.v:141553.9-141553.17"
+ attribute \src "libresoc.v:141217.9-141217.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i_ok$13[0:0]$6167 \ldst_port0_addr_i_ok
+ assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 \ldst_port0_addr_i_ok
case
- assign $1\ldst_port0_addr_i_ok$13[0:0]$6167 1'0
+ assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 1'0
end
sync always
- update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6166
+ update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6114
end
- attribute \src "libresoc.v:141562.3-141572.6"
- process $proc$libresoc.v:141562$6168
+ attribute \src "libresoc.v:141226.3-141236.6"
+ process $proc$libresoc.v:141226$6116
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\ldst_port0_st_data_i$18[63:0]$6169 $1\ldst_port0_st_data_i$18[63:0]$6171
- assign $0\ldst_port0_st_data_i_ok$17[0:0]$6170 $1\ldst_port0_st_data_i_ok$17[0:0]$6172
- attribute \src "libresoc.v:141563.5-141563.29"
+ assign $0\ldst_port0_st_data_i$18[63:0]$6117 $1\ldst_port0_st_data_i$18[63:0]$6119
+ assign $0\ldst_port0_st_data_i_ok$17[0:0]$6118 $1\ldst_port0_st_data_i_ok$17[0:0]$6120
+ attribute \src "libresoc.v:141227.5-141227.29"
switch \initial
- attribute \src "libresoc.v:141563.9-141563.17"
+ attribute \src "libresoc.v:141227.9-141227.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6172 $1\ldst_port0_st_data_i$18[63:0]$6171 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
+ assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6120 $1\ldst_port0_st_data_i$18[63:0]$6119 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
case
- assign $1\ldst_port0_st_data_i$18[63:0]$6171 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $1\ldst_port0_st_data_i_ok$17[0:0]$6172 1'0
+ assign $1\ldst_port0_st_data_i$18[63:0]$6119 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\ldst_port0_st_data_i_ok$17[0:0]$6120 1'0
end
sync always
- update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6169
- update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6170
+ update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6117
+ update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6118
end
- attribute \src "libresoc.v:141573.3-141583.6"
- process $proc$libresoc.v:141573$6173
+ attribute \src "libresoc.v:141237.3-141247.6"
+ process $proc$libresoc.v:141237$6121
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0]
assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:141574.5-141574.29"
+ attribute \src "libresoc.v:141238.5-141238.29"
switch \initial
- attribute \src "libresoc.v:141574.9-141574.17"
+ attribute \src "libresoc.v:141238.9-141238.17"
case 1'1
case
end
update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0]
update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0]
end
- attribute \src "libresoc.v:141584.3-141593.6"
- process $proc$libresoc.v:141584$6174
+ attribute \src "libresoc.v:141248.3-141257.6"
+ process $proc$libresoc.v:141248$6122
assign { } { }
assign { } { }
assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:141585.5-141585.29"
+ attribute \src "libresoc.v:141249.5-141249.29"
switch \initial
- attribute \src "libresoc.v:141585.9-141585.17"
+ attribute \src "libresoc.v:141249.9-141249.17"
case 1'1
case
end
sync always
update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0]
end
- attribute \src "libresoc.v:141594.3-141603.6"
- process $proc$libresoc.v:141594$6175
+ attribute \src "libresoc.v:141258.3-141267.6"
+ process $proc$libresoc.v:141258$6123
assign { } { }
assign { } { }
assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:141595.5-141595.29"
+ attribute \src "libresoc.v:141259.5-141259.29"
switch \initial
- attribute \src "libresoc.v:141595.9-141595.17"
+ attribute \src "libresoc.v:141259.9-141259.17"
case 1'1
case
end
sync always
update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0]
end
- attribute \src "libresoc.v:141604.3-141620.6"
- process $proc$libresoc.v:141604$6176
+ attribute \src "libresoc.v:141268.3-141284.6"
+ process $proc$libresoc.v:141268$6124
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\ldst_port0_exc_$signal[0:0]$6177 $1\ldst_port0_exc_$signal[0:0]$6185
- assign $0\ldst_port0_exc_$signal$1[0:0]$6178 $1\ldst_port0_exc_$signal$1[0:0]$6186
- assign $0\ldst_port0_exc_$signal$2[0:0]$6179 $1\ldst_port0_exc_$signal$2[0:0]$6187
- assign $0\ldst_port0_exc_$signal$3[0:0]$6180 $1\ldst_port0_exc_$signal$3[0:0]$6188
- assign $0\ldst_port0_exc_$signal$4[0:0]$6181 $1\ldst_port0_exc_$signal$4[0:0]$6189
- assign $0\ldst_port0_exc_$signal$5[0:0]$6182 $1\ldst_port0_exc_$signal$5[0:0]$6190
- assign $0\ldst_port0_exc_$signal$6[0:0]$6183 $1\ldst_port0_exc_$signal$6[0:0]$6191
- assign $0\ldst_port0_exc_$signal$7[0:0]$6184 $1\ldst_port0_exc_$signal$7[0:0]$6192
- attribute \src "libresoc.v:141605.5-141605.29"
+ assign $0\ldst_port0_exc_$signal[0:0]$6125 $1\ldst_port0_exc_$signal[0:0]$6133
+ assign $0\ldst_port0_exc_$signal$1[0:0]$6126 $1\ldst_port0_exc_$signal$1[0:0]$6134
+ assign $0\ldst_port0_exc_$signal$2[0:0]$6127 $1\ldst_port0_exc_$signal$2[0:0]$6135
+ assign $0\ldst_port0_exc_$signal$3[0:0]$6128 $1\ldst_port0_exc_$signal$3[0:0]$6136
+ assign $0\ldst_port0_exc_$signal$4[0:0]$6129 $1\ldst_port0_exc_$signal$4[0:0]$6137
+ assign $0\ldst_port0_exc_$signal$5[0:0]$6130 $1\ldst_port0_exc_$signal$5[0:0]$6138
+ assign $0\ldst_port0_exc_$signal$6[0:0]$6131 $1\ldst_port0_exc_$signal$6[0:0]$6139
+ assign $0\ldst_port0_exc_$signal$7[0:0]$6132 $1\ldst_port0_exc_$signal$7[0:0]$6140
+ attribute \src "libresoc.v:141269.5-141269.29"
switch \initial
- attribute \src "libresoc.v:141605.9-141605.17"
+ attribute \src "libresoc.v:141269.9-141269.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\ldst_port0_exc_$signal$7[0:0]$6192 $1\ldst_port0_exc_$signal$6[0:0]$6191 $1\ldst_port0_exc_$signal$5[0:0]$6190 $1\ldst_port0_exc_$signal$4[0:0]$6189 $1\ldst_port0_exc_$signal$3[0:0]$6188 $1\ldst_port0_exc_$signal$2[0:0]$6187 $1\ldst_port0_exc_$signal$1[0:0]$6186 $1\ldst_port0_exc_$signal[0:0]$6185 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 }
+ assign { $1\ldst_port0_exc_$signal$7[0:0]$6140 $1\ldst_port0_exc_$signal$6[0:0]$6139 $1\ldst_port0_exc_$signal$5[0:0]$6138 $1\ldst_port0_exc_$signal$4[0:0]$6137 $1\ldst_port0_exc_$signal$3[0:0]$6136 $1\ldst_port0_exc_$signal$2[0:0]$6135 $1\ldst_port0_exc_$signal$1[0:0]$6134 $1\ldst_port0_exc_$signal[0:0]$6133 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 }
case
- assign $1\ldst_port0_exc_$signal[0:0]$6185 1'0
- assign $1\ldst_port0_exc_$signal$1[0:0]$6186 1'0
- assign $1\ldst_port0_exc_$signal$2[0:0]$6187 1'0
- assign $1\ldst_port0_exc_$signal$3[0:0]$6188 1'0
- assign $1\ldst_port0_exc_$signal$4[0:0]$6189 1'0
- assign $1\ldst_port0_exc_$signal$5[0:0]$6190 1'0
- assign $1\ldst_port0_exc_$signal$6[0:0]$6191 1'0
- assign $1\ldst_port0_exc_$signal$7[0:0]$6192 1'0
+ assign $1\ldst_port0_exc_$signal[0:0]$6133 1'0
+ assign $1\ldst_port0_exc_$signal$1[0:0]$6134 1'0
+ assign $1\ldst_port0_exc_$signal$2[0:0]$6135 1'0
+ assign $1\ldst_port0_exc_$signal$3[0:0]$6136 1'0
+ assign $1\ldst_port0_exc_$signal$4[0:0]$6137 1'0
+ assign $1\ldst_port0_exc_$signal$5[0:0]$6138 1'0
+ assign $1\ldst_port0_exc_$signal$6[0:0]$6139 1'0
+ assign $1\ldst_port0_exc_$signal$7[0:0]$6140 1'0
end
sync always
- update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6177
- update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6178
- update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6179
- update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6180
- update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6181
- update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6182
- update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6183
- update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6184
+ update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6125
+ update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6126
+ update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6127
+ update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6128
+ update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6129
+ update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6130
+ update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6131
+ update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6132
end
- attribute \src "libresoc.v:141621.3-141635.6"
- process $proc$libresoc.v:141621$6193
+ attribute \src "libresoc.v:141285.3-141299.6"
+ process $proc$libresoc.v:141285$6141
assign { } { }
assign { } { }
assign { } { }
- assign $0\idx_l$23$next[0:0]$6194 $2\idx_l$23$next[0:0]$6196
- attribute \src "libresoc.v:141622.5-141622.29"
+ assign $0\idx_l$23$next[0:0]$6142 $2\idx_l$23$next[0:0]$6144
+ attribute \src "libresoc.v:141286.5-141286.29"
switch \initial
- attribute \src "libresoc.v:141622.9-141622.17"
+ attribute \src "libresoc.v:141286.9-141286.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\idx_l$23$next[0:0]$6195 \pick_o
+ assign $1\idx_l$23$next[0:0]$6143 \pick_o
case
- assign $1\idx_l$23$next[0:0]$6195 \idx_l$23
+ assign $1\idx_l$23$next[0:0]$6143 \idx_l$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\idx_l$23$next[0:0]$6196 1'0
+ assign $2\idx_l$23$next[0:0]$6144 1'0
case
- assign $2\idx_l$23$next[0:0]$6196 $1\idx_l$23$next[0:0]$6195
+ assign $2\idx_l$23$next[0:0]$6144 $1\idx_l$23$next[0:0]$6143
end
sync always
- update \idx_l$23$next $0\idx_l$23$next[0:0]$6194
+ update \idx_l$23$next $0\idx_l$23$next[0:0]$6142
end
- attribute \src "libresoc.v:141636.3-141645.6"
- process $proc$libresoc.v:141636$6197
+ attribute \src "libresoc.v:141300.3-141309.6"
+ process $proc$libresoc.v:141300$6145
assign { } { }
assign { } { }
assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:141637.5-141637.29"
+ attribute \src "libresoc.v:141301.5-141301.29"
switch \initial
- attribute \src "libresoc.v:141637.9-141637.17"
+ attribute \src "libresoc.v:141301.9-141301.17"
case 1'1
case
end
sync always
update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0]
end
- attribute \src "libresoc.v:141646.3-141655.6"
- process $proc$libresoc.v:141646$6198
+ attribute \src "libresoc.v:141310.3-141319.6"
+ process $proc$libresoc.v:141310$6146
assign { } { }
assign { } { }
assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:141647.5-141647.29"
+ attribute \src "libresoc.v:141311.5-141311.29"
switch \initial
- attribute \src "libresoc.v:141647.9-141647.17"
+ attribute \src "libresoc.v:141311.9-141311.17"
case 1'1
case
end
sync always
update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0]
end
- attribute \src "libresoc.v:141656.3-141665.6"
- process $proc$libresoc.v:141656$6199
+ attribute \src "libresoc.v:141320.3-141329.6"
+ process $proc$libresoc.v:141320$6147
assign { } { }
assign { } { }
assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:141657.5-141657.29"
+ attribute \src "libresoc.v:141321.5-141321.29"
switch \initial
- attribute \src "libresoc.v:141657.9-141657.17"
+ attribute \src "libresoc.v:141321.9-141321.17"
case 1'1
case
end
sync always
update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0]
end
- attribute \src "libresoc.v:141666.3-141675.6"
- process $proc$libresoc.v:141666$6200
+ attribute \src "libresoc.v:141330.3-141339.6"
+ process $proc$libresoc.v:141330$6148
assign { } { }
assign { } { }
assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:141667.5-141667.29"
+ attribute \src "libresoc.v:141331.5-141331.29"
switch \initial
- attribute \src "libresoc.v:141667.9-141667.17"
+ attribute \src "libresoc.v:141331.9-141331.17"
case 1'1
case
end
sync always
update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0]
end
- attribute \src "libresoc.v:141676.3-141685.6"
- process $proc$libresoc.v:141676$6201
+ attribute \src "libresoc.v:141340.3-141349.6"
+ process $proc$libresoc.v:141340$6149
assign { } { }
assign { } { }
assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:141677.5-141677.29"
+ attribute \src "libresoc.v:141341.5-141341.29"
switch \initial
- attribute \src "libresoc.v:141677.9-141677.17"
+ attribute \src "libresoc.v:141341.9-141341.17"
case 1'1
case
end
sync always
update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0]
end
- attribute \src "libresoc.v:141686.3-141700.6"
- process $proc$libresoc.v:141686$6202
+ attribute \src "libresoc.v:141350.3-141364.6"
+ process $proc$libresoc.v:141350$6150
assign { } { }
assign { } { }
assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:141687.5-141687.29"
+ attribute \src "libresoc.v:141351.5-141351.29"
switch \initial
- attribute \src "libresoc.v:141687.9-141687.17"
+ attribute \src "libresoc.v:141351.9-141351.17"
case 1'1
case
end
sync always
update \reset_l_s_reset $0\reset_l_s_reset[0:0]
end
- attribute \src "libresoc.v:141701.3-141710.6"
- process $proc$libresoc.v:141701$6203
+ attribute \src "libresoc.v:141365.3-141374.6"
+ process $proc$libresoc.v:141365$6151
assign { } { }
assign { } { }
assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:141702.5-141702.29"
+ attribute \src "libresoc.v:141366.5-141366.29"
switch \initial
- attribute \src "libresoc.v:141702.9-141702.17"
+ attribute \src "libresoc.v:141366.9-141366.17"
case 1'1
case
end
sync always
update \reset_l_r_reset $0\reset_l_r_reset[0:0]
end
- attribute \src "libresoc.v:141711.3-141720.6"
- process $proc$libresoc.v:141711$6204
+ attribute \src "libresoc.v:141375.3-141384.6"
+ process $proc$libresoc.v:141375$6152
assign { } { }
assign { } { }
- assign $0\ldst_port0_is_ld_i$8[0:0]$6205 $1\ldst_port0_is_ld_i$8[0:0]$6206
- attribute \src "libresoc.v:141712.5-141712.29"
+ assign $0\ldst_port0_is_ld_i$8[0:0]$6153 $1\ldst_port0_is_ld_i$8[0:0]$6154
+ attribute \src "libresoc.v:141376.5-141376.29"
switch \initial
- attribute \src "libresoc.v:141712.9-141712.17"
+ attribute \src "libresoc.v:141376.9-141376.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_is_ld_i$8[0:0]$6206 \ldst_port0_is_ld_i
+ assign $1\ldst_port0_is_ld_i$8[0:0]$6154 \ldst_port0_is_ld_i
case
- assign $1\ldst_port0_is_ld_i$8[0:0]$6206 1'0
+ assign $1\ldst_port0_is_ld_i$8[0:0]$6154 1'0
end
sync always
- update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6205
+ update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6153
end
- attribute \src "libresoc.v:141721.3-141730.6"
- process $proc$libresoc.v:141721$6207
+ attribute \src "libresoc.v:141385.3-141394.6"
+ process $proc$libresoc.v:141385$6155
assign { } { }
assign { } { }
- assign $0\ldst_port0_is_st_i$9[0:0]$6208 $1\ldst_port0_is_st_i$9[0:0]$6209
- attribute \src "libresoc.v:141722.5-141722.29"
+ assign $0\ldst_port0_is_st_i$9[0:0]$6156 $1\ldst_port0_is_st_i$9[0:0]$6157
+ attribute \src "libresoc.v:141386.5-141386.29"
switch \initial
- attribute \src "libresoc.v:141722.9-141722.17"
+ attribute \src "libresoc.v:141386.9-141386.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_is_st_i$9[0:0]$6209 \ldst_port0_is_st_i
+ assign $1\ldst_port0_is_st_i$9[0:0]$6157 \ldst_port0_is_st_i
case
- assign $1\ldst_port0_is_st_i$9[0:0]$6209 1'0
+ assign $1\ldst_port0_is_st_i$9[0:0]$6157 1'0
end
sync always
- update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6208
+ update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6156
end
- attribute \src "libresoc.v:141731.3-141740.6"
- process $proc$libresoc.v:141731$6210
+ attribute \src "libresoc.v:141395.3-141404.6"
+ process $proc$libresoc.v:141395$6158
assign { } { }
assign { } { }
- assign $0\ldst_port0_data_len$11[3:0]$6211 $1\ldst_port0_data_len$11[3:0]$6212
- attribute \src "libresoc.v:141732.5-141732.29"
+ assign $0\ldst_port0_data_len$11[3:0]$6159 $1\ldst_port0_data_len$11[3:0]$6160
+ attribute \src "libresoc.v:141396.5-141396.29"
switch \initial
- attribute \src "libresoc.v:141732.9-141732.17"
+ attribute \src "libresoc.v:141396.9-141396.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_data_len$11[3:0]$6212 \ldst_port0_data_len
+ assign $1\ldst_port0_data_len$11[3:0]$6160 \ldst_port0_data_len
case
- assign $1\ldst_port0_data_len$11[3:0]$6212 4'0000
+ assign $1\ldst_port0_data_len$11[3:0]$6160 4'0000
end
sync always
- update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6211
+ update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6159
end
- attribute \src "libresoc.v:141741.3-141750.6"
- process $proc$libresoc.v:141741$6213
+ attribute \src "libresoc.v:141405.3-141414.6"
+ process $proc$libresoc.v:141405$6161
assign { } { }
assign { } { }
assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:141742.5-141742.29"
+ attribute \src "libresoc.v:141406.5-141406.29"
switch \initial
- attribute \src "libresoc.v:141742.9-141742.17"
+ attribute \src "libresoc.v:141406.9-141406.17"
case 1'1
case
end
sync always
update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0]
end
- connect \$20 $or$libresoc.v:141515$6155_Y
- connect \$24 $ternary$libresoc.v:141516$6156_Y
- connect \$26 $not$libresoc.v:141517$6157_Y
- connect \$28 $not$libresoc.v:141518$6158_Y
+ connect \$20 $or$libresoc.v:141179$6103_Y
+ connect \$24 $ternary$libresoc.v:141180$6104_Y
+ connect \$26 $not$libresoc.v:141181$6105_Y
+ connect \$28 $not$libresoc.v:141182$6106_Y
connect \$22 \$24
connect \$32 \ldst_port0_addr_i
connect \ldst_port0_go_die_i$30 1'0
connect \reset_delay$next \reset_l_q_reset
connect \pick_i \$20
end
-attribute \src "libresoc.v:141770.1-141828.10"
+attribute \src "libresoc.v:141434.1-141492.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active"
attribute \generator "nMigen"
module \ld_active
- attribute \src "libresoc.v:141771.7-141771.20"
+ attribute \src "libresoc.v:141435.7-141435.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:141816.3-141824.6"
- wire $0\q_int$next[0:0]$6228
- attribute \src "libresoc.v:141814.3-141815.27"
+ attribute \src "libresoc.v:141480.3-141488.6"
+ wire $0\q_int$next[0:0]$6176
+ attribute \src "libresoc.v:141478.3-141479.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:141816.3-141824.6"
- wire $1\q_int$next[0:0]$6229
- attribute \src "libresoc.v:141793.7-141793.19"
+ attribute \src "libresoc.v:141480.3-141488.6"
+ wire $1\q_int$next[0:0]$6177
+ attribute \src "libresoc.v:141457.7-141457.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:141806.17-141806.96"
- wire $and$libresoc.v:141806$6218_Y
- attribute \src "libresoc.v:141811.17-141811.96"
- wire $and$libresoc.v:141811$6223_Y
- attribute \src "libresoc.v:141808.18-141808.99"
- wire $not$libresoc.v:141808$6220_Y
- attribute \src "libresoc.v:141810.17-141810.98"
- wire $not$libresoc.v:141810$6222_Y
- attribute \src "libresoc.v:141813.17-141813.98"
- wire $not$libresoc.v:141813$6225_Y
- attribute \src "libresoc.v:141807.18-141807.104"
- wire $or$libresoc.v:141807$6219_Y
- attribute \src "libresoc.v:141809.18-141809.105"
- wire $or$libresoc.v:141809$6221_Y
- attribute \src "libresoc.v:141812.17-141812.103"
- wire $or$libresoc.v:141812$6224_Y
+ attribute \src "libresoc.v:141470.17-141470.96"
+ wire $and$libresoc.v:141470$6166_Y
+ attribute \src "libresoc.v:141475.17-141475.96"
+ wire $and$libresoc.v:141475$6171_Y
+ attribute \src "libresoc.v:141472.18-141472.99"
+ wire $not$libresoc.v:141472$6168_Y
+ attribute \src "libresoc.v:141474.17-141474.98"
+ wire $not$libresoc.v:141474$6170_Y
+ attribute \src "libresoc.v:141477.17-141477.98"
+ wire $not$libresoc.v:141477$6173_Y
+ attribute \src "libresoc.v:141471.18-141471.104"
+ wire $or$libresoc.v:141471$6167_Y
+ attribute \src "libresoc.v:141473.18-141473.105"
+ wire $or$libresoc.v:141473$6169_Y
+ attribute \src "libresoc.v:141476.17-141476.103"
+ wire $or$libresoc.v:141476$6172_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:141771.7-141771.15"
+ attribute \src "libresoc.v:141435.7-141435.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_ld_active
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:141806$6218
+ cell $and $and$libresoc.v:141470$6166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:141806$6218_Y
+ connect \Y $and$libresoc.v:141470$6166_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:141811$6223
+ cell $and $and$libresoc.v:141475$6171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:141811$6223_Y
+ connect \Y $and$libresoc.v:141475$6171_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:141808$6220
+ cell $not $not$libresoc.v:141472$6168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_ld_active
- connect \Y $not$libresoc.v:141808$6220_Y
+ connect \Y $not$libresoc.v:141472$6168_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:141810$6222
+ cell $not $not$libresoc.v:141474$6170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_ld_active
- connect \Y $not$libresoc.v:141810$6222_Y
+ connect \Y $not$libresoc.v:141474$6170_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:141813$6225
+ cell $not $not$libresoc.v:141477$6173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_ld_active
- connect \Y $not$libresoc.v:141813$6225_Y
+ connect \Y $not$libresoc.v:141477$6173_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:141807$6219
+ cell $or $or$libresoc.v:141471$6167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_ld_active
- connect \Y $or$libresoc.v:141807$6219_Y
+ connect \Y $or$libresoc.v:141471$6167_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:141809$6221
+ cell $or $or$libresoc.v:141473$6169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_ld_active
connect \B \q_int
- connect \Y $or$libresoc.v:141809$6221_Y
+ connect \Y $or$libresoc.v:141473$6169_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:141812$6224
+ cell $or $or$libresoc.v:141476$6172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_ld_active
- connect \Y $or$libresoc.v:141812$6224_Y
+ connect \Y $or$libresoc.v:141476$6172_Y
end
- attribute \src "libresoc.v:141771.7-141771.20"
- process $proc$libresoc.v:141771$6230
+ attribute \src "libresoc.v:141435.7-141435.20"
+ process $proc$libresoc.v:141435$6178
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:141793.7-141793.19"
- process $proc$libresoc.v:141793$6231
+ attribute \src "libresoc.v:141457.7-141457.19"
+ process $proc$libresoc.v:141457$6179
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:141814.3-141815.27"
- process $proc$libresoc.v:141814$6226
+ attribute \src "libresoc.v:141478.3-141479.27"
+ process $proc$libresoc.v:141478$6174
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:141816.3-141824.6"
- process $proc$libresoc.v:141816$6227
+ attribute \src "libresoc.v:141480.3-141488.6"
+ process $proc$libresoc.v:141480$6175
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$6228 $1\q_int$next[0:0]$6229
- attribute \src "libresoc.v:141817.5-141817.29"
+ assign $0\q_int$next[0:0]$6176 $1\q_int$next[0:0]$6177
+ attribute \src "libresoc.v:141481.5-141481.29"
switch \initial
- attribute \src "libresoc.v:141817.9-141817.17"
+ attribute \src "libresoc.v:141481.9-141481.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$6229 1'0
+ assign $1\q_int$next[0:0]$6177 1'0
case
- assign $1\q_int$next[0:0]$6229 \$5
+ assign $1\q_int$next[0:0]$6177 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$6228
+ update \q_int$next $0\q_int$next[0:0]$6176
end
- connect \$9 $and$libresoc.v:141806$6218_Y
- connect \$11 $or$libresoc.v:141807$6219_Y
- connect \$13 $not$libresoc.v:141808$6220_Y
- connect \$15 $or$libresoc.v:141809$6221_Y
- connect \$1 $not$libresoc.v:141810$6222_Y
- connect \$3 $and$libresoc.v:141811$6223_Y
- connect \$5 $or$libresoc.v:141812$6224_Y
- connect \$7 $not$libresoc.v:141813$6225_Y
+ connect \$9 $and$libresoc.v:141470$6166_Y
+ connect \$11 $or$libresoc.v:141471$6167_Y
+ connect \$13 $not$libresoc.v:141472$6168_Y
+ connect \$15 $or$libresoc.v:141473$6169_Y
+ connect \$1 $not$libresoc.v:141474$6170_Y
+ connect \$3 $and$libresoc.v:141475$6171_Y
+ connect \$5 $or$libresoc.v:141476$6172_Y
+ connect \$7 $not$libresoc.v:141477$6173_Y
connect \qlq_ld_active \$15
connect \qn_ld_active \$13
connect \q_ld_active \$11
end
-attribute \src "libresoc.v:141832.1-143195.10"
+attribute \src "libresoc.v:141496.1-142859.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0"
attribute \generator "nMigen"
module \ldst0
- attribute \src "libresoc.v:142850.3-142858.6"
- wire $0\adr_l_r_adr$next[0:0]$6374
- attribute \src "libresoc.v:142732.3-142733.39"
+ attribute \src "libresoc.v:142514.3-142522.6"
+ wire $0\adr_l_r_adr$next[0:0]$6322
+ attribute \src "libresoc.v:142396.3-142397.39"
wire $0\adr_l_r_adr[0:0]
- attribute \src "libresoc.v:142678.3-142679.21"
+ attribute \src "libresoc.v:142342.3-142343.21"
wire $0\alu_ok[0:0]
- attribute \src "libresoc.v:143015.3-143024.6"
+ attribute \src "libresoc.v:142679.3-142688.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:143025.3-143034.6"
+ attribute \src "libresoc.v:142689.3-142698.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:143005.3-143014.6"
- wire width 64 $0\ea_r$next[63:0]$6462
- attribute \src "libresoc.v:142680.3-142681.25"
+ attribute \src "libresoc.v:142669.3-142678.6"
+ wire width 64 $0\ea_r$next[63:0]$6410
+ attribute \src "libresoc.v:142344.3-142345.25"
wire width 64 $0\ea_r[63:0]
- attribute \src "libresoc.v:141833.7-141833.20"
+ attribute \src "libresoc.v:141497.7-141497.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:143080.3-143099.6"
+ attribute \src "libresoc.v:142744.3-142763.6"
wire width 64 $0\ldd_o[63:0]
- attribute \src "libresoc.v:143044.3-143067.6"
+ attribute \src "libresoc.v:142708.3-142731.6"
wire width 64 $0\lddata_r[63:0]
- attribute \src "libresoc.v:142947.3-142956.6"
- wire width 64 $0\ldo_r$next[63:0]$6447
- attribute \src "libresoc.v:142688.3-142689.27"
+ attribute \src "libresoc.v:142611.3-142620.6"
+ wire width 64 $0\ldo_r$next[63:0]$6395
+ attribute \src "libresoc.v:142352.3-142353.27"
wire width 64 $0\ldo_r[63:0]
- attribute \src "libresoc.v:142676.3-142677.33"
+ attribute \src "libresoc.v:142340.3-142341.33"
wire width 96 $0\ldst_port0_addr_i[95:0]
- attribute \src "libresoc.v:143035.3-143043.6"
- wire $0\ldst_port0_addr_i_ok$next[0:0]$6467
- attribute \src "libresoc.v:142674.3-142675.57"
+ attribute \src "libresoc.v:142699.3-142707.6"
+ wire $0\ldst_port0_addr_i_ok$next[0:0]$6415
+ attribute \src "libresoc.v:142338.3-142339.57"
wire $0\ldst_port0_addr_i_ok[0:0]
- attribute \src "libresoc.v:143124.3-143135.6"
+ attribute \src "libresoc.v:142788.3-142799.6"
wire width 64 $0\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:142895.3-142903.6"
- wire $0\lsd_l_r_lsd$next[0:0]$6389
- attribute \src "libresoc.v:142722.3-142723.39"
+ attribute \src "libresoc.v:142559.3-142567.6"
+ wire $0\lsd_l_r_lsd$next[0:0]$6337
+ attribute \src "libresoc.v:142386.3-142387.39"
wire $0\lsd_l_r_lsd[0:0]
- attribute \src "libresoc.v:142823.3-142831.6"
- wire $0\opc_l_r_opc$next[0:0]$6365
- attribute \src "libresoc.v:142738.3-142739.39"
+ attribute \src "libresoc.v:142487.3-142495.6"
+ wire $0\opc_l_r_opc$next[0:0]$6313
+ attribute \src "libresoc.v:142402.3-142403.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:142814.3-142822.6"
- wire $0\opc_l_s_opc$next[0:0]$6362
- attribute \src "libresoc.v:142740.3-142741.39"
+ attribute \src "libresoc.v:142478.3-142486.6"
+ wire $0\opc_l_s_opc$next[0:0]$6310
+ attribute \src "libresoc.v:142404.3-142405.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__byte_reverse$next[0:0]$6392
- attribute \src "libresoc.v:142714.3-142715.57"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__byte_reverse$next[0:0]$6340
+ attribute \src "libresoc.v:142378.3-142379.57"
wire $0\oper_r__byte_reverse[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 4 $0\oper_r__data_len$next[3:0]$6393
- attribute \src "libresoc.v:142712.3-142713.49"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 4 $0\oper_r__data_len$next[3:0]$6341
+ attribute \src "libresoc.v:142376.3-142377.49"
wire width 4 $0\oper_r__data_len[3:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 14 $0\oper_r__fn_unit$next[13:0]$6394
- attribute \src "libresoc.v:142692.3-142693.47"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 14 $0\oper_r__fn_unit$next[13:0]$6342
+ attribute \src "libresoc.v:142356.3-142357.47"
wire width 14 $0\oper_r__fn_unit[13:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 64 $0\oper_r__imm_data__data$next[63:0]$6395
- attribute \src "libresoc.v:142694.3-142695.61"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 64 $0\oper_r__imm_data__data$next[63:0]$6343
+ attribute \src "libresoc.v:142358.3-142359.61"
wire width 64 $0\oper_r__imm_data__data[63:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__imm_data__ok$next[0:0]$6396
- attribute \src "libresoc.v:142696.3-142697.57"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__imm_data__ok$next[0:0]$6344
+ attribute \src "libresoc.v:142360.3-142361.57"
wire $0\oper_r__imm_data__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 32 $0\oper_r__insn$next[31:0]$6397
- attribute \src "libresoc.v:142720.3-142721.41"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 32 $0\oper_r__insn$next[31:0]$6345
+ attribute \src "libresoc.v:142384.3-142385.41"
wire width 32 $0\oper_r__insn[31:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 7 $0\oper_r__insn_type$next[6:0]$6398
- attribute \src "libresoc.v:142690.3-142691.51"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 7 $0\oper_r__insn_type$next[6:0]$6346
+ attribute \src "libresoc.v:142354.3-142355.51"
wire width 7 $0\oper_r__insn_type[6:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__is_32bit$next[0:0]$6399
- attribute \src "libresoc.v:142708.3-142709.49"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__is_32bit$next[0:0]$6347
+ attribute \src "libresoc.v:142372.3-142373.49"
wire $0\oper_r__is_32bit[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__is_signed$next[0:0]$6400
- attribute \src "libresoc.v:142710.3-142711.51"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__is_signed$next[0:0]$6348
+ attribute \src "libresoc.v:142374.3-142375.51"
wire $0\oper_r__is_signed[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 2 $0\oper_r__ldst_mode$next[1:0]$6401
- attribute \src "libresoc.v:142718.3-142719.51"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 2 $0\oper_r__ldst_mode$next[1:0]$6349
+ attribute \src "libresoc.v:142382.3-142383.51"
wire width 2 $0\oper_r__ldst_mode[1:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__oe__oe$next[0:0]$6402
- attribute \src "libresoc.v:142704.3-142705.45"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__oe__oe$next[0:0]$6350
+ attribute \src "libresoc.v:142368.3-142369.45"
wire $0\oper_r__oe__oe[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__oe__ok$next[0:0]$6403
- attribute \src "libresoc.v:142706.3-142707.45"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__oe__ok$next[0:0]$6351
+ attribute \src "libresoc.v:142370.3-142371.45"
wire $0\oper_r__oe__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__rc__ok$next[0:0]$6404
- attribute \src "libresoc.v:142702.3-142703.45"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__rc__ok$next[0:0]$6352
+ attribute \src "libresoc.v:142366.3-142367.45"
wire $0\oper_r__rc__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__rc__rc$next[0:0]$6405
- attribute \src "libresoc.v:142700.3-142701.45"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__rc__rc$next[0:0]$6353
+ attribute \src "libresoc.v:142364.3-142365.45"
wire $0\oper_r__rc__rc[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__sign_extend$next[0:0]$6406
- attribute \src "libresoc.v:142716.3-142717.55"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__sign_extend$next[0:0]$6354
+ attribute \src "libresoc.v:142380.3-142381.55"
wire $0\oper_r__sign_extend[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $0\oper_r__zero_a$next[0:0]$6407
- attribute \src "libresoc.v:142698.3-142699.45"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $0\oper_r__zero_a$next[0:0]$6355
+ attribute \src "libresoc.v:142362.3-142363.45"
wire $0\oper_r__zero_a[0:0]
- attribute \src "libresoc.v:142742.3-142743.28"
+ attribute \src "libresoc.v:142406.3-142407.28"
wire $0\p_st_go[0:0]
- attribute \src "libresoc.v:143068.3-143079.6"
+ attribute \src "libresoc.v:142732.3-142743.6"
wire width 64 $0\revnorev[63:0]
- attribute \src "libresoc.v:142841.3-142849.6"
- wire width 3 $0\src_l_r_src$next[2:0]$6371
- attribute \src "libresoc.v:142734.3-142735.39"
+ attribute \src "libresoc.v:142505.3-142513.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$6319
+ attribute \src "libresoc.v:142398.3-142399.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:142832.3-142840.6"
- wire width 3 $0\src_l_s_src$next[2:0]$6368
- attribute \src "libresoc.v:142736.3-142737.39"
+ attribute \src "libresoc.v:142496.3-142504.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$6316
+ attribute \src "libresoc.v:142400.3-142401.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:142957.3-142972.6"
- wire width 64 $0\src_r0$next[63:0]$6450
- attribute \src "libresoc.v:142686.3-142687.29"
+ attribute \src "libresoc.v:142621.3-142636.6"
+ wire width 64 $0\src_r0$next[63:0]$6398
+ attribute \src "libresoc.v:142350.3-142351.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:142973.3-142988.6"
- wire width 64 $0\src_r1$next[63:0]$6454
- attribute \src "libresoc.v:142684.3-142685.29"
+ attribute \src "libresoc.v:142637.3-142652.6"
+ wire width 64 $0\src_r1$next[63:0]$6402
+ attribute \src "libresoc.v:142348.3-142349.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:142989.3-143004.6"
- wire width 64 $0\src_r2$next[63:0]$6458
- attribute \src "libresoc.v:142682.3-142683.29"
+ attribute \src "libresoc.v:142653.3-142668.6"
+ wire width 64 $0\src_r2$next[63:0]$6406
+ attribute \src "libresoc.v:142346.3-142347.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:143100.3-143123.6"
+ attribute \src "libresoc.v:142764.3-142787.6"
wire width 64 $0\stdata_r[63:0]
- attribute \src "libresoc.v:142886.3-142894.6"
- wire $0\sto_l_r_sto$next[0:0]$6386
- attribute \src "libresoc.v:142724.3-142725.39"
+ attribute \src "libresoc.v:142550.3-142558.6"
+ wire $0\sto_l_r_sto$next[0:0]$6334
+ attribute \src "libresoc.v:142388.3-142389.39"
wire $0\sto_l_r_sto[0:0]
- attribute \src "libresoc.v:142877.3-142885.6"
- wire $0\upd_l_r_upd$next[0:0]$6383
- attribute \src "libresoc.v:142726.3-142727.39"
+ attribute \src "libresoc.v:142541.3-142549.6"
+ wire $0\upd_l_r_upd$next[0:0]$6331
+ attribute \src "libresoc.v:142390.3-142391.39"
wire $0\upd_l_r_upd[0:0]
- attribute \src "libresoc.v:142868.3-142876.6"
- wire $0\upd_l_s_upd$next[0:0]$6380
- attribute \src "libresoc.v:142728.3-142729.39"
+ attribute \src "libresoc.v:142532.3-142540.6"
+ wire $0\upd_l_s_upd$next[0:0]$6328
+ attribute \src "libresoc.v:142392.3-142393.39"
wire $0\upd_l_s_upd[0:0]
- attribute \src "libresoc.v:142859.3-142867.6"
- wire $0\wri_l_r_wri$next[0:0]$6377
- attribute \src "libresoc.v:142730.3-142731.39"
+ attribute \src "libresoc.v:142523.3-142531.6"
+ wire $0\wri_l_r_wri$next[0:0]$6325
+ attribute \src "libresoc.v:142394.3-142395.39"
wire $0\wri_l_r_wri[0:0]
- attribute \src "libresoc.v:142850.3-142858.6"
- wire $1\adr_l_r_adr$next[0:0]$6375
- attribute \src "libresoc.v:142029.7-142029.25"
+ attribute \src "libresoc.v:142514.3-142522.6"
+ wire $1\adr_l_r_adr$next[0:0]$6323
+ attribute \src "libresoc.v:141693.7-141693.25"
wire $1\adr_l_r_adr[0:0]
- attribute \src "libresoc.v:142043.7-142043.20"
+ attribute \src "libresoc.v:141707.7-141707.20"
wire $1\alu_ok[0:0]
- attribute \src "libresoc.v:143015.3-143024.6"
+ attribute \src "libresoc.v:142679.3-142688.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:143025.3-143034.6"
+ attribute \src "libresoc.v:142689.3-142698.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:143005.3-143014.6"
- wire width 64 $1\ea_r$next[63:0]$6463
- attribute \src "libresoc.v:142089.14-142089.41"
+ attribute \src "libresoc.v:142669.3-142678.6"
+ wire width 64 $1\ea_r$next[63:0]$6411
+ attribute \src "libresoc.v:141753.14-141753.41"
wire width 64 $1\ea_r[63:0]
- attribute \src "libresoc.v:143080.3-143099.6"
+ attribute \src "libresoc.v:142744.3-142763.6"
wire width 64 $1\ldd_o[63:0]
- attribute \src "libresoc.v:143044.3-143067.6"
+ attribute \src "libresoc.v:142708.3-142731.6"
wire width 64 $1\lddata_r[63:0]
- attribute \src "libresoc.v:142947.3-142956.6"
- wire width 64 $1\ldo_r$next[63:0]$6448
- attribute \src "libresoc.v:142119.14-142119.42"
+ attribute \src "libresoc.v:142611.3-142620.6"
+ wire width 64 $1\ldo_r$next[63:0]$6396
+ attribute \src "libresoc.v:141783.14-141783.42"
wire width 64 $1\ldo_r[63:0]
- attribute \src "libresoc.v:142124.14-142124.62"
+ attribute \src "libresoc.v:141788.14-141788.62"
wire width 96 $1\ldst_port0_addr_i[95:0]
- attribute \src "libresoc.v:143035.3-143043.6"
- wire $1\ldst_port0_addr_i_ok$next[0:0]$6468
- attribute \src "libresoc.v:142129.7-142129.34"
+ attribute \src "libresoc.v:142699.3-142707.6"
+ wire $1\ldst_port0_addr_i_ok$next[0:0]$6416
+ attribute \src "libresoc.v:141793.7-141793.34"
wire $1\ldst_port0_addr_i_ok[0:0]
- attribute \src "libresoc.v:143124.3-143135.6"
+ attribute \src "libresoc.v:142788.3-142799.6"
wire width 64 $1\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:142895.3-142903.6"
- wire $1\lsd_l_r_lsd$next[0:0]$6390
- attribute \src "libresoc.v:142178.7-142178.25"
+ attribute \src "libresoc.v:142559.3-142567.6"
+ wire $1\lsd_l_r_lsd$next[0:0]$6338
+ attribute \src "libresoc.v:141842.7-141842.25"
wire $1\lsd_l_r_lsd[0:0]
- attribute \src "libresoc.v:142823.3-142831.6"
- wire $1\opc_l_r_opc$next[0:0]$6366
- attribute \src "libresoc.v:142192.7-142192.25"
+ attribute \src "libresoc.v:142487.3-142495.6"
+ wire $1\opc_l_r_opc$next[0:0]$6314
+ attribute \src "libresoc.v:141856.7-141856.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:142814.3-142822.6"
- wire $1\opc_l_s_opc$next[0:0]$6363
- attribute \src "libresoc.v:142196.7-142196.25"
+ attribute \src "libresoc.v:142478.3-142486.6"
+ wire $1\opc_l_s_opc$next[0:0]$6311
+ attribute \src "libresoc.v:141860.7-141860.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__byte_reverse$next[0:0]$6408
- attribute \src "libresoc.v:142327.7-142327.34"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__byte_reverse$next[0:0]$6356
+ attribute \src "libresoc.v:141991.7-141991.34"
wire $1\oper_r__byte_reverse[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 4 $1\oper_r__data_len$next[3:0]$6409
- attribute \src "libresoc.v:142331.13-142331.36"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 4 $1\oper_r__data_len$next[3:0]$6357
+ attribute \src "libresoc.v:141995.13-141995.36"
wire width 4 $1\oper_r__data_len[3:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 14 $1\oper_r__fn_unit$next[13:0]$6410
- attribute \src "libresoc.v:142350.14-142350.40"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 14 $1\oper_r__fn_unit$next[13:0]$6358
+ attribute \src "libresoc.v:142014.14-142014.40"
wire width 14 $1\oper_r__fn_unit[13:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 64 $1\oper_r__imm_data__data$next[63:0]$6411
- attribute \src "libresoc.v:142354.14-142354.59"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 64 $1\oper_r__imm_data__data$next[63:0]$6359
+ attribute \src "libresoc.v:142018.14-142018.59"
wire width 64 $1\oper_r__imm_data__data[63:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__imm_data__ok$next[0:0]$6412
- attribute \src "libresoc.v:142358.7-142358.34"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__imm_data__ok$next[0:0]$6360
+ attribute \src "libresoc.v:142022.7-142022.34"
wire $1\oper_r__imm_data__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 32 $1\oper_r__insn$next[31:0]$6413
- attribute \src "libresoc.v:142362.14-142362.34"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 32 $1\oper_r__insn$next[31:0]$6361
+ attribute \src "libresoc.v:142026.14-142026.34"
wire width 32 $1\oper_r__insn[31:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 7 $1\oper_r__insn_type$next[6:0]$6414
- attribute \src "libresoc.v:142441.13-142441.38"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 7 $1\oper_r__insn_type$next[6:0]$6362
+ attribute \src "libresoc.v:142105.13-142105.38"
wire width 7 $1\oper_r__insn_type[6:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__is_32bit$next[0:0]$6415
- attribute \src "libresoc.v:142445.7-142445.30"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__is_32bit$next[0:0]$6363
+ attribute \src "libresoc.v:142109.7-142109.30"
wire $1\oper_r__is_32bit[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__is_signed$next[0:0]$6416
- attribute \src "libresoc.v:142449.7-142449.31"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__is_signed$next[0:0]$6364
+ attribute \src "libresoc.v:142113.7-142113.31"
wire $1\oper_r__is_signed[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 2 $1\oper_r__ldst_mode$next[1:0]$6417
- attribute \src "libresoc.v:142458.13-142458.37"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 2 $1\oper_r__ldst_mode$next[1:0]$6365
+ attribute \src "libresoc.v:142122.13-142122.37"
wire width 2 $1\oper_r__ldst_mode[1:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__oe__oe$next[0:0]$6418
- attribute \src "libresoc.v:142462.7-142462.28"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__oe__oe$next[0:0]$6366
+ attribute \src "libresoc.v:142126.7-142126.28"
wire $1\oper_r__oe__oe[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__oe__ok$next[0:0]$6419
- attribute \src "libresoc.v:142466.7-142466.28"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__oe__ok$next[0:0]$6367
+ attribute \src "libresoc.v:142130.7-142130.28"
wire $1\oper_r__oe__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__rc__ok$next[0:0]$6420
- attribute \src "libresoc.v:142470.7-142470.28"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__rc__ok$next[0:0]$6368
+ attribute \src "libresoc.v:142134.7-142134.28"
wire $1\oper_r__rc__ok[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__rc__rc$next[0:0]$6421
- attribute \src "libresoc.v:142474.7-142474.28"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__rc__rc$next[0:0]$6369
+ attribute \src "libresoc.v:142138.7-142138.28"
wire $1\oper_r__rc__rc[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__sign_extend$next[0:0]$6422
- attribute \src "libresoc.v:142478.7-142478.33"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__sign_extend$next[0:0]$6370
+ attribute \src "libresoc.v:142142.7-142142.33"
wire $1\oper_r__sign_extend[0:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $1\oper_r__zero_a$next[0:0]$6423
- attribute \src "libresoc.v:142482.7-142482.28"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $1\oper_r__zero_a$next[0:0]$6371
+ attribute \src "libresoc.v:142146.7-142146.28"
wire $1\oper_r__zero_a[0:0]
- attribute \src "libresoc.v:142486.7-142486.21"
+ attribute \src "libresoc.v:142150.7-142150.21"
wire $1\p_st_go[0:0]
- attribute \src "libresoc.v:143068.3-143079.6"
+ attribute \src "libresoc.v:142732.3-142743.6"
wire width 64 $1\revnorev[63:0]
- attribute \src "libresoc.v:142841.3-142849.6"
- wire width 3 $1\src_l_r_src$next[2:0]$6372
- attribute \src "libresoc.v:142528.13-142528.31"
+ attribute \src "libresoc.v:142505.3-142513.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$6320
+ attribute \src "libresoc.v:142192.13-142192.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:142832.3-142840.6"
- wire width 3 $1\src_l_s_src$next[2:0]$6369
- attribute \src "libresoc.v:142532.13-142532.31"
+ attribute \src "libresoc.v:142496.3-142504.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$6317
+ attribute \src "libresoc.v:142196.13-142196.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:142957.3-142972.6"
- wire width 64 $1\src_r0$next[63:0]$6451
- attribute \src "libresoc.v:142536.14-142536.43"
+ attribute \src "libresoc.v:142621.3-142636.6"
+ wire width 64 $1\src_r0$next[63:0]$6399
+ attribute \src "libresoc.v:142200.14-142200.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:142973.3-142988.6"
- wire width 64 $1\src_r1$next[63:0]$6455
- attribute \src "libresoc.v:142540.14-142540.43"
+ attribute \src "libresoc.v:142637.3-142652.6"
+ wire width 64 $1\src_r1$next[63:0]$6403
+ attribute \src "libresoc.v:142204.14-142204.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:142989.3-143004.6"
- wire width 64 $1\src_r2$next[63:0]$6459
- attribute \src "libresoc.v:142544.14-142544.43"
+ attribute \src "libresoc.v:142653.3-142668.6"
+ wire width 64 $1\src_r2$next[63:0]$6407
+ attribute \src "libresoc.v:142208.14-142208.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:143100.3-143123.6"
+ attribute \src "libresoc.v:142764.3-142787.6"
wire width 64 $1\stdata_r[63:0]
- attribute \src "libresoc.v:142886.3-142894.6"
- wire $1\sto_l_r_sto$next[0:0]$6387
- attribute \src "libresoc.v:142554.7-142554.25"
+ attribute \src "libresoc.v:142550.3-142558.6"
+ wire $1\sto_l_r_sto$next[0:0]$6335
+ attribute \src "libresoc.v:142218.7-142218.25"
wire $1\sto_l_r_sto[0:0]
- attribute \src "libresoc.v:142877.3-142885.6"
- wire $1\upd_l_r_upd$next[0:0]$6384
- attribute \src "libresoc.v:142564.7-142564.25"
+ attribute \src "libresoc.v:142541.3-142549.6"
+ wire $1\upd_l_r_upd$next[0:0]$6332
+ attribute \src "libresoc.v:142228.7-142228.25"
wire $1\upd_l_r_upd[0:0]
- attribute \src "libresoc.v:142868.3-142876.6"
- wire $1\upd_l_s_upd$next[0:0]$6381
- attribute \src "libresoc.v:142568.7-142568.25"
+ attribute \src "libresoc.v:142532.3-142540.6"
+ wire $1\upd_l_s_upd$next[0:0]$6329
+ attribute \src "libresoc.v:142232.7-142232.25"
wire $1\upd_l_s_upd[0:0]
- attribute \src "libresoc.v:142859.3-142867.6"
- wire $1\wri_l_r_wri$next[0:0]$6378
- attribute \src "libresoc.v:142578.7-142578.25"
+ attribute \src "libresoc.v:142523.3-142531.6"
+ wire $1\wri_l_r_wri$next[0:0]$6326
+ attribute \src "libresoc.v:142242.7-142242.25"
wire $1\wri_l_r_wri[0:0]
- attribute \src "libresoc.v:143080.3-143099.6"
+ attribute \src "libresoc.v:142744.3-142763.6"
wire width 64 $2\ldd_o[63:0]
- attribute \src "libresoc.v:143044.3-143067.6"
+ attribute \src "libresoc.v:142708.3-142731.6"
wire width 64 $2\lddata_r[63:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__byte_reverse$next[0:0]$6424
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 4 $2\oper_r__data_len$next[3:0]$6425
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 14 $2\oper_r__fn_unit$next[13:0]$6426
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 64 $2\oper_r__imm_data__data$next[63:0]$6427
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__imm_data__ok$next[0:0]$6428
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 32 $2\oper_r__insn$next[31:0]$6429
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 7 $2\oper_r__insn_type$next[6:0]$6430
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__is_32bit$next[0:0]$6431
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__is_signed$next[0:0]$6432
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 2 $2\oper_r__ldst_mode$next[1:0]$6433
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__oe__oe$next[0:0]$6434
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__oe__ok$next[0:0]$6435
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__rc__ok$next[0:0]$6436
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__rc__rc$next[0:0]$6437
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__sign_extend$next[0:0]$6438
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $2\oper_r__zero_a$next[0:0]$6439
- attribute \src "libresoc.v:142957.3-142972.6"
- wire width 64 $2\src_r0$next[63:0]$6452
- attribute \src "libresoc.v:142973.3-142988.6"
- wire width 64 $2\src_r1$next[63:0]$6456
- attribute \src "libresoc.v:142989.3-143004.6"
- wire width 64 $2\src_r2$next[63:0]$6460
- attribute \src "libresoc.v:143100.3-143123.6"
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__byte_reverse$next[0:0]$6372
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 4 $2\oper_r__data_len$next[3:0]$6373
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 14 $2\oper_r__fn_unit$next[13:0]$6374
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 64 $2\oper_r__imm_data__data$next[63:0]$6375
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__imm_data__ok$next[0:0]$6376
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 32 $2\oper_r__insn$next[31:0]$6377
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 7 $2\oper_r__insn_type$next[6:0]$6378
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__is_32bit$next[0:0]$6379
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__is_signed$next[0:0]$6380
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire width 2 $2\oper_r__ldst_mode$next[1:0]$6381
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__oe__oe$next[0:0]$6382
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__oe__ok$next[0:0]$6383
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__rc__ok$next[0:0]$6384
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__rc__rc$next[0:0]$6385
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__sign_extend$next[0:0]$6386
+ attribute \src "libresoc.v:142568.3-142610.6"
+ wire $2\oper_r__zero_a$next[0:0]$6387
+ attribute \src "libresoc.v:142621.3-142636.6"
+ wire width 64 $2\src_r0$next[63:0]$6400
+ attribute \src "libresoc.v:142637.3-142652.6"
+ wire width 64 $2\src_r1$next[63:0]$6404
+ attribute \src "libresoc.v:142653.3-142668.6"
+ wire width 64 $2\src_r2$next[63:0]$6408
+ attribute \src "libresoc.v:142764.3-142787.6"
wire width 64 $2\stdata_r[63:0]
- attribute \src "libresoc.v:142904.3-142946.6"
- wire width 64 $3\oper_r__imm_data__data$next[63:0]$6440
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $3\oper_r__imm_data__ok$next[0:0]$6441
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $3\oper_r__oe__oe$next[0:0]$6442
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $3\oper_r__oe__ok$next[0:0]$6443
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $3\oper_r__rc__ok$next[0:0]$6444
- attribute \src "libresoc.v:142904.3-142946.6"
- wire $3\oper_r__rc__rc$next[0:0]$6445
- attribute \src "libresoc.v:142660.18-142660.124"
- wire width 65 $add$libresoc.v:142660$6312_Y
- attribute \src "libresoc.v:142583.19-142583.118"
- wire $and$libresoc.v:142583$6232_Y
- attribute \src "libresoc.v:142584.19-142584.125"
- wire $and$libresoc.v:142584$6233_Y
- attribute \src "libresoc.v:142585.19-142585.120"
- wire $and$libresoc.v:142585$6234_Y
- attribute \src "libresoc.v:142586.19-142586.125"
- wire $and$libresoc.v:142586$6235_Y
- attribute \src "libresoc.v:142587.19-142587.118"
- wire $and$libresoc.v:142587$6236_Y
- attribute \src "libresoc.v:142589.19-142589.119"
- wire $and$libresoc.v:142589$6238_Y
- attribute \src "libresoc.v:142590.19-142590.123"
- wire $and$libresoc.v:142590$6239_Y
- attribute \src "libresoc.v:142591.19-142591.123"
- wire $and$libresoc.v:142591$6240_Y
- attribute \src "libresoc.v:142592.19-142592.120"
- wire $and$libresoc.v:142592$6241_Y
- attribute \src "libresoc.v:142593.19-142593.123"
- wire $and$libresoc.v:142593$6242_Y
- attribute \src "libresoc.v:142594.19-142594.119"
- wire $and$libresoc.v:142594$6243_Y
- attribute \src "libresoc.v:142595.19-142595.123"
- wire $and$libresoc.v:142595$6244_Y
- attribute \src "libresoc.v:142596.19-142596.125"
- wire $and$libresoc.v:142596$6245_Y
- attribute \src "libresoc.v:142598.19-142598.116"
- wire $and$libresoc.v:142598$6247_Y
- attribute \src "libresoc.v:142600.19-142600.120"
- wire $and$libresoc.v:142600$6249_Y
- attribute \src "libresoc.v:142601.19-142601.123"
- wire $and$libresoc.v:142601$6250_Y
- attribute \src "libresoc.v:142605.19-142605.125"
- wire $and$libresoc.v:142605$6254_Y
- attribute \src "libresoc.v:142606.19-142606.123"
- wire $and$libresoc.v:142606$6255_Y
- attribute \src "libresoc.v:142611.19-142611.116"
- wire $and$libresoc.v:142611$6260_Y
- attribute \src "libresoc.v:142613.19-142613.116"
- wire $and$libresoc.v:142613$6262_Y
- attribute \src "libresoc.v:142616.19-142616.118"
- wire $and$libresoc.v:142616$6265_Y
- attribute \src "libresoc.v:142618.19-142618.125"
- wire $and$libresoc.v:142618$6267_Y
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
wire \alu_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
wire \alu_valid
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire input 3 \cu_ad__go_i
wire \exc_$signal$184
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \exc_$signal$185
- attribute \src "libresoc.v:141833.7-141833.15"
+ attribute \src "libresoc.v:141497.7-141497.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110"
wire \ld_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \rst_l_s_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 27 \src1_i
+ wire width 64 input 29 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405"
wire width 64 \src1_or_z
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 28 \src2_i
+ wire width 64 input 27 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 64 \src2_or_imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 29 \src3_i
+ wire width 64 input 28 \src3_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 \src_l_q_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \wri_l_s_wri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
- cell $add $add$libresoc.v:142660$6312
+ cell $add $add$libresoc.v:142324$6260
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \src1_or_z
connect \B \src2_or_imm
- connect \Y $add$libresoc.v:142660$6312_Y
+ connect \Y $add$libresoc.v:142324$6260_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $and $and$libresoc.v:142583$6232
+ cell $and $and$libresoc.v:142247$6180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_valid
connect \B \$98
- connect \Y $and$libresoc.v:142583$6232_Y
+ connect \Y $and$libresoc.v:142247$6180_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $and $and$libresoc.v:142584$6233
+ cell $and $and$libresoc.v:142248$6181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_valid
connect \B \adr_l_q_adr
- connect \Y $and$libresoc.v:142584$6233_Y
+ connect \Y $and$libresoc.v:142248$6181_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $and $and$libresoc.v:142585$6234
+ cell $and $and$libresoc.v:142249$6182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$102
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142585$6234_Y
+ connect \Y $and$libresoc.v:142249$6182_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:142586$6235
+ cell $and $and$libresoc.v:142250$6183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sto_l_q_sto
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142586$6235_Y
+ connect \Y $and$libresoc.v:142250$6183_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:142587$6236
+ cell $and $and$libresoc.v:142251$6184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$106
connect \B \rd_done
- connect \Y $and$libresoc.v:142587$6236_Y
+ connect \Y $and$libresoc.v:142251$6184_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:142589$6238
+ cell $and $and$libresoc.v:142253$6186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$108
connect \B \op_is_st
- connect \Y $and$libresoc.v:142589$6238_Y
+ connect \Y $and$libresoc.v:142253$6186_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
- cell $and $and$libresoc.v:142590$6239
+ cell $and $and$libresoc.v:142254$6187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$110
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142590$6239_Y
+ connect \Y $and$libresoc.v:142254$6187_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:142591$6240
+ cell $and $and$libresoc.v:142255$6188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd_done
connect \B \wri_l_q_wri
- connect \Y $and$libresoc.v:142591$6240_Y
+ connect \Y $and$libresoc.v:142255$6188_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:142592$6241
+ cell $and $and$libresoc.v:142256$6189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$114
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142592$6241_Y
+ connect \Y $and$libresoc.v:142256$6189_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:142593$6242
+ cell $and $and$libresoc.v:142257$6190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$116
connect \B \lod_l_qn_lod
- connect \Y $and$libresoc.v:142593$6242_Y
+ connect \Y $and$libresoc.v:142257$6190_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:142594$6243
+ cell $and $and$libresoc.v:142258$6191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$118
connect \B \op_is_ld
- connect \Y $and$libresoc.v:142594$6243_Y
+ connect \Y $and$libresoc.v:142258$6191_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:142595$6244
+ cell $and $and$libresoc.v:142259$6192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$120
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142595$6244_Y
+ connect \Y $and$libresoc.v:142259$6192_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:142596$6245
+ cell $and $and$libresoc.v:142260$6193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd_l_q_upd
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142596$6245_Y
+ connect \Y $and$libresoc.v:142260$6193_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:142598$6247
+ cell $and $and$libresoc.v:142262$6195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$124
connect \B \$126
- connect \Y $and$libresoc.v:142598$6247_Y
+ connect \Y $and$libresoc.v:142262$6195_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:142600$6249
+ cell $and $and$libresoc.v:142264$6197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$128
connect \B \alu_valid
- connect \Y $and$libresoc.v:142600$6249_Y
+ connect \Y $and$libresoc.v:142264$6197_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:142601$6250
+ cell $and $and$libresoc.v:142265$6198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$130
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142601$6250_Y
+ connect \Y $and$libresoc.v:142265$6198_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:142605$6254
+ cell $and $and$libresoc.v:142269$6202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rst_l_q_rst
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142605$6254_Y
+ connect \Y $and$libresoc.v:142269$6202_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:142606$6255
+ cell $and $and$libresoc.v:142270$6203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$140
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142606$6255_Y
+ connect \Y $and$libresoc.v:142270$6203_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:142611$6260
+ cell $and $and$libresoc.v:142275$6208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$142
connect \B \$144
- connect \Y $and$libresoc.v:142611$6260_Y
+ connect \Y $and$libresoc.v:142275$6208_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463"
- cell $and $and$libresoc.v:142613$6262
+ cell $and $and$libresoc.v:142277$6210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$150
connect \B \$152
- connect \Y $and$libresoc.v:142613$6262_Y
+ connect \Y $and$libresoc.v:142277$6210_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $and $and$libresoc.v:142616$6265
+ cell $and $and$libresoc.v:142280$6213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$158
- connect \Y $and$libresoc.v:142616$6265_Y
+ connect \Y $and$libresoc.v:142280$6213_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
- cell $and $and$libresoc.v:142618$6267
+ cell $and $and$libresoc.v:142282$6215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$162
connect \B \cu_wr__go_i [1]
- connect \Y $and$libresoc.v:142618$6267_Y
+ connect \Y $and$libresoc.v:142282$6215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482"
- cell $and $and$libresoc.v:142621$6270
+ cell $and $and$libresoc.v:142285$6218
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { \cu_busy_o \cu_busy_o \cu_busy_o }
connect \B { 1'0 \$167 \op_is_ld }
- connect \Y $and$libresoc.v:142621$6270_Y
+ connect \Y $and$libresoc.v:142285$6218_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
- cell $and $and$libresoc.v:142622$6271
+ cell $and $and$libresoc.v:142286$6219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_ld
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142622$6271_Y
+ connect \Y $and$libresoc.v:142286$6219_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
- cell $and $and$libresoc.v:142623$6272
+ cell $and $and$libresoc.v:142287$6220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_st
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142623$6272_Y
+ connect \Y $and$libresoc.v:142287$6220_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494"
- cell $and $and$libresoc.v:142625$6275
+ cell $and $and$libresoc.v:142289$6223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_ok
connect \B \lsd_l_q_lsd
- connect \Y $and$libresoc.v:142625$6275_Y
+ connect \Y $and$libresoc.v:142289$6223_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312"
- cell $and $and$libresoc.v:142637$6289
+ cell $and $and$libresoc.v:142301$6237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_ld
connect \B \cu_ad__go_i
- connect \Y $and$libresoc.v:142637$6289_Y
+ connect \Y $and$libresoc.v:142301$6237_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313"
- cell $and $and$libresoc.v:142638$6290
+ cell $and $and$libresoc.v:142302$6238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_st
connect \B \cu_st__go_i
- connect \Y $and$libresoc.v:142638$6290_Y
+ connect \Y $and$libresoc.v:142302$6238_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $and $and$libresoc.v:142640$6292
+ cell $and $and$libresoc.v:142304$6240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_ok
connect \B \$30
- connect \Y $and$libresoc.v:142640$6292_Y
+ connect \Y $and$libresoc.v:142304$6240_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $and $and$libresoc.v:142642$6294
+ cell $and $and$libresoc.v:142306$6242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $and$libresoc.v:142642$6294_Y
+ connect \Y $and$libresoc.v:142306$6242_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $and $and$libresoc.v:142645$6297
+ cell $and $and$libresoc.v:142309$6245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \$41
- connect \Y $and$libresoc.v:142645$6297_Y
+ connect \Y $and$libresoc.v:142309$6245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $and $and$libresoc.v:142649$6301
+ cell $and $and$libresoc.v:142313$6249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$47
connect \B \$49
- connect \Y $and$libresoc.v:142649$6301_Y
+ connect \Y $and$libresoc.v:142313$6249_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367"
- cell $and $and$libresoc.v:142652$6304
+ cell $and $and$libresoc.v:142316$6252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \addr_ok
connect \B \op_is_st
- connect \Y $and$libresoc.v:142652$6304_Y
+ connect \Y $and$libresoc.v:142316$6252_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:142661$6313
+ cell $and $and$libresoc.v:142325$6261
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:142661$6313_Y
+ connect \Y $and$libresoc.v:142325$6261_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:142663$6315
+ cell $and $and$libresoc.v:142327$6263
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$76
connect \B \$78
- connect \Y $and$libresoc.v:142663$6315_Y
+ connect \Y $and$libresoc.v:142327$6263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:142665$6317
+ cell $and $and$libresoc.v:142329$6265
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$80
connect \B \$82
- connect \Y $and$libresoc.v:142665$6317_Y
+ connect \Y $and$libresoc.v:142329$6265_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
- cell $and $and$libresoc.v:142666$6318
+ cell $and $and$libresoc.v:142330$6266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src_l_q_src [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142666$6318_Y
+ connect \Y $and$libresoc.v:142330$6266_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
- cell $and $and$libresoc.v:142667$6319
+ cell $and $and$libresoc.v:142331$6267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$86
connect \B \op_is_st
- connect \Y $and$libresoc.v:142667$6319_Y
+ connect \Y $and$libresoc.v:142331$6267_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $and $and$libresoc.v:142672$6324
+ cell $and $and$libresoc.v:142336$6272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$92
- connect \Y $and$libresoc.v:142672$6324_Y
+ connect \Y $and$libresoc.v:142336$6272_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:142597$6246
+ cell $eq $eq$libresoc.v:142261$6194
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:142597$6246_Y
+ connect \Y $eq$libresoc.v:142261$6194_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:142617$6266
+ cell $eq $eq$libresoc.v:142281$6214
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:142617$6266_Y
+ connect \Y $eq$libresoc.v:142281$6214_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:142619$6268
+ cell $eq $eq$libresoc.v:142283$6216
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:142619$6268_Y
+ connect \Y $eq$libresoc.v:142283$6216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511"
- cell $eq $eq$libresoc.v:142630$6281
+ cell $eq $eq$libresoc.v:142294$6229
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__data_len
connect \B 2'10
- connect \Y $eq$libresoc.v:142630$6281_Y
+ connect \Y $eq$libresoc.v:142294$6229_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308"
- cell $eq $eq$libresoc.v:142635$6287
+ cell $eq $eq$libresoc.v:142299$6235
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__insn_type
connect \B 7'0100110
- connect \Y $eq$libresoc.v:142635$6287_Y
+ connect \Y $eq$libresoc.v:142299$6235_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309"
- cell $eq $eq$libresoc.v:142636$6288
+ cell $eq $eq$libresoc.v:142300$6236
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__insn_type
connect \B 7'0100101
- connect \Y $eq$libresoc.v:142636$6288_Y
+ connect \Y $eq$libresoc.v:142300$6236_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:142644$6296
+ cell $eq $eq$libresoc.v:142308$6244
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:142644$6296_Y
+ connect \Y $eq$libresoc.v:142308$6244_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:142648$6300
+ cell $eq $eq$libresoc.v:142312$6248
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:142648$6300_Y
+ connect \Y $eq$libresoc.v:142312$6248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
- cell $pos $extend$libresoc.v:142624$6273
+ cell $pos $extend$libresoc.v:142288$6221
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 96
connect \A \addr_r
- connect \Y $extend$libresoc.v:142624$6273_Y
+ connect \Y $extend$libresoc.v:142288$6221_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $extend$libresoc.v:142626$6276
+ cell $pos $extend$libresoc.v:142290$6224
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \ldst_port0_ld_data_o [7:0]
- connect \Y $extend$libresoc.v:142626$6276_Y
+ connect \Y $extend$libresoc.v:142290$6224_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $extend$libresoc.v:142631$6282
+ cell $pos $extend$libresoc.v:142295$6230
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \src_r2 [7:0]
- connect \Y $extend$libresoc.v:142631$6282_Y
+ connect \Y $extend$libresoc.v:142295$6230_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $not $not$libresoc.v:142609$6258
+ cell $not $not$libresoc.v:142273$6206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$147
- connect \Y $not$libresoc.v:142609$6258_Y
+ connect \Y $not$libresoc.v:142273$6206_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $not $not$libresoc.v:142614$6263
+ cell $not $not$libresoc.v:142278$6211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:142614$6263_Y
+ connect \Y $not$libresoc.v:142278$6211_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $not $not$libresoc.v:142639$6291
+ cell $not $not$libresoc.v:142303$6239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_valid
- connect \Y $not$libresoc.v:142639$6291_Y
+ connect \Y $not$libresoc.v:142303$6239_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $not $not$libresoc.v:142641$6293
+ cell $not $not$libresoc.v:142305$6241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rda_any
- connect \Y $not$libresoc.v:142641$6293_Y
+ connect \Y $not$libresoc.v:142305$6241_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $not $not$libresoc.v:142643$6295
+ cell $not $not$libresoc.v:142307$6243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:142643$6295_Y
+ connect \Y $not$libresoc.v:142307$6243_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $not $not$libresoc.v:142647$6299
+ cell $not $not$libresoc.v:142311$6247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:142647$6299_Y
+ connect \Y $not$libresoc.v:142311$6247_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $not $not$libresoc.v:142662$6314
+ cell $not $not$libresoc.v:142326$6262
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A { \oper_r__imm_data__ok \oper_r__zero_a }
- connect \Y $not$libresoc.v:142662$6314_Y
+ connect \Y $not$libresoc.v:142326$6262_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $not $not$libresoc.v:142664$6316
+ cell $not $not$libresoc.v:142328$6264
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:142664$6316_Y
+ connect \Y $not$libresoc.v:142328$6264_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $not $not$libresoc.v:142671$6323
+ cell $not $not$libresoc.v:142335$6271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$93
- connect \Y $not$libresoc.v:142671$6323_Y
+ connect \Y $not$libresoc.v:142335$6271_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $not $not$libresoc.v:142673$6325
+ cell $not $not$libresoc.v:142337$6273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_rd__rel_o [2]
- connect \Y $not$libresoc.v:142673$6325_Y
+ connect \Y $not$libresoc.v:142337$6273_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
- cell $or $or$libresoc.v:142588$6237
+ cell $or $or$libresoc.v:142252$6185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_done_o
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142588$6237_Y
+ connect \Y $or$libresoc.v:142252$6185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
- cell $or $or$libresoc.v:142599$6248
+ cell $or $or$libresoc.v:142263$6196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142599$6248_Y
+ connect \Y $or$libresoc.v:142263$6196_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:142602$6251
+ cell $or $or$libresoc.v:142266$6199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__go_i
connect \B \p_st_go
- connect \Y $or$libresoc.v:142602$6251_Y
+ connect \Y $or$libresoc.v:142266$6199_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:142603$6252
+ cell $or $or$libresoc.v:142267$6200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$134
connect \B \cu_wr__go_i [0]
- connect \Y $or$libresoc.v:142603$6252_Y
+ connect \Y $or$libresoc.v:142267$6200_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:142604$6253
+ cell $or $or$libresoc.v:142268$6201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$136
connect \B \cu_wr__go_i [1]
- connect \Y $or$libresoc.v:142604$6253_Y
+ connect \Y $or$libresoc.v:142268$6201_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $or $or$libresoc.v:142607$6256
+ cell $or $or$libresoc.v:142271$6204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o
connect \B \cu_wr__rel_o [0]
- connect \Y $or$libresoc.v:142607$6256_Y
+ connect \Y $or$libresoc.v:142271$6204_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $or $or$libresoc.v:142608$6257
+ cell $or $or$libresoc.v:142272$6205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$145
connect \B \cu_wr__rel_o [1]
- connect \Y $or$libresoc.v:142608$6257_Y
+ connect \Y $or$libresoc.v:142272$6205_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
- cell $or $or$libresoc.v:142610$6259
+ cell $or $or$libresoc.v:142274$6207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142610$6259_Y
+ connect \Y $or$libresoc.v:142274$6207_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463"
- cell $or $or$libresoc.v:142612$6261
+ cell $or $or$libresoc.v:142276$6209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lod_l_qn_lod
connect \B \op_is_st
- connect \Y $or$libresoc.v:142612$6261_Y
+ connect \Y $or$libresoc.v:142276$6209_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $or $or$libresoc.v:142615$6264
+ cell $or $or$libresoc.v:142279$6212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$156
connect \B \op_is_ld
- connect \Y $or$libresoc.v:142615$6264_Y
+ connect \Y $or$libresoc.v:142279$6212_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
- cell $or $or$libresoc.v:142620$6269
+ cell $or $or$libresoc.v:142284$6217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__go_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142620$6269_Y
+ connect \Y $or$libresoc.v:142284$6217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
- cell $or $or$libresoc.v:142628$6279
+ cell $or $or$libresoc.v:142292$6227
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:142628$6279_Y
+ connect \Y $or$libresoc.v:142292$6227_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
- cell $or $or$libresoc.v:142634$6286
+ cell $or $or$libresoc.v:142298$6234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_ad__go_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142634$6286_Y
+ connect \Y $or$libresoc.v:142298$6234_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $or $or$libresoc.v:142646$6298
+ cell $or $or$libresoc.v:142310$6246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$43
- connect \Y $or$libresoc.v:142646$6298_Y
+ connect \Y $or$libresoc.v:142310$6246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $or $or$libresoc.v:142650$6302
+ cell $or $or$libresoc.v:142314$6250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$51
- connect \Y $or$libresoc.v:142650$6302_Y
+ connect \Y $or$libresoc.v:142314$6250_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360"
- cell $or $or$libresoc.v:142651$6303
+ cell $or $or$libresoc.v:142315$6251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reset_w
connect \B { \$45 \$53 }
- connect \Y $or$libresoc.v:142651$6303_Y
+ connect \Y $or$libresoc.v:142315$6251_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
- cell $or $or$libresoc.v:142653$6305
+ cell $or $or$libresoc.v:142317$6253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \reset_s
connect \B \p_st_go
- connect \Y $or$libresoc.v:142653$6305_Y
+ connect \Y $or$libresoc.v:142317$6253_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372"
- cell $or $or$libresoc.v:142654$6306
+ cell $or $or$libresoc.v:142318$6254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \reset_s
connect \B \p_st_go
- connect \Y $or$libresoc.v:142654$6306_Y
+ connect \Y $or$libresoc.v:142318$6254_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372"
- cell $or $or$libresoc.v:142655$6307
+ cell $or $or$libresoc.v:142319$6255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$61
connect \B \ld_ok
- connect \Y $or$libresoc.v:142655$6307_Y
+ connect \Y $or$libresoc.v:142319$6255_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
- cell $or $or$libresoc.v:142668$6320
+ cell $or $or$libresoc.v:142332$6268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142668$6320_Y
+ connect \Y $or$libresoc.v:142332$6268_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
- cell $or $or$libresoc.v:142669$6321
+ cell $or $or$libresoc.v:142333$6269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_rd__go_i [0]
connect \B \cu_rd__go_i [1]
- connect \Y $or$libresoc.v:142669$6321_Y
+ connect \Y $or$libresoc.v:142333$6269_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $or $or$libresoc.v:142670$6322
+ cell $or $or$libresoc.v:142334$6270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_rd__rel_o [0]
connect \B \cu_rd__rel_o [1]
- connect \Y $or$libresoc.v:142670$6322_Y
+ connect \Y $or$libresoc.v:142334$6270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
- cell $pos $pos$libresoc.v:142624$6274
+ cell $pos $pos$libresoc.v:142288$6222
parameter \A_SIGNED 0
parameter \A_WIDTH 96
parameter \Y_WIDTH 96
- connect \A $extend$libresoc.v:142624$6273_Y
- connect \Y $pos$libresoc.v:142624$6274_Y
+ connect \A $extend$libresoc.v:142288$6221_Y
+ connect \Y $pos$libresoc.v:142288$6222_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142626$6277
+ cell $pos $pos$libresoc.v:142290$6225
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:142626$6276_Y
- connect \Y $pos$libresoc.v:142626$6277_Y
+ connect \A $extend$libresoc.v:142290$6224_Y
+ connect \Y $pos$libresoc.v:142290$6225_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142627$6278
+ cell $pos $pos$libresoc.v:142291$6226
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] }
- connect \Y $pos$libresoc.v:142627$6278_Y
+ connect \Y $pos$libresoc.v:142291$6226_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142629$6280
+ cell $pos $pos$libresoc.v:142293$6228
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] }
- connect \Y $pos$libresoc.v:142629$6280_Y
+ connect \Y $pos$libresoc.v:142293$6228_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142631$6283
+ cell $pos $pos$libresoc.v:142295$6231
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:142631$6282_Y
- connect \Y $pos$libresoc.v:142631$6283_Y
+ connect \A $extend$libresoc.v:142295$6230_Y
+ connect \Y $pos$libresoc.v:142295$6231_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142632$6284
+ cell $pos $pos$libresoc.v:142296$6232
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] }
- connect \Y $pos$libresoc.v:142632$6284_Y
+ connect \Y $pos$libresoc.v:142296$6232_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:142633$6285
+ cell $pos $pos$libresoc.v:142297$6233
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] }
- connect \Y $pos$libresoc.v:142633$6285_Y
+ connect \Y $pos$libresoc.v:142297$6233_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:142656$6308
+ cell $mux $ternary$libresoc.v:142320$6256
parameter \WIDTH 64
connect \A \ldo_r
connect \B \ldd_o
connect \S \ld_ok
- connect \Y $ternary$libresoc.v:142656$6308_Y
+ connect \Y $ternary$libresoc.v:142320$6256_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:142657$6309
+ cell $mux $ternary$libresoc.v:142321$6257
parameter \WIDTH 64
connect \A \ea_r
connect \B \alu_o
connect \S \alu_l_q_alu
- connect \Y $ternary$libresoc.v:142657$6309_Y
+ connect \Y $ternary$libresoc.v:142321$6257_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406"
- cell $mux $ternary$libresoc.v:142658$6310
+ cell $mux $ternary$libresoc.v:142322$6258
parameter \WIDTH 64
connect \A \src_r0
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \oper_r__zero_a
- connect \Y $ternary$libresoc.v:142658$6310_Y
+ connect \Y $ternary$libresoc.v:142322$6258_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
- cell $mux $ternary$libresoc.v:142659$6311
+ cell $mux $ternary$libresoc.v:142323$6259
parameter \WIDTH 64
connect \A \src_r1
connect \B \oper_r__imm_data__data
connect \S \oper_r__imm_data__ok
- connect \Y $ternary$libresoc.v:142659$6311_Y
+ connect \Y $ternary$libresoc.v:142323$6259_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142744.9-142750.4"
+ attribute \src "libresoc.v:142408.9-142414.4"
cell \adr_l \adr_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_adr \adr_l_s_adr
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142751.15-142757.4"
+ attribute \src "libresoc.v:142415.15-142421.4"
cell \alu_l$128 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142758.9-142764.4"
+ attribute \src "libresoc.v:142422.9-142428.4"
cell \lod_l \lod_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_lod \lod_l_s_lod
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142765.9-142771.4"
+ attribute \src "libresoc.v:142429.9-142435.4"
cell \lsd_l \lsd_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_lsd \lsd_l_s_lsd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142772.15-142778.4"
+ attribute \src "libresoc.v:142436.15-142442.4"
cell \opc_l$126 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142779.15-142785.4"
+ attribute \src "libresoc.v:142443.15-142449.4"
cell \rst_l$129 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142786.15-142792.4"
+ attribute \src "libresoc.v:142450.15-142456.4"
cell \src_l$127 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_src \src_l_s_src
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142793.9-142799.4"
+ attribute \src "libresoc.v:142457.9-142463.4"
cell \sto_l \sto_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_sto \sto_l_s_sto
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142800.9-142806.4"
+ attribute \src "libresoc.v:142464.9-142470.4"
cell \upd_l \upd_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_upd \upd_l_s_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142807.9-142813.4"
+ attribute \src "libresoc.v:142471.9-142477.4"
cell \wri_l \wri_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_wri \wri_l_r_wri
connect \s_wri \wri_l_s_wri
end
- attribute \src "libresoc.v:141833.7-141833.20"
- process $proc$libresoc.v:141833$6474
+ attribute \src "libresoc.v:141497.7-141497.20"
+ process $proc$libresoc.v:141497$6422
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:142029.7-142029.25"
- process $proc$libresoc.v:142029$6475
+ attribute \src "libresoc.v:141693.7-141693.25"
+ process $proc$libresoc.v:141693$6423
assign { } { }
assign $1\adr_l_r_adr[0:0] 1'1
sync always
sync init
update \adr_l_r_adr $1\adr_l_r_adr[0:0]
end
- attribute \src "libresoc.v:142043.7-142043.20"
- process $proc$libresoc.v:142043$6476
+ attribute \src "libresoc.v:141707.7-141707.20"
+ process $proc$libresoc.v:141707$6424
assign { } { }
assign $1\alu_ok[0:0] 1'0
sync always
sync init
update \alu_ok $1\alu_ok[0:0]
end
- attribute \src "libresoc.v:142089.14-142089.41"
- process $proc$libresoc.v:142089$6477
+ attribute \src "libresoc.v:141753.14-141753.41"
+ process $proc$libresoc.v:141753$6425
assign { } { }
assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ea_r $1\ea_r[63:0]
end
- attribute \src "libresoc.v:142119.14-142119.42"
- process $proc$libresoc.v:142119$6478
+ attribute \src "libresoc.v:141783.14-141783.42"
+ process $proc$libresoc.v:141783$6426
assign { } { }
assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ldo_r $1\ldo_r[63:0]
end
- attribute \src "libresoc.v:142124.14-142124.62"
- process $proc$libresoc.v:142124$6479
+ attribute \src "libresoc.v:141788.14-141788.62"
+ process $proc$libresoc.v:141788$6427
assign { } { }
assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0]
end
- attribute \src "libresoc.v:142129.7-142129.34"
- process $proc$libresoc.v:142129$6480
+ attribute \src "libresoc.v:141793.7-141793.34"
+ process $proc$libresoc.v:141793$6428
assign { } { }
assign $1\ldst_port0_addr_i_ok[0:0] 1'0
sync always
sync init
update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0]
end
- attribute \src "libresoc.v:142178.7-142178.25"
- process $proc$libresoc.v:142178$6481
+ attribute \src "libresoc.v:141842.7-141842.25"
+ process $proc$libresoc.v:141842$6429
assign { } { }
assign $1\lsd_l_r_lsd[0:0] 1'1
sync always
sync init
update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0]
end
- attribute \src "libresoc.v:142192.7-142192.25"
- process $proc$libresoc.v:142192$6482
+ attribute \src "libresoc.v:141856.7-141856.25"
+ process $proc$libresoc.v:141856$6430
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:142196.7-142196.25"
- process $proc$libresoc.v:142196$6483
+ attribute \src "libresoc.v:141860.7-141860.25"
+ process $proc$libresoc.v:141860$6431
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:142327.7-142327.34"
- process $proc$libresoc.v:142327$6484
+ attribute \src "libresoc.v:141991.7-141991.34"
+ process $proc$libresoc.v:141991$6432
assign { } { }
assign $1\oper_r__byte_reverse[0:0] 1'0
sync always
sync init
update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0]
end
- attribute \src "libresoc.v:142331.13-142331.36"
- process $proc$libresoc.v:142331$6485
+ attribute \src "libresoc.v:141995.13-141995.36"
+ process $proc$libresoc.v:141995$6433
assign { } { }
assign $1\oper_r__data_len[3:0] 4'0000
sync always
sync init
update \oper_r__data_len $1\oper_r__data_len[3:0]
end
- attribute \src "libresoc.v:142350.14-142350.40"
- process $proc$libresoc.v:142350$6486
+ attribute \src "libresoc.v:142014.14-142014.40"
+ process $proc$libresoc.v:142014$6434
assign { } { }
assign $1\oper_r__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \oper_r__fn_unit $1\oper_r__fn_unit[13:0]
end
- attribute \src "libresoc.v:142354.14-142354.59"
- process $proc$libresoc.v:142354$6487
+ attribute \src "libresoc.v:142018.14-142018.59"
+ process $proc$libresoc.v:142018$6435
assign { } { }
assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0]
end
- attribute \src "libresoc.v:142358.7-142358.34"
- process $proc$libresoc.v:142358$6488
+ attribute \src "libresoc.v:142022.7-142022.34"
+ process $proc$libresoc.v:142022$6436
assign { } { }
assign $1\oper_r__imm_data__ok[0:0] 1'0
sync always
sync init
update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:142362.14-142362.34"
- process $proc$libresoc.v:142362$6489
+ attribute \src "libresoc.v:142026.14-142026.34"
+ process $proc$libresoc.v:142026$6437
assign { } { }
assign $1\oper_r__insn[31:0] 0
sync always
sync init
update \oper_r__insn $1\oper_r__insn[31:0]
end
- attribute \src "libresoc.v:142441.13-142441.38"
- process $proc$libresoc.v:142441$6490
+ attribute \src "libresoc.v:142105.13-142105.38"
+ process $proc$libresoc.v:142105$6438
assign { } { }
assign $1\oper_r__insn_type[6:0] 7'0000000
sync always
sync init
update \oper_r__insn_type $1\oper_r__insn_type[6:0]
end
- attribute \src "libresoc.v:142445.7-142445.30"
- process $proc$libresoc.v:142445$6491
+ attribute \src "libresoc.v:142109.7-142109.30"
+ process $proc$libresoc.v:142109$6439
assign { } { }
assign $1\oper_r__is_32bit[0:0] 1'0
sync always
sync init
update \oper_r__is_32bit $1\oper_r__is_32bit[0:0]
end
- attribute \src "libresoc.v:142449.7-142449.31"
- process $proc$libresoc.v:142449$6492
+ attribute \src "libresoc.v:142113.7-142113.31"
+ process $proc$libresoc.v:142113$6440
assign { } { }
assign $1\oper_r__is_signed[0:0] 1'0
sync always
sync init
update \oper_r__is_signed $1\oper_r__is_signed[0:0]
end
- attribute \src "libresoc.v:142458.13-142458.37"
- process $proc$libresoc.v:142458$6493
+ attribute \src "libresoc.v:142122.13-142122.37"
+ process $proc$libresoc.v:142122$6441
assign { } { }
assign $1\oper_r__ldst_mode[1:0] 2'00
sync always
sync init
update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0]
end
- attribute \src "libresoc.v:142462.7-142462.28"
- process $proc$libresoc.v:142462$6494
+ attribute \src "libresoc.v:142126.7-142126.28"
+ process $proc$libresoc.v:142126$6442
assign { } { }
assign $1\oper_r__oe__oe[0:0] 1'0
sync always
sync init
update \oper_r__oe__oe $1\oper_r__oe__oe[0:0]
end
- attribute \src "libresoc.v:142466.7-142466.28"
- process $proc$libresoc.v:142466$6495
+ attribute \src "libresoc.v:142130.7-142130.28"
+ process $proc$libresoc.v:142130$6443
assign { } { }
assign $1\oper_r__oe__ok[0:0] 1'0
sync always
sync init
update \oper_r__oe__ok $1\oper_r__oe__ok[0:0]
end
- attribute \src "libresoc.v:142470.7-142470.28"
- process $proc$libresoc.v:142470$6496
+ attribute \src "libresoc.v:142134.7-142134.28"
+ process $proc$libresoc.v:142134$6444
assign { } { }
assign $1\oper_r__rc__ok[0:0] 1'0
sync always
sync init
update \oper_r__rc__ok $1\oper_r__rc__ok[0:0]
end
- attribute \src "libresoc.v:142474.7-142474.28"
- process $proc$libresoc.v:142474$6497
+ attribute \src "libresoc.v:142138.7-142138.28"
+ process $proc$libresoc.v:142138$6445
assign { } { }
assign $1\oper_r__rc__rc[0:0] 1'0
sync always
sync init
update \oper_r__rc__rc $1\oper_r__rc__rc[0:0]
end
- attribute \src "libresoc.v:142478.7-142478.33"
- process $proc$libresoc.v:142478$6498
+ attribute \src "libresoc.v:142142.7-142142.33"
+ process $proc$libresoc.v:142142$6446
assign { } { }
assign $1\oper_r__sign_extend[0:0] 1'0
sync always
sync init
update \oper_r__sign_extend $1\oper_r__sign_extend[0:0]
end
- attribute \src "libresoc.v:142482.7-142482.28"
- process $proc$libresoc.v:142482$6499
+ attribute \src "libresoc.v:142146.7-142146.28"
+ process $proc$libresoc.v:142146$6447
assign { } { }
assign $1\oper_r__zero_a[0:0] 1'0
sync always
sync init
update \oper_r__zero_a $1\oper_r__zero_a[0:0]
end
- attribute \src "libresoc.v:142486.7-142486.21"
- process $proc$libresoc.v:142486$6500
+ attribute \src "libresoc.v:142150.7-142150.21"
+ process $proc$libresoc.v:142150$6448
assign { } { }
assign $1\p_st_go[0:0] 1'0
sync always
sync init
update \p_st_go $1\p_st_go[0:0]
end
- attribute \src "libresoc.v:142528.13-142528.31"
- process $proc$libresoc.v:142528$6501
+ attribute \src "libresoc.v:142192.13-142192.31"
+ process $proc$libresoc.v:142192$6449
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:142532.13-142532.31"
- process $proc$libresoc.v:142532$6502
+ attribute \src "libresoc.v:142196.13-142196.31"
+ process $proc$libresoc.v:142196$6450
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:142536.14-142536.43"
- process $proc$libresoc.v:142536$6503
+ attribute \src "libresoc.v:142200.14-142200.43"
+ process $proc$libresoc.v:142200$6451
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:142540.14-142540.43"
- process $proc$libresoc.v:142540$6504
+ attribute \src "libresoc.v:142204.14-142204.43"
+ process $proc$libresoc.v:142204$6452
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:142544.14-142544.43"
- process $proc$libresoc.v:142544$6505
+ attribute \src "libresoc.v:142208.14-142208.43"
+ process $proc$libresoc.v:142208$6453
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:142554.7-142554.25"
- process $proc$libresoc.v:142554$6506
+ attribute \src "libresoc.v:142218.7-142218.25"
+ process $proc$libresoc.v:142218$6454
assign { } { }
assign $1\sto_l_r_sto[0:0] 1'1
sync always
sync init
update \sto_l_r_sto $1\sto_l_r_sto[0:0]
end
- attribute \src "libresoc.v:142564.7-142564.25"
- process $proc$libresoc.v:142564$6507
+ attribute \src "libresoc.v:142228.7-142228.25"
+ process $proc$libresoc.v:142228$6455
assign { } { }
assign $1\upd_l_r_upd[0:0] 1'1
sync always
sync init
update \upd_l_r_upd $1\upd_l_r_upd[0:0]
end
- attribute \src "libresoc.v:142568.7-142568.25"
- process $proc$libresoc.v:142568$6508
+ attribute \src "libresoc.v:142232.7-142232.25"
+ process $proc$libresoc.v:142232$6456
assign { } { }
assign $1\upd_l_s_upd[0:0] 1'0
sync always
sync init
update \upd_l_s_upd $1\upd_l_s_upd[0:0]
end
- attribute \src "libresoc.v:142578.7-142578.25"
- process $proc$libresoc.v:142578$6509
+ attribute \src "libresoc.v:142242.7-142242.25"
+ process $proc$libresoc.v:142242$6457
assign { } { }
assign $1\wri_l_r_wri[0:0] 1'1
sync always
sync init
update \wri_l_r_wri $1\wri_l_r_wri[0:0]
end
- attribute \src "libresoc.v:142674.3-142675.57"
- process $proc$libresoc.v:142674$6326
+ attribute \src "libresoc.v:142338.3-142339.57"
+ process $proc$libresoc.v:142338$6274
assign { } { }
assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next
sync posedge \coresync_clk
update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0]
end
- attribute \src "libresoc.v:142676.3-142677.33"
- process $proc$libresoc.v:142676$6327
+ attribute \src "libresoc.v:142340.3-142341.33"
+ process $proc$libresoc.v:142340$6275
assign { } { }
assign $0\ldst_port0_addr_i[95:0] \$175
sync posedge \coresync_clk
update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0]
end
- attribute \src "libresoc.v:142678.3-142679.21"
- process $proc$libresoc.v:142678$6328
+ attribute \src "libresoc.v:142342.3-142343.21"
+ process $proc$libresoc.v:142342$6276
assign { } { }
assign $0\alu_ok[0:0] \$96
sync posedge \coresync_clk
update \alu_ok $0\alu_ok[0:0]
end
- attribute \src "libresoc.v:142680.3-142681.25"
- process $proc$libresoc.v:142680$6329
+ attribute \src "libresoc.v:142344.3-142345.25"
+ process $proc$libresoc.v:142344$6277
assign { } { }
assign $0\ea_r[63:0] \ea_r$next
sync posedge \coresync_clk
update \ea_r $0\ea_r[63:0]
end
- attribute \src "libresoc.v:142682.3-142683.29"
- process $proc$libresoc.v:142682$6330
+ attribute \src "libresoc.v:142346.3-142347.29"
+ process $proc$libresoc.v:142346$6278
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:142684.3-142685.29"
- process $proc$libresoc.v:142684$6331
+ attribute \src "libresoc.v:142348.3-142349.29"
+ process $proc$libresoc.v:142348$6279
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:142686.3-142687.29"
- process $proc$libresoc.v:142686$6332
+ attribute \src "libresoc.v:142350.3-142351.29"
+ process $proc$libresoc.v:142350$6280
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:142688.3-142689.27"
- process $proc$libresoc.v:142688$6333
+ attribute \src "libresoc.v:142352.3-142353.27"
+ process $proc$libresoc.v:142352$6281
assign { } { }
assign $0\ldo_r[63:0] \ldo_r$next
sync posedge \coresync_clk
update \ldo_r $0\ldo_r[63:0]
end
- attribute \src "libresoc.v:142690.3-142691.51"
- process $proc$libresoc.v:142690$6334
+ attribute \src "libresoc.v:142354.3-142355.51"
+ process $proc$libresoc.v:142354$6282
assign { } { }
assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next
sync posedge \coresync_clk
update \oper_r__insn_type $0\oper_r__insn_type[6:0]
end
- attribute \src "libresoc.v:142692.3-142693.47"
- process $proc$libresoc.v:142692$6335
+ attribute \src "libresoc.v:142356.3-142357.47"
+ process $proc$libresoc.v:142356$6283
assign { } { }
assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next
sync posedge \coresync_clk
update \oper_r__fn_unit $0\oper_r__fn_unit[13:0]
end
- attribute \src "libresoc.v:142694.3-142695.61"
- process $proc$libresoc.v:142694$6336
+ attribute \src "libresoc.v:142358.3-142359.61"
+ process $proc$libresoc.v:142358$6284
assign { } { }
assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next
sync posedge \coresync_clk
update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0]
end
- attribute \src "libresoc.v:142696.3-142697.57"
- process $proc$libresoc.v:142696$6337
+ attribute \src "libresoc.v:142360.3-142361.57"
+ process $proc$libresoc.v:142360$6285
assign { } { }
assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next
sync posedge \coresync_clk
update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:142698.3-142699.45"
- process $proc$libresoc.v:142698$6338
+ attribute \src "libresoc.v:142362.3-142363.45"
+ process $proc$libresoc.v:142362$6286
assign { } { }
assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next
sync posedge \coresync_clk
update \oper_r__zero_a $0\oper_r__zero_a[0:0]
end
- attribute \src "libresoc.v:142700.3-142701.45"
- process $proc$libresoc.v:142700$6339
+ attribute \src "libresoc.v:142364.3-142365.45"
+ process $proc$libresoc.v:142364$6287
assign { } { }
assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next
sync posedge \coresync_clk
update \oper_r__rc__rc $0\oper_r__rc__rc[0:0]
end
- attribute \src "libresoc.v:142702.3-142703.45"
- process $proc$libresoc.v:142702$6340
+ attribute \src "libresoc.v:142366.3-142367.45"
+ process $proc$libresoc.v:142366$6288
assign { } { }
assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next
sync posedge \coresync_clk
update \oper_r__rc__ok $0\oper_r__rc__ok[0:0]
end
- attribute \src "libresoc.v:142704.3-142705.45"
- process $proc$libresoc.v:142704$6341
+ attribute \src "libresoc.v:142368.3-142369.45"
+ process $proc$libresoc.v:142368$6289
assign { } { }
assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next
sync posedge \coresync_clk
update \oper_r__oe__oe $0\oper_r__oe__oe[0:0]
end
- attribute \src "libresoc.v:142706.3-142707.45"
- process $proc$libresoc.v:142706$6342
+ attribute \src "libresoc.v:142370.3-142371.45"
+ process $proc$libresoc.v:142370$6290
assign { } { }
assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next
sync posedge \coresync_clk
update \oper_r__oe__ok $0\oper_r__oe__ok[0:0]
end
- attribute \src "libresoc.v:142708.3-142709.49"
- process $proc$libresoc.v:142708$6343
+ attribute \src "libresoc.v:142372.3-142373.49"
+ process $proc$libresoc.v:142372$6291
assign { } { }
assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next
sync posedge \coresync_clk
update \oper_r__is_32bit $0\oper_r__is_32bit[0:0]
end
- attribute \src "libresoc.v:142710.3-142711.51"
- process $proc$libresoc.v:142710$6344
+ attribute \src "libresoc.v:142374.3-142375.51"
+ process $proc$libresoc.v:142374$6292
assign { } { }
assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next
sync posedge \coresync_clk
update \oper_r__is_signed $0\oper_r__is_signed[0:0]
end
- attribute \src "libresoc.v:142712.3-142713.49"
- process $proc$libresoc.v:142712$6345
+ attribute \src "libresoc.v:142376.3-142377.49"
+ process $proc$libresoc.v:142376$6293
assign { } { }
assign $0\oper_r__data_len[3:0] \oper_r__data_len$next
sync posedge \coresync_clk
update \oper_r__data_len $0\oper_r__data_len[3:0]
end
- attribute \src "libresoc.v:142714.3-142715.57"
- process $proc$libresoc.v:142714$6346
+ attribute \src "libresoc.v:142378.3-142379.57"
+ process $proc$libresoc.v:142378$6294
assign { } { }
assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next
sync posedge \coresync_clk
update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0]
end
- attribute \src "libresoc.v:142716.3-142717.55"
- process $proc$libresoc.v:142716$6347
+ attribute \src "libresoc.v:142380.3-142381.55"
+ process $proc$libresoc.v:142380$6295
assign { } { }
assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next
sync posedge \coresync_clk
update \oper_r__sign_extend $0\oper_r__sign_extend[0:0]
end
- attribute \src "libresoc.v:142718.3-142719.51"
- process $proc$libresoc.v:142718$6348
+ attribute \src "libresoc.v:142382.3-142383.51"
+ process $proc$libresoc.v:142382$6296
assign { } { }
assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next
sync posedge \coresync_clk
update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0]
end
- attribute \src "libresoc.v:142720.3-142721.41"
- process $proc$libresoc.v:142720$6349
+ attribute \src "libresoc.v:142384.3-142385.41"
+ process $proc$libresoc.v:142384$6297
assign { } { }
assign $0\oper_r__insn[31:0] \oper_r__insn$next
sync posedge \coresync_clk
update \oper_r__insn $0\oper_r__insn[31:0]
end
- attribute \src "libresoc.v:142722.3-142723.39"
- process $proc$libresoc.v:142722$6350
+ attribute \src "libresoc.v:142386.3-142387.39"
+ process $proc$libresoc.v:142386$6298
assign { } { }
assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next
sync posedge \coresync_clk
update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0]
end
- attribute \src "libresoc.v:142724.3-142725.39"
- process $proc$libresoc.v:142724$6351
+ attribute \src "libresoc.v:142388.3-142389.39"
+ process $proc$libresoc.v:142388$6299
assign { } { }
assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next
sync posedge \coresync_clk
update \sto_l_r_sto $0\sto_l_r_sto[0:0]
end
- attribute \src "libresoc.v:142726.3-142727.39"
- process $proc$libresoc.v:142726$6352
+ attribute \src "libresoc.v:142390.3-142391.39"
+ process $proc$libresoc.v:142390$6300
assign { } { }
assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next
sync posedge \coresync_clk
update \upd_l_r_upd $0\upd_l_r_upd[0:0]
end
- attribute \src "libresoc.v:142728.3-142729.39"
- process $proc$libresoc.v:142728$6353
+ attribute \src "libresoc.v:142392.3-142393.39"
+ process $proc$libresoc.v:142392$6301
assign { } { }
assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next
sync posedge \coresync_clk
update \upd_l_s_upd $0\upd_l_s_upd[0:0]
end
- attribute \src "libresoc.v:142730.3-142731.39"
- process $proc$libresoc.v:142730$6354
+ attribute \src "libresoc.v:142394.3-142395.39"
+ process $proc$libresoc.v:142394$6302
assign { } { }
assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next
sync posedge \coresync_clk
update \wri_l_r_wri $0\wri_l_r_wri[0:0]
end
- attribute \src "libresoc.v:142732.3-142733.39"
- process $proc$libresoc.v:142732$6355
+ attribute \src "libresoc.v:142396.3-142397.39"
+ process $proc$libresoc.v:142396$6303
assign { } { }
assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next
sync posedge \coresync_clk
update \adr_l_r_adr $0\adr_l_r_adr[0:0]
end
- attribute \src "libresoc.v:142734.3-142735.39"
- process $proc$libresoc.v:142734$6356
+ attribute \src "libresoc.v:142398.3-142399.39"
+ process $proc$libresoc.v:142398$6304
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:142736.3-142737.39"
- process $proc$libresoc.v:142736$6357
+ attribute \src "libresoc.v:142400.3-142401.39"
+ process $proc$libresoc.v:142400$6305
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:142738.3-142739.39"
- process $proc$libresoc.v:142738$6358
+ attribute \src "libresoc.v:142402.3-142403.39"
+ process $proc$libresoc.v:142402$6306
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:142740.3-142741.39"
- process $proc$libresoc.v:142740$6359
+ attribute \src "libresoc.v:142404.3-142405.39"
+ process $proc$libresoc.v:142404$6307
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:142742.3-142743.28"
- process $proc$libresoc.v:142742$6360
+ attribute \src "libresoc.v:142406.3-142407.28"
+ process $proc$libresoc.v:142406$6308
assign { } { }
assign $0\p_st_go[0:0] \cu_st__go_i
sync posedge \coresync_clk
update \p_st_go $0\p_st_go[0:0]
end
- attribute \src "libresoc.v:142814.3-142822.6"
- process $proc$libresoc.v:142814$6361
+ attribute \src "libresoc.v:142478.3-142486.6"
+ process $proc$libresoc.v:142478$6309
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$6362 $1\opc_l_s_opc$next[0:0]$6363
- attribute \src "libresoc.v:142815.5-142815.29"
+ assign $0\opc_l_s_opc$next[0:0]$6310 $1\opc_l_s_opc$next[0:0]$6311
+ attribute \src "libresoc.v:142479.5-142479.29"
switch \initial
- attribute \src "libresoc.v:142815.9-142815.17"
+ attribute \src "libresoc.v:142479.9-142479.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$6363 1'0
+ assign $1\opc_l_s_opc$next[0:0]$6311 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$6363 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$6311 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6362
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6310
end
- attribute \src "libresoc.v:142823.3-142831.6"
- process $proc$libresoc.v:142823$6364
+ attribute \src "libresoc.v:142487.3-142495.6"
+ process $proc$libresoc.v:142487$6312
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$6365 $1\opc_l_r_opc$next[0:0]$6366
- attribute \src "libresoc.v:142824.5-142824.29"
+ assign $0\opc_l_r_opc$next[0:0]$6313 $1\opc_l_r_opc$next[0:0]$6314
+ attribute \src "libresoc.v:142488.5-142488.29"
switch \initial
- attribute \src "libresoc.v:142824.9-142824.17"
+ attribute \src "libresoc.v:142488.9-142488.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$6366 1'1
+ assign $1\opc_l_r_opc$next[0:0]$6314 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$6366 \reset_o
+ assign $1\opc_l_r_opc$next[0:0]$6314 \reset_o
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6365
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6313
end
- attribute \src "libresoc.v:142832.3-142840.6"
- process $proc$libresoc.v:142832$6367
+ attribute \src "libresoc.v:142496.3-142504.6"
+ process $proc$libresoc.v:142496$6315
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$6368 $1\src_l_s_src$next[2:0]$6369
- attribute \src "libresoc.v:142833.5-142833.29"
+ assign $0\src_l_s_src$next[2:0]$6316 $1\src_l_s_src$next[2:0]$6317
+ attribute \src "libresoc.v:142497.5-142497.29"
switch \initial
- attribute \src "libresoc.v:142833.9-142833.17"
+ attribute \src "libresoc.v:142497.9-142497.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$6369 3'000
+ assign $1\src_l_s_src$next[2:0]$6317 3'000
case
- assign $1\src_l_s_src$next[2:0]$6369 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$6317 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6368
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6316
end
- attribute \src "libresoc.v:142841.3-142849.6"
- process $proc$libresoc.v:142841$6370
+ attribute \src "libresoc.v:142505.3-142513.6"
+ process $proc$libresoc.v:142505$6318
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$6371 $1\src_l_r_src$next[2:0]$6372
- attribute \src "libresoc.v:142842.5-142842.29"
+ assign $0\src_l_r_src$next[2:0]$6319 $1\src_l_r_src$next[2:0]$6320
+ attribute \src "libresoc.v:142506.5-142506.29"
switch \initial
- attribute \src "libresoc.v:142842.9-142842.17"
+ attribute \src "libresoc.v:142506.9-142506.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$6372 3'111
+ assign $1\src_l_r_src$next[2:0]$6320 3'111
case
- assign $1\src_l_r_src$next[2:0]$6372 \reset_r
+ assign $1\src_l_r_src$next[2:0]$6320 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6371
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6319
end
- attribute \src "libresoc.v:142850.3-142858.6"
- process $proc$libresoc.v:142850$6373
+ attribute \src "libresoc.v:142514.3-142522.6"
+ process $proc$libresoc.v:142514$6321
assign { } { }
assign { } { }
- assign $0\adr_l_r_adr$next[0:0]$6374 $1\adr_l_r_adr$next[0:0]$6375
- attribute \src "libresoc.v:142851.5-142851.29"
+ assign $0\adr_l_r_adr$next[0:0]$6322 $1\adr_l_r_adr$next[0:0]$6323
+ attribute \src "libresoc.v:142515.5-142515.29"
switch \initial
- attribute \src "libresoc.v:142851.9-142851.17"
+ attribute \src "libresoc.v:142515.9-142515.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\adr_l_r_adr$next[0:0]$6375 1'1
+ assign $1\adr_l_r_adr$next[0:0]$6323 1'1
case
- assign $1\adr_l_r_adr$next[0:0]$6375 \reset_a
+ assign $1\adr_l_r_adr$next[0:0]$6323 \reset_a
end
sync always
- update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6374
+ update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6322
end
- attribute \src "libresoc.v:142859.3-142867.6"
- process $proc$libresoc.v:142859$6376
+ attribute \src "libresoc.v:142523.3-142531.6"
+ process $proc$libresoc.v:142523$6324
assign { } { }
assign { } { }
- assign $0\wri_l_r_wri$next[0:0]$6377 $1\wri_l_r_wri$next[0:0]$6378
- attribute \src "libresoc.v:142860.5-142860.29"
+ assign $0\wri_l_r_wri$next[0:0]$6325 $1\wri_l_r_wri$next[0:0]$6326
+ attribute \src "libresoc.v:142524.5-142524.29"
switch \initial
- attribute \src "libresoc.v:142860.9-142860.17"
+ attribute \src "libresoc.v:142524.9-142524.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wri_l_r_wri$next[0:0]$6378 1'1
+ assign $1\wri_l_r_wri$next[0:0]$6326 1'1
case
- assign $1\wri_l_r_wri$next[0:0]$6378 \$38 [0]
+ assign $1\wri_l_r_wri$next[0:0]$6326 \$38 [0]
end
sync always
- update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6377
+ update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6325
end
- attribute \src "libresoc.v:142868.3-142876.6"
- process $proc$libresoc.v:142868$6379
+ attribute \src "libresoc.v:142532.3-142540.6"
+ process $proc$libresoc.v:142532$6327
assign { } { }
assign { } { }
- assign $0\upd_l_s_upd$next[0:0]$6380 $1\upd_l_s_upd$next[0:0]$6381
- attribute \src "libresoc.v:142869.5-142869.29"
+ assign $0\upd_l_s_upd$next[0:0]$6328 $1\upd_l_s_upd$next[0:0]$6329
+ attribute \src "libresoc.v:142533.5-142533.29"
switch \initial
- attribute \src "libresoc.v:142869.9-142869.17"
+ attribute \src "libresoc.v:142533.9-142533.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\upd_l_s_upd$next[0:0]$6381 1'0
+ assign $1\upd_l_s_upd$next[0:0]$6329 1'0
case
- assign $1\upd_l_s_upd$next[0:0]$6381 \reset_i
+ assign $1\upd_l_s_upd$next[0:0]$6329 \reset_i
end
sync always
- update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6380
+ update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6328
end
- attribute \src "libresoc.v:142877.3-142885.6"
- process $proc$libresoc.v:142877$6382
+ attribute \src "libresoc.v:142541.3-142549.6"
+ process $proc$libresoc.v:142541$6330
assign { } { }
assign { } { }
- assign $0\upd_l_r_upd$next[0:0]$6383 $1\upd_l_r_upd$next[0:0]$6384
- attribute \src "libresoc.v:142878.5-142878.29"
+ assign $0\upd_l_r_upd$next[0:0]$6331 $1\upd_l_r_upd$next[0:0]$6332
+ attribute \src "libresoc.v:142542.5-142542.29"
switch \initial
- attribute \src "libresoc.v:142878.9-142878.17"
+ attribute \src "libresoc.v:142542.9-142542.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\upd_l_r_upd$next[0:0]$6384 1'1
+ assign $1\upd_l_r_upd$next[0:0]$6332 1'1
case
- assign $1\upd_l_r_upd$next[0:0]$6384 \reset_u
+ assign $1\upd_l_r_upd$next[0:0]$6332 \reset_u
end
sync always
- update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6383
+ update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6331
end
- attribute \src "libresoc.v:142886.3-142894.6"
- process $proc$libresoc.v:142886$6385
+ attribute \src "libresoc.v:142550.3-142558.6"
+ process $proc$libresoc.v:142550$6333
assign { } { }
assign { } { }
- assign $0\sto_l_r_sto$next[0:0]$6386 $1\sto_l_r_sto$next[0:0]$6387
- attribute \src "libresoc.v:142887.5-142887.29"
+ assign $0\sto_l_r_sto$next[0:0]$6334 $1\sto_l_r_sto$next[0:0]$6335
+ attribute \src "libresoc.v:142551.5-142551.29"
switch \initial
- attribute \src "libresoc.v:142887.9-142887.17"
+ attribute \src "libresoc.v:142551.9-142551.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sto_l_r_sto$next[0:0]$6387 1'1
+ assign $1\sto_l_r_sto$next[0:0]$6335 1'1
case
- assign $1\sto_l_r_sto$next[0:0]$6387 \$59
+ assign $1\sto_l_r_sto$next[0:0]$6335 \$59
end
sync always
- update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6386
+ update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6334
end
- attribute \src "libresoc.v:142895.3-142903.6"
- process $proc$libresoc.v:142895$6388
+ attribute \src "libresoc.v:142559.3-142567.6"
+ process $proc$libresoc.v:142559$6336
assign { } { }
assign { } { }
- assign $0\lsd_l_r_lsd$next[0:0]$6389 $1\lsd_l_r_lsd$next[0:0]$6390
- attribute \src "libresoc.v:142896.5-142896.29"
+ assign $0\lsd_l_r_lsd$next[0:0]$6337 $1\lsd_l_r_lsd$next[0:0]$6338
+ attribute \src "libresoc.v:142560.5-142560.29"
switch \initial
- attribute \src "libresoc.v:142896.9-142896.17"
+ attribute \src "libresoc.v:142560.9-142560.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\lsd_l_r_lsd$next[0:0]$6390 1'1
+ assign $1\lsd_l_r_lsd$next[0:0]$6338 1'1
case
- assign $1\lsd_l_r_lsd$next[0:0]$6390 \$63
+ assign $1\lsd_l_r_lsd$next[0:0]$6338 \$63
end
sync always
- update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6389
+ update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6337
end
- attribute \src "libresoc.v:142904.3-142946.6"
- process $proc$libresoc.v:142904$6391
+ attribute \src "libresoc.v:142568.3-142610.6"
+ process $proc$libresoc.v:142568$6339
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__byte_reverse$next[0:0]$6424
- assign $0\oper_r__data_len$next[3:0]$6393 $2\oper_r__data_len$next[3:0]$6425
- assign $0\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__fn_unit$next[13:0]$6426
+ assign $0\oper_r__byte_reverse$next[0:0]$6340 $2\oper_r__byte_reverse$next[0:0]$6372
+ assign $0\oper_r__data_len$next[3:0]$6341 $2\oper_r__data_len$next[3:0]$6373
+ assign $0\oper_r__fn_unit$next[13:0]$6342 $2\oper_r__fn_unit$next[13:0]$6374
assign { } { }
assign { } { }
- assign $0\oper_r__insn$next[31:0]$6397 $2\oper_r__insn$next[31:0]$6429
- assign $0\oper_r__insn_type$next[6:0]$6398 $2\oper_r__insn_type$next[6:0]$6430
- assign $0\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__is_32bit$next[0:0]$6431
- assign $0\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_signed$next[0:0]$6432
- assign $0\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__ldst_mode$next[1:0]$6433
+ assign $0\oper_r__insn$next[31:0]$6345 $2\oper_r__insn$next[31:0]$6377
+ assign $0\oper_r__insn_type$next[6:0]$6346 $2\oper_r__insn_type$next[6:0]$6378
+ assign $0\oper_r__is_32bit$next[0:0]$6347 $2\oper_r__is_32bit$next[0:0]$6379
+ assign $0\oper_r__is_signed$next[0:0]$6348 $2\oper_r__is_signed$next[0:0]$6380
+ assign $0\oper_r__ldst_mode$next[1:0]$6349 $2\oper_r__ldst_mode$next[1:0]$6381
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__sign_extend$next[0:0]$6438
- assign $0\oper_r__zero_a$next[0:0]$6407 $2\oper_r__zero_a$next[0:0]$6439
- assign $0\oper_r__imm_data__data$next[63:0]$6395 $3\oper_r__imm_data__data$next[63:0]$6440
- assign $0\oper_r__imm_data__ok$next[0:0]$6396 $3\oper_r__imm_data__ok$next[0:0]$6441
- assign $0\oper_r__oe__oe$next[0:0]$6402 $3\oper_r__oe__oe$next[0:0]$6442
- assign $0\oper_r__oe__ok$next[0:0]$6403 $3\oper_r__oe__ok$next[0:0]$6443
- assign $0\oper_r__rc__ok$next[0:0]$6404 $3\oper_r__rc__ok$next[0:0]$6444
- assign $0\oper_r__rc__rc$next[0:0]$6405 $3\oper_r__rc__rc$next[0:0]$6445
- attribute \src "libresoc.v:142905.5-142905.29"
+ assign $0\oper_r__sign_extend$next[0:0]$6354 $2\oper_r__sign_extend$next[0:0]$6386
+ assign $0\oper_r__zero_a$next[0:0]$6355 $2\oper_r__zero_a$next[0:0]$6387
+ assign $0\oper_r__imm_data__data$next[63:0]$6343 $3\oper_r__imm_data__data$next[63:0]$6388
+ assign $0\oper_r__imm_data__ok$next[0:0]$6344 $3\oper_r__imm_data__ok$next[0:0]$6389
+ assign $0\oper_r__oe__oe$next[0:0]$6350 $3\oper_r__oe__oe$next[0:0]$6390
+ assign $0\oper_r__oe__ok$next[0:0]$6351 $3\oper_r__oe__ok$next[0:0]$6391
+ assign $0\oper_r__rc__ok$next[0:0]$6352 $3\oper_r__rc__ok$next[0:0]$6392
+ assign $0\oper_r__rc__rc$next[0:0]$6353 $3\oper_r__rc__rc$next[0:0]$6393
+ attribute \src "libresoc.v:142569.5-142569.29"
switch \initial
- attribute \src "libresoc.v:142905.9-142905.17"
+ attribute \src "libresoc.v:142569.9-142569.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\oper_r__insn$next[31:0]$6413 $1\oper_r__ldst_mode$next[1:0]$6417 $1\oper_r__sign_extend$next[0:0]$6422 $1\oper_r__byte_reverse$next[0:0]$6408 $1\oper_r__data_len$next[3:0]$6409 $1\oper_r__is_signed$next[0:0]$6416 $1\oper_r__is_32bit$next[0:0]$6415 $1\oper_r__oe__ok$next[0:0]$6419 $1\oper_r__oe__oe$next[0:0]$6418 $1\oper_r__rc__ok$next[0:0]$6420 $1\oper_r__rc__rc$next[0:0]$6421 $1\oper_r__zero_a$next[0:0]$6423 $1\oper_r__imm_data__ok$next[0:0]$6412 $1\oper_r__imm_data__data$next[63:0]$6411 $1\oper_r__fn_unit$next[13:0]$6410 $1\oper_r__insn_type$next[6:0]$6414 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type }
+ assign { $1\oper_r__insn$next[31:0]$6361 $1\oper_r__ldst_mode$next[1:0]$6365 $1\oper_r__sign_extend$next[0:0]$6370 $1\oper_r__byte_reverse$next[0:0]$6356 $1\oper_r__data_len$next[3:0]$6357 $1\oper_r__is_signed$next[0:0]$6364 $1\oper_r__is_32bit$next[0:0]$6363 $1\oper_r__oe__ok$next[0:0]$6367 $1\oper_r__oe__oe$next[0:0]$6366 $1\oper_r__rc__ok$next[0:0]$6368 $1\oper_r__rc__rc$next[0:0]$6369 $1\oper_r__zero_a$next[0:0]$6371 $1\oper_r__imm_data__ok$next[0:0]$6360 $1\oper_r__imm_data__data$next[63:0]$6359 $1\oper_r__fn_unit$next[13:0]$6358 $1\oper_r__insn_type$next[6:0]$6362 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type }
case
- assign $1\oper_r__byte_reverse$next[0:0]$6408 \oper_r__byte_reverse
- assign $1\oper_r__data_len$next[3:0]$6409 \oper_r__data_len
- assign $1\oper_r__fn_unit$next[13:0]$6410 \oper_r__fn_unit
- assign $1\oper_r__imm_data__data$next[63:0]$6411 \oper_r__imm_data__data
- assign $1\oper_r__imm_data__ok$next[0:0]$6412 \oper_r__imm_data__ok
- assign $1\oper_r__insn$next[31:0]$6413 \oper_r__insn
- assign $1\oper_r__insn_type$next[6:0]$6414 \oper_r__insn_type
- assign $1\oper_r__is_32bit$next[0:0]$6415 \oper_r__is_32bit
- assign $1\oper_r__is_signed$next[0:0]$6416 \oper_r__is_signed
- assign $1\oper_r__ldst_mode$next[1:0]$6417 \oper_r__ldst_mode
- assign $1\oper_r__oe__oe$next[0:0]$6418 \oper_r__oe__oe
- assign $1\oper_r__oe__ok$next[0:0]$6419 \oper_r__oe__ok
- assign $1\oper_r__rc__ok$next[0:0]$6420 \oper_r__rc__ok
- assign $1\oper_r__rc__rc$next[0:0]$6421 \oper_r__rc__rc
- assign $1\oper_r__sign_extend$next[0:0]$6422 \oper_r__sign_extend
- assign $1\oper_r__zero_a$next[0:0]$6423 \oper_r__zero_a
+ assign $1\oper_r__byte_reverse$next[0:0]$6356 \oper_r__byte_reverse
+ assign $1\oper_r__data_len$next[3:0]$6357 \oper_r__data_len
+ assign $1\oper_r__fn_unit$next[13:0]$6358 \oper_r__fn_unit
+ assign $1\oper_r__imm_data__data$next[63:0]$6359 \oper_r__imm_data__data
+ assign $1\oper_r__imm_data__ok$next[0:0]$6360 \oper_r__imm_data__ok
+ assign $1\oper_r__insn$next[31:0]$6361 \oper_r__insn
+ assign $1\oper_r__insn_type$next[6:0]$6362 \oper_r__insn_type
+ assign $1\oper_r__is_32bit$next[0:0]$6363 \oper_r__is_32bit
+ assign $1\oper_r__is_signed$next[0:0]$6364 \oper_r__is_signed
+ assign $1\oper_r__ldst_mode$next[1:0]$6365 \oper_r__ldst_mode
+ assign $1\oper_r__oe__oe$next[0:0]$6366 \oper_r__oe__oe
+ assign $1\oper_r__oe__ok$next[0:0]$6367 \oper_r__oe__ok
+ assign $1\oper_r__rc__ok$next[0:0]$6368 \oper_r__rc__ok
+ assign $1\oper_r__rc__rc$next[0:0]$6369 \oper_r__rc__rc
+ assign $1\oper_r__sign_extend$next[0:0]$6370 \oper_r__sign_extend
+ assign $1\oper_r__zero_a$next[0:0]$6371 \oper_r__zero_a
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381"
switch \cu_done_o
assign { } { }
assign { } { }
assign { } { }
- assign { $2\oper_r__insn$next[31:0]$6429 $2\oper_r__ldst_mode$next[1:0]$6433 $2\oper_r__sign_extend$next[0:0]$6438 $2\oper_r__byte_reverse$next[0:0]$6424 $2\oper_r__data_len$next[3:0]$6425 $2\oper_r__is_signed$next[0:0]$6432 $2\oper_r__is_32bit$next[0:0]$6431 $2\oper_r__oe__ok$next[0:0]$6435 $2\oper_r__oe__oe$next[0:0]$6434 $2\oper_r__rc__ok$next[0:0]$6436 $2\oper_r__rc__rc$next[0:0]$6437 $2\oper_r__zero_a$next[0:0]$6439 $2\oper_r__imm_data__ok$next[0:0]$6428 $2\oper_r__imm_data__data$next[63:0]$6427 $2\oper_r__fn_unit$next[13:0]$6426 $2\oper_r__insn_type$next[6:0]$6430 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\oper_r__insn$next[31:0]$6377 $2\oper_r__ldst_mode$next[1:0]$6381 $2\oper_r__sign_extend$next[0:0]$6386 $2\oper_r__byte_reverse$next[0:0]$6372 $2\oper_r__data_len$next[3:0]$6373 $2\oper_r__is_signed$next[0:0]$6380 $2\oper_r__is_32bit$next[0:0]$6379 $2\oper_r__oe__ok$next[0:0]$6383 $2\oper_r__oe__oe$next[0:0]$6382 $2\oper_r__rc__ok$next[0:0]$6384 $2\oper_r__rc__rc$next[0:0]$6385 $2\oper_r__zero_a$next[0:0]$6387 $2\oper_r__imm_data__ok$next[0:0]$6376 $2\oper_r__imm_data__data$next[63:0]$6375 $2\oper_r__fn_unit$next[13:0]$6374 $2\oper_r__insn_type$next[6:0]$6378 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__byte_reverse$next[0:0]$6408
- assign $2\oper_r__data_len$next[3:0]$6425 $1\oper_r__data_len$next[3:0]$6409
- assign $2\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__fn_unit$next[13:0]$6410
- assign $2\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__imm_data__data$next[63:0]$6411
- assign $2\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__ok$next[0:0]$6412
- assign $2\oper_r__insn$next[31:0]$6429 $1\oper_r__insn$next[31:0]$6413
- assign $2\oper_r__insn_type$next[6:0]$6430 $1\oper_r__insn_type$next[6:0]$6414
- assign $2\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__is_32bit$next[0:0]$6415
- assign $2\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_signed$next[0:0]$6416
- assign $2\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__ldst_mode$next[1:0]$6417
- assign $2\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__oe__oe$next[0:0]$6418
- assign $2\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__ok$next[0:0]$6419
- assign $2\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__ok$next[0:0]$6420
- assign $2\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__rc__rc$next[0:0]$6421
- assign $2\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__sign_extend$next[0:0]$6422
- assign $2\oper_r__zero_a$next[0:0]$6439 $1\oper_r__zero_a$next[0:0]$6423
+ assign $2\oper_r__byte_reverse$next[0:0]$6372 $1\oper_r__byte_reverse$next[0:0]$6356
+ assign $2\oper_r__data_len$next[3:0]$6373 $1\oper_r__data_len$next[3:0]$6357
+ assign $2\oper_r__fn_unit$next[13:0]$6374 $1\oper_r__fn_unit$next[13:0]$6358
+ assign $2\oper_r__imm_data__data$next[63:0]$6375 $1\oper_r__imm_data__data$next[63:0]$6359
+ assign $2\oper_r__imm_data__ok$next[0:0]$6376 $1\oper_r__imm_data__ok$next[0:0]$6360
+ assign $2\oper_r__insn$next[31:0]$6377 $1\oper_r__insn$next[31:0]$6361
+ assign $2\oper_r__insn_type$next[6:0]$6378 $1\oper_r__insn_type$next[6:0]$6362
+ assign $2\oper_r__is_32bit$next[0:0]$6379 $1\oper_r__is_32bit$next[0:0]$6363
+ assign $2\oper_r__is_signed$next[0:0]$6380 $1\oper_r__is_signed$next[0:0]$6364
+ assign $2\oper_r__ldst_mode$next[1:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6365
+ assign $2\oper_r__oe__oe$next[0:0]$6382 $1\oper_r__oe__oe$next[0:0]$6366
+ assign $2\oper_r__oe__ok$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6367
+ assign $2\oper_r__rc__ok$next[0:0]$6384 $1\oper_r__rc__ok$next[0:0]$6368
+ assign $2\oper_r__rc__rc$next[0:0]$6385 $1\oper_r__rc__rc$next[0:0]$6369
+ assign $2\oper_r__sign_extend$next[0:0]$6386 $1\oper_r__sign_extend$next[0:0]$6370
+ assign $2\oper_r__zero_a$next[0:0]$6387 $1\oper_r__zero_a$next[0:0]$6371
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\oper_r__imm_data__data$next[63:0]$6440 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\oper_r__imm_data__ok$next[0:0]$6441 1'0
- assign $3\oper_r__rc__rc$next[0:0]$6445 1'0
- assign $3\oper_r__rc__ok$next[0:0]$6444 1'0
- assign $3\oper_r__oe__oe$next[0:0]$6442 1'0
- assign $3\oper_r__oe__ok$next[0:0]$6443 1'0
+ assign $3\oper_r__imm_data__data$next[63:0]$6388 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\oper_r__imm_data__ok$next[0:0]$6389 1'0
+ assign $3\oper_r__rc__rc$next[0:0]$6393 1'0
+ assign $3\oper_r__rc__ok$next[0:0]$6392 1'0
+ assign $3\oper_r__oe__oe$next[0:0]$6390 1'0
+ assign $3\oper_r__oe__ok$next[0:0]$6391 1'0
case
- assign $3\oper_r__imm_data__data$next[63:0]$6440 $2\oper_r__imm_data__data$next[63:0]$6427
- assign $3\oper_r__imm_data__ok$next[0:0]$6441 $2\oper_r__imm_data__ok$next[0:0]$6428
- assign $3\oper_r__oe__oe$next[0:0]$6442 $2\oper_r__oe__oe$next[0:0]$6434
- assign $3\oper_r__oe__ok$next[0:0]$6443 $2\oper_r__oe__ok$next[0:0]$6435
- assign $3\oper_r__rc__ok$next[0:0]$6444 $2\oper_r__rc__ok$next[0:0]$6436
- assign $3\oper_r__rc__rc$next[0:0]$6445 $2\oper_r__rc__rc$next[0:0]$6437
+ assign $3\oper_r__imm_data__data$next[63:0]$6388 $2\oper_r__imm_data__data$next[63:0]$6375
+ assign $3\oper_r__imm_data__ok$next[0:0]$6389 $2\oper_r__imm_data__ok$next[0:0]$6376
+ assign $3\oper_r__oe__oe$next[0:0]$6390 $2\oper_r__oe__oe$next[0:0]$6382
+ assign $3\oper_r__oe__ok$next[0:0]$6391 $2\oper_r__oe__ok$next[0:0]$6383
+ assign $3\oper_r__rc__ok$next[0:0]$6392 $2\oper_r__rc__ok$next[0:0]$6384
+ assign $3\oper_r__rc__rc$next[0:0]$6393 $2\oper_r__rc__rc$next[0:0]$6385
end
sync always
- update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6392
- update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6393
- update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6394
- update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6395
- update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6396
- update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6397
- update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6398
- update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6399
- update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6400
- update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6401
- update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6402
- update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6403
- update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6404
- update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6405
- update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6406
- update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6407
+ update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6340
+ update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6341
+ update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6342
+ update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6343
+ update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6344
+ update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6345
+ update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6346
+ update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6347
+ update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6348
+ update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6349
+ update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6350
+ update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6351
+ update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6352
+ update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6353
+ update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6354
+ update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6355
end
- attribute \src "libresoc.v:142947.3-142956.6"
- process $proc$libresoc.v:142947$6446
+ attribute \src "libresoc.v:142611.3-142620.6"
+ process $proc$libresoc.v:142611$6394
assign { } { }
assign { } { }
- assign $0\ldo_r$next[63:0]$6447 $1\ldo_r$next[63:0]$6448
- attribute \src "libresoc.v:142948.5-142948.29"
+ assign $0\ldo_r$next[63:0]$6395 $1\ldo_r$next[63:0]$6396
+ attribute \src "libresoc.v:142612.5-142612.29"
switch \initial
- attribute \src "libresoc.v:142948.9-142948.17"
+ attribute \src "libresoc.v:142612.9-142612.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldo_r$next[63:0]$6448 \ldd_o
+ assign $1\ldo_r$next[63:0]$6396 \ldd_o
case
- assign $1\ldo_r$next[63:0]$6448 \ldo_r
+ assign $1\ldo_r$next[63:0]$6396 \ldo_r
end
sync always
- update \ldo_r$next $0\ldo_r$next[63:0]$6447
+ update \ldo_r$next $0\ldo_r$next[63:0]$6395
end
- attribute \src "libresoc.v:142957.3-142972.6"
- process $proc$libresoc.v:142957$6449
+ attribute \src "libresoc.v:142621.3-142636.6"
+ process $proc$libresoc.v:142621$6397
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$6450 $2\src_r0$next[63:0]$6452
- attribute \src "libresoc.v:142958.5-142958.29"
+ assign $0\src_r0$next[63:0]$6398 $2\src_r0$next[63:0]$6400
+ attribute \src "libresoc.v:142622.5-142622.29"
switch \initial
- attribute \src "libresoc.v:142958.9-142958.17"
+ attribute \src "libresoc.v:142622.9-142622.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$6451 \src1_i
+ assign $1\src_r0$next[63:0]$6399 \src1_i
case
- assign $1\src_r0$next[63:0]$6451 \src_r0
+ assign $1\src_r0$next[63:0]$6399 \src_r0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r0$next[63:0]$6452 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r0$next[63:0]$6400 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r0$next[63:0]$6452 $1\src_r0$next[63:0]$6451
+ assign $2\src_r0$next[63:0]$6400 $1\src_r0$next[63:0]$6399
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$6450
+ update \src_r0$next $0\src_r0$next[63:0]$6398
end
- attribute \src "libresoc.v:142973.3-142988.6"
- process $proc$libresoc.v:142973$6453
+ attribute \src "libresoc.v:142637.3-142652.6"
+ process $proc$libresoc.v:142637$6401
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$6454 $2\src_r1$next[63:0]$6456
- attribute \src "libresoc.v:142974.5-142974.29"
+ assign $0\src_r1$next[63:0]$6402 $2\src_r1$next[63:0]$6404
+ attribute \src "libresoc.v:142638.5-142638.29"
switch \initial
- attribute \src "libresoc.v:142974.9-142974.17"
+ attribute \src "libresoc.v:142638.9-142638.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$6455 \src2_i
+ assign $1\src_r1$next[63:0]$6403 \src2_i
case
- assign $1\src_r1$next[63:0]$6455 \src_r1
+ assign $1\src_r1$next[63:0]$6403 \src_r1
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r1$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r1$next[63:0]$6404 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r1$next[63:0]$6456 $1\src_r1$next[63:0]$6455
+ assign $2\src_r1$next[63:0]$6404 $1\src_r1$next[63:0]$6403
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$6454
+ update \src_r1$next $0\src_r1$next[63:0]$6402
end
- attribute \src "libresoc.v:142989.3-143004.6"
- process $proc$libresoc.v:142989$6457
+ attribute \src "libresoc.v:142653.3-142668.6"
+ process $proc$libresoc.v:142653$6405
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$6458 $2\src_r2$next[63:0]$6460
- attribute \src "libresoc.v:142990.5-142990.29"
+ assign $0\src_r2$next[63:0]$6406 $2\src_r2$next[63:0]$6408
+ attribute \src "libresoc.v:142654.5-142654.29"
switch \initial
- attribute \src "libresoc.v:142990.9-142990.17"
+ attribute \src "libresoc.v:142654.9-142654.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$6459 \src3_i
+ assign $1\src_r2$next[63:0]$6407 \src3_i
case
- assign $1\src_r2$next[63:0]$6459 \src_r2
+ assign $1\src_r2$next[63:0]$6407 \src_r2
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r2$next[63:0]$6460 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r2$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r2$next[63:0]$6460 $1\src_r2$next[63:0]$6459
+ assign $2\src_r2$next[63:0]$6408 $1\src_r2$next[63:0]$6407
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$6458
+ update \src_r2$next $0\src_r2$next[63:0]$6406
end
- attribute \src "libresoc.v:143005.3-143014.6"
- process $proc$libresoc.v:143005$6461
+ attribute \src "libresoc.v:142669.3-142678.6"
+ process $proc$libresoc.v:142669$6409
assign { } { }
assign { } { }
- assign $0\ea_r$next[63:0]$6462 $1\ea_r$next[63:0]$6463
- attribute \src "libresoc.v:143006.5-143006.29"
+ assign $0\ea_r$next[63:0]$6410 $1\ea_r$next[63:0]$6411
+ attribute \src "libresoc.v:142670.5-142670.29"
switch \initial
- attribute \src "libresoc.v:143006.9-143006.17"
+ attribute \src "libresoc.v:142670.9-142670.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ea_r$next[63:0]$6463 \alu_o
+ assign $1\ea_r$next[63:0]$6411 \alu_o
case
- assign $1\ea_r$next[63:0]$6463 \ea_r
+ assign $1\ea_r$next[63:0]$6411 \ea_r
end
sync always
- update \ea_r$next $0\ea_r$next[63:0]$6462
+ update \ea_r$next $0\ea_r$next[63:0]$6410
end
- attribute \src "libresoc.v:143015.3-143024.6"
- process $proc$libresoc.v:143015$6464
+ attribute \src "libresoc.v:142679.3-142688.6"
+ process $proc$libresoc.v:142679$6412
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:143016.5-143016.29"
+ attribute \src "libresoc.v:142680.5-142680.29"
switch \initial
- attribute \src "libresoc.v:143016.9-143016.17"
+ attribute \src "libresoc.v:142680.9-142680.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:143025.3-143034.6"
- process $proc$libresoc.v:143025$6465
+ attribute \src "libresoc.v:142689.3-142698.6"
+ process $proc$libresoc.v:142689$6413
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:143026.5-143026.29"
+ attribute \src "libresoc.v:142690.5-142690.29"
switch \initial
- attribute \src "libresoc.v:143026.9-143026.17"
+ attribute \src "libresoc.v:142690.9-142690.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:143035.3-143043.6"
- process $proc$libresoc.v:143035$6466
+ attribute \src "libresoc.v:142699.3-142707.6"
+ process $proc$libresoc.v:142699$6414
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i_ok$next[0:0]$6467 $1\ldst_port0_addr_i_ok$next[0:0]$6468
- attribute \src "libresoc.v:143036.5-143036.29"
+ assign $0\ldst_port0_addr_i_ok$next[0:0]$6415 $1\ldst_port0_addr_i_ok$next[0:0]$6416
+ attribute \src "libresoc.v:142700.5-142700.29"
switch \initial
- attribute \src "libresoc.v:143036.9-143036.17"
+ attribute \src "libresoc.v:142700.9-142700.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i_ok$next[0:0]$6468 1'0
+ assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 1'0
case
- assign $1\ldst_port0_addr_i_ok$next[0:0]$6468 \$177
+ assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 \$177
end
sync always
- update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6467
+ update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6415
end
- attribute \src "libresoc.v:143044.3-143067.6"
- process $proc$libresoc.v:143044$6469
+ attribute \src "libresoc.v:142708.3-142731.6"
+ process $proc$libresoc.v:142708$6417
assign { } { }
assign { } { }
assign $0\lddata_r[63:0] $1\lddata_r[63:0]
- attribute \src "libresoc.v:143045.5-143045.29"
+ attribute \src "libresoc.v:142709.5-142709.29"
switch \initial
- attribute \src "libresoc.v:143045.9-143045.17"
+ attribute \src "libresoc.v:142709.9-142709.17"
case 1'1
case
end
sync always
update \lddata_r $0\lddata_r[63:0]
end
- attribute \src "libresoc.v:143068.3-143079.6"
- process $proc$libresoc.v:143068$6470
+ attribute \src "libresoc.v:142732.3-142743.6"
+ process $proc$libresoc.v:142732$6418
assign { } { }
assign $0\revnorev[63:0] $1\revnorev[63:0]
- attribute \src "libresoc.v:143069.5-143069.29"
+ attribute \src "libresoc.v:142733.5-142733.29"
switch \initial
- attribute \src "libresoc.v:143069.9-143069.17"
+ attribute \src "libresoc.v:142733.9-142733.17"
case 1'1
case
end
sync always
update \revnorev $0\revnorev[63:0]
end
- attribute \src "libresoc.v:143080.3-143099.6"
- process $proc$libresoc.v:143080$6471
+ attribute \src "libresoc.v:142744.3-142763.6"
+ process $proc$libresoc.v:142744$6419
assign { } { }
assign $0\ldd_o[63:0] $1\ldd_o[63:0]
- attribute \src "libresoc.v:143081.5-143081.29"
+ attribute \src "libresoc.v:142745.5-142745.29"
switch \initial
- attribute \src "libresoc.v:143081.9-143081.17"
+ attribute \src "libresoc.v:142745.9-142745.17"
case 1'1
case
end
sync always
update \ldd_o $0\ldd_o[63:0]
end
- attribute \src "libresoc.v:143100.3-143123.6"
- process $proc$libresoc.v:143100$6472
+ attribute \src "libresoc.v:142764.3-142787.6"
+ process $proc$libresoc.v:142764$6420
assign { } { }
assign { } { }
assign $0\stdata_r[63:0] $1\stdata_r[63:0]
- attribute \src "libresoc.v:143101.5-143101.29"
+ attribute \src "libresoc.v:142765.5-142765.29"
switch \initial
- attribute \src "libresoc.v:143101.9-143101.17"
+ attribute \src "libresoc.v:142765.9-142765.17"
case 1'1
case
end
sync always
update \stdata_r $0\stdata_r[63:0]
end
- attribute \src "libresoc.v:143124.3-143135.6"
- process $proc$libresoc.v:143124$6473
+ attribute \src "libresoc.v:142788.3-142799.6"
+ process $proc$libresoc.v:142788$6421
assign { } { }
assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:143125.5-143125.29"
+ attribute \src "libresoc.v:142789.5-142789.29"
switch \initial
- attribute \src "libresoc.v:143125.9-143125.17"
+ attribute \src "libresoc.v:142789.9-142789.17"
case 1'1
case
end
sync always
update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0]
end
- connect \$100 $and$libresoc.v:142583$6232_Y
- connect \$102 $and$libresoc.v:142584$6233_Y
- connect \$104 $and$libresoc.v:142585$6234_Y
- connect \$106 $and$libresoc.v:142586$6235_Y
- connect \$108 $and$libresoc.v:142587$6236_Y
- connect \$10 $or$libresoc.v:142588$6237_Y
- connect \$110 $and$libresoc.v:142589$6238_Y
- connect \$112 $and$libresoc.v:142590$6239_Y
- connect \$114 $and$libresoc.v:142591$6240_Y
- connect \$116 $and$libresoc.v:142592$6241_Y
- connect \$118 $and$libresoc.v:142593$6242_Y
- connect \$120 $and$libresoc.v:142594$6243_Y
- connect \$122 $and$libresoc.v:142595$6244_Y
- connect \$124 $and$libresoc.v:142596$6245_Y
- connect \$126 $eq$libresoc.v:142597$6246_Y
- connect \$128 $and$libresoc.v:142598$6247_Y
- connect \$12 $or$libresoc.v:142599$6248_Y
- connect \$130 $and$libresoc.v:142600$6249_Y
- connect \$132 $and$libresoc.v:142601$6250_Y
- connect \$134 $or$libresoc.v:142602$6251_Y
- connect \$136 $or$libresoc.v:142603$6252_Y
- connect \$138 $or$libresoc.v:142604$6253_Y
- connect \$140 $and$libresoc.v:142605$6254_Y
- connect \$142 $and$libresoc.v:142606$6255_Y
- connect \$145 $or$libresoc.v:142607$6256_Y
- connect \$147 $or$libresoc.v:142608$6257_Y
- connect \$144 $not$libresoc.v:142609$6258_Y
- connect \$14 $or$libresoc.v:142610$6259_Y
- connect \$150 $and$libresoc.v:142611$6260_Y
- connect \$152 $or$libresoc.v:142612$6261_Y
- connect \$154 $and$libresoc.v:142613$6262_Y
- connect \$156 $not$libresoc.v:142614$6263_Y
- connect \$158 $or$libresoc.v:142615$6264_Y
- connect \$160 $and$libresoc.v:142616$6265_Y
- connect \$162 $eq$libresoc.v:142617$6266_Y
- connect \$164 $and$libresoc.v:142618$6267_Y
- connect \$167 $eq$libresoc.v:142619$6268_Y
- connect \$16 $or$libresoc.v:142620$6269_Y
- connect \$169 $and$libresoc.v:142621$6270_Y
- connect \$171 $and$libresoc.v:142622$6271_Y
- connect \$173 $and$libresoc.v:142623$6272_Y
- connect \$175 $pos$libresoc.v:142624$6274_Y
- connect \$177 $and$libresoc.v:142625$6275_Y
- connect \$186 $pos$libresoc.v:142626$6277_Y
- connect \$188 $pos$libresoc.v:142627$6278_Y
- connect \$18 $or$libresoc.v:142628$6279_Y
- connect \$190 $pos$libresoc.v:142629$6280_Y
- connect \$192 $eq$libresoc.v:142630$6281_Y
- connect \$194 $pos$libresoc.v:142631$6283_Y
- connect \$196 $pos$libresoc.v:142632$6284_Y
- connect \$198 $pos$libresoc.v:142633$6285_Y
- connect \$20 $or$libresoc.v:142634$6286_Y
- connect \$22 $eq$libresoc.v:142635$6287_Y
- connect \$24 $eq$libresoc.v:142636$6288_Y
- connect \$26 $and$libresoc.v:142637$6289_Y
- connect \$28 $and$libresoc.v:142638$6290_Y
- connect \$30 $not$libresoc.v:142639$6291_Y
- connect \$32 $and$libresoc.v:142640$6292_Y
- connect \$34 $not$libresoc.v:142641$6293_Y
- connect \$36 $and$libresoc.v:142642$6294_Y
- connect \$39 $not$libresoc.v:142643$6295_Y
- connect \$41 $eq$libresoc.v:142644$6296_Y
- connect \$43 $and$libresoc.v:142645$6297_Y
- connect \$45 $or$libresoc.v:142646$6298_Y
- connect \$47 $not$libresoc.v:142647$6299_Y
- connect \$49 $eq$libresoc.v:142648$6300_Y
- connect \$51 $and$libresoc.v:142649$6301_Y
- connect \$53 $or$libresoc.v:142650$6302_Y
- connect \$55 $or$libresoc.v:142651$6303_Y
- connect \$57 $and$libresoc.v:142652$6304_Y
- connect \$59 $or$libresoc.v:142653$6305_Y
- connect \$61 $or$libresoc.v:142654$6306_Y
- connect \$63 $or$libresoc.v:142655$6307_Y
- connect \$65 $ternary$libresoc.v:142656$6308_Y
- connect \$67 $ternary$libresoc.v:142657$6309_Y
- connect \$69 $ternary$libresoc.v:142658$6310_Y
- connect \$71 $ternary$libresoc.v:142659$6311_Y
- connect \$74 $add$libresoc.v:142660$6312_Y
- connect \$76 $and$libresoc.v:142661$6313_Y
- connect \$78 $not$libresoc.v:142662$6314_Y
- connect \$80 $and$libresoc.v:142663$6315_Y
- connect \$82 $not$libresoc.v:142664$6316_Y
- connect \$84 $and$libresoc.v:142665$6317_Y
- connect \$86 $and$libresoc.v:142666$6318_Y
- connect \$88 $and$libresoc.v:142667$6319_Y
- connect \$8 $or$libresoc.v:142668$6320_Y
- connect \$90 $or$libresoc.v:142669$6321_Y
- connect \$93 $or$libresoc.v:142670$6322_Y
- connect \$92 $not$libresoc.v:142671$6323_Y
- connect \$96 $and$libresoc.v:142672$6324_Y
- connect \$98 $not$libresoc.v:142673$6325_Y
+ connect \$100 $and$libresoc.v:142247$6180_Y
+ connect \$102 $and$libresoc.v:142248$6181_Y
+ connect \$104 $and$libresoc.v:142249$6182_Y
+ connect \$106 $and$libresoc.v:142250$6183_Y
+ connect \$108 $and$libresoc.v:142251$6184_Y
+ connect \$10 $or$libresoc.v:142252$6185_Y
+ connect \$110 $and$libresoc.v:142253$6186_Y
+ connect \$112 $and$libresoc.v:142254$6187_Y
+ connect \$114 $and$libresoc.v:142255$6188_Y
+ connect \$116 $and$libresoc.v:142256$6189_Y
+ connect \$118 $and$libresoc.v:142257$6190_Y
+ connect \$120 $and$libresoc.v:142258$6191_Y
+ connect \$122 $and$libresoc.v:142259$6192_Y
+ connect \$124 $and$libresoc.v:142260$6193_Y
+ connect \$126 $eq$libresoc.v:142261$6194_Y
+ connect \$128 $and$libresoc.v:142262$6195_Y
+ connect \$12 $or$libresoc.v:142263$6196_Y
+ connect \$130 $and$libresoc.v:142264$6197_Y
+ connect \$132 $and$libresoc.v:142265$6198_Y
+ connect \$134 $or$libresoc.v:142266$6199_Y
+ connect \$136 $or$libresoc.v:142267$6200_Y
+ connect \$138 $or$libresoc.v:142268$6201_Y
+ connect \$140 $and$libresoc.v:142269$6202_Y
+ connect \$142 $and$libresoc.v:142270$6203_Y
+ connect \$145 $or$libresoc.v:142271$6204_Y
+ connect \$147 $or$libresoc.v:142272$6205_Y
+ connect \$144 $not$libresoc.v:142273$6206_Y
+ connect \$14 $or$libresoc.v:142274$6207_Y
+ connect \$150 $and$libresoc.v:142275$6208_Y
+ connect \$152 $or$libresoc.v:142276$6209_Y
+ connect \$154 $and$libresoc.v:142277$6210_Y
+ connect \$156 $not$libresoc.v:142278$6211_Y
+ connect \$158 $or$libresoc.v:142279$6212_Y
+ connect \$160 $and$libresoc.v:142280$6213_Y
+ connect \$162 $eq$libresoc.v:142281$6214_Y
+ connect \$164 $and$libresoc.v:142282$6215_Y
+ connect \$167 $eq$libresoc.v:142283$6216_Y
+ connect \$16 $or$libresoc.v:142284$6217_Y
+ connect \$169 $and$libresoc.v:142285$6218_Y
+ connect \$171 $and$libresoc.v:142286$6219_Y
+ connect \$173 $and$libresoc.v:142287$6220_Y
+ connect \$175 $pos$libresoc.v:142288$6222_Y
+ connect \$177 $and$libresoc.v:142289$6223_Y
+ connect \$186 $pos$libresoc.v:142290$6225_Y
+ connect \$188 $pos$libresoc.v:142291$6226_Y
+ connect \$18 $or$libresoc.v:142292$6227_Y
+ connect \$190 $pos$libresoc.v:142293$6228_Y
+ connect \$192 $eq$libresoc.v:142294$6229_Y
+ connect \$194 $pos$libresoc.v:142295$6231_Y
+ connect \$196 $pos$libresoc.v:142296$6232_Y
+ connect \$198 $pos$libresoc.v:142297$6233_Y
+ connect \$20 $or$libresoc.v:142298$6234_Y
+ connect \$22 $eq$libresoc.v:142299$6235_Y
+ connect \$24 $eq$libresoc.v:142300$6236_Y
+ connect \$26 $and$libresoc.v:142301$6237_Y
+ connect \$28 $and$libresoc.v:142302$6238_Y
+ connect \$30 $not$libresoc.v:142303$6239_Y
+ connect \$32 $and$libresoc.v:142304$6240_Y
+ connect \$34 $not$libresoc.v:142305$6241_Y
+ connect \$36 $and$libresoc.v:142306$6242_Y
+ connect \$39 $not$libresoc.v:142307$6243_Y
+ connect \$41 $eq$libresoc.v:142308$6244_Y
+ connect \$43 $and$libresoc.v:142309$6245_Y
+ connect \$45 $or$libresoc.v:142310$6246_Y
+ connect \$47 $not$libresoc.v:142311$6247_Y
+ connect \$49 $eq$libresoc.v:142312$6248_Y
+ connect \$51 $and$libresoc.v:142313$6249_Y
+ connect \$53 $or$libresoc.v:142314$6250_Y
+ connect \$55 $or$libresoc.v:142315$6251_Y
+ connect \$57 $and$libresoc.v:142316$6252_Y
+ connect \$59 $or$libresoc.v:142317$6253_Y
+ connect \$61 $or$libresoc.v:142318$6254_Y
+ connect \$63 $or$libresoc.v:142319$6255_Y
+ connect \$65 $ternary$libresoc.v:142320$6256_Y
+ connect \$67 $ternary$libresoc.v:142321$6257_Y
+ connect \$69 $ternary$libresoc.v:142322$6258_Y
+ connect \$71 $ternary$libresoc.v:142323$6259_Y
+ connect \$74 $add$libresoc.v:142324$6260_Y
+ connect \$76 $and$libresoc.v:142325$6261_Y
+ connect \$78 $not$libresoc.v:142326$6262_Y
+ connect \$80 $and$libresoc.v:142327$6263_Y
+ connect \$82 $not$libresoc.v:142328$6264_Y
+ connect \$84 $and$libresoc.v:142329$6265_Y
+ connect \$86 $and$libresoc.v:142330$6266_Y
+ connect \$88 $and$libresoc.v:142331$6267_Y
+ connect \$8 $or$libresoc.v:142332$6268_Y
+ connect \$90 $or$libresoc.v:142333$6269_Y
+ connect \$93 $or$libresoc.v:142334$6270_Y
+ connect \$92 $not$libresoc.v:142335$6271_Y
+ connect \$96 $and$libresoc.v:142336$6272_Y
+ connect \$98 $not$libresoc.v:142337$6273_Y
connect \$38 \$55
connect \$73 \$74
connect \$166 \$169
connect \reset_o \$10
connect \reset_i \$8
end
-attribute \src "libresoc.v:143199.1-143786.10"
+attribute \src "libresoc.v:142863.1-143450.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask"
attribute \generator "nMigen"
module \left_mask
- attribute \src "libresoc.v:143200.7-143200.20"
+ attribute \src "libresoc.v:142864.7-142864.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire width 64 $0\mask[63:0]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $10\mask[9:9]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $11\mask[10:10]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $12\mask[11:11]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $13\mask[12:12]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $14\mask[13:13]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $15\mask[14:14]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $16\mask[15:15]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $17\mask[16:16]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $18\mask[17:17]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $19\mask[18:18]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $1\mask[0:0]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $20\mask[19:19]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $21\mask[20:20]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $22\mask[21:21]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $23\mask[22:22]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $24\mask[23:23]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $25\mask[24:24]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $26\mask[25:25]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $27\mask[26:26]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $28\mask[27:27]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $29\mask[28:28]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $2\mask[1:1]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $30\mask[29:29]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $31\mask[30:30]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $32\mask[31:31]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $33\mask[32:32]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $34\mask[33:33]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $35\mask[34:34]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $36\mask[35:35]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $37\mask[36:36]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $38\mask[37:37]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $39\mask[38:38]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $3\mask[2:2]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $40\mask[39:39]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $41\mask[40:40]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $42\mask[41:41]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $43\mask[42:42]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $44\mask[43:43]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $45\mask[44:44]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $46\mask[45:45]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $47\mask[46:46]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $48\mask[47:47]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $49\mask[48:48]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $4\mask[3:3]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $50\mask[49:49]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $51\mask[50:50]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $52\mask[51:51]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $53\mask[52:52]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $54\mask[53:53]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $55\mask[54:54]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $56\mask[55:55]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $57\mask[56:56]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $58\mask[57:57]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $59\mask[58:58]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $5\mask[4:4]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $60\mask[59:59]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $61\mask[60:60]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $62\mask[61:61]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $63\mask[62:62]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $64\mask[63:63]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $6\mask[5:5]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $7\mask[6:6]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $8\mask[7:7]
- attribute \src "libresoc.v:143398.3-143785.6"
+ attribute \src "libresoc.v:143062.3-143449.6"
wire $9\mask[8:8]
- attribute \src "libresoc.v:143334.17-143334.96"
- wire $gt$libresoc.v:143334$6510_Y
- attribute \src "libresoc.v:143335.18-143335.98"
- wire $gt$libresoc.v:143335$6511_Y
- attribute \src "libresoc.v:143336.19-143336.99"
- wire $gt$libresoc.v:143336$6512_Y
- attribute \src "libresoc.v:143337.19-143337.99"
- wire $gt$libresoc.v:143337$6513_Y
- attribute \src "libresoc.v:143338.19-143338.99"
- wire $gt$libresoc.v:143338$6514_Y
- attribute \src "libresoc.v:143339.19-143339.99"
- wire $gt$libresoc.v:143339$6515_Y
- attribute \src "libresoc.v:143340.19-143340.99"
- wire $gt$libresoc.v:143340$6516_Y
- attribute \src "libresoc.v:143341.19-143341.99"
- wire $gt$libresoc.v:143341$6517_Y
- attribute \src "libresoc.v:143342.19-143342.99"
- wire $gt$libresoc.v:143342$6518_Y
- attribute \src "libresoc.v:143343.19-143343.99"
- wire $gt$libresoc.v:143343$6519_Y
- attribute \src "libresoc.v:143344.19-143344.99"
- wire $gt$libresoc.v:143344$6520_Y
- attribute \src "libresoc.v:143345.18-143345.97"
- wire $gt$libresoc.v:143345$6521_Y
- attribute \src "libresoc.v:143346.19-143346.99"
- wire $gt$libresoc.v:143346$6522_Y
- attribute \src "libresoc.v:143347.19-143347.99"
- wire $gt$libresoc.v:143347$6523_Y
- attribute \src "libresoc.v:143348.19-143348.99"
- wire $gt$libresoc.v:143348$6524_Y
- attribute \src "libresoc.v:143349.19-143349.99"
- wire $gt$libresoc.v:143349$6525_Y
- attribute \src "libresoc.v:143350.19-143350.99"
- wire $gt$libresoc.v:143350$6526_Y
- attribute \src "libresoc.v:143351.18-143351.97"
- wire $gt$libresoc.v:143351$6527_Y
- attribute \src "libresoc.v:143352.18-143352.97"
- wire $gt$libresoc.v:143352$6528_Y
- attribute \src "libresoc.v:143353.18-143353.97"
- wire $gt$libresoc.v:143353$6529_Y
- attribute \src "libresoc.v:143354.17-143354.96"
- wire $gt$libresoc.v:143354$6530_Y
- attribute \src "libresoc.v:143355.18-143355.97"
- wire $gt$libresoc.v:143355$6531_Y
- attribute \src "libresoc.v:143356.18-143356.97"
- wire $gt$libresoc.v:143356$6532_Y
- attribute \src "libresoc.v:143357.18-143357.97"
- wire $gt$libresoc.v:143357$6533_Y
- attribute \src "libresoc.v:143358.18-143358.97"
- wire $gt$libresoc.v:143358$6534_Y
- attribute \src "libresoc.v:143359.18-143359.97"
- wire $gt$libresoc.v:143359$6535_Y
- attribute \src "libresoc.v:143360.18-143360.97"
- wire $gt$libresoc.v:143360$6536_Y
- attribute \src "libresoc.v:143361.18-143361.97"
- wire $gt$libresoc.v:143361$6537_Y
- attribute \src "libresoc.v:143362.18-143362.98"
- wire $gt$libresoc.v:143362$6538_Y
- attribute \src "libresoc.v:143363.18-143363.98"
- wire $gt$libresoc.v:143363$6539_Y
- attribute \src "libresoc.v:143364.18-143364.98"
- wire $gt$libresoc.v:143364$6540_Y
- attribute \src "libresoc.v:143365.17-143365.96"
- wire $gt$libresoc.v:143365$6541_Y
- attribute \src "libresoc.v:143366.18-143366.98"
- wire $gt$libresoc.v:143366$6542_Y
- attribute \src "libresoc.v:143367.18-143367.98"
- wire $gt$libresoc.v:143367$6543_Y
- attribute \src "libresoc.v:143368.18-143368.98"
- wire $gt$libresoc.v:143368$6544_Y
- attribute \src "libresoc.v:143369.18-143369.98"
- wire $gt$libresoc.v:143369$6545_Y
- attribute \src "libresoc.v:143370.18-143370.98"
- wire $gt$libresoc.v:143370$6546_Y
- attribute \src "libresoc.v:143371.18-143371.98"
- wire $gt$libresoc.v:143371$6547_Y
- attribute \src "libresoc.v:143372.18-143372.98"
- wire $gt$libresoc.v:143372$6548_Y
- attribute \src "libresoc.v:143373.18-143373.98"
- wire $gt$libresoc.v:143373$6549_Y
- attribute \src "libresoc.v:143374.18-143374.98"
- wire $gt$libresoc.v:143374$6550_Y
- attribute \src "libresoc.v:143375.18-143375.98"
- wire $gt$libresoc.v:143375$6551_Y
- attribute \src "libresoc.v:143376.17-143376.96"
- wire $gt$libresoc.v:143376$6552_Y
- attribute \src "libresoc.v:143377.18-143377.98"
- wire $gt$libresoc.v:143377$6553_Y
- attribute \src "libresoc.v:143378.18-143378.98"
- wire $gt$libresoc.v:143378$6554_Y
- attribute \src "libresoc.v:143379.18-143379.98"
- wire $gt$libresoc.v:143379$6555_Y
- attribute \src "libresoc.v:143380.18-143380.98"
- wire $gt$libresoc.v:143380$6556_Y
- attribute \src "libresoc.v:143381.18-143381.98"
- wire $gt$libresoc.v:143381$6557_Y
- attribute \src "libresoc.v:143382.18-143382.98"
- wire $gt$libresoc.v:143382$6558_Y
- attribute \src "libresoc.v:143383.18-143383.98"
- wire $gt$libresoc.v:143383$6559_Y
- attribute \src "libresoc.v:143384.18-143384.98"
- wire $gt$libresoc.v:143384$6560_Y
- attribute \src "libresoc.v:143385.18-143385.98"
- wire $gt$libresoc.v:143385$6561_Y
- attribute \src "libresoc.v:143386.18-143386.98"
- wire $gt$libresoc.v:143386$6562_Y
- attribute \src "libresoc.v:143387.17-143387.96"
- wire $gt$libresoc.v:143387$6563_Y
- attribute \src "libresoc.v:143388.18-143388.98"
- wire $gt$libresoc.v:143388$6564_Y
- attribute \src "libresoc.v:143389.18-143389.98"
- wire $gt$libresoc.v:143389$6565_Y
- attribute \src "libresoc.v:143390.18-143390.98"
- wire $gt$libresoc.v:143390$6566_Y
- attribute \src "libresoc.v:143391.18-143391.98"
- wire $gt$libresoc.v:143391$6567_Y
- attribute \src "libresoc.v:143392.18-143392.98"
- wire $gt$libresoc.v:143392$6568_Y
- attribute \src "libresoc.v:143393.18-143393.98"
- wire $gt$libresoc.v:143393$6569_Y
- attribute \src "libresoc.v:143394.18-143394.98"
- wire $gt$libresoc.v:143394$6570_Y
- attribute \src "libresoc.v:143395.18-143395.98"
- wire $gt$libresoc.v:143395$6571_Y
- attribute \src "libresoc.v:143396.18-143396.98"
- wire $gt$libresoc.v:143396$6572_Y
- attribute \src "libresoc.v:143397.18-143397.98"
- wire $gt$libresoc.v:143397$6573_Y
+ attribute \src "libresoc.v:142998.17-142998.96"
+ wire $gt$libresoc.v:142998$6458_Y
+ attribute \src "libresoc.v:142999.18-142999.98"
+ wire $gt$libresoc.v:142999$6459_Y
+ attribute \src "libresoc.v:143000.19-143000.99"
+ wire $gt$libresoc.v:143000$6460_Y
+ attribute \src "libresoc.v:143001.19-143001.99"
+ wire $gt$libresoc.v:143001$6461_Y
+ attribute \src "libresoc.v:143002.19-143002.99"
+ wire $gt$libresoc.v:143002$6462_Y
+ attribute \src "libresoc.v:143003.19-143003.99"
+ wire $gt$libresoc.v:143003$6463_Y
+ attribute \src "libresoc.v:143004.19-143004.99"
+ wire $gt$libresoc.v:143004$6464_Y
+ attribute \src "libresoc.v:143005.19-143005.99"
+ wire $gt$libresoc.v:143005$6465_Y
+ attribute \src "libresoc.v:143006.19-143006.99"
+ wire $gt$libresoc.v:143006$6466_Y
+ attribute \src "libresoc.v:143007.19-143007.99"
+ wire $gt$libresoc.v:143007$6467_Y
+ attribute \src "libresoc.v:143008.19-143008.99"
+ wire $gt$libresoc.v:143008$6468_Y
+ attribute \src "libresoc.v:143009.18-143009.97"
+ wire $gt$libresoc.v:143009$6469_Y
+ attribute \src "libresoc.v:143010.19-143010.99"
+ wire $gt$libresoc.v:143010$6470_Y
+ attribute \src "libresoc.v:143011.19-143011.99"
+ wire $gt$libresoc.v:143011$6471_Y
+ attribute \src "libresoc.v:143012.19-143012.99"
+ wire $gt$libresoc.v:143012$6472_Y
+ attribute \src "libresoc.v:143013.19-143013.99"
+ wire $gt$libresoc.v:143013$6473_Y
+ attribute \src "libresoc.v:143014.19-143014.99"
+ wire $gt$libresoc.v:143014$6474_Y
+ attribute \src "libresoc.v:143015.18-143015.97"
+ wire $gt$libresoc.v:143015$6475_Y
+ attribute \src "libresoc.v:143016.18-143016.97"
+ wire $gt$libresoc.v:143016$6476_Y
+ attribute \src "libresoc.v:143017.18-143017.97"
+ wire $gt$libresoc.v:143017$6477_Y
+ attribute \src "libresoc.v:143018.17-143018.96"
+ wire $gt$libresoc.v:143018$6478_Y
+ attribute \src "libresoc.v:143019.18-143019.97"
+ wire $gt$libresoc.v:143019$6479_Y
+ attribute \src "libresoc.v:143020.18-143020.97"
+ wire $gt$libresoc.v:143020$6480_Y
+ attribute \src "libresoc.v:143021.18-143021.97"
+ wire $gt$libresoc.v:143021$6481_Y
+ attribute \src "libresoc.v:143022.18-143022.97"
+ wire $gt$libresoc.v:143022$6482_Y
+ attribute \src "libresoc.v:143023.18-143023.97"
+ wire $gt$libresoc.v:143023$6483_Y
+ attribute \src "libresoc.v:143024.18-143024.97"
+ wire $gt$libresoc.v:143024$6484_Y
+ attribute \src "libresoc.v:143025.18-143025.97"
+ wire $gt$libresoc.v:143025$6485_Y
+ attribute \src "libresoc.v:143026.18-143026.98"
+ wire $gt$libresoc.v:143026$6486_Y
+ attribute \src "libresoc.v:143027.18-143027.98"
+ wire $gt$libresoc.v:143027$6487_Y
+ attribute \src "libresoc.v:143028.18-143028.98"
+ wire $gt$libresoc.v:143028$6488_Y
+ attribute \src "libresoc.v:143029.17-143029.96"
+ wire $gt$libresoc.v:143029$6489_Y
+ attribute \src "libresoc.v:143030.18-143030.98"
+ wire $gt$libresoc.v:143030$6490_Y
+ attribute \src "libresoc.v:143031.18-143031.98"
+ wire $gt$libresoc.v:143031$6491_Y
+ attribute \src "libresoc.v:143032.18-143032.98"
+ wire $gt$libresoc.v:143032$6492_Y
+ attribute \src "libresoc.v:143033.18-143033.98"
+ wire $gt$libresoc.v:143033$6493_Y
+ attribute \src "libresoc.v:143034.18-143034.98"
+ wire $gt$libresoc.v:143034$6494_Y
+ attribute \src "libresoc.v:143035.18-143035.98"
+ wire $gt$libresoc.v:143035$6495_Y
+ attribute \src "libresoc.v:143036.18-143036.98"
+ wire $gt$libresoc.v:143036$6496_Y
+ attribute \src "libresoc.v:143037.18-143037.98"
+ wire $gt$libresoc.v:143037$6497_Y
+ attribute \src "libresoc.v:143038.18-143038.98"
+ wire $gt$libresoc.v:143038$6498_Y
+ attribute \src "libresoc.v:143039.18-143039.98"
+ wire $gt$libresoc.v:143039$6499_Y
+ attribute \src "libresoc.v:143040.17-143040.96"
+ wire $gt$libresoc.v:143040$6500_Y
+ attribute \src "libresoc.v:143041.18-143041.98"
+ wire $gt$libresoc.v:143041$6501_Y
+ attribute \src "libresoc.v:143042.18-143042.98"
+ wire $gt$libresoc.v:143042$6502_Y
+ attribute \src "libresoc.v:143043.18-143043.98"
+ wire $gt$libresoc.v:143043$6503_Y
+ attribute \src "libresoc.v:143044.18-143044.98"
+ wire $gt$libresoc.v:143044$6504_Y
+ attribute \src "libresoc.v:143045.18-143045.98"
+ wire $gt$libresoc.v:143045$6505_Y
+ attribute \src "libresoc.v:143046.18-143046.98"
+ wire $gt$libresoc.v:143046$6506_Y
+ attribute \src "libresoc.v:143047.18-143047.98"
+ wire $gt$libresoc.v:143047$6507_Y
+ attribute \src "libresoc.v:143048.18-143048.98"
+ wire $gt$libresoc.v:143048$6508_Y
+ attribute \src "libresoc.v:143049.18-143049.98"
+ wire $gt$libresoc.v:143049$6509_Y
+ attribute \src "libresoc.v:143050.18-143050.98"
+ wire $gt$libresoc.v:143050$6510_Y
+ attribute \src "libresoc.v:143051.17-143051.96"
+ wire $gt$libresoc.v:143051$6511_Y
+ attribute \src "libresoc.v:143052.18-143052.98"
+ wire $gt$libresoc.v:143052$6512_Y
+ attribute \src "libresoc.v:143053.18-143053.98"
+ wire $gt$libresoc.v:143053$6513_Y
+ attribute \src "libresoc.v:143054.18-143054.98"
+ wire $gt$libresoc.v:143054$6514_Y
+ attribute \src "libresoc.v:143055.18-143055.98"
+ wire $gt$libresoc.v:143055$6515_Y
+ attribute \src "libresoc.v:143056.18-143056.98"
+ wire $gt$libresoc.v:143056$6516_Y
+ attribute \src "libresoc.v:143057.18-143057.98"
+ wire $gt$libresoc.v:143057$6517_Y
+ attribute \src "libresoc.v:143058.18-143058.98"
+ wire $gt$libresoc.v:143058$6518_Y
+ attribute \src "libresoc.v:143059.18-143059.98"
+ wire $gt$libresoc.v:143059$6519_Y
+ attribute \src "libresoc.v:143060.18-143060.98"
+ wire $gt$libresoc.v:143060$6520_Y
+ attribute \src "libresoc.v:143061.18-143061.98"
+ wire $gt$libresoc.v:143061$6521_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$99
- attribute \src "libresoc.v:143200.7-143200.15"
+ attribute \src "libresoc.v:142864.7-142864.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20"
wire width 64 output 1 \mask
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19"
wire width 7 input 2 \shift
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143334$6510
+ cell $gt $gt$libresoc.v:142998$6458
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'100
- connect \Y $gt$libresoc.v:143334$6510_Y
+ connect \Y $gt$libresoc.v:142998$6458_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143335$6511
+ cell $gt $gt$libresoc.v:142999$6459
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110001
- connect \Y $gt$libresoc.v:143335$6511_Y
+ connect \Y $gt$libresoc.v:142999$6459_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143336$6512
+ cell $gt $gt$libresoc.v:143000$6460
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110010
- connect \Y $gt$libresoc.v:143336$6512_Y
+ connect \Y $gt$libresoc.v:143000$6460_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143337$6513
+ cell $gt $gt$libresoc.v:143001$6461
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110011
- connect \Y $gt$libresoc.v:143337$6513_Y
+ connect \Y $gt$libresoc.v:143001$6461_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143338$6514
+ cell $gt $gt$libresoc.v:143002$6462
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110100
- connect \Y $gt$libresoc.v:143338$6514_Y
+ connect \Y $gt$libresoc.v:143002$6462_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143339$6515
+ cell $gt $gt$libresoc.v:143003$6463
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110101
- connect \Y $gt$libresoc.v:143339$6515_Y
+ connect \Y $gt$libresoc.v:143003$6463_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143340$6516
+ cell $gt $gt$libresoc.v:143004$6464
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110110
- connect \Y $gt$libresoc.v:143340$6516_Y
+ connect \Y $gt$libresoc.v:143004$6464_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143341$6517
+ cell $gt $gt$libresoc.v:143005$6465
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110111
- connect \Y $gt$libresoc.v:143341$6517_Y
+ connect \Y $gt$libresoc.v:143005$6465_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143342$6518
+ cell $gt $gt$libresoc.v:143006$6466
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111000
- connect \Y $gt$libresoc.v:143342$6518_Y
+ connect \Y $gt$libresoc.v:143006$6466_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143343$6519
+ cell $gt $gt$libresoc.v:143007$6467
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111001
- connect \Y $gt$libresoc.v:143343$6519_Y
+ connect \Y $gt$libresoc.v:143007$6467_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143344$6520
+ cell $gt $gt$libresoc.v:143008$6468
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111010
- connect \Y $gt$libresoc.v:143344$6520_Y
+ connect \Y $gt$libresoc.v:143008$6468_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143345$6521
+ cell $gt $gt$libresoc.v:143009$6469
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'101
- connect \Y $gt$libresoc.v:143345$6521_Y
+ connect \Y $gt$libresoc.v:143009$6469_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143346$6522
+ cell $gt $gt$libresoc.v:143010$6470
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111011
- connect \Y $gt$libresoc.v:143346$6522_Y
+ connect \Y $gt$libresoc.v:143010$6470_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143347$6523
+ cell $gt $gt$libresoc.v:143011$6471
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111100
- connect \Y $gt$libresoc.v:143347$6523_Y
+ connect \Y $gt$libresoc.v:143011$6471_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143348$6524
+ cell $gt $gt$libresoc.v:143012$6472
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111101
- connect \Y $gt$libresoc.v:143348$6524_Y
+ connect \Y $gt$libresoc.v:143012$6472_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143349$6525
+ cell $gt $gt$libresoc.v:143013$6473
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111110
- connect \Y $gt$libresoc.v:143349$6525_Y
+ connect \Y $gt$libresoc.v:143013$6473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143350$6526
+ cell $gt $gt$libresoc.v:143014$6474
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111111
- connect \Y $gt$libresoc.v:143350$6526_Y
+ connect \Y $gt$libresoc.v:143014$6474_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143351$6527
+ cell $gt $gt$libresoc.v:143015$6475
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'110
- connect \Y $gt$libresoc.v:143351$6527_Y
+ connect \Y $gt$libresoc.v:143015$6475_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143352$6528
+ cell $gt $gt$libresoc.v:143016$6476
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'111
- connect \Y $gt$libresoc.v:143352$6528_Y
+ connect \Y $gt$libresoc.v:143016$6476_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143353$6529
+ cell $gt $gt$libresoc.v:143017$6477
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1000
- connect \Y $gt$libresoc.v:143353$6529_Y
+ connect \Y $gt$libresoc.v:143017$6477_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143354$6530
+ cell $gt $gt$libresoc.v:143018$6478
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'0
- connect \Y $gt$libresoc.v:143354$6530_Y
+ connect \Y $gt$libresoc.v:143018$6478_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143355$6531
+ cell $gt $gt$libresoc.v:143019$6479
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1001
- connect \Y $gt$libresoc.v:143355$6531_Y
+ connect \Y $gt$libresoc.v:143019$6479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143356$6532
+ cell $gt $gt$libresoc.v:143020$6480
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1010
- connect \Y $gt$libresoc.v:143356$6532_Y
+ connect \Y $gt$libresoc.v:143020$6480_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143357$6533
+ cell $gt $gt$libresoc.v:143021$6481
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1011
- connect \Y $gt$libresoc.v:143357$6533_Y
+ connect \Y $gt$libresoc.v:143021$6481_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143358$6534
+ cell $gt $gt$libresoc.v:143022$6482
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1100
- connect \Y $gt$libresoc.v:143358$6534_Y
+ connect \Y $gt$libresoc.v:143022$6482_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143359$6535
+ cell $gt $gt$libresoc.v:143023$6483
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1101
- connect \Y $gt$libresoc.v:143359$6535_Y
+ connect \Y $gt$libresoc.v:143023$6483_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143360$6536
+ cell $gt $gt$libresoc.v:143024$6484
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1110
- connect \Y $gt$libresoc.v:143360$6536_Y
+ connect \Y $gt$libresoc.v:143024$6484_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143361$6537
+ cell $gt $gt$libresoc.v:143025$6485
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1111
- connect \Y $gt$libresoc.v:143361$6537_Y
+ connect \Y $gt$libresoc.v:143025$6485_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143362$6538
+ cell $gt $gt$libresoc.v:143026$6486
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10000
- connect \Y $gt$libresoc.v:143362$6538_Y
+ connect \Y $gt$libresoc.v:143026$6486_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143363$6539
+ cell $gt $gt$libresoc.v:143027$6487
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10001
- connect \Y $gt$libresoc.v:143363$6539_Y
+ connect \Y $gt$libresoc.v:143027$6487_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143364$6540
+ cell $gt $gt$libresoc.v:143028$6488
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10010
- connect \Y $gt$libresoc.v:143364$6540_Y
+ connect \Y $gt$libresoc.v:143028$6488_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143365$6541
+ cell $gt $gt$libresoc.v:143029$6489
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'1
- connect \Y $gt$libresoc.v:143365$6541_Y
+ connect \Y $gt$libresoc.v:143029$6489_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143366$6542
+ cell $gt $gt$libresoc.v:143030$6490
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10011
- connect \Y $gt$libresoc.v:143366$6542_Y
+ connect \Y $gt$libresoc.v:143030$6490_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143367$6543
+ cell $gt $gt$libresoc.v:143031$6491
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10100
- connect \Y $gt$libresoc.v:143367$6543_Y
+ connect \Y $gt$libresoc.v:143031$6491_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143368$6544
+ cell $gt $gt$libresoc.v:143032$6492
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10101
- connect \Y $gt$libresoc.v:143368$6544_Y
+ connect \Y $gt$libresoc.v:143032$6492_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143369$6545
+ cell $gt $gt$libresoc.v:143033$6493
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10110
- connect \Y $gt$libresoc.v:143369$6545_Y
+ connect \Y $gt$libresoc.v:143033$6493_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143370$6546
+ cell $gt $gt$libresoc.v:143034$6494
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10111
- connect \Y $gt$libresoc.v:143370$6546_Y
+ connect \Y $gt$libresoc.v:143034$6494_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143371$6547
+ cell $gt $gt$libresoc.v:143035$6495
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11000
- connect \Y $gt$libresoc.v:143371$6547_Y
+ connect \Y $gt$libresoc.v:143035$6495_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143372$6548
+ cell $gt $gt$libresoc.v:143036$6496
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11001
- connect \Y $gt$libresoc.v:143372$6548_Y
+ connect \Y $gt$libresoc.v:143036$6496_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143373$6549
+ cell $gt $gt$libresoc.v:143037$6497
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11010
- connect \Y $gt$libresoc.v:143373$6549_Y
+ connect \Y $gt$libresoc.v:143037$6497_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143374$6550
+ cell $gt $gt$libresoc.v:143038$6498
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11011
- connect \Y $gt$libresoc.v:143374$6550_Y
+ connect \Y $gt$libresoc.v:143038$6498_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143375$6551
+ cell $gt $gt$libresoc.v:143039$6499
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11100
- connect \Y $gt$libresoc.v:143375$6551_Y
+ connect \Y $gt$libresoc.v:143039$6499_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143376$6552
+ cell $gt $gt$libresoc.v:143040$6500
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'10
- connect \Y $gt$libresoc.v:143376$6552_Y
+ connect \Y $gt$libresoc.v:143040$6500_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143377$6553
+ cell $gt $gt$libresoc.v:143041$6501
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11101
- connect \Y $gt$libresoc.v:143377$6553_Y
+ connect \Y $gt$libresoc.v:143041$6501_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143378$6554
+ cell $gt $gt$libresoc.v:143042$6502
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11110
- connect \Y $gt$libresoc.v:143378$6554_Y
+ connect \Y $gt$libresoc.v:143042$6502_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143379$6555
+ cell $gt $gt$libresoc.v:143043$6503
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11111
- connect \Y $gt$libresoc.v:143379$6555_Y
+ connect \Y $gt$libresoc.v:143043$6503_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143380$6556
+ cell $gt $gt$libresoc.v:143044$6504
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100000
- connect \Y $gt$libresoc.v:143380$6556_Y
+ connect \Y $gt$libresoc.v:143044$6504_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143381$6557
+ cell $gt $gt$libresoc.v:143045$6505
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100001
- connect \Y $gt$libresoc.v:143381$6557_Y
+ connect \Y $gt$libresoc.v:143045$6505_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143382$6558
+ cell $gt $gt$libresoc.v:143046$6506
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100010
- connect \Y $gt$libresoc.v:143382$6558_Y
+ connect \Y $gt$libresoc.v:143046$6506_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143383$6559
+ cell $gt $gt$libresoc.v:143047$6507
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100011
- connect \Y $gt$libresoc.v:143383$6559_Y
+ connect \Y $gt$libresoc.v:143047$6507_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143384$6560
+ cell $gt $gt$libresoc.v:143048$6508
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100100
- connect \Y $gt$libresoc.v:143384$6560_Y
+ connect \Y $gt$libresoc.v:143048$6508_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143385$6561
+ cell $gt $gt$libresoc.v:143049$6509
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100101
- connect \Y $gt$libresoc.v:143385$6561_Y
+ connect \Y $gt$libresoc.v:143049$6509_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143386$6562
+ cell $gt $gt$libresoc.v:143050$6510
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100110
- connect \Y $gt$libresoc.v:143386$6562_Y
+ connect \Y $gt$libresoc.v:143050$6510_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143387$6563
+ cell $gt $gt$libresoc.v:143051$6511
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'11
- connect \Y $gt$libresoc.v:143387$6563_Y
+ connect \Y $gt$libresoc.v:143051$6511_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143388$6564
+ cell $gt $gt$libresoc.v:143052$6512
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100111
- connect \Y $gt$libresoc.v:143388$6564_Y
+ connect \Y $gt$libresoc.v:143052$6512_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143389$6565
+ cell $gt $gt$libresoc.v:143053$6513
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101000
- connect \Y $gt$libresoc.v:143389$6565_Y
+ connect \Y $gt$libresoc.v:143053$6513_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143390$6566
+ cell $gt $gt$libresoc.v:143054$6514
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101001
- connect \Y $gt$libresoc.v:143390$6566_Y
+ connect \Y $gt$libresoc.v:143054$6514_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143391$6567
+ cell $gt $gt$libresoc.v:143055$6515
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101010
- connect \Y $gt$libresoc.v:143391$6567_Y
+ connect \Y $gt$libresoc.v:143055$6515_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143392$6568
+ cell $gt $gt$libresoc.v:143056$6516
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101011
- connect \Y $gt$libresoc.v:143392$6568_Y
+ connect \Y $gt$libresoc.v:143056$6516_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143393$6569
+ cell $gt $gt$libresoc.v:143057$6517
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101100
- connect \Y $gt$libresoc.v:143393$6569_Y
+ connect \Y $gt$libresoc.v:143057$6517_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143394$6570
+ cell $gt $gt$libresoc.v:143058$6518
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101101
- connect \Y $gt$libresoc.v:143394$6570_Y
+ connect \Y $gt$libresoc.v:143058$6518_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143395$6571
+ cell $gt $gt$libresoc.v:143059$6519
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101110
- connect \Y $gt$libresoc.v:143395$6571_Y
+ connect \Y $gt$libresoc.v:143059$6519_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143396$6572
+ cell $gt $gt$libresoc.v:143060$6520
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101111
- connect \Y $gt$libresoc.v:143396$6572_Y
+ connect \Y $gt$libresoc.v:143060$6520_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:143397$6573
+ cell $gt $gt$libresoc.v:143061$6521
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110000
- connect \Y $gt$libresoc.v:143397$6573_Y
+ connect \Y $gt$libresoc.v:143061$6521_Y
end
- attribute \src "libresoc.v:143200.7-143200.20"
- process $proc$libresoc.v:143200$6575
+ attribute \src "libresoc.v:142864.7-142864.20"
+ process $proc$libresoc.v:142864$6523
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:143398.3-143785.6"
- process $proc$libresoc.v:143398$6574
+ attribute \src "libresoc.v:143062.3-143449.6"
+ process $proc$libresoc.v:143062$6522
assign { } { }
assign { } { }
assign $0\mask[63:0] [0] $1\mask[0:0]
assign $0\mask[63:0] [61] $62\mask[61:61]
assign $0\mask[63:0] [62] $63\mask[62:62]
assign $0\mask[63:0] [63] $64\mask[63:63]
- attribute \src "libresoc.v:143399.5-143399.29"
+ attribute \src "libresoc.v:143063.5-143063.29"
switch \initial
- attribute \src "libresoc.v:143399.9-143399.17"
+ attribute \src "libresoc.v:143063.9-143063.17"
case 1'1
case
end
sync always
update \mask $0\mask[63:0]
end
- connect \$9 $gt$libresoc.v:143334$6510_Y
- connect \$99 $gt$libresoc.v:143335$6511_Y
- connect \$101 $gt$libresoc.v:143336$6512_Y
- connect \$103 $gt$libresoc.v:143337$6513_Y
- connect \$105 $gt$libresoc.v:143338$6514_Y
- connect \$107 $gt$libresoc.v:143339$6515_Y
- connect \$109 $gt$libresoc.v:143340$6516_Y
- connect \$111 $gt$libresoc.v:143341$6517_Y
- connect \$113 $gt$libresoc.v:143342$6518_Y
- connect \$115 $gt$libresoc.v:143343$6519_Y
- connect \$117 $gt$libresoc.v:143344$6520_Y
- connect \$11 $gt$libresoc.v:143345$6521_Y
- connect \$119 $gt$libresoc.v:143346$6522_Y
- connect \$121 $gt$libresoc.v:143347$6523_Y
- connect \$123 $gt$libresoc.v:143348$6524_Y
- connect \$125 $gt$libresoc.v:143349$6525_Y
- connect \$127 $gt$libresoc.v:143350$6526_Y
- connect \$13 $gt$libresoc.v:143351$6527_Y
- connect \$15 $gt$libresoc.v:143352$6528_Y
- connect \$17 $gt$libresoc.v:143353$6529_Y
- connect \$1 $gt$libresoc.v:143354$6530_Y
- connect \$19 $gt$libresoc.v:143355$6531_Y
- connect \$21 $gt$libresoc.v:143356$6532_Y
- connect \$23 $gt$libresoc.v:143357$6533_Y
- connect \$25 $gt$libresoc.v:143358$6534_Y
- connect \$27 $gt$libresoc.v:143359$6535_Y
- connect \$29 $gt$libresoc.v:143360$6536_Y
- connect \$31 $gt$libresoc.v:143361$6537_Y
- connect \$33 $gt$libresoc.v:143362$6538_Y
- connect \$35 $gt$libresoc.v:143363$6539_Y
- connect \$37 $gt$libresoc.v:143364$6540_Y
- connect \$3 $gt$libresoc.v:143365$6541_Y
- connect \$39 $gt$libresoc.v:143366$6542_Y
- connect \$41 $gt$libresoc.v:143367$6543_Y
- connect \$43 $gt$libresoc.v:143368$6544_Y
- connect \$45 $gt$libresoc.v:143369$6545_Y
- connect \$47 $gt$libresoc.v:143370$6546_Y
- connect \$49 $gt$libresoc.v:143371$6547_Y
- connect \$51 $gt$libresoc.v:143372$6548_Y
- connect \$53 $gt$libresoc.v:143373$6549_Y
- connect \$55 $gt$libresoc.v:143374$6550_Y
- connect \$57 $gt$libresoc.v:143375$6551_Y
- connect \$5 $gt$libresoc.v:143376$6552_Y
- connect \$59 $gt$libresoc.v:143377$6553_Y
- connect \$61 $gt$libresoc.v:143378$6554_Y
- connect \$63 $gt$libresoc.v:143379$6555_Y
- connect \$65 $gt$libresoc.v:143380$6556_Y
- connect \$67 $gt$libresoc.v:143381$6557_Y
- connect \$69 $gt$libresoc.v:143382$6558_Y
- connect \$71 $gt$libresoc.v:143383$6559_Y
- connect \$73 $gt$libresoc.v:143384$6560_Y
- connect \$75 $gt$libresoc.v:143385$6561_Y
- connect \$77 $gt$libresoc.v:143386$6562_Y
- connect \$7 $gt$libresoc.v:143387$6563_Y
- connect \$79 $gt$libresoc.v:143388$6564_Y
- connect \$81 $gt$libresoc.v:143389$6565_Y
- connect \$83 $gt$libresoc.v:143390$6566_Y
- connect \$85 $gt$libresoc.v:143391$6567_Y
- connect \$87 $gt$libresoc.v:143392$6568_Y
- connect \$89 $gt$libresoc.v:143393$6569_Y
- connect \$91 $gt$libresoc.v:143394$6570_Y
- connect \$93 $gt$libresoc.v:143395$6571_Y
- connect \$95 $gt$libresoc.v:143396$6572_Y
- connect \$97 $gt$libresoc.v:143397$6573_Y
+ connect \$9 $gt$libresoc.v:142998$6458_Y
+ connect \$99 $gt$libresoc.v:142999$6459_Y
+ connect \$101 $gt$libresoc.v:143000$6460_Y
+ connect \$103 $gt$libresoc.v:143001$6461_Y
+ connect \$105 $gt$libresoc.v:143002$6462_Y
+ connect \$107 $gt$libresoc.v:143003$6463_Y
+ connect \$109 $gt$libresoc.v:143004$6464_Y
+ connect \$111 $gt$libresoc.v:143005$6465_Y
+ connect \$113 $gt$libresoc.v:143006$6466_Y
+ connect \$115 $gt$libresoc.v:143007$6467_Y
+ connect \$117 $gt$libresoc.v:143008$6468_Y
+ connect \$11 $gt$libresoc.v:143009$6469_Y
+ connect \$119 $gt$libresoc.v:143010$6470_Y
+ connect \$121 $gt$libresoc.v:143011$6471_Y
+ connect \$123 $gt$libresoc.v:143012$6472_Y
+ connect \$125 $gt$libresoc.v:143013$6473_Y
+ connect \$127 $gt$libresoc.v:143014$6474_Y
+ connect \$13 $gt$libresoc.v:143015$6475_Y
+ connect \$15 $gt$libresoc.v:143016$6476_Y
+ connect \$17 $gt$libresoc.v:143017$6477_Y
+ connect \$1 $gt$libresoc.v:143018$6478_Y
+ connect \$19 $gt$libresoc.v:143019$6479_Y
+ connect \$21 $gt$libresoc.v:143020$6480_Y
+ connect \$23 $gt$libresoc.v:143021$6481_Y
+ connect \$25 $gt$libresoc.v:143022$6482_Y
+ connect \$27 $gt$libresoc.v:143023$6483_Y
+ connect \$29 $gt$libresoc.v:143024$6484_Y
+ connect \$31 $gt$libresoc.v:143025$6485_Y
+ connect \$33 $gt$libresoc.v:143026$6486_Y
+ connect \$35 $gt$libresoc.v:143027$6487_Y
+ connect \$37 $gt$libresoc.v:143028$6488_Y
+ connect \$3 $gt$libresoc.v:143029$6489_Y
+ connect \$39 $gt$libresoc.v:143030$6490_Y
+ connect \$41 $gt$libresoc.v:143031$6491_Y
+ connect \$43 $gt$libresoc.v:143032$6492_Y
+ connect \$45 $gt$libresoc.v:143033$6493_Y
+ connect \$47 $gt$libresoc.v:143034$6494_Y
+ connect \$49 $gt$libresoc.v:143035$6495_Y
+ connect \$51 $gt$libresoc.v:143036$6496_Y
+ connect \$53 $gt$libresoc.v:143037$6497_Y
+ connect \$55 $gt$libresoc.v:143038$6498_Y
+ connect \$57 $gt$libresoc.v:143039$6499_Y
+ connect \$5 $gt$libresoc.v:143040$6500_Y
+ connect \$59 $gt$libresoc.v:143041$6501_Y
+ connect \$61 $gt$libresoc.v:143042$6502_Y
+ connect \$63 $gt$libresoc.v:143043$6503_Y
+ connect \$65 $gt$libresoc.v:143044$6504_Y
+ connect \$67 $gt$libresoc.v:143045$6505_Y
+ connect \$69 $gt$libresoc.v:143046$6506_Y
+ connect \$71 $gt$libresoc.v:143047$6507_Y
+ connect \$73 $gt$libresoc.v:143048$6508_Y
+ connect \$75 $gt$libresoc.v:143049$6509_Y
+ connect \$77 $gt$libresoc.v:143050$6510_Y
+ connect \$7 $gt$libresoc.v:143051$6511_Y
+ connect \$79 $gt$libresoc.v:143052$6512_Y
+ connect \$81 $gt$libresoc.v:143053$6513_Y
+ connect \$83 $gt$libresoc.v:143054$6514_Y
+ connect \$85 $gt$libresoc.v:143055$6515_Y
+ connect \$87 $gt$libresoc.v:143056$6516_Y
+ connect \$89 $gt$libresoc.v:143057$6517_Y
+ connect \$91 $gt$libresoc.v:143058$6518_Y
+ connect \$93 $gt$libresoc.v:143059$6519_Y
+ connect \$95 $gt$libresoc.v:143060$6520_Y
+ connect \$97 $gt$libresoc.v:143061$6521_Y
end
-attribute \src "libresoc.v:143790.1-143819.10"
+attribute \src "libresoc.v:143454.1-143483.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp"
attribute \generator "nMigen"
module \lenexp
- attribute \src "libresoc.v:143814.17-143814.101"
- wire width 64 $extend$libresoc.v:143814$6579_Y
- attribute \src "libresoc.v:143814.17-143814.101"
- wire width 64 $pos$libresoc.v:143814$6580_Y
- attribute \src "libresoc.v:143811.17-143811.111"
- wire width 20 $sshl$libresoc.v:143811$6576_Y
- attribute \src "libresoc.v:143813.17-143813.113"
- wire width 32 $sshl$libresoc.v:143813$6578_Y
- attribute \src "libresoc.v:143812.17-143812.107"
- wire width 21 $sub$libresoc.v:143812$6577_Y
+ attribute \src "libresoc.v:143478.17-143478.101"
+ wire width 64 $extend$libresoc.v:143478$6527_Y
+ attribute \src "libresoc.v:143478.17-143478.101"
+ wire width 64 $pos$libresoc.v:143478$6528_Y
+ attribute \src "libresoc.v:143475.17-143475.111"
+ wire width 20 $sshl$libresoc.v:143475$6524_Y
+ attribute \src "libresoc.v:143477.17-143477.113"
+ wire width 32 $sshl$libresoc.v:143477$6526_Y
+ attribute \src "libresoc.v:143476.17-143476.107"
+ wire width 21 $sub$libresoc.v:143476$6525_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
wire width 21 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
wire width 176 output 3 \rexp_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $pos $extend$libresoc.v:143814$6579
+ cell $pos $extend$libresoc.v:143478$6527
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \$7
- connect \Y $extend$libresoc.v:143814$6579_Y
+ connect \Y $extend$libresoc.v:143478$6527_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $pos $pos$libresoc.v:143814$6580
+ cell $pos $pos$libresoc.v:143478$6528
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:143814$6579_Y
- connect \Y $pos$libresoc.v:143814$6580_Y
+ connect \A $extend$libresoc.v:143478$6527_Y
+ connect \Y $pos$libresoc.v:143478$6528_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $sshl $sshl$libresoc.v:143811$6576
+ cell $sshl $sshl$libresoc.v:143475$6524
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A 5'00001
connect \B \len_i
- connect \Y $sshl$libresoc.v:143811$6576_Y
+ connect \Y $sshl$libresoc.v:143475$6524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $sshl $sshl$libresoc.v:143813$6578
+ cell $sshl $sshl$libresoc.v:143477$6526
parameter \A_SIGNED 0
parameter \A_WIDTH 17
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \binlen
connect \B \addr_i
- connect \Y $sshl$libresoc.v:143813$6578_Y
+ connect \Y $sshl$libresoc.v:143477$6526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $sub $sub$libresoc.v:143812$6577
+ cell $sub $sub$libresoc.v:143476$6525
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 21
connect \A \$2
connect \B 1'1
- connect \Y $sub$libresoc.v:143812$6577_Y
+ connect \Y $sub$libresoc.v:143476$6525_Y
end
- connect \$2 $sshl$libresoc.v:143811$6576_Y
- connect \$4 $sub$libresoc.v:143812$6577_Y
- connect \$7 $sshl$libresoc.v:143813$6578_Y
- connect \$6 $pos$libresoc.v:143814$6580_Y
+ connect \$2 $sshl$libresoc.v:143475$6524_Y
+ connect \$4 $sub$libresoc.v:143476$6525_Y
+ connect \$7 $sshl$libresoc.v:143477$6526_Y
+ connect \$6 $pos$libresoc.v:143478$6528_Y
connect \$1 \$4
connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] }
connect \lexp_o \$6
connect \binlen \$4 [16:0]
end
-attribute \src "libresoc.v:143823.1-143881.10"
+attribute \src "libresoc.v:143487.1-143545.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l"
attribute \generator "nMigen"
module \lod_l
- attribute \src "libresoc.v:143824.7-143824.20"
+ attribute \src "libresoc.v:143488.7-143488.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:143869.3-143877.6"
- wire $0\q_int$next[0:0]$6591
- attribute \src "libresoc.v:143867.3-143868.27"
+ attribute \src "libresoc.v:143533.3-143541.6"
+ wire $0\q_int$next[0:0]$6539
+ attribute \src "libresoc.v:143531.3-143532.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:143869.3-143877.6"
- wire $1\q_int$next[0:0]$6592
- attribute \src "libresoc.v:143846.7-143846.19"
+ attribute \src "libresoc.v:143533.3-143541.6"
+ wire $1\q_int$next[0:0]$6540
+ attribute \src "libresoc.v:143510.7-143510.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:143859.17-143859.96"
- wire $and$libresoc.v:143859$6581_Y
- attribute \src "libresoc.v:143864.17-143864.96"
- wire $and$libresoc.v:143864$6586_Y
- attribute \src "libresoc.v:143861.18-143861.93"
- wire $not$libresoc.v:143861$6583_Y
- attribute \src "libresoc.v:143863.17-143863.92"
- wire $not$libresoc.v:143863$6585_Y
- attribute \src "libresoc.v:143866.17-143866.92"
- wire $not$libresoc.v:143866$6588_Y
- attribute \src "libresoc.v:143860.18-143860.98"
- wire $or$libresoc.v:143860$6582_Y
- attribute \src "libresoc.v:143862.18-143862.99"
- wire $or$libresoc.v:143862$6584_Y
- attribute \src "libresoc.v:143865.17-143865.97"
- wire $or$libresoc.v:143865$6587_Y
+ attribute \src "libresoc.v:143523.17-143523.96"
+ wire $and$libresoc.v:143523$6529_Y
+ attribute \src "libresoc.v:143528.17-143528.96"
+ wire $and$libresoc.v:143528$6534_Y
+ attribute \src "libresoc.v:143525.18-143525.93"
+ wire $not$libresoc.v:143525$6531_Y
+ attribute \src "libresoc.v:143527.17-143527.92"
+ wire $not$libresoc.v:143527$6533_Y
+ attribute \src "libresoc.v:143530.17-143530.92"
+ wire $not$libresoc.v:143530$6536_Y
+ attribute \src "libresoc.v:143524.18-143524.98"
+ wire $or$libresoc.v:143524$6530_Y
+ attribute \src "libresoc.v:143526.18-143526.99"
+ wire $or$libresoc.v:143526$6532_Y
+ attribute \src "libresoc.v:143529.17-143529.97"
+ wire $or$libresoc.v:143529$6535_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:143824.7-143824.15"
+ attribute \src "libresoc.v:143488.7-143488.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_lod
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:143859$6581
+ cell $and $and$libresoc.v:143523$6529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:143859$6581_Y
+ connect \Y $and$libresoc.v:143523$6529_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:143864$6586
+ cell $and $and$libresoc.v:143528$6534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:143864$6586_Y
+ connect \Y $and$libresoc.v:143528$6534_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:143861$6583
+ cell $not $not$libresoc.v:143525$6531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_lod
- connect \Y $not$libresoc.v:143861$6583_Y
+ connect \Y $not$libresoc.v:143525$6531_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:143863$6585
+ cell $not $not$libresoc.v:143527$6533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lod
- connect \Y $not$libresoc.v:143863$6585_Y
+ connect \Y $not$libresoc.v:143527$6533_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:143866$6588
+ cell $not $not$libresoc.v:143530$6536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lod
- connect \Y $not$libresoc.v:143866$6588_Y
+ connect \Y $not$libresoc.v:143530$6536_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:143860$6582
+ cell $or $or$libresoc.v:143524$6530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_lod
- connect \Y $or$libresoc.v:143860$6582_Y
+ connect \Y $or$libresoc.v:143524$6530_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:143862$6584
+ cell $or $or$libresoc.v:143526$6532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_lod
connect \B \q_int
- connect \Y $or$libresoc.v:143862$6584_Y
+ connect \Y $or$libresoc.v:143526$6532_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:143865$6587
+ cell $or $or$libresoc.v:143529$6535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_lod
- connect \Y $or$libresoc.v:143865$6587_Y
+ connect \Y $or$libresoc.v:143529$6535_Y
end
- attribute \src "libresoc.v:143824.7-143824.20"
- process $proc$libresoc.v:143824$6593
+ attribute \src "libresoc.v:143488.7-143488.20"
+ process $proc$libresoc.v:143488$6541
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:143846.7-143846.19"
- process $proc$libresoc.v:143846$6594
+ attribute \src "libresoc.v:143510.7-143510.19"
+ process $proc$libresoc.v:143510$6542
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:143867.3-143868.27"
- process $proc$libresoc.v:143867$6589
+ attribute \src "libresoc.v:143531.3-143532.27"
+ process $proc$libresoc.v:143531$6537
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:143869.3-143877.6"
- process $proc$libresoc.v:143869$6590
+ attribute \src "libresoc.v:143533.3-143541.6"
+ process $proc$libresoc.v:143533$6538
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$6591 $1\q_int$next[0:0]$6592
- attribute \src "libresoc.v:143870.5-143870.29"
+ assign $0\q_int$next[0:0]$6539 $1\q_int$next[0:0]$6540
+ attribute \src "libresoc.v:143534.5-143534.29"
switch \initial
- attribute \src "libresoc.v:143870.9-143870.17"
+ attribute \src "libresoc.v:143534.9-143534.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$6592 1'0
+ assign $1\q_int$next[0:0]$6540 1'0
case
- assign $1\q_int$next[0:0]$6592 \$5
+ assign $1\q_int$next[0:0]$6540 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$6591
+ update \q_int$next $0\q_int$next[0:0]$6539
end
- connect \$9 $and$libresoc.v:143859$6581_Y
- connect \$11 $or$libresoc.v:143860$6582_Y
- connect \$13 $not$libresoc.v:143861$6583_Y
- connect \$15 $or$libresoc.v:143862$6584_Y
- connect \$1 $not$libresoc.v:143863$6585_Y
- connect \$3 $and$libresoc.v:143864$6586_Y
- connect \$5 $or$libresoc.v:143865$6587_Y
- connect \$7 $not$libresoc.v:143866$6588_Y
+ connect \$9 $and$libresoc.v:143523$6529_Y
+ connect \$11 $or$libresoc.v:143524$6530_Y
+ connect \$13 $not$libresoc.v:143525$6531_Y
+ connect \$15 $or$libresoc.v:143526$6532_Y
+ connect \$1 $not$libresoc.v:143527$6533_Y
+ connect \$3 $and$libresoc.v:143528$6534_Y
+ connect \$5 $or$libresoc.v:143529$6535_Y
+ connect \$7 $not$libresoc.v:143530$6536_Y
connect \qlq_lod \$15
connect \qn_lod \$13
connect \q_lod \$11
end
-attribute \src "libresoc.v:143885.1-145005.10"
+attribute \src "libresoc.v:143549.1-144669.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0"
attribute \generator "nMigen"
module \logical0
- attribute \src "libresoc.v:144630.3-144631.24"
+ attribute \src "libresoc.v:144294.3-144295.24"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:144628.3-144629.44"
+ attribute \src "libresoc.v:144292.3-144293.44"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:144935.3-144943.6"
- wire $0\alu_l_r_alu$next[0:0]$6795
- attribute \src "libresoc.v:144552.3-144553.39"
+ attribute \src "libresoc.v:144599.3-144607.6"
+ wire $0\alu_l_r_alu$next[0:0]$6743
+ attribute \src "libresoc.v:144216.3-144217.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6724
- attribute \src "libresoc.v:144602.3-144603.83"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6672
+ attribute \src "libresoc.v:144266.3-144267.83"
wire width 4 $0\alu_logical0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725
- attribute \src "libresoc.v:144572.3-144573.81"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673
+ attribute \src "libresoc.v:144236.3-144237.81"
wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726
- attribute \src "libresoc.v:144574.3-144575.95"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674
+ attribute \src "libresoc.v:144238.3-144239.95"
wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727
- attribute \src "libresoc.v:144576.3-144577.91"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675
+ attribute \src "libresoc.v:144240.3-144241.91"
wire $0\alu_logical0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6728
- attribute \src "libresoc.v:144590.3-144591.89"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6676
+ attribute \src "libresoc.v:144254.3-144255.89"
wire width 2 $0\alu_logical0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6729
- attribute \src "libresoc.v:144604.3-144605.75"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6677
+ attribute \src "libresoc.v:144268.3-144269.75"
wire width 32 $0\alu_logical0_logical_op__insn[31:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6730
- attribute \src "libresoc.v:144570.3-144571.85"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6678
+ attribute \src "libresoc.v:144234.3-144235.85"
wire width 7 $0\alu_logical0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6731
- attribute \src "libresoc.v:144586.3-144587.85"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6679
+ attribute \src "libresoc.v:144250.3-144251.85"
wire $0\alu_logical0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6732
- attribute \src "libresoc.v:144592.3-144593.87"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6680
+ attribute \src "libresoc.v:144256.3-144257.87"
wire $0\alu_logical0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733
- attribute \src "libresoc.v:144598.3-144599.83"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681
+ attribute \src "libresoc.v:144262.3-144263.83"
wire $0\alu_logical0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6734
- attribute \src "libresoc.v:144600.3-144601.85"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6682
+ attribute \src "libresoc.v:144264.3-144265.85"
wire $0\alu_logical0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735
- attribute \src "libresoc.v:144582.3-144583.79"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683
+ attribute \src "libresoc.v:144246.3-144247.79"
wire $0\alu_logical0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736
- attribute \src "libresoc.v:144584.3-144585.79"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684
+ attribute \src "libresoc.v:144248.3-144249.79"
wire $0\alu_logical0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6737
- attribute \src "libresoc.v:144596.3-144597.91"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6685
+ attribute \src "libresoc.v:144260.3-144261.91"
wire $0\alu_logical0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738
- attribute \src "libresoc.v:144580.3-144581.79"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686
+ attribute \src "libresoc.v:144244.3-144245.79"
wire $0\alu_logical0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739
- attribute \src "libresoc.v:144578.3-144579.79"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687
+ attribute \src "libresoc.v:144242.3-144243.79"
wire $0\alu_logical0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740
- attribute \src "libresoc.v:144594.3-144595.85"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688
+ attribute \src "libresoc.v:144258.3-144259.85"
wire $0\alu_logical0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6741
- attribute \src "libresoc.v:144588.3-144589.79"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6689
+ attribute \src "libresoc.v:144252.3-144253.79"
wire $0\alu_logical0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:144926.3-144934.6"
- wire $0\alui_l_r_alui$next[0:0]$6792
- attribute \src "libresoc.v:144554.3-144555.43"
+ attribute \src "libresoc.v:144590.3-144598.6"
+ wire $0\alui_l_r_alui$next[0:0]$6740
+ attribute \src "libresoc.v:144218.3-144219.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:144852.3-144873.6"
- wire width 64 $0\data_r0__o$next[63:0]$6767
- attribute \src "libresoc.v:144566.3-144567.37"
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire width 64 $0\data_r0__o$next[63:0]$6715
+ attribute \src "libresoc.v:144230.3-144231.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:144852.3-144873.6"
- wire $0\data_r0__o_ok$next[0:0]$6768
- attribute \src "libresoc.v:144568.3-144569.43"
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire $0\data_r0__o_ok$next[0:0]$6716
+ attribute \src "libresoc.v:144232.3-144233.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:144874.3-144895.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$6775
- attribute \src "libresoc.v:144562.3-144563.43"
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$6723
+ attribute \src "libresoc.v:144226.3-144227.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:144874.3-144895.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$6776
- attribute \src "libresoc.v:144564.3-144565.49"
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$6724
+ attribute \src "libresoc.v:144228.3-144229.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:144944.3-144953.6"
+ attribute \src "libresoc.v:144608.3-144617.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:144954.3-144963.6"
+ attribute \src "libresoc.v:144618.3-144627.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:143886.7-143886.20"
+ attribute \src "libresoc.v:143550.7-143550.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:144768.3-144776.6"
- wire $0\opc_l_r_opc$next[0:0]$6709
- attribute \src "libresoc.v:144614.3-144615.39"
+ attribute \src "libresoc.v:144432.3-144440.6"
+ wire $0\opc_l_r_opc$next[0:0]$6657
+ attribute \src "libresoc.v:144278.3-144279.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:144759.3-144767.6"
- wire $0\opc_l_s_opc$next[0:0]$6706
- attribute \src "libresoc.v:144616.3-144617.39"
+ attribute \src "libresoc.v:144423.3-144431.6"
+ wire $0\opc_l_s_opc$next[0:0]$6654
+ attribute \src "libresoc.v:144280.3-144281.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:144964.3-144972.6"
- wire width 2 $0\prev_wr_go$next[1:0]$6800
- attribute \src "libresoc.v:144626.3-144627.37"
+ attribute \src "libresoc.v:144628.3-144636.6"
+ wire width 2 $0\prev_wr_go$next[1:0]$6748
+ attribute \src "libresoc.v:144290.3-144291.37"
wire width 2 $0\prev_wr_go[1:0]
- attribute \src "libresoc.v:144713.3-144722.6"
+ attribute \src "libresoc.v:144377.3-144386.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:144804.3-144812.6"
- wire width 2 $0\req_l_r_req$next[1:0]$6721
- attribute \src "libresoc.v:144606.3-144607.39"
+ attribute \src "libresoc.v:144468.3-144476.6"
+ wire width 2 $0\req_l_r_req$next[1:0]$6669
+ attribute \src "libresoc.v:144270.3-144271.39"
wire width 2 $0\req_l_r_req[1:0]
- attribute \src "libresoc.v:144795.3-144803.6"
- wire width 2 $0\req_l_s_req$next[1:0]$6718
- attribute \src "libresoc.v:144608.3-144609.39"
+ attribute \src "libresoc.v:144459.3-144467.6"
+ wire width 2 $0\req_l_s_req$next[1:0]$6666
+ attribute \src "libresoc.v:144272.3-144273.39"
wire width 2 $0\req_l_s_req[1:0]
- attribute \src "libresoc.v:144732.3-144740.6"
- wire $0\rok_l_r_rdok$next[0:0]$6697
- attribute \src "libresoc.v:144622.3-144623.41"
+ attribute \src "libresoc.v:144396.3-144404.6"
+ wire $0\rok_l_r_rdok$next[0:0]$6645
+ attribute \src "libresoc.v:144286.3-144287.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:144723.3-144731.6"
- wire $0\rok_l_s_rdok$next[0:0]$6694
- attribute \src "libresoc.v:144624.3-144625.41"
+ attribute \src "libresoc.v:144387.3-144395.6"
+ wire $0\rok_l_s_rdok$next[0:0]$6642
+ attribute \src "libresoc.v:144288.3-144289.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:144750.3-144758.6"
- wire $0\rst_l_r_rst$next[0:0]$6703
- attribute \src "libresoc.v:144618.3-144619.39"
+ attribute \src "libresoc.v:144414.3-144422.6"
+ wire $0\rst_l_r_rst$next[0:0]$6651
+ attribute \src "libresoc.v:144282.3-144283.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:144741.3-144749.6"
- wire $0\rst_l_s_rst$next[0:0]$6700
- attribute \src "libresoc.v:144620.3-144621.39"
+ attribute \src "libresoc.v:144405.3-144413.6"
+ wire $0\rst_l_s_rst$next[0:0]$6648
+ attribute \src "libresoc.v:144284.3-144285.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:144786.3-144794.6"
- wire width 3 $0\src_l_r_src$next[2:0]$6715
- attribute \src "libresoc.v:144610.3-144611.39"
+ attribute \src "libresoc.v:144450.3-144458.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$6663
+ attribute \src "libresoc.v:144274.3-144275.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:144777.3-144785.6"
- wire width 3 $0\src_l_s_src$next[2:0]$6712
- attribute \src "libresoc.v:144612.3-144613.39"
+ attribute \src "libresoc.v:144441.3-144449.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$6660
+ attribute \src "libresoc.v:144276.3-144277.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:144896.3-144905.6"
- wire width 64 $0\src_r0$next[63:0]$6783
- attribute \src "libresoc.v:144560.3-144561.29"
+ attribute \src "libresoc.v:144560.3-144569.6"
+ wire width 64 $0\src_r0$next[63:0]$6731
+ attribute \src "libresoc.v:144224.3-144225.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:144906.3-144915.6"
- wire width 64 $0\src_r1$next[63:0]$6786
- attribute \src "libresoc.v:144558.3-144559.29"
+ attribute \src "libresoc.v:144570.3-144579.6"
+ wire width 64 $0\src_r1$next[63:0]$6734
+ attribute \src "libresoc.v:144222.3-144223.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:144916.3-144925.6"
- wire $0\src_r2$next[0:0]$6789
- attribute \src "libresoc.v:144556.3-144557.29"
+ attribute \src "libresoc.v:144580.3-144589.6"
+ wire $0\src_r2$next[0:0]$6737
+ attribute \src "libresoc.v:144220.3-144221.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:144004.7-144004.24"
+ attribute \src "libresoc.v:143668.7-143668.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:144014.7-144014.26"
+ attribute \src "libresoc.v:143678.7-143678.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:144935.3-144943.6"
- wire $1\alu_l_r_alu$next[0:0]$6796
- attribute \src "libresoc.v:144022.7-144022.25"
+ attribute \src "libresoc.v:144599.3-144607.6"
+ wire $1\alu_l_r_alu$next[0:0]$6744
+ attribute \src "libresoc.v:143686.7-143686.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6742
- attribute \src "libresoc.v:144030.13-144030.53"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6690
+ attribute \src "libresoc.v:143694.13-143694.53"
wire width 4 $1\alu_logical0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743
- attribute \src "libresoc.v:144049.14-144049.57"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691
+ attribute \src "libresoc.v:143713.14-143713.57"
wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744
- attribute \src "libresoc.v:144053.14-144053.76"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692
+ attribute \src "libresoc.v:143717.14-143717.76"
wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745
- attribute \src "libresoc.v:144057.7-144057.51"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693
+ attribute \src "libresoc.v:143721.7-143721.51"
wire $1\alu_logical0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746
- attribute \src "libresoc.v:144065.13-144065.56"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694
+ attribute \src "libresoc.v:143729.13-143729.56"
wire width 2 $1\alu_logical0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6747
- attribute \src "libresoc.v:144069.14-144069.51"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6695
+ attribute \src "libresoc.v:143733.14-143733.51"
wire width 32 $1\alu_logical0_logical_op__insn[31:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748
- attribute \src "libresoc.v:144148.13-144148.55"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696
+ attribute \src "libresoc.v:143812.13-143812.55"
wire width 7 $1\alu_logical0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6749
- attribute \src "libresoc.v:144152.7-144152.48"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6697
+ attribute \src "libresoc.v:143816.7-143816.48"
wire $1\alu_logical0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6750
- attribute \src "libresoc.v:144156.7-144156.49"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6698
+ attribute \src "libresoc.v:143820.7-143820.49"
wire $1\alu_logical0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751
- attribute \src "libresoc.v:144160.7-144160.47"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699
+ attribute \src "libresoc.v:143824.7-143824.47"
wire $1\alu_logical0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6752
- attribute \src "libresoc.v:144164.7-144164.48"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6700
+ attribute \src "libresoc.v:143828.7-143828.48"
wire $1\alu_logical0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753
- attribute \src "libresoc.v:144168.7-144168.45"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701
+ attribute \src "libresoc.v:143832.7-143832.45"
wire $1\alu_logical0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754
- attribute \src "libresoc.v:144172.7-144172.45"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702
+ attribute \src "libresoc.v:143836.7-143836.45"
wire $1\alu_logical0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6755
- attribute \src "libresoc.v:144176.7-144176.51"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6703
+ attribute \src "libresoc.v:143840.7-143840.51"
wire $1\alu_logical0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756
- attribute \src "libresoc.v:144180.7-144180.45"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704
+ attribute \src "libresoc.v:143844.7-143844.45"
wire $1\alu_logical0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757
- attribute \src "libresoc.v:144184.7-144184.45"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705
+ attribute \src "libresoc.v:143848.7-143848.45"
wire $1\alu_logical0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758
- attribute \src "libresoc.v:144188.7-144188.48"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706
+ attribute \src "libresoc.v:143852.7-143852.48"
wire $1\alu_logical0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6759
- attribute \src "libresoc.v:144192.7-144192.45"
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6707
+ attribute \src "libresoc.v:143856.7-143856.45"
wire $1\alu_logical0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:144926.3-144934.6"
- wire $1\alui_l_r_alui$next[0:0]$6793
- attribute \src "libresoc.v:144218.7-144218.27"
+ attribute \src "libresoc.v:144590.3-144598.6"
+ wire $1\alui_l_r_alui$next[0:0]$6741
+ attribute \src "libresoc.v:143882.7-143882.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:144852.3-144873.6"
- wire width 64 $1\data_r0__o$next[63:0]$6769
- attribute \src "libresoc.v:144252.14-144252.47"
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire width 64 $1\data_r0__o$next[63:0]$6717
+ attribute \src "libresoc.v:143916.14-143916.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:144852.3-144873.6"
- wire $1\data_r0__o_ok$next[0:0]$6770
- attribute \src "libresoc.v:144256.7-144256.27"
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire $1\data_r0__o_ok$next[0:0]$6718
+ attribute \src "libresoc.v:143920.7-143920.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:144874.3-144895.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$6777
- attribute \src "libresoc.v:144260.13-144260.33"
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$6725
+ attribute \src "libresoc.v:143924.13-143924.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:144874.3-144895.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$6778
- attribute \src "libresoc.v:144264.7-144264.30"
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$6726
+ attribute \src "libresoc.v:143928.7-143928.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:144944.3-144953.6"
+ attribute \src "libresoc.v:144608.3-144617.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:144954.3-144963.6"
+ attribute \src "libresoc.v:144618.3-144627.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:144768.3-144776.6"
- wire $1\opc_l_r_opc$next[0:0]$6710
- attribute \src "libresoc.v:144278.7-144278.25"
+ attribute \src "libresoc.v:144432.3-144440.6"
+ wire $1\opc_l_r_opc$next[0:0]$6658
+ attribute \src "libresoc.v:143942.7-143942.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:144759.3-144767.6"
- wire $1\opc_l_s_opc$next[0:0]$6707
- attribute \src "libresoc.v:144282.7-144282.25"
+ attribute \src "libresoc.v:144423.3-144431.6"
+ wire $1\opc_l_s_opc$next[0:0]$6655
+ attribute \src "libresoc.v:143946.7-143946.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:144964.3-144972.6"
- wire width 2 $1\prev_wr_go$next[1:0]$6801
- attribute \src "libresoc.v:144416.13-144416.30"
+ attribute \src "libresoc.v:144628.3-144636.6"
+ wire width 2 $1\prev_wr_go$next[1:0]$6749
+ attribute \src "libresoc.v:144080.13-144080.30"
wire width 2 $1\prev_wr_go[1:0]
- attribute \src "libresoc.v:144713.3-144722.6"
+ attribute \src "libresoc.v:144377.3-144386.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:144804.3-144812.6"
- wire width 2 $1\req_l_r_req$next[1:0]$6722
- attribute \src "libresoc.v:144424.13-144424.31"
+ attribute \src "libresoc.v:144468.3-144476.6"
+ wire width 2 $1\req_l_r_req$next[1:0]$6670
+ attribute \src "libresoc.v:144088.13-144088.31"
wire width 2 $1\req_l_r_req[1:0]
- attribute \src "libresoc.v:144795.3-144803.6"
- wire width 2 $1\req_l_s_req$next[1:0]$6719
- attribute \src "libresoc.v:144428.13-144428.31"
+ attribute \src "libresoc.v:144459.3-144467.6"
+ wire width 2 $1\req_l_s_req$next[1:0]$6667
+ attribute \src "libresoc.v:144092.13-144092.31"
wire width 2 $1\req_l_s_req[1:0]
- attribute \src "libresoc.v:144732.3-144740.6"
- wire $1\rok_l_r_rdok$next[0:0]$6698
- attribute \src "libresoc.v:144440.7-144440.26"
+ attribute \src "libresoc.v:144396.3-144404.6"
+ wire $1\rok_l_r_rdok$next[0:0]$6646
+ attribute \src "libresoc.v:144104.7-144104.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:144723.3-144731.6"
- wire $1\rok_l_s_rdok$next[0:0]$6695
- attribute \src "libresoc.v:144444.7-144444.26"
+ attribute \src "libresoc.v:144387.3-144395.6"
+ wire $1\rok_l_s_rdok$next[0:0]$6643
+ attribute \src "libresoc.v:144108.7-144108.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:144750.3-144758.6"
- wire $1\rst_l_r_rst$next[0:0]$6704
- attribute \src "libresoc.v:144448.7-144448.25"
+ attribute \src "libresoc.v:144414.3-144422.6"
+ wire $1\rst_l_r_rst$next[0:0]$6652
+ attribute \src "libresoc.v:144112.7-144112.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:144741.3-144749.6"
- wire $1\rst_l_s_rst$next[0:0]$6701
- attribute \src "libresoc.v:144452.7-144452.25"
+ attribute \src "libresoc.v:144405.3-144413.6"
+ wire $1\rst_l_s_rst$next[0:0]$6649
+ attribute \src "libresoc.v:144116.7-144116.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:144786.3-144794.6"
- wire width 3 $1\src_l_r_src$next[2:0]$6716
- attribute \src "libresoc.v:144466.13-144466.31"
+ attribute \src "libresoc.v:144450.3-144458.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$6664
+ attribute \src "libresoc.v:144130.13-144130.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:144777.3-144785.6"
- wire width 3 $1\src_l_s_src$next[2:0]$6713
- attribute \src "libresoc.v:144470.13-144470.31"
+ attribute \src "libresoc.v:144441.3-144449.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$6661
+ attribute \src "libresoc.v:144134.13-144134.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:144896.3-144905.6"
- wire width 64 $1\src_r0$next[63:0]$6784
- attribute \src "libresoc.v:144478.14-144478.43"
+ attribute \src "libresoc.v:144560.3-144569.6"
+ wire width 64 $1\src_r0$next[63:0]$6732
+ attribute \src "libresoc.v:144142.14-144142.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:144906.3-144915.6"
- wire width 64 $1\src_r1$next[63:0]$6787
- attribute \src "libresoc.v:144482.14-144482.43"
+ attribute \src "libresoc.v:144570.3-144579.6"
+ wire width 64 $1\src_r1$next[63:0]$6735
+ attribute \src "libresoc.v:144146.14-144146.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:144916.3-144925.6"
- wire $1\src_r2$next[0:0]$6790
- attribute \src "libresoc.v:144486.7-144486.20"
+ attribute \src "libresoc.v:144580.3-144589.6"
+ wire $1\src_r2$next[0:0]$6738
+ attribute \src "libresoc.v:144150.7-144150.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:144813.3-144851.6"
- wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760
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- wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764
- attribute \src "libresoc.v:144813.3-144851.6"
- wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765
- attribute \src "libresoc.v:144852.3-144873.6"
- wire width 64 $2\data_r0__o$next[63:0]$6771
- attribute \src "libresoc.v:144852.3-144873.6"
- wire $2\data_r0__o_ok$next[0:0]$6772
- attribute \src "libresoc.v:144874.3-144895.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$6779
- attribute \src "libresoc.v:144874.3-144895.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$6780
- attribute \src "libresoc.v:144852.3-144873.6"
- wire $3\data_r0__o_ok$next[0:0]$6773
- attribute \src "libresoc.v:144874.3-144895.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$6781
- attribute \src "libresoc.v:144495.17-144495.109"
- wire $and$libresoc.v:144495$6595_Y
- attribute \src "libresoc.v:144496.18-144496.130"
- wire width 3 $and$libresoc.v:144496$6596_Y
- attribute \src "libresoc.v:144498.19-144498.114"
- wire width 3 $and$libresoc.v:144498$6598_Y
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- wire $and$libresoc.v:144499$6599_Y
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- wire $and$libresoc.v:144500$6600_Y
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- wire width 2 $and$libresoc.v:144501$6601_Y
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- wire width 2 $and$libresoc.v:144502$6602_Y
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- wire $and$libresoc.v:144503$6603_Y
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- wire $and$libresoc.v:144504$6604_Y
- attribute \src "libresoc.v:144506.18-144506.98"
- wire $and$libresoc.v:144506$6606_Y
- attribute \src "libresoc.v:144508.18-144508.100"
- wire $and$libresoc.v:144508$6608_Y
- attribute \src "libresoc.v:144509.17-144509.123"
- wire $and$libresoc.v:144509$6609_Y
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- wire width 2 $and$libresoc.v:144510$6610_Y
- attribute \src "libresoc.v:144512.18-144512.119"
- wire width 2 $and$libresoc.v:144512$6612_Y
- attribute \src "libresoc.v:144515.18-144515.116"
- wire $and$libresoc.v:144515$6615_Y
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- wire $and$libresoc.v:144520$6620_Y
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- wire width 2 $and$libresoc.v:144521$6621_Y
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- wire $and$libresoc.v:144523$6623_Y
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- wire $and$libresoc.v:144526$6626_Y
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- wire $and$libresoc.v:144527$6627_Y
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- wire $and$libresoc.v:144528$6628_Y
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- wire $and$libresoc.v:144537$6637_Y
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- wire $and$libresoc.v:144538$6638_Y
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- wire $and$libresoc.v:144547$6647_Y
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- wire $eq$libresoc.v:144522$6622_Y
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- wire $not$libresoc.v:144505$6605_Y
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- wire $not$libresoc.v:144514$6614_Y
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- wire $not$libresoc.v:144519$6619_Y
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- wire width 3 $not$libresoc.v:144525$6625_Y
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- wire $not$libresoc.v:144550$6650_Y
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- wire $not$libresoc.v:144551$6651_Y
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- wire $or$libresoc.v:144518$6618_Y
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- wire $or$libresoc.v:144529$6629_Y
- attribute \src "libresoc.v:144530.18-144530.124"
- wire $or$libresoc.v:144530$6630_Y
- attribute \src "libresoc.v:144531.18-144531.142"
- wire width 2 $or$libresoc.v:144531$6631_Y
- attribute \src "libresoc.v:144532.18-144532.155"
- wire width 3 $or$libresoc.v:144532$6632_Y
- attribute \src "libresoc.v:144535.18-144535.120"
- wire width 2 $or$libresoc.v:144535$6635_Y
- attribute \src "libresoc.v:144536.17-144536.117"
- wire width 3 $or$libresoc.v:144536$6636_Y
- attribute \src "libresoc.v:144542.17-144542.104"
- wire $reduce_and$libresoc.v:144542$6642_Y
- attribute \src "libresoc.v:144513.18-144513.106"
- wire $reduce_or$libresoc.v:144513$6613_Y
- attribute \src "libresoc.v:144516.18-144516.113"
- wire $reduce_or$libresoc.v:144516$6616_Y
- attribute \src "libresoc.v:144517.18-144517.112"
- wire $reduce_or$libresoc.v:144517$6617_Y
- attribute \src "libresoc.v:144539.18-144539.162"
- wire $ternary$libresoc.v:144539$6639_Y
- attribute \src "libresoc.v:144540.18-144540.163"
- wire width 64 $ternary$libresoc.v:144540$6640_Y
- attribute \src "libresoc.v:144541.18-144541.168"
- wire $ternary$libresoc.v:144541$6641_Y
- attribute \src "libresoc.v:144543.18-144543.188"
- wire width 64 $ternary$libresoc.v:144543$6643_Y
- attribute \src "libresoc.v:144544.18-144544.115"
- wire width 64 $ternary$libresoc.v:144544$6644_Y
- attribute \src "libresoc.v:144545.18-144545.125"
- wire width 64 $ternary$libresoc.v:144545$6645_Y
- attribute \src "libresoc.v:144546.18-144546.118"
- wire $ternary$libresoc.v:144546$6646_Y
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712
+ attribute \src "libresoc.v:144477.3-144515.6"
+ wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire width 64 $2\data_r0__o$next[63:0]$6719
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire $2\data_r0__o_ok$next[0:0]$6720
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$6727
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$6728
+ attribute \src "libresoc.v:144516.3-144537.6"
+ wire $3\data_r0__o_ok$next[0:0]$6721
+ attribute \src "libresoc.v:144538.3-144559.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$6729
+ attribute \src "libresoc.v:144159.17-144159.109"
+ wire $and$libresoc.v:144159$6543_Y
+ attribute \src "libresoc.v:144160.18-144160.130"
+ wire width 3 $and$libresoc.v:144160$6544_Y
+ attribute \src "libresoc.v:144162.19-144162.114"
+ wire width 3 $and$libresoc.v:144162$6546_Y
+ attribute \src "libresoc.v:144163.19-144163.125"
+ wire $and$libresoc.v:144163$6547_Y
+ attribute \src "libresoc.v:144164.19-144164.125"
+ wire $and$libresoc.v:144164$6548_Y
+ attribute \src "libresoc.v:144165.19-144165.133"
+ wire width 2 $and$libresoc.v:144165$6549_Y
+ attribute \src "libresoc.v:144166.19-144166.121"
+ wire width 2 $and$libresoc.v:144166$6550_Y
+ attribute \src "libresoc.v:144167.19-144167.127"
+ wire $and$libresoc.v:144167$6551_Y
+ attribute \src "libresoc.v:144168.19-144168.127"
+ wire $and$libresoc.v:144168$6552_Y
+ attribute \src "libresoc.v:144170.18-144170.98"
+ wire $and$libresoc.v:144170$6554_Y
+ attribute \src "libresoc.v:144172.18-144172.100"
+ wire $and$libresoc.v:144172$6556_Y
+ attribute \src "libresoc.v:144173.17-144173.123"
+ wire $and$libresoc.v:144173$6557_Y
+ attribute \src "libresoc.v:144174.18-144174.138"
+ wire width 2 $and$libresoc.v:144174$6558_Y
+ attribute \src "libresoc.v:144176.18-144176.119"
+ wire width 2 $and$libresoc.v:144176$6560_Y
+ attribute \src "libresoc.v:144179.18-144179.116"
+ wire $and$libresoc.v:144179$6563_Y
+ attribute \src "libresoc.v:144184.18-144184.113"
+ wire $and$libresoc.v:144184$6568_Y
+ attribute \src "libresoc.v:144185.18-144185.125"
+ wire width 2 $and$libresoc.v:144185$6569_Y
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+ wire $and$libresoc.v:144187$6571_Y
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+ wire $and$libresoc.v:144190$6574_Y
+ attribute \src "libresoc.v:144191.18-144191.130"
+ wire $and$libresoc.v:144191$6575_Y
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+ wire $and$libresoc.v:144192$6576_Y
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+ wire $and$libresoc.v:144201$6585_Y
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+ wire $and$libresoc.v:144202$6586_Y
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+ wire $and$libresoc.v:144211$6595_Y
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+ wire $and$libresoc.v:144212$6596_Y
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+ wire $eq$libresoc.v:144186$6570_Y
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+ wire $eq$libresoc.v:144188$6572_Y
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+ wire width 3 $not$libresoc.v:144189$6573_Y
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+ wire $not$libresoc.v:144214$6598_Y
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+ wire $not$libresoc.v:144215$6599_Y
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+ wire $or$libresoc.v:144193$6577_Y
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+ wire $or$libresoc.v:144194$6578_Y
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+ wire width 2 $or$libresoc.v:144195$6579_Y
+ attribute \src "libresoc.v:144196.18-144196.155"
+ wire width 3 $or$libresoc.v:144196$6580_Y
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+ wire width 2 $or$libresoc.v:144199$6583_Y
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+ wire width 3 $or$libresoc.v:144200$6584_Y
+ attribute \src "libresoc.v:144206.17-144206.104"
+ wire $reduce_and$libresoc.v:144206$6590_Y
+ attribute \src "libresoc.v:144177.18-144177.106"
+ wire $reduce_or$libresoc.v:144177$6561_Y
+ attribute \src "libresoc.v:144180.18-144180.113"
+ wire $reduce_or$libresoc.v:144180$6564_Y
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+ wire $reduce_or$libresoc.v:144181$6565_Y
+ attribute \src "libresoc.v:144203.18-144203.162"
+ wire $ternary$libresoc.v:144203$6587_Y
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+ wire width 64 $ternary$libresoc.v:144204$6588_Y
+ attribute \src "libresoc.v:144205.18-144205.168"
+ wire $ternary$libresoc.v:144205$6589_Y
+ attribute \src "libresoc.v:144207.18-144207.188"
+ wire width 64 $ternary$libresoc.v:144207$6591_Y
+ attribute \src "libresoc.v:144208.18-144208.115"
+ wire width 64 $ternary$libresoc.v:144208$6592_Y
+ attribute \src "libresoc.v:144209.18-144209.125"
+ wire width 64 $ternary$libresoc.v:144209$6593_Y
+ attribute \src "libresoc.v:144210.18-144210.118"
+ wire $ternary$libresoc.v:144210$6594_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 32 \cr_a_ok
wire width 64 output 31 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 4 output 33 \dest2_o
- attribute \src "libresoc.v:143886.7-143886.15"
+ attribute \src "libresoc.v:143550.7-143550.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 25 \src1_i
+ wire width 64 input 26 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 26 \src2_i
+ wire width 64 input 25 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 27 \src3_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:144495$6595
+ cell $and $and$libresoc.v:144159$6543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:144495$6595_Y
+ connect \Y $and$libresoc.v:144159$6543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:144496$6596
+ cell $and $and$libresoc.v:144160$6544
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$93
connect \B { 1'1 \$97 \$95 }
- connect \Y $and$libresoc.v:144496$6596_Y
+ connect \Y $and$libresoc.v:144160$6544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:144498$6598
+ cell $and $and$libresoc.v:144162$6546
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$99
connect \B \$101
- connect \Y $and$libresoc.v:144498$6598_Y
+ connect \Y $and$libresoc.v:144162$6546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:144499$6599
+ cell $and $and$libresoc.v:144163$6547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:144499$6599_Y
+ connect \Y $and$libresoc.v:144163$6547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:144500$6600
+ cell $and $and$libresoc.v:144164$6548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:144500$6600_Y
+ connect \Y $and$libresoc.v:144164$6548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:144501$6601
+ cell $and $and$libresoc.v:144165$6549
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \req_l_q_req
connect \B { \$105 \$107 }
- connect \Y $and$libresoc.v:144501$6601_Y
+ connect \Y $and$libresoc.v:144165$6549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:144502$6602
+ cell $and $and$libresoc.v:144166$6550
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$109
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:144502$6602_Y
+ connect \Y $and$libresoc.v:144166$6550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:144503$6603
+ cell $and $and$libresoc.v:144167$6551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144503$6603_Y
+ connect \Y $and$libresoc.v:144167$6551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:144504$6604
+ cell $and $and$libresoc.v:144168$6552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144504$6604_Y
+ connect \Y $and$libresoc.v:144168$6552_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:144506$6606
+ cell $and $and$libresoc.v:144170$6554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$11
- connect \Y $and$libresoc.v:144506$6606_Y
+ connect \Y $and$libresoc.v:144170$6554_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:144508$6608
+ cell $and $and$libresoc.v:144172$6556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$15
- connect \Y $and$libresoc.v:144508$6608_Y
+ connect \Y $and$libresoc.v:144172$6556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:144509$6609
+ cell $and $and$libresoc.v:144173$6557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:144509$6609_Y
+ connect \Y $and$libresoc.v:144173$6557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:144510$6610
+ cell $and $and$libresoc.v:144174$6558
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:144510$6610_Y
+ connect \Y $and$libresoc.v:144174$6558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:144512$6612
+ cell $and $and$libresoc.v:144176$6560
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__rel_o
connect \B \$23
- connect \Y $and$libresoc.v:144512$6612_Y
+ connect \Y $and$libresoc.v:144176$6560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:144515$6615
+ cell $and $and$libresoc.v:144179$6563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$21
- connect \Y $and$libresoc.v:144515$6615_Y
+ connect \Y $and$libresoc.v:144179$6563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:144520$6620
+ cell $and $and$libresoc.v:144184$6568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$37
- connect \Y $and$libresoc.v:144520$6620_Y
+ connect \Y $and$libresoc.v:144184$6568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:144521$6621
+ cell $and $and$libresoc.v:144185$6569
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:144521$6621_Y
+ connect \Y $and$libresoc.v:144185$6569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:144523$6623
+ cell $and $and$libresoc.v:144187$6571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \$43
- connect \Y $and$libresoc.v:144523$6623_Y
+ connect \Y $and$libresoc.v:144187$6571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:144526$6626
+ cell $and $and$libresoc.v:144190$6574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$47
connect \B \alu_logical0_n_ready_i
- connect \Y $and$libresoc.v:144526$6626_Y
+ connect \Y $and$libresoc.v:144190$6574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:144527$6627
+ cell $and $and$libresoc.v:144191$6575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_logical0_n_valid_o
- connect \Y $and$libresoc.v:144527$6627_Y
+ connect \Y $and$libresoc.v:144191$6575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:144528$6628
+ cell $and $and$libresoc.v:144192$6576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144528$6628_Y
+ connect \Y $and$libresoc.v:144192$6576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:144533$6633
+ cell $and $and$libresoc.v:144197$6581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144533$6633_Y
+ connect \Y $and$libresoc.v:144197$6581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:144534$6634
+ cell $and $and$libresoc.v:144198$6582
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:144534$6634_Y
+ connect \Y $and$libresoc.v:144198$6582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:144537$6637
+ cell $and $and$libresoc.v:144201$6585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144537$6637_Y
+ connect \Y $and$libresoc.v:144201$6585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:144538$6638
+ cell $and $and$libresoc.v:144202$6586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:144538$6638_Y
+ connect \Y $and$libresoc.v:144202$6586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:144547$6647
+ cell $and $and$libresoc.v:144211$6595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:144547$6647_Y
+ connect \Y $and$libresoc.v:144211$6595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:144548$6648
+ cell $and $and$libresoc.v:144212$6596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:144548$6648_Y
+ connect \Y $and$libresoc.v:144212$6596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:144549$6649
+ cell $and $and$libresoc.v:144213$6597
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:144549$6649_Y
+ connect \Y $and$libresoc.v:144213$6597_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:144522$6622
+ cell $eq $eq$libresoc.v:144186$6570
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B 1'0
- connect \Y $eq$libresoc.v:144522$6622_Y
+ connect \Y $eq$libresoc.v:144186$6570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:144524$6624
+ cell $eq $eq$libresoc.v:144188$6572
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:144524$6624_Y
+ connect \Y $eq$libresoc.v:144188$6572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:144497$6597
+ cell $not $not$libresoc.v:144161$6545
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:144497$6597_Y
+ connect \Y $not$libresoc.v:144161$6545_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:144505$6605
+ cell $not $not$libresoc.v:144169$6553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:144505$6605_Y
+ connect \Y $not$libresoc.v:144169$6553_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:144507$6607
+ cell $not $not$libresoc.v:144171$6555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:144507$6607_Y
+ connect \Y $not$libresoc.v:144171$6555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:144511$6611
+ cell $not $not$libresoc.v:144175$6559
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:144511$6611_Y
+ connect \Y $not$libresoc.v:144175$6559_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:144514$6614
+ cell $not $not$libresoc.v:144178$6562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$22
- connect \Y $not$libresoc.v:144514$6614_Y
+ connect \Y $not$libresoc.v:144178$6562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:144519$6619
+ cell $not $not$libresoc.v:144183$6567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_ready_i
- connect \Y $not$libresoc.v:144519$6619_Y
+ connect \Y $not$libresoc.v:144183$6567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:144525$6625
+ cell $not $not$libresoc.v:144189$6573
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:144525$6625_Y
+ connect \Y $not$libresoc.v:144189$6573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:144550$6650
+ cell $not $not$libresoc.v:144214$6598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_logical_op__zero_a
- connect \Y $not$libresoc.v:144550$6650_Y
+ connect \Y $not$libresoc.v:144214$6598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:144551$6651
+ cell $not $not$libresoc.v:144215$6599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_logical_op__imm_data__ok
- connect \Y $not$libresoc.v:144551$6651_Y
+ connect \Y $not$libresoc.v:144215$6599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:144518$6618
+ cell $or $or$libresoc.v:144182$6566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $or$libresoc.v:144518$6618_Y
+ connect \Y $or$libresoc.v:144182$6566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:144529$6629
+ cell $or $or$libresoc.v:144193$6577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:144529$6629_Y
+ connect \Y $or$libresoc.v:144193$6577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:144530$6630
+ cell $or $or$libresoc.v:144194$6578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:144530$6630_Y
+ connect \Y $or$libresoc.v:144194$6578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:144531$6631
+ cell $or $or$libresoc.v:144195$6579
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:144531$6631_Y
+ connect \Y $or$libresoc.v:144195$6579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:144532$6632
+ cell $or $or$libresoc.v:144196$6580
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:144532$6632_Y
+ connect \Y $or$libresoc.v:144196$6580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:144535$6635
+ cell $or $or$libresoc.v:144199$6583
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:144535$6635_Y
+ connect \Y $or$libresoc.v:144199$6583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:144536$6636
+ cell $or $or$libresoc.v:144200$6584
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$4
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:144536$6636_Y
+ connect \Y $or$libresoc.v:144200$6584_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:144542$6642
+ cell $reduce_and $reduce_and$libresoc.v:144206$6590
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$6
- connect \Y $reduce_and$libresoc.v:144542$6642_Y
+ connect \Y $reduce_and$libresoc.v:144206$6590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:144513$6613
+ cell $reduce_or $reduce_or$libresoc.v:144177$6561
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \$25
- connect \Y $reduce_or$libresoc.v:144513$6613_Y
+ connect \Y $reduce_or$libresoc.v:144177$6561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:144516$6616
+ cell $reduce_or $reduce_or$libresoc.v:144180$6564
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:144516$6616_Y
+ connect \Y $reduce_or$libresoc.v:144180$6564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:144517$6617
+ cell $reduce_or $reduce_or$libresoc.v:144181$6565
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:144517$6617_Y
+ connect \Y $reduce_or$libresoc.v:144181$6565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:144539$6639
+ cell $mux $ternary$libresoc.v:144203$6587
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \alu_logical0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:144539$6639_Y
+ connect \Y $ternary$libresoc.v:144203$6587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:144540$6640
+ cell $mux $ternary$libresoc.v:144204$6588
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \alu_logical0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:144540$6640_Y
+ connect \Y $ternary$libresoc.v:144204$6588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:144541$6641
+ cell $mux $ternary$libresoc.v:144205$6589
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_logical0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:144541$6641_Y
+ connect \Y $ternary$libresoc.v:144205$6589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:144543$6643
+ cell $mux $ternary$libresoc.v:144207$6591
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_logical0_logical_op__imm_data__data
connect \S \alu_logical0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:144543$6643_Y
+ connect \Y $ternary$libresoc.v:144207$6591_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:144544$6644
+ cell $mux $ternary$libresoc.v:144208$6592
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:144544$6644_Y
+ connect \Y $ternary$libresoc.v:144208$6592_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:144545$6645
+ cell $mux $ternary$libresoc.v:144209$6593
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm$80
connect \S \src_sel$77
- connect \Y $ternary$libresoc.v:144545$6645_Y
+ connect \Y $ternary$libresoc.v:144209$6593_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:144546$6646
+ cell $mux $ternary$libresoc.v:144210$6594
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:144546$6646_Y
+ connect \Y $ternary$libresoc.v:144210$6594_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144632.14-144638.4"
+ attribute \src "libresoc.v:144296.14-144302.4"
cell \alu_l$61 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144639.16-144671.4"
+ attribute \src "libresoc.v:144303.16-144335.4"
cell \alu_logical0 \alu_logical0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so \alu_logical0_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144672.15-144678.4"
+ attribute \src "libresoc.v:144336.15-144342.4"
cell \alui_l$60 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144679.14-144685.4"
+ attribute \src "libresoc.v:144343.14-144349.4"
cell \opc_l$56 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144686.14-144692.4"
+ attribute \src "libresoc.v:144350.14-144356.4"
cell \req_l$57 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144693.14-144699.4"
+ attribute \src "libresoc.v:144357.14-144363.4"
cell \rok_l$59 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144700.14-144705.4"
+ attribute \src "libresoc.v:144364.14-144369.4"
cell \rst_l$58 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144706.14-144712.4"
+ attribute \src "libresoc.v:144370.14-144376.4"
cell \src_l$55 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:143886.7-143886.20"
- process $proc$libresoc.v:143886$6802
+ attribute \src "libresoc.v:143550.7-143550.20"
+ process $proc$libresoc.v:143550$6750
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:144004.7-144004.24"
- process $proc$libresoc.v:144004$6803
+ attribute \src "libresoc.v:143668.7-143668.24"
+ process $proc$libresoc.v:143668$6751
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:144014.7-144014.26"
- process $proc$libresoc.v:144014$6804
+ attribute \src "libresoc.v:143678.7-143678.26"
+ process $proc$libresoc.v:143678$6752
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:144022.7-144022.25"
- process $proc$libresoc.v:144022$6805
+ attribute \src "libresoc.v:143686.7-143686.25"
+ process $proc$libresoc.v:143686$6753
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:144030.13-144030.53"
- process $proc$libresoc.v:144030$6806
+ attribute \src "libresoc.v:143694.13-143694.53"
+ process $proc$libresoc.v:143694$6754
assign { } { }
assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:144049.14-144049.57"
- process $proc$libresoc.v:144049$6807
+ attribute \src "libresoc.v:143713.14-143713.57"
+ process $proc$libresoc.v:143713$6755
assign { } { }
assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:144053.14-144053.76"
- process $proc$libresoc.v:144053$6808
+ attribute \src "libresoc.v:143717.14-143717.76"
+ process $proc$libresoc.v:143717$6756
assign { } { }
assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:144057.7-144057.51"
- process $proc$libresoc.v:144057$6809
+ attribute \src "libresoc.v:143721.7-143721.51"
+ process $proc$libresoc.v:143721$6757
assign { } { }
assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:144065.13-144065.56"
- process $proc$libresoc.v:144065$6810
+ attribute \src "libresoc.v:143729.13-143729.56"
+ process $proc$libresoc.v:143729$6758
assign { } { }
assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:144069.14-144069.51"
- process $proc$libresoc.v:144069$6811
+ attribute \src "libresoc.v:143733.14-143733.51"
+ process $proc$libresoc.v:143733$6759
assign { } { }
assign $1\alu_logical0_logical_op__insn[31:0] 0
sync always
sync init
update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:144148.13-144148.55"
- process $proc$libresoc.v:144148$6812
+ attribute \src "libresoc.v:143812.13-143812.55"
+ process $proc$libresoc.v:143812$6760
assign { } { }
assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:144152.7-144152.48"
- process $proc$libresoc.v:144152$6813
+ attribute \src "libresoc.v:143816.7-143816.48"
+ process $proc$libresoc.v:143816$6761
assign { } { }
assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:144156.7-144156.49"
- process $proc$libresoc.v:144156$6814
+ attribute \src "libresoc.v:143820.7-143820.49"
+ process $proc$libresoc.v:143820$6762
assign { } { }
assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:144160.7-144160.47"
- process $proc$libresoc.v:144160$6815
+ attribute \src "libresoc.v:143824.7-143824.47"
+ process $proc$libresoc.v:143824$6763
assign { } { }
assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:144164.7-144164.48"
- process $proc$libresoc.v:144164$6816
+ attribute \src "libresoc.v:143828.7-143828.48"
+ process $proc$libresoc.v:143828$6764
assign { } { }
assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:144168.7-144168.45"
- process $proc$libresoc.v:144168$6817
+ attribute \src "libresoc.v:143832.7-143832.45"
+ process $proc$libresoc.v:143832$6765
assign { } { }
assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:144172.7-144172.45"
- process $proc$libresoc.v:144172$6818
+ attribute \src "libresoc.v:143836.7-143836.45"
+ process $proc$libresoc.v:143836$6766
assign { } { }
assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:144176.7-144176.51"
- process $proc$libresoc.v:144176$6819
+ attribute \src "libresoc.v:143840.7-143840.51"
+ process $proc$libresoc.v:143840$6767
assign { } { }
assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:144180.7-144180.45"
- process $proc$libresoc.v:144180$6820
+ attribute \src "libresoc.v:143844.7-143844.45"
+ process $proc$libresoc.v:143844$6768
assign { } { }
assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:144184.7-144184.45"
- process $proc$libresoc.v:144184$6821
+ attribute \src "libresoc.v:143848.7-143848.45"
+ process $proc$libresoc.v:143848$6769
assign { } { }
assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:144188.7-144188.48"
- process $proc$libresoc.v:144188$6822
+ attribute \src "libresoc.v:143852.7-143852.48"
+ process $proc$libresoc.v:143852$6770
assign { } { }
assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:144192.7-144192.45"
- process $proc$libresoc.v:144192$6823
+ attribute \src "libresoc.v:143856.7-143856.45"
+ process $proc$libresoc.v:143856$6771
assign { } { }
assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:144218.7-144218.27"
- process $proc$libresoc.v:144218$6824
+ attribute \src "libresoc.v:143882.7-143882.27"
+ process $proc$libresoc.v:143882$6772
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:144252.14-144252.47"
- process $proc$libresoc.v:144252$6825
+ attribute \src "libresoc.v:143916.14-143916.47"
+ process $proc$libresoc.v:143916$6773
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:144256.7-144256.27"
- process $proc$libresoc.v:144256$6826
+ attribute \src "libresoc.v:143920.7-143920.27"
+ process $proc$libresoc.v:143920$6774
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:144260.13-144260.33"
- process $proc$libresoc.v:144260$6827
+ attribute \src "libresoc.v:143924.13-143924.33"
+ process $proc$libresoc.v:143924$6775
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:144264.7-144264.30"
- process $proc$libresoc.v:144264$6828
+ attribute \src "libresoc.v:143928.7-143928.30"
+ process $proc$libresoc.v:143928$6776
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:144278.7-144278.25"
- process $proc$libresoc.v:144278$6829
+ attribute \src "libresoc.v:143942.7-143942.25"
+ process $proc$libresoc.v:143942$6777
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:144282.7-144282.25"
- process $proc$libresoc.v:144282$6830
+ attribute \src "libresoc.v:143946.7-143946.25"
+ process $proc$libresoc.v:143946$6778
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:144416.13-144416.30"
- process $proc$libresoc.v:144416$6831
+ attribute \src "libresoc.v:144080.13-144080.30"
+ process $proc$libresoc.v:144080$6779
assign { } { }
assign $1\prev_wr_go[1:0] 2'00
sync always
sync init
update \prev_wr_go $1\prev_wr_go[1:0]
end
- attribute \src "libresoc.v:144424.13-144424.31"
- process $proc$libresoc.v:144424$6832
+ attribute \src "libresoc.v:144088.13-144088.31"
+ process $proc$libresoc.v:144088$6780
assign { } { }
assign $1\req_l_r_req[1:0] 2'11
sync always
sync init
update \req_l_r_req $1\req_l_r_req[1:0]
end
- attribute \src "libresoc.v:144428.13-144428.31"
- process $proc$libresoc.v:144428$6833
+ attribute \src "libresoc.v:144092.13-144092.31"
+ process $proc$libresoc.v:144092$6781
assign { } { }
assign $1\req_l_s_req[1:0] 2'00
sync always
sync init
update \req_l_s_req $1\req_l_s_req[1:0]
end
- attribute \src "libresoc.v:144440.7-144440.26"
- process $proc$libresoc.v:144440$6834
+ attribute \src "libresoc.v:144104.7-144104.26"
+ process $proc$libresoc.v:144104$6782
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:144444.7-144444.26"
- process $proc$libresoc.v:144444$6835
+ attribute \src "libresoc.v:144108.7-144108.26"
+ process $proc$libresoc.v:144108$6783
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:144448.7-144448.25"
- process $proc$libresoc.v:144448$6836
+ attribute \src "libresoc.v:144112.7-144112.25"
+ process $proc$libresoc.v:144112$6784
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:144452.7-144452.25"
- process $proc$libresoc.v:144452$6837
+ attribute \src "libresoc.v:144116.7-144116.25"
+ process $proc$libresoc.v:144116$6785
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:144466.13-144466.31"
- process $proc$libresoc.v:144466$6838
+ attribute \src "libresoc.v:144130.13-144130.31"
+ process $proc$libresoc.v:144130$6786
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:144470.13-144470.31"
- process $proc$libresoc.v:144470$6839
+ attribute \src "libresoc.v:144134.13-144134.31"
+ process $proc$libresoc.v:144134$6787
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:144478.14-144478.43"
- process $proc$libresoc.v:144478$6840
+ attribute \src "libresoc.v:144142.14-144142.43"
+ process $proc$libresoc.v:144142$6788
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:144482.14-144482.43"
- process $proc$libresoc.v:144482$6841
+ attribute \src "libresoc.v:144146.14-144146.43"
+ process $proc$libresoc.v:144146$6789
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:144486.7-144486.20"
- process $proc$libresoc.v:144486$6842
+ attribute \src "libresoc.v:144150.7-144150.20"
+ process $proc$libresoc.v:144150$6790
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:144552.3-144553.39"
- process $proc$libresoc.v:144552$6652
+ attribute \src "libresoc.v:144216.3-144217.39"
+ process $proc$libresoc.v:144216$6600
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:144554.3-144555.43"
- process $proc$libresoc.v:144554$6653
+ attribute \src "libresoc.v:144218.3-144219.43"
+ process $proc$libresoc.v:144218$6601
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:144556.3-144557.29"
- process $proc$libresoc.v:144556$6654
+ attribute \src "libresoc.v:144220.3-144221.29"
+ process $proc$libresoc.v:144220$6602
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:144558.3-144559.29"
- process $proc$libresoc.v:144558$6655
+ attribute \src "libresoc.v:144222.3-144223.29"
+ process $proc$libresoc.v:144222$6603
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:144560.3-144561.29"
- process $proc$libresoc.v:144560$6656
+ attribute \src "libresoc.v:144224.3-144225.29"
+ process $proc$libresoc.v:144224$6604
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:144562.3-144563.43"
- process $proc$libresoc.v:144562$6657
+ attribute \src "libresoc.v:144226.3-144227.43"
+ process $proc$libresoc.v:144226$6605
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:144564.3-144565.49"
- process $proc$libresoc.v:144564$6658
+ attribute \src "libresoc.v:144228.3-144229.49"
+ process $proc$libresoc.v:144228$6606
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:144566.3-144567.37"
- process $proc$libresoc.v:144566$6659
+ attribute \src "libresoc.v:144230.3-144231.37"
+ process $proc$libresoc.v:144230$6607
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:144568.3-144569.43"
- process $proc$libresoc.v:144568$6660
+ attribute \src "libresoc.v:144232.3-144233.43"
+ process $proc$libresoc.v:144232$6608
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:144570.3-144571.85"
- process $proc$libresoc.v:144570$6661
+ attribute \src "libresoc.v:144234.3-144235.85"
+ process $proc$libresoc.v:144234$6609
assign { } { }
assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:144572.3-144573.81"
- process $proc$libresoc.v:144572$6662
+ attribute \src "libresoc.v:144236.3-144237.81"
+ process $proc$libresoc.v:144236$6610
assign { } { }
assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:144574.3-144575.95"
- process $proc$libresoc.v:144574$6663
+ attribute \src "libresoc.v:144238.3-144239.95"
+ process $proc$libresoc.v:144238$6611
assign { } { }
assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:144576.3-144577.91"
- process $proc$libresoc.v:144576$6664
+ attribute \src "libresoc.v:144240.3-144241.91"
+ process $proc$libresoc.v:144240$6612
assign { } { }
assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:144578.3-144579.79"
- process $proc$libresoc.v:144578$6665
+ attribute \src "libresoc.v:144242.3-144243.79"
+ process $proc$libresoc.v:144242$6613
assign { } { }
assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:144580.3-144581.79"
- process $proc$libresoc.v:144580$6666
+ attribute \src "libresoc.v:144244.3-144245.79"
+ process $proc$libresoc.v:144244$6614
assign { } { }
assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:144582.3-144583.79"
- process $proc$libresoc.v:144582$6667
+ attribute \src "libresoc.v:144246.3-144247.79"
+ process $proc$libresoc.v:144246$6615
assign { } { }
assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:144584.3-144585.79"
- process $proc$libresoc.v:144584$6668
+ attribute \src "libresoc.v:144248.3-144249.79"
+ process $proc$libresoc.v:144248$6616
assign { } { }
assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:144586.3-144587.85"
- process $proc$libresoc.v:144586$6669
+ attribute \src "libresoc.v:144250.3-144251.85"
+ process $proc$libresoc.v:144250$6617
assign { } { }
assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:144588.3-144589.79"
- process $proc$libresoc.v:144588$6670
+ attribute \src "libresoc.v:144252.3-144253.79"
+ process $proc$libresoc.v:144252$6618
assign { } { }
assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:144590.3-144591.89"
- process $proc$libresoc.v:144590$6671
+ attribute \src "libresoc.v:144254.3-144255.89"
+ process $proc$libresoc.v:144254$6619
assign { } { }
assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:144592.3-144593.87"
- process $proc$libresoc.v:144592$6672
+ attribute \src "libresoc.v:144256.3-144257.87"
+ process $proc$libresoc.v:144256$6620
assign { } { }
assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:144594.3-144595.85"
- process $proc$libresoc.v:144594$6673
+ attribute \src "libresoc.v:144258.3-144259.85"
+ process $proc$libresoc.v:144258$6621
assign { } { }
assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:144596.3-144597.91"
- process $proc$libresoc.v:144596$6674
+ attribute \src "libresoc.v:144260.3-144261.91"
+ process $proc$libresoc.v:144260$6622
assign { } { }
assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:144598.3-144599.83"
- process $proc$libresoc.v:144598$6675
+ attribute \src "libresoc.v:144262.3-144263.83"
+ process $proc$libresoc.v:144262$6623
assign { } { }
assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:144600.3-144601.85"
- process $proc$libresoc.v:144600$6676
+ attribute \src "libresoc.v:144264.3-144265.85"
+ process $proc$libresoc.v:144264$6624
assign { } { }
assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:144602.3-144603.83"
- process $proc$libresoc.v:144602$6677
+ attribute \src "libresoc.v:144266.3-144267.83"
+ process $proc$libresoc.v:144266$6625
assign { } { }
assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:144604.3-144605.75"
- process $proc$libresoc.v:144604$6678
+ attribute \src "libresoc.v:144268.3-144269.75"
+ process $proc$libresoc.v:144268$6626
assign { } { }
assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:144606.3-144607.39"
- process $proc$libresoc.v:144606$6679
+ attribute \src "libresoc.v:144270.3-144271.39"
+ process $proc$libresoc.v:144270$6627
assign { } { }
assign $0\req_l_r_req[1:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[1:0]
end
- attribute \src "libresoc.v:144608.3-144609.39"
- process $proc$libresoc.v:144608$6680
+ attribute \src "libresoc.v:144272.3-144273.39"
+ process $proc$libresoc.v:144272$6628
assign { } { }
assign $0\req_l_s_req[1:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[1:0]
end
- attribute \src "libresoc.v:144610.3-144611.39"
- process $proc$libresoc.v:144610$6681
+ attribute \src "libresoc.v:144274.3-144275.39"
+ process $proc$libresoc.v:144274$6629
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:144612.3-144613.39"
- process $proc$libresoc.v:144612$6682
+ attribute \src "libresoc.v:144276.3-144277.39"
+ process $proc$libresoc.v:144276$6630
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:144614.3-144615.39"
- process $proc$libresoc.v:144614$6683
+ attribute \src "libresoc.v:144278.3-144279.39"
+ process $proc$libresoc.v:144278$6631
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:144616.3-144617.39"
- process $proc$libresoc.v:144616$6684
+ attribute \src "libresoc.v:144280.3-144281.39"
+ process $proc$libresoc.v:144280$6632
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:144618.3-144619.39"
- process $proc$libresoc.v:144618$6685
+ attribute \src "libresoc.v:144282.3-144283.39"
+ process $proc$libresoc.v:144282$6633
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:144620.3-144621.39"
- process $proc$libresoc.v:144620$6686
+ attribute \src "libresoc.v:144284.3-144285.39"
+ process $proc$libresoc.v:144284$6634
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:144622.3-144623.41"
- process $proc$libresoc.v:144622$6687
+ attribute \src "libresoc.v:144286.3-144287.41"
+ process $proc$libresoc.v:144286$6635
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:144624.3-144625.41"
- process $proc$libresoc.v:144624$6688
+ attribute \src "libresoc.v:144288.3-144289.41"
+ process $proc$libresoc.v:144288$6636
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:144626.3-144627.37"
- process $proc$libresoc.v:144626$6689
+ attribute \src "libresoc.v:144290.3-144291.37"
+ process $proc$libresoc.v:144290$6637
assign { } { }
assign $0\prev_wr_go[1:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[1:0]
end
- attribute \src "libresoc.v:144628.3-144629.44"
- process $proc$libresoc.v:144628$6690
+ attribute \src "libresoc.v:144292.3-144293.44"
+ process $proc$libresoc.v:144292$6638
assign { } { }
assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:144630.3-144631.24"
- process $proc$libresoc.v:144630$6691
+ attribute \src "libresoc.v:144294.3-144295.24"
+ process $proc$libresoc.v:144294$6639
assign { } { }
assign $0\all_rd_dly[0:0] \$9
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:144713.3-144722.6"
- process $proc$libresoc.v:144713$6692
+ attribute \src "libresoc.v:144377.3-144386.6"
+ process $proc$libresoc.v:144377$6640
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:144714.5-144714.29"
+ attribute \src "libresoc.v:144378.5-144378.29"
switch \initial
- attribute \src "libresoc.v:144714.9-144714.17"
+ attribute \src "libresoc.v:144378.9-144378.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:144723.3-144731.6"
- process $proc$libresoc.v:144723$6693
+ attribute \src "libresoc.v:144387.3-144395.6"
+ process $proc$libresoc.v:144387$6641
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$6694 $1\rok_l_s_rdok$next[0:0]$6695
- attribute \src "libresoc.v:144724.5-144724.29"
+ assign $0\rok_l_s_rdok$next[0:0]$6642 $1\rok_l_s_rdok$next[0:0]$6643
+ attribute \src "libresoc.v:144388.5-144388.29"
switch \initial
- attribute \src "libresoc.v:144724.9-144724.17"
+ attribute \src "libresoc.v:144388.9-144388.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$6695 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$6643 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$6695 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$6643 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6694
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6642
end
- attribute \src "libresoc.v:144732.3-144740.6"
- process $proc$libresoc.v:144732$6696
+ attribute \src "libresoc.v:144396.3-144404.6"
+ process $proc$libresoc.v:144396$6644
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$6697 $1\rok_l_r_rdok$next[0:0]$6698
- attribute \src "libresoc.v:144733.5-144733.29"
+ assign $0\rok_l_r_rdok$next[0:0]$6645 $1\rok_l_r_rdok$next[0:0]$6646
+ attribute \src "libresoc.v:144397.5-144397.29"
switch \initial
- attribute \src "libresoc.v:144733.9-144733.17"
+ attribute \src "libresoc.v:144397.9-144397.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$6698 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$6646 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$6698 \$63
+ assign $1\rok_l_r_rdok$next[0:0]$6646 \$63
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6697
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6645
end
- attribute \src "libresoc.v:144741.3-144749.6"
- process $proc$libresoc.v:144741$6699
+ attribute \src "libresoc.v:144405.3-144413.6"
+ process $proc$libresoc.v:144405$6647
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$6700 $1\rst_l_s_rst$next[0:0]$6701
- attribute \src "libresoc.v:144742.5-144742.29"
+ assign $0\rst_l_s_rst$next[0:0]$6648 $1\rst_l_s_rst$next[0:0]$6649
+ attribute \src "libresoc.v:144406.5-144406.29"
switch \initial
- attribute \src "libresoc.v:144742.9-144742.17"
+ attribute \src "libresoc.v:144406.9-144406.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$6701 1'0
+ assign $1\rst_l_s_rst$next[0:0]$6649 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$6701 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$6649 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6700
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6648
end
- attribute \src "libresoc.v:144750.3-144758.6"
- process $proc$libresoc.v:144750$6702
+ attribute \src "libresoc.v:144414.3-144422.6"
+ process $proc$libresoc.v:144414$6650
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$6703 $1\rst_l_r_rst$next[0:0]$6704
- attribute \src "libresoc.v:144751.5-144751.29"
+ assign $0\rst_l_r_rst$next[0:0]$6651 $1\rst_l_r_rst$next[0:0]$6652
+ attribute \src "libresoc.v:144415.5-144415.29"
switch \initial
- attribute \src "libresoc.v:144751.9-144751.17"
+ attribute \src "libresoc.v:144415.9-144415.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$6704 1'1
+ assign $1\rst_l_r_rst$next[0:0]$6652 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$6704 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$6652 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6703
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6651
end
- attribute \src "libresoc.v:144759.3-144767.6"
- process $proc$libresoc.v:144759$6705
+ attribute \src "libresoc.v:144423.3-144431.6"
+ process $proc$libresoc.v:144423$6653
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$6706 $1\opc_l_s_opc$next[0:0]$6707
- attribute \src "libresoc.v:144760.5-144760.29"
+ assign $0\opc_l_s_opc$next[0:0]$6654 $1\opc_l_s_opc$next[0:0]$6655
+ attribute \src "libresoc.v:144424.5-144424.29"
switch \initial
- attribute \src "libresoc.v:144760.9-144760.17"
+ attribute \src "libresoc.v:144424.9-144424.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$6707 1'0
+ assign $1\opc_l_s_opc$next[0:0]$6655 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$6707 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$6655 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6706
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6654
end
- attribute \src "libresoc.v:144768.3-144776.6"
- process $proc$libresoc.v:144768$6708
+ attribute \src "libresoc.v:144432.3-144440.6"
+ process $proc$libresoc.v:144432$6656
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$6709 $1\opc_l_r_opc$next[0:0]$6710
- attribute \src "libresoc.v:144769.5-144769.29"
+ assign $0\opc_l_r_opc$next[0:0]$6657 $1\opc_l_r_opc$next[0:0]$6658
+ attribute \src "libresoc.v:144433.5-144433.29"
switch \initial
- attribute \src "libresoc.v:144769.9-144769.17"
+ attribute \src "libresoc.v:144433.9-144433.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$6710 1'1
+ assign $1\opc_l_r_opc$next[0:0]$6658 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$6710 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$6658 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6709
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6657
end
- attribute \src "libresoc.v:144777.3-144785.6"
- process $proc$libresoc.v:144777$6711
+ attribute \src "libresoc.v:144441.3-144449.6"
+ process $proc$libresoc.v:144441$6659
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$6712 $1\src_l_s_src$next[2:0]$6713
- attribute \src "libresoc.v:144778.5-144778.29"
+ assign $0\src_l_s_src$next[2:0]$6660 $1\src_l_s_src$next[2:0]$6661
+ attribute \src "libresoc.v:144442.5-144442.29"
switch \initial
- attribute \src "libresoc.v:144778.9-144778.17"
+ attribute \src "libresoc.v:144442.9-144442.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$6713 3'000
+ assign $1\src_l_s_src$next[2:0]$6661 3'000
case
- assign $1\src_l_s_src$next[2:0]$6713 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$6661 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6712
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6660
end
- attribute \src "libresoc.v:144786.3-144794.6"
- process $proc$libresoc.v:144786$6714
+ attribute \src "libresoc.v:144450.3-144458.6"
+ process $proc$libresoc.v:144450$6662
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$6715 $1\src_l_r_src$next[2:0]$6716
- attribute \src "libresoc.v:144787.5-144787.29"
+ assign $0\src_l_r_src$next[2:0]$6663 $1\src_l_r_src$next[2:0]$6664
+ attribute \src "libresoc.v:144451.5-144451.29"
switch \initial
- attribute \src "libresoc.v:144787.9-144787.17"
+ attribute \src "libresoc.v:144451.9-144451.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$6716 3'111
+ assign $1\src_l_r_src$next[2:0]$6664 3'111
case
- assign $1\src_l_r_src$next[2:0]$6716 \reset_r
+ assign $1\src_l_r_src$next[2:0]$6664 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6715
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6663
end
- attribute \src "libresoc.v:144795.3-144803.6"
- process $proc$libresoc.v:144795$6717
+ attribute \src "libresoc.v:144459.3-144467.6"
+ process $proc$libresoc.v:144459$6665
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[1:0]$6718 $1\req_l_s_req$next[1:0]$6719
- attribute \src "libresoc.v:144796.5-144796.29"
+ assign $0\req_l_s_req$next[1:0]$6666 $1\req_l_s_req$next[1:0]$6667
+ attribute \src "libresoc.v:144460.5-144460.29"
switch \initial
- attribute \src "libresoc.v:144796.9-144796.17"
+ attribute \src "libresoc.v:144460.9-144460.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[1:0]$6719 2'00
+ assign $1\req_l_s_req$next[1:0]$6667 2'00
case
- assign $1\req_l_s_req$next[1:0]$6719 \$65
+ assign $1\req_l_s_req$next[1:0]$6667 \$65
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6718
+ update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6666
end
- attribute \src "libresoc.v:144804.3-144812.6"
- process $proc$libresoc.v:144804$6720
+ attribute \src "libresoc.v:144468.3-144476.6"
+ process $proc$libresoc.v:144468$6668
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[1:0]$6721 $1\req_l_r_req$next[1:0]$6722
- attribute \src "libresoc.v:144805.5-144805.29"
+ assign $0\req_l_r_req$next[1:0]$6669 $1\req_l_r_req$next[1:0]$6670
+ attribute \src "libresoc.v:144469.5-144469.29"
switch \initial
- attribute \src "libresoc.v:144805.9-144805.17"
+ attribute \src "libresoc.v:144469.9-144469.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[1:0]$6722 2'11
+ assign $1\req_l_r_req$next[1:0]$6670 2'11
case
- assign $1\req_l_r_req$next[1:0]$6722 \$67
+ assign $1\req_l_r_req$next[1:0]$6670 \$67
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6721
+ update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6669
end
- attribute \src "libresoc.v:144813.3-144851.6"
- process $proc$libresoc.v:144813$6723
+ attribute \src "libresoc.v:144477.3-144515.6"
+ process $proc$libresoc.v:144477$6671
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__data_len$next[3:0]$6724 $1\alu_logical0_logical_op__data_len$next[3:0]$6742
- assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743
+ assign $0\alu_logical0_logical_op__data_len$next[3:0]$6672 $1\alu_logical0_logical_op__data_len$next[3:0]$6690
+ assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6728 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746
- assign $0\alu_logical0_logical_op__insn$next[31:0]$6729 $1\alu_logical0_logical_op__insn$next[31:0]$6747
- assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6730 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748
- assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6731 $1\alu_logical0_logical_op__invert_in$next[0:0]$6749
- assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6732 $1\alu_logical0_logical_op__invert_out$next[0:0]$6750
- assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751
- assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6734 $1\alu_logical0_logical_op__is_signed$next[0:0]$6752
+ assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694
+ assign $0\alu_logical0_logical_op__insn$next[31:0]$6677 $1\alu_logical0_logical_op__insn$next[31:0]$6695
+ assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696
+ assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697
+ assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698
+ assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699
+ assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6737 $1\alu_logical0_logical_op__output_carry$next[0:0]$6755
+ assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758
- assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6741 $1\alu_logical0_logical_op__zero_a$next[0:0]$6759
- assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760
- assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761
- assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762
- assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763
- assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764
- assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765
- attribute \src "libresoc.v:144814.5-144814.29"
+ assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706
+ assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707
+ assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708
+ assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709
+ assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710
+ assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711
+ assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712
+ assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713
+ attribute \src "libresoc.v:144478.5-144478.29"
switch \initial
- attribute \src "libresoc.v:144814.9-144814.17"
+ attribute \src "libresoc.v:144478.9-144478.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_logical0_logical_op__insn$next[31:0]$6747 $1\alu_logical0_logical_op__data_len$next[3:0]$6742 $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
+ assign { $1\alu_logical0_logical_op__insn$next[31:0]$6695 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
case
- assign $1\alu_logical0_logical_op__data_len$next[3:0]$6742 \alu_logical0_logical_op__data_len
- assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 \alu_logical0_logical_op__fn_unit
- assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 \alu_logical0_logical_op__imm_data__data
- assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 \alu_logical0_logical_op__imm_data__ok
- assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 \alu_logical0_logical_op__input_carry
- assign $1\alu_logical0_logical_op__insn$next[31:0]$6747 \alu_logical0_logical_op__insn
- assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 \alu_logical0_logical_op__insn_type
- assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 \alu_logical0_logical_op__invert_in
- assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 \alu_logical0_logical_op__invert_out
- assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 \alu_logical0_logical_op__is_32bit
- assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 \alu_logical0_logical_op__is_signed
- assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 \alu_logical0_logical_op__oe__oe
- assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 \alu_logical0_logical_op__oe__ok
- assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 \alu_logical0_logical_op__output_carry
- assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 \alu_logical0_logical_op__rc__ok
- assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 \alu_logical0_logical_op__rc__rc
- assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 \alu_logical0_logical_op__write_cr0
- assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 \alu_logical0_logical_op__zero_a
+ assign $1\alu_logical0_logical_op__data_len$next[3:0]$6690 \alu_logical0_logical_op__data_len
+ assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 \alu_logical0_logical_op__fn_unit
+ assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 \alu_logical0_logical_op__imm_data__data
+ assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 \alu_logical0_logical_op__imm_data__ok
+ assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 \alu_logical0_logical_op__input_carry
+ assign $1\alu_logical0_logical_op__insn$next[31:0]$6695 \alu_logical0_logical_op__insn
+ assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 \alu_logical0_logical_op__insn_type
+ assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 \alu_logical0_logical_op__invert_in
+ assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 \alu_logical0_logical_op__invert_out
+ assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 \alu_logical0_logical_op__is_32bit
+ assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 \alu_logical0_logical_op__is_signed
+ assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 \alu_logical0_logical_op__oe__oe
+ assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 \alu_logical0_logical_op__oe__ok
+ assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 \alu_logical0_logical_op__output_carry
+ assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 \alu_logical0_logical_op__rc__ok
+ assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 \alu_logical0_logical_op__rc__rc
+ assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 \alu_logical0_logical_op__write_cr0
+ assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 \alu_logical0_logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 1'0
- assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 1'0
- assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 1'0
- assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 1'0
- assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 1'0
+ assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 1'0
+ assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 1'0
+ assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 1'0
+ assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 1'0
+ assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 1'0
case
- assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744
- assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745
- assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753
- assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754
- assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756
- assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757
+ assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692
+ assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693
+ assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701
+ assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702
+ assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704
+ assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705
end
sync always
- update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6724
- update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725
- update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726
- update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727
- update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6728
- update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6729
- update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6730
- update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6731
- update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6732
- update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733
- update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6734
- update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735
- update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736
- update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6737
- update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738
- update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739
- update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740
- update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6741
+ update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6672
+ update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673
+ update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674
+ update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675
+ update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6676
+ update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6677
+ update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6678
+ update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6679
+ update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6680
+ update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681
+ update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6682
+ update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683
+ update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684
+ update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6685
+ update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686
+ update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687
+ update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688
+ update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6689
end
- attribute \src "libresoc.v:144852.3-144873.6"
- process $proc$libresoc.v:144852$6766
+ attribute \src "libresoc.v:144516.3-144537.6"
+ process $proc$libresoc.v:144516$6714
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$6767 $2\data_r0__o$next[63:0]$6771
+ assign $0\data_r0__o$next[63:0]$6715 $2\data_r0__o$next[63:0]$6719
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$6768 $3\data_r0__o_ok$next[0:0]$6773
- attribute \src "libresoc.v:144853.5-144853.29"
+ assign $0\data_r0__o_ok$next[0:0]$6716 $3\data_r0__o_ok$next[0:0]$6721
+ attribute \src "libresoc.v:144517.5-144517.29"
switch \initial
- attribute \src "libresoc.v:144853.9-144853.17"
+ attribute \src "libresoc.v:144517.9-144517.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$6770 $1\data_r0__o$next[63:0]$6769 } { \o_ok \alu_logical0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$6718 $1\data_r0__o$next[63:0]$6717 } { \o_ok \alu_logical0_o }
case
- assign $1\data_r0__o$next[63:0]$6769 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$6770 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$6717 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$6718 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$6772 $2\data_r0__o$next[63:0]$6771 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$6720 $2\data_r0__o$next[63:0]$6719 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$6771 $1\data_r0__o$next[63:0]$6769
- assign $2\data_r0__o_ok$next[0:0]$6772 $1\data_r0__o_ok$next[0:0]$6770
+ assign $2\data_r0__o$next[63:0]$6719 $1\data_r0__o$next[63:0]$6717
+ assign $2\data_r0__o_ok$next[0:0]$6720 $1\data_r0__o_ok$next[0:0]$6718
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$6773 1'0
+ assign $3\data_r0__o_ok$next[0:0]$6721 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$6773 $2\data_r0__o_ok$next[0:0]$6772
+ assign $3\data_r0__o_ok$next[0:0]$6721 $2\data_r0__o_ok$next[0:0]$6720
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$6767
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6768
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$6715
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6716
end
- attribute \src "libresoc.v:144874.3-144895.6"
- process $proc$libresoc.v:144874$6774
+ attribute \src "libresoc.v:144538.3-144559.6"
+ process $proc$libresoc.v:144538$6722
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$6775 $2\data_r1__cr_a$next[3:0]$6779
+ assign $0\data_r1__cr_a$next[3:0]$6723 $2\data_r1__cr_a$next[3:0]$6727
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$6776 $3\data_r1__cr_a_ok$next[0:0]$6781
- attribute \src "libresoc.v:144875.5-144875.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$6724 $3\data_r1__cr_a_ok$next[0:0]$6729
+ attribute \src "libresoc.v:144539.5-144539.29"
switch \initial
- attribute \src "libresoc.v:144875.9-144875.17"
+ attribute \src "libresoc.v:144539.9-144539.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$6778 $1\data_r1__cr_a$next[3:0]$6777 } { \cr_a_ok \alu_logical0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$6726 $1\data_r1__cr_a$next[3:0]$6725 } { \cr_a_ok \alu_logical0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$6777 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$6778 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$6725 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$6726 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$6780 $2\data_r1__cr_a$next[3:0]$6779 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$6728 $2\data_r1__cr_a$next[3:0]$6727 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$6779 $1\data_r1__cr_a$next[3:0]$6777
- assign $2\data_r1__cr_a_ok$next[0:0]$6780 $1\data_r1__cr_a_ok$next[0:0]$6778
+ assign $2\data_r1__cr_a$next[3:0]$6727 $1\data_r1__cr_a$next[3:0]$6725
+ assign $2\data_r1__cr_a_ok$next[0:0]$6728 $1\data_r1__cr_a_ok$next[0:0]$6726
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$6781 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$6729 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$6781 $2\data_r1__cr_a_ok$next[0:0]$6780
+ assign $3\data_r1__cr_a_ok$next[0:0]$6729 $2\data_r1__cr_a_ok$next[0:0]$6728
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6775
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6776
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6723
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6724
end
- attribute \src "libresoc.v:144896.3-144905.6"
- process $proc$libresoc.v:144896$6782
+ attribute \src "libresoc.v:144560.3-144569.6"
+ process $proc$libresoc.v:144560$6730
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$6783 $1\src_r0$next[63:0]$6784
- attribute \src "libresoc.v:144897.5-144897.29"
+ assign $0\src_r0$next[63:0]$6731 $1\src_r0$next[63:0]$6732
+ attribute \src "libresoc.v:144561.5-144561.29"
switch \initial
- attribute \src "libresoc.v:144897.9-144897.17"
+ attribute \src "libresoc.v:144561.9-144561.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$6784 \src_or_imm
+ assign $1\src_r0$next[63:0]$6732 \src_or_imm
case
- assign $1\src_r0$next[63:0]$6784 \src_r0
+ assign $1\src_r0$next[63:0]$6732 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$6783
+ update \src_r0$next $0\src_r0$next[63:0]$6731
end
- attribute \src "libresoc.v:144906.3-144915.6"
- process $proc$libresoc.v:144906$6785
+ attribute \src "libresoc.v:144570.3-144579.6"
+ process $proc$libresoc.v:144570$6733
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$6786 $1\src_r1$next[63:0]$6787
- attribute \src "libresoc.v:144907.5-144907.29"
+ assign $0\src_r1$next[63:0]$6734 $1\src_r1$next[63:0]$6735
+ attribute \src "libresoc.v:144571.5-144571.29"
switch \initial
- attribute \src "libresoc.v:144907.9-144907.17"
+ attribute \src "libresoc.v:144571.9-144571.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$6787 \src_or_imm$80
+ assign $1\src_r1$next[63:0]$6735 \src_or_imm$80
case
- assign $1\src_r1$next[63:0]$6787 \src_r1
+ assign $1\src_r1$next[63:0]$6735 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$6786
+ update \src_r1$next $0\src_r1$next[63:0]$6734
end
- attribute \src "libresoc.v:144916.3-144925.6"
- process $proc$libresoc.v:144916$6788
+ attribute \src "libresoc.v:144580.3-144589.6"
+ process $proc$libresoc.v:144580$6736
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$6789 $1\src_r2$next[0:0]$6790
- attribute \src "libresoc.v:144917.5-144917.29"
+ assign $0\src_r2$next[0:0]$6737 $1\src_r2$next[0:0]$6738
+ attribute \src "libresoc.v:144581.5-144581.29"
switch \initial
- attribute \src "libresoc.v:144917.9-144917.17"
+ attribute \src "libresoc.v:144581.9-144581.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$6790 \src3_i
+ assign $1\src_r2$next[0:0]$6738 \src3_i
case
- assign $1\src_r2$next[0:0]$6790 \src_r2
+ assign $1\src_r2$next[0:0]$6738 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$6789
+ update \src_r2$next $0\src_r2$next[0:0]$6737
end
- attribute \src "libresoc.v:144926.3-144934.6"
- process $proc$libresoc.v:144926$6791
+ attribute \src "libresoc.v:144590.3-144598.6"
+ process $proc$libresoc.v:144590$6739
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$6792 $1\alui_l_r_alui$next[0:0]$6793
- attribute \src "libresoc.v:144927.5-144927.29"
+ assign $0\alui_l_r_alui$next[0:0]$6740 $1\alui_l_r_alui$next[0:0]$6741
+ attribute \src "libresoc.v:144591.5-144591.29"
switch \initial
- attribute \src "libresoc.v:144927.9-144927.17"
+ attribute \src "libresoc.v:144591.9-144591.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$6793 1'1
+ assign $1\alui_l_r_alui$next[0:0]$6741 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$6793 \$89
+ assign $1\alui_l_r_alui$next[0:0]$6741 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6792
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6740
end
- attribute \src "libresoc.v:144935.3-144943.6"
- process $proc$libresoc.v:144935$6794
+ attribute \src "libresoc.v:144599.3-144607.6"
+ process $proc$libresoc.v:144599$6742
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$6795 $1\alu_l_r_alu$next[0:0]$6796
- attribute \src "libresoc.v:144936.5-144936.29"
+ assign $0\alu_l_r_alu$next[0:0]$6743 $1\alu_l_r_alu$next[0:0]$6744
+ attribute \src "libresoc.v:144600.5-144600.29"
switch \initial
- attribute \src "libresoc.v:144936.9-144936.17"
+ attribute \src "libresoc.v:144600.9-144600.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$6796 1'1
+ assign $1\alu_l_r_alu$next[0:0]$6744 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$6796 \$91
+ assign $1\alu_l_r_alu$next[0:0]$6744 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6795
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6743
end
- attribute \src "libresoc.v:144944.3-144953.6"
- process $proc$libresoc.v:144944$6797
+ attribute \src "libresoc.v:144608.3-144617.6"
+ process $proc$libresoc.v:144608$6745
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:144945.5-144945.29"
+ attribute \src "libresoc.v:144609.5-144609.29"
switch \initial
- attribute \src "libresoc.v:144945.9-144945.17"
+ attribute \src "libresoc.v:144609.9-144609.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:144954.3-144963.6"
- process $proc$libresoc.v:144954$6798
+ attribute \src "libresoc.v:144618.3-144627.6"
+ process $proc$libresoc.v:144618$6746
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:144955.5-144955.29"
+ attribute \src "libresoc.v:144619.5-144619.29"
switch \initial
- attribute \src "libresoc.v:144955.9-144955.17"
+ attribute \src "libresoc.v:144619.9-144619.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:144964.3-144972.6"
- process $proc$libresoc.v:144964$6799
+ attribute \src "libresoc.v:144628.3-144636.6"
+ process $proc$libresoc.v:144628$6747
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[1:0]$6800 $1\prev_wr_go$next[1:0]$6801
- attribute \src "libresoc.v:144965.5-144965.29"
+ assign $0\prev_wr_go$next[1:0]$6748 $1\prev_wr_go$next[1:0]$6749
+ attribute \src "libresoc.v:144629.5-144629.29"
switch \initial
- attribute \src "libresoc.v:144965.9-144965.17"
+ attribute \src "libresoc.v:144629.9-144629.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[1:0]$6801 2'00
- case
- assign $1\prev_wr_go$next[1:0]$6801 \$19
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6800
- end
- connect \$9 $and$libresoc.v:144495$6595_Y
- connect \$99 $and$libresoc.v:144496$6596_Y
- connect \$101 $not$libresoc.v:144497$6597_Y
- connect \$103 $and$libresoc.v:144498$6598_Y
- connect \$105 $and$libresoc.v:144499$6599_Y
- connect \$107 $and$libresoc.v:144500$6600_Y
- connect \$109 $and$libresoc.v:144501$6601_Y
- connect \$111 $and$libresoc.v:144502$6602_Y
- connect \$113 $and$libresoc.v:144503$6603_Y
- connect \$115 $and$libresoc.v:144504$6604_Y
- connect \$11 $not$libresoc.v:144505$6605_Y
- connect \$13 $and$libresoc.v:144506$6606_Y
- connect \$15 $not$libresoc.v:144507$6607_Y
- connect \$17 $and$libresoc.v:144508$6608_Y
- connect \$1 $and$libresoc.v:144509$6609_Y
- connect \$19 $and$libresoc.v:144510$6610_Y
- connect \$23 $not$libresoc.v:144511$6611_Y
- connect \$25 $and$libresoc.v:144512$6612_Y
- connect \$22 $reduce_or$libresoc.v:144513$6613_Y
- connect \$21 $not$libresoc.v:144514$6614_Y
- connect \$29 $and$libresoc.v:144515$6615_Y
- connect \$31 $reduce_or$libresoc.v:144516$6616_Y
- connect \$33 $reduce_or$libresoc.v:144517$6617_Y
- connect \$35 $or$libresoc.v:144518$6618_Y
- connect \$37 $not$libresoc.v:144519$6619_Y
- connect \$39 $and$libresoc.v:144520$6620_Y
- connect \$41 $and$libresoc.v:144521$6621_Y
- connect \$43 $eq$libresoc.v:144522$6622_Y
- connect \$45 $and$libresoc.v:144523$6623_Y
- connect \$47 $eq$libresoc.v:144524$6624_Y
- connect \$4 $not$libresoc.v:144525$6625_Y
- connect \$49 $and$libresoc.v:144526$6626_Y
- connect \$51 $and$libresoc.v:144527$6627_Y
- connect \$53 $and$libresoc.v:144528$6628_Y
- connect \$55 $or$libresoc.v:144529$6629_Y
- connect \$57 $or$libresoc.v:144530$6630_Y
- connect \$59 $or$libresoc.v:144531$6631_Y
- connect \$61 $or$libresoc.v:144532$6632_Y
- connect \$63 $and$libresoc.v:144533$6633_Y
- connect \$65 $and$libresoc.v:144534$6634_Y
- connect \$67 $or$libresoc.v:144535$6635_Y
- connect \$6 $or$libresoc.v:144536$6636_Y
- connect \$69 $and$libresoc.v:144537$6637_Y
- connect \$71 $and$libresoc.v:144538$6638_Y
- connect \$73 $ternary$libresoc.v:144539$6639_Y
- connect \$75 $ternary$libresoc.v:144540$6640_Y
- connect \$78 $ternary$libresoc.v:144541$6641_Y
- connect \$3 $reduce_and$libresoc.v:144542$6642_Y
- connect \$81 $ternary$libresoc.v:144543$6643_Y
- connect \$83 $ternary$libresoc.v:144544$6644_Y
- connect \$85 $ternary$libresoc.v:144545$6645_Y
- connect \$87 $ternary$libresoc.v:144546$6646_Y
- connect \$89 $and$libresoc.v:144547$6647_Y
- connect \$91 $and$libresoc.v:144548$6648_Y
- connect \$93 $and$libresoc.v:144549$6649_Y
- connect \$95 $not$libresoc.v:144550$6650_Y
- connect \$97 $not$libresoc.v:144551$6651_Y
+ assign $1\prev_wr_go$next[1:0]$6749 2'00
+ case
+ assign $1\prev_wr_go$next[1:0]$6749 \$19
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6748
+ end
+ connect \$9 $and$libresoc.v:144159$6543_Y
+ connect \$99 $and$libresoc.v:144160$6544_Y
+ connect \$101 $not$libresoc.v:144161$6545_Y
+ connect \$103 $and$libresoc.v:144162$6546_Y
+ connect \$105 $and$libresoc.v:144163$6547_Y
+ connect \$107 $and$libresoc.v:144164$6548_Y
+ connect \$109 $and$libresoc.v:144165$6549_Y
+ connect \$111 $and$libresoc.v:144166$6550_Y
+ connect \$113 $and$libresoc.v:144167$6551_Y
+ connect \$115 $and$libresoc.v:144168$6552_Y
+ connect \$11 $not$libresoc.v:144169$6553_Y
+ connect \$13 $and$libresoc.v:144170$6554_Y
+ connect \$15 $not$libresoc.v:144171$6555_Y
+ connect \$17 $and$libresoc.v:144172$6556_Y
+ connect \$1 $and$libresoc.v:144173$6557_Y
+ connect \$19 $and$libresoc.v:144174$6558_Y
+ connect \$23 $not$libresoc.v:144175$6559_Y
+ connect \$25 $and$libresoc.v:144176$6560_Y
+ connect \$22 $reduce_or$libresoc.v:144177$6561_Y
+ connect \$21 $not$libresoc.v:144178$6562_Y
+ connect \$29 $and$libresoc.v:144179$6563_Y
+ connect \$31 $reduce_or$libresoc.v:144180$6564_Y
+ connect \$33 $reduce_or$libresoc.v:144181$6565_Y
+ connect \$35 $or$libresoc.v:144182$6566_Y
+ connect \$37 $not$libresoc.v:144183$6567_Y
+ connect \$39 $and$libresoc.v:144184$6568_Y
+ connect \$41 $and$libresoc.v:144185$6569_Y
+ connect \$43 $eq$libresoc.v:144186$6570_Y
+ connect \$45 $and$libresoc.v:144187$6571_Y
+ connect \$47 $eq$libresoc.v:144188$6572_Y
+ connect \$4 $not$libresoc.v:144189$6573_Y
+ connect \$49 $and$libresoc.v:144190$6574_Y
+ connect \$51 $and$libresoc.v:144191$6575_Y
+ connect \$53 $and$libresoc.v:144192$6576_Y
+ connect \$55 $or$libresoc.v:144193$6577_Y
+ connect \$57 $or$libresoc.v:144194$6578_Y
+ connect \$59 $or$libresoc.v:144195$6579_Y
+ connect \$61 $or$libresoc.v:144196$6580_Y
+ connect \$63 $and$libresoc.v:144197$6581_Y
+ connect \$65 $and$libresoc.v:144198$6582_Y
+ connect \$67 $or$libresoc.v:144199$6583_Y
+ connect \$6 $or$libresoc.v:144200$6584_Y
+ connect \$69 $and$libresoc.v:144201$6585_Y
+ connect \$71 $and$libresoc.v:144202$6586_Y
+ connect \$73 $ternary$libresoc.v:144203$6587_Y
+ connect \$75 $ternary$libresoc.v:144204$6588_Y
+ connect \$78 $ternary$libresoc.v:144205$6589_Y
+ connect \$3 $reduce_and$libresoc.v:144206$6590_Y
+ connect \$81 $ternary$libresoc.v:144207$6591_Y
+ connect \$83 $ternary$libresoc.v:144208$6592_Y
+ connect \$85 $ternary$libresoc.v:144209$6593_Y
+ connect \$87 $ternary$libresoc.v:144210$6594_Y
+ connect \$89 $and$libresoc.v:144211$6595_Y
+ connect \$91 $and$libresoc.v:144212$6596_Y
+ connect \$93 $and$libresoc.v:144213$6597_Y
+ connect \$95 $not$libresoc.v:144214$6598_Y
+ connect \$97 $not$libresoc.v:144215$6599_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$111
connect \all_rd_dly$next \all_rd
connect \all_rd \$9
end
-attribute \src "libresoc.v:145009.1-146400.10"
+attribute \src "libresoc.v:144673.1-146064.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1"
attribute \generator "nMigen"
module \logical_pipe1
- attribute \src "libresoc.v:146339.3-146357.6"
- wire width 4 $0\cr_a$next[3:0]$6927
- attribute \src "libresoc.v:146099.3-146100.25"
+ attribute \src "libresoc.v:146003.3-146021.6"
+ wire width 4 $0\cr_a$next[3:0]$6875
+ attribute \src "libresoc.v:145763.3-145764.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:146339.3-146357.6"
- wire $0\cr_a_ok$next[0:0]$6928
- attribute \src "libresoc.v:146101.3-146102.31"
+ attribute \src "libresoc.v:146003.3-146021.6"
+ wire $0\cr_a_ok$next[0:0]$6876
+ attribute \src "libresoc.v:145765.3-145766.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:145010.7-145010.20"
+ attribute \src "libresoc.v:144674.7-144674.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 4 $0\logical_op__data_len$next[3:0]$6878
- attribute \src "libresoc.v:146139.3-146140.57"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 4 $0\logical_op__data_len$next[3:0]$6826
+ attribute \src "libresoc.v:145803.3-145804.57"
wire width 4 $0\logical_op__data_len[3:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 14 $0\logical_op__fn_unit$next[13:0]$6879
- attribute \src "libresoc.v:146109.3-146110.55"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 14 $0\logical_op__fn_unit$next[13:0]$6827
+ attribute \src "libresoc.v:145773.3-145774.55"
wire width 14 $0\logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 64 $0\logical_op__imm_data__data$next[63:0]$6880
- attribute \src "libresoc.v:146111.3-146112.69"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 64 $0\logical_op__imm_data__data$next[63:0]$6828
+ attribute \src "libresoc.v:145775.3-145776.69"
wire width 64 $0\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__imm_data__ok$next[0:0]$6881
- attribute \src "libresoc.v:146113.3-146114.65"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__imm_data__ok$next[0:0]$6829
+ attribute \src "libresoc.v:145777.3-145778.65"
wire $0\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 2 $0\logical_op__input_carry$next[1:0]$6882
- attribute \src "libresoc.v:146127.3-146128.63"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 2 $0\logical_op__input_carry$next[1:0]$6830
+ attribute \src "libresoc.v:145791.3-145792.63"
wire width 2 $0\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 32 $0\logical_op__insn$next[31:0]$6883
- attribute \src "libresoc.v:146141.3-146142.49"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 32 $0\logical_op__insn$next[31:0]$6831
+ attribute \src "libresoc.v:145805.3-145806.49"
wire width 32 $0\logical_op__insn[31:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 7 $0\logical_op__insn_type$next[6:0]$6884
- attribute \src "libresoc.v:146107.3-146108.59"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 7 $0\logical_op__insn_type$next[6:0]$6832
+ attribute \src "libresoc.v:145771.3-145772.59"
wire width 7 $0\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__invert_in$next[0:0]$6885
- attribute \src "libresoc.v:146123.3-146124.59"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__invert_in$next[0:0]$6833
+ attribute \src "libresoc.v:145787.3-145788.59"
wire $0\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__invert_out$next[0:0]$6886
- attribute \src "libresoc.v:146129.3-146130.61"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__invert_out$next[0:0]$6834
+ attribute \src "libresoc.v:145793.3-145794.61"
wire $0\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__is_32bit$next[0:0]$6887
- attribute \src "libresoc.v:146135.3-146136.57"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__is_32bit$next[0:0]$6835
+ attribute \src "libresoc.v:145799.3-145800.57"
wire $0\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__is_signed$next[0:0]$6888
- attribute \src "libresoc.v:146137.3-146138.59"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__is_signed$next[0:0]$6836
+ attribute \src "libresoc.v:145801.3-145802.59"
wire $0\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__oe__oe$next[0:0]$6889
- attribute \src "libresoc.v:146119.3-146120.53"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__oe__oe$next[0:0]$6837
+ attribute \src "libresoc.v:145783.3-145784.53"
wire $0\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__oe__ok$next[0:0]$6890
- attribute \src "libresoc.v:146121.3-146122.53"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__oe__ok$next[0:0]$6838
+ attribute \src "libresoc.v:145785.3-145786.53"
wire $0\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__output_carry$next[0:0]$6891
- attribute \src "libresoc.v:146133.3-146134.65"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__output_carry$next[0:0]$6839
+ attribute \src "libresoc.v:145797.3-145798.65"
wire $0\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__rc__ok$next[0:0]$6892
- attribute \src "libresoc.v:146117.3-146118.53"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__rc__ok$next[0:0]$6840
+ attribute \src "libresoc.v:145781.3-145782.53"
wire $0\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__rc__rc$next[0:0]$6893
- attribute \src "libresoc.v:146115.3-146116.53"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__rc__rc$next[0:0]$6841
+ attribute \src "libresoc.v:145779.3-145780.53"
wire $0\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__write_cr0$next[0:0]$6894
- attribute \src "libresoc.v:146131.3-146132.59"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__write_cr0$next[0:0]$6842
+ attribute \src "libresoc.v:145795.3-145796.59"
wire $0\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $0\logical_op__zero_a$next[0:0]$6895
- attribute \src "libresoc.v:146125.3-146126.53"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $0\logical_op__zero_a$next[0:0]$6843
+ attribute \src "libresoc.v:145789.3-145790.53"
wire $0\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:146265.3-146277.6"
- wire width 2 $0\muxid$next[1:0]$6875
- attribute \src "libresoc.v:146143.3-146144.27"
+ attribute \src "libresoc.v:145929.3-145941.6"
+ wire width 2 $0\muxid$next[1:0]$6823
+ attribute \src "libresoc.v:145807.3-145808.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:146320.3-146338.6"
- wire width 64 $0\o$next[63:0]$6921
- attribute \src "libresoc.v:146103.3-146104.19"
+ attribute \src "libresoc.v:145984.3-146002.6"
+ wire width 64 $0\o$next[63:0]$6869
+ attribute \src "libresoc.v:145767.3-145768.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:146320.3-146338.6"
- wire $0\o_ok$next[0:0]$6922
- attribute \src "libresoc.v:146105.3-146106.25"
+ attribute \src "libresoc.v:145984.3-146002.6"
+ wire $0\o_ok$next[0:0]$6870
+ attribute \src "libresoc.v:145769.3-145770.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:146247.3-146264.6"
- wire $0\r_busy$next[0:0]$6871
- attribute \src "libresoc.v:146145.3-146146.29"
+ attribute \src "libresoc.v:145911.3-145928.6"
+ wire $0\r_busy$next[0:0]$6819
+ attribute \src "libresoc.v:145809.3-145810.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:146358.3-146376.6"
- wire $0\xer_so$next[0:0]$6933
- attribute \src "libresoc.v:146095.3-146096.29"
+ attribute \src "libresoc.v:146022.3-146040.6"
+ wire $0\xer_so$next[0:0]$6881
+ attribute \src "libresoc.v:145759.3-145760.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:146358.3-146376.6"
- wire $0\xer_so_ok$next[0:0]$6934
- attribute \src "libresoc.v:146097.3-146098.35"
+ attribute \src "libresoc.v:146022.3-146040.6"
+ wire $0\xer_so_ok$next[0:0]$6882
+ attribute \src "libresoc.v:145761.3-145762.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:146339.3-146357.6"
- wire width 4 $1\cr_a$next[3:0]$6929
- attribute \src "libresoc.v:145019.13-145019.24"
+ attribute \src "libresoc.v:146003.3-146021.6"
+ wire width 4 $1\cr_a$next[3:0]$6877
+ attribute \src "libresoc.v:144683.13-144683.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:146339.3-146357.6"
- wire $1\cr_a_ok$next[0:0]$6930
- attribute \src "libresoc.v:145028.7-145028.21"
+ attribute \src "libresoc.v:146003.3-146021.6"
+ wire $1\cr_a_ok$next[0:0]$6878
+ attribute \src "libresoc.v:144692.7-144692.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 4 $1\logical_op__data_len$next[3:0]$6896
- attribute \src "libresoc.v:145313.13-145313.40"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 4 $1\logical_op__data_len$next[3:0]$6844
+ attribute \src "libresoc.v:144977.13-144977.40"
wire width 4 $1\logical_op__data_len[3:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 14 $1\logical_op__fn_unit$next[13:0]$6897
- attribute \src "libresoc.v:145337.14-145337.44"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 14 $1\logical_op__fn_unit$next[13:0]$6845
+ attribute \src "libresoc.v:145001.14-145001.44"
wire width 14 $1\logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 64 $1\logical_op__imm_data__data$next[63:0]$6898
- attribute \src "libresoc.v:145376.14-145376.63"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 64 $1\logical_op__imm_data__data$next[63:0]$6846
+ attribute \src "libresoc.v:145040.14-145040.63"
wire width 64 $1\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__imm_data__ok$next[0:0]$6899
- attribute \src "libresoc.v:145385.7-145385.38"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__imm_data__ok$next[0:0]$6847
+ attribute \src "libresoc.v:145049.7-145049.38"
wire $1\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 2 $1\logical_op__input_carry$next[1:0]$6900
- attribute \src "libresoc.v:145398.13-145398.43"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 2 $1\logical_op__input_carry$next[1:0]$6848
+ attribute \src "libresoc.v:145062.13-145062.43"
wire width 2 $1\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 32 $1\logical_op__insn$next[31:0]$6901
- attribute \src "libresoc.v:145415.14-145415.38"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 32 $1\logical_op__insn$next[31:0]$6849
+ attribute \src "libresoc.v:145079.14-145079.38"
wire width 32 $1\logical_op__insn[31:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 7 $1\logical_op__insn_type$next[6:0]$6902
- attribute \src "libresoc.v:145499.13-145499.42"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 7 $1\logical_op__insn_type$next[6:0]$6850
+ attribute \src "libresoc.v:145163.13-145163.42"
wire width 7 $1\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__invert_in$next[0:0]$6903
- attribute \src "libresoc.v:145658.7-145658.35"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__invert_in$next[0:0]$6851
+ attribute \src "libresoc.v:145322.7-145322.35"
wire $1\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__invert_out$next[0:0]$6904
- attribute \src "libresoc.v:145667.7-145667.36"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__invert_out$next[0:0]$6852
+ attribute \src "libresoc.v:145331.7-145331.36"
wire $1\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__is_32bit$next[0:0]$6905
- attribute \src "libresoc.v:145676.7-145676.34"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__is_32bit$next[0:0]$6853
+ attribute \src "libresoc.v:145340.7-145340.34"
wire $1\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__is_signed$next[0:0]$6906
- attribute \src "libresoc.v:145685.7-145685.35"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__is_signed$next[0:0]$6854
+ attribute \src "libresoc.v:145349.7-145349.35"
wire $1\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__oe__oe$next[0:0]$6907
- attribute \src "libresoc.v:145694.7-145694.32"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__oe__oe$next[0:0]$6855
+ attribute \src "libresoc.v:145358.7-145358.32"
wire $1\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__oe__ok$next[0:0]$6908
- attribute \src "libresoc.v:145703.7-145703.32"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__oe__ok$next[0:0]$6856
+ attribute \src "libresoc.v:145367.7-145367.32"
wire $1\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__output_carry$next[0:0]$6909
- attribute \src "libresoc.v:145712.7-145712.38"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__output_carry$next[0:0]$6857
+ attribute \src "libresoc.v:145376.7-145376.38"
wire $1\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__rc__ok$next[0:0]$6910
- attribute \src "libresoc.v:145721.7-145721.32"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__rc__ok$next[0:0]$6858
+ attribute \src "libresoc.v:145385.7-145385.32"
wire $1\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__rc__rc$next[0:0]$6911
- attribute \src "libresoc.v:145730.7-145730.32"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__rc__rc$next[0:0]$6859
+ attribute \src "libresoc.v:145394.7-145394.32"
wire $1\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__write_cr0$next[0:0]$6912
- attribute \src "libresoc.v:145739.7-145739.35"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__write_cr0$next[0:0]$6860
+ attribute \src "libresoc.v:145403.7-145403.35"
wire $1\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $1\logical_op__zero_a$next[0:0]$6913
- attribute \src "libresoc.v:145748.7-145748.32"
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $1\logical_op__zero_a$next[0:0]$6861
+ attribute \src "libresoc.v:145412.7-145412.32"
wire $1\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:146265.3-146277.6"
- wire width 2 $1\muxid$next[1:0]$6876
- attribute \src "libresoc.v:146033.13-146033.25"
+ attribute \src "libresoc.v:145929.3-145941.6"
+ wire width 2 $1\muxid$next[1:0]$6824
+ attribute \src "libresoc.v:145697.13-145697.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:146320.3-146338.6"
- wire width 64 $1\o$next[63:0]$6923
- attribute \src "libresoc.v:146048.14-146048.38"
+ attribute \src "libresoc.v:145984.3-146002.6"
+ wire width 64 $1\o$next[63:0]$6871
+ attribute \src "libresoc.v:145712.14-145712.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:146320.3-146338.6"
- wire $1\o_ok$next[0:0]$6924
- attribute \src "libresoc.v:146055.7-146055.18"
+ attribute \src "libresoc.v:145984.3-146002.6"
+ wire $1\o_ok$next[0:0]$6872
+ attribute \src "libresoc.v:145719.7-145719.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:146247.3-146264.6"
- wire $1\r_busy$next[0:0]$6872
- attribute \src "libresoc.v:146069.7-146069.20"
+ attribute \src "libresoc.v:145911.3-145928.6"
+ wire $1\r_busy$next[0:0]$6820
+ attribute \src "libresoc.v:145733.7-145733.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:146358.3-146376.6"
- wire $1\xer_so$next[0:0]$6935
- attribute \src "libresoc.v:146078.7-146078.20"
+ attribute \src "libresoc.v:146022.3-146040.6"
+ wire $1\xer_so$next[0:0]$6883
+ attribute \src "libresoc.v:145742.7-145742.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:146358.3-146376.6"
- wire $1\xer_so_ok$next[0:0]$6936
- attribute \src "libresoc.v:146087.7-146087.23"
+ attribute \src "libresoc.v:146022.3-146040.6"
+ wire $1\xer_so_ok$next[0:0]$6884
+ attribute \src "libresoc.v:145751.7-145751.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:146339.3-146357.6"
- wire $2\cr_a_ok$next[0:0]$6931
- attribute \src "libresoc.v:146278.3-146319.6"
- wire width 64 $2\logical_op__imm_data__data$next[63:0]$6914
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $2\logical_op__imm_data__ok$next[0:0]$6915
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $2\logical_op__oe__oe$next[0:0]$6916
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $2\logical_op__oe__ok$next[0:0]$6917
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $2\logical_op__rc__ok$next[0:0]$6918
- attribute \src "libresoc.v:146278.3-146319.6"
- wire $2\logical_op__rc__rc$next[0:0]$6919
- attribute \src "libresoc.v:146320.3-146338.6"
- wire $2\o_ok$next[0:0]$6925
- attribute \src "libresoc.v:146247.3-146264.6"
- wire $2\r_busy$next[0:0]$6873
- attribute \src "libresoc.v:146358.3-146376.6"
- wire $2\xer_so_ok$next[0:0]$6937
- attribute \src "libresoc.v:146094.18-146094.118"
- wire $and$libresoc.v:146094$6843_Y
+ attribute \src "libresoc.v:146003.3-146021.6"
+ wire $2\cr_a_ok$next[0:0]$6879
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire width 64 $2\logical_op__imm_data__data$next[63:0]$6862
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $2\logical_op__imm_data__ok$next[0:0]$6863
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $2\logical_op__oe__oe$next[0:0]$6864
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $2\logical_op__oe__ok$next[0:0]$6865
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $2\logical_op__rc__ok$next[0:0]$6866
+ attribute \src "libresoc.v:145942.3-145983.6"
+ wire $2\logical_op__rc__rc$next[0:0]$6867
+ attribute \src "libresoc.v:145984.3-146002.6"
+ wire $2\o_ok$next[0:0]$6873
+ attribute \src "libresoc.v:145911.3-145928.6"
+ wire $2\r_busy$next[0:0]$6821
+ attribute \src "libresoc.v:146022.3-146040.6"
+ wire $2\xer_so_ok$next[0:0]$6885
+ attribute \src "libresoc.v:145758.18-145758.118"
+ wire $and$libresoc.v:145758$6791_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
wire \cr_a_ok$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:145010.7-145010.15"
+ attribute \src "libresoc.v:144674.7-144674.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:146094$6843
+ cell $and $and$libresoc.v:145758$6791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$63
connect \B \p_ready_o
- connect \Y $and$libresoc.v:146094$6843_Y
+ connect \Y $and$libresoc.v:145758$6791_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:146147.14-146192.4"
+ attribute \src "libresoc.v:145811.14-145856.4"
cell \input$50 \input
connect \logical_op__data_len \input_logical_op__data_len
connect \logical_op__data_len$18 \input_logical_op__data_len$38
connect \xer_so$22 \input_xer_so$42
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:146193.13-146238.4"
+ attribute \src "libresoc.v:145857.13-145902.4"
cell \main$51 \main
connect \logical_op__data_len \main_logical_op__data_len
connect \logical_op__data_len$18 \main_logical_op__data_len$60
connect \xer_so$20 \main_xer_so$62
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:146239.10-146242.4"
+ attribute \src "libresoc.v:145903.10-145906.4"
cell \n$49 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:146243.10-146246.4"
+ attribute \src "libresoc.v:145907.10-145910.4"
cell \p$48 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:145010.7-145010.20"
- process $proc$libresoc.v:145010$6938
+ attribute \src "libresoc.v:144674.7-144674.20"
+ process $proc$libresoc.v:144674$6886
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:145019.13-145019.24"
- process $proc$libresoc.v:145019$6939
+ attribute \src "libresoc.v:144683.13-144683.24"
+ process $proc$libresoc.v:144683$6887
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:145028.7-145028.21"
- process $proc$libresoc.v:145028$6940
+ attribute \src "libresoc.v:144692.7-144692.21"
+ process $proc$libresoc.v:144692$6888
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:145313.13-145313.40"
- process $proc$libresoc.v:145313$6941
+ attribute \src "libresoc.v:144977.13-144977.40"
+ process $proc$libresoc.v:144977$6889
assign { } { }
assign $1\logical_op__data_len[3:0] 4'0000
sync always
sync init
update \logical_op__data_len $1\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:145337.14-145337.44"
- process $proc$libresoc.v:145337$6942
+ attribute \src "libresoc.v:145001.14-145001.44"
+ process $proc$libresoc.v:145001$6890
assign { } { }
assign $1\logical_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \logical_op__fn_unit $1\logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:145376.14-145376.63"
- process $proc$libresoc.v:145376$6943
+ attribute \src "libresoc.v:145040.14-145040.63"
+ process $proc$libresoc.v:145040$6891
assign { } { }
assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:145385.7-145385.38"
- process $proc$libresoc.v:145385$6944
+ attribute \src "libresoc.v:145049.7-145049.38"
+ process $proc$libresoc.v:145049$6892
assign { } { }
assign $1\logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:145398.13-145398.43"
- process $proc$libresoc.v:145398$6945
+ attribute \src "libresoc.v:145062.13-145062.43"
+ process $proc$libresoc.v:145062$6893
assign { } { }
assign $1\logical_op__input_carry[1:0] 2'00
sync always
sync init
update \logical_op__input_carry $1\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:145415.14-145415.38"
- process $proc$libresoc.v:145415$6946
+ attribute \src "libresoc.v:145079.14-145079.38"
+ process $proc$libresoc.v:145079$6894
assign { } { }
assign $1\logical_op__insn[31:0] 0
sync always
sync init
update \logical_op__insn $1\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:145499.13-145499.42"
- process $proc$libresoc.v:145499$6947
+ attribute \src "libresoc.v:145163.13-145163.42"
+ process $proc$libresoc.v:145163$6895
assign { } { }
assign $1\logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \logical_op__insn_type $1\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:145658.7-145658.35"
- process $proc$libresoc.v:145658$6948
+ attribute \src "libresoc.v:145322.7-145322.35"
+ process $proc$libresoc.v:145322$6896
assign { } { }
assign $1\logical_op__invert_in[0:0] 1'0
sync always
sync init
update \logical_op__invert_in $1\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:145667.7-145667.36"
- process $proc$libresoc.v:145667$6949
+ attribute \src "libresoc.v:145331.7-145331.36"
+ process $proc$libresoc.v:145331$6897
assign { } { }
assign $1\logical_op__invert_out[0:0] 1'0
sync always
sync init
update \logical_op__invert_out $1\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:145676.7-145676.34"
- process $proc$libresoc.v:145676$6950
+ attribute \src "libresoc.v:145340.7-145340.34"
+ process $proc$libresoc.v:145340$6898
assign { } { }
assign $1\logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \logical_op__is_32bit $1\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:145685.7-145685.35"
- process $proc$libresoc.v:145685$6951
+ attribute \src "libresoc.v:145349.7-145349.35"
+ process $proc$libresoc.v:145349$6899
assign { } { }
assign $1\logical_op__is_signed[0:0] 1'0
sync always
sync init
update \logical_op__is_signed $1\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:145694.7-145694.32"
- process $proc$libresoc.v:145694$6952
+ attribute \src "libresoc.v:145358.7-145358.32"
+ process $proc$libresoc.v:145358$6900
assign { } { }
assign $1\logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \logical_op__oe__oe $1\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:145703.7-145703.32"
- process $proc$libresoc.v:145703$6953
+ attribute \src "libresoc.v:145367.7-145367.32"
+ process $proc$libresoc.v:145367$6901
assign { } { }
assign $1\logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \logical_op__oe__ok $1\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:145712.7-145712.38"
- process $proc$libresoc.v:145712$6954
+ attribute \src "libresoc.v:145376.7-145376.38"
+ process $proc$libresoc.v:145376$6902
assign { } { }
assign $1\logical_op__output_carry[0:0] 1'0
sync always
sync init
update \logical_op__output_carry $1\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:145721.7-145721.32"
- process $proc$libresoc.v:145721$6955
+ attribute \src "libresoc.v:145385.7-145385.32"
+ process $proc$libresoc.v:145385$6903
assign { } { }
assign $1\logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \logical_op__rc__ok $1\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:145730.7-145730.32"
- process $proc$libresoc.v:145730$6956
+ attribute \src "libresoc.v:145394.7-145394.32"
+ process $proc$libresoc.v:145394$6904
assign { } { }
assign $1\logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \logical_op__rc__rc $1\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:145739.7-145739.35"
- process $proc$libresoc.v:145739$6957
+ attribute \src "libresoc.v:145403.7-145403.35"
+ process $proc$libresoc.v:145403$6905
assign { } { }
assign $1\logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:145748.7-145748.32"
- process $proc$libresoc.v:145748$6958
+ attribute \src "libresoc.v:145412.7-145412.32"
+ process $proc$libresoc.v:145412$6906
assign { } { }
assign $1\logical_op__zero_a[0:0] 1'0
sync always
sync init
update \logical_op__zero_a $1\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:146033.13-146033.25"
- process $proc$libresoc.v:146033$6959
+ attribute \src "libresoc.v:145697.13-145697.25"
+ process $proc$libresoc.v:145697$6907
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:146048.14-146048.38"
- process $proc$libresoc.v:146048$6960
+ attribute \src "libresoc.v:145712.14-145712.38"
+ process $proc$libresoc.v:145712$6908
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:146055.7-146055.18"
- process $proc$libresoc.v:146055$6961
+ attribute \src "libresoc.v:145719.7-145719.18"
+ process $proc$libresoc.v:145719$6909
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:146069.7-146069.20"
- process $proc$libresoc.v:146069$6962
+ attribute \src "libresoc.v:145733.7-145733.20"
+ process $proc$libresoc.v:145733$6910
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:146078.7-146078.20"
- process $proc$libresoc.v:146078$6963
+ attribute \src "libresoc.v:145742.7-145742.20"
+ process $proc$libresoc.v:145742$6911
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:146087.7-146087.23"
- process $proc$libresoc.v:146087$6964
+ attribute \src "libresoc.v:145751.7-145751.23"
+ process $proc$libresoc.v:145751$6912
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:146095.3-146096.29"
- process $proc$libresoc.v:146095$6844
+ attribute \src "libresoc.v:145759.3-145760.29"
+ process $proc$libresoc.v:145759$6792
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:146097.3-146098.35"
- process $proc$libresoc.v:146097$6845
+ attribute \src "libresoc.v:145761.3-145762.35"
+ process $proc$libresoc.v:145761$6793
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:146099.3-146100.25"
- process $proc$libresoc.v:146099$6846
+ attribute \src "libresoc.v:145763.3-145764.25"
+ process $proc$libresoc.v:145763$6794
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:146101.3-146102.31"
- process $proc$libresoc.v:146101$6847
+ attribute \src "libresoc.v:145765.3-145766.31"
+ process $proc$libresoc.v:145765$6795
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:146103.3-146104.19"
- process $proc$libresoc.v:146103$6848
+ attribute \src "libresoc.v:145767.3-145768.19"
+ process $proc$libresoc.v:145767$6796
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:146105.3-146106.25"
- process $proc$libresoc.v:146105$6849
+ attribute \src "libresoc.v:145769.3-145770.25"
+ process $proc$libresoc.v:145769$6797
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:146107.3-146108.59"
- process $proc$libresoc.v:146107$6850
+ attribute \src "libresoc.v:145771.3-145772.59"
+ process $proc$libresoc.v:145771$6798
assign { } { }
assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next
sync posedge \coresync_clk
update \logical_op__insn_type $0\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:146109.3-146110.55"
- process $proc$libresoc.v:146109$6851
+ attribute \src "libresoc.v:145773.3-145774.55"
+ process $proc$libresoc.v:145773$6799
assign { } { }
assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next
sync posedge \coresync_clk
update \logical_op__fn_unit $0\logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:146111.3-146112.69"
- process $proc$libresoc.v:146111$6852
+ attribute \src "libresoc.v:145775.3-145776.69"
+ process $proc$libresoc.v:145775$6800
assign { } { }
assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next
sync posedge \coresync_clk
update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:146113.3-146114.65"
- process $proc$libresoc.v:146113$6853
+ attribute \src "libresoc.v:145777.3-145778.65"
+ process $proc$libresoc.v:145777$6801
assign { } { }
assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:146115.3-146116.53"
- process $proc$libresoc.v:146115$6854
+ attribute \src "libresoc.v:145779.3-145780.53"
+ process $proc$libresoc.v:145779$6802
assign { } { }
assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next
sync posedge \coresync_clk
update \logical_op__rc__rc $0\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:146117.3-146118.53"
- process $proc$libresoc.v:146117$6855
+ attribute \src "libresoc.v:145781.3-145782.53"
+ process $proc$libresoc.v:145781$6803
assign { } { }
assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next
sync posedge \coresync_clk
update \logical_op__rc__ok $0\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:146119.3-146120.53"
- process $proc$libresoc.v:146119$6856
+ attribute \src "libresoc.v:145783.3-145784.53"
+ process $proc$libresoc.v:145783$6804
assign { } { }
assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next
sync posedge \coresync_clk
update \logical_op__oe__oe $0\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:146121.3-146122.53"
- process $proc$libresoc.v:146121$6857
+ attribute \src "libresoc.v:145785.3-145786.53"
+ process $proc$libresoc.v:145785$6805
assign { } { }
assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next
sync posedge \coresync_clk
update \logical_op__oe__ok $0\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:146123.3-146124.59"
- process $proc$libresoc.v:146123$6858
+ attribute \src "libresoc.v:145787.3-145788.59"
+ process $proc$libresoc.v:145787$6806
assign { } { }
assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next
sync posedge \coresync_clk
update \logical_op__invert_in $0\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:146125.3-146126.53"
- process $proc$libresoc.v:146125$6859
+ attribute \src "libresoc.v:145789.3-145790.53"
+ process $proc$libresoc.v:145789$6807
assign { } { }
assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next
sync posedge \coresync_clk
update \logical_op__zero_a $0\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:146127.3-146128.63"
- process $proc$libresoc.v:146127$6860
+ attribute \src "libresoc.v:145791.3-145792.63"
+ process $proc$libresoc.v:145791$6808
assign { } { }
assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next
sync posedge \coresync_clk
update \logical_op__input_carry $0\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:146129.3-146130.61"
- process $proc$libresoc.v:146129$6861
+ attribute \src "libresoc.v:145793.3-145794.61"
+ process $proc$libresoc.v:145793$6809
assign { } { }
assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next
sync posedge \coresync_clk
update \logical_op__invert_out $0\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:146131.3-146132.59"
- process $proc$libresoc.v:146131$6862
+ attribute \src "libresoc.v:145795.3-145796.59"
+ process $proc$libresoc.v:145795$6810
assign { } { }
assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next
sync posedge \coresync_clk
update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:146133.3-146134.65"
- process $proc$libresoc.v:146133$6863
+ attribute \src "libresoc.v:145797.3-145798.65"
+ process $proc$libresoc.v:145797$6811
assign { } { }
assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next
sync posedge \coresync_clk
update \logical_op__output_carry $0\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:146135.3-146136.57"
- process $proc$libresoc.v:146135$6864
+ attribute \src "libresoc.v:145799.3-145800.57"
+ process $proc$libresoc.v:145799$6812
assign { } { }
assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next
sync posedge \coresync_clk
update \logical_op__is_32bit $0\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:146137.3-146138.59"
- process $proc$libresoc.v:146137$6865
+ attribute \src "libresoc.v:145801.3-145802.59"
+ process $proc$libresoc.v:145801$6813
assign { } { }
assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next
sync posedge \coresync_clk
update \logical_op__is_signed $0\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:146139.3-146140.57"
- process $proc$libresoc.v:146139$6866
+ attribute \src "libresoc.v:145803.3-145804.57"
+ process $proc$libresoc.v:145803$6814
assign { } { }
assign $0\logical_op__data_len[3:0] \logical_op__data_len$next
sync posedge \coresync_clk
update \logical_op__data_len $0\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:146141.3-146142.49"
- process $proc$libresoc.v:146141$6867
+ attribute \src "libresoc.v:145805.3-145806.49"
+ process $proc$libresoc.v:145805$6815
assign { } { }
assign $0\logical_op__insn[31:0] \logical_op__insn$next
sync posedge \coresync_clk
update \logical_op__insn $0\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:146143.3-146144.27"
- process $proc$libresoc.v:146143$6868
+ attribute \src "libresoc.v:145807.3-145808.27"
+ process $proc$libresoc.v:145807$6816
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:146145.3-146146.29"
- process $proc$libresoc.v:146145$6869
+ attribute \src "libresoc.v:145809.3-145810.29"
+ process $proc$libresoc.v:145809$6817
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:146247.3-146264.6"
- process $proc$libresoc.v:146247$6870
+ attribute \src "libresoc.v:145911.3-145928.6"
+ process $proc$libresoc.v:145911$6818
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$6871 $2\r_busy$next[0:0]$6873
- attribute \src "libresoc.v:146248.5-146248.29"
+ assign $0\r_busy$next[0:0]$6819 $2\r_busy$next[0:0]$6821
+ attribute \src "libresoc.v:145912.5-145912.29"
switch \initial
- attribute \src "libresoc.v:146248.9-146248.17"
+ attribute \src "libresoc.v:145912.9-145912.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$6872 1'1
+ assign $1\r_busy$next[0:0]$6820 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$6872 1'0
+ assign $1\r_busy$next[0:0]$6820 1'0
case
- assign $1\r_busy$next[0:0]$6872 \r_busy
+ assign $1\r_busy$next[0:0]$6820 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$6873 1'0
+ assign $2\r_busy$next[0:0]$6821 1'0
case
- assign $2\r_busy$next[0:0]$6873 $1\r_busy$next[0:0]$6872
+ assign $2\r_busy$next[0:0]$6821 $1\r_busy$next[0:0]$6820
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$6871
+ update \r_busy$next $0\r_busy$next[0:0]$6819
end
- attribute \src "libresoc.v:146265.3-146277.6"
- process $proc$libresoc.v:146265$6874
+ attribute \src "libresoc.v:145929.3-145941.6"
+ process $proc$libresoc.v:145929$6822
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$6875 $1\muxid$next[1:0]$6876
- attribute \src "libresoc.v:146266.5-146266.29"
+ assign $0\muxid$next[1:0]$6823 $1\muxid$next[1:0]$6824
+ attribute \src "libresoc.v:145930.5-145930.29"
switch \initial
- attribute \src "libresoc.v:146266.9-146266.17"
+ attribute \src "libresoc.v:145930.9-145930.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$6876 \muxid$66
+ assign $1\muxid$next[1:0]$6824 \muxid$66
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$6876 \muxid$66
+ assign $1\muxid$next[1:0]$6824 \muxid$66
case
- assign $1\muxid$next[1:0]$6876 \muxid
+ assign $1\muxid$next[1:0]$6824 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$6875
+ update \muxid$next $0\muxid$next[1:0]$6823
end
- attribute \src "libresoc.v:146278.3-146319.6"
- process $proc$libresoc.v:146278$6877
+ attribute \src "libresoc.v:145942.3-145983.6"
+ process $proc$libresoc.v:145942$6825
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$next[3:0]$6878 $1\logical_op__data_len$next[3:0]$6896
- assign $0\logical_op__fn_unit$next[13:0]$6879 $1\logical_op__fn_unit$next[13:0]$6897
+ assign $0\logical_op__data_len$next[3:0]$6826 $1\logical_op__data_len$next[3:0]$6844
+ assign $0\logical_op__fn_unit$next[13:0]$6827 $1\logical_op__fn_unit$next[13:0]$6845
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$next[1:0]$6882 $1\logical_op__input_carry$next[1:0]$6900
- assign $0\logical_op__insn$next[31:0]$6883 $1\logical_op__insn$next[31:0]$6901
- assign $0\logical_op__insn_type$next[6:0]$6884 $1\logical_op__insn_type$next[6:0]$6902
- assign $0\logical_op__invert_in$next[0:0]$6885 $1\logical_op__invert_in$next[0:0]$6903
- assign $0\logical_op__invert_out$next[0:0]$6886 $1\logical_op__invert_out$next[0:0]$6904
- assign $0\logical_op__is_32bit$next[0:0]$6887 $1\logical_op__is_32bit$next[0:0]$6905
- assign $0\logical_op__is_signed$next[0:0]$6888 $1\logical_op__is_signed$next[0:0]$6906
+ assign $0\logical_op__input_carry$next[1:0]$6830 $1\logical_op__input_carry$next[1:0]$6848
+ assign $0\logical_op__insn$next[31:0]$6831 $1\logical_op__insn$next[31:0]$6849
+ assign $0\logical_op__insn_type$next[6:0]$6832 $1\logical_op__insn_type$next[6:0]$6850
+ assign $0\logical_op__invert_in$next[0:0]$6833 $1\logical_op__invert_in$next[0:0]$6851
+ assign $0\logical_op__invert_out$next[0:0]$6834 $1\logical_op__invert_out$next[0:0]$6852
+ assign $0\logical_op__is_32bit$next[0:0]$6835 $1\logical_op__is_32bit$next[0:0]$6853
+ assign $0\logical_op__is_signed$next[0:0]$6836 $1\logical_op__is_signed$next[0:0]$6854
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$next[0:0]$6891 $1\logical_op__output_carry$next[0:0]$6909
+ assign $0\logical_op__output_carry$next[0:0]$6839 $1\logical_op__output_carry$next[0:0]$6857
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$next[0:0]$6894 $1\logical_op__write_cr0$next[0:0]$6912
- assign $0\logical_op__zero_a$next[0:0]$6895 $1\logical_op__zero_a$next[0:0]$6913
- assign $0\logical_op__imm_data__data$next[63:0]$6880 $2\logical_op__imm_data__data$next[63:0]$6914
- assign $0\logical_op__imm_data__ok$next[0:0]$6881 $2\logical_op__imm_data__ok$next[0:0]$6915
- assign $0\logical_op__oe__oe$next[0:0]$6889 $2\logical_op__oe__oe$next[0:0]$6916
- assign $0\logical_op__oe__ok$next[0:0]$6890 $2\logical_op__oe__ok$next[0:0]$6917
- assign $0\logical_op__rc__ok$next[0:0]$6892 $2\logical_op__rc__ok$next[0:0]$6918
- assign $0\logical_op__rc__rc$next[0:0]$6893 $2\logical_op__rc__rc$next[0:0]$6919
- attribute \src "libresoc.v:146279.5-146279.29"
+ assign $0\logical_op__write_cr0$next[0:0]$6842 $1\logical_op__write_cr0$next[0:0]$6860
+ assign $0\logical_op__zero_a$next[0:0]$6843 $1\logical_op__zero_a$next[0:0]$6861
+ assign $0\logical_op__imm_data__data$next[63:0]$6828 $2\logical_op__imm_data__data$next[63:0]$6862
+ assign $0\logical_op__imm_data__ok$next[0:0]$6829 $2\logical_op__imm_data__ok$next[0:0]$6863
+ assign $0\logical_op__oe__oe$next[0:0]$6837 $2\logical_op__oe__oe$next[0:0]$6864
+ assign $0\logical_op__oe__ok$next[0:0]$6838 $2\logical_op__oe__ok$next[0:0]$6865
+ assign $0\logical_op__rc__ok$next[0:0]$6840 $2\logical_op__rc__ok$next[0:0]$6866
+ assign $0\logical_op__rc__rc$next[0:0]$6841 $2\logical_op__rc__rc$next[0:0]$6867
+ attribute \src "libresoc.v:145943.5-145943.29"
switch \initial
- attribute \src "libresoc.v:146279.9-146279.17"
+ attribute \src "libresoc.v:145943.9-145943.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$6901 $1\logical_op__data_len$next[3:0]$6896 $1\logical_op__is_signed$next[0:0]$6906 $1\logical_op__is_32bit$next[0:0]$6905 $1\logical_op__output_carry$next[0:0]$6909 $1\logical_op__write_cr0$next[0:0]$6912 $1\logical_op__invert_out$next[0:0]$6904 $1\logical_op__input_carry$next[1:0]$6900 $1\logical_op__zero_a$next[0:0]$6913 $1\logical_op__invert_in$next[0:0]$6903 $1\logical_op__oe__ok$next[0:0]$6908 $1\logical_op__oe__oe$next[0:0]$6907 $1\logical_op__rc__ok$next[0:0]$6910 $1\logical_op__rc__rc$next[0:0]$6911 $1\logical_op__imm_data__ok$next[0:0]$6899 $1\logical_op__imm_data__data$next[63:0]$6898 $1\logical_op__fn_unit$next[13:0]$6897 $1\logical_op__insn_type$next[6:0]$6902 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
+ assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$6901 $1\logical_op__data_len$next[3:0]$6896 $1\logical_op__is_signed$next[0:0]$6906 $1\logical_op__is_32bit$next[0:0]$6905 $1\logical_op__output_carry$next[0:0]$6909 $1\logical_op__write_cr0$next[0:0]$6912 $1\logical_op__invert_out$next[0:0]$6904 $1\logical_op__input_carry$next[1:0]$6900 $1\logical_op__zero_a$next[0:0]$6913 $1\logical_op__invert_in$next[0:0]$6903 $1\logical_op__oe__ok$next[0:0]$6908 $1\logical_op__oe__oe$next[0:0]$6907 $1\logical_op__rc__ok$next[0:0]$6910 $1\logical_op__rc__rc$next[0:0]$6911 $1\logical_op__imm_data__ok$next[0:0]$6899 $1\logical_op__imm_data__data$next[63:0]$6898 $1\logical_op__fn_unit$next[13:0]$6897 $1\logical_op__insn_type$next[6:0]$6902 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
+ assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
case
- assign $1\logical_op__data_len$next[3:0]$6896 \logical_op__data_len
- assign $1\logical_op__fn_unit$next[13:0]$6897 \logical_op__fn_unit
- assign $1\logical_op__imm_data__data$next[63:0]$6898 \logical_op__imm_data__data
- assign $1\logical_op__imm_data__ok$next[0:0]$6899 \logical_op__imm_data__ok
- assign $1\logical_op__input_carry$next[1:0]$6900 \logical_op__input_carry
- assign $1\logical_op__insn$next[31:0]$6901 \logical_op__insn
- assign $1\logical_op__insn_type$next[6:0]$6902 \logical_op__insn_type
- assign $1\logical_op__invert_in$next[0:0]$6903 \logical_op__invert_in
- assign $1\logical_op__invert_out$next[0:0]$6904 \logical_op__invert_out
- assign $1\logical_op__is_32bit$next[0:0]$6905 \logical_op__is_32bit
- assign $1\logical_op__is_signed$next[0:0]$6906 \logical_op__is_signed
- assign $1\logical_op__oe__oe$next[0:0]$6907 \logical_op__oe__oe
- assign $1\logical_op__oe__ok$next[0:0]$6908 \logical_op__oe__ok
- assign $1\logical_op__output_carry$next[0:0]$6909 \logical_op__output_carry
- assign $1\logical_op__rc__ok$next[0:0]$6910 \logical_op__rc__ok
- assign $1\logical_op__rc__rc$next[0:0]$6911 \logical_op__rc__rc
- assign $1\logical_op__write_cr0$next[0:0]$6912 \logical_op__write_cr0
- assign $1\logical_op__zero_a$next[0:0]$6913 \logical_op__zero_a
+ assign $1\logical_op__data_len$next[3:0]$6844 \logical_op__data_len
+ assign $1\logical_op__fn_unit$next[13:0]$6845 \logical_op__fn_unit
+ assign $1\logical_op__imm_data__data$next[63:0]$6846 \logical_op__imm_data__data
+ assign $1\logical_op__imm_data__ok$next[0:0]$6847 \logical_op__imm_data__ok
+ assign $1\logical_op__input_carry$next[1:0]$6848 \logical_op__input_carry
+ assign $1\logical_op__insn$next[31:0]$6849 \logical_op__insn
+ assign $1\logical_op__insn_type$next[6:0]$6850 \logical_op__insn_type
+ assign $1\logical_op__invert_in$next[0:0]$6851 \logical_op__invert_in
+ assign $1\logical_op__invert_out$next[0:0]$6852 \logical_op__invert_out
+ assign $1\logical_op__is_32bit$next[0:0]$6853 \logical_op__is_32bit
+ assign $1\logical_op__is_signed$next[0:0]$6854 \logical_op__is_signed
+ assign $1\logical_op__oe__oe$next[0:0]$6855 \logical_op__oe__oe
+ assign $1\logical_op__oe__ok$next[0:0]$6856 \logical_op__oe__ok
+ assign $1\logical_op__output_carry$next[0:0]$6857 \logical_op__output_carry
+ assign $1\logical_op__rc__ok$next[0:0]$6858 \logical_op__rc__ok
+ assign $1\logical_op__rc__rc$next[0:0]$6859 \logical_op__rc__rc
+ assign $1\logical_op__write_cr0$next[0:0]$6860 \logical_op__write_cr0
+ assign $1\logical_op__zero_a$next[0:0]$6861 \logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$next[63:0]$6914 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$next[0:0]$6915 1'0
- assign $2\logical_op__rc__rc$next[0:0]$6919 1'0
- assign $2\logical_op__rc__ok$next[0:0]$6918 1'0
- assign $2\logical_op__oe__oe$next[0:0]$6916 1'0
- assign $2\logical_op__oe__ok$next[0:0]$6917 1'0
+ assign $2\logical_op__imm_data__data$next[63:0]$6862 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$next[0:0]$6863 1'0
+ assign $2\logical_op__rc__rc$next[0:0]$6867 1'0
+ assign $2\logical_op__rc__ok$next[0:0]$6866 1'0
+ assign $2\logical_op__oe__oe$next[0:0]$6864 1'0
+ assign $2\logical_op__oe__ok$next[0:0]$6865 1'0
case
- assign $2\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__imm_data__data$next[63:0]$6898
- assign $2\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__ok$next[0:0]$6899
- assign $2\logical_op__oe__oe$next[0:0]$6916 $1\logical_op__oe__oe$next[0:0]$6907
- assign $2\logical_op__oe__ok$next[0:0]$6917 $1\logical_op__oe__ok$next[0:0]$6908
- assign $2\logical_op__rc__ok$next[0:0]$6918 $1\logical_op__rc__ok$next[0:0]$6910
- assign $2\logical_op__rc__rc$next[0:0]$6919 $1\logical_op__rc__rc$next[0:0]$6911
+ assign $2\logical_op__imm_data__data$next[63:0]$6862 $1\logical_op__imm_data__data$next[63:0]$6846
+ assign $2\logical_op__imm_data__ok$next[0:0]$6863 $1\logical_op__imm_data__ok$next[0:0]$6847
+ assign $2\logical_op__oe__oe$next[0:0]$6864 $1\logical_op__oe__oe$next[0:0]$6855
+ assign $2\logical_op__oe__ok$next[0:0]$6865 $1\logical_op__oe__ok$next[0:0]$6856
+ assign $2\logical_op__rc__ok$next[0:0]$6866 $1\logical_op__rc__ok$next[0:0]$6858
+ assign $2\logical_op__rc__rc$next[0:0]$6867 $1\logical_op__rc__rc$next[0:0]$6859
end
sync always
- update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6878
- update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6879
- update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6880
- update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6881
- update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6882
- update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6883
- update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6884
- update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6885
- update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6886
- update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6887
- update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6888
- update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6889
- update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6890
- update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6891
- update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6892
- update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6893
- update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6894
- update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6895
+ update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6826
+ update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6827
+ update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6828
+ update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6829
+ update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6830
+ update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6831
+ update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6832
+ update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6833
+ update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6834
+ update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6835
+ update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6836
+ update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6837
+ update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6838
+ update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6839
+ update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6840
+ update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6841
+ update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6842
+ update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6843
end
- attribute \src "libresoc.v:146320.3-146338.6"
- process $proc$libresoc.v:146320$6920
+ attribute \src "libresoc.v:145984.3-146002.6"
+ process $proc$libresoc.v:145984$6868
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$6921 $1\o$next[63:0]$6923
+ assign $0\o$next[63:0]$6869 $1\o$next[63:0]$6871
assign { } { }
- assign $0\o_ok$next[0:0]$6922 $2\o_ok$next[0:0]$6925
- attribute \src "libresoc.v:146321.5-146321.29"
+ assign $0\o_ok$next[0:0]$6870 $2\o_ok$next[0:0]$6873
+ attribute \src "libresoc.v:145985.5-145985.29"
switch \initial
- attribute \src "libresoc.v:146321.9-146321.17"
+ attribute \src "libresoc.v:145985.9-145985.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$6924 $1\o$next[63:0]$6923 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$6924 $1\o$next[63:0]$6923 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 }
case
- assign $1\o$next[63:0]$6923 \o
- assign $1\o_ok$next[0:0]$6924 \o_ok
+ assign $1\o$next[63:0]$6871 \o
+ assign $1\o_ok$next[0:0]$6872 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$6925 1'0
+ assign $2\o_ok$next[0:0]$6873 1'0
case
- assign $2\o_ok$next[0:0]$6925 $1\o_ok$next[0:0]$6924
+ assign $2\o_ok$next[0:0]$6873 $1\o_ok$next[0:0]$6872
end
sync always
- update \o$next $0\o$next[63:0]$6921
- update \o_ok$next $0\o_ok$next[0:0]$6922
+ update \o$next $0\o$next[63:0]$6869
+ update \o_ok$next $0\o_ok$next[0:0]$6870
end
- attribute \src "libresoc.v:146339.3-146357.6"
- process $proc$libresoc.v:146339$6926
+ attribute \src "libresoc.v:146003.3-146021.6"
+ process $proc$libresoc.v:146003$6874
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$6927 $1\cr_a$next[3:0]$6929
+ assign $0\cr_a$next[3:0]$6875 $1\cr_a$next[3:0]$6877
assign { } { }
- assign $0\cr_a_ok$next[0:0]$6928 $2\cr_a_ok$next[0:0]$6931
- attribute \src "libresoc.v:146340.5-146340.29"
+ assign $0\cr_a_ok$next[0:0]$6876 $2\cr_a_ok$next[0:0]$6879
+ attribute \src "libresoc.v:146004.5-146004.29"
switch \initial
- attribute \src "libresoc.v:146340.9-146340.17"
+ attribute \src "libresoc.v:146004.9-146004.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$6930 $1\cr_a$next[3:0]$6929 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$6930 $1\cr_a$next[3:0]$6929 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 }
case
- assign $1\cr_a$next[3:0]$6929 \cr_a
- assign $1\cr_a_ok$next[0:0]$6930 \cr_a_ok
+ assign $1\cr_a$next[3:0]$6877 \cr_a
+ assign $1\cr_a_ok$next[0:0]$6878 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$6931 1'0
+ assign $2\cr_a_ok$next[0:0]$6879 1'0
case
- assign $2\cr_a_ok$next[0:0]$6931 $1\cr_a_ok$next[0:0]$6930
+ assign $2\cr_a_ok$next[0:0]$6879 $1\cr_a_ok$next[0:0]$6878
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$6927
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6928
+ update \cr_a$next $0\cr_a$next[3:0]$6875
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6876
end
- attribute \src "libresoc.v:146358.3-146376.6"
- process $proc$libresoc.v:146358$6932
+ attribute \src "libresoc.v:146022.3-146040.6"
+ process $proc$libresoc.v:146022$6880
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$6933 $1\xer_so$next[0:0]$6935
+ assign $0\xer_so$next[0:0]$6881 $1\xer_so$next[0:0]$6883
assign { } { }
- assign $0\xer_so_ok$next[0:0]$6934 $2\xer_so_ok$next[0:0]$6937
- attribute \src "libresoc.v:146359.5-146359.29"
+ assign $0\xer_so_ok$next[0:0]$6882 $2\xer_so_ok$next[0:0]$6885
+ attribute \src "libresoc.v:146023.5-146023.29"
switch \initial
- attribute \src "libresoc.v:146359.9-146359.17"
+ attribute \src "libresoc.v:146023.9-146023.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$6936 $1\xer_so$next[0:0]$6935 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$6936 $1\xer_so$next[0:0]$6935 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 }
case
- assign $1\xer_so$next[0:0]$6935 \xer_so
- assign $1\xer_so_ok$next[0:0]$6936 \xer_so_ok
+ assign $1\xer_so$next[0:0]$6883 \xer_so
+ assign $1\xer_so_ok$next[0:0]$6884 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$6937 1'0
+ assign $2\xer_so_ok$next[0:0]$6885 1'0
case
- assign $2\xer_so_ok$next[0:0]$6937 $1\xer_so_ok$next[0:0]$6936
+ assign $2\xer_so_ok$next[0:0]$6885 $1\xer_so_ok$next[0:0]$6884
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$6933
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6934
+ update \xer_so$next $0\xer_so$next[0:0]$6881
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6882
end
- connect \$64 $and$libresoc.v:146094$6843_Y
+ connect \$64 $and$libresoc.v:145758$6791_Y
connect \cr_a$89 4'0000
connect \cr_a_ok$90 1'0
connect \xer_so_ok$93 1'0
connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:146404.1-147437.10"
+attribute \src "libresoc.v:146068.1-147101.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2"
attribute \generator "nMigen"
module \logical_pipe2
- attribute \src "libresoc.v:147404.3-147422.6"
- wire width 4 $0\cr_a$22$next[3:0]$7070
- attribute \src "libresoc.v:147208.3-147209.33"
- wire width 4 $0\cr_a$22[3:0]$6967
- attribute \src "libresoc.v:146416.13-146416.29"
- wire width 4 $0\cr_a$22[3:0]$7077
- attribute \src "libresoc.v:147404.3-147422.6"
- wire $0\cr_a_ok$23$next[0:0]$7071
- attribute \src "libresoc.v:147210.3-147211.39"
- wire $0\cr_a_ok$23[0:0]$6969
- attribute \src "libresoc.v:146425.7-146425.26"
- wire $0\cr_a_ok$23[0:0]$7079
- attribute \src "libresoc.v:146405.7-146405.20"
+ attribute \src "libresoc.v:147068.3-147086.6"
+ wire width 4 $0\cr_a$22$next[3:0]$7018
+ attribute \src "libresoc.v:146872.3-146873.33"
+ wire width 4 $0\cr_a$22[3:0]$6915
+ attribute \src "libresoc.v:146080.13-146080.29"
+ wire width 4 $0\cr_a$22[3:0]$7025
+ attribute \src "libresoc.v:147068.3-147086.6"
+ wire $0\cr_a_ok$23$next[0:0]$7019
+ attribute \src "libresoc.v:146874.3-146875.39"
+ wire $0\cr_a_ok$23[0:0]$6917
+ attribute \src "libresoc.v:146089.7-146089.26"
+ wire $0\cr_a_ok$23[0:0]$7027
+ attribute \src "libresoc.v:146069.7-146069.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 4 $0\logical_op__data_len$18$next[3:0]$7021
- attribute \src "libresoc.v:147248.3-147249.65"
- wire width 4 $0\logical_op__data_len$18[3:0]$7007
- attribute \src "libresoc.v:146436.13-146436.45"
- wire width 4 $0\logical_op__data_len$18[3:0]$7081
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7022
- attribute \src "libresoc.v:147218.3-147219.61"
- wire width 14 $0\logical_op__fn_unit$3[13:0]$6977
- attribute \src "libresoc.v:146475.14-146475.48"
- wire width 14 $0\logical_op__fn_unit$3[13:0]$7083
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7023
- attribute \src "libresoc.v:147220.3-147221.75"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$6979
- attribute \src "libresoc.v:146499.14-146499.67"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$7085
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__imm_data__ok$5$next[0:0]$7024
- attribute \src "libresoc.v:147222.3-147223.71"
- wire $0\logical_op__imm_data__ok$5[0:0]$6981
- attribute \src "libresoc.v:146508.7-146508.42"
- wire $0\logical_op__imm_data__ok$5[0:0]$7087
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 2 $0\logical_op__input_carry$12$next[1:0]$7025
- attribute \src "libresoc.v:147236.3-147237.71"
- wire width 2 $0\logical_op__input_carry$12[1:0]$6995
- attribute \src "libresoc.v:146525.13-146525.48"
- wire width 2 $0\logical_op__input_carry$12[1:0]$7089
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 32 $0\logical_op__insn$19$next[31:0]$7026
- attribute \src "libresoc.v:147250.3-147251.57"
- wire width 32 $0\logical_op__insn$19[31:0]$7009
- attribute \src "libresoc.v:146538.14-146538.43"
- wire width 32 $0\logical_op__insn$19[31:0]$7091
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 7 $0\logical_op__insn_type$2$next[6:0]$7027
- attribute \src "libresoc.v:147216.3-147217.65"
- wire width 7 $0\logical_op__insn_type$2[6:0]$6975
- attribute \src "libresoc.v:146697.13-146697.46"
- wire width 7 $0\logical_op__insn_type$2[6:0]$7093
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__invert_in$10$next[0:0]$7028
- attribute \src "libresoc.v:147232.3-147233.67"
- wire $0\logical_op__invert_in$10[0:0]$6991
- attribute \src "libresoc.v:146781.7-146781.40"
- wire $0\logical_op__invert_in$10[0:0]$7095
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__invert_out$13$next[0:0]$7029
- attribute \src "libresoc.v:147238.3-147239.69"
- wire $0\logical_op__invert_out$13[0:0]$6997
- attribute \src "libresoc.v:146790.7-146790.41"
- wire $0\logical_op__invert_out$13[0:0]$7097
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__is_32bit$16$next[0:0]$7030
- attribute \src "libresoc.v:147244.3-147245.65"
- wire $0\logical_op__is_32bit$16[0:0]$7003
- attribute \src "libresoc.v:146799.7-146799.39"
- wire $0\logical_op__is_32bit$16[0:0]$7099
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__is_signed$17$next[0:0]$7031
- attribute \src "libresoc.v:147246.3-147247.67"
- wire $0\logical_op__is_signed$17[0:0]$7005
- attribute \src "libresoc.v:146808.7-146808.40"
- wire $0\logical_op__is_signed$17[0:0]$7101
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__oe__oe$8$next[0:0]$7032
- attribute \src "libresoc.v:147228.3-147229.59"
- wire $0\logical_op__oe__oe$8[0:0]$6987
- attribute \src "libresoc.v:146819.7-146819.36"
- wire $0\logical_op__oe__oe$8[0:0]$7103
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__oe__ok$9$next[0:0]$7033
- attribute \src "libresoc.v:147230.3-147231.59"
- wire $0\logical_op__oe__ok$9[0:0]$6989
- attribute \src "libresoc.v:146828.7-146828.36"
- wire $0\logical_op__oe__ok$9[0:0]$7105
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__output_carry$15$next[0:0]$7034
- attribute \src "libresoc.v:147242.3-147243.73"
- wire $0\logical_op__output_carry$15[0:0]$7001
- attribute \src "libresoc.v:146835.7-146835.43"
- wire $0\logical_op__output_carry$15[0:0]$7107
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__rc__ok$7$next[0:0]$7035
- attribute \src "libresoc.v:147226.3-147227.59"
- wire $0\logical_op__rc__ok$7[0:0]$6985
- attribute \src "libresoc.v:146846.7-146846.36"
- wire $0\logical_op__rc__ok$7[0:0]$7109
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__rc__rc$6$next[0:0]$7036
- attribute \src "libresoc.v:147224.3-147225.59"
- wire $0\logical_op__rc__rc$6[0:0]$6983
- attribute \src "libresoc.v:146855.7-146855.36"
- wire $0\logical_op__rc__rc$6[0:0]$7111
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__write_cr0$14$next[0:0]$7037
- attribute \src "libresoc.v:147240.3-147241.67"
- wire $0\logical_op__write_cr0$14[0:0]$6999
- attribute \src "libresoc.v:146862.7-146862.40"
- wire $0\logical_op__write_cr0$14[0:0]$7113
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $0\logical_op__zero_a$11$next[0:0]$7038
- attribute \src "libresoc.v:147234.3-147235.61"
- wire $0\logical_op__zero_a$11[0:0]$6993
- attribute \src "libresoc.v:146871.7-146871.37"
- wire $0\logical_op__zero_a$11[0:0]$7115
- attribute \src "libresoc.v:147330.3-147342.6"
- wire width 2 $0\muxid$1$next[1:0]$7018
- attribute \src "libresoc.v:147252.3-147253.33"
- wire width 2 $0\muxid$1[1:0]$7011
- attribute \src "libresoc.v:146880.13-146880.29"
- wire width 2 $0\muxid$1[1:0]$7117
- attribute \src "libresoc.v:147385.3-147403.6"
- wire width 64 $0\o$20$next[63:0]$7064
- attribute \src "libresoc.v:147212.3-147213.27"
- wire width 64 $0\o$20[63:0]$6971
- attribute \src "libresoc.v:146895.14-146895.43"
- wire width 64 $0\o$20[63:0]$7119
- attribute \src "libresoc.v:147385.3-147403.6"
- wire $0\o_ok$21$next[0:0]$7065
- attribute \src "libresoc.v:147214.3-147215.33"
- wire $0\o_ok$21[0:0]$6973
- attribute \src "libresoc.v:146904.7-146904.23"
- wire $0\o_ok$21[0:0]$7121
- attribute \src "libresoc.v:147312.3-147329.6"
- wire $0\r_busy$next[0:0]$7014
- attribute \src "libresoc.v:147254.3-147255.29"
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 4 $0\logical_op__data_len$18$next[3:0]$6969
+ attribute \src "libresoc.v:146912.3-146913.65"
+ wire width 4 $0\logical_op__data_len$18[3:0]$6955
+ attribute \src "libresoc.v:146100.13-146100.45"
+ wire width 4 $0\logical_op__data_len$18[3:0]$7029
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6970
+ attribute \src "libresoc.v:146882.3-146883.61"
+ wire width 14 $0\logical_op__fn_unit$3[13:0]$6925
+ attribute \src "libresoc.v:146139.14-146139.48"
+ wire width 14 $0\logical_op__fn_unit$3[13:0]$7031
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6971
+ attribute \src "libresoc.v:146884.3-146885.75"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$6927
+ attribute \src "libresoc.v:146163.14-146163.67"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$7033
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__imm_data__ok$5$next[0:0]$6972
+ attribute \src "libresoc.v:146886.3-146887.71"
+ wire $0\logical_op__imm_data__ok$5[0:0]$6929
+ attribute \src "libresoc.v:146172.7-146172.42"
+ wire $0\logical_op__imm_data__ok$5[0:0]$7035
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 2 $0\logical_op__input_carry$12$next[1:0]$6973
+ attribute \src "libresoc.v:146900.3-146901.71"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$6943
+ attribute \src "libresoc.v:146189.13-146189.48"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$7037
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 32 $0\logical_op__insn$19$next[31:0]$6974
+ attribute \src "libresoc.v:146914.3-146915.57"
+ wire width 32 $0\logical_op__insn$19[31:0]$6957
+ attribute \src "libresoc.v:146202.14-146202.43"
+ wire width 32 $0\logical_op__insn$19[31:0]$7039
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 7 $0\logical_op__insn_type$2$next[6:0]$6975
+ attribute \src "libresoc.v:146880.3-146881.65"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$6923
+ attribute \src "libresoc.v:146361.13-146361.46"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$7041
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__invert_in$10$next[0:0]$6976
+ attribute \src "libresoc.v:146896.3-146897.67"
+ wire $0\logical_op__invert_in$10[0:0]$6939
+ attribute \src "libresoc.v:146445.7-146445.40"
+ wire $0\logical_op__invert_in$10[0:0]$7043
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__invert_out$13$next[0:0]$6977
+ attribute \src "libresoc.v:146902.3-146903.69"
+ wire $0\logical_op__invert_out$13[0:0]$6945
+ attribute \src "libresoc.v:146454.7-146454.41"
+ wire $0\logical_op__invert_out$13[0:0]$7045
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__is_32bit$16$next[0:0]$6978
+ attribute \src "libresoc.v:146908.3-146909.65"
+ wire $0\logical_op__is_32bit$16[0:0]$6951
+ attribute \src "libresoc.v:146463.7-146463.39"
+ wire $0\logical_op__is_32bit$16[0:0]$7047
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__is_signed$17$next[0:0]$6979
+ attribute \src "libresoc.v:146910.3-146911.67"
+ wire $0\logical_op__is_signed$17[0:0]$6953
+ attribute \src "libresoc.v:146472.7-146472.40"
+ wire $0\logical_op__is_signed$17[0:0]$7049
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__oe__oe$8$next[0:0]$6980
+ attribute \src "libresoc.v:146892.3-146893.59"
+ wire $0\logical_op__oe__oe$8[0:0]$6935
+ attribute \src "libresoc.v:146483.7-146483.36"
+ wire $0\logical_op__oe__oe$8[0:0]$7051
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__oe__ok$9$next[0:0]$6981
+ attribute \src "libresoc.v:146894.3-146895.59"
+ wire $0\logical_op__oe__ok$9[0:0]$6937
+ attribute \src "libresoc.v:146492.7-146492.36"
+ wire $0\logical_op__oe__ok$9[0:0]$7053
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__output_carry$15$next[0:0]$6982
+ attribute \src "libresoc.v:146906.3-146907.73"
+ wire $0\logical_op__output_carry$15[0:0]$6949
+ attribute \src "libresoc.v:146499.7-146499.43"
+ wire $0\logical_op__output_carry$15[0:0]$7055
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__rc__ok$7$next[0:0]$6983
+ attribute \src "libresoc.v:146890.3-146891.59"
+ wire $0\logical_op__rc__ok$7[0:0]$6933
+ attribute \src "libresoc.v:146510.7-146510.36"
+ wire $0\logical_op__rc__ok$7[0:0]$7057
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__rc__rc$6$next[0:0]$6984
+ attribute \src "libresoc.v:146888.3-146889.59"
+ wire $0\logical_op__rc__rc$6[0:0]$6931
+ attribute \src "libresoc.v:146519.7-146519.36"
+ wire $0\logical_op__rc__rc$6[0:0]$7059
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__write_cr0$14$next[0:0]$6985
+ attribute \src "libresoc.v:146904.3-146905.67"
+ wire $0\logical_op__write_cr0$14[0:0]$6947
+ attribute \src "libresoc.v:146526.7-146526.40"
+ wire $0\logical_op__write_cr0$14[0:0]$7061
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $0\logical_op__zero_a$11$next[0:0]$6986
+ attribute \src "libresoc.v:146898.3-146899.61"
+ wire $0\logical_op__zero_a$11[0:0]$6941
+ attribute \src "libresoc.v:146535.7-146535.37"
+ wire $0\logical_op__zero_a$11[0:0]$7063
+ attribute \src "libresoc.v:146994.3-147006.6"
+ wire width 2 $0\muxid$1$next[1:0]$6966
+ attribute \src "libresoc.v:146916.3-146917.33"
+ wire width 2 $0\muxid$1[1:0]$6959
+ attribute \src "libresoc.v:146544.13-146544.29"
+ wire width 2 $0\muxid$1[1:0]$7065
+ attribute \src "libresoc.v:147049.3-147067.6"
+ wire width 64 $0\o$20$next[63:0]$7012
+ attribute \src "libresoc.v:146876.3-146877.27"
+ wire width 64 $0\o$20[63:0]$6919
+ attribute \src "libresoc.v:146559.14-146559.43"
+ wire width 64 $0\o$20[63:0]$7067
+ attribute \src "libresoc.v:147049.3-147067.6"
+ wire $0\o_ok$21$next[0:0]$7013
+ attribute \src "libresoc.v:146878.3-146879.33"
+ wire $0\o_ok$21[0:0]$6921
+ attribute \src "libresoc.v:146568.7-146568.23"
+ wire $0\o_ok$21[0:0]$7069
+ attribute \src "libresoc.v:146976.3-146993.6"
+ wire $0\r_busy$next[0:0]$6962
+ attribute \src "libresoc.v:146918.3-146919.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:147404.3-147422.6"
- wire width 4 $1\cr_a$22$next[3:0]$7072
- attribute \src "libresoc.v:147404.3-147422.6"
- wire $1\cr_a_ok$23$next[0:0]$7073
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 4 $1\logical_op__data_len$18$next[3:0]$7039
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7040
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7041
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__imm_data__ok$5$next[0:0]$7042
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 2 $1\logical_op__input_carry$12$next[1:0]$7043
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 32 $1\logical_op__insn$19$next[31:0]$7044
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 7 $1\logical_op__insn_type$2$next[6:0]$7045
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__invert_in$10$next[0:0]$7046
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__invert_out$13$next[0:0]$7047
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__is_32bit$16$next[0:0]$7048
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__is_signed$17$next[0:0]$7049
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__oe__oe$8$next[0:0]$7050
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__oe__ok$9$next[0:0]$7051
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__output_carry$15$next[0:0]$7052
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__rc__ok$7$next[0:0]$7053
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__rc__rc$6$next[0:0]$7054
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__write_cr0$14$next[0:0]$7055
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $1\logical_op__zero_a$11$next[0:0]$7056
- attribute \src "libresoc.v:147330.3-147342.6"
- wire width 2 $1\muxid$1$next[1:0]$7019
- attribute \src "libresoc.v:147385.3-147403.6"
- wire width 64 $1\o$20$next[63:0]$7066
- attribute \src "libresoc.v:147385.3-147403.6"
- wire $1\o_ok$21$next[0:0]$7067
- attribute \src "libresoc.v:147312.3-147329.6"
- wire $1\r_busy$next[0:0]$7015
- attribute \src "libresoc.v:147198.7-147198.20"
+ attribute \src "libresoc.v:147068.3-147086.6"
+ wire width 4 $1\cr_a$22$next[3:0]$7020
+ attribute \src "libresoc.v:147068.3-147086.6"
+ wire $1\cr_a_ok$23$next[0:0]$7021
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 4 $1\logical_op__data_len$18$next[3:0]$6987
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 14 $1\logical_op__fn_unit$3$next[13:0]$6988
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6989
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__imm_data__ok$5$next[0:0]$6990
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 2 $1\logical_op__input_carry$12$next[1:0]$6991
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 32 $1\logical_op__insn$19$next[31:0]$6992
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 7 $1\logical_op__insn_type$2$next[6:0]$6993
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__invert_in$10$next[0:0]$6994
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__invert_out$13$next[0:0]$6995
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__is_32bit$16$next[0:0]$6996
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__is_signed$17$next[0:0]$6997
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__oe__oe$8$next[0:0]$6998
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__oe__ok$9$next[0:0]$6999
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__output_carry$15$next[0:0]$7000
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__rc__ok$7$next[0:0]$7001
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__rc__rc$6$next[0:0]$7002
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__write_cr0$14$next[0:0]$7003
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $1\logical_op__zero_a$11$next[0:0]$7004
+ attribute \src "libresoc.v:146994.3-147006.6"
+ wire width 2 $1\muxid$1$next[1:0]$6967
+ attribute \src "libresoc.v:147049.3-147067.6"
+ wire width 64 $1\o$20$next[63:0]$7014
+ attribute \src "libresoc.v:147049.3-147067.6"
+ wire $1\o_ok$21$next[0:0]$7015
+ attribute \src "libresoc.v:146976.3-146993.6"
+ wire $1\r_busy$next[0:0]$6963
+ attribute \src "libresoc.v:146862.7-146862.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:147404.3-147422.6"
- wire $2\cr_a_ok$23$next[0:0]$7074
- attribute \src "libresoc.v:147343.3-147384.6"
- wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7057
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $2\logical_op__imm_data__ok$5$next[0:0]$7058
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $2\logical_op__oe__oe$8$next[0:0]$7059
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $2\logical_op__oe__ok$9$next[0:0]$7060
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $2\logical_op__rc__ok$7$next[0:0]$7061
- attribute \src "libresoc.v:147343.3-147384.6"
- wire $2\logical_op__rc__rc$6$next[0:0]$7062
- attribute \src "libresoc.v:147385.3-147403.6"
- wire $2\o_ok$21$next[0:0]$7068
- attribute \src "libresoc.v:147312.3-147329.6"
- wire $2\r_busy$next[0:0]$7016
- attribute \src "libresoc.v:147207.18-147207.118"
- wire $and$libresoc.v:147207$6965_Y
+ attribute \src "libresoc.v:147068.3-147086.6"
+ wire $2\cr_a_ok$23$next[0:0]$7022
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7005
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $2\logical_op__imm_data__ok$5$next[0:0]$7006
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $2\logical_op__oe__oe$8$next[0:0]$7007
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $2\logical_op__oe__ok$9$next[0:0]$7008
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $2\logical_op__rc__ok$7$next[0:0]$7009
+ attribute \src "libresoc.v:147007.3-147048.6"
+ wire $2\logical_op__rc__rc$6$next[0:0]$7010
+ attribute \src "libresoc.v:147049.3-147067.6"
+ wire $2\o_ok$21$next[0:0]$7016
+ attribute \src "libresoc.v:146976.3-146993.6"
+ wire $2\r_busy$next[0:0]$6964
+ attribute \src "libresoc.v:146871.18-146871.118"
+ wire $and$libresoc.v:146871$6913_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 54 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 25 \cr_a
wire \cr_a_ok$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$73
- attribute \src "libresoc.v:146405.7-146405.15"
+ attribute \src "libresoc.v:146069.7-146069.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$47
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:147207$6965
+ cell $and $and$libresoc.v:146871$6913
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$48
connect \B \p_ready_o
- connect \Y $and$libresoc.v:147207$6965_Y
+ connect \Y $and$libresoc.v:146871$6913_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:147256.10-147259.4"
+ attribute \src "libresoc.v:146920.10-146923.4"
cell \n$53 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:147260.15-147307.4"
+ attribute \src "libresoc.v:146924.15-146971.4"
cell \output$54 \output
connect \cr_a \output_cr_a
connect \cr_a$22 \output_cr_a$45
connect \xer_so \output_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:147308.10-147311.4"
+ attribute \src "libresoc.v:146972.10-146975.4"
cell \p$52 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:146405.7-146405.20"
- process $proc$libresoc.v:146405$7075
+ attribute \src "libresoc.v:146069.7-146069.20"
+ process $proc$libresoc.v:146069$7023
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:146416.13-146416.29"
- process $proc$libresoc.v:146416$7076
+ attribute \src "libresoc.v:146080.13-146080.29"
+ process $proc$libresoc.v:146080$7024
assign { } { }
- assign $0\cr_a$22[3:0]$7077 4'0000
+ assign $0\cr_a$22[3:0]$7025 4'0000
sync always
sync init
- update \cr_a$22 $0\cr_a$22[3:0]$7077
+ update \cr_a$22 $0\cr_a$22[3:0]$7025
end
- attribute \src "libresoc.v:146425.7-146425.26"
- process $proc$libresoc.v:146425$7078
+ attribute \src "libresoc.v:146089.7-146089.26"
+ process $proc$libresoc.v:146089$7026
assign { } { }
- assign $0\cr_a_ok$23[0:0]$7079 1'0
+ assign $0\cr_a_ok$23[0:0]$7027 1'0
sync always
sync init
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7079
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7027
end
- attribute \src "libresoc.v:146436.13-146436.45"
- process $proc$libresoc.v:146436$7080
+ attribute \src "libresoc.v:146100.13-146100.45"
+ process $proc$libresoc.v:146100$7028
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$7081 4'0000
+ assign $0\logical_op__data_len$18[3:0]$7029 4'0000
sync always
sync init
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7081
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7029
end
- attribute \src "libresoc.v:146475.14-146475.48"
- process $proc$libresoc.v:146475$7082
+ attribute \src "libresoc.v:146139.14-146139.48"
+ process $proc$libresoc.v:146139$7030
assign { } { }
- assign $0\logical_op__fn_unit$3[13:0]$7083 14'00000000000000
+ assign $0\logical_op__fn_unit$3[13:0]$7031 14'00000000000000
sync always
sync init
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7083
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7031
end
- attribute \src "libresoc.v:146499.14-146499.67"
- process $proc$libresoc.v:146499$7084
+ attribute \src "libresoc.v:146163.14-146163.67"
+ process $proc$libresoc.v:146163$7032
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$4[63:0]$7033 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7085
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7033
end
- attribute \src "libresoc.v:146508.7-146508.42"
- process $proc$libresoc.v:146508$7086
+ attribute \src "libresoc.v:146172.7-146172.42"
+ process $proc$libresoc.v:146172$7034
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$7087 1'0
+ assign $0\logical_op__imm_data__ok$5[0:0]$7035 1'0
sync always
sync init
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7087
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7035
end
- attribute \src "libresoc.v:146525.13-146525.48"
- process $proc$libresoc.v:146525$7088
+ attribute \src "libresoc.v:146189.13-146189.48"
+ process $proc$libresoc.v:146189$7036
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$7089 2'00
+ assign $0\logical_op__input_carry$12[1:0]$7037 2'00
sync always
sync init
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7089
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7037
end
- attribute \src "libresoc.v:146538.14-146538.43"
- process $proc$libresoc.v:146538$7090
+ attribute \src "libresoc.v:146202.14-146202.43"
+ process $proc$libresoc.v:146202$7038
assign { } { }
- assign $0\logical_op__insn$19[31:0]$7091 0
+ assign $0\logical_op__insn$19[31:0]$7039 0
sync always
sync init
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7091
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7039
end
- attribute \src "libresoc.v:146697.13-146697.46"
- process $proc$libresoc.v:146697$7092
+ attribute \src "libresoc.v:146361.13-146361.46"
+ process $proc$libresoc.v:146361$7040
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$7093 7'0000000
+ assign $0\logical_op__insn_type$2[6:0]$7041 7'0000000
sync always
sync init
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7093
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7041
end
- attribute \src "libresoc.v:146781.7-146781.40"
- process $proc$libresoc.v:146781$7094
+ attribute \src "libresoc.v:146445.7-146445.40"
+ process $proc$libresoc.v:146445$7042
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$7095 1'0
+ assign $0\logical_op__invert_in$10[0:0]$7043 1'0
sync always
sync init
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7095
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7043
end
- attribute \src "libresoc.v:146790.7-146790.41"
- process $proc$libresoc.v:146790$7096
+ attribute \src "libresoc.v:146454.7-146454.41"
+ process $proc$libresoc.v:146454$7044
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$7097 1'0
+ assign $0\logical_op__invert_out$13[0:0]$7045 1'0
sync always
sync init
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7097
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7045
end
- attribute \src "libresoc.v:146799.7-146799.39"
- process $proc$libresoc.v:146799$7098
+ attribute \src "libresoc.v:146463.7-146463.39"
+ process $proc$libresoc.v:146463$7046
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$7099 1'0
+ assign $0\logical_op__is_32bit$16[0:0]$7047 1'0
sync always
sync init
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7099
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7047
end
- attribute \src "libresoc.v:146808.7-146808.40"
- process $proc$libresoc.v:146808$7100
+ attribute \src "libresoc.v:146472.7-146472.40"
+ process $proc$libresoc.v:146472$7048
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$7101 1'0
+ assign $0\logical_op__is_signed$17[0:0]$7049 1'0
sync always
sync init
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7101
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7049
end
- attribute \src "libresoc.v:146819.7-146819.36"
- process $proc$libresoc.v:146819$7102
+ attribute \src "libresoc.v:146483.7-146483.36"
+ process $proc$libresoc.v:146483$7050
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$7103 1'0
+ assign $0\logical_op__oe__oe$8[0:0]$7051 1'0
sync always
sync init
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7103
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7051
end
- attribute \src "libresoc.v:146828.7-146828.36"
- process $proc$libresoc.v:146828$7104
+ attribute \src "libresoc.v:146492.7-146492.36"
+ process $proc$libresoc.v:146492$7052
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$7105 1'0
+ assign $0\logical_op__oe__ok$9[0:0]$7053 1'0
sync always
sync init
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7105
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7053
end
- attribute \src "libresoc.v:146835.7-146835.43"
- process $proc$libresoc.v:146835$7106
+ attribute \src "libresoc.v:146499.7-146499.43"
+ process $proc$libresoc.v:146499$7054
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$7107 1'0
+ assign $0\logical_op__output_carry$15[0:0]$7055 1'0
sync always
sync init
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7107
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7055
end
- attribute \src "libresoc.v:146846.7-146846.36"
- process $proc$libresoc.v:146846$7108
+ attribute \src "libresoc.v:146510.7-146510.36"
+ process $proc$libresoc.v:146510$7056
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$7109 1'0
+ assign $0\logical_op__rc__ok$7[0:0]$7057 1'0
sync always
sync init
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7109
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7057
end
- attribute \src "libresoc.v:146855.7-146855.36"
- process $proc$libresoc.v:146855$7110
+ attribute \src "libresoc.v:146519.7-146519.36"
+ process $proc$libresoc.v:146519$7058
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$7111 1'0
+ assign $0\logical_op__rc__rc$6[0:0]$7059 1'0
sync always
sync init
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7111
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7059
end
- attribute \src "libresoc.v:146862.7-146862.40"
- process $proc$libresoc.v:146862$7112
+ attribute \src "libresoc.v:146526.7-146526.40"
+ process $proc$libresoc.v:146526$7060
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$7113 1'0
+ assign $0\logical_op__write_cr0$14[0:0]$7061 1'0
sync always
sync init
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7113
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7061
end
- attribute \src "libresoc.v:146871.7-146871.37"
- process $proc$libresoc.v:146871$7114
+ attribute \src "libresoc.v:146535.7-146535.37"
+ process $proc$libresoc.v:146535$7062
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$7115 1'0
+ assign $0\logical_op__zero_a$11[0:0]$7063 1'0
sync always
sync init
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7115
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7063
end
- attribute \src "libresoc.v:146880.13-146880.29"
- process $proc$libresoc.v:146880$7116
+ attribute \src "libresoc.v:146544.13-146544.29"
+ process $proc$libresoc.v:146544$7064
assign { } { }
- assign $0\muxid$1[1:0]$7117 2'00
+ assign $0\muxid$1[1:0]$7065 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$7117
+ update \muxid$1 $0\muxid$1[1:0]$7065
end
- attribute \src "libresoc.v:146895.14-146895.43"
- process $proc$libresoc.v:146895$7118
+ attribute \src "libresoc.v:146559.14-146559.43"
+ process $proc$libresoc.v:146559$7066
assign { } { }
- assign $0\o$20[63:0]$7119 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$20[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$20 $0\o$20[63:0]$7119
+ update \o$20 $0\o$20[63:0]$7067
end
- attribute \src "libresoc.v:146904.7-146904.23"
- process $proc$libresoc.v:146904$7120
+ attribute \src "libresoc.v:146568.7-146568.23"
+ process $proc$libresoc.v:146568$7068
assign { } { }
- assign $0\o_ok$21[0:0]$7121 1'0
+ assign $0\o_ok$21[0:0]$7069 1'0
sync always
sync init
- update \o_ok$21 $0\o_ok$21[0:0]$7121
+ update \o_ok$21 $0\o_ok$21[0:0]$7069
end
- attribute \src "libresoc.v:147198.7-147198.20"
- process $proc$libresoc.v:147198$7122
+ attribute \src "libresoc.v:146862.7-146862.20"
+ process $proc$libresoc.v:146862$7070
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:147208.3-147209.33"
- process $proc$libresoc.v:147208$6966
+ attribute \src "libresoc.v:146872.3-146873.33"
+ process $proc$libresoc.v:146872$6914
assign { } { }
- assign $0\cr_a$22[3:0]$6967 \cr_a$22$next
+ assign $0\cr_a$22[3:0]$6915 \cr_a$22$next
sync posedge \coresync_clk
- update \cr_a$22 $0\cr_a$22[3:0]$6967
+ update \cr_a$22 $0\cr_a$22[3:0]$6915
end
- attribute \src "libresoc.v:147210.3-147211.39"
- process $proc$libresoc.v:147210$6968
+ attribute \src "libresoc.v:146874.3-146875.39"
+ process $proc$libresoc.v:146874$6916
assign { } { }
- assign $0\cr_a_ok$23[0:0]$6969 \cr_a_ok$23$next
+ assign $0\cr_a_ok$23[0:0]$6917 \cr_a_ok$23$next
sync posedge \coresync_clk
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6969
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6917
end
- attribute \src "libresoc.v:147212.3-147213.27"
- process $proc$libresoc.v:147212$6970
+ attribute \src "libresoc.v:146876.3-146877.27"
+ process $proc$libresoc.v:146876$6918
assign { } { }
- assign $0\o$20[63:0]$6971 \o$20$next
+ assign $0\o$20[63:0]$6919 \o$20$next
sync posedge \coresync_clk
- update \o$20 $0\o$20[63:0]$6971
+ update \o$20 $0\o$20[63:0]$6919
end
- attribute \src "libresoc.v:147214.3-147215.33"
- process $proc$libresoc.v:147214$6972
+ attribute \src "libresoc.v:146878.3-146879.33"
+ process $proc$libresoc.v:146878$6920
assign { } { }
- assign $0\o_ok$21[0:0]$6973 \o_ok$21$next
+ assign $0\o_ok$21[0:0]$6921 \o_ok$21$next
sync posedge \coresync_clk
- update \o_ok$21 $0\o_ok$21[0:0]$6973
+ update \o_ok$21 $0\o_ok$21[0:0]$6921
end
- attribute \src "libresoc.v:147216.3-147217.65"
- process $proc$libresoc.v:147216$6974
+ attribute \src "libresoc.v:146880.3-146881.65"
+ process $proc$libresoc.v:146880$6922
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$6975 \logical_op__insn_type$2$next
+ assign $0\logical_op__insn_type$2[6:0]$6923 \logical_op__insn_type$2$next
sync posedge \coresync_clk
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6975
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6923
end
- attribute \src "libresoc.v:147218.3-147219.61"
- process $proc$libresoc.v:147218$6976
+ attribute \src "libresoc.v:146882.3-146883.61"
+ process $proc$libresoc.v:146882$6924
assign { } { }
- assign $0\logical_op__fn_unit$3[13:0]$6977 \logical_op__fn_unit$3$next
+ assign $0\logical_op__fn_unit$3[13:0]$6925 \logical_op__fn_unit$3$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6977
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6925
end
- attribute \src "libresoc.v:147220.3-147221.75"
- process $proc$libresoc.v:147220$6978
+ attribute \src "libresoc.v:146884.3-146885.75"
+ process $proc$libresoc.v:146884$6926
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$6979 \logical_op__imm_data__data$4$next
+ assign $0\logical_op__imm_data__data$4[63:0]$6927 \logical_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6979
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6927
end
- attribute \src "libresoc.v:147222.3-147223.71"
- process $proc$libresoc.v:147222$6980
+ attribute \src "libresoc.v:146886.3-146887.71"
+ process $proc$libresoc.v:146886$6928
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$6981 \logical_op__imm_data__ok$5$next
+ assign $0\logical_op__imm_data__ok$5[0:0]$6929 \logical_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6981
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6929
end
- attribute \src "libresoc.v:147224.3-147225.59"
- process $proc$libresoc.v:147224$6982
+ attribute \src "libresoc.v:146888.3-146889.59"
+ process $proc$libresoc.v:146888$6930
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$6983 \logical_op__rc__rc$6$next
+ assign $0\logical_op__rc__rc$6[0:0]$6931 \logical_op__rc__rc$6$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6983
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6931
end
- attribute \src "libresoc.v:147226.3-147227.59"
- process $proc$libresoc.v:147226$6984
+ attribute \src "libresoc.v:146890.3-146891.59"
+ process $proc$libresoc.v:146890$6932
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$6985 \logical_op__rc__ok$7$next
+ assign $0\logical_op__rc__ok$7[0:0]$6933 \logical_op__rc__ok$7$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6985
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6933
end
- attribute \src "libresoc.v:147228.3-147229.59"
- process $proc$libresoc.v:147228$6986
+ attribute \src "libresoc.v:146892.3-146893.59"
+ process $proc$libresoc.v:146892$6934
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$6987 \logical_op__oe__oe$8$next
+ assign $0\logical_op__oe__oe$8[0:0]$6935 \logical_op__oe__oe$8$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6987
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6935
end
- attribute \src "libresoc.v:147230.3-147231.59"
- process $proc$libresoc.v:147230$6988
+ attribute \src "libresoc.v:146894.3-146895.59"
+ process $proc$libresoc.v:146894$6936
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$6989 \logical_op__oe__ok$9$next
+ assign $0\logical_op__oe__ok$9[0:0]$6937 \logical_op__oe__ok$9$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6989
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6937
end
- attribute \src "libresoc.v:147232.3-147233.67"
- process $proc$libresoc.v:147232$6990
+ attribute \src "libresoc.v:146896.3-146897.67"
+ process $proc$libresoc.v:146896$6938
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$6991 \logical_op__invert_in$10$next
+ assign $0\logical_op__invert_in$10[0:0]$6939 \logical_op__invert_in$10$next
sync posedge \coresync_clk
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6991
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6939
end
- attribute \src "libresoc.v:147234.3-147235.61"
- process $proc$libresoc.v:147234$6992
+ attribute \src "libresoc.v:146898.3-146899.61"
+ process $proc$libresoc.v:146898$6940
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$6993 \logical_op__zero_a$11$next
+ assign $0\logical_op__zero_a$11[0:0]$6941 \logical_op__zero_a$11$next
sync posedge \coresync_clk
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6993
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6941
end
- attribute \src "libresoc.v:147236.3-147237.71"
- process $proc$libresoc.v:147236$6994
+ attribute \src "libresoc.v:146900.3-146901.71"
+ process $proc$libresoc.v:146900$6942
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$6995 \logical_op__input_carry$12$next
+ assign $0\logical_op__input_carry$12[1:0]$6943 \logical_op__input_carry$12$next
sync posedge \coresync_clk
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6995
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6943
end
- attribute \src "libresoc.v:147238.3-147239.69"
- process $proc$libresoc.v:147238$6996
+ attribute \src "libresoc.v:146902.3-146903.69"
+ process $proc$libresoc.v:146902$6944
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$6997 \logical_op__invert_out$13$next
+ assign $0\logical_op__invert_out$13[0:0]$6945 \logical_op__invert_out$13$next
sync posedge \coresync_clk
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6997
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6945
end
- attribute \src "libresoc.v:147240.3-147241.67"
- process $proc$libresoc.v:147240$6998
+ attribute \src "libresoc.v:146904.3-146905.67"
+ process $proc$libresoc.v:146904$6946
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$6999 \logical_op__write_cr0$14$next
+ assign $0\logical_op__write_cr0$14[0:0]$6947 \logical_op__write_cr0$14$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6999
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6947
end
- attribute \src "libresoc.v:147242.3-147243.73"
- process $proc$libresoc.v:147242$7000
+ attribute \src "libresoc.v:146906.3-146907.73"
+ process $proc$libresoc.v:146906$6948
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$7001 \logical_op__output_carry$15$next
+ assign $0\logical_op__output_carry$15[0:0]$6949 \logical_op__output_carry$15$next
sync posedge \coresync_clk
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7001
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6949
end
- attribute \src "libresoc.v:147244.3-147245.65"
- process $proc$libresoc.v:147244$7002
+ attribute \src "libresoc.v:146908.3-146909.65"
+ process $proc$libresoc.v:146908$6950
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$7003 \logical_op__is_32bit$16$next
+ assign $0\logical_op__is_32bit$16[0:0]$6951 \logical_op__is_32bit$16$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7003
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6951
end
- attribute \src "libresoc.v:147246.3-147247.67"
- process $proc$libresoc.v:147246$7004
+ attribute \src "libresoc.v:146910.3-146911.67"
+ process $proc$libresoc.v:146910$6952
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$7005 \logical_op__is_signed$17$next
+ assign $0\logical_op__is_signed$17[0:0]$6953 \logical_op__is_signed$17$next
sync posedge \coresync_clk
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7005
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6953
end
- attribute \src "libresoc.v:147248.3-147249.65"
- process $proc$libresoc.v:147248$7006
+ attribute \src "libresoc.v:146912.3-146913.65"
+ process $proc$libresoc.v:146912$6954
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$7007 \logical_op__data_len$18$next
+ assign $0\logical_op__data_len$18[3:0]$6955 \logical_op__data_len$18$next
sync posedge \coresync_clk
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7007
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6955
end
- attribute \src "libresoc.v:147250.3-147251.57"
- process $proc$libresoc.v:147250$7008
+ attribute \src "libresoc.v:146914.3-146915.57"
+ process $proc$libresoc.v:146914$6956
assign { } { }
- assign $0\logical_op__insn$19[31:0]$7009 \logical_op__insn$19$next
+ assign $0\logical_op__insn$19[31:0]$6957 \logical_op__insn$19$next
sync posedge \coresync_clk
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7009
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6957
end
- attribute \src "libresoc.v:147252.3-147253.33"
- process $proc$libresoc.v:147252$7010
+ attribute \src "libresoc.v:146916.3-146917.33"
+ process $proc$libresoc.v:146916$6958
assign { } { }
- assign $0\muxid$1[1:0]$7011 \muxid$1$next
+ assign $0\muxid$1[1:0]$6959 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$7011
+ update \muxid$1 $0\muxid$1[1:0]$6959
end
- attribute \src "libresoc.v:147254.3-147255.29"
- process $proc$libresoc.v:147254$7012
+ attribute \src "libresoc.v:146918.3-146919.29"
+ process $proc$libresoc.v:146918$6960
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:147312.3-147329.6"
- process $proc$libresoc.v:147312$7013
+ attribute \src "libresoc.v:146976.3-146993.6"
+ process $proc$libresoc.v:146976$6961
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$7014 $2\r_busy$next[0:0]$7016
- attribute \src "libresoc.v:147313.5-147313.29"
+ assign $0\r_busy$next[0:0]$6962 $2\r_busy$next[0:0]$6964
+ attribute \src "libresoc.v:146977.5-146977.29"
switch \initial
- attribute \src "libresoc.v:147313.9-147313.17"
+ attribute \src "libresoc.v:146977.9-146977.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$7015 1'1
+ assign $1\r_busy$next[0:0]$6963 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$7015 1'0
+ assign $1\r_busy$next[0:0]$6963 1'0
case
- assign $1\r_busy$next[0:0]$7015 \r_busy
+ assign $1\r_busy$next[0:0]$6963 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$7016 1'0
+ assign $2\r_busy$next[0:0]$6964 1'0
case
- assign $2\r_busy$next[0:0]$7016 $1\r_busy$next[0:0]$7015
+ assign $2\r_busy$next[0:0]$6964 $1\r_busy$next[0:0]$6963
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$7014
+ update \r_busy$next $0\r_busy$next[0:0]$6962
end
- attribute \src "libresoc.v:147330.3-147342.6"
- process $proc$libresoc.v:147330$7017
+ attribute \src "libresoc.v:146994.3-147006.6"
+ process $proc$libresoc.v:146994$6965
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$7018 $1\muxid$1$next[1:0]$7019
- attribute \src "libresoc.v:147331.5-147331.29"
+ assign $0\muxid$1$next[1:0]$6966 $1\muxid$1$next[1:0]$6967
+ attribute \src "libresoc.v:146995.5-146995.29"
switch \initial
- attribute \src "libresoc.v:147331.9-147331.17"
+ attribute \src "libresoc.v:146995.9-146995.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$7019 \muxid$51
+ assign $1\muxid$1$next[1:0]$6967 \muxid$51
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$7019 \muxid$51
+ assign $1\muxid$1$next[1:0]$6967 \muxid$51
case
- assign $1\muxid$1$next[1:0]$7019 \muxid$1
+ assign $1\muxid$1$next[1:0]$6967 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$7018
+ update \muxid$1$next $0\muxid$1$next[1:0]$6966
end
- attribute \src "libresoc.v:147343.3-147384.6"
- process $proc$libresoc.v:147343$7020
+ attribute \src "libresoc.v:147007.3-147048.6"
+ process $proc$libresoc.v:147007$6968
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$18$next[3:0]$7021 $1\logical_op__data_len$18$next[3:0]$7039
- assign $0\logical_op__fn_unit$3$next[13:0]$7022 $1\logical_op__fn_unit$3$next[13:0]$7040
+ assign $0\logical_op__data_len$18$next[3:0]$6969 $1\logical_op__data_len$18$next[3:0]$6987
+ assign $0\logical_op__fn_unit$3$next[13:0]$6970 $1\logical_op__fn_unit$3$next[13:0]$6988
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$12$next[1:0]$7025 $1\logical_op__input_carry$12$next[1:0]$7043
- assign $0\logical_op__insn$19$next[31:0]$7026 $1\logical_op__insn$19$next[31:0]$7044
- assign $0\logical_op__insn_type$2$next[6:0]$7027 $1\logical_op__insn_type$2$next[6:0]$7045
- assign $0\logical_op__invert_in$10$next[0:0]$7028 $1\logical_op__invert_in$10$next[0:0]$7046
- assign $0\logical_op__invert_out$13$next[0:0]$7029 $1\logical_op__invert_out$13$next[0:0]$7047
- assign $0\logical_op__is_32bit$16$next[0:0]$7030 $1\logical_op__is_32bit$16$next[0:0]$7048
- assign $0\logical_op__is_signed$17$next[0:0]$7031 $1\logical_op__is_signed$17$next[0:0]$7049
+ assign $0\logical_op__input_carry$12$next[1:0]$6973 $1\logical_op__input_carry$12$next[1:0]$6991
+ assign $0\logical_op__insn$19$next[31:0]$6974 $1\logical_op__insn$19$next[31:0]$6992
+ assign $0\logical_op__insn_type$2$next[6:0]$6975 $1\logical_op__insn_type$2$next[6:0]$6993
+ assign $0\logical_op__invert_in$10$next[0:0]$6976 $1\logical_op__invert_in$10$next[0:0]$6994
+ assign $0\logical_op__invert_out$13$next[0:0]$6977 $1\logical_op__invert_out$13$next[0:0]$6995
+ assign $0\logical_op__is_32bit$16$next[0:0]$6978 $1\logical_op__is_32bit$16$next[0:0]$6996
+ assign $0\logical_op__is_signed$17$next[0:0]$6979 $1\logical_op__is_signed$17$next[0:0]$6997
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$15$next[0:0]$7034 $1\logical_op__output_carry$15$next[0:0]$7052
+ assign $0\logical_op__output_carry$15$next[0:0]$6982 $1\logical_op__output_carry$15$next[0:0]$7000
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$14$next[0:0]$7037 $1\logical_op__write_cr0$14$next[0:0]$7055
- assign $0\logical_op__zero_a$11$next[0:0]$7038 $1\logical_op__zero_a$11$next[0:0]$7056
- assign $0\logical_op__imm_data__data$4$next[63:0]$7023 $2\logical_op__imm_data__data$4$next[63:0]$7057
- assign $0\logical_op__imm_data__ok$5$next[0:0]$7024 $2\logical_op__imm_data__ok$5$next[0:0]$7058
- assign $0\logical_op__oe__oe$8$next[0:0]$7032 $2\logical_op__oe__oe$8$next[0:0]$7059
- assign $0\logical_op__oe__ok$9$next[0:0]$7033 $2\logical_op__oe__ok$9$next[0:0]$7060
- assign $0\logical_op__rc__ok$7$next[0:0]$7035 $2\logical_op__rc__ok$7$next[0:0]$7061
- assign $0\logical_op__rc__rc$6$next[0:0]$7036 $2\logical_op__rc__rc$6$next[0:0]$7062
- attribute \src "libresoc.v:147344.5-147344.29"
+ assign $0\logical_op__write_cr0$14$next[0:0]$6985 $1\logical_op__write_cr0$14$next[0:0]$7003
+ assign $0\logical_op__zero_a$11$next[0:0]$6986 $1\logical_op__zero_a$11$next[0:0]$7004
+ assign $0\logical_op__imm_data__data$4$next[63:0]$6971 $2\logical_op__imm_data__data$4$next[63:0]$7005
+ assign $0\logical_op__imm_data__ok$5$next[0:0]$6972 $2\logical_op__imm_data__ok$5$next[0:0]$7006
+ assign $0\logical_op__oe__oe$8$next[0:0]$6980 $2\logical_op__oe__oe$8$next[0:0]$7007
+ assign $0\logical_op__oe__ok$9$next[0:0]$6981 $2\logical_op__oe__ok$9$next[0:0]$7008
+ assign $0\logical_op__rc__ok$7$next[0:0]$6983 $2\logical_op__rc__ok$7$next[0:0]$7009
+ assign $0\logical_op__rc__rc$6$next[0:0]$6984 $2\logical_op__rc__rc$6$next[0:0]$7010
+ attribute \src "libresoc.v:147008.5-147008.29"
switch \initial
- attribute \src "libresoc.v:147344.9-147344.17"
+ attribute \src "libresoc.v:147008.9-147008.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$7044 $1\logical_op__data_len$18$next[3:0]$7039 $1\logical_op__is_signed$17$next[0:0]$7049 $1\logical_op__is_32bit$16$next[0:0]$7048 $1\logical_op__output_carry$15$next[0:0]$7052 $1\logical_op__write_cr0$14$next[0:0]$7055 $1\logical_op__invert_out$13$next[0:0]$7047 $1\logical_op__input_carry$12$next[1:0]$7043 $1\logical_op__zero_a$11$next[0:0]$7056 $1\logical_op__invert_in$10$next[0:0]$7046 $1\logical_op__oe__ok$9$next[0:0]$7051 $1\logical_op__oe__oe$8$next[0:0]$7050 $1\logical_op__rc__ok$7$next[0:0]$7053 $1\logical_op__rc__rc$6$next[0:0]$7054 $1\logical_op__imm_data__ok$5$next[0:0]$7042 $1\logical_op__imm_data__data$4$next[63:0]$7041 $1\logical_op__fn_unit$3$next[13:0]$7040 $1\logical_op__insn_type$2$next[6:0]$7045 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
+ assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$7044 $1\logical_op__data_len$18$next[3:0]$7039 $1\logical_op__is_signed$17$next[0:0]$7049 $1\logical_op__is_32bit$16$next[0:0]$7048 $1\logical_op__output_carry$15$next[0:0]$7052 $1\logical_op__write_cr0$14$next[0:0]$7055 $1\logical_op__invert_out$13$next[0:0]$7047 $1\logical_op__input_carry$12$next[1:0]$7043 $1\logical_op__zero_a$11$next[0:0]$7056 $1\logical_op__invert_in$10$next[0:0]$7046 $1\logical_op__oe__ok$9$next[0:0]$7051 $1\logical_op__oe__oe$8$next[0:0]$7050 $1\logical_op__rc__ok$7$next[0:0]$7053 $1\logical_op__rc__rc$6$next[0:0]$7054 $1\logical_op__imm_data__ok$5$next[0:0]$7042 $1\logical_op__imm_data__data$4$next[63:0]$7041 $1\logical_op__fn_unit$3$next[13:0]$7040 $1\logical_op__insn_type$2$next[6:0]$7045 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
+ assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
case
- assign $1\logical_op__data_len$18$next[3:0]$7039 \logical_op__data_len$18
- assign $1\logical_op__fn_unit$3$next[13:0]$7040 \logical_op__fn_unit$3
- assign $1\logical_op__imm_data__data$4$next[63:0]$7041 \logical_op__imm_data__data$4
- assign $1\logical_op__imm_data__ok$5$next[0:0]$7042 \logical_op__imm_data__ok$5
- assign $1\logical_op__input_carry$12$next[1:0]$7043 \logical_op__input_carry$12
- assign $1\logical_op__insn$19$next[31:0]$7044 \logical_op__insn$19
- assign $1\logical_op__insn_type$2$next[6:0]$7045 \logical_op__insn_type$2
- assign $1\logical_op__invert_in$10$next[0:0]$7046 \logical_op__invert_in$10
- assign $1\logical_op__invert_out$13$next[0:0]$7047 \logical_op__invert_out$13
- assign $1\logical_op__is_32bit$16$next[0:0]$7048 \logical_op__is_32bit$16
- assign $1\logical_op__is_signed$17$next[0:0]$7049 \logical_op__is_signed$17
- assign $1\logical_op__oe__oe$8$next[0:0]$7050 \logical_op__oe__oe$8
- assign $1\logical_op__oe__ok$9$next[0:0]$7051 \logical_op__oe__ok$9
- assign $1\logical_op__output_carry$15$next[0:0]$7052 \logical_op__output_carry$15
- assign $1\logical_op__rc__ok$7$next[0:0]$7053 \logical_op__rc__ok$7
- assign $1\logical_op__rc__rc$6$next[0:0]$7054 \logical_op__rc__rc$6
- assign $1\logical_op__write_cr0$14$next[0:0]$7055 \logical_op__write_cr0$14
- assign $1\logical_op__zero_a$11$next[0:0]$7056 \logical_op__zero_a$11
+ assign $1\logical_op__data_len$18$next[3:0]$6987 \logical_op__data_len$18
+ assign $1\logical_op__fn_unit$3$next[13:0]$6988 \logical_op__fn_unit$3
+ assign $1\logical_op__imm_data__data$4$next[63:0]$6989 \logical_op__imm_data__data$4
+ assign $1\logical_op__imm_data__ok$5$next[0:0]$6990 \logical_op__imm_data__ok$5
+ assign $1\logical_op__input_carry$12$next[1:0]$6991 \logical_op__input_carry$12
+ assign $1\logical_op__insn$19$next[31:0]$6992 \logical_op__insn$19
+ assign $1\logical_op__insn_type$2$next[6:0]$6993 \logical_op__insn_type$2
+ assign $1\logical_op__invert_in$10$next[0:0]$6994 \logical_op__invert_in$10
+ assign $1\logical_op__invert_out$13$next[0:0]$6995 \logical_op__invert_out$13
+ assign $1\logical_op__is_32bit$16$next[0:0]$6996 \logical_op__is_32bit$16
+ assign $1\logical_op__is_signed$17$next[0:0]$6997 \logical_op__is_signed$17
+ assign $1\logical_op__oe__oe$8$next[0:0]$6998 \logical_op__oe__oe$8
+ assign $1\logical_op__oe__ok$9$next[0:0]$6999 \logical_op__oe__ok$9
+ assign $1\logical_op__output_carry$15$next[0:0]$7000 \logical_op__output_carry$15
+ assign $1\logical_op__rc__ok$7$next[0:0]$7001 \logical_op__rc__ok$7
+ assign $1\logical_op__rc__rc$6$next[0:0]$7002 \logical_op__rc__rc$6
+ assign $1\logical_op__write_cr0$14$next[0:0]$7003 \logical_op__write_cr0$14
+ assign $1\logical_op__zero_a$11$next[0:0]$7004 \logical_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$4$next[63:0]$7057 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$5$next[0:0]$7058 1'0
- assign $2\logical_op__rc__rc$6$next[0:0]$7062 1'0
- assign $2\logical_op__rc__ok$7$next[0:0]$7061 1'0
- assign $2\logical_op__oe__oe$8$next[0:0]$7059 1'0
- assign $2\logical_op__oe__ok$9$next[0:0]$7060 1'0
+ assign $2\logical_op__imm_data__data$4$next[63:0]$7005 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 1'0
+ assign $2\logical_op__rc__rc$6$next[0:0]$7010 1'0
+ assign $2\logical_op__rc__ok$7$next[0:0]$7009 1'0
+ assign $2\logical_op__oe__oe$8$next[0:0]$7007 1'0
+ assign $2\logical_op__oe__ok$9$next[0:0]$7008 1'0
case
- assign $2\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__imm_data__data$4$next[63:0]$7041
- assign $2\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__ok$5$next[0:0]$7042
- assign $2\logical_op__oe__oe$8$next[0:0]$7059 $1\logical_op__oe__oe$8$next[0:0]$7050
- assign $2\logical_op__oe__ok$9$next[0:0]$7060 $1\logical_op__oe__ok$9$next[0:0]$7051
- assign $2\logical_op__rc__ok$7$next[0:0]$7061 $1\logical_op__rc__ok$7$next[0:0]$7053
- assign $2\logical_op__rc__rc$6$next[0:0]$7062 $1\logical_op__rc__rc$6$next[0:0]$7054
+ assign $2\logical_op__imm_data__data$4$next[63:0]$7005 $1\logical_op__imm_data__data$4$next[63:0]$6989
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 $1\logical_op__imm_data__ok$5$next[0:0]$6990
+ assign $2\logical_op__oe__oe$8$next[0:0]$7007 $1\logical_op__oe__oe$8$next[0:0]$6998
+ assign $2\logical_op__oe__ok$9$next[0:0]$7008 $1\logical_op__oe__ok$9$next[0:0]$6999
+ assign $2\logical_op__rc__ok$7$next[0:0]$7009 $1\logical_op__rc__ok$7$next[0:0]$7001
+ assign $2\logical_op__rc__rc$6$next[0:0]$7010 $1\logical_op__rc__rc$6$next[0:0]$7002
end
sync always
- update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7021
- update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7022
- update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7023
- update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7024
- update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7025
- update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7026
- update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7027
- update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7028
- update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7029
- update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7030
- update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7031
- update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7032
- update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7033
- update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7034
- update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7035
- update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7036
- update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7037
- update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7038
+ update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6969
+ update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6970
+ update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6971
+ update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6972
+ update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6973
+ update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6974
+ update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6975
+ update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6976
+ update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6977
+ update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6978
+ update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6979
+ update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6980
+ update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6981
+ update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6982
+ update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6983
+ update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6984
+ update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6985
+ update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6986
end
- attribute \src "libresoc.v:147385.3-147403.6"
- process $proc$libresoc.v:147385$7063
+ attribute \src "libresoc.v:147049.3-147067.6"
+ process $proc$libresoc.v:147049$7011
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$20$next[63:0]$7064 $1\o$20$next[63:0]$7066
+ assign $0\o$20$next[63:0]$7012 $1\o$20$next[63:0]$7014
assign { } { }
- assign $0\o_ok$21$next[0:0]$7065 $2\o_ok$21$next[0:0]$7068
- attribute \src "libresoc.v:147386.5-147386.29"
+ assign $0\o_ok$21$next[0:0]$7013 $2\o_ok$21$next[0:0]$7016
+ attribute \src "libresoc.v:147050.5-147050.29"
switch \initial
- attribute \src "libresoc.v:147386.9-147386.17"
+ attribute \src "libresoc.v:147050.9-147050.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$7067 $1\o$20$next[63:0]$7066 } { \o_ok$71 \o$70 }
+ assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$7067 $1\o$20$next[63:0]$7066 } { \o_ok$71 \o$70 }
+ assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 }
case
- assign $1\o$20$next[63:0]$7066 \o$20
- assign $1\o_ok$21$next[0:0]$7067 \o_ok$21
+ assign $1\o$20$next[63:0]$7014 \o$20
+ assign $1\o_ok$21$next[0:0]$7015 \o_ok$21
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$21$next[0:0]$7068 1'0
+ assign $2\o_ok$21$next[0:0]$7016 1'0
case
- assign $2\o_ok$21$next[0:0]$7068 $1\o_ok$21$next[0:0]$7067
+ assign $2\o_ok$21$next[0:0]$7016 $1\o_ok$21$next[0:0]$7015
end
sync always
- update \o$20$next $0\o$20$next[63:0]$7064
- update \o_ok$21$next $0\o_ok$21$next[0:0]$7065
+ update \o$20$next $0\o$20$next[63:0]$7012
+ update \o_ok$21$next $0\o_ok$21$next[0:0]$7013
end
- attribute \src "libresoc.v:147404.3-147422.6"
- process $proc$libresoc.v:147404$7069
+ attribute \src "libresoc.v:147068.3-147086.6"
+ process $proc$libresoc.v:147068$7017
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$22$next[3:0]$7070 $1\cr_a$22$next[3:0]$7072
+ assign $0\cr_a$22$next[3:0]$7018 $1\cr_a$22$next[3:0]$7020
assign { } { }
- assign $0\cr_a_ok$23$next[0:0]$7071 $2\cr_a_ok$23$next[0:0]$7074
- attribute \src "libresoc.v:147405.5-147405.29"
+ assign $0\cr_a_ok$23$next[0:0]$7019 $2\cr_a_ok$23$next[0:0]$7022
+ attribute \src "libresoc.v:147069.5-147069.29"
switch \initial
- attribute \src "libresoc.v:147405.9-147405.17"
+ attribute \src "libresoc.v:147069.9-147069.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$7073 $1\cr_a$22$next[3:0]$7072 } { \cr_a_ok$73 \cr_a$72 }
+ assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$7073 $1\cr_a$22$next[3:0]$7072 } { \cr_a_ok$73 \cr_a$72 }
+ assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 }
case
- assign $1\cr_a$22$next[3:0]$7072 \cr_a$22
- assign $1\cr_a_ok$23$next[0:0]$7073 \cr_a_ok$23
+ assign $1\cr_a$22$next[3:0]$7020 \cr_a$22
+ assign $1\cr_a_ok$23$next[0:0]$7021 \cr_a_ok$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$23$next[0:0]$7074 1'0
+ assign $2\cr_a_ok$23$next[0:0]$7022 1'0
case
- assign $2\cr_a_ok$23$next[0:0]$7074 $1\cr_a_ok$23$next[0:0]$7073
+ assign $2\cr_a_ok$23$next[0:0]$7022 $1\cr_a_ok$23$next[0:0]$7021
end
sync always
- update \cr_a$22$next $0\cr_a$22$next[3:0]$7070
- update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7071
+ update \cr_a$22$next $0\cr_a$22$next[3:0]$7018
+ update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7019
end
- connect \$49 $and$libresoc.v:147207$6965_Y
+ connect \$49 $and$libresoc.v:146871$6913_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 }
wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
attribute \src "ls180.v:4193.1-4298.4"
wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
- attribute \src "ls180.v:129.5-129.64"
+ attribute \src "ls180.v:138.5-138.64"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
- attribute \src "ls180.v:131.5-131.65"
+ attribute \src "ls180.v:140.5-140.65"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
- attribute \src "ls180.v:130.5-130.65"
+ attribute \src "ls180.v:139.5-139.65"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
- attribute \src "ls180.v:122.5-122.58"
+ attribute \src "ls180.v:118.5-118.58"
wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0]
attribute \src "ls180.v:1320.11-1320.55"
wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:124.12-124.65"
+ attribute \src "ls180.v:120.12-120.65"
wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
- attribute \src "ls180.v:125.12-125.66"
+ attribute \src "ls180.v:121.12-121.66"
wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
- attribute \src "ls180.v:133.12-133.66"
+ attribute \src "ls180.v:122.12-122.66"
wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
- attribute \src "ls180.v:142.11-142.65"
+ attribute \src "ls180.v:131.11-131.65"
wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
- attribute \src "ls180.v:139.5-139.62"
+ attribute \src "ls180.v:128.5-128.62"
wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
- attribute \src "ls180.v:141.5-141.60"
+ attribute \src "ls180.v:130.5-130.60"
wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
- attribute \src "ls180.v:144.5-144.62"
+ attribute \src "ls180.v:133.5-133.62"
wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
- attribute \src "ls180.v:140.5-140.61"
+ attribute \src "ls180.v:129.5-129.61"
wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
- attribute \src "ls180.v:143.11-143.65"
+ attribute \src "ls180.v:132.11-132.65"
wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
- attribute \src "ls180.v:135.12-135.69"
+ attribute \src "ls180.v:124.12-124.69"
wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
- attribute \src "ls180.v:136.5-136.62"
+ attribute \src "ls180.v:125.5-125.62"
wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
- attribute \src "ls180.v:138.5-138.62"
+ attribute \src "ls180.v:127.5-127.62"
wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
- attribute \src "ls180.v:137.5-137.61"
+ attribute \src "ls180.v:126.5-126.61"
wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
- attribute \src "ls180.v:121.5-121.58"
+ attribute \src "ls180.v:117.5-117.58"
wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
attribute \src "ls180.v:55.12-55.50"
wire width 16 $1\libresocsim_libresoc_interrupt[15:0]
wire width 2 \dfi_p0_wrdata_mask
attribute \src "ls180.v:998.12-998.17"
wire width 36 \dummy
- attribute \src "ls180.v:14.13-14.19"
- wire input 10 \eint_0
- attribute \src "ls180.v:15.13-15.19"
- wire input 11 \eint_1
- attribute \src "ls180.v:16.13-16.19"
- wire input 12 \eint_2
+ attribute \src "ls180.v:30.13-30.19"
+ wire input 26 \eint_0
+ attribute \src "ls180.v:31.13-31.19"
+ wire input 27 \eint_1
+ attribute \src "ls180.v:32.13-32.19"
+ wire input 28 \eint_2
attribute \src "ls180.v:996.11-996.19"
wire width 3 \eint_tmp
attribute \src "ls180.v:884.12-884.34"
wire width 8 \gpio1_status
attribute \src "ls180.v:990.6-990.14"
wire \gpio1_we
- attribute \src "ls180.v:11.20-11.26"
- wire width 16 input 7 \gpio_i
- attribute \src "ls180.v:12.21-12.27"
- wire width 16 output 8 \gpio_o
- attribute \src "ls180.v:13.21-13.28"
- wire width 16 output 9 \gpio_oe
+ attribute \src "ls180.v:7.20-7.26"
+ wire width 16 input 3 \gpio_i
+ attribute \src "ls180.v:8.21-8.27"
+ wire width 16 output 4 \gpio_o
+ attribute \src "ls180.v:9.21-9.28"
+ wire width 16 output 5 \gpio_oe
attribute \src "ls180.v:1000.6-1000.12"
wire \i2c_oe
attribute \src "ls180.v:1003.5-1003.11"
wire \i2c_re
- attribute \src "ls180.v:5.14-5.21"
- wire output 1 \i2c_scl
+ attribute \src "ls180.v:22.14-22.21"
+ wire output 18 \i2c_scl
attribute \src "ls180.v:999.6-999.15"
wire \i2c_scl_1
attribute \src "ls180.v:1001.6-1001.14"
wire \i2c_sda0
attribute \src "ls180.v:1004.6-1004.14"
wire \i2c_sda1
- attribute \src "ls180.v:6.13-6.22"
- wire input 2 \i2c_sda_i
- attribute \src "ls180.v:7.14-7.23"
- wire output 3 \i2c_sda_o
- attribute \src "ls180.v:8.14-8.24"
- wire output 4 \i2c_sda_oe
+ attribute \src "ls180.v:23.13-23.22"
+ wire input 19 \i2c_sda_i
+ attribute \src "ls180.v:24.14-24.23"
+ wire output 20 \i2c_sda_o
+ attribute \src "ls180.v:25.14-25.24"
+ wire output 21 \i2c_sda_oe
attribute \src "ls180.v:1005.6-1005.16"
wire \i2c_status
attribute \src "ls180.v:1002.11-1002.22"
wire width 64 \libresocsim_libresoc2
attribute \src "ls180.v:115.12-115.40"
wire width 2 \libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:126.6-126.51"
+ attribute \src "ls180.v:142.6-142.51"
wire \libresocsim_libresoc_constraintmanager_eint_0
- attribute \src "ls180.v:127.6-127.51"
+ attribute \src "ls180.v:143.6-143.51"
wire \libresocsim_libresoc_constraintmanager_eint_1
- attribute \src "ls180.v:128.6-128.51"
+ attribute \src "ls180.v:144.6-144.51"
wire \libresocsim_libresoc_constraintmanager_eint_2
- attribute \src "ls180.v:123.13-123.58"
+ attribute \src "ls180.v:119.13-119.58"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i
- attribute \src "ls180.v:124.12-124.57"
+ attribute \src "ls180.v:120.12-120.57"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o
- attribute \src "ls180.v:125.12-125.58"
+ attribute \src "ls180.v:121.12-121.58"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe
- attribute \src "ls180.v:117.6-117.52"
+ attribute \src "ls180.v:134.6-134.52"
wire \libresocsim_libresoc_constraintmanager_i2c_scl
- attribute \src "ls180.v:118.6-118.54"
+ attribute \src "ls180.v:135.6-135.54"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_i
- attribute \src "ls180.v:119.6-119.54"
+ attribute \src "ls180.v:136.6-136.54"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_o
- attribute \src "ls180.v:120.6-120.55"
+ attribute \src "ls180.v:137.6-137.55"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe
- attribute \src "ls180.v:133.12-133.58"
+ attribute \src "ls180.v:122.12-122.58"
wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a
- attribute \src "ls180.v:142.11-142.58"
+ attribute \src "ls180.v:131.11-131.58"
wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba
- attribute \src "ls180.v:139.5-139.55"
+ attribute \src "ls180.v:128.5-128.55"
wire \libresocsim_libresoc_constraintmanager_sdram_cas_n
- attribute \src "ls180.v:141.5-141.53"
+ attribute \src "ls180.v:130.5-130.53"
wire \libresocsim_libresoc_constraintmanager_sdram_cke
- attribute \src "ls180.v:144.5-144.55"
+ attribute \src "ls180.v:133.5-133.55"
wire \libresocsim_libresoc_constraintmanager_sdram_clock
- attribute \src "ls180.v:140.5-140.54"
+ attribute \src "ls180.v:129.5-129.54"
wire \libresocsim_libresoc_constraintmanager_sdram_cs_n
- attribute \src "ls180.v:143.11-143.58"
+ attribute \src "ls180.v:132.11-132.58"
wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm
- attribute \src "ls180.v:134.13-134.62"
+ attribute \src "ls180.v:123.13-123.62"
wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i
- attribute \src "ls180.v:135.12-135.61"
+ attribute \src "ls180.v:124.12-124.61"
wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o
- attribute \src "ls180.v:136.5-136.55"
+ attribute \src "ls180.v:125.5-125.55"
wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe
- attribute \src "ls180.v:138.5-138.55"
+ attribute \src "ls180.v:127.5-127.55"
wire \libresocsim_libresoc_constraintmanager_sdram_ras_n
- attribute \src "ls180.v:137.5-137.54"
+ attribute \src "ls180.v:126.5-126.54"
wire \libresocsim_libresoc_constraintmanager_sdram_we_n
- attribute \src "ls180.v:129.5-129.57"
+ attribute \src "ls180.v:138.5-138.57"
wire \libresocsim_libresoc_constraintmanager_spimaster_clk
- attribute \src "ls180.v:131.5-131.58"
+ attribute \src "ls180.v:140.5-140.58"
wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n
- attribute \src "ls180.v:132.6-132.59"
+ attribute \src "ls180.v:141.6-141.59"
wire \libresocsim_libresoc_constraintmanager_spimaster_miso
- attribute \src "ls180.v:130.5-130.58"
+ attribute \src "ls180.v:139.5-139.58"
wire \libresocsim_libresoc_constraintmanager_spimaster_mosi
- attribute \src "ls180.v:122.5-122.51"
+ attribute \src "ls180.v:118.5-118.51"
wire \libresocsim_libresoc_constraintmanager_uart_rx
- attribute \src "ls180.v:121.5-121.51"
+ attribute \src "ls180.v:117.5-117.51"
wire \libresocsim_libresoc_constraintmanager_uart_tx
attribute \src "ls180.v:62.6-62.35"
wire \libresocsim_libresoc_dbus_ack
wire width 8 \rxtx_w
attribute \src "ls180.v:862.6-862.13"
wire \rxtx_we
- attribute \src "ls180.v:21.21-21.28"
- wire width 13 output 17 \sdram_a
+ attribute \src "ls180.v:10.21-10.28"
+ wire width 13 output 6 \sdram_a
attribute \src "ls180.v:314.5-314.21"
wire \sdram_address_re
attribute \src "ls180.v:313.12-313.33"
wire width 13 \sdram_address_storage
- attribute \src "ls180.v:30.20-30.28"
- wire width 2 output 26 \sdram_ba
+ attribute \src "ls180.v:19.20-19.28"
+ wire width 2 output 15 \sdram_ba
attribute \src "ls180.v:316.5-316.22"
wire \sdram_baddress_re
attribute \src "ls180.v:315.11-315.33"
wire \sdram_bankmachine3_twtpcon_valid
attribute \src "ls180.v:722.6-722.23"
wire \sdram_cas_allowed
- attribute \src "ls180.v:27.14-27.25"
- wire output 23 \sdram_cas_n
+ attribute \src "ls180.v:16.14-16.25"
+ wire output 12 \sdram_cas_n
attribute \src "ls180.v:740.6-740.25"
wire \sdram_choose_cmd_ce
attribute \src "ls180.v:729.13-729.43"
wire \sdram_choose_req_want_reads
attribute \src "ls180.v:742.5-742.33"
wire \sdram_choose_req_want_writes
- attribute \src "ls180.v:29.14-29.23"
- wire output 25 \sdram_cke
+ attribute \src "ls180.v:18.14-18.23"
+ wire output 14 \sdram_cke
attribute \src "ls180.v:302.6-302.17"
wire \sdram_cke_1
- attribute \src "ls180.v:32.14-32.25"
- wire output 28 \sdram_clock
+ attribute \src "ls180.v:21.14-21.25"
+ wire output 17 \sdram_clock
attribute \src "ls180.v:370.5-370.19"
wire \sdram_cmd_last
attribute \src "ls180.v:371.12-371.31"
wire \sdram_command_re
attribute \src "ls180.v:307.11-307.32"
wire width 6 \sdram_command_storage
- attribute \src "ls180.v:28.14-28.24"
- wire output 24 \sdram_cs_n
+ attribute \src "ls180.v:17.14-17.24"
+ wire output 13 \sdram_cs_n
attribute \src "ls180.v:361.5-361.23"
wire \sdram_dfi_p0_act_n
attribute \src "ls180.v:352.12-352.32"
wire \sdram_dfi_p0_wrdata_en
attribute \src "ls180.v:364.12-364.36"
wire width 2 \sdram_dfi_p0_wrdata_mask
- attribute \src "ls180.v:31.20-31.28"
- wire width 2 output 27 \sdram_dm
- attribute \src "ls180.v:22.20-22.30"
- wire width 16 input 18 \sdram_dq_i
- attribute \src "ls180.v:23.21-23.31"
- wire width 16 output 19 \sdram_dq_o
- attribute \src "ls180.v:24.14-24.25"
- wire output 20 \sdram_dq_oe
+ attribute \src "ls180.v:20.20-20.28"
+ wire width 2 output 16 \sdram_dm
+ attribute \src "ls180.v:11.20-11.30"
+ wire width 16 input 7 \sdram_dq_i
+ attribute \src "ls180.v:12.21-12.31"
+ wire width 16 output 8 \sdram_dq_o
+ attribute \src "ls180.v:13.14-13.25"
+ wire output 9 \sdram_dq_oe
attribute \src "ls180.v:776.5-776.14"
wire \sdram_en0
attribute \src "ls180.v:779.5-779.14"
wire \sdram_postponer_req_o
attribute \src "ls180.v:721.6-721.23"
wire \sdram_ras_allowed
- attribute \src "ls180.v:26.14-26.25"
- wire output 22 \sdram_ras_n
+ attribute \src "ls180.v:15.14-15.25"
+ wire output 11 \sdram_ras_n
attribute \src "ls180.v:306.5-306.13"
wire \sdram_re
attribute \src "ls180.v:774.6-774.26"
wire \sdram_wants_refresh
attribute \src "ls180.v:320.6-320.14"
wire \sdram_we
- attribute \src "ls180.v:25.14-25.24"
- wire output 21 \sdram_we_n
+ attribute \src "ls180.v:14.14-14.24"
+ wire output 10 \sdram_we_n
attribute \src "ls180.v:318.5-318.20"
wire \sdram_wrdata_re
attribute \src "ls180.v:317.12-317.32"
wire \socbushandler_reset
attribute \src "ls180.v:815.5-815.23"
wire \socbushandler_skip
- attribute \src "ls180.v:17.14-17.27"
- wire output 13 \spimaster_clk
- attribute \src "ls180.v:19.14-19.28"
- wire output 15 \spimaster_cs_n
- attribute \src "ls180.v:20.13-20.27"
- wire input 16 \spimaster_miso
- attribute \src "ls180.v:18.14-18.28"
- wire output 14 \spimaster_mosi
+ attribute \src "ls180.v:26.14-26.27"
+ wire output 22 \spimaster_clk
+ attribute \src "ls180.v:28.14-28.28"
+ wire output 24 \spimaster_cs_n
+ attribute \src "ls180.v:29.13-29.27"
+ wire input 25 \spimaster_miso
+ attribute \src "ls180.v:27.14-27.28"
+ wire output 23 \spimaster_mosi
attribute \src "ls180.v:1022.11-1022.47"
wire width 3 \subfragments_bankmachine0_next_state
attribute \src "ls180.v:1021.11-1021.42"
wire \uart_phy_uart_clk_rxen
attribute \src "ls180.v:843.5-843.27"
wire \uart_phy_uart_clk_txen
- attribute \src "ls180.v:10.13-10.20"
- wire input 6 \uart_rx
+ attribute \src "ls180.v:6.13-6.20"
+ wire input 2 \uart_rx
attribute \src "ls180.v:895.6-895.21"
wire \uart_sink_first
attribute \src "ls180.v:896.6-896.20"
wire \uart_source_ready
attribute \src "ls180.v:898.6-898.23"
wire \uart_source_valid
- attribute \src "ls180.v:9.13-9.20"
- wire input 5 \uart_tx
+ attribute \src "ls180.v:5.13-5.20"
+ wire input 1 \uart_tx
attribute \src "ls180.v:802.5-802.17"
wire \wb_sdram_ack
attribute \src "ls180.v:796.12-796.24"
sync init
update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
end
+ attribute \src "ls180.v:117.5-117.58"
+ process $proc$ls180.v:117$1651
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+ end
attribute \src "ls180.v:1176.11-1176.55"
process $proc$ls180.v:1176$2084
assign { } { }
sync init
update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
end
+ attribute \src "ls180.v:118.5-118.58"
+ process $proc$ls180.v:118$1652
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
+ sync always
+ update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
+ sync init
+ end
attribute \src "ls180.v:1189.11-1189.55"
process $proc$ls180.v:1189$2085
assign { } { }
sync init
update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:121.5-121.58"
- process $proc$ls180.v:121$1651
+ attribute \src "ls180.v:120.12-120.65"
+ process $proc$ls180.v:120$1653
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+ update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
end
- attribute \src "ls180.v:122.5-122.58"
- process $proc$ls180.v:122$1652
+ attribute \src "ls180.v:121.12-121.66"
+ process $proc$ls180.v:121$1654
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
sync always
- update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ end
+ attribute \src "ls180.v:122.12-122.66"
+ process $proc$ls180.v:122$1655
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
end
attribute \src "ls180.v:1230.11-1230.55"
process $proc$ls180.v:1230$2086
sync init
update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:124.12-124.65"
- process $proc$ls180.v:124$1653
+ attribute \src "ls180.v:124.12-124.69"
+ process $proc$ls180.v:124$1656
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
end
- attribute \src "ls180.v:125.12-125.66"
- process $proc$ls180.v:125$1654
+ attribute \src "ls180.v:125.5-125.62"
+ process $proc$ls180.v:125$1657
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
end
- attribute \src "ls180.v:129.5-129.64"
- process $proc$ls180.v:129$1655
+ attribute \src "ls180.v:126.5-126.61"
+ process $proc$ls180.v:126$1658
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+ end
+ attribute \src "ls180.v:127.5-127.62"
+ process $proc$ls180.v:127$1659
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+ end
+ attribute \src "ls180.v:128.5-128.62"
+ process $proc$ls180.v:128$1660
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+ end
+ attribute \src "ls180.v:129.5-129.61"
+ process $proc$ls180.v:129$1661
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
end
attribute \src "ls180.v:1295.11-1295.55"
process $proc$ls180.v:1295$2087
sync init
update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:130.5-130.65"
- process $proc$ls180.v:130$1656
+ attribute \src "ls180.v:130.5-130.60"
+ process $proc$ls180.v:130$1662
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
end
- attribute \src "ls180.v:131.5-131.65"
- process $proc$ls180.v:131$1657
+ attribute \src "ls180.v:131.11-131.65"
+ process $proc$ls180.v:131$1663
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
+ end
+ attribute \src "ls180.v:132.11-132.65"
+ process $proc$ls180.v:132$1664
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
end
attribute \src "ls180.v:1320.11-1320.55"
process $proc$ls180.v:1320$2088
sync init
update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:133.12-133.66"
- process $proc$ls180.v:133$1658
+ attribute \src "ls180.v:133.5-133.62"
+ process $proc$ls180.v:133$1665
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
end
attribute \src "ls180.v:1342.11-1342.35"
process $proc$ls180.v:1342$2089
sync init
update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
end
- attribute \src "ls180.v:135.12-135.69"
- process $proc$ls180.v:135$1659
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
- end
attribute \src "ls180.v:1350.5-1350.28"
process $proc$ls180.v:1350$2097
assign { } { }
sync init
update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:136.5-136.62"
- process $proc$ls180.v:136$1660
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
- end
attribute \src "ls180.v:1360.12-1360.36"
process $proc$ls180.v:1360$2107
assign { } { }
sync init
update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:137.5-137.61"
- process $proc$ls180.v:137$1661
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
- end
attribute \src "ls180.v:1370.5-1370.29"
process $proc$ls180.v:1370$2117
assign { } { }
sync init
update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:138.5-138.62"
- process $proc$ls180.v:138$1662
+ attribute \src "ls180.v:138.5-138.64"
+ process $proc$ls180.v:138$1666
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
end
attribute \src "ls180.v:1380.12-1380.37"
process $proc$ls180.v:1380$2127
sync init
update \array_muxed1 $1\array_muxed1[12:0]
end
- attribute \src "ls180.v:139.5-139.62"
- process $proc$ls180.v:139$1663
+ attribute \src "ls180.v:139.5-139.65"
+ process $proc$ls180.v:139$1667
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
end
attribute \src "ls180.v:1390.5-1390.24"
process $proc$ls180.v:1390$2137
sync init
update \array_muxed6 $1\array_muxed6[0:0]
end
- attribute \src "ls180.v:140.5-140.61"
- process $proc$ls180.v:140$1664
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
- end
- attribute \src "ls180.v:141.5-141.60"
- process $proc$ls180.v:141$1665
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
- end
- attribute \src "ls180.v:142.11-142.65"
- process $proc$ls180.v:142$1666
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
- end
- attribute \src "ls180.v:143.11-143.65"
- process $proc$ls180.v:143$1667
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
- end
- attribute \src "ls180.v:144.5-144.62"
- process $proc$ls180.v:144$1668
+ attribute \src "ls180.v:140.5-140.65"
+ process $proc$ls180.v:140$1668
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
end
attribute \src "ls180.v:1451.32-1451.44"
process $proc$ls180.v:1451$2142
connect \rx_fifo_wrport_dat_r \memdat_6
connect \rx_fifo_rdport_dat_r \memdat_7
end
-attribute \src "libresoc.v:147441.1-147499.10"
+attribute \src "libresoc.v:147105.1-147163.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l"
attribute \generator "nMigen"
module \lsd_l
- attribute \src "libresoc.v:147442.7-147442.20"
+ attribute \src "libresoc.v:147106.7-147106.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:147487.3-147495.6"
- wire $0\q_int$next[0:0]$7133
- attribute \src "libresoc.v:147485.3-147486.27"
+ attribute \src "libresoc.v:147151.3-147159.6"
+ wire $0\q_int$next[0:0]$7081
+ attribute \src "libresoc.v:147149.3-147150.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:147487.3-147495.6"
- wire $1\q_int$next[0:0]$7134
- attribute \src "libresoc.v:147464.7-147464.19"
+ attribute \src "libresoc.v:147151.3-147159.6"
+ wire $1\q_int$next[0:0]$7082
+ attribute \src "libresoc.v:147128.7-147128.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:147477.17-147477.96"
- wire $and$libresoc.v:147477$7123_Y
- attribute \src "libresoc.v:147482.17-147482.96"
- wire $and$libresoc.v:147482$7128_Y
- attribute \src "libresoc.v:147479.18-147479.93"
- wire $not$libresoc.v:147479$7125_Y
- attribute \src "libresoc.v:147481.17-147481.92"
- wire $not$libresoc.v:147481$7127_Y
- attribute \src "libresoc.v:147484.17-147484.92"
- wire $not$libresoc.v:147484$7130_Y
- attribute \src "libresoc.v:147478.18-147478.98"
- wire $or$libresoc.v:147478$7124_Y
- attribute \src "libresoc.v:147480.18-147480.99"
- wire $or$libresoc.v:147480$7126_Y
- attribute \src "libresoc.v:147483.17-147483.97"
- wire $or$libresoc.v:147483$7129_Y
+ attribute \src "libresoc.v:147141.17-147141.96"
+ wire $and$libresoc.v:147141$7071_Y
+ attribute \src "libresoc.v:147146.17-147146.96"
+ wire $and$libresoc.v:147146$7076_Y
+ attribute \src "libresoc.v:147143.18-147143.93"
+ wire $not$libresoc.v:147143$7073_Y
+ attribute \src "libresoc.v:147145.17-147145.92"
+ wire $not$libresoc.v:147145$7075_Y
+ attribute \src "libresoc.v:147148.17-147148.92"
+ wire $not$libresoc.v:147148$7078_Y
+ attribute \src "libresoc.v:147142.18-147142.98"
+ wire $or$libresoc.v:147142$7072_Y
+ attribute \src "libresoc.v:147144.18-147144.99"
+ wire $or$libresoc.v:147144$7074_Y
+ attribute \src "libresoc.v:147147.17-147147.97"
+ wire $or$libresoc.v:147147$7077_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:147442.7-147442.15"
+ attribute \src "libresoc.v:147106.7-147106.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_lsd
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:147477$7123
+ cell $and $and$libresoc.v:147141$7071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:147477$7123_Y
+ connect \Y $and$libresoc.v:147141$7071_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:147482$7128
+ cell $and $and$libresoc.v:147146$7076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:147482$7128_Y
+ connect \Y $and$libresoc.v:147146$7076_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:147479$7125
+ cell $not $not$libresoc.v:147143$7073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_lsd
- connect \Y $not$libresoc.v:147479$7125_Y
+ connect \Y $not$libresoc.v:147143$7073_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:147481$7127
+ cell $not $not$libresoc.v:147145$7075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lsd
- connect \Y $not$libresoc.v:147481$7127_Y
+ connect \Y $not$libresoc.v:147145$7075_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:147484$7130
+ cell $not $not$libresoc.v:147148$7078
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lsd
- connect \Y $not$libresoc.v:147484$7130_Y
+ connect \Y $not$libresoc.v:147148$7078_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:147478$7124
+ cell $or $or$libresoc.v:147142$7072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_lsd
- connect \Y $or$libresoc.v:147478$7124_Y
+ connect \Y $or$libresoc.v:147142$7072_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:147480$7126
+ cell $or $or$libresoc.v:147144$7074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_lsd
connect \B \q_int
- connect \Y $or$libresoc.v:147480$7126_Y
+ connect \Y $or$libresoc.v:147144$7074_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:147483$7129
+ cell $or $or$libresoc.v:147147$7077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_lsd
- connect \Y $or$libresoc.v:147483$7129_Y
+ connect \Y $or$libresoc.v:147147$7077_Y
end
- attribute \src "libresoc.v:147442.7-147442.20"
- process $proc$libresoc.v:147442$7135
+ attribute \src "libresoc.v:147106.7-147106.20"
+ process $proc$libresoc.v:147106$7083
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:147464.7-147464.19"
- process $proc$libresoc.v:147464$7136
+ attribute \src "libresoc.v:147128.7-147128.19"
+ process $proc$libresoc.v:147128$7084
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:147485.3-147486.27"
- process $proc$libresoc.v:147485$7131
+ attribute \src "libresoc.v:147149.3-147150.27"
+ process $proc$libresoc.v:147149$7079
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:147487.3-147495.6"
- process $proc$libresoc.v:147487$7132
+ attribute \src "libresoc.v:147151.3-147159.6"
+ process $proc$libresoc.v:147151$7080
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$7133 $1\q_int$next[0:0]$7134
- attribute \src "libresoc.v:147488.5-147488.29"
+ assign $0\q_int$next[0:0]$7081 $1\q_int$next[0:0]$7082
+ attribute \src "libresoc.v:147152.5-147152.29"
switch \initial
- attribute \src "libresoc.v:147488.9-147488.17"
+ attribute \src "libresoc.v:147152.9-147152.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$7134 1'0
+ assign $1\q_int$next[0:0]$7082 1'0
case
- assign $1\q_int$next[0:0]$7134 \$5
+ assign $1\q_int$next[0:0]$7082 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$7133
+ update \q_int$next $0\q_int$next[0:0]$7081
end
- connect \$9 $and$libresoc.v:147477$7123_Y
- connect \$11 $or$libresoc.v:147478$7124_Y
- connect \$13 $not$libresoc.v:147479$7125_Y
- connect \$15 $or$libresoc.v:147480$7126_Y
- connect \$1 $not$libresoc.v:147481$7127_Y
- connect \$3 $and$libresoc.v:147482$7128_Y
- connect \$5 $or$libresoc.v:147483$7129_Y
- connect \$7 $not$libresoc.v:147484$7130_Y
+ connect \$9 $and$libresoc.v:147141$7071_Y
+ connect \$11 $or$libresoc.v:147142$7072_Y
+ connect \$13 $not$libresoc.v:147143$7073_Y
+ connect \$15 $or$libresoc.v:147144$7074_Y
+ connect \$1 $not$libresoc.v:147145$7075_Y
+ connect \$3 $and$libresoc.v:147146$7076_Y
+ connect \$5 $or$libresoc.v:147147$7077_Y
+ connect \$7 $not$libresoc.v:147148$7078_Y
connect \qlq_lsd \$15
connect \qn_lsd \$13
connect \q_lsd \$11
end
-attribute \src "libresoc.v:147503.1-148037.10"
+attribute \src "libresoc.v:147167.1-147701.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem"
attribute \generator "nMigen"
module \lsmem
- attribute \src "libresoc.v:147891.3-147916.6"
- wire width 45 $0\dbus__adr$next[44:0]$7222
- attribute \src "libresoc.v:147741.3-147742.35"
+ attribute \src "libresoc.v:147555.3-147580.6"
+ wire width 45 $0\dbus__adr$next[44:0]$7170
+ attribute \src "libresoc.v:147405.3-147406.35"
wire width 45 $0\dbus__adr[44:0]
- attribute \src "libresoc.v:147751.3-147778.6"
- wire $0\dbus__cyc$next[0:0]$7196
- attribute \src "libresoc.v:147749.3-147750.35"
+ attribute \src "libresoc.v:147415.3-147442.6"
+ wire $0\dbus__cyc$next[0:0]$7144
+ attribute \src "libresoc.v:147413.3-147414.35"
wire $0\dbus__cyc[0:0]
- attribute \src "libresoc.v:147943.3-147968.6"
- wire width 64 $0\dbus__dat_w$next[63:0]$7232
- attribute \src "libresoc.v:147737.3-147738.39"
+ attribute \src "libresoc.v:147607.3-147632.6"
+ wire width 64 $0\dbus__dat_w$next[63:0]$7180
+ attribute \src "libresoc.v:147401.3-147402.39"
wire width 64 $0\dbus__dat_w[63:0]
- attribute \src "libresoc.v:147835.3-147865.6"
- wire width 8 $0\dbus__sel$next[7:0]$7210
- attribute \src "libresoc.v:147745.3-147746.35"
+ attribute \src "libresoc.v:147499.3-147529.6"
+ wire width 8 $0\dbus__sel$next[7:0]$7158
+ attribute \src "libresoc.v:147409.3-147410.35"
wire width 8 $0\dbus__sel[7:0]
- attribute \src "libresoc.v:147779.3-147806.6"
- wire $0\dbus__stb$next[0:0]$7202
- attribute \src "libresoc.v:147747.3-147748.35"
+ attribute \src "libresoc.v:147443.3-147470.6"
+ wire $0\dbus__stb$next[0:0]$7150
+ attribute \src "libresoc.v:147411.3-147412.35"
wire $0\dbus__stb[0:0]
- attribute \src "libresoc.v:147917.3-147942.6"
- wire $0\dbus__we$next[0:0]$7227
- attribute \src "libresoc.v:147739.3-147740.33"
+ attribute \src "libresoc.v:147581.3-147606.6"
+ wire $0\dbus__we$next[0:0]$7175
+ attribute \src "libresoc.v:147403.3-147404.33"
wire $0\dbus__we[0:0]
- attribute \src "libresoc.v:147504.7-147504.20"
+ attribute \src "libresoc.v:147168.7-147168.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:148015.3-148034.6"
- wire width 45 $0\m_badaddr_o$next[44:0]$7247
- attribute \src "libresoc.v:147731.3-147732.39"
+ attribute \src "libresoc.v:147679.3-147698.6"
+ wire width 45 $0\m_badaddr_o$next[44:0]$7195
+ attribute \src "libresoc.v:147395.3-147396.39"
wire width 45 $0\m_badaddr_o[44:0]
- attribute \src "libresoc.v:147817.3-147834.6"
+ attribute \src "libresoc.v:147481.3-147498.6"
wire $0\m_busy_o[0:0]
- attribute \src "libresoc.v:147866.3-147890.6"
- wire width 64 $0\m_ld_data_o$next[63:0]$7216
- attribute \src "libresoc.v:147743.3-147744.39"
+ attribute \src "libresoc.v:147530.3-147554.6"
+ wire width 64 $0\m_ld_data_o$next[63:0]$7164
+ attribute \src "libresoc.v:147407.3-147408.39"
wire width 64 $0\m_ld_data_o[63:0]
- attribute \src "libresoc.v:147969.3-147991.6"
- wire $0\m_load_err_o$next[0:0]$7237
- attribute \src "libresoc.v:147735.3-147736.41"
+ attribute \src "libresoc.v:147633.3-147655.6"
+ wire $0\m_load_err_o$next[0:0]$7185
+ attribute \src "libresoc.v:147399.3-147400.41"
wire $0\m_load_err_o[0:0]
- attribute \src "libresoc.v:147992.3-148014.6"
- wire $0\m_store_err_o$next[0:0]$7242
- attribute \src "libresoc.v:147733.3-147734.43"
+ attribute \src "libresoc.v:147656.3-147678.6"
+ wire $0\m_store_err_o$next[0:0]$7190
+ attribute \src "libresoc.v:147397.3-147398.43"
wire $0\m_store_err_o[0:0]
- attribute \src "libresoc.v:147807.3-147816.6"
+ attribute \src "libresoc.v:147471.3-147480.6"
wire $0\x_busy_o[0:0]
- attribute \src "libresoc.v:147891.3-147916.6"
- wire width 45 $1\dbus__adr$next[44:0]$7223
- attribute \src "libresoc.v:147609.14-147609.42"
+ attribute \src "libresoc.v:147555.3-147580.6"
+ wire width 45 $1\dbus__adr$next[44:0]$7171
+ attribute \src "libresoc.v:147273.14-147273.42"
wire width 45 $1\dbus__adr[44:0]
- attribute \src "libresoc.v:147751.3-147778.6"
- wire $1\dbus__cyc$next[0:0]$7197
- attribute \src "libresoc.v:147614.7-147614.23"
+ attribute \src "libresoc.v:147415.3-147442.6"
+ wire $1\dbus__cyc$next[0:0]$7145
+ attribute \src "libresoc.v:147278.7-147278.23"
wire $1\dbus__cyc[0:0]
- attribute \src "libresoc.v:147943.3-147968.6"
- wire width 64 $1\dbus__dat_w$next[63:0]$7233
- attribute \src "libresoc.v:147621.14-147621.48"
+ attribute \src "libresoc.v:147607.3-147632.6"
+ wire width 64 $1\dbus__dat_w$next[63:0]$7181
+ attribute \src "libresoc.v:147285.14-147285.48"
wire width 64 $1\dbus__dat_w[63:0]
- attribute \src "libresoc.v:147835.3-147865.6"
- wire width 8 $1\dbus__sel$next[7:0]$7211
- attribute \src "libresoc.v:147628.13-147628.30"
+ attribute \src "libresoc.v:147499.3-147529.6"
+ wire width 8 $1\dbus__sel$next[7:0]$7159
+ attribute \src "libresoc.v:147292.13-147292.30"
wire width 8 $1\dbus__sel[7:0]
- attribute \src "libresoc.v:147779.3-147806.6"
- wire $1\dbus__stb$next[0:0]$7203
- attribute \src "libresoc.v:147633.7-147633.23"
+ attribute \src "libresoc.v:147443.3-147470.6"
+ wire $1\dbus__stb$next[0:0]$7151
+ attribute \src "libresoc.v:147297.7-147297.23"
wire $1\dbus__stb[0:0]
- attribute \src "libresoc.v:147917.3-147942.6"
- wire $1\dbus__we$next[0:0]$7228
- attribute \src "libresoc.v:147638.7-147638.22"
+ attribute \src "libresoc.v:147581.3-147606.6"
+ wire $1\dbus__we$next[0:0]$7176
+ attribute \src "libresoc.v:147302.7-147302.22"
wire $1\dbus__we[0:0]
- attribute \src "libresoc.v:148015.3-148034.6"
- wire width 45 $1\m_badaddr_o$next[44:0]$7248
- attribute \src "libresoc.v:147642.14-147642.44"
+ attribute \src "libresoc.v:147679.3-147698.6"
+ wire width 45 $1\m_badaddr_o$next[44:0]$7196
+ attribute \src "libresoc.v:147306.14-147306.44"
wire width 45 $1\m_badaddr_o[44:0]
- attribute \src "libresoc.v:147817.3-147834.6"
+ attribute \src "libresoc.v:147481.3-147498.6"
wire $1\m_busy_o[0:0]
- attribute \src "libresoc.v:147866.3-147890.6"
- wire width 64 $1\m_ld_data_o$next[63:0]$7217
- attribute \src "libresoc.v:147649.14-147649.48"
+ attribute \src "libresoc.v:147530.3-147554.6"
+ wire width 64 $1\m_ld_data_o$next[63:0]$7165
+ attribute \src "libresoc.v:147313.14-147313.48"
wire width 64 $1\m_ld_data_o[63:0]
- attribute \src "libresoc.v:147969.3-147991.6"
- wire $1\m_load_err_o$next[0:0]$7238
- attribute \src "libresoc.v:147653.7-147653.26"
+ attribute \src "libresoc.v:147633.3-147655.6"
+ wire $1\m_load_err_o$next[0:0]$7186
+ attribute \src "libresoc.v:147317.7-147317.26"
wire $1\m_load_err_o[0:0]
- attribute \src "libresoc.v:147992.3-148014.6"
- wire $1\m_store_err_o$next[0:0]$7243
- attribute \src "libresoc.v:147659.7-147659.27"
+ attribute \src "libresoc.v:147656.3-147678.6"
+ wire $1\m_store_err_o$next[0:0]$7191
+ attribute \src "libresoc.v:147323.7-147323.27"
wire $1\m_store_err_o[0:0]
- attribute \src "libresoc.v:147807.3-147816.6"
+ attribute \src "libresoc.v:147471.3-147480.6"
wire $1\x_busy_o[0:0]
- attribute \src "libresoc.v:147891.3-147916.6"
- wire width 45 $2\dbus__adr$next[44:0]$7224
- attribute \src "libresoc.v:147751.3-147778.6"
- wire $2\dbus__cyc$next[0:0]$7198
- attribute \src "libresoc.v:147943.3-147968.6"
- wire width 64 $2\dbus__dat_w$next[63:0]$7234
- attribute \src "libresoc.v:147835.3-147865.6"
- wire width 8 $2\dbus__sel$next[7:0]$7212
- attribute \src "libresoc.v:147779.3-147806.6"
- wire $2\dbus__stb$next[0:0]$7204
- attribute \src "libresoc.v:147917.3-147942.6"
- wire $2\dbus__we$next[0:0]$7229
- attribute \src "libresoc.v:148015.3-148034.6"
- wire width 45 $2\m_badaddr_o$next[44:0]$7249
- attribute \src "libresoc.v:147817.3-147834.6"
+ attribute \src "libresoc.v:147555.3-147580.6"
+ wire width 45 $2\dbus__adr$next[44:0]$7172
+ attribute \src "libresoc.v:147415.3-147442.6"
+ wire $2\dbus__cyc$next[0:0]$7146
+ attribute \src "libresoc.v:147607.3-147632.6"
+ wire width 64 $2\dbus__dat_w$next[63:0]$7182
+ attribute \src "libresoc.v:147499.3-147529.6"
+ wire width 8 $2\dbus__sel$next[7:0]$7160
+ attribute \src "libresoc.v:147443.3-147470.6"
+ wire $2\dbus__stb$next[0:0]$7152
+ attribute \src "libresoc.v:147581.3-147606.6"
+ wire $2\dbus__we$next[0:0]$7177
+ attribute \src "libresoc.v:147679.3-147698.6"
+ wire width 45 $2\m_badaddr_o$next[44:0]$7197
+ attribute \src "libresoc.v:147481.3-147498.6"
wire $2\m_busy_o[0:0]
- attribute \src "libresoc.v:147866.3-147890.6"
- wire width 64 $2\m_ld_data_o$next[63:0]$7218
- attribute \src "libresoc.v:147969.3-147991.6"
- wire $2\m_load_err_o$next[0:0]$7239
- attribute \src "libresoc.v:147992.3-148014.6"
- wire $2\m_store_err_o$next[0:0]$7244
- attribute \src "libresoc.v:147891.3-147916.6"
- wire width 45 $3\dbus__adr$next[44:0]$7225
- attribute \src "libresoc.v:147751.3-147778.6"
- wire $3\dbus__cyc$next[0:0]$7199
- attribute \src "libresoc.v:147943.3-147968.6"
- wire width 64 $3\dbus__dat_w$next[63:0]$7235
- attribute \src "libresoc.v:147835.3-147865.6"
- wire width 8 $3\dbus__sel$next[7:0]$7213
- attribute \src "libresoc.v:147779.3-147806.6"
- wire $3\dbus__stb$next[0:0]$7205
- attribute \src "libresoc.v:147917.3-147942.6"
- wire $3\dbus__we$next[0:0]$7230
- attribute \src "libresoc.v:148015.3-148034.6"
- wire width 45 $3\m_badaddr_o$next[44:0]$7250
- attribute \src "libresoc.v:147866.3-147890.6"
- wire width 64 $3\m_ld_data_o$next[63:0]$7219
- attribute \src "libresoc.v:147969.3-147991.6"
- wire $3\m_load_err_o$next[0:0]$7240
- attribute \src "libresoc.v:147992.3-148014.6"
- wire $3\m_store_err_o$next[0:0]$7245
- attribute \src "libresoc.v:147751.3-147778.6"
- wire $4\dbus__cyc$next[0:0]$7200
- attribute \src "libresoc.v:147835.3-147865.6"
- wire width 8 $4\dbus__sel$next[7:0]$7214
- attribute \src "libresoc.v:147779.3-147806.6"
- wire $4\dbus__stb$next[0:0]$7206
- attribute \src "libresoc.v:147866.3-147890.6"
- wire width 64 $4\m_ld_data_o$next[63:0]$7220
- attribute \src "libresoc.v:147687.18-147687.116"
- wire $and$libresoc.v:147687$7141_Y
- attribute \src "libresoc.v:147690.18-147690.111"
- wire $and$libresoc.v:147690$7144_Y
- attribute \src "libresoc.v:147695.18-147695.116"
- wire $and$libresoc.v:147695$7149_Y
- attribute \src "libresoc.v:147697.18-147697.111"
- wire $and$libresoc.v:147697$7151_Y
- attribute \src "libresoc.v:147699.17-147699.114"
- wire $and$libresoc.v:147699$7153_Y
- attribute \src "libresoc.v:147703.18-147703.116"
- wire $and$libresoc.v:147703$7157_Y
- attribute \src "libresoc.v:147705.18-147705.111"
- wire $and$libresoc.v:147705$7159_Y
- attribute \src "libresoc.v:147711.18-147711.116"
- wire $and$libresoc.v:147711$7165_Y
- attribute \src "libresoc.v:147713.18-147713.111"
- wire $and$libresoc.v:147713$7167_Y
- attribute \src "libresoc.v:147715.18-147715.116"
- wire $and$libresoc.v:147715$7169_Y
- attribute \src "libresoc.v:147717.18-147717.111"
- wire $and$libresoc.v:147717$7171_Y
- attribute \src "libresoc.v:147719.18-147719.116"
- wire $and$libresoc.v:147719$7173_Y
- attribute \src "libresoc.v:147721.17-147721.108"
- wire $and$libresoc.v:147721$7175_Y
- attribute \src "libresoc.v:147722.18-147722.111"
- wire $and$libresoc.v:147722$7176_Y
- attribute \src "libresoc.v:147723.18-147723.120"
- wire $and$libresoc.v:147723$7177_Y
- attribute \src "libresoc.v:147726.18-147726.120"
- wire $and$libresoc.v:147726$7180_Y
- attribute \src "libresoc.v:147728.18-147728.120"
- wire $and$libresoc.v:147728$7182_Y
- attribute \src "libresoc.v:147684.18-147684.110"
- wire $not$libresoc.v:147684$7138_Y
- attribute \src "libresoc.v:147689.18-147689.110"
- wire $not$libresoc.v:147689$7143_Y
- attribute \src "libresoc.v:147692.18-147692.110"
- wire $not$libresoc.v:147692$7146_Y
- attribute \src "libresoc.v:147696.18-147696.110"
- wire $not$libresoc.v:147696$7150_Y
- attribute \src "libresoc.v:147700.18-147700.110"
- wire $not$libresoc.v:147700$7154_Y
- attribute \src "libresoc.v:147704.18-147704.110"
- wire $not$libresoc.v:147704$7158_Y
- attribute \src "libresoc.v:147707.18-147707.110"
- wire $not$libresoc.v:147707$7161_Y
- attribute \src "libresoc.v:147710.17-147710.109"
- wire $not$libresoc.v:147710$7164_Y
- attribute \src "libresoc.v:147712.18-147712.110"
- wire $not$libresoc.v:147712$7166_Y
- attribute \src "libresoc.v:147716.18-147716.110"
- wire $not$libresoc.v:147716$7170_Y
- attribute \src "libresoc.v:147720.18-147720.110"
- wire $not$libresoc.v:147720$7174_Y
- attribute \src "libresoc.v:147724.18-147724.110"
- wire $not$libresoc.v:147724$7178_Y
- attribute \src "libresoc.v:147725.18-147725.109"
- wire $not$libresoc.v:147725$7179_Y
- attribute \src "libresoc.v:147727.18-147727.110"
- wire $not$libresoc.v:147727$7181_Y
- attribute \src "libresoc.v:147729.18-147729.110"
- wire $not$libresoc.v:147729$7183_Y
- attribute \src "libresoc.v:147683.17-147683.119"
- wire $or$libresoc.v:147683$7137_Y
- attribute \src "libresoc.v:147685.18-147685.110"
- wire $or$libresoc.v:147685$7139_Y
- attribute \src "libresoc.v:147686.18-147686.114"
- wire $or$libresoc.v:147686$7140_Y
- attribute \src "libresoc.v:147688.17-147688.113"
- wire $or$libresoc.v:147688$7142_Y
- attribute \src "libresoc.v:147691.18-147691.120"
- wire $or$libresoc.v:147691$7145_Y
- attribute \src "libresoc.v:147693.18-147693.111"
- wire $or$libresoc.v:147693$7147_Y
- attribute \src "libresoc.v:147694.18-147694.114"
- wire $or$libresoc.v:147694$7148_Y
- attribute \src "libresoc.v:147698.18-147698.120"
- wire $or$libresoc.v:147698$7152_Y
- attribute \src "libresoc.v:147701.18-147701.111"
- wire $or$libresoc.v:147701$7155_Y
- attribute \src "libresoc.v:147702.18-147702.114"
- wire $or$libresoc.v:147702$7156_Y
- attribute \src "libresoc.v:147706.18-147706.120"
- wire $or$libresoc.v:147706$7160_Y
- attribute \src "libresoc.v:147708.18-147708.111"
- wire $or$libresoc.v:147708$7162_Y
- attribute \src "libresoc.v:147709.18-147709.114"
- wire $or$libresoc.v:147709$7163_Y
- attribute \src "libresoc.v:147714.18-147714.114"
- wire $or$libresoc.v:147714$7168_Y
- attribute \src "libresoc.v:147718.18-147718.114"
- wire $or$libresoc.v:147718$7172_Y
- attribute \src "libresoc.v:147730.18-147730.127"
- wire $or$libresoc.v:147730$7184_Y
+ attribute \src "libresoc.v:147530.3-147554.6"
+ wire width 64 $2\m_ld_data_o$next[63:0]$7166
+ attribute \src "libresoc.v:147633.3-147655.6"
+ wire $2\m_load_err_o$next[0:0]$7187
+ attribute \src "libresoc.v:147656.3-147678.6"
+ wire $2\m_store_err_o$next[0:0]$7192
+ attribute \src "libresoc.v:147555.3-147580.6"
+ wire width 45 $3\dbus__adr$next[44:0]$7173
+ attribute \src "libresoc.v:147415.3-147442.6"
+ wire $3\dbus__cyc$next[0:0]$7147
+ attribute \src "libresoc.v:147607.3-147632.6"
+ wire width 64 $3\dbus__dat_w$next[63:0]$7183
+ attribute \src "libresoc.v:147499.3-147529.6"
+ wire width 8 $3\dbus__sel$next[7:0]$7161
+ attribute \src "libresoc.v:147443.3-147470.6"
+ wire $3\dbus__stb$next[0:0]$7153
+ attribute \src "libresoc.v:147581.3-147606.6"
+ wire $3\dbus__we$next[0:0]$7178
+ attribute \src "libresoc.v:147679.3-147698.6"
+ wire width 45 $3\m_badaddr_o$next[44:0]$7198
+ attribute \src "libresoc.v:147530.3-147554.6"
+ wire width 64 $3\m_ld_data_o$next[63:0]$7167
+ attribute \src "libresoc.v:147633.3-147655.6"
+ wire $3\m_load_err_o$next[0:0]$7188
+ attribute \src "libresoc.v:147656.3-147678.6"
+ wire $3\m_store_err_o$next[0:0]$7193
+ attribute \src "libresoc.v:147415.3-147442.6"
+ wire $4\dbus__cyc$next[0:0]$7148
+ attribute \src "libresoc.v:147499.3-147529.6"
+ wire width 8 $4\dbus__sel$next[7:0]$7162
+ attribute \src "libresoc.v:147443.3-147470.6"
+ wire $4\dbus__stb$next[0:0]$7154
+ attribute \src "libresoc.v:147530.3-147554.6"
+ wire width 64 $4\m_ld_data_o$next[63:0]$7168
+ attribute \src "libresoc.v:147351.18-147351.116"
+ wire $and$libresoc.v:147351$7089_Y
+ attribute \src "libresoc.v:147354.18-147354.111"
+ wire $and$libresoc.v:147354$7092_Y
+ attribute \src "libresoc.v:147359.18-147359.116"
+ wire $and$libresoc.v:147359$7097_Y
+ attribute \src "libresoc.v:147361.18-147361.111"
+ wire $and$libresoc.v:147361$7099_Y
+ attribute \src "libresoc.v:147363.17-147363.114"
+ wire $and$libresoc.v:147363$7101_Y
+ attribute \src "libresoc.v:147367.18-147367.116"
+ wire $and$libresoc.v:147367$7105_Y
+ attribute \src "libresoc.v:147369.18-147369.111"
+ wire $and$libresoc.v:147369$7107_Y
+ attribute \src "libresoc.v:147375.18-147375.116"
+ wire $and$libresoc.v:147375$7113_Y
+ attribute \src "libresoc.v:147377.18-147377.111"
+ wire $and$libresoc.v:147377$7115_Y
+ attribute \src "libresoc.v:147379.18-147379.116"
+ wire $and$libresoc.v:147379$7117_Y
+ attribute \src "libresoc.v:147381.18-147381.111"
+ wire $and$libresoc.v:147381$7119_Y
+ attribute \src "libresoc.v:147383.18-147383.116"
+ wire $and$libresoc.v:147383$7121_Y
+ attribute \src "libresoc.v:147385.17-147385.108"
+ wire $and$libresoc.v:147385$7123_Y
+ attribute \src "libresoc.v:147386.18-147386.111"
+ wire $and$libresoc.v:147386$7124_Y
+ attribute \src "libresoc.v:147387.18-147387.120"
+ wire $and$libresoc.v:147387$7125_Y
+ attribute \src "libresoc.v:147390.18-147390.120"
+ wire $and$libresoc.v:147390$7128_Y
+ attribute \src "libresoc.v:147392.18-147392.120"
+ wire $and$libresoc.v:147392$7130_Y
+ attribute \src "libresoc.v:147348.18-147348.110"
+ wire $not$libresoc.v:147348$7086_Y
+ attribute \src "libresoc.v:147353.18-147353.110"
+ wire $not$libresoc.v:147353$7091_Y
+ attribute \src "libresoc.v:147356.18-147356.110"
+ wire $not$libresoc.v:147356$7094_Y
+ attribute \src "libresoc.v:147360.18-147360.110"
+ wire $not$libresoc.v:147360$7098_Y
+ attribute \src "libresoc.v:147364.18-147364.110"
+ wire $not$libresoc.v:147364$7102_Y
+ attribute \src "libresoc.v:147368.18-147368.110"
+ wire $not$libresoc.v:147368$7106_Y
+ attribute \src "libresoc.v:147371.18-147371.110"
+ wire $not$libresoc.v:147371$7109_Y
+ attribute \src "libresoc.v:147374.17-147374.109"
+ wire $not$libresoc.v:147374$7112_Y
+ attribute \src "libresoc.v:147376.18-147376.110"
+ wire $not$libresoc.v:147376$7114_Y
+ attribute \src "libresoc.v:147380.18-147380.110"
+ wire $not$libresoc.v:147380$7118_Y
+ attribute \src "libresoc.v:147384.18-147384.110"
+ wire $not$libresoc.v:147384$7122_Y
+ attribute \src "libresoc.v:147388.18-147388.110"
+ wire $not$libresoc.v:147388$7126_Y
+ attribute \src "libresoc.v:147389.18-147389.109"
+ wire $not$libresoc.v:147389$7127_Y
+ attribute \src "libresoc.v:147391.18-147391.110"
+ wire $not$libresoc.v:147391$7129_Y
+ attribute \src "libresoc.v:147393.18-147393.110"
+ wire $not$libresoc.v:147393$7131_Y
+ attribute \src "libresoc.v:147347.17-147347.119"
+ wire $or$libresoc.v:147347$7085_Y
+ attribute \src "libresoc.v:147349.18-147349.110"
+ wire $or$libresoc.v:147349$7087_Y
+ attribute \src "libresoc.v:147350.18-147350.114"
+ wire $or$libresoc.v:147350$7088_Y
+ attribute \src "libresoc.v:147352.17-147352.113"
+ wire $or$libresoc.v:147352$7090_Y
+ attribute \src "libresoc.v:147355.18-147355.120"
+ wire $or$libresoc.v:147355$7093_Y
+ attribute \src "libresoc.v:147357.18-147357.111"
+ wire $or$libresoc.v:147357$7095_Y
+ attribute \src "libresoc.v:147358.18-147358.114"
+ wire $or$libresoc.v:147358$7096_Y
+ attribute \src "libresoc.v:147362.18-147362.120"
+ wire $or$libresoc.v:147362$7100_Y
+ attribute \src "libresoc.v:147365.18-147365.111"
+ wire $or$libresoc.v:147365$7103_Y
+ attribute \src "libresoc.v:147366.18-147366.114"
+ wire $or$libresoc.v:147366$7104_Y
+ attribute \src "libresoc.v:147370.18-147370.120"
+ wire $or$libresoc.v:147370$7108_Y
+ attribute \src "libresoc.v:147372.18-147372.111"
+ wire $or$libresoc.v:147372$7110_Y
+ attribute \src "libresoc.v:147373.18-147373.114"
+ wire $or$libresoc.v:147373$7111_Y
+ attribute \src "libresoc.v:147378.18-147378.114"
+ wire $or$libresoc.v:147378$7116_Y
+ attribute \src "libresoc.v:147382.18-147382.114"
+ wire $or$libresoc.v:147382$7120_Y
+ attribute \src "libresoc.v:147394.18-147394.127"
+ wire $or$libresoc.v:147394$7132_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
wire \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
wire \$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 13 \dbus__ack
wire output 19 \dbus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire \dbus__we$next
- attribute \src "libresoc.v:147504.7-147504.15"
+ attribute \src "libresoc.v:147168.7-147168.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77"
wire width 45 \m_badaddr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57"
wire input 10 \x_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147687$7141
+ cell $and $and$libresoc.v:147351$7089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147687$7141_Y
+ connect \Y $and$libresoc.v:147351$7089_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147690$7144
+ cell $and $and$libresoc.v:147354$7092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$17
connect \B \$19
- connect \Y $and$libresoc.v:147690$7144_Y
+ connect \Y $and$libresoc.v:147354$7092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147695$7149
+ cell $and $and$libresoc.v:147359$7097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147695$7149_Y
+ connect \Y $and$libresoc.v:147359$7097_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147697$7151
+ cell $and $and$libresoc.v:147361$7099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $and$libresoc.v:147697$7151_Y
+ connect \Y $and$libresoc.v:147361$7099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147699$7153
+ cell $and $and$libresoc.v:147363$7101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147699$7153_Y
+ connect \Y $and$libresoc.v:147363$7101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147703$7157
+ cell $and $and$libresoc.v:147367$7105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147703$7157_Y
+ connect \Y $and$libresoc.v:147367$7105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147705$7159
+ cell $and $and$libresoc.v:147369$7107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$45
connect \B \$47
- connect \Y $and$libresoc.v:147705$7159_Y
+ connect \Y $and$libresoc.v:147369$7107_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147711$7165
+ cell $and $and$libresoc.v:147375$7113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$57
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147711$7165_Y
+ connect \Y $and$libresoc.v:147375$7113_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147713$7167
+ cell $and $and$libresoc.v:147377$7115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$59
connect \B \$61
- connect \Y $and$libresoc.v:147713$7167_Y
+ connect \Y $and$libresoc.v:147377$7115_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147715$7169
+ cell $and $and$libresoc.v:147379$7117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$65
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147715$7169_Y
+ connect \Y $and$libresoc.v:147379$7117_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147717$7171
+ cell $and $and$libresoc.v:147381$7119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$67
connect \B \$69
- connect \Y $and$libresoc.v:147717$7171_Y
+ connect \Y $and$libresoc.v:147381$7119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147719$7173
+ cell $and $and$libresoc.v:147383$7121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \x_valid_i
- connect \Y $and$libresoc.v:147719$7173_Y
+ connect \Y $and$libresoc.v:147383$7121_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147721$7175
+ cell $and $and$libresoc.v:147385$7123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:147721$7175_Y
+ connect \Y $and$libresoc.v:147385$7123_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:147722$7176
+ cell $and $and$libresoc.v:147386$7124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$75
connect \B \$77
- connect \Y $and$libresoc.v:147722$7176_Y
+ connect \Y $and$libresoc.v:147386$7124_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:147723$7177
+ cell $and $and$libresoc.v:147387$7125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:147723$7177_Y
+ connect \Y $and$libresoc.v:147387$7125_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:147726$7180
+ cell $and $and$libresoc.v:147390$7128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:147726$7180_Y
+ connect \Y $and$libresoc.v:147390$7128_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:147728$7182
+ cell $and $and$libresoc.v:147392$7130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:147728$7182_Y
+ connect \Y $and$libresoc.v:147392$7130_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:147684$7138
+ cell $not $not$libresoc.v:147348$7086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:147684$7138_Y
+ connect \Y $not$libresoc.v:147348$7086_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147689$7143
+ cell $not $not$libresoc.v:147353$7091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147689$7143_Y
+ connect \Y $not$libresoc.v:147353$7091_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:147692$7146
+ cell $not $not$libresoc.v:147356$7094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:147692$7146_Y
+ connect \Y $not$libresoc.v:147356$7094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147696$7150
+ cell $not $not$libresoc.v:147360$7098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147696$7150_Y
+ connect \Y $not$libresoc.v:147360$7098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:147700$7154
+ cell $not $not$libresoc.v:147364$7102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:147700$7154_Y
+ connect \Y $not$libresoc.v:147364$7102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147704$7158
+ cell $not $not$libresoc.v:147368$7106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147704$7158_Y
+ connect \Y $not$libresoc.v:147368$7106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:147707$7161
+ cell $not $not$libresoc.v:147371$7109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:147707$7161_Y
+ connect \Y $not$libresoc.v:147371$7109_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147710$7164
+ cell $not $not$libresoc.v:147374$7112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147710$7164_Y
+ connect \Y $not$libresoc.v:147374$7112_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147712$7166
+ cell $not $not$libresoc.v:147376$7114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147712$7166_Y
+ connect \Y $not$libresoc.v:147376$7114_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147716$7170
+ cell $not $not$libresoc.v:147380$7118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147716$7170_Y
+ connect \Y $not$libresoc.v:147380$7118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:147720$7174
+ cell $not $not$libresoc.v:147384$7122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:147720$7174_Y
+ connect \Y $not$libresoc.v:147384$7122_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:147724$7178
+ cell $not $not$libresoc.v:147388$7126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:147724$7178_Y
+ connect \Y $not$libresoc.v:147388$7126_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142"
- cell $not $not$libresoc.v:147725$7179
+ cell $not $not$libresoc.v:147389$7127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbus__we
- connect \Y $not$libresoc.v:147725$7179_Y
+ connect \Y $not$libresoc.v:147389$7127_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:147727$7181
+ cell $not $not$libresoc.v:147391$7129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:147727$7181_Y
+ connect \Y $not$libresoc.v:147391$7129_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:147729$7183
+ cell $not $not$libresoc.v:147393$7131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:147729$7183_Y
+ connect \Y $not$libresoc.v:147393$7131_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147683$7137
+ cell $or $or$libresoc.v:147347$7085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:147683$7137_Y
+ connect \Y $or$libresoc.v:147347$7085_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147685$7139
+ cell $or $or$libresoc.v:147349$7087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \$11
- connect \Y $or$libresoc.v:147685$7139_Y
+ connect \Y $or$libresoc.v:147349$7087_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147686$7140
+ cell $or $or$libresoc.v:147350$7088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147686$7140_Y
+ connect \Y $or$libresoc.v:147350$7088_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147688$7142
+ cell $or $or$libresoc.v:147352$7090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147688$7142_Y
+ connect \Y $or$libresoc.v:147352$7090_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147691$7145
+ cell $or $or$libresoc.v:147355$7093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:147691$7145_Y
+ connect \Y $or$libresoc.v:147355$7093_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147693$7147
+ cell $or $or$libresoc.v:147357$7095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $or$libresoc.v:147693$7147_Y
+ connect \Y $or$libresoc.v:147357$7095_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147694$7148
+ cell $or $or$libresoc.v:147358$7096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147694$7148_Y
+ connect \Y $or$libresoc.v:147358$7096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147698$7152
+ cell $or $or$libresoc.v:147362$7100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:147698$7152_Y
+ connect \Y $or$libresoc.v:147362$7100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147701$7155
+ cell $or $or$libresoc.v:147365$7103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$37
connect \B \$39
- connect \Y $or$libresoc.v:147701$7155_Y
+ connect \Y $or$libresoc.v:147365$7103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147702$7156
+ cell $or $or$libresoc.v:147366$7104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147702$7156_Y
+ connect \Y $or$libresoc.v:147366$7104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147706$7160
+ cell $or $or$libresoc.v:147370$7108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:147706$7160_Y
+ connect \Y $or$libresoc.v:147370$7108_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:147708$7162
+ cell $or $or$libresoc.v:147372$7110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \$53
- connect \Y $or$libresoc.v:147708$7162_Y
+ connect \Y $or$libresoc.v:147372$7110_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147709$7163
+ cell $or $or$libresoc.v:147373$7111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147709$7163_Y
+ connect \Y $or$libresoc.v:147373$7111_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147714$7168
+ cell $or $or$libresoc.v:147378$7116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147714$7168_Y
+ connect \Y $or$libresoc.v:147378$7116_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:147718$7172
+ cell $or $or$libresoc.v:147382$7120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:147718$7172_Y
+ connect \Y $or$libresoc.v:147382$7120_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
- cell $or $or$libresoc.v:147730$7184
+ cell $or $or$libresoc.v:147394$7132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \m_load_err_o
connect \B \m_store_err_o
- connect \Y $or$libresoc.v:147730$7184_Y
+ connect \Y $or$libresoc.v:147394$7132_Y
end
- attribute \src "libresoc.v:147504.7-147504.20"
- process $proc$libresoc.v:147504$7251
+ attribute \src "libresoc.v:147168.7-147168.20"
+ process $proc$libresoc.v:147168$7199
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:147609.14-147609.42"
- process $proc$libresoc.v:147609$7252
+ attribute \src "libresoc.v:147273.14-147273.42"
+ process $proc$libresoc.v:147273$7200
assign { } { }
assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \dbus__adr $1\dbus__adr[44:0]
end
- attribute \src "libresoc.v:147614.7-147614.23"
- process $proc$libresoc.v:147614$7253
+ attribute \src "libresoc.v:147278.7-147278.23"
+ process $proc$libresoc.v:147278$7201
assign { } { }
assign $1\dbus__cyc[0:0] 1'0
sync always
sync init
update \dbus__cyc $1\dbus__cyc[0:0]
end
- attribute \src "libresoc.v:147621.14-147621.48"
- process $proc$libresoc.v:147621$7254
+ attribute \src "libresoc.v:147285.14-147285.48"
+ process $proc$libresoc.v:147285$7202
assign { } { }
assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbus__dat_w $1\dbus__dat_w[63:0]
end
- attribute \src "libresoc.v:147628.13-147628.30"
- process $proc$libresoc.v:147628$7255
+ attribute \src "libresoc.v:147292.13-147292.30"
+ process $proc$libresoc.v:147292$7203
assign { } { }
assign $1\dbus__sel[7:0] 8'00000000
sync always
sync init
update \dbus__sel $1\dbus__sel[7:0]
end
- attribute \src "libresoc.v:147633.7-147633.23"
- process $proc$libresoc.v:147633$7256
+ attribute \src "libresoc.v:147297.7-147297.23"
+ process $proc$libresoc.v:147297$7204
assign { } { }
assign $1\dbus__stb[0:0] 1'0
sync always
sync init
update \dbus__stb $1\dbus__stb[0:0]
end
- attribute \src "libresoc.v:147638.7-147638.22"
- process $proc$libresoc.v:147638$7257
+ attribute \src "libresoc.v:147302.7-147302.22"
+ process $proc$libresoc.v:147302$7205
assign { } { }
assign $1\dbus__we[0:0] 1'0
sync always
sync init
update \dbus__we $1\dbus__we[0:0]
end
- attribute \src "libresoc.v:147642.14-147642.44"
- process $proc$libresoc.v:147642$7258
+ attribute \src "libresoc.v:147306.14-147306.44"
+ process $proc$libresoc.v:147306$7206
assign { } { }
assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \m_badaddr_o $1\m_badaddr_o[44:0]
end
- attribute \src "libresoc.v:147649.14-147649.48"
- process $proc$libresoc.v:147649$7259
+ attribute \src "libresoc.v:147313.14-147313.48"
+ process $proc$libresoc.v:147313$7207
assign { } { }
assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \m_ld_data_o $1\m_ld_data_o[63:0]
end
- attribute \src "libresoc.v:147653.7-147653.26"
- process $proc$libresoc.v:147653$7260
+ attribute \src "libresoc.v:147317.7-147317.26"
+ process $proc$libresoc.v:147317$7208
assign { } { }
assign $1\m_load_err_o[0:0] 1'0
sync always
sync init
update \m_load_err_o $1\m_load_err_o[0:0]
end
- attribute \src "libresoc.v:147659.7-147659.27"
- process $proc$libresoc.v:147659$7261
+ attribute \src "libresoc.v:147323.7-147323.27"
+ process $proc$libresoc.v:147323$7209
assign { } { }
assign $1\m_store_err_o[0:0] 1'0
sync always
sync init
update \m_store_err_o $1\m_store_err_o[0:0]
end
- attribute \src "libresoc.v:147731.3-147732.39"
- process $proc$libresoc.v:147731$7185
+ attribute \src "libresoc.v:147395.3-147396.39"
+ process $proc$libresoc.v:147395$7133
assign { } { }
assign $0\m_badaddr_o[44:0] \m_badaddr_o$next
sync posedge \coresync_clk
update \m_badaddr_o $0\m_badaddr_o[44:0]
end
- attribute \src "libresoc.v:147733.3-147734.43"
- process $proc$libresoc.v:147733$7186
+ attribute \src "libresoc.v:147397.3-147398.43"
+ process $proc$libresoc.v:147397$7134
assign { } { }
assign $0\m_store_err_o[0:0] \m_store_err_o$next
sync posedge \coresync_clk
update \m_store_err_o $0\m_store_err_o[0:0]
end
- attribute \src "libresoc.v:147735.3-147736.41"
- process $proc$libresoc.v:147735$7187
+ attribute \src "libresoc.v:147399.3-147400.41"
+ process $proc$libresoc.v:147399$7135
assign { } { }
assign $0\m_load_err_o[0:0] \m_load_err_o$next
sync posedge \coresync_clk
update \m_load_err_o $0\m_load_err_o[0:0]
end
- attribute \src "libresoc.v:147737.3-147738.39"
- process $proc$libresoc.v:147737$7188
+ attribute \src "libresoc.v:147401.3-147402.39"
+ process $proc$libresoc.v:147401$7136
assign { } { }
assign $0\dbus__dat_w[63:0] \dbus__dat_w$next
sync posedge \coresync_clk
update \dbus__dat_w $0\dbus__dat_w[63:0]
end
- attribute \src "libresoc.v:147739.3-147740.33"
- process $proc$libresoc.v:147739$7189
+ attribute \src "libresoc.v:147403.3-147404.33"
+ process $proc$libresoc.v:147403$7137
assign { } { }
assign $0\dbus__we[0:0] \dbus__we$next
sync posedge \coresync_clk
update \dbus__we $0\dbus__we[0:0]
end
- attribute \src "libresoc.v:147741.3-147742.35"
- process $proc$libresoc.v:147741$7190
+ attribute \src "libresoc.v:147405.3-147406.35"
+ process $proc$libresoc.v:147405$7138
assign { } { }
assign $0\dbus__adr[44:0] \dbus__adr$next
sync posedge \coresync_clk
update \dbus__adr $0\dbus__adr[44:0]
end
- attribute \src "libresoc.v:147743.3-147744.39"
- process $proc$libresoc.v:147743$7191
+ attribute \src "libresoc.v:147407.3-147408.39"
+ process $proc$libresoc.v:147407$7139
assign { } { }
assign $0\m_ld_data_o[63:0] \m_ld_data_o$next
sync posedge \coresync_clk
update \m_ld_data_o $0\m_ld_data_o[63:0]
end
- attribute \src "libresoc.v:147745.3-147746.35"
- process $proc$libresoc.v:147745$7192
+ attribute \src "libresoc.v:147409.3-147410.35"
+ process $proc$libresoc.v:147409$7140
assign { } { }
assign $0\dbus__sel[7:0] \dbus__sel$next
sync posedge \coresync_clk
update \dbus__sel $0\dbus__sel[7:0]
end
- attribute \src "libresoc.v:147747.3-147748.35"
- process $proc$libresoc.v:147747$7193
+ attribute \src "libresoc.v:147411.3-147412.35"
+ process $proc$libresoc.v:147411$7141
assign { } { }
assign $0\dbus__stb[0:0] \dbus__stb$next
sync posedge \coresync_clk
update \dbus__stb $0\dbus__stb[0:0]
end
- attribute \src "libresoc.v:147749.3-147750.35"
- process $proc$libresoc.v:147749$7194
+ attribute \src "libresoc.v:147413.3-147414.35"
+ process $proc$libresoc.v:147413$7142
assign { } { }
assign $0\dbus__cyc[0:0] \dbus__cyc$next
sync posedge \coresync_clk
update \dbus__cyc $0\dbus__cyc[0:0]
end
- attribute \src "libresoc.v:147751.3-147778.6"
- process $proc$libresoc.v:147751$7195
+ attribute \src "libresoc.v:147415.3-147442.6"
+ process $proc$libresoc.v:147415$7143
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__cyc$next[0:0]$7196 $4\dbus__cyc$next[0:0]$7200
- attribute \src "libresoc.v:147752.5-147752.29"
+ assign $0\dbus__cyc$next[0:0]$7144 $4\dbus__cyc$next[0:0]$7148
+ attribute \src "libresoc.v:147416.5-147416.29"
switch \initial
- attribute \src "libresoc.v:147752.9-147752.17"
+ attribute \src "libresoc.v:147416.9-147416.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__cyc$next[0:0]$7197 $2\dbus__cyc$next[0:0]$7198
+ assign $1\dbus__cyc$next[0:0]$7145 $2\dbus__cyc$next[0:0]$7146
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$7 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__cyc$next[0:0]$7198 $3\dbus__cyc$next[0:0]$7199
+ assign $2\dbus__cyc$next[0:0]$7146 $3\dbus__cyc$next[0:0]$7147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$13
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__cyc$next[0:0]$7199 1'0
+ assign $3\dbus__cyc$next[0:0]$7147 1'0
case
- assign $3\dbus__cyc$next[0:0]$7199 \dbus__cyc
+ assign $3\dbus__cyc$next[0:0]$7147 \dbus__cyc
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__cyc$next[0:0]$7198 1'1
+ assign $2\dbus__cyc$next[0:0]$7146 1'1
case
- assign $2\dbus__cyc$next[0:0]$7198 \dbus__cyc
+ assign $2\dbus__cyc$next[0:0]$7146 \dbus__cyc
end
case
- assign $1\dbus__cyc$next[0:0]$7197 \dbus__cyc
+ assign $1\dbus__cyc$next[0:0]$7145 \dbus__cyc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__cyc$next[0:0]$7200 1'0
+ assign $4\dbus__cyc$next[0:0]$7148 1'0
case
- assign $4\dbus__cyc$next[0:0]$7200 $1\dbus__cyc$next[0:0]$7197
+ assign $4\dbus__cyc$next[0:0]$7148 $1\dbus__cyc$next[0:0]$7145
end
sync always
- update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7196
+ update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7144
end
- attribute \src "libresoc.v:147779.3-147806.6"
- process $proc$libresoc.v:147779$7201
+ attribute \src "libresoc.v:147443.3-147470.6"
+ process $proc$libresoc.v:147443$7149
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__stb$next[0:0]$7202 $4\dbus__stb$next[0:0]$7206
- attribute \src "libresoc.v:147780.5-147780.29"
+ assign $0\dbus__stb$next[0:0]$7150 $4\dbus__stb$next[0:0]$7154
+ attribute \src "libresoc.v:147444.5-147444.29"
switch \initial
- attribute \src "libresoc.v:147780.9-147780.17"
+ attribute \src "libresoc.v:147444.9-147444.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__stb$next[0:0]$7203 $2\dbus__stb$next[0:0]$7204
+ assign $1\dbus__stb$next[0:0]$7151 $2\dbus__stb$next[0:0]$7152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$21 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__stb$next[0:0]$7204 $3\dbus__stb$next[0:0]$7205
+ assign $2\dbus__stb$next[0:0]$7152 $3\dbus__stb$next[0:0]$7153
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$27
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__stb$next[0:0]$7205 1'0
+ assign $3\dbus__stb$next[0:0]$7153 1'0
case
- assign $3\dbus__stb$next[0:0]$7205 \dbus__stb
+ assign $3\dbus__stb$next[0:0]$7153 \dbus__stb
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__stb$next[0:0]$7204 1'1
+ assign $2\dbus__stb$next[0:0]$7152 1'1
case
- assign $2\dbus__stb$next[0:0]$7204 \dbus__stb
+ assign $2\dbus__stb$next[0:0]$7152 \dbus__stb
end
case
- assign $1\dbus__stb$next[0:0]$7203 \dbus__stb
+ assign $1\dbus__stb$next[0:0]$7151 \dbus__stb
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__stb$next[0:0]$7206 1'0
+ assign $4\dbus__stb$next[0:0]$7154 1'0
case
- assign $4\dbus__stb$next[0:0]$7206 $1\dbus__stb$next[0:0]$7203
+ assign $4\dbus__stb$next[0:0]$7154 $1\dbus__stb$next[0:0]$7151
end
sync always
- update \dbus__stb$next $0\dbus__stb$next[0:0]$7202
+ update \dbus__stb$next $0\dbus__stb$next[0:0]$7150
end
- attribute \src "libresoc.v:147807.3-147816.6"
- process $proc$libresoc.v:147807$7207
+ attribute \src "libresoc.v:147471.3-147480.6"
+ process $proc$libresoc.v:147471$7155
assign { } { }
assign { } { }
assign $0\x_busy_o[0:0] $1\x_busy_o[0:0]
- attribute \src "libresoc.v:147808.5-147808.29"
+ attribute \src "libresoc.v:147472.5-147472.29"
switch \initial
- attribute \src "libresoc.v:147808.9-147808.17"
+ attribute \src "libresoc.v:147472.9-147472.17"
case 1'1
case
end
sync always
update \x_busy_o $0\x_busy_o[0:0]
end
- attribute \src "libresoc.v:147817.3-147834.6"
- process $proc$libresoc.v:147817$7208
+ attribute \src "libresoc.v:147481.3-147498.6"
+ process $proc$libresoc.v:147481$7156
assign { } { }
assign { } { }
assign $0\m_busy_o[0:0] $1\m_busy_o[0:0]
- attribute \src "libresoc.v:147818.5-147818.29"
+ attribute \src "libresoc.v:147482.5-147482.29"
switch \initial
- attribute \src "libresoc.v:147818.9-147818.17"
+ attribute \src "libresoc.v:147482.9-147482.17"
case 1'1
case
end
sync always
update \m_busy_o $0\m_busy_o[0:0]
end
- attribute \src "libresoc.v:147835.3-147865.6"
- process $proc$libresoc.v:147835$7209
+ attribute \src "libresoc.v:147499.3-147529.6"
+ process $proc$libresoc.v:147499$7157
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__sel$next[7:0]$7210 $4\dbus__sel$next[7:0]$7214
- attribute \src "libresoc.v:147836.5-147836.29"
+ assign $0\dbus__sel$next[7:0]$7158 $4\dbus__sel$next[7:0]$7162
+ attribute \src "libresoc.v:147500.5-147500.29"
switch \initial
- attribute \src "libresoc.v:147836.9-147836.17"
+ attribute \src "libresoc.v:147500.9-147500.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__sel$next[7:0]$7211 $2\dbus__sel$next[7:0]$7212
+ assign $1\dbus__sel$next[7:0]$7159 $2\dbus__sel$next[7:0]$7160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$35 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__sel$next[7:0]$7212 $3\dbus__sel$next[7:0]$7213
+ assign $2\dbus__sel$next[7:0]$7160 $3\dbus__sel$next[7:0]$7161
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$41
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__sel$next[7:0]$7213 8'00000000
+ assign $3\dbus__sel$next[7:0]$7161 8'00000000
case
- assign $3\dbus__sel$next[7:0]$7213 \dbus__sel
+ assign $3\dbus__sel$next[7:0]$7161 \dbus__sel
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__sel$next[7:0]$7212 \x_mask_i
+ assign $2\dbus__sel$next[7:0]$7160 \x_mask_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__sel$next[7:0]$7212 8'00000000
+ assign $2\dbus__sel$next[7:0]$7160 8'00000000
end
case
- assign $1\dbus__sel$next[7:0]$7211 \dbus__sel
+ assign $1\dbus__sel$next[7:0]$7159 \dbus__sel
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__sel$next[7:0]$7214 8'00000000
+ assign $4\dbus__sel$next[7:0]$7162 8'00000000
case
- assign $4\dbus__sel$next[7:0]$7214 $1\dbus__sel$next[7:0]$7211
+ assign $4\dbus__sel$next[7:0]$7162 $1\dbus__sel$next[7:0]$7159
end
sync always
- update \dbus__sel$next $0\dbus__sel$next[7:0]$7210
+ update \dbus__sel$next $0\dbus__sel$next[7:0]$7158
end
- attribute \src "libresoc.v:147866.3-147890.6"
- process $proc$libresoc.v:147866$7215
+ attribute \src "libresoc.v:147530.3-147554.6"
+ process $proc$libresoc.v:147530$7163
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_ld_data_o$next[63:0]$7216 $4\m_ld_data_o$next[63:0]$7220
- attribute \src "libresoc.v:147867.5-147867.29"
+ assign $0\m_ld_data_o$next[63:0]$7164 $4\m_ld_data_o$next[63:0]$7168
+ attribute \src "libresoc.v:147531.5-147531.29"
switch \initial
- attribute \src "libresoc.v:147867.9-147867.17"
+ attribute \src "libresoc.v:147531.9-147531.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_ld_data_o$next[63:0]$7217 $2\m_ld_data_o$next[63:0]$7218
+ assign $1\m_ld_data_o$next[63:0]$7165 $2\m_ld_data_o$next[63:0]$7166
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$49 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_ld_data_o$next[63:0]$7218 $3\m_ld_data_o$next[63:0]$7219
+ assign $2\m_ld_data_o$next[63:0]$7166 $3\m_ld_data_o$next[63:0]$7167
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$55
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_ld_data_o$next[63:0]$7219 \dbus__dat_r
+ assign $3\m_ld_data_o$next[63:0]$7167 \dbus__dat_r
case
- assign $3\m_ld_data_o$next[63:0]$7219 \m_ld_data_o
+ assign $3\m_ld_data_o$next[63:0]$7167 \m_ld_data_o
end
case
- assign $2\m_ld_data_o$next[63:0]$7218 \m_ld_data_o
+ assign $2\m_ld_data_o$next[63:0]$7166 \m_ld_data_o
end
case
- assign $1\m_ld_data_o$next[63:0]$7217 \m_ld_data_o
+ assign $1\m_ld_data_o$next[63:0]$7165 \m_ld_data_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\m_ld_data_o$next[63:0]$7220 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $4\m_ld_data_o$next[63:0]$7168 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $4\m_ld_data_o$next[63:0]$7220 $1\m_ld_data_o$next[63:0]$7217
+ assign $4\m_ld_data_o$next[63:0]$7168 $1\m_ld_data_o$next[63:0]$7165
end
sync always
- update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7216
+ update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7164
end
- attribute \src "libresoc.v:147891.3-147916.6"
- process $proc$libresoc.v:147891$7221
+ attribute \src "libresoc.v:147555.3-147580.6"
+ process $proc$libresoc.v:147555$7169
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__adr$next[44:0]$7222 $3\dbus__adr$next[44:0]$7225
- attribute \src "libresoc.v:147892.5-147892.29"
+ assign $0\dbus__adr$next[44:0]$7170 $3\dbus__adr$next[44:0]$7173
+ attribute \src "libresoc.v:147556.5-147556.29"
switch \initial
- attribute \src "libresoc.v:147892.9-147892.17"
+ attribute \src "libresoc.v:147556.9-147556.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__adr$next[44:0]$7223 $2\dbus__adr$next[44:0]$7224
+ assign $1\dbus__adr$next[44:0]$7171 $2\dbus__adr$next[44:0]$7172
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$63 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__adr$next[44:0]$7224 \dbus__adr
+ assign $2\dbus__adr$next[44:0]$7172 \dbus__adr
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__adr$next[44:0]$7224 \x_addr_i [47:3]
+ assign $2\dbus__adr$next[44:0]$7172 \x_addr_i [47:3]
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__adr$next[44:0]$7224 45'000000000000000000000000000000000000000000000
+ assign $2\dbus__adr$next[44:0]$7172 45'000000000000000000000000000000000000000000000
end
case
- assign $1\dbus__adr$next[44:0]$7223 \dbus__adr
+ assign $1\dbus__adr$next[44:0]$7171 \dbus__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__adr$next[44:0]$7225 45'000000000000000000000000000000000000000000000
+ assign $3\dbus__adr$next[44:0]$7173 45'000000000000000000000000000000000000000000000
case
- assign $3\dbus__adr$next[44:0]$7225 $1\dbus__adr$next[44:0]$7223
+ assign $3\dbus__adr$next[44:0]$7173 $1\dbus__adr$next[44:0]$7171
end
sync always
- update \dbus__adr$next $0\dbus__adr$next[44:0]$7222
+ update \dbus__adr$next $0\dbus__adr$next[44:0]$7170
end
- attribute \src "libresoc.v:147917.3-147942.6"
- process $proc$libresoc.v:147917$7226
+ attribute \src "libresoc.v:147581.3-147606.6"
+ process $proc$libresoc.v:147581$7174
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__we$next[0:0]$7227 $3\dbus__we$next[0:0]$7230
- attribute \src "libresoc.v:147918.5-147918.29"
+ assign $0\dbus__we$next[0:0]$7175 $3\dbus__we$next[0:0]$7178
+ attribute \src "libresoc.v:147582.5-147582.29"
switch \initial
- attribute \src "libresoc.v:147918.9-147918.17"
+ attribute \src "libresoc.v:147582.9-147582.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__we$next[0:0]$7228 $2\dbus__we$next[0:0]$7229
+ assign $1\dbus__we$next[0:0]$7176 $2\dbus__we$next[0:0]$7177
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$71 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__we$next[0:0]$7229 \dbus__we
+ assign $2\dbus__we$next[0:0]$7177 \dbus__we
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__we$next[0:0]$7229 \x_st_i
+ assign $2\dbus__we$next[0:0]$7177 \x_st_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__we$next[0:0]$7229 1'0
+ assign $2\dbus__we$next[0:0]$7177 1'0
end
case
- assign $1\dbus__we$next[0:0]$7228 \dbus__we
+ assign $1\dbus__we$next[0:0]$7176 \dbus__we
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__we$next[0:0]$7230 1'0
+ assign $3\dbus__we$next[0:0]$7178 1'0
case
- assign $3\dbus__we$next[0:0]$7230 $1\dbus__we$next[0:0]$7228
+ assign $3\dbus__we$next[0:0]$7178 $1\dbus__we$next[0:0]$7176
end
sync always
- update \dbus__we$next $0\dbus__we$next[0:0]$7227
+ update \dbus__we$next $0\dbus__we$next[0:0]$7175
end
- attribute \src "libresoc.v:147943.3-147968.6"
- process $proc$libresoc.v:147943$7231
+ attribute \src "libresoc.v:147607.3-147632.6"
+ process $proc$libresoc.v:147607$7179
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__dat_w$next[63:0]$7232 $3\dbus__dat_w$next[63:0]$7235
- attribute \src "libresoc.v:147944.5-147944.29"
+ assign $0\dbus__dat_w$next[63:0]$7180 $3\dbus__dat_w$next[63:0]$7183
+ attribute \src "libresoc.v:147608.5-147608.29"
switch \initial
- attribute \src "libresoc.v:147944.9-147944.17"
+ attribute \src "libresoc.v:147608.9-147608.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__dat_w$next[63:0]$7233 $2\dbus__dat_w$next[63:0]$7234
+ assign $1\dbus__dat_w$next[63:0]$7181 $2\dbus__dat_w$next[63:0]$7182
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$79 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__dat_w$next[63:0]$7234 \dbus__dat_w
+ assign $2\dbus__dat_w$next[63:0]$7182 \dbus__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__dat_w$next[63:0]$7234 \x_st_data_i
+ assign $2\dbus__dat_w$next[63:0]$7182 \x_st_data_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__dat_w$next[63:0]$7234 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dbus__dat_w$next[63:0]$7182 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $1\dbus__dat_w$next[63:0]$7233 \dbus__dat_w
+ assign $1\dbus__dat_w$next[63:0]$7181 \dbus__dat_w
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__dat_w$next[63:0]$7235 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dbus__dat_w$next[63:0]$7183 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dbus__dat_w$next[63:0]$7235 $1\dbus__dat_w$next[63:0]$7233
+ assign $3\dbus__dat_w$next[63:0]$7183 $1\dbus__dat_w$next[63:0]$7181
end
sync always
- update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7232
+ update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7180
end
- attribute \src "libresoc.v:147969.3-147991.6"
- process $proc$libresoc.v:147969$7236
+ attribute \src "libresoc.v:147633.3-147655.6"
+ process $proc$libresoc.v:147633$7184
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_load_err_o$next[0:0]$7237 $3\m_load_err_o$next[0:0]$7240
- attribute \src "libresoc.v:147970.5-147970.29"
+ assign $0\m_load_err_o$next[0:0]$7185 $3\m_load_err_o$next[0:0]$7188
+ attribute \src "libresoc.v:147634.5-147634.29"
switch \initial
- attribute \src "libresoc.v:147970.9-147970.17"
+ attribute \src "libresoc.v:147634.9-147634.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_load_err_o$next[0:0]$7238 $2\m_load_err_o$next[0:0]$7239
+ assign $1\m_load_err_o$next[0:0]$7186 $2\m_load_err_o$next[0:0]$7187
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$83 \$81 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_load_err_o$next[0:0]$7239 \$85
+ assign $2\m_load_err_o$next[0:0]$7187 \$85
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\m_load_err_o$next[0:0]$7239 1'0
+ assign $2\m_load_err_o$next[0:0]$7187 1'0
case
- assign $2\m_load_err_o$next[0:0]$7239 \m_load_err_o
+ assign $2\m_load_err_o$next[0:0]$7187 \m_load_err_o
end
case
- assign $1\m_load_err_o$next[0:0]$7238 \m_load_err_o
+ assign $1\m_load_err_o$next[0:0]$7186 \m_load_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_load_err_o$next[0:0]$7240 1'0
+ assign $3\m_load_err_o$next[0:0]$7188 1'0
case
- assign $3\m_load_err_o$next[0:0]$7240 $1\m_load_err_o$next[0:0]$7238
+ assign $3\m_load_err_o$next[0:0]$7188 $1\m_load_err_o$next[0:0]$7186
end
sync always
- update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7237
+ update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7185
end
- attribute \src "libresoc.v:147992.3-148014.6"
- process $proc$libresoc.v:147992$7241
+ attribute \src "libresoc.v:147656.3-147678.6"
+ process $proc$libresoc.v:147656$7189
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_store_err_o$next[0:0]$7242 $3\m_store_err_o$next[0:0]$7245
- attribute \src "libresoc.v:147993.5-147993.29"
+ assign $0\m_store_err_o$next[0:0]$7190 $3\m_store_err_o$next[0:0]$7193
+ attribute \src "libresoc.v:147657.5-147657.29"
switch \initial
- attribute \src "libresoc.v:147993.9-147993.17"
+ attribute \src "libresoc.v:147657.9-147657.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_store_err_o$next[0:0]$7243 $2\m_store_err_o$next[0:0]$7244
+ assign $1\m_store_err_o$next[0:0]$7191 $2\m_store_err_o$next[0:0]$7192
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$89 \$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_store_err_o$next[0:0]$7244 \dbus__we
+ assign $2\m_store_err_o$next[0:0]$7192 \dbus__we
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\m_store_err_o$next[0:0]$7244 1'0
+ assign $2\m_store_err_o$next[0:0]$7192 1'0
case
- assign $2\m_store_err_o$next[0:0]$7244 \m_store_err_o
+ assign $2\m_store_err_o$next[0:0]$7192 \m_store_err_o
end
case
- assign $1\m_store_err_o$next[0:0]$7243 \m_store_err_o
+ assign $1\m_store_err_o$next[0:0]$7191 \m_store_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_store_err_o$next[0:0]$7245 1'0
+ assign $3\m_store_err_o$next[0:0]$7193 1'0
case
- assign $3\m_store_err_o$next[0:0]$7245 $1\m_store_err_o$next[0:0]$7243
+ assign $3\m_store_err_o$next[0:0]$7193 $1\m_store_err_o$next[0:0]$7191
end
sync always
- update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7242
+ update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7190
end
- attribute \src "libresoc.v:148015.3-148034.6"
- process $proc$libresoc.v:148015$7246
+ attribute \src "libresoc.v:147679.3-147698.6"
+ process $proc$libresoc.v:147679$7194
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_badaddr_o$next[44:0]$7247 $3\m_badaddr_o$next[44:0]$7250
- attribute \src "libresoc.v:148016.5-148016.29"
+ assign $0\m_badaddr_o$next[44:0]$7195 $3\m_badaddr_o$next[44:0]$7198
+ attribute \src "libresoc.v:147680.5-147680.29"
switch \initial
- attribute \src "libresoc.v:148016.9-148016.17"
+ attribute \src "libresoc.v:147680.9-147680.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_badaddr_o$next[44:0]$7248 $2\m_badaddr_o$next[44:0]$7249
+ assign $1\m_badaddr_o$next[44:0]$7196 $2\m_badaddr_o$next[44:0]$7197
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$93 \$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_badaddr_o$next[44:0]$7249 \dbus__adr
+ assign $2\m_badaddr_o$next[44:0]$7197 \dbus__adr
case
- assign $2\m_badaddr_o$next[44:0]$7249 \m_badaddr_o
+ assign $2\m_badaddr_o$next[44:0]$7197 \m_badaddr_o
end
case
- assign $1\m_badaddr_o$next[44:0]$7248 \m_badaddr_o
+ assign $1\m_badaddr_o$next[44:0]$7196 \m_badaddr_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_badaddr_o$next[44:0]$7250 45'000000000000000000000000000000000000000000000
- case
- assign $3\m_badaddr_o$next[44:0]$7250 $1\m_badaddr_o$next[44:0]$7248
- end
- sync always
- update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7247
- end
- connect \$9 $or$libresoc.v:147683$7137_Y
- connect \$11 $not$libresoc.v:147684$7138_Y
- connect \$13 $or$libresoc.v:147685$7139_Y
- connect \$15 $or$libresoc.v:147686$7140_Y
- connect \$17 $and$libresoc.v:147687$7141_Y
- connect \$1 $or$libresoc.v:147688$7142_Y
- connect \$19 $not$libresoc.v:147689$7143_Y
- connect \$21 $and$libresoc.v:147690$7144_Y
- connect \$23 $or$libresoc.v:147691$7145_Y
- connect \$25 $not$libresoc.v:147692$7146_Y
- connect \$27 $or$libresoc.v:147693$7147_Y
- connect \$29 $or$libresoc.v:147694$7148_Y
- connect \$31 $and$libresoc.v:147695$7149_Y
- connect \$33 $not$libresoc.v:147696$7150_Y
- connect \$35 $and$libresoc.v:147697$7151_Y
- connect \$37 $or$libresoc.v:147698$7152_Y
- connect \$3 $and$libresoc.v:147699$7153_Y
- connect \$39 $not$libresoc.v:147700$7154_Y
- connect \$41 $or$libresoc.v:147701$7155_Y
- connect \$43 $or$libresoc.v:147702$7156_Y
- connect \$45 $and$libresoc.v:147703$7157_Y
- connect \$47 $not$libresoc.v:147704$7158_Y
- connect \$49 $and$libresoc.v:147705$7159_Y
- connect \$51 $or$libresoc.v:147706$7160_Y
- connect \$53 $not$libresoc.v:147707$7161_Y
- connect \$55 $or$libresoc.v:147708$7162_Y
- connect \$57 $or$libresoc.v:147709$7163_Y
- connect \$5 $not$libresoc.v:147710$7164_Y
- connect \$59 $and$libresoc.v:147711$7165_Y
- connect \$61 $not$libresoc.v:147712$7166_Y
- connect \$63 $and$libresoc.v:147713$7167_Y
- connect \$65 $or$libresoc.v:147714$7168_Y
- connect \$67 $and$libresoc.v:147715$7169_Y
- connect \$69 $not$libresoc.v:147716$7170_Y
- connect \$71 $and$libresoc.v:147717$7171_Y
- connect \$73 $or$libresoc.v:147718$7172_Y
- connect \$75 $and$libresoc.v:147719$7173_Y
- connect \$77 $not$libresoc.v:147720$7174_Y
- connect \$7 $and$libresoc.v:147721$7175_Y
- connect \$79 $and$libresoc.v:147722$7176_Y
- connect \$81 $and$libresoc.v:147723$7177_Y
- connect \$83 $not$libresoc.v:147724$7178_Y
- connect \$85 $not$libresoc.v:147725$7179_Y
- connect \$87 $and$libresoc.v:147726$7180_Y
- connect \$89 $not$libresoc.v:147727$7181_Y
- connect \$91 $and$libresoc.v:147728$7182_Y
- connect \$93 $not$libresoc.v:147729$7183_Y
- connect \$95 $or$libresoc.v:147730$7184_Y
+ assign $3\m_badaddr_o$next[44:0]$7198 45'000000000000000000000000000000000000000000000
+ case
+ assign $3\m_badaddr_o$next[44:0]$7198 $1\m_badaddr_o$next[44:0]$7196
+ end
+ sync always
+ update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7195
+ end
+ connect \$9 $or$libresoc.v:147347$7085_Y
+ connect \$11 $not$libresoc.v:147348$7086_Y
+ connect \$13 $or$libresoc.v:147349$7087_Y
+ connect \$15 $or$libresoc.v:147350$7088_Y
+ connect \$17 $and$libresoc.v:147351$7089_Y
+ connect \$1 $or$libresoc.v:147352$7090_Y
+ connect \$19 $not$libresoc.v:147353$7091_Y
+ connect \$21 $and$libresoc.v:147354$7092_Y
+ connect \$23 $or$libresoc.v:147355$7093_Y
+ connect \$25 $not$libresoc.v:147356$7094_Y
+ connect \$27 $or$libresoc.v:147357$7095_Y
+ connect \$29 $or$libresoc.v:147358$7096_Y
+ connect \$31 $and$libresoc.v:147359$7097_Y
+ connect \$33 $not$libresoc.v:147360$7098_Y
+ connect \$35 $and$libresoc.v:147361$7099_Y
+ connect \$37 $or$libresoc.v:147362$7100_Y
+ connect \$3 $and$libresoc.v:147363$7101_Y
+ connect \$39 $not$libresoc.v:147364$7102_Y
+ connect \$41 $or$libresoc.v:147365$7103_Y
+ connect \$43 $or$libresoc.v:147366$7104_Y
+ connect \$45 $and$libresoc.v:147367$7105_Y
+ connect \$47 $not$libresoc.v:147368$7106_Y
+ connect \$49 $and$libresoc.v:147369$7107_Y
+ connect \$51 $or$libresoc.v:147370$7108_Y
+ connect \$53 $not$libresoc.v:147371$7109_Y
+ connect \$55 $or$libresoc.v:147372$7110_Y
+ connect \$57 $or$libresoc.v:147373$7111_Y
+ connect \$5 $not$libresoc.v:147374$7112_Y
+ connect \$59 $and$libresoc.v:147375$7113_Y
+ connect \$61 $not$libresoc.v:147376$7114_Y
+ connect \$63 $and$libresoc.v:147377$7115_Y
+ connect \$65 $or$libresoc.v:147378$7116_Y
+ connect \$67 $and$libresoc.v:147379$7117_Y
+ connect \$69 $not$libresoc.v:147380$7118_Y
+ connect \$71 $and$libresoc.v:147381$7119_Y
+ connect \$73 $or$libresoc.v:147382$7120_Y
+ connect \$75 $and$libresoc.v:147383$7121_Y
+ connect \$77 $not$libresoc.v:147384$7122_Y
+ connect \$7 $and$libresoc.v:147385$7123_Y
+ connect \$79 $and$libresoc.v:147386$7124_Y
+ connect \$81 $and$libresoc.v:147387$7125_Y
+ connect \$83 $not$libresoc.v:147388$7126_Y
+ connect \$85 $not$libresoc.v:147389$7127_Y
+ connect \$87 $and$libresoc.v:147390$7128_Y
+ connect \$89 $not$libresoc.v:147391$7129_Y
+ connect \$91 $and$libresoc.v:147392$7130_Y
+ connect \$93 $not$libresoc.v:147393$7131_Y
+ connect \$95 $or$libresoc.v:147394$7132_Y
connect \x_stall_i 1'0
connect \m_stall_i 1'0
end
-attribute \src "libresoc.v:148041.1-149074.10"
+attribute \src "libresoc.v:147705.1-148738.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main"
attribute \generator "nMigen"
module \main
- attribute \src "libresoc.v:148574.3-148596.6"
+ attribute \src "libresoc.v:148238.3-148260.6"
wire width 64 $0\a_i[63:0]
- attribute \src "libresoc.v:148673.3-148699.6"
+ attribute \src "libresoc.v:148337.3-148363.6"
wire $0\a_lt[0:0]
- attribute \src "libresoc.v:149026.3-149036.6"
+ attribute \src "libresoc.v:148690.3-148700.6"
wire width 64 $0\a_n[63:0]
- attribute \src "libresoc.v:148996.3-149005.6"
+ attribute \src "libresoc.v:148660.3-148669.6"
wire width 66 $0\add_a[65:0]
- attribute \src "libresoc.v:149006.3-149015.6"
+ attribute \src "libresoc.v:148670.3-148679.6"
wire width 66 $0\add_b[65:0]
- attribute \src "libresoc.v:149016.3-149025.6"
+ attribute \src "libresoc.v:148680.3-148689.6"
wire width 66 $0\add_o[65:0]
- attribute \src "libresoc.v:148840.3-148862.6"
+ attribute \src "libresoc.v:148504.3-148526.6"
wire width 64 $0\b_i[63:0]
- attribute \src "libresoc.v:148822.3-148839.6"
+ attribute \src "libresoc.v:148486.3-148503.6"
wire width 2 $0\ca[1:0]
- attribute \src "libresoc.v:149037.3-149047.6"
+ attribute \src "libresoc.v:148701.3-148711.6"
wire $0\carry_32[0:0]
- attribute \src "libresoc.v:149048.3-149058.6"
+ attribute \src "libresoc.v:148712.3-148722.6"
wire $0\carry_64[0:0]
- attribute \src "libresoc.v:148700.3-148733.6"
+ attribute \src "libresoc.v:148364.3-148397.6"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:148734.3-148756.6"
+ attribute \src "libresoc.v:148398.3-148420.6"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:148964.3-148995.6"
+ attribute \src "libresoc.v:148628.3-148659.6"
wire width 8 $0\eqs[7:0]
- attribute \src "libresoc.v:148042.7-148042.20"
+ attribute \src "libresoc.v:147706.7-147706.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:148564.3-148573.6"
+ attribute \src "libresoc.v:148228.3-148237.6"
wire $0\is_32bit[0:0]
- attribute \src "libresoc.v:148635.3-148653.6"
+ attribute \src "libresoc.v:148299.3-148317.6"
wire $0\msb_a[0:0]
- attribute \src "libresoc.v:148654.3-148672.6"
+ attribute \src "libresoc.v:148318.3-148336.6"
wire $0\msb_b[0:0]
- attribute \src "libresoc.v:148757.3-148798.6"
+ attribute \src "libresoc.v:148421.3-148462.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:148799.3-148821.6"
+ attribute \src "libresoc.v:148463.3-148485.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:148893.3-148910.6"
+ attribute \src "libresoc.v:148557.3-148574.6"
wire width 2 $0\ov[1:0]
- attribute \src "libresoc.v:148941.3-148963.6"
+ attribute \src "libresoc.v:148605.3-148627.6"
wire width 8 $0\src1[7:0]
- attribute \src "libresoc.v:148608.3-148634.6"
+ attribute \src "libresoc.v:148272.3-148298.6"
wire width 5 $0\tval[4:0]
- attribute \src "libresoc.v:148863.3-148877.6"
- wire width 2 $0\xer_ca$20[1:0]$7337
- attribute \src "libresoc.v:148878.3-148892.6"
+ attribute \src "libresoc.v:148527.3-148541.6"
+ wire width 2 $0\xer_ca$20[1:0]$7285
+ attribute \src "libresoc.v:148542.3-148556.6"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:148911.3-148925.6"
+ attribute \src "libresoc.v:148575.3-148589.6"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:148926.3-148940.6"
+ attribute \src "libresoc.v:148590.3-148604.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:148597.3-148607.6"
+ attribute \src "libresoc.v:148261.3-148271.6"
wire $0\zerohi[0:0]
- attribute \src "libresoc.v:149059.3-149069.6"
+ attribute \src "libresoc.v:148723.3-148733.6"
wire $0\zerolo[0:0]
- attribute \src "libresoc.v:148574.3-148596.6"
+ attribute \src "libresoc.v:148238.3-148260.6"
wire width 64 $1\a_i[63:0]
- attribute \src "libresoc.v:148673.3-148699.6"
+ attribute \src "libresoc.v:148337.3-148363.6"
wire $1\a_lt[0:0]
- attribute \src "libresoc.v:149026.3-149036.6"
+ attribute \src "libresoc.v:148690.3-148700.6"
wire width 64 $1\a_n[63:0]
- attribute \src "libresoc.v:148996.3-149005.6"
+ attribute \src "libresoc.v:148660.3-148669.6"
wire width 66 $1\add_a[65:0]
- attribute \src "libresoc.v:149006.3-149015.6"
+ attribute \src "libresoc.v:148670.3-148679.6"
wire width 66 $1\add_b[65:0]
- attribute \src "libresoc.v:149016.3-149025.6"
+ attribute \src "libresoc.v:148680.3-148689.6"
wire width 66 $1\add_o[65:0]
- attribute \src "libresoc.v:148840.3-148862.6"
+ attribute \src "libresoc.v:148504.3-148526.6"
wire width 64 $1\b_i[63:0]
- attribute \src "libresoc.v:148822.3-148839.6"
+ attribute \src "libresoc.v:148486.3-148503.6"
wire width 2 $1\ca[1:0]
- attribute \src "libresoc.v:149037.3-149047.6"
+ attribute \src "libresoc.v:148701.3-148711.6"
wire $1\carry_32[0:0]
- attribute \src "libresoc.v:149048.3-149058.6"
+ attribute \src "libresoc.v:148712.3-148722.6"
wire $1\carry_64[0:0]
- attribute \src "libresoc.v:148700.3-148733.6"
+ attribute \src "libresoc.v:148364.3-148397.6"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:148734.3-148756.6"
+ attribute \src "libresoc.v:148398.3-148420.6"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:148964.3-148995.6"
+ attribute \src "libresoc.v:148628.3-148659.6"
wire width 8 $1\eqs[7:0]
- attribute \src "libresoc.v:148564.3-148573.6"
+ attribute \src "libresoc.v:148228.3-148237.6"
wire $1\is_32bit[0:0]
- attribute \src "libresoc.v:148635.3-148653.6"
+ attribute \src "libresoc.v:148299.3-148317.6"
wire $1\msb_a[0:0]
- attribute \src "libresoc.v:148654.3-148672.6"
+ attribute \src "libresoc.v:148318.3-148336.6"
wire $1\msb_b[0:0]
- attribute \src "libresoc.v:148757.3-148798.6"
+ attribute \src "libresoc.v:148421.3-148462.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:148799.3-148821.6"
+ attribute \src "libresoc.v:148463.3-148485.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:148893.3-148910.6"
+ attribute \src "libresoc.v:148557.3-148574.6"
wire width 2 $1\ov[1:0]
- attribute \src "libresoc.v:148941.3-148963.6"
+ attribute \src "libresoc.v:148605.3-148627.6"
wire width 8 $1\src1[7:0]
- attribute \src "libresoc.v:148608.3-148634.6"
+ attribute \src "libresoc.v:148272.3-148298.6"
wire width 5 $1\tval[4:0]
- attribute \src "libresoc.v:148863.3-148877.6"
- wire width 2 $1\xer_ca$20[1:0]$7338
- attribute \src "libresoc.v:148878.3-148892.6"
+ attribute \src "libresoc.v:148527.3-148541.6"
+ wire width 2 $1\xer_ca$20[1:0]$7286
+ attribute \src "libresoc.v:148542.3-148556.6"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:148911.3-148925.6"
+ attribute \src "libresoc.v:148575.3-148589.6"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:148926.3-148940.6"
+ attribute \src "libresoc.v:148590.3-148604.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:148597.3-148607.6"
+ attribute \src "libresoc.v:148261.3-148271.6"
wire $1\zerohi[0:0]
- attribute \src "libresoc.v:149059.3-149069.6"
+ attribute \src "libresoc.v:148723.3-148733.6"
wire $1\zerolo[0:0]
- attribute \src "libresoc.v:148574.3-148596.6"
+ attribute \src "libresoc.v:148238.3-148260.6"
wire width 64 $2\a_i[63:0]
- attribute \src "libresoc.v:148673.3-148699.6"
+ attribute \src "libresoc.v:148337.3-148363.6"
wire $2\a_lt[0:0]
- attribute \src "libresoc.v:148840.3-148862.6"
+ attribute \src "libresoc.v:148504.3-148526.6"
wire width 64 $2\b_i[63:0]
- attribute \src "libresoc.v:148700.3-148733.6"
+ attribute \src "libresoc.v:148364.3-148397.6"
wire width 2 $2\cr_a[3:2]
- attribute \src "libresoc.v:148635.3-148653.6"
+ attribute \src "libresoc.v:148299.3-148317.6"
wire $2\msb_a[0:0]
- attribute \src "libresoc.v:148654.3-148672.6"
+ attribute \src "libresoc.v:148318.3-148336.6"
wire $2\msb_b[0:0]
- attribute \src "libresoc.v:148757.3-148798.6"
+ attribute \src "libresoc.v:148421.3-148462.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:148608.3-148634.6"
+ attribute \src "libresoc.v:148272.3-148298.6"
wire width 5 $2\tval[4:0]
- attribute \src "libresoc.v:148673.3-148699.6"
+ attribute \src "libresoc.v:148337.3-148363.6"
wire $3\a_lt[0:0]
- attribute \src "libresoc.v:148757.3-148798.6"
+ attribute \src "libresoc.v:148421.3-148462.6"
wire width 64 $3\o[63:0]
- attribute \src "libresoc.v:148608.3-148634.6"
+ attribute \src "libresoc.v:148272.3-148298.6"
wire width 5 $3\tval[4:0]
- attribute \src "libresoc.v:148757.3-148798.6"
+ attribute \src "libresoc.v:148421.3-148462.6"
wire width 64 $4\o[63:0]
- attribute \src "libresoc.v:148539.18-148539.105"
- wire width 67 $add$libresoc.v:148539$7298_Y
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- wire $and$libresoc.v:148513$7272_Y
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- wire $and$libresoc.v:148517$7276_Y
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- wire $and$libresoc.v:148550$7309_Y
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- wire $and$libresoc.v:148555$7314_Y
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- wire $and$libresoc.v:148558$7317_Y
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- wire $and$libresoc.v:148561$7320_Y
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- wire $eq$libresoc.v:148504$7263_Y
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- wire $eq$libresoc.v:148505$7264_Y
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- wire $eq$libresoc.v:148506$7265_Y
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- wire $eq$libresoc.v:148518$7277_Y
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- wire $eq$libresoc.v:148519$7278_Y
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- wire $eq$libresoc.v:148520$7279_Y
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- wire $eq$libresoc.v:148521$7280_Y
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- wire $eq$libresoc.v:148522$7281_Y
- attribute \src "libresoc.v:148523.19-148523.111"
- wire $eq$libresoc.v:148523$7282_Y
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- wire $eq$libresoc.v:148524$7283_Y
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- wire $eq$libresoc.v:148525$7284_Y
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- wire $eq$libresoc.v:148526$7285_Y
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- wire $eq$libresoc.v:148528$7287_Y
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- wire $eq$libresoc.v:148529$7288_Y
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- wire $eq$libresoc.v:148530$7289_Y
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- wire $eq$libresoc.v:148531$7290_Y
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- wire $eq$libresoc.v:148533$7292_Y
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- wire $eq$libresoc.v:148534$7293_Y
- attribute \src "libresoc.v:148536.18-148536.118"
- wire $eq$libresoc.v:148536$7295_Y
- attribute \src "libresoc.v:148537.18-148537.118"
- wire $eq$libresoc.v:148537$7296_Y
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- wire $ne$libresoc.v:148551$7310_Y
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- wire $ne$libresoc.v:148562$7321_Y
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- wire $not$libresoc.v:148512$7271_Y
- attribute \src "libresoc.v:148516.19-148516.100"
- wire $not$libresoc.v:148516$7275_Y
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- wire $not$libresoc.v:148527$7286_Y
- attribute \src "libresoc.v:148540.18-148540.97"
- wire width 64 $not$libresoc.v:148540$7299_Y
- attribute \src "libresoc.v:148545.18-148545.99"
- wire $not$libresoc.v:148545$7304_Y
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- wire $not$libresoc.v:148548$7307_Y
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- wire $not$libresoc.v:148552$7311_Y
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- wire $not$libresoc.v:148553$7312_Y
- attribute \src "libresoc.v:148532.18-148532.104"
- wire $or$libresoc.v:148532$7291_Y
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- wire $or$libresoc.v:148535$7294_Y
- attribute \src "libresoc.v:148538.18-148538.104"
- wire $or$libresoc.v:148538$7297_Y
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- wire $or$libresoc.v:148549$7308_Y
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- wire $or$libresoc.v:148554$7313_Y
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- wire $or$libresoc.v:148557$7316_Y
- attribute \src "libresoc.v:148560.18-148560.110"
- wire $or$libresoc.v:148560$7319_Y
- attribute \src "libresoc.v:148503.18-148503.98"
- wire $reduce_or$libresoc.v:148503$7262_Y
- attribute \src "libresoc.v:148507.19-148507.99"
- wire $reduce_or$libresoc.v:148507$7266_Y
- attribute \src "libresoc.v:148544.18-148544.99"
- wire $reduce_or$libresoc.v:148544$7303_Y
- attribute \src "libresoc.v:148547.18-148547.99"
- wire $reduce_or$libresoc.v:148547$7306_Y
- attribute \src "libresoc.v:148556.18-148556.121"
- wire $ternary$libresoc.v:148556$7315_Y
- attribute \src "libresoc.v:148559.18-148559.119"
- wire $ternary$libresoc.v:148559$7318_Y
- attribute \src "libresoc.v:148563.18-148563.123"
- wire $ternary$libresoc.v:148563$7322_Y
- attribute \src "libresoc.v:148508.19-148508.111"
- wire $xor$libresoc.v:148508$7267_Y
- attribute \src "libresoc.v:148509.19-148509.111"
- wire $xor$libresoc.v:148509$7268_Y
- attribute \src "libresoc.v:148510.19-148510.110"
- wire $xor$libresoc.v:148510$7269_Y
- attribute \src "libresoc.v:148511.19-148511.110"
- wire $xor$libresoc.v:148511$7270_Y
- attribute \src "libresoc.v:148514.19-148514.110"
- wire $xor$libresoc.v:148514$7273_Y
- attribute \src "libresoc.v:148515.19-148515.110"
- wire $xor$libresoc.v:148515$7274_Y
- attribute \src "libresoc.v:148541.18-148541.111"
- wire $xor$libresoc.v:148541$7300_Y
- attribute \src "libresoc.v:148542.18-148542.107"
- wire $xor$libresoc.v:148542$7301_Y
- attribute \src "libresoc.v:148543.18-148543.113"
- wire width 32 $xor$libresoc.v:148543$7302_Y
- attribute \src "libresoc.v:148546.18-148546.115"
- wire width 32 $xor$libresoc.v:148546$7305_Y
+ attribute \src "libresoc.v:148203.18-148203.105"
+ wire width 67 $add$libresoc.v:148203$7246_Y
+ attribute \src "libresoc.v:148177.19-148177.107"
+ wire $and$libresoc.v:148177$7220_Y
+ attribute \src "libresoc.v:148181.19-148181.107"
+ wire $and$libresoc.v:148181$7224_Y
+ attribute \src "libresoc.v:148214.18-148214.106"
+ wire $and$libresoc.v:148214$7257_Y
+ attribute \src "libresoc.v:148219.18-148219.106"
+ wire $and$libresoc.v:148219$7262_Y
+ attribute \src "libresoc.v:148222.18-148222.106"
+ wire $and$libresoc.v:148222$7265_Y
+ attribute \src "libresoc.v:148225.18-148225.106"
+ wire $and$libresoc.v:148225$7268_Y
+ attribute \src "libresoc.v:148168.19-148168.118"
+ wire $eq$libresoc.v:148168$7211_Y
+ attribute \src "libresoc.v:148169.19-148169.118"
+ wire $eq$libresoc.v:148169$7212_Y
+ attribute \src "libresoc.v:148170.19-148170.118"
+ wire $eq$libresoc.v:148170$7213_Y
+ attribute \src "libresoc.v:148182.19-148182.109"
+ wire $eq$libresoc.v:148182$7225_Y
+ attribute \src "libresoc.v:148183.19-148183.110"
+ wire $eq$libresoc.v:148183$7226_Y
+ attribute \src "libresoc.v:148184.19-148184.111"
+ wire $eq$libresoc.v:148184$7227_Y
+ attribute \src "libresoc.v:148185.19-148185.111"
+ wire $eq$libresoc.v:148185$7228_Y
+ attribute \src "libresoc.v:148186.19-148186.111"
+ wire $eq$libresoc.v:148186$7229_Y
+ attribute \src "libresoc.v:148187.19-148187.111"
+ wire $eq$libresoc.v:148187$7230_Y
+ attribute \src "libresoc.v:148188.19-148188.111"
+ wire $eq$libresoc.v:148188$7231_Y
+ attribute \src "libresoc.v:148189.19-148189.111"
+ wire $eq$libresoc.v:148189$7232_Y
+ attribute \src "libresoc.v:148190.18-148190.118"
+ wire $eq$libresoc.v:148190$7233_Y
+ attribute \src "libresoc.v:148192.18-148192.118"
+ wire $eq$libresoc.v:148192$7235_Y
+ attribute \src "libresoc.v:148193.18-148193.118"
+ wire $eq$libresoc.v:148193$7236_Y
+ attribute \src "libresoc.v:148194.18-148194.118"
+ wire $eq$libresoc.v:148194$7237_Y
+ attribute \src "libresoc.v:148195.18-148195.118"
+ wire $eq$libresoc.v:148195$7238_Y
+ attribute \src "libresoc.v:148197.18-148197.118"
+ wire $eq$libresoc.v:148197$7240_Y
+ attribute \src "libresoc.v:148198.18-148198.118"
+ wire $eq$libresoc.v:148198$7241_Y
+ attribute \src "libresoc.v:148200.18-148200.118"
+ wire $eq$libresoc.v:148200$7243_Y
+ attribute \src "libresoc.v:148201.18-148201.118"
+ wire $eq$libresoc.v:148201$7244_Y
+ attribute \src "libresoc.v:148215.18-148215.107"
+ wire $ne$libresoc.v:148215$7258_Y
+ attribute \src "libresoc.v:148226.18-148226.107"
+ wire $ne$libresoc.v:148226$7269_Y
+ attribute \src "libresoc.v:148176.19-148176.100"
+ wire $not$libresoc.v:148176$7219_Y
+ attribute \src "libresoc.v:148180.19-148180.100"
+ wire $not$libresoc.v:148180$7223_Y
+ attribute \src "libresoc.v:148191.18-148191.110"
+ wire $not$libresoc.v:148191$7234_Y
+ attribute \src "libresoc.v:148204.18-148204.97"
+ wire width 64 $not$libresoc.v:148204$7247_Y
+ attribute \src "libresoc.v:148209.18-148209.99"
+ wire $not$libresoc.v:148209$7252_Y
+ attribute \src "libresoc.v:148212.18-148212.99"
+ wire $not$libresoc.v:148212$7255_Y
+ attribute \src "libresoc.v:148216.18-148216.99"
+ wire $not$libresoc.v:148216$7259_Y
+ attribute \src "libresoc.v:148217.18-148217.99"
+ wire $not$libresoc.v:148217$7260_Y
+ attribute \src "libresoc.v:148196.18-148196.104"
+ wire $or$libresoc.v:148196$7239_Y
+ attribute \src "libresoc.v:148199.18-148199.104"
+ wire $or$libresoc.v:148199$7242_Y
+ attribute \src "libresoc.v:148202.18-148202.104"
+ wire $or$libresoc.v:148202$7245_Y
+ attribute \src "libresoc.v:148213.18-148213.110"
+ wire $or$libresoc.v:148213$7256_Y
+ attribute \src "libresoc.v:148218.18-148218.110"
+ wire $or$libresoc.v:148218$7261_Y
+ attribute \src "libresoc.v:148221.18-148221.110"
+ wire $or$libresoc.v:148221$7264_Y
+ attribute \src "libresoc.v:148224.18-148224.110"
+ wire $or$libresoc.v:148224$7267_Y
+ attribute \src "libresoc.v:148167.18-148167.98"
+ wire $reduce_or$libresoc.v:148167$7210_Y
+ attribute \src "libresoc.v:148171.19-148171.99"
+ wire $reduce_or$libresoc.v:148171$7214_Y
+ attribute \src "libresoc.v:148208.18-148208.99"
+ wire $reduce_or$libresoc.v:148208$7251_Y
+ attribute \src "libresoc.v:148211.18-148211.99"
+ wire $reduce_or$libresoc.v:148211$7254_Y
+ attribute \src "libresoc.v:148220.18-148220.121"
+ wire $ternary$libresoc.v:148220$7263_Y
+ attribute \src "libresoc.v:148223.18-148223.119"
+ wire $ternary$libresoc.v:148223$7266_Y
+ attribute \src "libresoc.v:148227.18-148227.123"
+ wire $ternary$libresoc.v:148227$7270_Y
+ attribute \src "libresoc.v:148172.19-148172.111"
+ wire $xor$libresoc.v:148172$7215_Y
+ attribute \src "libresoc.v:148173.19-148173.111"
+ wire $xor$libresoc.v:148173$7216_Y
+ attribute \src "libresoc.v:148174.19-148174.110"
+ wire $xor$libresoc.v:148174$7217_Y
+ attribute \src "libresoc.v:148175.19-148175.110"
+ wire $xor$libresoc.v:148175$7218_Y
+ attribute \src "libresoc.v:148178.19-148178.110"
+ wire $xor$libresoc.v:148178$7221_Y
+ attribute \src "libresoc.v:148179.19-148179.110"
+ wire $xor$libresoc.v:148179$7222_Y
+ attribute \src "libresoc.v:148205.18-148205.111"
+ wire $xor$libresoc.v:148205$7248_Y
+ attribute \src "libresoc.v:148206.18-148206.107"
+ wire $xor$libresoc.v:148206$7249_Y
+ attribute \src "libresoc.v:148207.18-148207.113"
+ wire width 32 $xor$libresoc.v:148207$7250_Y
+ attribute \src "libresoc.v:148210.18-148210.115"
+ wire width 32 $xor$libresoc.v:148210$7253_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168"
wire output 45 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178"
wire width 8 \eqs
- attribute \src "libresoc.v:148042.7-148042.15"
+ attribute \src "libresoc.v:147706.7-147706.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
wire \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
wire \zerolo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86"
- cell $add $add$libresoc.v:148539$7298
+ cell $add $add$libresoc.v:148203$7246
parameter \A_SIGNED 0
parameter \A_WIDTH 66
parameter \B_SIGNED 0
parameter \Y_WIDTH 67
connect \A \add_a
connect \B \add_b
- connect \Y $add$libresoc.v:148539$7298_Y
+ connect \Y $add$libresoc.v:148203$7246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $and $and$libresoc.v:148513$7272
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
connect \A \$113
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$121
connect \B \$123
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
connect \A \zerolo
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:148555$7314
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$79
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:148558$7317
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$85
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:148561$7320
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$91
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166"
- cell $eq $eq$libresoc.v:148504$7263
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parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 1'1
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168"
- cell $eq $eq$libresoc.v:148505$7264
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parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 2'10
- connect \Y $eq$libresoc.v:148505$7264_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170"
- cell $eq $eq$libresoc.v:148506$7265
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parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 3'100
- connect \Y $eq$libresoc.v:148506$7265_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148518$7277
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148518$7277_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148519$7278
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148519$7278_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148520$7279
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148520$7279_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148521$7280
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148521$7280_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148522$7281
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148522$7281_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148523$7282
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148523$7282_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148524$7283
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148524$7283_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:148525$7284
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148525$7284_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56"
- cell $eq $eq$libresoc.v:148526$7285
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148526$7285_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67"
- cell $eq $eq$libresoc.v:148528$7287
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148528$7287_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67"
- cell $eq $eq$libresoc.v:148529$7288
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148529$7288_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:148530$7289
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:148530$7289_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:148531$7290
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148531$7290_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:148533$7292
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:148533$7292_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:148534$7293
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148534$7293_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:148536$7295
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:148536$7295_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:148537$7296
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:148537$7296_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123"
- cell $ne $ne$libresoc.v:148551$7310
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msb_a
connect \B \msb_b
- connect \Y $ne$libresoc.v:148551$7310_Y
+ connect \Y $ne$libresoc.v:148215$7258_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123"
- cell $ne $ne$libresoc.v:148562$7321
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msb_a
connect \B \msb_b
- connect \Y $ne$libresoc.v:148562$7321_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $not $not$libresoc.v:148512$7271
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$116
- connect \Y $not$libresoc.v:148512$7271_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $not $not$libresoc.v:148516$7275
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$124
- connect \Y $not$libresoc.v:148516$7275_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57"
- cell $not $not$libresoc.v:148527$7286
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_op__insn [21]
- connect \Y $not$libresoc.v:148527$7286_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
- cell $not $not$libresoc.v:148540$7299
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $not $not$libresoc.v:148545$7304
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$58
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $not $not$libresoc.v:148548$7307
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$64
- connect \Y $not$libresoc.v:148548$7307_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132"
- cell $not $not$libresoc.v:148552$7311
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_lt
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132"
- cell $not $not$libresoc.v:148553$7312
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_lt
- connect \Y $not$libresoc.v:148553$7312_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:148532$7291
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:148532$7291_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:148535$7294
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \$38
- connect \Y $or$libresoc.v:148535$7294_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:148538$7297
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B \$44
- connect \Y $or$libresoc.v:148538$7297_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:148549$7308
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:148549$7308_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:148554$7313
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:148554$7313_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:148557$7316
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:148557$7316_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:148560$7319
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:148560$7319_Y
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185"
- cell $reduce_or $reduce_or$libresoc.v:148503$7262
+ cell $reduce_or $reduce_or$libresoc.v:148167$7210
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183"
- cell $reduce_or $reduce_or$libresoc.v:148507$7266
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parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
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end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $reduce_or $reduce_or$libresoc.v:148544$7303
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parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 1
connect \A \$59
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $reduce_or $reduce_or$libresoc.v:148547$7306
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parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 1
connect \A \$65
- connect \Y $reduce_or$libresoc.v:148547$7306_Y
+ connect \Y $reduce_or$libresoc.v:148211$7254_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120"
- cell $mux $ternary$libresoc.v:148556$7315
+ cell $mux $ternary$libresoc.v:148220$7263
parameter \WIDTH 1
connect \A \a_n [63]
connect \B \a_n [31]
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:148556$7315_Y
+ connect \Y $ternary$libresoc.v:148220$7263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121"
- cell $mux $ternary$libresoc.v:148559$7318
+ cell $mux $ternary$libresoc.v:148223$7266
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:148559$7318_Y
+ connect \Y $ternary$libresoc.v:148223$7266_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131"
- cell $mux $ternary$libresoc.v:148563$7322
+ cell $mux $ternary$libresoc.v:148227$7270
parameter \WIDTH 1
connect \A \carry_64
connect \B \carry_32
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:148563$7322_Y
+ connect \Y $ternary$libresoc.v:148227$7270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152"
- cell $xor $xor$libresoc.v:148508$7267
+ cell $xor $xor$libresoc.v:148172$7215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [32]
connect \B \b_i [32]
- connect \Y $xor$libresoc.v:148508$7267_Y
+ connect \Y $xor$libresoc.v:148172$7215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152"
- cell $xor $xor$libresoc.v:148509$7268
+ cell $xor $xor$libresoc.v:148173$7216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \add_o [33]
connect \B \$109
- connect \Y $xor$libresoc.v:148509$7268_Y
+ connect \Y $xor$libresoc.v:148173$7216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:148510$7269
+ cell $xor $xor$libresoc.v:148174$7217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [0]
connect \B \add_o [64]
- connect \Y $xor$libresoc.v:148510$7269_Y
+ connect \Y $xor$libresoc.v:148174$7217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:148511$7270
+ cell $xor $xor$libresoc.v:148175$7218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [63]
connect \B \b_i [63]
- connect \Y $xor$libresoc.v:148511$7270_Y
+ connect \Y $xor$libresoc.v:148175$7218_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:148514$7273
+ cell $xor $xor$libresoc.v:148178$7221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [1]
connect \B \add_o [32]
- connect \Y $xor$libresoc.v:148514$7273_Y
+ connect \Y $xor$libresoc.v:148178$7221_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:148515$7274
+ cell $xor $xor$libresoc.v:148179$7222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [31]
connect \B \b_i [31]
- connect \Y $xor$libresoc.v:148515$7274_Y
+ connect \Y $xor$libresoc.v:148179$7222_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110"
- cell $xor $xor$libresoc.v:148541$7300
+ cell $xor $xor$libresoc.v:148205$7248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \add_o [33]
connect \B \ra [32]
- connect \Y $xor$libresoc.v:148541$7300_Y
+ connect \Y $xor$libresoc.v:148205$7248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110"
- cell $xor $xor$libresoc.v:148542$7301
+ cell $xor $xor$libresoc.v:148206$7249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \rb [32]
- connect \Y $xor$libresoc.v:148542$7301_Y
+ connect \Y $xor$libresoc.v:148206$7249_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $xor $xor$libresoc.v:148543$7302
+ cell $xor $xor$libresoc.v:148207$7250
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \a_n [31:0]
connect \B \rb [31:0]
- connect \Y $xor$libresoc.v:148543$7302_Y
+ connect \Y $xor$libresoc.v:148207$7250_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $xor $xor$libresoc.v:148546$7305
+ cell $xor $xor$libresoc.v:148210$7253
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \a_n [63:32]
connect \B \rb [63:32]
- connect \Y $xor$libresoc.v:148546$7305_Y
+ connect \Y $xor$libresoc.v:148210$7253_Y
end
- attribute \src "libresoc.v:148042.7-148042.20"
- process $proc$libresoc.v:148042$7352
+ attribute \src "libresoc.v:147706.7-147706.20"
+ process $proc$libresoc.v:147706$7300
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:148564.3-148573.6"
- process $proc$libresoc.v:148564$7323
+ attribute \src "libresoc.v:148228.3-148237.6"
+ process $proc$libresoc.v:148228$7271
assign { } { }
assign { } { }
assign $0\is_32bit[0:0] $1\is_32bit[0:0]
- attribute \src "libresoc.v:148565.5-148565.29"
+ attribute \src "libresoc.v:148229.5-148229.29"
switch \initial
- attribute \src "libresoc.v:148565.9-148565.17"
+ attribute \src "libresoc.v:148229.9-148229.17"
case 1'1
case
end
sync always
update \is_32bit $0\is_32bit[0:0]
end
- attribute \src "libresoc.v:148574.3-148596.6"
- process $proc$libresoc.v:148574$7324
+ attribute \src "libresoc.v:148238.3-148260.6"
+ process $proc$libresoc.v:148238$7272
assign { } { }
assign $0\a_i[63:0] $1\a_i[63:0]
- attribute \src "libresoc.v:148575.5-148575.29"
+ attribute \src "libresoc.v:148239.5-148239.29"
switch \initial
- attribute \src "libresoc.v:148575.9-148575.17"
+ attribute \src "libresoc.v:148239.9-148239.17"
case 1'1
case
end
sync always
update \a_i $0\a_i[63:0]
end
- attribute \src "libresoc.v:148597.3-148607.6"
- process $proc$libresoc.v:148597$7325
+ attribute \src "libresoc.v:148261.3-148271.6"
+ process $proc$libresoc.v:148261$7273
assign { } { }
assign { } { }
assign $0\zerohi[0:0] $1\zerohi[0:0]
- attribute \src "libresoc.v:148598.5-148598.29"
+ attribute \src "libresoc.v:148262.5-148262.29"
switch \initial
- attribute \src "libresoc.v:148598.9-148598.17"
+ attribute \src "libresoc.v:148262.9-148262.17"
case 1'1
case
end
sync always
update \zerohi $0\zerohi[0:0]
end
- attribute \src "libresoc.v:148608.3-148634.6"
- process $proc$libresoc.v:148608$7326
+ attribute \src "libresoc.v:148272.3-148298.6"
+ process $proc$libresoc.v:148272$7274
assign { } { }
assign { } { }
assign $0\tval[4:0] $1\tval[4:0]
- attribute \src "libresoc.v:148609.5-148609.29"
+ attribute \src "libresoc.v:148273.5-148273.29"
switch \initial
- attribute \src "libresoc.v:148609.9-148609.17"
+ attribute \src "libresoc.v:148273.9-148273.17"
case 1'1
case
end
sync always
update \tval $0\tval[4:0]
end
- attribute \src "libresoc.v:148635.3-148653.6"
- process $proc$libresoc.v:148635$7327
+ attribute \src "libresoc.v:148299.3-148317.6"
+ process $proc$libresoc.v:148299$7275
assign { } { }
assign { } { }
assign $0\msb_a[0:0] $1\msb_a[0:0]
- attribute \src "libresoc.v:148636.5-148636.29"
+ attribute \src "libresoc.v:148300.5-148300.29"
switch \initial
- attribute \src "libresoc.v:148636.9-148636.17"
+ attribute \src "libresoc.v:148300.9-148300.17"
case 1'1
case
end
sync always
update \msb_a $0\msb_a[0:0]
end
- attribute \src "libresoc.v:148654.3-148672.6"
- process $proc$libresoc.v:148654$7328
+ attribute \src "libresoc.v:148318.3-148336.6"
+ process $proc$libresoc.v:148318$7276
assign { } { }
assign { } { }
assign $0\msb_b[0:0] $1\msb_b[0:0]
- attribute \src "libresoc.v:148655.5-148655.29"
+ attribute \src "libresoc.v:148319.5-148319.29"
switch \initial
- attribute \src "libresoc.v:148655.9-148655.17"
+ attribute \src "libresoc.v:148319.9-148319.17"
case 1'1
case
end
sync always
update \msb_b $0\msb_b[0:0]
end
- attribute \src "libresoc.v:148673.3-148699.6"
- process $proc$libresoc.v:148673$7329
+ attribute \src "libresoc.v:148337.3-148363.6"
+ process $proc$libresoc.v:148337$7277
assign { } { }
assign { } { }
assign $0\a_lt[0:0] $1\a_lt[0:0]
- attribute \src "libresoc.v:148674.5-148674.29"
+ attribute \src "libresoc.v:148338.5-148338.29"
switch \initial
- attribute \src "libresoc.v:148674.9-148674.17"
+ attribute \src "libresoc.v:148338.9-148338.17"
case 1'1
case
end
sync always
update \a_lt $0\a_lt[0:0]
end
- attribute \src "libresoc.v:148700.3-148733.6"
- process $proc$libresoc.v:148700$7330
+ attribute \src "libresoc.v:148364.3-148397.6"
+ process $proc$libresoc.v:148364$7278
assign { } { }
assign { } { }
assign $0\cr_a[3:0] $1\cr_a[3:0]
- attribute \src "libresoc.v:148701.5-148701.29"
+ attribute \src "libresoc.v:148365.5-148365.29"
switch \initial
- attribute \src "libresoc.v:148701.9-148701.17"
+ attribute \src "libresoc.v:148365.9-148365.17"
case 1'1
case
end
sync always
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:148734.3-148756.6"
- process $proc$libresoc.v:148734$7331
+ attribute \src "libresoc.v:148398.3-148420.6"
+ process $proc$libresoc.v:148398$7279
assign { } { }
assign { } { }
assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:148735.5-148735.29"
+ attribute \src "libresoc.v:148399.5-148399.29"
switch \initial
- attribute \src "libresoc.v:148735.9-148735.17"
+ attribute \src "libresoc.v:148399.9-148399.17"
case 1'1
case
end
sync always
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:148757.3-148798.6"
- process $proc$libresoc.v:148757$7332
+ attribute \src "libresoc.v:148421.3-148462.6"
+ process $proc$libresoc.v:148421$7280
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:148758.5-148758.29"
+ attribute \src "libresoc.v:148422.5-148422.29"
switch \initial
- attribute \src "libresoc.v:148758.9-148758.17"
+ attribute \src "libresoc.v:148422.9-148422.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:148799.3-148821.6"
- process $proc$libresoc.v:148799$7333
+ attribute \src "libresoc.v:148463.3-148485.6"
+ process $proc$libresoc.v:148463$7281
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:148800.5-148800.29"
+ attribute \src "libresoc.v:148464.5-148464.29"
switch \initial
- attribute \src "libresoc.v:148800.9-148800.17"
+ attribute \src "libresoc.v:148464.9-148464.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:148822.3-148839.6"
- process $proc$libresoc.v:148822$7334
+ attribute \src "libresoc.v:148486.3-148503.6"
+ process $proc$libresoc.v:148486$7282
assign { } { }
assign { } { }
assign $0\ca[1:0] $1\ca[1:0]
- attribute \src "libresoc.v:148823.5-148823.29"
+ attribute \src "libresoc.v:148487.5-148487.29"
switch \initial
- attribute \src "libresoc.v:148823.9-148823.17"
+ attribute \src "libresoc.v:148487.9-148487.17"
case 1'1
case
end
sync always
update \ca $0\ca[1:0]
end
- attribute \src "libresoc.v:148840.3-148862.6"
- process $proc$libresoc.v:148840$7335
+ attribute \src "libresoc.v:148504.3-148526.6"
+ process $proc$libresoc.v:148504$7283
assign { } { }
assign $0\b_i[63:0] $1\b_i[63:0]
- attribute \src "libresoc.v:148841.5-148841.29"
+ attribute \src "libresoc.v:148505.5-148505.29"
switch \initial
- attribute \src "libresoc.v:148841.9-148841.17"
+ attribute \src "libresoc.v:148505.9-148505.17"
case 1'1
case
end
sync always
update \b_i $0\b_i[63:0]
end
- attribute \src "libresoc.v:148863.3-148877.6"
- process $proc$libresoc.v:148863$7336
+ attribute \src "libresoc.v:148527.3-148541.6"
+ process $proc$libresoc.v:148527$7284
assign { } { }
assign { } { }
- assign $0\xer_ca$20[1:0]$7337 $1\xer_ca$20[1:0]$7338
- attribute \src "libresoc.v:148864.5-148864.29"
+ assign $0\xer_ca$20[1:0]$7285 $1\xer_ca$20[1:0]$7286
+ attribute \src "libresoc.v:148528.5-148528.29"
switch \initial
- attribute \src "libresoc.v:148864.9-148864.17"
+ attribute \src "libresoc.v:148528.9-148528.17"
case 1'1
case
end
switch \alu_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0001010
- assign $1\xer_ca$20[1:0]$7338 2'00
+ assign $1\xer_ca$20[1:0]$7286 2'00
attribute \src "libresoc.v:0.0-0.0"
case 7'0000010
assign { } { }
- assign $1\xer_ca$20[1:0]$7338 \ca
+ assign $1\xer_ca$20[1:0]$7286 \ca
case
- assign $1\xer_ca$20[1:0]$7338 2'00
+ assign $1\xer_ca$20[1:0]$7286 2'00
end
sync always
- update \xer_ca$20 $0\xer_ca$20[1:0]$7337
+ update \xer_ca$20 $0\xer_ca$20[1:0]$7285
end
- attribute \src "libresoc.v:148878.3-148892.6"
- process $proc$libresoc.v:148878$7339
+ attribute \src "libresoc.v:148542.3-148556.6"
+ process $proc$libresoc.v:148542$7287
assign { } { }
assign { } { }
assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:148879.5-148879.29"
+ attribute \src "libresoc.v:148543.5-148543.29"
switch \initial
- attribute \src "libresoc.v:148879.9-148879.17"
+ attribute \src "libresoc.v:148543.9-148543.17"
case 1'1
case
end
sync always
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:148893.3-148910.6"
- process $proc$libresoc.v:148893$7340
+ attribute \src "libresoc.v:148557.3-148574.6"
+ process $proc$libresoc.v:148557$7288
assign { } { }
assign { } { }
assign $0\ov[1:0] $1\ov[1:0]
- attribute \src "libresoc.v:148894.5-148894.29"
+ attribute \src "libresoc.v:148558.5-148558.29"
switch \initial
- attribute \src "libresoc.v:148894.9-148894.17"
+ attribute \src "libresoc.v:148558.9-148558.17"
case 1'1
case
end
sync always
update \ov $0\ov[1:0]
end
- attribute \src "libresoc.v:148911.3-148925.6"
- process $proc$libresoc.v:148911$7341
+ attribute \src "libresoc.v:148575.3-148589.6"
+ process $proc$libresoc.v:148575$7289
assign { } { }
assign { } { }
assign $0\xer_ov[1:0] $1\xer_ov[1:0]
- attribute \src "libresoc.v:148912.5-148912.29"
+ attribute \src "libresoc.v:148576.5-148576.29"
switch \initial
- attribute \src "libresoc.v:148912.9-148912.17"
+ attribute \src "libresoc.v:148576.9-148576.17"
case 1'1
case
end
sync always
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:148926.3-148940.6"
- process $proc$libresoc.v:148926$7342
+ attribute \src "libresoc.v:148590.3-148604.6"
+ process $proc$libresoc.v:148590$7290
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:148927.5-148927.29"
+ attribute \src "libresoc.v:148591.5-148591.29"
switch \initial
- attribute \src "libresoc.v:148927.9-148927.17"
+ attribute \src "libresoc.v:148591.9-148591.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:148941.3-148963.6"
- process $proc$libresoc.v:148941$7343
+ attribute \src "libresoc.v:148605.3-148627.6"
+ process $proc$libresoc.v:148605$7291
assign { } { }
assign { } { }
assign $0\src1[7:0] $1\src1[7:0]
- attribute \src "libresoc.v:148942.5-148942.29"
+ attribute \src "libresoc.v:148606.5-148606.29"
switch \initial
- attribute \src "libresoc.v:148942.9-148942.17"
+ attribute \src "libresoc.v:148606.9-148606.17"
case 1'1
case
end
sync always
update \src1 $0\src1[7:0]
end
- attribute \src "libresoc.v:148964.3-148995.6"
- process $proc$libresoc.v:148964$7344
+ attribute \src "libresoc.v:148628.3-148659.6"
+ process $proc$libresoc.v:148628$7292
assign { } { }
assign { } { }
assign $0\eqs[7:0] $1\eqs[7:0]
- attribute \src "libresoc.v:148965.5-148965.29"
+ attribute \src "libresoc.v:148629.5-148629.29"
switch \initial
- attribute \src "libresoc.v:148965.9-148965.17"
+ attribute \src "libresoc.v:148629.9-148629.17"
case 1'1
case
end
sync always
update \eqs $0\eqs[7:0]
end
- attribute \src "libresoc.v:148996.3-149005.6"
- process $proc$libresoc.v:148996$7345
+ attribute \src "libresoc.v:148660.3-148669.6"
+ process $proc$libresoc.v:148660$7293
assign { } { }
assign { } { }
assign $0\add_a[65:0] $1\add_a[65:0]
- attribute \src "libresoc.v:148997.5-148997.29"
+ attribute \src "libresoc.v:148661.5-148661.29"
switch \initial
- attribute \src "libresoc.v:148997.9-148997.17"
+ attribute \src "libresoc.v:148661.9-148661.17"
case 1'1
case
end
sync always
update \add_a $0\add_a[65:0]
end
- attribute \src "libresoc.v:149006.3-149015.6"
- process $proc$libresoc.v:149006$7346
+ attribute \src "libresoc.v:148670.3-148679.6"
+ process $proc$libresoc.v:148670$7294
assign { } { }
assign { } { }
assign $0\add_b[65:0] $1\add_b[65:0]
- attribute \src "libresoc.v:149007.5-149007.29"
+ attribute \src "libresoc.v:148671.5-148671.29"
switch \initial
- attribute \src "libresoc.v:149007.9-149007.17"
+ attribute \src "libresoc.v:148671.9-148671.17"
case 1'1
case
end
sync always
update \add_b $0\add_b[65:0]
end
- attribute \src "libresoc.v:149016.3-149025.6"
- process $proc$libresoc.v:149016$7347
+ attribute \src "libresoc.v:148680.3-148689.6"
+ process $proc$libresoc.v:148680$7295
assign { } { }
assign { } { }
assign $0\add_o[65:0] $1\add_o[65:0]
- attribute \src "libresoc.v:149017.5-149017.29"
+ attribute \src "libresoc.v:148681.5-148681.29"
switch \initial
- attribute \src "libresoc.v:149017.9-149017.17"
+ attribute \src "libresoc.v:148681.9-148681.17"
case 1'1
case
end
sync always
update \add_o $0\add_o[65:0]
end
- attribute \src "libresoc.v:149026.3-149036.6"
- process $proc$libresoc.v:149026$7348
+ attribute \src "libresoc.v:148690.3-148700.6"
+ process $proc$libresoc.v:148690$7296
assign { } { }
assign { } { }
assign $0\a_n[63:0] $1\a_n[63:0]
- attribute \src "libresoc.v:149027.5-149027.29"
+ attribute \src "libresoc.v:148691.5-148691.29"
switch \initial
- attribute \src "libresoc.v:149027.9-149027.17"
+ attribute \src "libresoc.v:148691.9-148691.17"
case 1'1
case
end
sync always
update \a_n $0\a_n[63:0]
end
- attribute \src "libresoc.v:149037.3-149047.6"
- process $proc$libresoc.v:149037$7349
+ attribute \src "libresoc.v:148701.3-148711.6"
+ process $proc$libresoc.v:148701$7297
assign { } { }
assign { } { }
assign $0\carry_32[0:0] $1\carry_32[0:0]
- attribute \src "libresoc.v:149038.5-149038.29"
+ attribute \src "libresoc.v:148702.5-148702.29"
switch \initial
- attribute \src "libresoc.v:149038.9-149038.17"
+ attribute \src "libresoc.v:148702.9-148702.17"
case 1'1
case
end
sync always
update \carry_32 $0\carry_32[0:0]
end
- attribute \src "libresoc.v:149048.3-149058.6"
- process $proc$libresoc.v:149048$7350
+ attribute \src "libresoc.v:148712.3-148722.6"
+ process $proc$libresoc.v:148712$7298
assign { } { }
assign { } { }
assign $0\carry_64[0:0] $1\carry_64[0:0]
- attribute \src "libresoc.v:149049.5-149049.29"
+ attribute \src "libresoc.v:148713.5-148713.29"
switch \initial
- attribute \src "libresoc.v:149049.9-149049.17"
+ attribute \src "libresoc.v:148713.9-148713.17"
case 1'1
case
end
sync always
update \carry_64 $0\carry_64[0:0]
end
- attribute \src "libresoc.v:149059.3-149069.6"
- process $proc$libresoc.v:149059$7351
+ attribute \src "libresoc.v:148723.3-148733.6"
+ process $proc$libresoc.v:148723$7299
assign { } { }
assign { } { }
assign $0\zerolo[0:0] $1\zerolo[0:0]
- attribute \src "libresoc.v:149060.5-149060.29"
+ attribute \src "libresoc.v:148724.5-148724.29"
switch \initial
- attribute \src "libresoc.v:149060.9-149060.17"
+ attribute \src "libresoc.v:148724.9-148724.17"
case 1'1
case
end
sync always
update \zerolo $0\zerolo[0:0]
end
- connect \$99 $reduce_or$libresoc.v:148503$7262_Y
- connect \$101 $eq$libresoc.v:148504$7263_Y
- connect \$103 $eq$libresoc.v:148505$7264_Y
- connect \$105 $eq$libresoc.v:148506$7265_Y
- connect \$107 $reduce_or$libresoc.v:148507$7266_Y
- connect \$109 $xor$libresoc.v:148508$7267_Y
- connect \$111 $xor$libresoc.v:148509$7268_Y
- connect \$113 $xor$libresoc.v:148510$7269_Y
- connect \$116 $xor$libresoc.v:148511$7270_Y
- connect \$115 $not$libresoc.v:148512$7271_Y
- connect \$119 $and$libresoc.v:148513$7272_Y
- connect \$121 $xor$libresoc.v:148514$7273_Y
- connect \$124 $xor$libresoc.v:148515$7274_Y
- connect \$123 $not$libresoc.v:148516$7275_Y
- connect \$127 $and$libresoc.v:148517$7276_Y
- connect \$129 $eq$libresoc.v:148518$7277_Y
- connect \$131 $eq$libresoc.v:148519$7278_Y
- connect \$133 $eq$libresoc.v:148520$7279_Y
- connect \$135 $eq$libresoc.v:148521$7280_Y
- connect \$137 $eq$libresoc.v:148522$7281_Y
- connect \$139 $eq$libresoc.v:148523$7282_Y
- connect \$141 $eq$libresoc.v:148524$7283_Y
- connect \$143 $eq$libresoc.v:148525$7284_Y
- connect \$22 $eq$libresoc.v:148526$7285_Y
- connect \$24 $not$libresoc.v:148527$7286_Y
- connect \$26 $eq$libresoc.v:148528$7287_Y
- connect \$28 $eq$libresoc.v:148529$7288_Y
- connect \$30 $eq$libresoc.v:148530$7289_Y
- connect \$32 $eq$libresoc.v:148531$7290_Y
- connect \$34 $or$libresoc.v:148532$7291_Y
- connect \$36 $eq$libresoc.v:148533$7292_Y
- connect \$38 $eq$libresoc.v:148534$7293_Y
- connect \$40 $or$libresoc.v:148535$7294_Y
- connect \$42 $eq$libresoc.v:148536$7295_Y
- connect \$44 $eq$libresoc.v:148537$7296_Y
- connect \$46 $or$libresoc.v:148538$7297_Y
- connect \$49 $add$libresoc.v:148539$7298_Y
- connect \$51 $not$libresoc.v:148540$7299_Y
- connect \$53 $xor$libresoc.v:148541$7300_Y
- connect \$55 $xor$libresoc.v:148542$7301_Y
- connect \$59 $xor$libresoc.v:148543$7302_Y
- connect \$58 $reduce_or$libresoc.v:148544$7303_Y
- connect \$57 $not$libresoc.v:148545$7304_Y
- connect \$65 $xor$libresoc.v:148546$7305_Y
- connect \$64 $reduce_or$libresoc.v:148547$7306_Y
- connect \$63 $not$libresoc.v:148548$7307_Y
- connect \$69 $or$libresoc.v:148549$7308_Y
- connect \$71 $and$libresoc.v:148550$7309_Y
- connect \$73 $ne$libresoc.v:148551$7310_Y
- connect \$75 $not$libresoc.v:148552$7311_Y
- connect \$77 $not$libresoc.v:148553$7312_Y
- connect \$79 $or$libresoc.v:148554$7313_Y
- connect \$81 $and$libresoc.v:148555$7314_Y
- connect \$83 $ternary$libresoc.v:148556$7315_Y
- connect \$85 $or$libresoc.v:148557$7316_Y
- connect \$87 $and$libresoc.v:148558$7317_Y
- connect \$89 $ternary$libresoc.v:148559$7318_Y
- connect \$91 $or$libresoc.v:148560$7319_Y
- connect \$93 $and$libresoc.v:148561$7320_Y
- connect \$95 $ne$libresoc.v:148562$7321_Y
- connect \$97 $ternary$libresoc.v:148563$7322_Y
+ connect \$99 $reduce_or$libresoc.v:148167$7210_Y
+ connect \$101 $eq$libresoc.v:148168$7211_Y
+ connect \$103 $eq$libresoc.v:148169$7212_Y
+ connect \$105 $eq$libresoc.v:148170$7213_Y
+ connect \$107 $reduce_or$libresoc.v:148171$7214_Y
+ connect \$109 $xor$libresoc.v:148172$7215_Y
+ connect \$111 $xor$libresoc.v:148173$7216_Y
+ connect \$113 $xor$libresoc.v:148174$7217_Y
+ connect \$116 $xor$libresoc.v:148175$7218_Y
+ connect \$115 $not$libresoc.v:148176$7219_Y
+ connect \$119 $and$libresoc.v:148177$7220_Y
+ connect \$121 $xor$libresoc.v:148178$7221_Y
+ connect \$124 $xor$libresoc.v:148179$7222_Y
+ connect \$123 $not$libresoc.v:148180$7223_Y
+ connect \$127 $and$libresoc.v:148181$7224_Y
+ connect \$129 $eq$libresoc.v:148182$7225_Y
+ connect \$131 $eq$libresoc.v:148183$7226_Y
+ connect \$133 $eq$libresoc.v:148184$7227_Y
+ connect \$135 $eq$libresoc.v:148185$7228_Y
+ connect \$137 $eq$libresoc.v:148186$7229_Y
+ connect \$139 $eq$libresoc.v:148187$7230_Y
+ connect \$141 $eq$libresoc.v:148188$7231_Y
+ connect \$143 $eq$libresoc.v:148189$7232_Y
+ connect \$22 $eq$libresoc.v:148190$7233_Y
+ connect \$24 $not$libresoc.v:148191$7234_Y
+ connect \$26 $eq$libresoc.v:148192$7235_Y
+ connect \$28 $eq$libresoc.v:148193$7236_Y
+ connect \$30 $eq$libresoc.v:148194$7237_Y
+ connect \$32 $eq$libresoc.v:148195$7238_Y
+ connect \$34 $or$libresoc.v:148196$7239_Y
+ connect \$36 $eq$libresoc.v:148197$7240_Y
+ connect \$38 $eq$libresoc.v:148198$7241_Y
+ connect \$40 $or$libresoc.v:148199$7242_Y
+ connect \$42 $eq$libresoc.v:148200$7243_Y
+ connect \$44 $eq$libresoc.v:148201$7244_Y
+ connect \$46 $or$libresoc.v:148202$7245_Y
+ connect \$49 $add$libresoc.v:148203$7246_Y
+ connect \$51 $not$libresoc.v:148204$7247_Y
+ connect \$53 $xor$libresoc.v:148205$7248_Y
+ connect \$55 $xor$libresoc.v:148206$7249_Y
+ connect \$59 $xor$libresoc.v:148207$7250_Y
+ connect \$58 $reduce_or$libresoc.v:148208$7251_Y
+ connect \$57 $not$libresoc.v:148209$7252_Y
+ connect \$65 $xor$libresoc.v:148210$7253_Y
+ connect \$64 $reduce_or$libresoc.v:148211$7254_Y
+ connect \$63 $not$libresoc.v:148212$7255_Y
+ connect \$69 $or$libresoc.v:148213$7256_Y
+ connect \$71 $and$libresoc.v:148214$7257_Y
+ connect \$73 $ne$libresoc.v:148215$7258_Y
+ connect \$75 $not$libresoc.v:148216$7259_Y
+ connect \$77 $not$libresoc.v:148217$7260_Y
+ connect \$79 $or$libresoc.v:148218$7261_Y
+ connect \$81 $and$libresoc.v:148219$7262_Y
+ connect \$83 $ternary$libresoc.v:148220$7263_Y
+ connect \$85 $or$libresoc.v:148221$7264_Y
+ connect \$87 $and$libresoc.v:148222$7265_Y
+ connect \$89 $ternary$libresoc.v:148223$7266_Y
+ connect \$91 $or$libresoc.v:148224$7267_Y
+ connect \$93 $and$libresoc.v:148225$7268_Y
+ connect \$95 $ne$libresoc.v:148226$7269_Y
+ connect \$97 $ternary$libresoc.v:148227$7270_Y
connect \$48 \$49
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$21 \xer_so
end
-attribute \src "libresoc.v:149078.1-149492.10"
+attribute \src "libresoc.v:148742.1-149156.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main"
attribute \generator "nMigen"
module \main$114
- attribute \src "libresoc.v:149079.7-149079.20"
+ attribute \src "libresoc.v:148743.7-148743.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:149444.3-149474.6"
+ attribute \src "libresoc.v:149108.3-149138.6"
wire width 4 $0\mode[3:0]
- attribute \src "libresoc.v:149409.3-149443.6"
+ attribute \src "libresoc.v:149073.3-149107.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:149444.3-149474.6"
+ attribute \src "libresoc.v:149108.3-149138.6"
wire width 4 $1\mode[3:0]
- attribute \src "libresoc.v:149409.3-149443.6"
+ attribute \src "libresoc.v:149073.3-149107.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:149079.7-149079.15"
+ attribute \src "libresoc.v:148743.7-148743.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46"
wire width 5 \mb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 42 \xer_so$19
attribute \module_not_derived 1
- attribute \src "libresoc.v:149393.11-149408.4"
+ attribute \src "libresoc.v:149057.11-149072.4"
cell \rotator \rotator
connect \arith \rotator_arith
connect \carry_out_o \rotator_carry_out_o
connect \shift \rotator_shift
connect \sign_ext_rs \rotator_sign_ext_rs
end
- attribute \src "libresoc.v:149079.7-149079.20"
- process $proc$libresoc.v:149079$7355
+ attribute \src "libresoc.v:148743.7-148743.20"
+ process $proc$libresoc.v:148743$7303
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:149409.3-149443.6"
- process $proc$libresoc.v:149409$7353
+ attribute \src "libresoc.v:149073.3-149107.6"
+ process $proc$libresoc.v:149073$7301
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:149410.5-149410.29"
+ attribute \src "libresoc.v:149074.5-149074.29"
switch \initial
- attribute \src "libresoc.v:149410.9-149410.17"
+ attribute \src "libresoc.v:149074.9-149074.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:149444.3-149474.6"
- process $proc$libresoc.v:149444$7354
+ attribute \src "libresoc.v:149108.3-149138.6"
+ process $proc$libresoc.v:149108$7302
assign { } { }
assign { } { }
assign $0\mode[3:0] $1\mode[3:0]
- attribute \src "libresoc.v:149445.5-149445.29"
+ attribute \src "libresoc.v:149109.5-149109.29"
switch \initial
- attribute \src "libresoc.v:149445.9-149445.17"
+ attribute \src "libresoc.v:149109.9-149109.17"
case 1'1
case
end
connect \me \sr_op__insn [5:1]
connect \mb \sr_op__insn [10:6]
end
-attribute \src "libresoc.v:149496.1-150036.10"
+attribute \src "libresoc.v:149160.1-149700.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main"
attribute \generator "nMigen"
module \main$22
- attribute \src "libresoc.v:149943.3-149966.6"
+ attribute \src "libresoc.v:149607.3-149630.6"
wire $0\bc_taken[0:0]
- attribute \src "libresoc.v:149818.3-149829.6"
+ attribute \src "libresoc.v:149482.3-149493.6"
wire width 64 $0\br_addr[63:0]
- attribute \src "libresoc.v:149830.3-149856.6"
+ attribute \src "libresoc.v:149494.3-149520.6"
wire width 64 $0\br_imm_addr[63:0]
- attribute \src "libresoc.v:149857.3-149875.6"
+ attribute \src "libresoc.v:149521.3-149539.6"
wire $0\br_taken[0:0]
- attribute \src "libresoc.v:149915.3-149929.6"
+ attribute \src "libresoc.v:149579.3-149593.6"
wire $0\cr_bit[0:0]
- attribute \src "libresoc.v:149993.3-150013.6"
+ attribute \src "libresoc.v:149657.3-149677.6"
wire width 64 $0\ctr_m[63:0]
- attribute \src "libresoc.v:149967.3-149979.6"
+ attribute \src "libresoc.v:149631.3-149643.6"
wire width 64 $0\ctr_n[63:0]
- attribute \src "libresoc.v:149930.3-149942.6"
+ attribute \src "libresoc.v:149594.3-149606.6"
wire $0\ctr_write[0:0]
- attribute \src "libresoc.v:150014.3-150026.6"
+ attribute \src "libresoc.v:149678.3-149690.6"
wire $0\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:149980.3-149992.6"
- wire width 64 $0\fast1$10[63:0]$7388
- attribute \src "libresoc.v:149876.3-149894.6"
+ attribute \src "libresoc.v:149644.3-149656.6"
+ wire width 64 $0\fast1$10[63:0]$7336
+ attribute \src "libresoc.v:149540.3-149558.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:149895.3-149904.6"
- wire width 64 $0\fast2$11[63:0]$7380
- attribute \src "libresoc.v:149905.3-149914.6"
+ attribute \src "libresoc.v:149559.3-149568.6"
+ wire width 64 $0\fast2$11[63:0]$7328
+ attribute \src "libresoc.v:149569.3-149578.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:149497.7-149497.20"
+ attribute \src "libresoc.v:149161.7-149161.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:149943.3-149966.6"
+ attribute \src "libresoc.v:149607.3-149630.6"
wire $1\bc_taken[0:0]
- attribute \src "libresoc.v:149818.3-149829.6"
+ attribute \src "libresoc.v:149482.3-149493.6"
wire width 64 $1\br_addr[63:0]
- attribute \src "libresoc.v:149830.3-149856.6"
+ attribute \src "libresoc.v:149494.3-149520.6"
wire width 64 $1\br_imm_addr[63:0]
- attribute \src "libresoc.v:149857.3-149875.6"
+ attribute \src "libresoc.v:149521.3-149539.6"
wire $1\br_taken[0:0]
- attribute \src "libresoc.v:149915.3-149929.6"
+ attribute \src "libresoc.v:149579.3-149593.6"
wire $1\cr_bit[0:0]
- attribute \src "libresoc.v:149993.3-150013.6"
+ attribute \src "libresoc.v:149657.3-149677.6"
wire width 64 $1\ctr_m[63:0]
- attribute \src "libresoc.v:149967.3-149979.6"
+ attribute \src "libresoc.v:149631.3-149643.6"
wire width 64 $1\ctr_n[63:0]
- attribute \src "libresoc.v:149930.3-149942.6"
+ attribute \src "libresoc.v:149594.3-149606.6"
wire $1\ctr_write[0:0]
- attribute \src "libresoc.v:150014.3-150026.6"
+ attribute \src "libresoc.v:149678.3-149690.6"
wire $1\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:149980.3-149992.6"
- wire width 64 $1\fast1$10[63:0]$7389
- attribute \src "libresoc.v:149876.3-149894.6"
+ attribute \src "libresoc.v:149644.3-149656.6"
+ wire width 64 $1\fast1$10[63:0]$7337
+ attribute \src "libresoc.v:149540.3-149558.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:149895.3-149904.6"
- wire width 64 $1\fast2$11[63:0]$7381
- attribute \src "libresoc.v:149905.3-149914.6"
+ attribute \src "libresoc.v:149559.3-149568.6"
+ wire width 64 $1\fast2$11[63:0]$7329
+ attribute \src "libresoc.v:149569.3-149578.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:149943.3-149966.6"
+ attribute \src "libresoc.v:149607.3-149630.6"
wire $2\bc_taken[0:0]
- attribute \src "libresoc.v:149830.3-149856.6"
+ attribute \src "libresoc.v:149494.3-149520.6"
wire width 64 $2\br_imm_addr[63:0]
- attribute \src "libresoc.v:149993.3-150013.6"
+ attribute \src "libresoc.v:149657.3-149677.6"
wire width 64 $2\ctr_m[63:0]
- attribute \src "libresoc.v:149802.18-149802.119"
- wire width 65 $add$libresoc.v:149802$7358_Y
- attribute \src "libresoc.v:149817.18-149817.113"
- wire width 65 $add$libresoc.v:149817$7374_Y
- attribute \src "libresoc.v:149809.18-149809.115"
- wire $and$libresoc.v:149809$7365_Y
- attribute \src "libresoc.v:149810.18-149810.117"
- wire $and$libresoc.v:149810$7366_Y
- attribute \src "libresoc.v:149816.18-149816.118"
- wire $and$libresoc.v:149816$7373_Y
- attribute \src "libresoc.v:149800.18-149800.120"
- wire $eq$libresoc.v:149800$7356_Y
- attribute \src "libresoc.v:149803.18-149803.111"
- wire $eq$libresoc.v:149803$7359_Y
- attribute \src "libresoc.v:149805.18-149805.111"
- wire $eq$libresoc.v:149805$7361_Y
- attribute \src "libresoc.v:149806.18-149806.111"
- wire $eq$libresoc.v:149806$7362_Y
- attribute \src "libresoc.v:149807.18-149807.109"
- wire $eq$libresoc.v:149807$7363_Y
- attribute \src "libresoc.v:149812.18-149812.98"
- wire width 64 $extend$libresoc.v:149812$7368_Y
- attribute \src "libresoc.v:149808.18-149808.104"
- wire $not$libresoc.v:149808$7364_Y
- attribute \src "libresoc.v:149815.18-149815.112"
- wire $not$libresoc.v:149815$7372_Y
- attribute \src "libresoc.v:149801.18-149801.116"
- wire $or$libresoc.v:149801$7357_Y
- attribute \src "libresoc.v:149804.18-149804.109"
- wire $or$libresoc.v:149804$7360_Y
- attribute \src "libresoc.v:149812.18-149812.98"
- wire width 64 $pos$libresoc.v:149812$7369_Y
- attribute \src "libresoc.v:149813.18-149813.103"
- wire $reduce_or$libresoc.v:149813$7370_Y
- attribute \src "libresoc.v:149811.18-149811.108"
- wire width 65 $sub$libresoc.v:149811$7367_Y
- attribute \src "libresoc.v:149814.18-149814.108"
- wire $xor$libresoc.v:149814$7371_Y
+ attribute \src "libresoc.v:149466.18-149466.119"
+ wire width 65 $add$libresoc.v:149466$7306_Y
+ attribute \src "libresoc.v:149481.18-149481.113"
+ wire width 65 $add$libresoc.v:149481$7322_Y
+ attribute \src "libresoc.v:149473.18-149473.115"
+ wire $and$libresoc.v:149473$7313_Y
+ attribute \src "libresoc.v:149474.18-149474.117"
+ wire $and$libresoc.v:149474$7314_Y
+ attribute \src "libresoc.v:149480.18-149480.118"
+ wire $and$libresoc.v:149480$7321_Y
+ attribute \src "libresoc.v:149464.18-149464.120"
+ wire $eq$libresoc.v:149464$7304_Y
+ attribute \src "libresoc.v:149467.18-149467.111"
+ wire $eq$libresoc.v:149467$7307_Y
+ attribute \src "libresoc.v:149469.18-149469.111"
+ wire $eq$libresoc.v:149469$7309_Y
+ attribute \src "libresoc.v:149470.18-149470.111"
+ wire $eq$libresoc.v:149470$7310_Y
+ attribute \src "libresoc.v:149471.18-149471.109"
+ wire $eq$libresoc.v:149471$7311_Y
+ attribute \src "libresoc.v:149476.18-149476.98"
+ wire width 64 $extend$libresoc.v:149476$7316_Y
+ attribute \src "libresoc.v:149472.18-149472.104"
+ wire $not$libresoc.v:149472$7312_Y
+ attribute \src "libresoc.v:149479.18-149479.112"
+ wire $not$libresoc.v:149479$7320_Y
+ attribute \src "libresoc.v:149465.18-149465.116"
+ wire $or$libresoc.v:149465$7305_Y
+ attribute \src "libresoc.v:149468.18-149468.109"
+ wire $or$libresoc.v:149468$7308_Y
+ attribute \src "libresoc.v:149476.18-149476.98"
+ wire width 64 $pos$libresoc.v:149476$7317_Y
+ attribute \src "libresoc.v:149477.18-149477.103"
+ wire $reduce_or$libresoc.v:149477$7318_Y
+ attribute \src "libresoc.v:149475.18-149475.108"
+ wire width 65 $sub$libresoc.v:149475$7315_Y
+ attribute \src "libresoc.v:149478.18-149478.108"
+ wire $xor$libresoc.v:149478$7319_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
wire width 64 output 23 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 24 \fast2_ok
- attribute \src "libresoc.v:149497.7-149497.15"
+ attribute \src "libresoc.v:149161.7-149161.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 27 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 26 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95"
- cell $add $add$libresoc.v:149802$7358
+ cell $add $add$libresoc.v:149466$7306
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \br_imm_addr
connect \B \br_op__cia
- connect \Y $add$libresoc.v:149802$7358_Y
+ connect \Y $add$libresoc.v:149466$7306_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175"
- cell $add $add$libresoc.v:149817$7374
+ cell $add $add$libresoc.v:149481$7322
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \br_op__cia
connect \B 3'100
- connect \Y $add$libresoc.v:149817$7374_Y
+ connect \Y $add$libresoc.v:149481$7322_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138"
- cell $and $and$libresoc.v:149809$7365
+ cell $and $and$libresoc.v:149473$7313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
connect \B \$29
- connect \Y $and$libresoc.v:149809$7365_Y
+ connect \Y $and$libresoc.v:149473$7313_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140"
- cell $and $and$libresoc.v:149810$7366
+ cell $and $and$libresoc.v:149474$7314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
connect \B \cr_bit
- connect \Y $and$libresoc.v:149810$7366_Y
+ connect \Y $and$libresoc.v:149474$7314_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160"
- cell $and $and$libresoc.v:149816$7373
+ cell $and $and$libresoc.v:149480$7321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn [10]
connect \B \$44
- connect \Y $and$libresoc.v:149816$7373_Y
+ connect \Y $and$libresoc.v:149480$7321_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
- cell $eq $eq$libresoc.v:149800$7356
+ cell $eq $eq$libresoc.v:149464$7304
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn_type
connect \B 7'0001000
- connect \Y $eq$libresoc.v:149800$7356_Y
+ connect \Y $eq$libresoc.v:149464$7304_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121"
- cell $eq $eq$libresoc.v:149803$7359
+ cell $eq $eq$libresoc.v:149467$7307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_bit
connect \B \bo [3]
- connect \Y $eq$libresoc.v:149803$7359_Y
+ connect \Y $eq$libresoc.v:149467$7307_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- cell $eq $eq$libresoc.v:149805$7361
+ cell $eq $eq$libresoc.v:149469$7309
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4:3]
connect \B 1'0
- connect \Y $eq$libresoc.v:149805$7361_Y
+ connect \Y $eq$libresoc.v:149469$7309_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
- cell $eq $eq$libresoc.v:149806$7362
+ cell $eq $eq$libresoc.v:149470$7310
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4:3]
connect \B 1'1
- connect \Y $eq$libresoc.v:149806$7362_Y
+ connect \Y $eq$libresoc.v:149470$7310_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141"
- cell $eq $eq$libresoc.v:149807$7363
+ cell $eq $eq$libresoc.v:149471$7311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4]
connect \B 1'1
- connect \Y $eq$libresoc.v:149807$7363_Y
+ connect \Y $eq$libresoc.v:149471$7311_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:149812$7368
+ cell $pos $extend$libresoc.v:149476$7316
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \fast1 [31:0]
- connect \Y $extend$libresoc.v:149812$7368_Y
+ connect \Y $extend$libresoc.v:149476$7316_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138"
- cell $not $not$libresoc.v:149808$7364
+ cell $not $not$libresoc.v:149472$7312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cr_bit
- connect \Y $not$libresoc.v:149808$7364_Y
+ connect \Y $not$libresoc.v:149472$7312_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160"
- cell $not $not$libresoc.v:149815$7372
+ cell $not $not$libresoc.v:149479$7320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \br_op__insn [6]
- connect \Y $not$libresoc.v:149815$7372_Y
+ connect \Y $not$libresoc.v:149479$7320_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
- cell $or $or$libresoc.v:149801$7357
+ cell $or $or$libresoc.v:149465$7305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn [1]
connect \B \$12
- connect \Y $or$libresoc.v:149801$7357_Y
+ connect \Y $or$libresoc.v:149465$7305_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121"
- cell $or $or$libresoc.v:149804$7360
+ cell $or $or$libresoc.v:149468$7308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \bo [4]
- connect \Y $or$libresoc.v:149804$7360_Y
+ connect \Y $or$libresoc.v:149468$7308_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:149812$7369
+ cell $pos $pos$libresoc.v:149476$7317
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:149812$7368_Y
- connect \Y $pos$libresoc.v:149812$7369_Y
+ connect \A $extend$libresoc.v:149476$7316_Y
+ connect \Y $pos$libresoc.v:149476$7317_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136"
- cell $reduce_or $reduce_or$libresoc.v:149813$7370
+ cell $reduce_or $reduce_or$libresoc.v:149477$7318
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \ctr_n
- connect \Y $reduce_or$libresoc.v:149813$7370_Y
+ connect \Y $reduce_or$libresoc.v:149477$7318_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125"
- cell $sub $sub$libresoc.v:149811$7367
+ cell $sub $sub$libresoc.v:149475$7315
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \fast1
connect \B 1'1
- connect \Y $sub$libresoc.v:149811$7367_Y
+ connect \Y $sub$libresoc.v:149475$7315_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136"
- cell $xor $xor$libresoc.v:149814$7371
+ cell $xor $xor$libresoc.v:149478$7319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [1]
connect \B \$40
- connect \Y $xor$libresoc.v:149814$7371_Y
+ connect \Y $xor$libresoc.v:149478$7319_Y
end
- attribute \src "libresoc.v:149497.7-149497.20"
- process $proc$libresoc.v:149497$7392
+ attribute \src "libresoc.v:149161.7-149161.20"
+ process $proc$libresoc.v:149161$7340
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:149818.3-149829.6"
- process $proc$libresoc.v:149818$7375
+ attribute \src "libresoc.v:149482.3-149493.6"
+ process $proc$libresoc.v:149482$7323
assign { } { }
assign $0\br_addr[63:0] $1\br_addr[63:0]
- attribute \src "libresoc.v:149819.5-149819.29"
+ attribute \src "libresoc.v:149483.5-149483.29"
switch \initial
- attribute \src "libresoc.v:149819.9-149819.17"
+ attribute \src "libresoc.v:149483.9-149483.17"
case 1'1
case
end
sync always
update \br_addr $0\br_addr[63:0]
end
- attribute \src "libresoc.v:149830.3-149856.6"
- process $proc$libresoc.v:149830$7376
+ attribute \src "libresoc.v:149494.3-149520.6"
+ process $proc$libresoc.v:149494$7324
assign { } { }
assign { } { }
assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0]
- attribute \src "libresoc.v:149831.5-149831.29"
+ attribute \src "libresoc.v:149495.5-149495.29"
switch \initial
- attribute \src "libresoc.v:149831.9-149831.17"
+ attribute \src "libresoc.v:149495.9-149495.17"
case 1'1
case
end
sync always
update \br_imm_addr $0\br_imm_addr[63:0]
end
- attribute \src "libresoc.v:149857.3-149875.6"
- process $proc$libresoc.v:149857$7377
+ attribute \src "libresoc.v:149521.3-149539.6"
+ process $proc$libresoc.v:149521$7325
assign { } { }
assign { } { }
assign $0\br_taken[0:0] $1\br_taken[0:0]
- attribute \src "libresoc.v:149858.5-149858.29"
+ attribute \src "libresoc.v:149522.5-149522.29"
switch \initial
- attribute \src "libresoc.v:149858.9-149858.17"
+ attribute \src "libresoc.v:149522.9-149522.17"
case 1'1
case
end
sync always
update \br_taken $0\br_taken[0:0]
end
- attribute \src "libresoc.v:149876.3-149894.6"
- process $proc$libresoc.v:149876$7378
+ attribute \src "libresoc.v:149540.3-149558.6"
+ process $proc$libresoc.v:149540$7326
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:149877.5-149877.29"
+ attribute \src "libresoc.v:149541.5-149541.29"
switch \initial
- attribute \src "libresoc.v:149877.9-149877.17"
+ attribute \src "libresoc.v:149541.9-149541.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:149895.3-149904.6"
- process $proc$libresoc.v:149895$7379
+ attribute \src "libresoc.v:149559.3-149568.6"
+ process $proc$libresoc.v:149559$7327
assign { } { }
assign { } { }
- assign $0\fast2$11[63:0]$7380 $1\fast2$11[63:0]$7381
- attribute \src "libresoc.v:149896.5-149896.29"
+ assign $0\fast2$11[63:0]$7328 $1\fast2$11[63:0]$7329
+ attribute \src "libresoc.v:149560.5-149560.29"
switch \initial
- attribute \src "libresoc.v:149896.9-149896.17"
+ attribute \src "libresoc.v:149560.9-149560.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fast2$11[63:0]$7381 \$48 [63:0]
+ assign $1\fast2$11[63:0]$7329 \$48 [63:0]
case
- assign $1\fast2$11[63:0]$7381 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$11[63:0]$7329 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast2$11 $0\fast2$11[63:0]$7380
+ update \fast2$11 $0\fast2$11[63:0]$7328
end
- attribute \src "libresoc.v:149905.3-149914.6"
- process $proc$libresoc.v:149905$7382
+ attribute \src "libresoc.v:149569.3-149578.6"
+ process $proc$libresoc.v:149569$7330
assign { } { }
assign { } { }
assign $0\fast2_ok[0:0] $1\fast2_ok[0:0]
- attribute \src "libresoc.v:149906.5-149906.29"
+ attribute \src "libresoc.v:149570.5-149570.29"
switch \initial
- attribute \src "libresoc.v:149906.9-149906.17"
+ attribute \src "libresoc.v:149570.9-149570.17"
case 1'1
case
end
sync always
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:149915.3-149929.6"
- process $proc$libresoc.v:149915$7383
+ attribute \src "libresoc.v:149579.3-149593.6"
+ process $proc$libresoc.v:149579$7331
assign { } { }
assign { } { }
assign $0\cr_bit[0:0] $1\cr_bit[0:0]
- attribute \src "libresoc.v:149916.5-149916.29"
+ attribute \src "libresoc.v:149580.5-149580.29"
switch \initial
- attribute \src "libresoc.v:149916.9-149916.17"
+ attribute \src "libresoc.v:149580.9-149580.17"
case 1'1
case
end
sync always
update \cr_bit $0\cr_bit[0:0]
end
- attribute \src "libresoc.v:149930.3-149942.6"
- process $proc$libresoc.v:149930$7384
+ attribute \src "libresoc.v:149594.3-149606.6"
+ process $proc$libresoc.v:149594$7332
assign { } { }
assign { } { }
assign $0\ctr_write[0:0] $1\ctr_write[0:0]
- attribute \src "libresoc.v:149931.5-149931.29"
+ attribute \src "libresoc.v:149595.5-149595.29"
switch \initial
- attribute \src "libresoc.v:149931.9-149931.17"
+ attribute \src "libresoc.v:149595.9-149595.17"
case 1'1
case
end
sync always
update \ctr_write $0\ctr_write[0:0]
end
- attribute \src "libresoc.v:149943.3-149966.6"
- process $proc$libresoc.v:149943$7385
+ attribute \src "libresoc.v:149607.3-149630.6"
+ process $proc$libresoc.v:149607$7333
assign { } { }
assign { } { }
assign $0\bc_taken[0:0] $1\bc_taken[0:0]
- attribute \src "libresoc.v:149944.5-149944.29"
+ attribute \src "libresoc.v:149608.5-149608.29"
switch \initial
- attribute \src "libresoc.v:149944.9-149944.17"
+ attribute \src "libresoc.v:149608.9-149608.17"
case 1'1
case
end
sync always
update \bc_taken $0\bc_taken[0:0]
end
- attribute \src "libresoc.v:149967.3-149979.6"
- process $proc$libresoc.v:149967$7386
+ attribute \src "libresoc.v:149631.3-149643.6"
+ process $proc$libresoc.v:149631$7334
assign { } { }
assign { } { }
assign $0\ctr_n[63:0] $1\ctr_n[63:0]
- attribute \src "libresoc.v:149968.5-149968.29"
+ attribute \src "libresoc.v:149632.5-149632.29"
switch \initial
- attribute \src "libresoc.v:149968.9-149968.17"
+ attribute \src "libresoc.v:149632.9-149632.17"
case 1'1
case
end
sync always
update \ctr_n $0\ctr_n[63:0]
end
- attribute \src "libresoc.v:149980.3-149992.6"
- process $proc$libresoc.v:149980$7387
+ attribute \src "libresoc.v:149644.3-149656.6"
+ process $proc$libresoc.v:149644$7335
assign { } { }
assign { } { }
- assign $0\fast1$10[63:0]$7388 $1\fast1$10[63:0]$7389
- attribute \src "libresoc.v:149981.5-149981.29"
+ assign $0\fast1$10[63:0]$7336 $1\fast1$10[63:0]$7337
+ attribute \src "libresoc.v:149645.5-149645.29"
switch \initial
- attribute \src "libresoc.v:149981.9-149981.17"
+ attribute \src "libresoc.v:149645.9-149645.17"
case 1'1
case
end
switch \bo [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $1\fast1$10[63:0]$7389 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$10[63:0]$7337 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\fast1$10[63:0]$7389 \ctr_n
+ assign $1\fast1$10[63:0]$7337 \ctr_n
end
sync always
- update \fast1$10 $0\fast1$10[63:0]$7388
+ update \fast1$10 $0\fast1$10[63:0]$7336
end
- attribute \src "libresoc.v:149993.3-150013.6"
- process $proc$libresoc.v:149993$7390
+ attribute \src "libresoc.v:149657.3-149677.6"
+ process $proc$libresoc.v:149657$7338
assign { } { }
assign { } { }
assign $0\ctr_m[63:0] $1\ctr_m[63:0]
- attribute \src "libresoc.v:149994.5-149994.29"
+ attribute \src "libresoc.v:149658.5-149658.29"
switch \initial
- attribute \src "libresoc.v:149994.9-149994.17"
+ attribute \src "libresoc.v:149658.9-149658.17"
case 1'1
case
end
sync always
update \ctr_m $0\ctr_m[63:0]
end
- attribute \src "libresoc.v:150014.3-150026.6"
- process $proc$libresoc.v:150014$7391
+ attribute \src "libresoc.v:149678.3-149690.6"
+ process $proc$libresoc.v:149678$7339
assign { } { }
assign { } { }
assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:150015.5-150015.29"
+ attribute \src "libresoc.v:149679.5-149679.29"
switch \initial
- attribute \src "libresoc.v:150015.9-150015.17"
+ attribute \src "libresoc.v:149679.9-149679.17"
case 1'1
case
end
sync always
update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0]
end
- connect \$12 $eq$libresoc.v:149800$7356_Y
- connect \$14 $or$libresoc.v:149801$7357_Y
- connect \$17 $add$libresoc.v:149802$7358_Y
- connect \$19 $eq$libresoc.v:149803$7359_Y
- connect \$21 $or$libresoc.v:149804$7360_Y
- connect \$23 $eq$libresoc.v:149805$7361_Y
- connect \$25 $eq$libresoc.v:149806$7362_Y
- connect \$27 $eq$libresoc.v:149807$7363_Y
- connect \$29 $not$libresoc.v:149808$7364_Y
- connect \$31 $and$libresoc.v:149809$7365_Y
- connect \$33 $and$libresoc.v:149810$7366_Y
- connect \$36 $sub$libresoc.v:149811$7367_Y
- connect \$38 $pos$libresoc.v:149812$7369_Y
- connect \$40 $reduce_or$libresoc.v:149813$7370_Y
- connect \$42 $xor$libresoc.v:149814$7371_Y
- connect \$44 $not$libresoc.v:149815$7372_Y
- connect \$46 $and$libresoc.v:149816$7373_Y
- connect \$49 $add$libresoc.v:149817$7374_Y
+ connect \$12 $eq$libresoc.v:149464$7304_Y
+ connect \$14 $or$libresoc.v:149465$7305_Y
+ connect \$17 $add$libresoc.v:149466$7306_Y
+ connect \$19 $eq$libresoc.v:149467$7307_Y
+ connect \$21 $or$libresoc.v:149468$7308_Y
+ connect \$23 $eq$libresoc.v:149469$7309_Y
+ connect \$25 $eq$libresoc.v:149470$7310_Y
+ connect \$27 $eq$libresoc.v:149471$7311_Y
+ connect \$29 $not$libresoc.v:149472$7312_Y
+ connect \$31 $and$libresoc.v:149473$7313_Y
+ connect \$33 $and$libresoc.v:149474$7314_Y
+ connect \$36 $sub$libresoc.v:149475$7315_Y
+ connect \$38 $pos$libresoc.v:149476$7317_Y
+ connect \$40 $reduce_or$libresoc.v:149477$7318_Y
+ connect \$42 $xor$libresoc.v:149478$7319_Y
+ connect \$44 $not$libresoc.v:149479$7320_Y
+ connect \$46 $and$libresoc.v:149480$7321_Y
+ connect \$49 $add$libresoc.v:149481$7322_Y
connect \$16 \$17
connect \$35 \$36
connect \$48 \$49
connect \bi \br_op__insn [17:16]
connect \bo \br_op__insn [25:21]
end
-attribute \src "libresoc.v:150040.1-150990.10"
+attribute \src "libresoc.v:149704.1-150654.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main"
attribute \generator "nMigen"
module \main$38
- attribute \src "libresoc.v:150955.3-150966.6"
+ attribute \src "libresoc.v:150619.3-150630.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:150453.3-150464.6"
+ attribute \src "libresoc.v:150117.3-150128.6"
wire width 64 $0\a_s[63:0]
- attribute \src "libresoc.v:150967.3-150978.6"
+ attribute \src "libresoc.v:150631.3-150642.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:150736.3-150747.6"
+ attribute \src "libresoc.v:150400.3-150411.6"
wire width 64 $0\b_s[63:0]
- attribute \src "libresoc.v:150529.3-150560.6"
- wire width 64 $0\fast1$11[63:0]$7438
- attribute \src "libresoc.v:150561.3-150592.6"
+ attribute \src "libresoc.v:150193.3-150224.6"
+ wire width 64 $0\fast1$11[63:0]$7386
+ attribute \src "libresoc.v:150225.3-150256.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire width 64 $0\fast2$12[63:0]$7443
- attribute \src "libresoc.v:150676.3-150707.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire width 64 $0\fast2$12[63:0]$7391
+ attribute \src "libresoc.v:150340.3-150371.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:150041.7-150041.20"
+ attribute \src "libresoc.v:149705.7-149705.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $0\msr_ok[0:0]
- attribute \src "libresoc.v:150465.3-150496.6"
+ attribute \src "libresoc.v:150129.3-150160.6"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:150497.3-150528.6"
+ attribute \src "libresoc.v:150161.3-150192.6"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:150917.3-150935.6"
+ attribute \src "libresoc.v:150581.3-150599.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:150936.3-150954.6"
+ attribute \src "libresoc.v:150600.3-150618.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$60[0:0]$7457
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$61[0:0]$7458
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$62[0:0]$7459
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$67[0:0]$7460
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$68[0:0]$7461
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$69[0:0]$7462
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal$70[0:0]$7463
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $0\trapexc_$signal[0:0]$7456
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $10\fast2$12[19:19]$7453
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$60[0:0]$7405
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$61[0:0]$7406
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$62[0:0]$7407
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$67[0:0]$7408
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$68[0:0]$7409
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$69[0:0]$7410
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal$70[0:0]$7411
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $0\trapexc_$signal[0:0]$7404
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $10\fast2$12[19:19]$7401
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 2 $10\msr[5:4]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $11\msr[15:15]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $12\msr[12:12]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $13\msr[60:60]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $14\msr[12:12]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $15\msr[12:12]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 2 $16\msr[5:4]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $17\msr[15:15]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 3 $18\msr[34:32]
- attribute \src "libresoc.v:150955.3-150966.6"
+ attribute \src "libresoc.v:150619.3-150630.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:150453.3-150464.6"
+ attribute \src "libresoc.v:150117.3-150128.6"
wire width 64 $1\a_s[63:0]
- attribute \src "libresoc.v:150967.3-150978.6"
+ attribute \src "libresoc.v:150631.3-150642.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:150736.3-150747.6"
+ attribute \src "libresoc.v:150400.3-150411.6"
wire width 64 $1\b_s[63:0]
- attribute \src "libresoc.v:150529.3-150560.6"
- wire width 64 $1\fast1$11[63:0]$7439
- attribute \src "libresoc.v:150561.3-150592.6"
+ attribute \src "libresoc.v:150193.3-150224.6"
+ wire width 64 $1\fast1$11[63:0]$7387
+ attribute \src "libresoc.v:150225.3-150256.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire width 64 $1\fast2$12[63:0]$7444
- attribute \src "libresoc.v:150676.3-150707.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire width 64 $1\fast2$12[63:0]$7392
+ attribute \src "libresoc.v:150340.3-150371.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $1\msr_ok[0:0]
- attribute \src "libresoc.v:150465.3-150496.6"
+ attribute \src "libresoc.v:150129.3-150160.6"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:150497.3-150528.6"
+ attribute \src "libresoc.v:150161.3-150192.6"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:150917.3-150935.6"
+ attribute \src "libresoc.v:150581.3-150599.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:150936.3-150954.6"
+ attribute \src "libresoc.v:150600.3-150618.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$60[0:0]$7465
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$61[0:0]$7466
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$62[0:0]$7467
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$67[0:0]$7468
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$68[0:0]$7469
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$69[0:0]$7470
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal$70[0:0]$7471
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $1\trapexc_$signal[0:0]$7464
- attribute \src "libresoc.v:150529.3-150560.6"
- wire width 64 $2\fast1$11[63:0]$7440
- attribute \src "libresoc.v:150561.3-150592.6"
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$60[0:0]$7413
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$61[0:0]$7414
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$62[0:0]$7415
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$67[0:0]$7416
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$68[0:0]$7417
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$69[0:0]$7418
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal$70[0:0]$7419
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $1\trapexc_$signal[0:0]$7412
+ attribute \src "libresoc.v:150193.3-150224.6"
+ wire width 64 $2\fast1$11[63:0]$7388
+ attribute \src "libresoc.v:150225.3-150256.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire width 64 $2\fast2$12[63:0]$7445
- attribute \src "libresoc.v:150676.3-150707.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire width 64 $2\fast2$12[63:0]$7393
+ attribute \src "libresoc.v:150340.3-150371.6"
wire $2\fast2_ok[0:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 64 $2\msr[63:0]
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150412.3-150580.6"
wire $2\msr_ok[0:0]
- attribute \src "libresoc.v:150465.3-150496.6"
+ attribute \src "libresoc.v:150129.3-150160.6"
wire width 64 $2\nia[63:0]
- attribute \src "libresoc.v:150497.3-150528.6"
+ attribute \src "libresoc.v:150161.3-150192.6"
wire $2\nia_ok[0:0]
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$60[0:0]$7473
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$61[0:0]$7474
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$62[0:0]$7475
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$67[0:0]$7476
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$68[0:0]$7477
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$69[0:0]$7478
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal$70[0:0]$7479
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $2\trapexc_$signal[0:0]$7472
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $3\fast2$12[17:17]$7446
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$60[0:0]$7421
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$61[0:0]$7422
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$62[0:0]$7423
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$67[0:0]$7424
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$68[0:0]$7425
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$69[0:0]$7426
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal$70[0:0]$7427
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $2\trapexc_$signal[0:0]$7420
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $3\fast2$12[17:17]$7394
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 11 $3\msr[11:1]
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$60[0:0]$7481
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$61[0:0]$7482
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$62[0:0]$7483
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$67[0:0]$7484
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$68[0:0]$7485
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$69[0:0]$7486
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal$70[0:0]$7487
- attribute \src "libresoc.v:150708.3-150735.6"
- wire $3\trapexc_$signal[0:0]$7480
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $4\fast2$12[18:18]$7447
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$60[0:0]$7429
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$61[0:0]$7430
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$62[0:0]$7431
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$67[0:0]$7432
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$68[0:0]$7433
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$69[0:0]$7434
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal$70[0:0]$7435
+ attribute \src "libresoc.v:150372.3-150399.6"
+ wire $3\trapexc_$signal[0:0]$7428
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $4\fast2$12[18:18]$7395
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 47 $4\msr[59:13]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $5\fast2$12[20:20]$7448
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $5\fast2$12[20:20]$7396
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 3 $5\msr[63:61]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $6\fast2$12[16:16]$7449
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $6\fast2$12[16:16]$7397
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 11 $6\msr[11:1]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire width 2 $7\fast2$12[19:18]$7450
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire width 2 $7\fast2$12[19:18]$7398
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 47 $7\msr[59:13]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $8\fast2$12[28:28]$7451
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $8\fast2$12[28:28]$7399
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 3 $8\msr[63:61]
- attribute \src "libresoc.v:150593.3-150675.6"
- wire $9\fast2$12[30:30]$7452
- attribute \src "libresoc.v:150748.3-150916.6"
+ attribute \src "libresoc.v:150257.3-150339.6"
+ wire $9\fast2$12[30:30]$7400
+ attribute \src "libresoc.v:150412.3-150580.6"
wire width 3 $9\msr[34:32]
- attribute \src "libresoc.v:150429.18-150429.113"
- wire width 65 $add$libresoc.v:150429$7409_Y
- attribute \src "libresoc.v:150423.18-150423.108"
- wire width 5 $and$libresoc.v:150423$7402_Y
- attribute \src "libresoc.v:150431.18-150431.118"
- wire width 8 $and$libresoc.v:150431$7411_Y
- attribute \src "libresoc.v:150433.18-150433.118"
- wire width 8 $and$libresoc.v:150433$7413_Y
- attribute \src "libresoc.v:150435.18-150435.118"
- wire width 8 $and$libresoc.v:150435$7415_Y
- attribute \src "libresoc.v:150437.18-150437.119"
- wire width 8 $and$libresoc.v:150437$7417_Y
- attribute \src "libresoc.v:150439.18-150439.119"
- wire width 8 $and$libresoc.v:150439$7419_Y
- attribute \src "libresoc.v:150441.18-150441.119"
- wire width 8 $and$libresoc.v:150441$7421_Y
- attribute \src "libresoc.v:150447.18-150447.106"
- wire $and$libresoc.v:150447$7428_Y
- attribute \src "libresoc.v:150452.18-150452.106"
- wire $and$libresoc.v:150452$7433_Y
- attribute \src "libresoc.v:150422.18-150422.100"
- wire $eq$libresoc.v:150422$7401_Y
- attribute \src "libresoc.v:150430.18-150430.119"
- wire $eq$libresoc.v:150430$7410_Y
- attribute \src "libresoc.v:150444.18-150444.121"
- wire $eq$libresoc.v:150444$7425_Y
- attribute \src "libresoc.v:150445.18-150445.121"
- wire $eq$libresoc.v:150445$7426_Y
- attribute \src "libresoc.v:150446.18-150446.111"
- wire $eq$libresoc.v:150446$7427_Y
- attribute \src "libresoc.v:150450.18-150450.121"
- wire $eq$libresoc.v:150450$7431_Y
- attribute \src "libresoc.v:150451.18-150451.114"
- wire $eq$libresoc.v:150451$7432_Y
- attribute \src "libresoc.v:150416.18-150416.95"
- wire width 64 $extend$libresoc.v:150416$7393_Y
- attribute \src "libresoc.v:150417.18-150417.95"
- wire width 64 $extend$libresoc.v:150417$7395_Y
- attribute \src "libresoc.v:150428.18-150428.100"
- wire width 64 $extend$libresoc.v:150428$7407_Y
- attribute \src "libresoc.v:150443.18-150443.109"
- wire width 65 $extend$libresoc.v:150443$7423_Y
- attribute \src "libresoc.v:150419.18-150419.121"
- wire $gt$libresoc.v:150419$7398_Y
- attribute \src "libresoc.v:150421.18-150421.99"
- wire $gt$libresoc.v:150421$7400_Y
- attribute \src "libresoc.v:150418.18-150418.121"
- wire $lt$libresoc.v:150418$7397_Y
- attribute \src "libresoc.v:150420.18-150420.99"
- wire $lt$libresoc.v:150420$7399_Y
- attribute \src "libresoc.v:150448.18-150448.112"
- wire $not$libresoc.v:150448$7429_Y
- attribute \src "libresoc.v:150449.18-150449.112"
- wire $not$libresoc.v:150449$7430_Y
- attribute \src "libresoc.v:150426.18-150426.106"
- wire $or$libresoc.v:150426$7405_Y
- attribute \src "libresoc.v:150416.18-150416.95"
- wire width 64 $pos$libresoc.v:150416$7394_Y
- attribute \src "libresoc.v:150417.18-150417.95"
- wire width 64 $pos$libresoc.v:150417$7396_Y
- attribute \src "libresoc.v:150428.18-150428.100"
- wire width 64 $pos$libresoc.v:150428$7408_Y
- attribute \src "libresoc.v:150443.18-150443.109"
- wire width 65 $pos$libresoc.v:150443$7424_Y
- attribute \src "libresoc.v:150424.18-150424.100"
- wire $reduce_or$libresoc.v:150424$7403_Y
- attribute \src "libresoc.v:150425.18-150425.113"
- wire $reduce_or$libresoc.v:150425$7404_Y
- attribute \src "libresoc.v:150432.18-150432.91"
- wire $reduce_or$libresoc.v:150432$7412_Y
- attribute \src "libresoc.v:150434.18-150434.91"
- wire $reduce_or$libresoc.v:150434$7414_Y
- attribute \src "libresoc.v:150436.18-150436.91"
- wire $reduce_or$libresoc.v:150436$7416_Y
- attribute \src "libresoc.v:150438.18-150438.91"
- wire $reduce_or$libresoc.v:150438$7418_Y
- attribute \src "libresoc.v:150440.18-150440.91"
- wire $reduce_or$libresoc.v:150440$7420_Y
- attribute \src "libresoc.v:150442.18-150442.91"
- wire $reduce_or$libresoc.v:150442$7422_Y
- attribute \src "libresoc.v:150427.18-150427.120"
- wire width 20 $sshl$libresoc.v:150427$7406_Y
+ attribute \src "libresoc.v:150093.18-150093.113"
+ wire width 65 $add$libresoc.v:150093$7357_Y
+ attribute \src "libresoc.v:150087.18-150087.108"
+ wire width 5 $and$libresoc.v:150087$7350_Y
+ attribute \src "libresoc.v:150095.18-150095.118"
+ wire width 8 $and$libresoc.v:150095$7359_Y
+ attribute \src "libresoc.v:150097.18-150097.118"
+ wire width 8 $and$libresoc.v:150097$7361_Y
+ attribute \src "libresoc.v:150099.18-150099.118"
+ wire width 8 $and$libresoc.v:150099$7363_Y
+ attribute \src "libresoc.v:150101.18-150101.119"
+ wire width 8 $and$libresoc.v:150101$7365_Y
+ attribute \src "libresoc.v:150103.18-150103.119"
+ wire width 8 $and$libresoc.v:150103$7367_Y
+ attribute \src "libresoc.v:150105.18-150105.119"
+ wire width 8 $and$libresoc.v:150105$7369_Y
+ attribute \src "libresoc.v:150111.18-150111.106"
+ wire $and$libresoc.v:150111$7376_Y
+ attribute \src "libresoc.v:150116.18-150116.106"
+ wire $and$libresoc.v:150116$7381_Y
+ attribute \src "libresoc.v:150086.18-150086.100"
+ wire $eq$libresoc.v:150086$7349_Y
+ attribute \src "libresoc.v:150094.18-150094.119"
+ wire $eq$libresoc.v:150094$7358_Y
+ attribute \src "libresoc.v:150108.18-150108.121"
+ wire $eq$libresoc.v:150108$7373_Y
+ attribute \src "libresoc.v:150109.18-150109.121"
+ wire $eq$libresoc.v:150109$7374_Y
+ attribute \src "libresoc.v:150110.18-150110.111"
+ wire $eq$libresoc.v:150110$7375_Y
+ attribute \src "libresoc.v:150114.18-150114.121"
+ wire $eq$libresoc.v:150114$7379_Y
+ attribute \src "libresoc.v:150115.18-150115.114"
+ wire $eq$libresoc.v:150115$7380_Y
+ attribute \src "libresoc.v:150080.18-150080.95"
+ wire width 64 $extend$libresoc.v:150080$7341_Y
+ attribute \src "libresoc.v:150081.18-150081.95"
+ wire width 64 $extend$libresoc.v:150081$7343_Y
+ attribute \src "libresoc.v:150092.18-150092.100"
+ wire width 64 $extend$libresoc.v:150092$7355_Y
+ attribute \src "libresoc.v:150107.18-150107.109"
+ wire width 65 $extend$libresoc.v:150107$7371_Y
+ attribute \src "libresoc.v:150083.18-150083.121"
+ wire $gt$libresoc.v:150083$7346_Y
+ attribute \src "libresoc.v:150085.18-150085.99"
+ wire $gt$libresoc.v:150085$7348_Y
+ attribute \src "libresoc.v:150082.18-150082.121"
+ wire $lt$libresoc.v:150082$7345_Y
+ attribute \src "libresoc.v:150084.18-150084.99"
+ wire $lt$libresoc.v:150084$7347_Y
+ attribute \src "libresoc.v:150112.18-150112.112"
+ wire $not$libresoc.v:150112$7377_Y
+ attribute \src "libresoc.v:150113.18-150113.112"
+ wire $not$libresoc.v:150113$7378_Y
+ attribute \src "libresoc.v:150090.18-150090.106"
+ wire $or$libresoc.v:150090$7353_Y
+ attribute \src "libresoc.v:150080.18-150080.95"
+ wire width 64 $pos$libresoc.v:150080$7342_Y
+ attribute \src "libresoc.v:150081.18-150081.95"
+ wire width 64 $pos$libresoc.v:150081$7344_Y
+ attribute \src "libresoc.v:150092.18-150092.100"
+ wire width 64 $pos$libresoc.v:150092$7356_Y
+ attribute \src "libresoc.v:150107.18-150107.109"
+ wire width 65 $pos$libresoc.v:150107$7372_Y
+ attribute \src "libresoc.v:150088.18-150088.100"
+ wire $reduce_or$libresoc.v:150088$7351_Y
+ attribute \src "libresoc.v:150089.18-150089.113"
+ wire $reduce_or$libresoc.v:150089$7352_Y
+ attribute \src "libresoc.v:150096.18-150096.91"
+ wire $reduce_or$libresoc.v:150096$7360_Y
+ attribute \src "libresoc.v:150098.18-150098.91"
+ wire $reduce_or$libresoc.v:150098$7362_Y
+ attribute \src "libresoc.v:150100.18-150100.91"
+ wire $reduce_or$libresoc.v:150100$7364_Y
+ attribute \src "libresoc.v:150102.18-150102.91"
+ wire $reduce_or$libresoc.v:150102$7366_Y
+ attribute \src "libresoc.v:150104.18-150104.91"
+ wire $reduce_or$libresoc.v:150104$7368_Y
+ attribute \src "libresoc.v:150106.18-150106.91"
+ wire $reduce_or$libresoc.v:150106$7370_Y
+ attribute \src "libresoc.v:150091.18-150091.120"
+ wire width 20 $sshl$libresoc.v:150091$7354_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire width 64 \$13
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire \gt_s
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160"
wire \gt_u
- attribute \src "libresoc.v:150041.7-150041.15"
+ attribute \src "libresoc.v:149705.7-149705.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
wire \lt_s
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \trapexc_$signal$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315"
- cell $add $add$libresoc.v:150429$7409
+ cell $add $add$libresoc.v:150093$7357
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \trap_op__cia
connect \B 3'100
- connect \Y $add$libresoc.v:150429$7409_Y
+ connect \Y $add$libresoc.v:150093$7357_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $and $and$libresoc.v:150423$7402
+ cell $and $and$libresoc.v:150087$7350
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \trap_bits
connect \B \to
- connect \Y $and$libresoc.v:150423$7402_Y
+ connect \Y $and$libresoc.v:150087$7350_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193"
- cell $and $and$libresoc.v:150431$7411
+ cell $and $and$libresoc.v:150095$7359
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 2'10
- connect \Y $and$libresoc.v:150431$7411_Y
+ connect \Y $and$libresoc.v:150095$7359_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
- cell $and $and$libresoc.v:150433$7413
+ cell $and $and$libresoc.v:150097$7361
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 1'1
- connect \Y $and$libresoc.v:150433$7413_Y
+ connect \Y $and$libresoc.v:150097$7361_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197"
- cell $and $and$libresoc.v:150435$7415
+ cell $and $and$libresoc.v:150099$7363
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 4'1000
- connect \Y $and$libresoc.v:150435$7415_Y
+ connect \Y $and$libresoc.v:150099$7363_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
- cell $and $and$libresoc.v:150437$7417
+ cell $and $and$libresoc.v:150101$7365
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 7'1000000
- connect \Y $and$libresoc.v:150437$7417_Y
+ connect \Y $and$libresoc.v:150101$7365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
- cell $and $and$libresoc.v:150439$7419
+ cell $and $and$libresoc.v:150103$7367
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 8'10000000
- connect \Y $and$libresoc.v:150439$7419_Y
+ connect \Y $and$libresoc.v:150103$7367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
- cell $and $and$libresoc.v:150441$7421
+ cell $and $and$libresoc.v:150105$7369
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 7'1000000
- connect \Y $and$libresoc.v:150441$7421_Y
+ connect \Y $and$libresoc.v:150105$7369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
- cell $and $and$libresoc.v:150447$7428
+ cell $and $and$libresoc.v:150111$7376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$79
connect \B \$81
- connect \Y $and$libresoc.v:150447$7428_Y
+ connect \Y $and$libresoc.v:150111$7376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296"
- cell $and $and$libresoc.v:150452$7433
+ cell $and $and$libresoc.v:150116$7381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$89
connect \B \$91
- connect \Y $and$libresoc.v:150452$7433_Y
+ connect \Y $and$libresoc.v:150116$7381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- cell $eq $eq$libresoc.v:150422$7401
+ cell $eq $eq$libresoc.v:150086$7349
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $eq$libresoc.v:150422$7401_Y
+ connect \Y $eq$libresoc.v:150086$7349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190"
- cell $eq $eq$libresoc.v:150430$7410
+ cell $eq $eq$libresoc.v:150094$7358
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__traptype
connect \B 1'0
- connect \Y $eq$libresoc.v:150430$7410_Y
+ connect \Y $eq$libresoc.v:150094$7358_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234"
- cell $eq $eq$libresoc.v:150444$7425
+ cell $eq $eq$libresoc.v:150108$7373
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__insn_type
connect \B 7'1001000
- connect \Y $eq$libresoc.v:150444$7425_Y
+ connect \Y $eq$libresoc.v:150108$7373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240"
- cell $eq $eq$libresoc.v:150445$7426
+ cell $eq $eq$libresoc.v:150109$7374
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__msr [34:32]
connect \B 3'010
- connect \Y $eq$libresoc.v:150445$7426_Y
+ connect \Y $eq$libresoc.v:150109$7374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
- cell $eq $eq$libresoc.v:150446$7427
+ cell $eq $eq$libresoc.v:150110$7375
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [34:32]
connect \B 3'000
- connect \Y $eq$libresoc.v:150446$7427_Y
+ connect \Y $eq$libresoc.v:150110$7375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295"
- cell $eq $eq$libresoc.v:150450$7431
+ cell $eq $eq$libresoc.v:150114$7379
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__msr [34:32]
connect \B 3'010
- connect \Y $eq$libresoc.v:150450$7431_Y
+ connect \Y $eq$libresoc.v:150114$7379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296"
- cell $eq $eq$libresoc.v:150451$7432
+ cell $eq $eq$libresoc.v:150115$7380
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast2 [34:32]
connect \B 3'000
- connect \Y $eq$libresoc.v:150451$7432_Y
+ connect \Y $eq$libresoc.v:150115$7380_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:150416$7393
+ cell $pos $extend$libresoc.v:150080$7341
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \ra [31:0]
- connect \Y $extend$libresoc.v:150416$7393_Y
+ connect \Y $extend$libresoc.v:150080$7341_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:150417$7395
+ cell $pos $extend$libresoc.v:150081$7343
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \rb [31:0]
- connect \Y $extend$libresoc.v:150417$7395_Y
+ connect \Y $extend$libresoc.v:150081$7343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $pos $extend$libresoc.v:150428$7407
+ cell $pos $extend$libresoc.v:150092$7355
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \Y_WIDTH 64
connect \A \$36
- connect \Y $extend$libresoc.v:150428$7407_Y
+ connect \Y $extend$libresoc.v:150092$7355_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $extend$libresoc.v:150443$7423
+ cell $pos $extend$libresoc.v:150107$7371
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \trap_op__msr
- connect \Y $extend$libresoc.v:150443$7423_Y
+ connect \Y $extend$libresoc.v:150107$7371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
- cell $gt $gt$libresoc.v:150419$7398
+ cell $gt $gt$libresoc.v:150083$7346
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $gt$libresoc.v:150419$7398_Y
+ connect \Y $gt$libresoc.v:150083$7346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166"
- cell $gt $gt$libresoc.v:150421$7400
+ cell $gt $gt$libresoc.v:150085$7348
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $gt$libresoc.v:150421$7400_Y
+ connect \Y $gt$libresoc.v:150085$7348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
- cell $lt $lt$libresoc.v:150418$7397
+ cell $lt $lt$libresoc.v:150082$7345
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $lt$libresoc.v:150418$7397_Y
+ connect \Y $lt$libresoc.v:150082$7345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165"
- cell $lt $lt$libresoc.v:150420$7399
+ cell $lt $lt$libresoc.v:150084$7347
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $lt$libresoc.v:150420$7399_Y
+ connect \Y $lt$libresoc.v:150084$7347_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256"
- cell $not $not$libresoc.v:150448$7429
+ cell $not $not$libresoc.v:150112$7377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \trap_op__msr [60]
- connect \Y $not$libresoc.v:150448$7429_Y
+ connect \Y $not$libresoc.v:150112$7377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
- cell $not $not$libresoc.v:150449$7430
+ cell $not $not$libresoc.v:150113$7378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \trap_op__insn [9]
- connect \Y $not$libresoc.v:150449$7430_Y
+ connect \Y $not$libresoc.v:150113$7378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $or $or$libresoc.v:150426$7405
+ cell $or $or$libresoc.v:150090$7353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$27
connect \B \$31
- connect \Y $or$libresoc.v:150426$7405_Y
+ connect \Y $or$libresoc.v:150090$7353_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:150416$7394
+ cell $pos $pos$libresoc.v:150080$7342
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:150416$7393_Y
- connect \Y $pos$libresoc.v:150416$7394_Y
+ connect \A $extend$libresoc.v:150080$7341_Y
+ connect \Y $pos$libresoc.v:150080$7342_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:150417$7396
+ cell $pos $pos$libresoc.v:150081$7344
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:150417$7395_Y
- connect \Y $pos$libresoc.v:150417$7396_Y
+ connect \A $extend$libresoc.v:150081$7343_Y
+ connect \Y $pos$libresoc.v:150081$7344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $pos $pos$libresoc.v:150428$7408
+ cell $pos $pos$libresoc.v:150092$7356
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:150428$7407_Y
- connect \Y $pos$libresoc.v:150428$7408_Y
+ connect \A $extend$libresoc.v:150092$7355_Y
+ connect \Y $pos$libresoc.v:150092$7356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $pos$libresoc.v:150443$7424
+ cell $pos $pos$libresoc.v:150107$7372
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:150443$7423_Y
- connect \Y $pos$libresoc.v:150443$7424_Y
+ connect \A $extend$libresoc.v:150107$7371_Y
+ connect \Y $pos$libresoc.v:150107$7372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $reduce_or $reduce_or$libresoc.v:150424$7403
+ cell $reduce_or $reduce_or$libresoc.v:150088$7351
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $reduce_or$libresoc.v:150424$7403_Y
+ connect \Y $reduce_or$libresoc.v:150088$7351_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $reduce_or $reduce_or$libresoc.v:150425$7404
+ cell $reduce_or $reduce_or$libresoc.v:150089$7352
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \trap_op__traptype
- connect \Y $reduce_or$libresoc.v:150425$7404_Y
+ connect \Y $reduce_or$libresoc.v:150089$7352_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150432$7412
+ cell $reduce_or $reduce_or$libresoc.v:150096$7360
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$45
- connect \Y $reduce_or$libresoc.v:150432$7412_Y
+ connect \Y $reduce_or$libresoc.v:150096$7360_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150434$7414
+ cell $reduce_or $reduce_or$libresoc.v:150098$7362
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$49
- connect \Y $reduce_or$libresoc.v:150434$7414_Y
+ connect \Y $reduce_or$libresoc.v:150098$7362_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150436$7416
+ cell $reduce_or $reduce_or$libresoc.v:150100$7364
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$53
- connect \Y $reduce_or$libresoc.v:150436$7416_Y
+ connect \Y $reduce_or$libresoc.v:150100$7364_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150438$7418
+ cell $reduce_or $reduce_or$libresoc.v:150102$7366
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$57
- connect \Y $reduce_or$libresoc.v:150438$7418_Y
+ connect \Y $reduce_or$libresoc.v:150102$7366_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150440$7420
+ cell $reduce_or $reduce_or$libresoc.v:150104$7368
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$64
- connect \Y $reduce_or$libresoc.v:150440$7420_Y
+ connect \Y $reduce_or$libresoc.v:150104$7368_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:150442$7422
+ cell $reduce_or $reduce_or$libresoc.v:150106$7370
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$72
- connect \Y $reduce_or$libresoc.v:150442$7422_Y
+ connect \Y $reduce_or$libresoc.v:150106$7370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $sshl $sshl$libresoc.v:150427$7406
+ cell $sshl $sshl$libresoc.v:150091$7354
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \trap_op__trapaddr
connect \B 3'100
- connect \Y $sshl$libresoc.v:150427$7406_Y
+ connect \Y $sshl$libresoc.v:150091$7354_Y
end
- attribute \src "libresoc.v:150041.7-150041.20"
- process $proc$libresoc.v:150041$7494
+ attribute \src "libresoc.v:149705.7-149705.20"
+ process $proc$libresoc.v:149705$7442
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:150453.3-150464.6"
- process $proc$libresoc.v:150453$7434
+ attribute \src "libresoc.v:150117.3-150128.6"
+ process $proc$libresoc.v:150117$7382
assign { } { }
assign $0\a_s[63:0] $1\a_s[63:0]
- attribute \src "libresoc.v:150454.5-150454.29"
+ attribute \src "libresoc.v:150118.5-150118.29"
switch \initial
- attribute \src "libresoc.v:150454.9-150454.17"
+ attribute \src "libresoc.v:150118.9-150118.17"
case 1'1
case
end
sync always
update \a_s $0\a_s[63:0]
end
- attribute \src "libresoc.v:150465.3-150496.6"
- process $proc$libresoc.v:150465$7435
+ attribute \src "libresoc.v:150129.3-150160.6"
+ process $proc$libresoc.v:150129$7383
assign { } { }
assign { } { }
assign $0\nia[63:0] $1\nia[63:0]
- attribute \src "libresoc.v:150466.5-150466.29"
+ attribute \src "libresoc.v:150130.5-150130.29"
switch \initial
- attribute \src "libresoc.v:150466.9-150466.17"
+ attribute \src "libresoc.v:150130.9-150130.17"
case 1'1
case
end
sync always
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:150497.3-150528.6"
- process $proc$libresoc.v:150497$7436
+ attribute \src "libresoc.v:150161.3-150192.6"
+ process $proc$libresoc.v:150161$7384
assign { } { }
assign { } { }
assign $0\nia_ok[0:0] $1\nia_ok[0:0]
- attribute \src "libresoc.v:150498.5-150498.29"
+ attribute \src "libresoc.v:150162.5-150162.29"
switch \initial
- attribute \src "libresoc.v:150498.9-150498.17"
+ attribute \src "libresoc.v:150162.9-150162.17"
case 1'1
case
end
sync always
update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:150529.3-150560.6"
- process $proc$libresoc.v:150529$7437
+ attribute \src "libresoc.v:150193.3-150224.6"
+ process $proc$libresoc.v:150193$7385
assign { } { }
assign { } { }
- assign $0\fast1$11[63:0]$7438 $1\fast1$11[63:0]$7439
- attribute \src "libresoc.v:150530.5-150530.29"
+ assign $0\fast1$11[63:0]$7386 $1\fast1$11[63:0]$7387
+ attribute \src "libresoc.v:150194.5-150194.29"
switch \initial
- attribute \src "libresoc.v:150530.9-150530.17"
+ attribute \src "libresoc.v:150194.9-150194.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0111111
assign { } { }
- assign $1\fast1$11[63:0]$7439 $2\fast1$11[63:0]$7440
+ assign $1\fast1$11[63:0]$7387 $2\fast1$11[63:0]$7388
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1$11[63:0]$7440 \trap_op__cia
+ assign $2\fast1$11[63:0]$7388 \trap_op__cia
case
- assign $2\fast1$11[63:0]$7440 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast1$11[63:0]$7388 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
case 7'1001000 , 7'1001010
- assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000111
- assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000110
- assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1001001
assign { } { }
- assign $1\fast1$11[63:0]$7439 \$39 [63:0]
+ assign $1\fast1$11[63:0]$7387 \$39 [63:0]
case
- assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast1$11 $0\fast1$11[63:0]$7438
+ update \fast1$11 $0\fast1$11[63:0]$7386
end
- attribute \src "libresoc.v:150561.3-150592.6"
- process $proc$libresoc.v:150561$7441
+ attribute \src "libresoc.v:150225.3-150256.6"
+ process $proc$libresoc.v:150225$7389
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:150562.5-150562.29"
+ attribute \src "libresoc.v:150226.5-150226.29"
switch \initial
- attribute \src "libresoc.v:150562.9-150562.17"
+ attribute \src "libresoc.v:150226.9-150226.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:150593.3-150675.6"
- process $proc$libresoc.v:150593$7442
+ attribute \src "libresoc.v:150257.3-150339.6"
+ process $proc$libresoc.v:150257$7390
assign { } { }
assign { } { }
- assign $0\fast2$12[63:0]$7443 $1\fast2$12[63:0]$7444
- attribute \src "libresoc.v:150594.5-150594.29"
+ assign $0\fast2$12[63:0]$7391 $1\fast2$12[63:0]$7392
+ attribute \src "libresoc.v:150258.5-150258.29"
switch \initial
- attribute \src "libresoc.v:150594.9-150594.17"
+ attribute \src "libresoc.v:150258.9-150258.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0111111
assign { } { }
- assign $1\fast2$12[63:0]$7444 $2\fast2$12[63:0]$7445
+ assign $1\fast2$12[63:0]$7392 $2\fast2$12[63:0]$7393
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign { $2\fast2$12[63:0]$7445 [29] $2\fast2$12[63:0]$7445 [27] $2\fast2$12[63:0]$7445 [21] } 3'000
- assign $2\fast2$12[63:0]$7445 [15:0] \trap_op__msr [15:0]
- assign $2\fast2$12[63:0]$7445 [26:22] \trap_op__msr [26:22]
- assign $2\fast2$12[63:0]$7445 [63:31] \trap_op__msr [63:31]
- assign $2\fast2$12[63:0]$7445 [17] $3\fast2$12[17:17]$7446
- assign { } { }
- assign $2\fast2$12[63:0]$7445 [20] $5\fast2$12[20:20]$7448
- assign $2\fast2$12[63:0]$7445 [16] $6\fast2$12[16:16]$7449
- assign $2\fast2$12[63:0]$7445 [18] $7\fast2$12[19:18]$7450 [0]
- assign $2\fast2$12[63:0]$7445 [28] $8\fast2$12[28:28]$7451
- assign $2\fast2$12[63:0]$7445 [30] $9\fast2$12[30:30]$7452
- assign $2\fast2$12[63:0]$7445 [19] $10\fast2$12[19:19]$7453
+ assign { $2\fast2$12[63:0]$7393 [29] $2\fast2$12[63:0]$7393 [27] $2\fast2$12[63:0]$7393 [21] } 3'000
+ assign $2\fast2$12[63:0]$7393 [15:0] \trap_op__msr [15:0]
+ assign $2\fast2$12[63:0]$7393 [26:22] \trap_op__msr [26:22]
+ assign $2\fast2$12[63:0]$7393 [63:31] \trap_op__msr [63:31]
+ assign $2\fast2$12[63:0]$7393 [17] $3\fast2$12[17:17]$7394
+ assign { } { }
+ assign $2\fast2$12[63:0]$7393 [20] $5\fast2$12[20:20]$7396
+ assign $2\fast2$12[63:0]$7393 [16] $6\fast2$12[16:16]$7397
+ assign $2\fast2$12[63:0]$7393 [18] $7\fast2$12[19:18]$7398 [0]
+ assign $2\fast2$12[63:0]$7393 [28] $8\fast2$12[28:28]$7399
+ assign $2\fast2$12[63:0]$7393 [30] $9\fast2$12[30:30]$7400
+ assign $2\fast2$12[63:0]$7393 [19] $10\fast2$12[19:19]$7401
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190"
switch \$42
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fast2$12[17:17]$7446 1'1
+ assign $3\fast2$12[17:17]$7394 1'1
case
- assign $3\fast2$12[17:17]$7446 1'0
+ assign $3\fast2$12[17:17]$7394 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193"
switch \$44
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fast2$12[18:18]$7447 1'1
+ assign $4\fast2$12[18:18]$7395 1'1
case
- assign $4\fast2$12[18:18]$7447 1'0
+ assign $4\fast2$12[18:18]$7395 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
switch \$48
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fast2$12[20:20]$7448 1'1
+ assign $5\fast2$12[20:20]$7396 1'1
case
- assign $5\fast2$12[20:20]$7448 1'0
+ assign $5\fast2$12[20:20]$7396 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197"
switch \$52
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\fast2$12[16:16]$7449 1'1
+ assign $6\fast2$12[16:16]$7397 1'1
case
- assign $6\fast2$12[16:16]$7449 1'0
+ assign $6\fast2$12[16:16]$7397 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
switch \$56
assign { } { }
assign { } { }
assign { } { }
- assign $9\fast2$12[30:30]$7452 \trapexc_$signal
- assign $8\fast2$12[28:28]$7451 \trapexc_$signal$60
- assign $7\fast2$12[19:18]$7450 [1] \trapexc_$signal$61
- assign $7\fast2$12[19:18]$7450 [0] \trapexc_$signal$62
+ assign $9\fast2$12[30:30]$7400 \trapexc_$signal
+ assign $8\fast2$12[28:28]$7399 \trapexc_$signal$60
+ assign $7\fast2$12[19:18]$7398 [1] \trapexc_$signal$61
+ assign $7\fast2$12[19:18]$7398 [0] \trapexc_$signal$62
case
- assign $7\fast2$12[19:18]$7450 { 1'0 $4\fast2$12[18:18]$7447 }
- assign $8\fast2$12[28:28]$7451 1'0
- assign $9\fast2$12[30:30]$7452 1'0
+ assign $7\fast2$12[19:18]$7398 { 1'0 $4\fast2$12[18:18]$7395 }
+ assign $8\fast2$12[28:28]$7399 1'0
+ assign $9\fast2$12[30:30]$7400 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
switch \$63
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $10\fast2$12[19:19]$7453 1'1
+ assign $10\fast2$12[19:19]$7401 1'1
case
- assign $10\fast2$12[19:19]$7453 $7\fast2$12[19:18]$7450 [1]
+ assign $10\fast2$12[19:19]$7401 $7\fast2$12[19:18]$7398 [1]
end
case
- assign $2\fast2$12[63:0]$7445 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast2$12[63:0]$7393 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
case 7'1001000 , 7'1001010
- assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000111
- assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000110
- assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1001001
assign { } { }
- assign { $1\fast2$12[63:0]$7444 [30:27] $1\fast2$12[63:0]$7444 [21:16] } 10'0000000000
- assign $1\fast2$12[63:0]$7444 [15:0] \trap_op__msr [15:0]
- assign $1\fast2$12[63:0]$7444 [26:22] \trap_op__msr [26:22]
- assign $1\fast2$12[63:0]$7444 [63:31] \trap_op__msr [63:31]
+ assign { $1\fast2$12[63:0]$7392 [30:27] $1\fast2$12[63:0]$7392 [21:16] } 10'0000000000
+ assign $1\fast2$12[63:0]$7392 [15:0] \trap_op__msr [15:0]
+ assign $1\fast2$12[63:0]$7392 [26:22] \trap_op__msr [26:22]
+ assign $1\fast2$12[63:0]$7392 [63:31] \trap_op__msr [63:31]
case
- assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast2$12 $0\fast2$12[63:0]$7443
+ update \fast2$12 $0\fast2$12[63:0]$7391
end
- attribute \src "libresoc.v:150676.3-150707.6"
- process $proc$libresoc.v:150676$7454
+ attribute \src "libresoc.v:150340.3-150371.6"
+ process $proc$libresoc.v:150340$7402
assign { } { }
assign { } { }
assign $0\fast2_ok[0:0] $1\fast2_ok[0:0]
- attribute \src "libresoc.v:150677.5-150677.29"
+ attribute \src "libresoc.v:150341.5-150341.29"
switch \initial
- attribute \src "libresoc.v:150677.9-150677.17"
+ attribute \src "libresoc.v:150341.9-150341.17"
case 1'1
case
end
sync always
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:150708.3-150735.6"
- process $proc$libresoc.v:150708$7455
+ attribute \src "libresoc.v:150372.3-150399.6"
+ process $proc$libresoc.v:150372$7403
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trapexc_$signal[0:0]$7456 $1\trapexc_$signal[0:0]$7464
- assign $0\trapexc_$signal$60[0:0]$7457 $1\trapexc_$signal$60[0:0]$7465
- assign $0\trapexc_$signal$61[0:0]$7458 $1\trapexc_$signal$61[0:0]$7466
- assign $0\trapexc_$signal$62[0:0]$7459 $1\trapexc_$signal$62[0:0]$7467
- assign $0\trapexc_$signal$67[0:0]$7460 $1\trapexc_$signal$67[0:0]$7468
- assign $0\trapexc_$signal$68[0:0]$7461 $1\trapexc_$signal$68[0:0]$7469
- assign $0\trapexc_$signal$69[0:0]$7462 $1\trapexc_$signal$69[0:0]$7470
- assign $0\trapexc_$signal$70[0:0]$7463 $1\trapexc_$signal$70[0:0]$7471
- attribute \src "libresoc.v:150709.5-150709.29"
+ assign $0\trapexc_$signal[0:0]$7404 $1\trapexc_$signal[0:0]$7412
+ assign $0\trapexc_$signal$60[0:0]$7405 $1\trapexc_$signal$60[0:0]$7413
+ assign $0\trapexc_$signal$61[0:0]$7406 $1\trapexc_$signal$61[0:0]$7414
+ assign $0\trapexc_$signal$62[0:0]$7407 $1\trapexc_$signal$62[0:0]$7415
+ assign $0\trapexc_$signal$67[0:0]$7408 $1\trapexc_$signal$67[0:0]$7416
+ assign $0\trapexc_$signal$68[0:0]$7409 $1\trapexc_$signal$68[0:0]$7417
+ assign $0\trapexc_$signal$69[0:0]$7410 $1\trapexc_$signal$69[0:0]$7418
+ assign $0\trapexc_$signal$70[0:0]$7411 $1\trapexc_$signal$70[0:0]$7419
+ attribute \src "libresoc.v:150373.5-150373.29"
switch \initial
- attribute \src "libresoc.v:150709.9-150709.17"
+ attribute \src "libresoc.v:150373.9-150373.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\trapexc_$signal[0:0]$7464 $2\trapexc_$signal[0:0]$7472
- assign $1\trapexc_$signal$60[0:0]$7465 $2\trapexc_$signal$60[0:0]$7473
- assign $1\trapexc_$signal$61[0:0]$7466 $2\trapexc_$signal$61[0:0]$7474
- assign $1\trapexc_$signal$62[0:0]$7467 $2\trapexc_$signal$62[0:0]$7475
- assign $1\trapexc_$signal$67[0:0]$7468 $2\trapexc_$signal$67[0:0]$7476
- assign $1\trapexc_$signal$68[0:0]$7469 $2\trapexc_$signal$68[0:0]$7477
- assign $1\trapexc_$signal$69[0:0]$7470 $2\trapexc_$signal$69[0:0]$7478
- assign $1\trapexc_$signal$70[0:0]$7471 $2\trapexc_$signal$70[0:0]$7479
+ assign $1\trapexc_$signal[0:0]$7412 $2\trapexc_$signal[0:0]$7420
+ assign $1\trapexc_$signal$60[0:0]$7413 $2\trapexc_$signal$60[0:0]$7421
+ assign $1\trapexc_$signal$61[0:0]$7414 $2\trapexc_$signal$61[0:0]$7422
+ assign $1\trapexc_$signal$62[0:0]$7415 $2\trapexc_$signal$62[0:0]$7423
+ assign $1\trapexc_$signal$67[0:0]$7416 $2\trapexc_$signal$67[0:0]$7424
+ assign $1\trapexc_$signal$68[0:0]$7417 $2\trapexc_$signal$68[0:0]$7425
+ assign $1\trapexc_$signal$69[0:0]$7418 $2\trapexc_$signal$69[0:0]$7426
+ assign $1\trapexc_$signal$70[0:0]$7419 $2\trapexc_$signal$70[0:0]$7427
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\trapexc_$signal[0:0]$7472 $3\trapexc_$signal[0:0]$7480
- assign $2\trapexc_$signal$60[0:0]$7473 $3\trapexc_$signal$60[0:0]$7481
- assign $2\trapexc_$signal$61[0:0]$7474 $3\trapexc_$signal$61[0:0]$7482
- assign $2\trapexc_$signal$62[0:0]$7475 $3\trapexc_$signal$62[0:0]$7483
- assign $2\trapexc_$signal$67[0:0]$7476 $3\trapexc_$signal$67[0:0]$7484
- assign $2\trapexc_$signal$68[0:0]$7477 $3\trapexc_$signal$68[0:0]$7485
- assign $2\trapexc_$signal$69[0:0]$7478 $3\trapexc_$signal$69[0:0]$7486
- assign $2\trapexc_$signal$70[0:0]$7479 $3\trapexc_$signal$70[0:0]$7487
+ assign $2\trapexc_$signal[0:0]$7420 $3\trapexc_$signal[0:0]$7428
+ assign $2\trapexc_$signal$60[0:0]$7421 $3\trapexc_$signal$60[0:0]$7429
+ assign $2\trapexc_$signal$61[0:0]$7422 $3\trapexc_$signal$61[0:0]$7430
+ assign $2\trapexc_$signal$62[0:0]$7423 $3\trapexc_$signal$62[0:0]$7431
+ assign $2\trapexc_$signal$67[0:0]$7424 $3\trapexc_$signal$67[0:0]$7432
+ assign $2\trapexc_$signal$68[0:0]$7425 $3\trapexc_$signal$68[0:0]$7433
+ assign $2\trapexc_$signal$69[0:0]$7426 $3\trapexc_$signal$69[0:0]$7434
+ assign $2\trapexc_$signal$70[0:0]$7427 $3\trapexc_$signal$70[0:0]$7435
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
switch \$71
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $3\trapexc_$signal$70[0:0]$7487 $3\trapexc_$signal$62[0:0]$7483 $3\trapexc_$signal$60[0:0]$7481 $3\trapexc_$signal$61[0:0]$7482 $3\trapexc_$signal[0:0]$7480 $3\trapexc_$signal$69[0:0]$7486 $3\trapexc_$signal$68[0:0]$7485 $3\trapexc_$signal$67[0:0]$7484 } \trap_op__ldst_exc
+ assign { $3\trapexc_$signal$70[0:0]$7435 $3\trapexc_$signal$62[0:0]$7431 $3\trapexc_$signal$60[0:0]$7429 $3\trapexc_$signal$61[0:0]$7430 $3\trapexc_$signal[0:0]$7428 $3\trapexc_$signal$69[0:0]$7434 $3\trapexc_$signal$68[0:0]$7433 $3\trapexc_$signal$67[0:0]$7432 } \trap_op__ldst_exc
case
- assign $3\trapexc_$signal[0:0]$7480 1'0
- assign $3\trapexc_$signal$60[0:0]$7481 1'0
- assign $3\trapexc_$signal$61[0:0]$7482 1'0
- assign $3\trapexc_$signal$62[0:0]$7483 1'0
- assign $3\trapexc_$signal$67[0:0]$7484 1'0
- assign $3\trapexc_$signal$68[0:0]$7485 1'0
- assign $3\trapexc_$signal$69[0:0]$7486 1'0
- assign $3\trapexc_$signal$70[0:0]$7487 1'0
+ assign $3\trapexc_$signal[0:0]$7428 1'0
+ assign $3\trapexc_$signal$60[0:0]$7429 1'0
+ assign $3\trapexc_$signal$61[0:0]$7430 1'0
+ assign $3\trapexc_$signal$62[0:0]$7431 1'0
+ assign $3\trapexc_$signal$67[0:0]$7432 1'0
+ assign $3\trapexc_$signal$68[0:0]$7433 1'0
+ assign $3\trapexc_$signal$69[0:0]$7434 1'0
+ assign $3\trapexc_$signal$70[0:0]$7435 1'0
end
case
- assign $2\trapexc_$signal[0:0]$7472 1'0
- assign $2\trapexc_$signal$60[0:0]$7473 1'0
- assign $2\trapexc_$signal$61[0:0]$7474 1'0
- assign $2\trapexc_$signal$62[0:0]$7475 1'0
- assign $2\trapexc_$signal$67[0:0]$7476 1'0
- assign $2\trapexc_$signal$68[0:0]$7477 1'0
- assign $2\trapexc_$signal$69[0:0]$7478 1'0
- assign $2\trapexc_$signal$70[0:0]$7479 1'0
- end
- case
- assign $1\trapexc_$signal[0:0]$7464 1'0
- assign $1\trapexc_$signal$60[0:0]$7465 1'0
- assign $1\trapexc_$signal$61[0:0]$7466 1'0
- assign $1\trapexc_$signal$62[0:0]$7467 1'0
- assign $1\trapexc_$signal$67[0:0]$7468 1'0
- assign $1\trapexc_$signal$68[0:0]$7469 1'0
- assign $1\trapexc_$signal$69[0:0]$7470 1'0
- assign $1\trapexc_$signal$70[0:0]$7471 1'0
- end
- sync always
- update \trapexc_$signal $0\trapexc_$signal[0:0]$7456
- update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7457
- update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7458
- update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7459
- update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7460
- update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7461
- update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7462
- update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7463
- end
- attribute \src "libresoc.v:150736.3-150747.6"
- process $proc$libresoc.v:150736$7488
+ assign $2\trapexc_$signal[0:0]$7420 1'0
+ assign $2\trapexc_$signal$60[0:0]$7421 1'0
+ assign $2\trapexc_$signal$61[0:0]$7422 1'0
+ assign $2\trapexc_$signal$62[0:0]$7423 1'0
+ assign $2\trapexc_$signal$67[0:0]$7424 1'0
+ assign $2\trapexc_$signal$68[0:0]$7425 1'0
+ assign $2\trapexc_$signal$69[0:0]$7426 1'0
+ assign $2\trapexc_$signal$70[0:0]$7427 1'0
+ end
+ case
+ assign $1\trapexc_$signal[0:0]$7412 1'0
+ assign $1\trapexc_$signal$60[0:0]$7413 1'0
+ assign $1\trapexc_$signal$61[0:0]$7414 1'0
+ assign $1\trapexc_$signal$62[0:0]$7415 1'0
+ assign $1\trapexc_$signal$67[0:0]$7416 1'0
+ assign $1\trapexc_$signal$68[0:0]$7417 1'0
+ assign $1\trapexc_$signal$69[0:0]$7418 1'0
+ assign $1\trapexc_$signal$70[0:0]$7419 1'0
+ end
+ sync always
+ update \trapexc_$signal $0\trapexc_$signal[0:0]$7404
+ update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7405
+ update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7406
+ update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7407
+ update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7408
+ update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7409
+ update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7410
+ update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7411
+ end
+ attribute \src "libresoc.v:150400.3-150411.6"
+ process $proc$libresoc.v:150400$7436
assign { } { }
assign $0\b_s[63:0] $1\b_s[63:0]
- attribute \src "libresoc.v:150737.5-150737.29"
+ attribute \src "libresoc.v:150401.5-150401.29"
switch \initial
- attribute \src "libresoc.v:150737.9-150737.17"
+ attribute \src "libresoc.v:150401.9-150401.17"
case 1'1
case
end
sync always
update \b_s $0\b_s[63:0]
end
- attribute \src "libresoc.v:150748.3-150916.6"
- process $proc$libresoc.v:150748$7489
+ attribute \src "libresoc.v:150412.3-150580.6"
+ process $proc$libresoc.v:150412$7437
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\msr[63:0] $1\msr[63:0]
assign $0\msr_ok[0:0] $1\msr_ok[0:0]
- attribute \src "libresoc.v:150749.5-150749.29"
+ attribute \src "libresoc.v:150413.5-150413.29"
switch \initial
- attribute \src "libresoc.v:150749.9-150749.17"
+ attribute \src "libresoc.v:150413.9-150413.17"
case 1'1
case
end
update \msr $0\msr[63:0]
update \msr_ok $0\msr_ok[0:0]
end
- attribute \src "libresoc.v:150917.3-150935.6"
- process $proc$libresoc.v:150917$7490
+ attribute \src "libresoc.v:150581.3-150599.6"
+ process $proc$libresoc.v:150581$7438
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:150918.5-150918.29"
+ attribute \src "libresoc.v:150582.5-150582.29"
switch \initial
- attribute \src "libresoc.v:150918.9-150918.17"
+ attribute \src "libresoc.v:150582.9-150582.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:150936.3-150954.6"
- process $proc$libresoc.v:150936$7491
+ attribute \src "libresoc.v:150600.3-150618.6"
+ process $proc$libresoc.v:150600$7439
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:150937.5-150937.29"
+ attribute \src "libresoc.v:150601.5-150601.29"
switch \initial
- attribute \src "libresoc.v:150937.9-150937.17"
+ attribute \src "libresoc.v:150601.9-150601.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:150955.3-150966.6"
- process $proc$libresoc.v:150955$7492
+ attribute \src "libresoc.v:150619.3-150630.6"
+ process $proc$libresoc.v:150619$7440
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:150956.5-150956.29"
+ attribute \src "libresoc.v:150620.5-150620.29"
switch \initial
- attribute \src "libresoc.v:150956.9-150956.17"
+ attribute \src "libresoc.v:150620.9-150620.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:150967.3-150978.6"
- process $proc$libresoc.v:150967$7493
+ attribute \src "libresoc.v:150631.3-150642.6"
+ process $proc$libresoc.v:150631$7441
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:150968.5-150968.29"
+ attribute \src "libresoc.v:150632.5-150632.29"
switch \initial
- attribute \src "libresoc.v:150968.9-150968.17"
+ attribute \src "libresoc.v:150632.9-150632.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- connect \$13 $pos$libresoc.v:150416$7394_Y
- connect \$15 $pos$libresoc.v:150417$7396_Y
- connect \$17 $lt$libresoc.v:150418$7397_Y
- connect \$19 $gt$libresoc.v:150419$7398_Y
- connect \$21 $lt$libresoc.v:150420$7399_Y
- connect \$23 $gt$libresoc.v:150421$7400_Y
- connect \$25 $eq$libresoc.v:150422$7401_Y
- connect \$28 $and$libresoc.v:150423$7402_Y
- connect \$27 $reduce_or$libresoc.v:150424$7403_Y
- connect \$31 $reduce_or$libresoc.v:150425$7404_Y
- connect \$33 $or$libresoc.v:150426$7405_Y
- connect \$36 $sshl$libresoc.v:150427$7406_Y
- connect \$35 $pos$libresoc.v:150428$7408_Y
- connect \$40 $add$libresoc.v:150429$7409_Y
- connect \$42 $eq$libresoc.v:150430$7410_Y
- connect \$45 $and$libresoc.v:150431$7411_Y
- connect \$44 $reduce_or$libresoc.v:150432$7412_Y
- connect \$49 $and$libresoc.v:150433$7413_Y
- connect \$48 $reduce_or$libresoc.v:150434$7414_Y
- connect \$53 $and$libresoc.v:150435$7415_Y
- connect \$52 $reduce_or$libresoc.v:150436$7416_Y
- connect \$57 $and$libresoc.v:150437$7417_Y
- connect \$56 $reduce_or$libresoc.v:150438$7418_Y
- connect \$64 $and$libresoc.v:150439$7419_Y
- connect \$63 $reduce_or$libresoc.v:150440$7420_Y
- connect \$72 $and$libresoc.v:150441$7421_Y
- connect \$71 $reduce_or$libresoc.v:150442$7422_Y
- connect \$75 $pos$libresoc.v:150443$7424_Y
- connect \$77 $eq$libresoc.v:150444$7425_Y
- connect \$79 $eq$libresoc.v:150445$7426_Y
- connect \$81 $eq$libresoc.v:150446$7427_Y
- connect \$83 $and$libresoc.v:150447$7428_Y
- connect \$85 $not$libresoc.v:150448$7429_Y
- connect \$87 $not$libresoc.v:150449$7430_Y
- connect \$89 $eq$libresoc.v:150450$7431_Y
- connect \$91 $eq$libresoc.v:150451$7432_Y
- connect \$93 $and$libresoc.v:150452$7433_Y
+ connect \$13 $pos$libresoc.v:150080$7342_Y
+ connect \$15 $pos$libresoc.v:150081$7344_Y
+ connect \$17 $lt$libresoc.v:150082$7345_Y
+ connect \$19 $gt$libresoc.v:150083$7346_Y
+ connect \$21 $lt$libresoc.v:150084$7347_Y
+ connect \$23 $gt$libresoc.v:150085$7348_Y
+ connect \$25 $eq$libresoc.v:150086$7349_Y
+ connect \$28 $and$libresoc.v:150087$7350_Y
+ connect \$27 $reduce_or$libresoc.v:150088$7351_Y
+ connect \$31 $reduce_or$libresoc.v:150089$7352_Y
+ connect \$33 $or$libresoc.v:150090$7353_Y
+ connect \$36 $sshl$libresoc.v:150091$7354_Y
+ connect \$35 $pos$libresoc.v:150092$7356_Y
+ connect \$40 $add$libresoc.v:150093$7357_Y
+ connect \$42 $eq$libresoc.v:150094$7358_Y
+ connect \$45 $and$libresoc.v:150095$7359_Y
+ connect \$44 $reduce_or$libresoc.v:150096$7360_Y
+ connect \$49 $and$libresoc.v:150097$7361_Y
+ connect \$48 $reduce_or$libresoc.v:150098$7362_Y
+ connect \$53 $and$libresoc.v:150099$7363_Y
+ connect \$52 $reduce_or$libresoc.v:150100$7364_Y
+ connect \$57 $and$libresoc.v:150101$7365_Y
+ connect \$56 $reduce_or$libresoc.v:150102$7366_Y
+ connect \$64 $and$libresoc.v:150103$7367_Y
+ connect \$63 $reduce_or$libresoc.v:150104$7368_Y
+ connect \$72 $and$libresoc.v:150105$7369_Y
+ connect \$71 $reduce_or$libresoc.v:150106$7370_Y
+ connect \$75 $pos$libresoc.v:150107$7372_Y
+ connect \$77 $eq$libresoc.v:150108$7373_Y
+ connect \$79 $eq$libresoc.v:150109$7374_Y
+ connect \$81 $eq$libresoc.v:150110$7375_Y
+ connect \$83 $and$libresoc.v:150111$7376_Y
+ connect \$85 $not$libresoc.v:150112$7377_Y
+ connect \$87 $not$libresoc.v:150113$7378_Y
+ connect \$89 $eq$libresoc.v:150114$7379_Y
+ connect \$91 $eq$libresoc.v:150115$7380_Y
+ connect \$93 $and$libresoc.v:150116$7381_Y
connect \$39 \$40
connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \muxid$1 \muxid
connect \lt_s \$17
connect \to \trap_op__insn [25:21]
end
-attribute \src "libresoc.v:150994.1-151983.10"
+attribute \src "libresoc.v:150658.1-151647.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main"
attribute \generator "nMigen"
module \main$51
- attribute \src "libresoc.v:151902.3-151936.6"
+ attribute \src "libresoc.v:151566.3-151600.6"
wire width 32 $0\a32[31:0]
- attribute \src "libresoc.v:151751.3-151777.6"
+ attribute \src "libresoc.v:151415.3-151441.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:151685.3-151723.6"
+ attribute \src "libresoc.v:151349.3-151387.6"
wire width 64 $0\bpermd_rb[63:0]
- attribute \src "libresoc.v:151646.3-151684.6"
+ attribute \src "libresoc.v:151310.3-151348.6"
wire width 64 $0\bpermd_rs[63:0]
- attribute \src "libresoc.v:151611.3-151645.6"
+ attribute \src "libresoc.v:151275.3-151309.6"
wire width 64 $0\clz_sig_in[63:0]
- attribute \src "libresoc.v:151937.3-151979.6"
+ attribute \src "libresoc.v:151601.3-151643.6"
wire width 64 $0\cntz_i[63:0]
- attribute \src "libresoc.v:151867.3-151901.6"
+ attribute \src "libresoc.v:151531.3-151565.6"
wire $0\count_right[0:0]
- attribute \src "libresoc.v:150995.7-150995.20"
+ attribute \src "libresoc.v:150659.7-150659.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:151556.3-151610.6"
+ attribute \src "libresoc.v:151220.3-151274.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:151556.3-151610.6"
+ attribute \src "libresoc.v:151220.3-151274.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:151805.3-151835.6"
+ attribute \src "libresoc.v:151469.3-151499.6"
wire $0\par0[0:0]
- attribute \src "libresoc.v:151836.3-151866.6"
+ attribute \src "libresoc.v:151500.3-151530.6"
wire $0\par1[0:0]
- attribute \src "libresoc.v:151724.3-151750.6"
+ attribute \src "libresoc.v:151388.3-151414.6"
wire width 64 $0\popcount_a[63:0]
- attribute \src "libresoc.v:151778.3-151804.6"
+ attribute \src "libresoc.v:151442.3-151468.6"
wire width 64 $0\popcount_data_len[63:0]
- attribute \src "libresoc.v:151902.3-151936.6"
+ attribute \src "libresoc.v:151566.3-151600.6"
wire width 32 $1\a32[31:0]
- attribute \src "libresoc.v:151751.3-151777.6"
+ attribute \src "libresoc.v:151415.3-151441.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:151685.3-151723.6"
+ attribute \src "libresoc.v:151349.3-151387.6"
wire width 64 $1\bpermd_rb[63:0]
- attribute \src "libresoc.v:151646.3-151684.6"
+ attribute \src "libresoc.v:151310.3-151348.6"
wire width 64 $1\bpermd_rs[63:0]
- attribute \src "libresoc.v:151611.3-151645.6"
+ attribute \src "libresoc.v:151275.3-151309.6"
wire width 64 $1\clz_sig_in[63:0]
- attribute \src "libresoc.v:151937.3-151979.6"
+ attribute \src "libresoc.v:151601.3-151643.6"
wire width 64 $1\cntz_i[63:0]
- attribute \src "libresoc.v:151867.3-151901.6"
+ attribute \src "libresoc.v:151531.3-151565.6"
wire $1\count_right[0:0]
- attribute \src "libresoc.v:151556.3-151610.6"
+ attribute \src "libresoc.v:151220.3-151274.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:151556.3-151610.6"
+ attribute \src "libresoc.v:151220.3-151274.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:151805.3-151835.6"
+ attribute \src "libresoc.v:151469.3-151499.6"
wire $1\par0[0:0]
- attribute \src "libresoc.v:151836.3-151866.6"
+ attribute \src "libresoc.v:151500.3-151530.6"
wire $1\par1[0:0]
- attribute \src "libresoc.v:151724.3-151750.6"
+ attribute \src "libresoc.v:151388.3-151414.6"
wire width 64 $1\popcount_a[63:0]
- attribute \src "libresoc.v:151778.3-151804.6"
+ attribute \src "libresoc.v:151442.3-151468.6"
wire width 64 $1\popcount_data_len[63:0]
- attribute \src "libresoc.v:151937.3-151979.6"
+ attribute \src "libresoc.v:151601.3-151643.6"
wire width 64 $2\cntz_i[63:0]
- attribute \src "libresoc.v:151556.3-151610.6"
+ attribute \src "libresoc.v:151220.3-151274.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:151503.18-151503.103"
- wire width 64 $and$libresoc.v:151503$7541_Y
- attribute \src "libresoc.v:151462.18-151462.118"
- wire $eq$libresoc.v:151462$7495_Y
- attribute \src "libresoc.v:151463.19-151463.119"
- wire $eq$libresoc.v:151463$7496_Y
- attribute \src "libresoc.v:151464.19-151464.119"
- wire $eq$libresoc.v:151464$7497_Y
- attribute \src "libresoc.v:151465.19-151465.119"
- wire $eq$libresoc.v:151465$7498_Y
- attribute \src "libresoc.v:151466.19-151466.119"
- wire $eq$libresoc.v:151466$7499_Y
- attribute \src "libresoc.v:151467.19-151467.119"
- wire $eq$libresoc.v:151467$7500_Y
- attribute \src "libresoc.v:151468.19-151468.119"
- wire $eq$libresoc.v:151468$7501_Y
- attribute \src "libresoc.v:151469.19-151469.119"
- wire $eq$libresoc.v:151469$7502_Y
- attribute \src "libresoc.v:151470.19-151470.119"
- wire $eq$libresoc.v:151470$7503_Y
- attribute \src "libresoc.v:151471.19-151471.119"
- wire $eq$libresoc.v:151471$7504_Y
- attribute \src "libresoc.v:151472.19-151472.119"
- wire $eq$libresoc.v:151472$7505_Y
- attribute \src "libresoc.v:151473.19-151473.119"
- wire $eq$libresoc.v:151473$7506_Y
- attribute \src "libresoc.v:151474.19-151474.119"
- wire $eq$libresoc.v:151474$7507_Y
- attribute \src "libresoc.v:151475.19-151475.119"
- wire $eq$libresoc.v:151475$7508_Y
- attribute \src "libresoc.v:151476.19-151476.119"
- wire $eq$libresoc.v:151476$7509_Y
- attribute \src "libresoc.v:151477.19-151477.119"
- wire $eq$libresoc.v:151477$7510_Y
- attribute \src "libresoc.v:151478.19-151478.119"
- wire $eq$libresoc.v:151478$7511_Y
- attribute \src "libresoc.v:151479.19-151479.119"
- wire $eq$libresoc.v:151479$7512_Y
- attribute \src "libresoc.v:151480.19-151480.119"
- wire $eq$libresoc.v:151480$7513_Y
- attribute \src "libresoc.v:151481.19-151481.119"
- wire $eq$libresoc.v:151481$7514_Y
- attribute \src "libresoc.v:151482.19-151482.119"
- wire $eq$libresoc.v:151482$7515_Y
- attribute \src "libresoc.v:151483.19-151483.119"
- wire $eq$libresoc.v:151483$7516_Y
- attribute \src "libresoc.v:151484.19-151484.119"
- wire $eq$libresoc.v:151484$7517_Y
- attribute \src "libresoc.v:151485.19-151485.119"
- wire $eq$libresoc.v:151485$7518_Y
- attribute \src "libresoc.v:151486.19-151486.119"
- wire $eq$libresoc.v:151486$7519_Y
- attribute \src "libresoc.v:151487.19-151487.119"
- wire $eq$libresoc.v:151487$7520_Y
- attribute \src "libresoc.v:151488.19-151488.119"
- wire $eq$libresoc.v:151488$7521_Y
- attribute \src "libresoc.v:151489.19-151489.119"
- wire $eq$libresoc.v:151489$7522_Y
- attribute \src "libresoc.v:151490.19-151490.128"
- wire $eq$libresoc.v:151490$7523_Y
- attribute \src "libresoc.v:151506.18-151506.114"
- wire $eq$libresoc.v:151506$7544_Y
- attribute \src "libresoc.v:151507.18-151507.114"
- wire $eq$libresoc.v:151507$7545_Y
- attribute \src "libresoc.v:151508.18-151508.114"
- wire $eq$libresoc.v:151508$7546_Y
- attribute \src "libresoc.v:151509.18-151509.114"
- wire $eq$libresoc.v:151509$7547_Y
- attribute \src "libresoc.v:151510.18-151510.114"
- wire $eq$libresoc.v:151510$7548_Y
- attribute \src "libresoc.v:151511.18-151511.114"
- wire $eq$libresoc.v:151511$7549_Y
- attribute \src "libresoc.v:151512.18-151512.114"
- wire $eq$libresoc.v:151512$7550_Y
- attribute \src "libresoc.v:151513.18-151513.114"
- wire $eq$libresoc.v:151513$7551_Y
- attribute \src "libresoc.v:151514.18-151514.116"
- wire $eq$libresoc.v:151514$7552_Y
- attribute \src "libresoc.v:151515.18-151515.116"
- wire $eq$libresoc.v:151515$7553_Y
- attribute \src "libresoc.v:151516.18-151516.116"
- wire $eq$libresoc.v:151516$7554_Y
- attribute \src "libresoc.v:151517.18-151517.116"
- wire $eq$libresoc.v:151517$7555_Y
- attribute \src "libresoc.v:151518.18-151518.116"
- wire $eq$libresoc.v:151518$7556_Y
- attribute \src "libresoc.v:151519.18-151519.116"
- wire $eq$libresoc.v:151519$7557_Y
- attribute \src "libresoc.v:151520.18-151520.116"
- wire $eq$libresoc.v:151520$7558_Y
- attribute \src "libresoc.v:151521.18-151521.116"
- wire $eq$libresoc.v:151521$7559_Y
- attribute \src "libresoc.v:151522.18-151522.118"
- wire $eq$libresoc.v:151522$7560_Y
- attribute \src "libresoc.v:151523.18-151523.118"
- wire $eq$libresoc.v:151523$7561_Y
- attribute \src "libresoc.v:151524.18-151524.118"
- wire $eq$libresoc.v:151524$7562_Y
- attribute \src "libresoc.v:151525.18-151525.118"
- wire $eq$libresoc.v:151525$7563_Y
- attribute \src "libresoc.v:151526.18-151526.118"
- wire $eq$libresoc.v:151526$7564_Y
- attribute \src "libresoc.v:151527.18-151527.118"
- wire $eq$libresoc.v:151527$7565_Y
- attribute \src "libresoc.v:151528.18-151528.118"
- wire $eq$libresoc.v:151528$7566_Y
- attribute \src "libresoc.v:151529.18-151529.118"
- wire $eq$libresoc.v:151529$7567_Y
- attribute \src "libresoc.v:151530.18-151530.118"
- wire $eq$libresoc.v:151530$7568_Y
- attribute \src "libresoc.v:151531.18-151531.118"
- wire $eq$libresoc.v:151531$7569_Y
- attribute \src "libresoc.v:151532.18-151532.118"
- wire $eq$libresoc.v:151532$7570_Y
- attribute \src "libresoc.v:151533.18-151533.118"
- wire $eq$libresoc.v:151533$7571_Y
- attribute \src "libresoc.v:151534.18-151534.118"
- wire $eq$libresoc.v:151534$7572_Y
- attribute \src "libresoc.v:151535.18-151535.118"
- wire $eq$libresoc.v:151535$7573_Y
- attribute \src "libresoc.v:151536.18-151536.118"
- wire $eq$libresoc.v:151536$7574_Y
- attribute \src "libresoc.v:151537.18-151537.118"
- wire $eq$libresoc.v:151537$7575_Y
- attribute \src "libresoc.v:151538.18-151538.118"
- wire $eq$libresoc.v:151538$7576_Y
- attribute \src "libresoc.v:151539.18-151539.118"
- wire $eq$libresoc.v:151539$7577_Y
- attribute \src "libresoc.v:151540.18-151540.118"
- wire $eq$libresoc.v:151540$7578_Y
- attribute \src "libresoc.v:151541.18-151541.118"
- wire $eq$libresoc.v:151541$7579_Y
- attribute \src "libresoc.v:151492.19-151492.104"
- wire width 64 $extend$libresoc.v:151492$7525_Y
- attribute \src "libresoc.v:151494.19-151494.93"
- wire width 8 $extend$libresoc.v:151494$7528_Y
- attribute \src "libresoc.v:151496.19-151496.105"
- wire width 64 $extend$libresoc.v:151496$7531_Y
- attribute \src "libresoc.v:151497.19-151497.118"
- wire width 64 $extend$libresoc.v:151497$7533_Y
- attribute \src "libresoc.v:151501.19-151501.105"
- wire width 64 $extend$libresoc.v:151501$7538_Y
- attribute \src "libresoc.v:151504.18-151504.103"
- wire width 64 $or$libresoc.v:151504$7542_Y
- attribute \src "libresoc.v:151492.19-151492.104"
- wire width 64 $pos$libresoc.v:151492$7526_Y
- attribute \src "libresoc.v:151494.19-151494.93"
- wire width 8 $pos$libresoc.v:151494$7529_Y
- attribute \src "libresoc.v:151496.19-151496.105"
- wire width 64 $pos$libresoc.v:151496$7532_Y
- attribute \src "libresoc.v:151497.19-151497.118"
- wire width 64 $pos$libresoc.v:151497$7534_Y
- attribute \src "libresoc.v:151501.19-151501.105"
- wire width 64 $pos$libresoc.v:151501$7539_Y
- attribute \src "libresoc.v:151498.19-151498.131"
- wire $reduce_xor$libresoc.v:151498$7535_Y
- attribute \src "libresoc.v:151499.19-151499.133"
- wire $reduce_xor$libresoc.v:151499$7536_Y
- attribute \src "libresoc.v:151493.19-151493.112"
- wire width 8 $sub$libresoc.v:151493$7527_Y
- attribute \src "libresoc.v:151495.19-151495.135"
- wire width 8 $ternary$libresoc.v:151495$7530_Y
- attribute \src "libresoc.v:151500.19-151500.398"
- wire width 32 $ternary$libresoc.v:151500$7537_Y
- attribute \src "libresoc.v:151502.19-151502.621"
- wire width 64 $ternary$libresoc.v:151502$7540_Y
- attribute \src "libresoc.v:151491.19-151491.108"
- wire $xor$libresoc.v:151491$7524_Y
- attribute \src "libresoc.v:151505.18-151505.103"
- wire width 64 $xor$libresoc.v:151505$7543_Y
+ attribute \src "libresoc.v:151167.18-151167.103"
+ wire width 64 $and$libresoc.v:151167$7489_Y
+ attribute \src "libresoc.v:151126.18-151126.118"
+ wire $eq$libresoc.v:151126$7443_Y
+ attribute \src "libresoc.v:151127.19-151127.119"
+ wire $eq$libresoc.v:151127$7444_Y
+ attribute \src "libresoc.v:151128.19-151128.119"
+ wire $eq$libresoc.v:151128$7445_Y
+ attribute \src "libresoc.v:151129.19-151129.119"
+ wire $eq$libresoc.v:151129$7446_Y
+ attribute \src "libresoc.v:151130.19-151130.119"
+ wire $eq$libresoc.v:151130$7447_Y
+ attribute \src "libresoc.v:151131.19-151131.119"
+ wire $eq$libresoc.v:151131$7448_Y
+ attribute \src "libresoc.v:151132.19-151132.119"
+ wire $eq$libresoc.v:151132$7449_Y
+ attribute \src "libresoc.v:151133.19-151133.119"
+ wire $eq$libresoc.v:151133$7450_Y
+ attribute \src "libresoc.v:151134.19-151134.119"
+ wire $eq$libresoc.v:151134$7451_Y
+ attribute \src "libresoc.v:151135.19-151135.119"
+ wire $eq$libresoc.v:151135$7452_Y
+ attribute \src "libresoc.v:151136.19-151136.119"
+ wire $eq$libresoc.v:151136$7453_Y
+ attribute \src "libresoc.v:151137.19-151137.119"
+ wire $eq$libresoc.v:151137$7454_Y
+ attribute \src "libresoc.v:151138.19-151138.119"
+ wire $eq$libresoc.v:151138$7455_Y
+ attribute \src "libresoc.v:151139.19-151139.119"
+ wire $eq$libresoc.v:151139$7456_Y
+ attribute \src "libresoc.v:151140.19-151140.119"
+ wire $eq$libresoc.v:151140$7457_Y
+ attribute \src "libresoc.v:151141.19-151141.119"
+ wire $eq$libresoc.v:151141$7458_Y
+ attribute \src "libresoc.v:151142.19-151142.119"
+ wire $eq$libresoc.v:151142$7459_Y
+ attribute \src "libresoc.v:151143.19-151143.119"
+ wire $eq$libresoc.v:151143$7460_Y
+ attribute \src "libresoc.v:151144.19-151144.119"
+ wire $eq$libresoc.v:151144$7461_Y
+ attribute \src "libresoc.v:151145.19-151145.119"
+ wire $eq$libresoc.v:151145$7462_Y
+ attribute \src "libresoc.v:151146.19-151146.119"
+ wire $eq$libresoc.v:151146$7463_Y
+ attribute \src "libresoc.v:151147.19-151147.119"
+ wire $eq$libresoc.v:151147$7464_Y
+ attribute \src "libresoc.v:151148.19-151148.119"
+ wire $eq$libresoc.v:151148$7465_Y
+ attribute \src "libresoc.v:151149.19-151149.119"
+ wire $eq$libresoc.v:151149$7466_Y
+ attribute \src "libresoc.v:151150.19-151150.119"
+ wire $eq$libresoc.v:151150$7467_Y
+ attribute \src "libresoc.v:151151.19-151151.119"
+ wire $eq$libresoc.v:151151$7468_Y
+ attribute \src "libresoc.v:151152.19-151152.119"
+ wire $eq$libresoc.v:151152$7469_Y
+ attribute \src "libresoc.v:151153.19-151153.119"
+ wire $eq$libresoc.v:151153$7470_Y
+ attribute \src "libresoc.v:151154.19-151154.128"
+ wire $eq$libresoc.v:151154$7471_Y
+ attribute \src "libresoc.v:151170.18-151170.114"
+ wire $eq$libresoc.v:151170$7492_Y
+ attribute \src "libresoc.v:151171.18-151171.114"
+ wire $eq$libresoc.v:151171$7493_Y
+ attribute \src "libresoc.v:151172.18-151172.114"
+ wire $eq$libresoc.v:151172$7494_Y
+ attribute \src "libresoc.v:151173.18-151173.114"
+ wire $eq$libresoc.v:151173$7495_Y
+ attribute \src "libresoc.v:151174.18-151174.114"
+ wire $eq$libresoc.v:151174$7496_Y
+ attribute \src "libresoc.v:151175.18-151175.114"
+ wire $eq$libresoc.v:151175$7497_Y
+ attribute \src "libresoc.v:151176.18-151176.114"
+ wire $eq$libresoc.v:151176$7498_Y
+ attribute \src "libresoc.v:151177.18-151177.114"
+ wire $eq$libresoc.v:151177$7499_Y
+ attribute \src "libresoc.v:151178.18-151178.116"
+ wire $eq$libresoc.v:151178$7500_Y
+ attribute \src "libresoc.v:151179.18-151179.116"
+ wire $eq$libresoc.v:151179$7501_Y
+ attribute \src "libresoc.v:151180.18-151180.116"
+ wire $eq$libresoc.v:151180$7502_Y
+ attribute \src "libresoc.v:151181.18-151181.116"
+ wire $eq$libresoc.v:151181$7503_Y
+ attribute \src "libresoc.v:151182.18-151182.116"
+ wire $eq$libresoc.v:151182$7504_Y
+ attribute \src "libresoc.v:151183.18-151183.116"
+ wire $eq$libresoc.v:151183$7505_Y
+ attribute \src "libresoc.v:151184.18-151184.116"
+ wire $eq$libresoc.v:151184$7506_Y
+ attribute \src "libresoc.v:151185.18-151185.116"
+ wire $eq$libresoc.v:151185$7507_Y
+ attribute \src "libresoc.v:151186.18-151186.118"
+ wire $eq$libresoc.v:151186$7508_Y
+ attribute \src "libresoc.v:151187.18-151187.118"
+ wire $eq$libresoc.v:151187$7509_Y
+ attribute \src "libresoc.v:151188.18-151188.118"
+ wire $eq$libresoc.v:151188$7510_Y
+ attribute \src "libresoc.v:151189.18-151189.118"
+ wire $eq$libresoc.v:151189$7511_Y
+ attribute \src "libresoc.v:151190.18-151190.118"
+ wire $eq$libresoc.v:151190$7512_Y
+ attribute \src "libresoc.v:151191.18-151191.118"
+ wire $eq$libresoc.v:151191$7513_Y
+ attribute \src "libresoc.v:151192.18-151192.118"
+ wire $eq$libresoc.v:151192$7514_Y
+ attribute \src "libresoc.v:151193.18-151193.118"
+ wire $eq$libresoc.v:151193$7515_Y
+ attribute \src "libresoc.v:151194.18-151194.118"
+ wire $eq$libresoc.v:151194$7516_Y
+ attribute \src "libresoc.v:151195.18-151195.118"
+ wire $eq$libresoc.v:151195$7517_Y
+ attribute \src "libresoc.v:151196.18-151196.118"
+ wire $eq$libresoc.v:151196$7518_Y
+ attribute \src "libresoc.v:151197.18-151197.118"
+ wire $eq$libresoc.v:151197$7519_Y
+ attribute \src "libresoc.v:151198.18-151198.118"
+ wire $eq$libresoc.v:151198$7520_Y
+ attribute \src "libresoc.v:151199.18-151199.118"
+ wire $eq$libresoc.v:151199$7521_Y
+ attribute \src "libresoc.v:151200.18-151200.118"
+ wire $eq$libresoc.v:151200$7522_Y
+ attribute \src "libresoc.v:151201.18-151201.118"
+ wire $eq$libresoc.v:151201$7523_Y
+ attribute \src "libresoc.v:151202.18-151202.118"
+ wire $eq$libresoc.v:151202$7524_Y
+ attribute \src "libresoc.v:151203.18-151203.118"
+ wire $eq$libresoc.v:151203$7525_Y
+ attribute \src "libresoc.v:151204.18-151204.118"
+ wire $eq$libresoc.v:151204$7526_Y
+ attribute \src "libresoc.v:151205.18-151205.118"
+ wire $eq$libresoc.v:151205$7527_Y
+ attribute \src "libresoc.v:151156.19-151156.104"
+ wire width 64 $extend$libresoc.v:151156$7473_Y
+ attribute \src "libresoc.v:151158.19-151158.93"
+ wire width 8 $extend$libresoc.v:151158$7476_Y
+ attribute \src "libresoc.v:151160.19-151160.105"
+ wire width 64 $extend$libresoc.v:151160$7479_Y
+ attribute \src "libresoc.v:151161.19-151161.118"
+ wire width 64 $extend$libresoc.v:151161$7481_Y
+ attribute \src "libresoc.v:151165.19-151165.105"
+ wire width 64 $extend$libresoc.v:151165$7486_Y
+ attribute \src "libresoc.v:151168.18-151168.103"
+ wire width 64 $or$libresoc.v:151168$7490_Y
+ attribute \src "libresoc.v:151156.19-151156.104"
+ wire width 64 $pos$libresoc.v:151156$7474_Y
+ attribute \src "libresoc.v:151158.19-151158.93"
+ wire width 8 $pos$libresoc.v:151158$7477_Y
+ attribute \src "libresoc.v:151160.19-151160.105"
+ wire width 64 $pos$libresoc.v:151160$7480_Y
+ attribute \src "libresoc.v:151161.19-151161.118"
+ wire width 64 $pos$libresoc.v:151161$7482_Y
+ attribute \src "libresoc.v:151165.19-151165.105"
+ wire width 64 $pos$libresoc.v:151165$7487_Y
+ attribute \src "libresoc.v:151162.19-151162.131"
+ wire $reduce_xor$libresoc.v:151162$7483_Y
+ attribute \src "libresoc.v:151163.19-151163.133"
+ wire $reduce_xor$libresoc.v:151163$7484_Y
+ attribute \src "libresoc.v:151157.19-151157.112"
+ wire width 8 $sub$libresoc.v:151157$7475_Y
+ attribute \src "libresoc.v:151159.19-151159.135"
+ wire width 8 $ternary$libresoc.v:151159$7478_Y
+ attribute \src "libresoc.v:151164.19-151164.398"
+ wire width 32 $ternary$libresoc.v:151164$7485_Y
+ attribute \src "libresoc.v:151166.19-151166.621"
+ wire width 64 $ternary$libresoc.v:151166$7488_Y
+ attribute \src "libresoc.v:151155.19-151155.108"
+ wire $xor$libresoc.v:151155$7472_Y
+ attribute \src "libresoc.v:151169.18-151169.103"
+ wire width 64 $xor$libresoc.v:151169$7491_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
wire width 64 \cntz_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99"
wire \count_right
- attribute \src "libresoc.v:150995.7-150995.15"
+ attribute \src "libresoc.v:150659.7-150659.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 43 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
- cell $and $and$libresoc.v:151503$7541
+ cell $and $and$libresoc.v:151167$7489
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $and$libresoc.v:151503$7541_Y
+ connect \Y $and$libresoc.v:151167$7489_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151462$7495
+ cell $eq $eq$libresoc.v:151126$7443
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151462$7495_Y
+ connect \Y $eq$libresoc.v:151126$7443_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151463$7496
+ cell $eq $eq$libresoc.v:151127$7444
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151463$7496_Y
+ connect \Y $eq$libresoc.v:151127$7444_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151464$7497
+ cell $eq $eq$libresoc.v:151128$7445
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151464$7497_Y
+ connect \Y $eq$libresoc.v:151128$7445_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151465$7498
+ cell $eq $eq$libresoc.v:151129$7446
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151465$7498_Y
+ connect \Y $eq$libresoc.v:151129$7446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151466$7499
+ cell $eq $eq$libresoc.v:151130$7447
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151466$7499_Y
+ connect \Y $eq$libresoc.v:151130$7447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151467$7500
+ cell $eq $eq$libresoc.v:151131$7448
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151467$7500_Y
+ connect \Y $eq$libresoc.v:151131$7448_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151468$7501
+ cell $eq $eq$libresoc.v:151132$7449
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151468$7501_Y
+ connect \Y $eq$libresoc.v:151132$7449_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151469$7502
+ cell $eq $eq$libresoc.v:151133$7450
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151469$7502_Y
+ connect \Y $eq$libresoc.v:151133$7450_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151470$7503
+ cell $eq $eq$libresoc.v:151134$7451
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151470$7503_Y
+ connect \Y $eq$libresoc.v:151134$7451_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151471$7504
+ cell $eq $eq$libresoc.v:151135$7452
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151471$7504_Y
+ connect \Y $eq$libresoc.v:151135$7452_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151472$7505
+ cell $eq $eq$libresoc.v:151136$7453
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151472$7505_Y
+ connect \Y $eq$libresoc.v:151136$7453_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151473$7506
+ cell $eq $eq$libresoc.v:151137$7454
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:151473$7506_Y
+ connect \Y $eq$libresoc.v:151137$7454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151474$7507
+ cell $eq $eq$libresoc.v:151138$7455
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151474$7507_Y
+ connect \Y $eq$libresoc.v:151138$7455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151475$7508
+ cell $eq $eq$libresoc.v:151139$7456
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151475$7508_Y
+ connect \Y $eq$libresoc.v:151139$7456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151476$7509
+ cell $eq $eq$libresoc.v:151140$7457
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151476$7509_Y
+ connect \Y $eq$libresoc.v:151140$7457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151477$7510
+ cell $eq $eq$libresoc.v:151141$7458
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151477$7510_Y
+ connect \Y $eq$libresoc.v:151141$7458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151478$7511
+ cell $eq $eq$libresoc.v:151142$7459
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151478$7511_Y
+ connect \Y $eq$libresoc.v:151142$7459_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151479$7512
+ cell $eq $eq$libresoc.v:151143$7460
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151479$7512_Y
+ connect \Y $eq$libresoc.v:151143$7460_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151480$7513
+ cell $eq $eq$libresoc.v:151144$7461
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151480$7513_Y
+ connect \Y $eq$libresoc.v:151144$7461_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151481$7514
+ cell $eq $eq$libresoc.v:151145$7462
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:151481$7514_Y
+ connect \Y $eq$libresoc.v:151145$7462_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151482$7515
+ cell $eq $eq$libresoc.v:151146$7463
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151482$7515_Y
+ connect \Y $eq$libresoc.v:151146$7463_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151483$7516
+ cell $eq $eq$libresoc.v:151147$7464
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151483$7516_Y
+ connect \Y $eq$libresoc.v:151147$7464_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151484$7517
+ cell $eq $eq$libresoc.v:151148$7465
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151484$7517_Y
+ connect \Y $eq$libresoc.v:151148$7465_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151485$7518
+ cell $eq $eq$libresoc.v:151149$7466
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151485$7518_Y
+ connect \Y $eq$libresoc.v:151149$7466_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151486$7519
+ cell $eq $eq$libresoc.v:151150$7467
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151486$7519_Y
+ connect \Y $eq$libresoc.v:151150$7467_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151487$7520
+ cell $eq $eq$libresoc.v:151151$7468
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151487$7520_Y
+ connect \Y $eq$libresoc.v:151151$7468_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151488$7521
+ cell $eq $eq$libresoc.v:151152$7469
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151488$7521_Y
+ connect \Y $eq$libresoc.v:151152$7469_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151489$7522
+ cell $eq $eq$libresoc.v:151153$7470
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:151489$7522_Y
+ connect \Y $eq$libresoc.v:151153$7470_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
- cell $eq $eq$libresoc.v:151490$7523
+ cell $eq $eq$libresoc.v:151154$7471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__data_len [3]
connect \B 1'1
- connect \Y $eq$libresoc.v:151490$7523_Y
+ connect \Y $eq$libresoc.v:151154$7471_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151506$7544
+ cell $eq $eq$libresoc.v:151170$7492
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151506$7544_Y
+ connect \Y $eq$libresoc.v:151170$7492_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151507$7545
+ cell $eq $eq$libresoc.v:151171$7493
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151507$7545_Y
+ connect \Y $eq$libresoc.v:151171$7493_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151508$7546
+ cell $eq $eq$libresoc.v:151172$7494
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151508$7546_Y
+ connect \Y $eq$libresoc.v:151172$7494_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151509$7547
+ cell $eq $eq$libresoc.v:151173$7495
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151509$7547_Y
+ connect \Y $eq$libresoc.v:151173$7495_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151510$7548
+ cell $eq $eq$libresoc.v:151174$7496
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151510$7548_Y
+ connect \Y $eq$libresoc.v:151174$7496_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151511$7549
+ cell $eq $eq$libresoc.v:151175$7497
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151511$7549_Y
+ connect \Y $eq$libresoc.v:151175$7497_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151512$7550
+ cell $eq $eq$libresoc.v:151176$7498
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151512$7550_Y
+ connect \Y $eq$libresoc.v:151176$7498_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151513$7551
+ cell $eq $eq$libresoc.v:151177$7499
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:151513$7551_Y
+ connect \Y $eq$libresoc.v:151177$7499_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151514$7552
+ cell $eq $eq$libresoc.v:151178$7500
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151514$7552_Y
+ connect \Y $eq$libresoc.v:151178$7500_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151515$7553
+ cell $eq $eq$libresoc.v:151179$7501
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151515$7553_Y
+ connect \Y $eq$libresoc.v:151179$7501_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151516$7554
+ cell $eq $eq$libresoc.v:151180$7502
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151516$7554_Y
+ connect \Y $eq$libresoc.v:151180$7502_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151517$7555
+ cell $eq $eq$libresoc.v:151181$7503
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151517$7555_Y
+ connect \Y $eq$libresoc.v:151181$7503_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151518$7556
+ cell $eq $eq$libresoc.v:151182$7504
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151518$7556_Y
+ connect \Y $eq$libresoc.v:151182$7504_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151519$7557
+ cell $eq $eq$libresoc.v:151183$7505
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151519$7557_Y
+ connect \Y $eq$libresoc.v:151183$7505_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151520$7558
+ cell $eq $eq$libresoc.v:151184$7506
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151520$7558_Y
+ connect \Y $eq$libresoc.v:151184$7506_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151521$7559
+ cell $eq $eq$libresoc.v:151185$7507
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:151521$7559_Y
+ connect \Y $eq$libresoc.v:151185$7507_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151522$7560
+ cell $eq $eq$libresoc.v:151186$7508
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151522$7560_Y
+ connect \Y $eq$libresoc.v:151186$7508_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151523$7561
+ cell $eq $eq$libresoc.v:151187$7509
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151523$7561_Y
+ connect \Y $eq$libresoc.v:151187$7509_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151524$7562
+ cell $eq $eq$libresoc.v:151188$7510
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151524$7562_Y
+ connect \Y $eq$libresoc.v:151188$7510_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151525$7563
+ cell $eq $eq$libresoc.v:151189$7511
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151525$7563_Y
+ connect \Y $eq$libresoc.v:151189$7511_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151526$7564
+ cell $eq $eq$libresoc.v:151190$7512
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151526$7564_Y
+ connect \Y $eq$libresoc.v:151190$7512_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151527$7565
+ cell $eq $eq$libresoc.v:151191$7513
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151527$7565_Y
+ connect \Y $eq$libresoc.v:151191$7513_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151528$7566
+ cell $eq $eq$libresoc.v:151192$7514
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151528$7566_Y
+ connect \Y $eq$libresoc.v:151192$7514_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151529$7567
+ cell $eq $eq$libresoc.v:151193$7515
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:151529$7567_Y
+ connect \Y $eq$libresoc.v:151193$7515_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151530$7568
+ cell $eq $eq$libresoc.v:151194$7516
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151530$7568_Y
+ connect \Y $eq$libresoc.v:151194$7516_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151531$7569
+ cell $eq $eq$libresoc.v:151195$7517
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151531$7569_Y
+ connect \Y $eq$libresoc.v:151195$7517_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151532$7570
+ cell $eq $eq$libresoc.v:151196$7518
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151532$7570_Y
+ connect \Y $eq$libresoc.v:151196$7518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151533$7571
+ cell $eq $eq$libresoc.v:151197$7519
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151533$7571_Y
+ connect \Y $eq$libresoc.v:151197$7519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151534$7572
+ cell $eq $eq$libresoc.v:151198$7520
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151534$7572_Y
+ connect \Y $eq$libresoc.v:151198$7520_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151535$7573
+ cell $eq $eq$libresoc.v:151199$7521
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151535$7573_Y
+ connect \Y $eq$libresoc.v:151199$7521_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151536$7574
+ cell $eq $eq$libresoc.v:151200$7522
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151536$7574_Y
+ connect \Y $eq$libresoc.v:151200$7522_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151537$7575
+ cell $eq $eq$libresoc.v:151201$7523
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:151537$7575_Y
+ connect \Y $eq$libresoc.v:151201$7523_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151538$7576
+ cell $eq $eq$libresoc.v:151202$7524
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151538$7576_Y
+ connect \Y $eq$libresoc.v:151202$7524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151539$7577
+ cell $eq $eq$libresoc.v:151203$7525
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151539$7577_Y
+ connect \Y $eq$libresoc.v:151203$7525_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151540$7578
+ cell $eq $eq$libresoc.v:151204$7526
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151540$7578_Y
+ connect \Y $eq$libresoc.v:151204$7526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:151541$7579
+ cell $eq $eq$libresoc.v:151205$7527
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:151541$7579_Y
+ connect \Y $eq$libresoc.v:151205$7527_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $pos $extend$libresoc.v:151492$7525
+ cell $pos $extend$libresoc.v:151156$7473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 64
connect \A \$158
- connect \Y $extend$libresoc.v:151492$7525_Y
+ connect \Y $extend$libresoc.v:151156$7473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18"
- cell $pos $extend$libresoc.v:151494$7528
+ cell $pos $extend$libresoc.v:151158$7476
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 8
connect \A \clz_lz
- connect \Y $extend$libresoc.v:151494$7528_Y
+ connect \Y $extend$libresoc.v:151158$7476_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $pos $extend$libresoc.v:151496$7531
+ cell $pos $extend$libresoc.v:151160$7479
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \$166
- connect \Y $extend$libresoc.v:151496$7531_Y
+ connect \Y $extend$libresoc.v:151160$7479_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $extend$libresoc.v:151497$7533
+ cell $pos $extend$libresoc.v:151161$7481
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 64
connect \A \logical_op__data_len
- connect \Y $extend$libresoc.v:151497$7533_Y
+ connect \Y $extend$libresoc.v:151161$7481_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $pos $extend$libresoc.v:151501$7538
+ cell $pos $extend$libresoc.v:151165$7486
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \$176
- connect \Y $extend$libresoc.v:151501$7538_Y
+ connect \Y $extend$libresoc.v:151165$7486_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
- cell $or $or$libresoc.v:151504$7542
+ cell $or $or$libresoc.v:151168$7490
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $or$libresoc.v:151504$7542_Y
+ connect \Y $or$libresoc.v:151168$7490_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $pos $pos$libresoc.v:151492$7526
+ cell $pos $pos$libresoc.v:151156$7474
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:151492$7525_Y
- connect \Y $pos$libresoc.v:151492$7526_Y
+ connect \A $extend$libresoc.v:151156$7473_Y
+ connect \Y $pos$libresoc.v:151156$7474_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18"
- cell $pos $pos$libresoc.v:151494$7529
+ cell $pos $pos$libresoc.v:151158$7477
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:151494$7528_Y
- connect \Y $pos$libresoc.v:151494$7529_Y
+ connect \A $extend$libresoc.v:151158$7476_Y
+ connect \Y $pos$libresoc.v:151158$7477_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $pos $pos$libresoc.v:151496$7532
+ cell $pos $pos$libresoc.v:151160$7480
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:151496$7531_Y
- connect \Y $pos$libresoc.v:151496$7532_Y
+ connect \A $extend$libresoc.v:151160$7479_Y
+ connect \Y $pos$libresoc.v:151160$7480_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $pos$libresoc.v:151497$7534
+ cell $pos $pos$libresoc.v:151161$7482
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:151497$7533_Y
- connect \Y $pos$libresoc.v:151497$7534_Y
+ connect \A $extend$libresoc.v:151161$7481_Y
+ connect \Y $pos$libresoc.v:151161$7482_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $pos $pos$libresoc.v:151501$7539
+ cell $pos $pos$libresoc.v:151165$7487
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:151501$7538_Y
- connect \Y $pos$libresoc.v:151501$7539_Y
+ connect \A $extend$libresoc.v:151165$7486_Y
+ connect \Y $pos$libresoc.v:151165$7487_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
- cell $reduce_xor $reduce_xor$libresoc.v:151498$7535
+ cell $reduce_xor $reduce_xor$libresoc.v:151162$7483
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [24] \ra [16] \ra [8] \ra [0] }
- connect \Y $reduce_xor$libresoc.v:151498$7535_Y
+ connect \Y $reduce_xor$libresoc.v:151162$7483_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
- cell $reduce_xor $reduce_xor$libresoc.v:151499$7536
+ cell $reduce_xor $reduce_xor$libresoc.v:151163$7484
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [56] \ra [48] \ra [40] \ra [32] }
- connect \Y $reduce_xor$libresoc.v:151499$7536_Y
+ connect \Y $reduce_xor$libresoc.v:151163$7484_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $sub $sub$libresoc.v:151493$7527
+ cell $sub $sub$libresoc.v:151157$7475
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \clz_lz
connect \B 6'100000
- connect \Y $sub$libresoc.v:151493$7527_Y
+ connect \Y $sub$libresoc.v:151157$7475_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $mux $ternary$libresoc.v:151495$7530
+ cell $mux $ternary$libresoc.v:151159$7478
parameter \WIDTH 8
connect \A \$164
connect \B \$162
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:151495$7530_Y
+ connect \Y $ternary$libresoc.v:151159$7478_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $mux $ternary$libresoc.v:151500$7537
+ cell $mux $ternary$libresoc.v:151164$7485
parameter \WIDTH 32
connect \A \a32
connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] }
connect \S \count_right
- connect \Y $ternary$libresoc.v:151500$7537_Y
+ connect \Y $ternary$libresoc.v:151164$7485_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109"
- cell $mux $ternary$libresoc.v:151502$7540
+ cell $mux $ternary$libresoc.v:151166$7488
parameter \WIDTH 64
connect \A \ra
connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] }
connect \S \count_right
- connect \Y $ternary$libresoc.v:151502$7540_Y
+ connect \Y $ternary$libresoc.v:151166$7488_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $xor $xor$libresoc.v:151491$7524
+ cell $xor $xor$libresoc.v:151155$7472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \par0
connect \B \par1
- connect \Y $xor$libresoc.v:151491$7524_Y
+ connect \Y $xor$libresoc.v:151155$7472_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
- cell $xor $xor$libresoc.v:151505$7543
+ cell $xor $xor$libresoc.v:151169$7491
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $xor$libresoc.v:151505$7543_Y
+ connect \Y $xor$libresoc.v:151169$7491_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:151542.10-151546.4"
+ attribute \src "libresoc.v:151206.10-151210.4"
cell \bpermd \bpermd
connect \ra \bpermd_ra
connect \rb \bpermd_rb
connect \rs \bpermd_rs
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:151547.7-151550.4"
+ attribute \src "libresoc.v:151211.7-151214.4"
cell \clz \clz
connect \lz \clz_lz
connect \sig_in \clz_sig_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:151551.12-151555.4"
+ attribute \src "libresoc.v:151215.12-151219.4"
cell \popcount \popcount
connect \a \popcount_a
connect \data_len \popcount_data_len
connect \o \popcount_o
end
- attribute \src "libresoc.v:150995.7-150995.20"
- process $proc$libresoc.v:150995$7592
+ attribute \src "libresoc.v:150659.7-150659.20"
+ process $proc$libresoc.v:150659$7540
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:151556.3-151610.6"
- process $proc$libresoc.v:151556$7580
+ attribute \src "libresoc.v:151220.3-151274.6"
+ process $proc$libresoc.v:151220$7528
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:151557.5-151557.29"
+ attribute \src "libresoc.v:151221.5-151221.29"
switch \initial
- attribute \src "libresoc.v:151557.9-151557.17"
+ attribute \src "libresoc.v:151221.9-151221.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:151611.3-151645.6"
- process $proc$libresoc.v:151611$7581
+ attribute \src "libresoc.v:151275.3-151309.6"
+ process $proc$libresoc.v:151275$7529
assign { } { }
assign { } { }
assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0]
- attribute \src "libresoc.v:151612.5-151612.29"
+ attribute \src "libresoc.v:151276.5-151276.29"
switch \initial
- attribute \src "libresoc.v:151612.9-151612.17"
+ attribute \src "libresoc.v:151276.9-151276.17"
case 1'1
case
end
sync always
update \clz_sig_in $0\clz_sig_in[63:0]
end
- attribute \src "libresoc.v:151646.3-151684.6"
- process $proc$libresoc.v:151646$7582
+ attribute \src "libresoc.v:151310.3-151348.6"
+ process $proc$libresoc.v:151310$7530
assign { } { }
assign { } { }
assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0]
- attribute \src "libresoc.v:151647.5-151647.29"
+ attribute \src "libresoc.v:151311.5-151311.29"
switch \initial
- attribute \src "libresoc.v:151647.9-151647.17"
+ attribute \src "libresoc.v:151311.9-151311.17"
case 1'1
case
end
sync always
update \bpermd_rs $0\bpermd_rs[63:0]
end
- attribute \src "libresoc.v:151685.3-151723.6"
- process $proc$libresoc.v:151685$7583
+ attribute \src "libresoc.v:151349.3-151387.6"
+ process $proc$libresoc.v:151349$7531
assign { } { }
assign { } { }
assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0]
- attribute \src "libresoc.v:151686.5-151686.29"
+ attribute \src "libresoc.v:151350.5-151350.29"
switch \initial
- attribute \src "libresoc.v:151686.9-151686.17"
+ attribute \src "libresoc.v:151350.9-151350.17"
case 1'1
case
end
sync always
update \bpermd_rb $0\bpermd_rb[63:0]
end
- attribute \src "libresoc.v:151724.3-151750.6"
- process $proc$libresoc.v:151724$7584
+ attribute \src "libresoc.v:151388.3-151414.6"
+ process $proc$libresoc.v:151388$7532
assign { } { }
assign { } { }
assign $0\popcount_a[63:0] $1\popcount_a[63:0]
- attribute \src "libresoc.v:151725.5-151725.29"
+ attribute \src "libresoc.v:151389.5-151389.29"
switch \initial
- attribute \src "libresoc.v:151725.9-151725.17"
+ attribute \src "libresoc.v:151389.9-151389.17"
case 1'1
case
end
sync always
update \popcount_a $0\popcount_a[63:0]
end
- attribute \src "libresoc.v:151751.3-151777.6"
- process $proc$libresoc.v:151751$7585
+ attribute \src "libresoc.v:151415.3-151441.6"
+ process $proc$libresoc.v:151415$7533
assign { } { }
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:151752.5-151752.29"
+ attribute \src "libresoc.v:151416.5-151416.29"
switch \initial
- attribute \src "libresoc.v:151752.9-151752.17"
+ attribute \src "libresoc.v:151416.9-151416.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- attribute \src "libresoc.v:151778.3-151804.6"
- process $proc$libresoc.v:151778$7586
+ attribute \src "libresoc.v:151442.3-151468.6"
+ process $proc$libresoc.v:151442$7534
assign { } { }
assign { } { }
assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0]
- attribute \src "libresoc.v:151779.5-151779.29"
+ attribute \src "libresoc.v:151443.5-151443.29"
switch \initial
- attribute \src "libresoc.v:151779.9-151779.17"
+ attribute \src "libresoc.v:151443.9-151443.17"
case 1'1
case
end
sync always
update \popcount_data_len $0\popcount_data_len[63:0]
end
- attribute \src "libresoc.v:151805.3-151835.6"
- process $proc$libresoc.v:151805$7587
+ attribute \src "libresoc.v:151469.3-151499.6"
+ process $proc$libresoc.v:151469$7535
assign { } { }
assign { } { }
assign $0\par0[0:0] $1\par0[0:0]
- attribute \src "libresoc.v:151806.5-151806.29"
+ attribute \src "libresoc.v:151470.5-151470.29"
switch \initial
- attribute \src "libresoc.v:151806.9-151806.17"
+ attribute \src "libresoc.v:151470.9-151470.17"
case 1'1
case
end
sync always
update \par0 $0\par0[0:0]
end
- attribute \src "libresoc.v:151836.3-151866.6"
- process $proc$libresoc.v:151836$7588
+ attribute \src "libresoc.v:151500.3-151530.6"
+ process $proc$libresoc.v:151500$7536
assign { } { }
assign { } { }
assign $0\par1[0:0] $1\par1[0:0]
- attribute \src "libresoc.v:151837.5-151837.29"
+ attribute \src "libresoc.v:151501.5-151501.29"
switch \initial
- attribute \src "libresoc.v:151837.9-151837.17"
+ attribute \src "libresoc.v:151501.9-151501.17"
case 1'1
case
end
sync always
update \par1 $0\par1[0:0]
end
- attribute \src "libresoc.v:151867.3-151901.6"
- process $proc$libresoc.v:151867$7589
+ attribute \src "libresoc.v:151531.3-151565.6"
+ process $proc$libresoc.v:151531$7537
assign { } { }
assign { } { }
assign $0\count_right[0:0] $1\count_right[0:0]
- attribute \src "libresoc.v:151868.5-151868.29"
+ attribute \src "libresoc.v:151532.5-151532.29"
switch \initial
- attribute \src "libresoc.v:151868.9-151868.17"
+ attribute \src "libresoc.v:151532.9-151532.17"
case 1'1
case
end
sync always
update \count_right $0\count_right[0:0]
end
- attribute \src "libresoc.v:151902.3-151936.6"
- process $proc$libresoc.v:151902$7590
+ attribute \src "libresoc.v:151566.3-151600.6"
+ process $proc$libresoc.v:151566$7538
assign { } { }
assign { } { }
assign $0\a32[31:0] $1\a32[31:0]
- attribute \src "libresoc.v:151903.5-151903.29"
+ attribute \src "libresoc.v:151567.5-151567.29"
switch \initial
- attribute \src "libresoc.v:151903.9-151903.17"
+ attribute \src "libresoc.v:151567.9-151567.17"
case 1'1
case
end
sync always
update \a32 $0\a32[31:0]
end
- attribute \src "libresoc.v:151937.3-151979.6"
- process $proc$libresoc.v:151937$7591
+ attribute \src "libresoc.v:151601.3-151643.6"
+ process $proc$libresoc.v:151601$7539
assign { } { }
assign { } { }
assign $0\cntz_i[63:0] $1\cntz_i[63:0]
- attribute \src "libresoc.v:151938.5-151938.29"
+ attribute \src "libresoc.v:151602.5-151602.29"
switch \initial
- attribute \src "libresoc.v:151938.9-151938.17"
+ attribute \src "libresoc.v:151602.9-151602.17"
case 1'1
case
end
sync always
update \cntz_i $0\cntz_i[63:0]
end
- connect \$99 $eq$libresoc.v:151462$7495_Y
- connect \$101 $eq$libresoc.v:151463$7496_Y
- connect \$103 $eq$libresoc.v:151464$7497_Y
- connect \$105 $eq$libresoc.v:151465$7498_Y
- connect \$107 $eq$libresoc.v:151466$7499_Y
- connect \$109 $eq$libresoc.v:151467$7500_Y
- connect \$111 $eq$libresoc.v:151468$7501_Y
- connect \$113 $eq$libresoc.v:151469$7502_Y
- connect \$115 $eq$libresoc.v:151470$7503_Y
- connect \$117 $eq$libresoc.v:151471$7504_Y
- connect \$119 $eq$libresoc.v:151472$7505_Y
- connect \$121 $eq$libresoc.v:151473$7506_Y
- connect \$123 $eq$libresoc.v:151474$7507_Y
- connect \$125 $eq$libresoc.v:151475$7508_Y
- connect \$127 $eq$libresoc.v:151476$7509_Y
- connect \$129 $eq$libresoc.v:151477$7510_Y
- connect \$131 $eq$libresoc.v:151478$7511_Y
- connect \$133 $eq$libresoc.v:151479$7512_Y
- connect \$135 $eq$libresoc.v:151480$7513_Y
- connect \$137 $eq$libresoc.v:151481$7514_Y
- connect \$139 $eq$libresoc.v:151482$7515_Y
- connect \$141 $eq$libresoc.v:151483$7516_Y
- connect \$143 $eq$libresoc.v:151484$7517_Y
- connect \$145 $eq$libresoc.v:151485$7518_Y
- connect \$147 $eq$libresoc.v:151486$7519_Y
- connect \$149 $eq$libresoc.v:151487$7520_Y
- connect \$151 $eq$libresoc.v:151488$7521_Y
- connect \$153 $eq$libresoc.v:151489$7522_Y
- connect \$155 $eq$libresoc.v:151490$7523_Y
- connect \$158 $xor$libresoc.v:151491$7524_Y
- connect \$157 $pos$libresoc.v:151492$7526_Y
- connect \$162 $sub$libresoc.v:151493$7527_Y
- connect \$164 $pos$libresoc.v:151494$7529_Y
- connect \$166 $ternary$libresoc.v:151495$7530_Y
- connect \$161 $pos$libresoc.v:151496$7532_Y
- connect \$169 $pos$libresoc.v:151497$7534_Y
- connect \$171 $reduce_xor$libresoc.v:151498$7535_Y
- connect \$173 $reduce_xor$libresoc.v:151499$7536_Y
- connect \$176 $ternary$libresoc.v:151500$7537_Y
- connect \$175 $pos$libresoc.v:151501$7539_Y
- connect \$179 $ternary$libresoc.v:151502$7540_Y
- connect \$21 $and$libresoc.v:151503$7541_Y
- connect \$23 $or$libresoc.v:151504$7542_Y
- connect \$25 $xor$libresoc.v:151505$7543_Y
- connect \$27 $eq$libresoc.v:151506$7544_Y
- connect \$29 $eq$libresoc.v:151507$7545_Y
- connect \$31 $eq$libresoc.v:151508$7546_Y
- connect \$33 $eq$libresoc.v:151509$7547_Y
- connect \$35 $eq$libresoc.v:151510$7548_Y
- connect \$37 $eq$libresoc.v:151511$7549_Y
- connect \$39 $eq$libresoc.v:151512$7550_Y
- connect \$41 $eq$libresoc.v:151513$7551_Y
- connect \$43 $eq$libresoc.v:151514$7552_Y
- connect \$45 $eq$libresoc.v:151515$7553_Y
- connect \$47 $eq$libresoc.v:151516$7554_Y
- connect \$49 $eq$libresoc.v:151517$7555_Y
- connect \$51 $eq$libresoc.v:151518$7556_Y
- connect \$53 $eq$libresoc.v:151519$7557_Y
- connect \$55 $eq$libresoc.v:151520$7558_Y
- connect \$57 $eq$libresoc.v:151521$7559_Y
- connect \$59 $eq$libresoc.v:151522$7560_Y
- connect \$61 $eq$libresoc.v:151523$7561_Y
- connect \$63 $eq$libresoc.v:151524$7562_Y
- connect \$65 $eq$libresoc.v:151525$7563_Y
- connect \$67 $eq$libresoc.v:151526$7564_Y
- connect \$69 $eq$libresoc.v:151527$7565_Y
- connect \$71 $eq$libresoc.v:151528$7566_Y
- connect \$73 $eq$libresoc.v:151529$7567_Y
- connect \$75 $eq$libresoc.v:151530$7568_Y
- connect \$77 $eq$libresoc.v:151531$7569_Y
- connect \$79 $eq$libresoc.v:151532$7570_Y
- connect \$81 $eq$libresoc.v:151533$7571_Y
- connect \$83 $eq$libresoc.v:151534$7572_Y
- connect \$85 $eq$libresoc.v:151535$7573_Y
- connect \$87 $eq$libresoc.v:151536$7574_Y
- connect \$89 $eq$libresoc.v:151537$7575_Y
- connect \$91 $eq$libresoc.v:151538$7576_Y
- connect \$93 $eq$libresoc.v:151539$7577_Y
- connect \$95 $eq$libresoc.v:151540$7578_Y
- connect \$97 $eq$libresoc.v:151541$7579_Y
+ connect \$99 $eq$libresoc.v:151126$7443_Y
+ connect \$101 $eq$libresoc.v:151127$7444_Y
+ connect \$103 $eq$libresoc.v:151128$7445_Y
+ connect \$105 $eq$libresoc.v:151129$7446_Y
+ connect \$107 $eq$libresoc.v:151130$7447_Y
+ connect \$109 $eq$libresoc.v:151131$7448_Y
+ connect \$111 $eq$libresoc.v:151132$7449_Y
+ connect \$113 $eq$libresoc.v:151133$7450_Y
+ connect \$115 $eq$libresoc.v:151134$7451_Y
+ connect \$117 $eq$libresoc.v:151135$7452_Y
+ connect \$119 $eq$libresoc.v:151136$7453_Y
+ connect \$121 $eq$libresoc.v:151137$7454_Y
+ connect \$123 $eq$libresoc.v:151138$7455_Y
+ connect \$125 $eq$libresoc.v:151139$7456_Y
+ connect \$127 $eq$libresoc.v:151140$7457_Y
+ connect \$129 $eq$libresoc.v:151141$7458_Y
+ connect \$131 $eq$libresoc.v:151142$7459_Y
+ connect \$133 $eq$libresoc.v:151143$7460_Y
+ connect \$135 $eq$libresoc.v:151144$7461_Y
+ connect \$137 $eq$libresoc.v:151145$7462_Y
+ connect \$139 $eq$libresoc.v:151146$7463_Y
+ connect \$141 $eq$libresoc.v:151147$7464_Y
+ connect \$143 $eq$libresoc.v:151148$7465_Y
+ connect \$145 $eq$libresoc.v:151149$7466_Y
+ connect \$147 $eq$libresoc.v:151150$7467_Y
+ connect \$149 $eq$libresoc.v:151151$7468_Y
+ connect \$151 $eq$libresoc.v:151152$7469_Y
+ connect \$153 $eq$libresoc.v:151153$7470_Y
+ connect \$155 $eq$libresoc.v:151154$7471_Y
+ connect \$158 $xor$libresoc.v:151155$7472_Y
+ connect \$157 $pos$libresoc.v:151156$7474_Y
+ connect \$162 $sub$libresoc.v:151157$7475_Y
+ connect \$164 $pos$libresoc.v:151158$7477_Y
+ connect \$166 $ternary$libresoc.v:151159$7478_Y
+ connect \$161 $pos$libresoc.v:151160$7480_Y
+ connect \$169 $pos$libresoc.v:151161$7482_Y
+ connect \$171 $reduce_xor$libresoc.v:151162$7483_Y
+ connect \$173 $reduce_xor$libresoc.v:151163$7484_Y
+ connect \$176 $ternary$libresoc.v:151164$7485_Y
+ connect \$175 $pos$libresoc.v:151165$7487_Y
+ connect \$179 $ternary$libresoc.v:151166$7488_Y
+ connect \$21 $and$libresoc.v:151167$7489_Y
+ connect \$23 $or$libresoc.v:151168$7490_Y
+ connect \$25 $xor$libresoc.v:151169$7491_Y
+ connect \$27 $eq$libresoc.v:151170$7492_Y
+ connect \$29 $eq$libresoc.v:151171$7493_Y
+ connect \$31 $eq$libresoc.v:151172$7494_Y
+ connect \$33 $eq$libresoc.v:151173$7495_Y
+ connect \$35 $eq$libresoc.v:151174$7496_Y
+ connect \$37 $eq$libresoc.v:151175$7497_Y
+ connect \$39 $eq$libresoc.v:151176$7498_Y
+ connect \$41 $eq$libresoc.v:151177$7499_Y
+ connect \$43 $eq$libresoc.v:151178$7500_Y
+ connect \$45 $eq$libresoc.v:151179$7501_Y
+ connect \$47 $eq$libresoc.v:151180$7502_Y
+ connect \$49 $eq$libresoc.v:151181$7503_Y
+ connect \$51 $eq$libresoc.v:151182$7504_Y
+ connect \$53 $eq$libresoc.v:151183$7505_Y
+ connect \$55 $eq$libresoc.v:151184$7506_Y
+ connect \$57 $eq$libresoc.v:151185$7507_Y
+ connect \$59 $eq$libresoc.v:151186$7508_Y
+ connect \$61 $eq$libresoc.v:151187$7509_Y
+ connect \$63 $eq$libresoc.v:151188$7510_Y
+ connect \$65 $eq$libresoc.v:151189$7511_Y
+ connect \$67 $eq$libresoc.v:151190$7512_Y
+ connect \$69 $eq$libresoc.v:151191$7513_Y
+ connect \$71 $eq$libresoc.v:151192$7514_Y
+ connect \$73 $eq$libresoc.v:151193$7515_Y
+ connect \$75 $eq$libresoc.v:151194$7516_Y
+ connect \$77 $eq$libresoc.v:151195$7517_Y
+ connect \$79 $eq$libresoc.v:151196$7518_Y
+ connect \$81 $eq$libresoc.v:151197$7519_Y
+ connect \$83 $eq$libresoc.v:151198$7520_Y
+ connect \$85 $eq$libresoc.v:151199$7521_Y
+ connect \$87 $eq$libresoc.v:151200$7522_Y
+ connect \$89 $eq$libresoc.v:151201$7523_Y
+ connect \$91 $eq$libresoc.v:151202$7524_Y
+ connect \$93 $eq$libresoc.v:151203$7525_Y
+ connect \$95 $eq$libresoc.v:151204$7526_Y
+ connect \$97 $eq$libresoc.v:151205$7527_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$20 \xer_so
end
-attribute \src "libresoc.v:151987.1-152590.10"
+attribute \src "libresoc.v:151651.1-152254.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main"
attribute \generator "nMigen"
module \main$9
- attribute \src "libresoc.v:152377.3-152403.6"
+ attribute \src "libresoc.v:152041.3-152067.6"
wire width 2 $0\BC[1:0]
- attribute \src "libresoc.v:152471.3-152485.6"
+ attribute \src "libresoc.v:152135.3-152149.6"
wire width 2 $0\ba[1:0]
- attribute \src "libresoc.v:152486.3-152500.6"
+ attribute \src "libresoc.v:152150.3-152164.6"
wire width 2 $0\bb[1:0]
- attribute \src "libresoc.v:152501.3-152525.6"
+ attribute \src "libresoc.v:152165.3-152189.6"
wire $0\bit_a[0:0]
- attribute \src "libresoc.v:152526.3-152550.6"
+ attribute \src "libresoc.v:152190.3-152214.6"
wire $0\bit_b[0:0]
- attribute \src "libresoc.v:152551.3-152565.6"
+ attribute \src "libresoc.v:152215.3-152229.6"
wire $0\bit_o[0:0]
- attribute \src "libresoc.v:152456.3-152470.6"
+ attribute \src "libresoc.v:152120.3-152134.6"
wire width 2 $0\bt[1:0]
- attribute \src "libresoc.v:152269.3-152303.6"
- wire width 4 $0\cr_a$6[3:0]$7607
- attribute \src "libresoc.v:152269.3-152303.6"
+ attribute \src "libresoc.v:151933.3-151967.6"
+ wire width 4 $0\cr_a$6[3:0]$7555
+ attribute \src "libresoc.v:151933.3-151967.6"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:152404.3-152440.6"
+ attribute \src "libresoc.v:152068.3-152104.6"
wire $0\cr_bit[0:0]
- attribute \src "libresoc.v:152566.3-152584.6"
- wire width 32 $0\full_cr$5[31:0]$7622
- attribute \src "libresoc.v:152304.3-152322.6"
+ attribute \src "libresoc.v:152230.3-152248.6"
+ wire width 32 $0\full_cr$5[31:0]$7570
+ attribute \src "libresoc.v:151968.3-151986.6"
wire $0\full_cr_ok[0:0]
- attribute \src "libresoc.v:151988.7-151988.20"
+ attribute \src "libresoc.v:151652.7-151652.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:152441.3-152455.6"
+ attribute \src "libresoc.v:152105.3-152119.6"
wire width 4 $0\lut[3:0]
- attribute \src "libresoc.v:152323.3-152376.6"
+ attribute \src "libresoc.v:151987.3-152040.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:152323.3-152376.6"
+ attribute \src "libresoc.v:151987.3-152040.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:152377.3-152403.6"
+ attribute \src "libresoc.v:152041.3-152067.6"
wire width 2 $1\BC[1:0]
- attribute \src "libresoc.v:152471.3-152485.6"
+ attribute \src "libresoc.v:152135.3-152149.6"
wire width 2 $1\ba[1:0]
- attribute \src "libresoc.v:152486.3-152500.6"
+ attribute \src "libresoc.v:152150.3-152164.6"
wire width 2 $1\bb[1:0]
- attribute \src "libresoc.v:152501.3-152525.6"
+ attribute \src "libresoc.v:152165.3-152189.6"
wire $1\bit_a[0:0]
- attribute \src "libresoc.v:152526.3-152550.6"
+ attribute \src "libresoc.v:152190.3-152214.6"
wire $1\bit_b[0:0]
- attribute \src "libresoc.v:152551.3-152565.6"
+ attribute \src "libresoc.v:152215.3-152229.6"
wire $1\bit_o[0:0]
- attribute \src "libresoc.v:152456.3-152470.6"
+ attribute \src "libresoc.v:152120.3-152134.6"
wire width 2 $1\bt[1:0]
- attribute \src "libresoc.v:152269.3-152303.6"
- wire width 4 $1\cr_a$6[3:0]$7608
- attribute \src "libresoc.v:152269.3-152303.6"
+ attribute \src "libresoc.v:151933.3-151967.6"
+ wire width 4 $1\cr_a$6[3:0]$7556
+ attribute \src "libresoc.v:151933.3-151967.6"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:152404.3-152440.6"
+ attribute \src "libresoc.v:152068.3-152104.6"
wire $1\cr_bit[0:0]
- attribute \src "libresoc.v:152566.3-152584.6"
- wire width 32 $1\full_cr$5[31:0]$7623
- attribute \src "libresoc.v:152304.3-152322.6"
+ attribute \src "libresoc.v:152230.3-152248.6"
+ wire width 32 $1\full_cr$5[31:0]$7571
+ attribute \src "libresoc.v:151968.3-151986.6"
wire $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:152441.3-152455.6"
+ attribute \src "libresoc.v:152105.3-152119.6"
wire width 4 $1\lut[3:0]
- attribute \src "libresoc.v:152323.3-152376.6"
+ attribute \src "libresoc.v:151987.3-152040.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:152323.3-152376.6"
+ attribute \src "libresoc.v:151987.3-152040.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:152501.3-152525.6"
+ attribute \src "libresoc.v:152165.3-152189.6"
wire $2\bit_a[0:0]
- attribute \src "libresoc.v:152526.3-152550.6"
+ attribute \src "libresoc.v:152190.3-152214.6"
wire $2\bit_b[0:0]
- attribute \src "libresoc.v:152269.3-152303.6"
- wire width 4 $2\cr_a$6[3:0]$7609
- attribute \src "libresoc.v:152404.3-152440.6"
+ attribute \src "libresoc.v:151933.3-151967.6"
+ wire width 4 $2\cr_a$6[3:0]$7557
+ attribute \src "libresoc.v:152068.3-152104.6"
wire $2\cr_bit[0:0]
- attribute \src "libresoc.v:152323.3-152376.6"
+ attribute \src "libresoc.v:151987.3-152040.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:152265.18-152265.96"
- wire width 64 $extend$libresoc.v:152265$7599_Y
- attribute \src "libresoc.v:152267.18-152267.98"
- wire width 65 $extend$libresoc.v:152267$7602_Y
- attribute \src "libresoc.v:152268.17-152268.92"
- wire width 5 $extend$libresoc.v:152268$7604_Y
- attribute \src "libresoc.v:152265.18-152265.96"
- wire width 64 $pos$libresoc.v:152265$7600_Y
- attribute \src "libresoc.v:152267.18-152267.98"
- wire width 65 $pos$libresoc.v:152267$7603_Y
- attribute \src "libresoc.v:152268.17-152268.92"
- wire width 5 $pos$libresoc.v:152268$7605_Y
- attribute \src "libresoc.v:152259.18-152259.116"
- wire width 3 $sub$libresoc.v:152259$7593_Y
- attribute \src "libresoc.v:152260.18-152260.116"
- wire width 3 $sub$libresoc.v:152260$7594_Y
- attribute \src "libresoc.v:152261.18-152261.116"
- wire width 3 $sub$libresoc.v:152261$7595_Y
- attribute \src "libresoc.v:152262.18-152262.114"
- wire $ternary$libresoc.v:152262$7596_Y
- attribute \src "libresoc.v:152263.18-152263.115"
- wire $ternary$libresoc.v:152263$7597_Y
- attribute \src "libresoc.v:152264.18-152264.112"
- wire $ternary$libresoc.v:152264$7598_Y
- attribute \src "libresoc.v:152266.18-152266.108"
- wire width 64 $ternary$libresoc.v:152266$7601_Y
+ attribute \src "libresoc.v:151929.18-151929.96"
+ wire width 64 $extend$libresoc.v:151929$7547_Y
+ attribute \src "libresoc.v:151931.18-151931.98"
+ wire width 65 $extend$libresoc.v:151931$7550_Y
+ attribute \src "libresoc.v:151932.17-151932.92"
+ wire width 5 $extend$libresoc.v:151932$7552_Y
+ attribute \src "libresoc.v:151929.18-151929.96"
+ wire width 64 $pos$libresoc.v:151929$7548_Y
+ attribute \src "libresoc.v:151931.18-151931.98"
+ wire width 65 $pos$libresoc.v:151931$7551_Y
+ attribute \src "libresoc.v:151932.17-151932.92"
+ wire width 5 $pos$libresoc.v:151932$7553_Y
+ attribute \src "libresoc.v:151923.18-151923.116"
+ wire width 3 $sub$libresoc.v:151923$7541_Y
+ attribute \src "libresoc.v:151924.18-151924.116"
+ wire width 3 $sub$libresoc.v:151924$7542_Y
+ attribute \src "libresoc.v:151925.18-151925.116"
+ wire width 3 $sub$libresoc.v:151925$7543_Y
+ attribute \src "libresoc.v:151926.18-151926.114"
+ wire $ternary$libresoc.v:151926$7544_Y
+ attribute \src "libresoc.v:151927.18-151927.115"
+ wire $ternary$libresoc.v:151927$7545_Y
+ attribute \src "libresoc.v:151928.18-151928.112"
+ wire $ternary$libresoc.v:151928$7546_Y
+ attribute \src "libresoc.v:151930.18-151930.108"
+ wire width 64 $ternary$libresoc.v:151930$7549_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86"
wire width 3 \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87"
wire width 32 output 16 \full_cr$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 17 \full_cr_ok
- attribute \src "libresoc.v:151988.7-151988.15"
+ attribute \src "libresoc.v:151652.7-151652.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70"
wire width 4 \lut
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 5 \rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:152265$7599
+ cell $pos $extend$libresoc.v:151929$7547
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \full_cr
- connect \Y $extend$libresoc.v:152265$7599_Y
+ connect \Y $extend$libresoc.v:151929$7547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $pos $extend$libresoc.v:152267$7602
+ cell $pos $extend$libresoc.v:151931$7550
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$27
- connect \Y $extend$libresoc.v:152267$7602_Y
+ connect \Y $extend$libresoc.v:151931$7550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:152268$7604
+ cell $pos $extend$libresoc.v:151932$7552
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 5
connect \A \cr_a
- connect \Y $extend$libresoc.v:152268$7604_Y
+ connect \Y $extend$libresoc.v:151932$7552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:152265$7600
+ cell $pos $pos$libresoc.v:151929$7548
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:152265$7599_Y
- connect \Y $pos$libresoc.v:152265$7600_Y
+ connect \A $extend$libresoc.v:151929$7547_Y
+ connect \Y $pos$libresoc.v:151929$7548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $pos $pos$libresoc.v:152267$7603
+ cell $pos $pos$libresoc.v:151931$7551
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:152267$7602_Y
- connect \Y $pos$libresoc.v:152267$7603_Y
+ connect \A $extend$libresoc.v:151931$7550_Y
+ connect \Y $pos$libresoc.v:151931$7551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:152268$7605
+ cell $pos $pos$libresoc.v:151932$7553
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
- connect \A $extend$libresoc.v:152268$7604_Y
- connect \Y $pos$libresoc.v:152268$7605_Y
+ connect \A $extend$libresoc.v:151932$7552_Y
+ connect \Y $pos$libresoc.v:151932$7553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86"
- cell $sub $sub$libresoc.v:152259$7593
+ cell $sub $sub$libresoc.v:151923$7541
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [22:21]
- connect \Y $sub$libresoc.v:152259$7593_Y
+ connect \Y $sub$libresoc.v:151923$7541_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87"
- cell $sub $sub$libresoc.v:152260$7594
+ cell $sub $sub$libresoc.v:151924$7542
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [17:16]
- connect \Y $sub$libresoc.v:152260$7594_Y
+ connect \Y $sub$libresoc.v:151924$7542_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88"
- cell $sub $sub$libresoc.v:152261$7595
+ cell $sub $sub$libresoc.v:151925$7543
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [12:11]
- connect \Y $sub$libresoc.v:152261$7595_Y
+ connect \Y $sub$libresoc.v:151925$7543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99"
- cell $mux $ternary$libresoc.v:152262$7596
+ cell $mux $ternary$libresoc.v:151926$7544
parameter \WIDTH 1
connect \A \lut [1]
connect \B \lut [3]
connect \S \bit_a
- connect \Y $ternary$libresoc.v:152262$7596_Y
+ connect \Y $ternary$libresoc.v:151926$7544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100"
- cell $mux $ternary$libresoc.v:152263$7597
+ cell $mux $ternary$libresoc.v:151927$7545
parameter \WIDTH 1
connect \A \lut [0]
connect \B \lut [2]
connect \S \bit_a
- connect \Y $ternary$libresoc.v:152263$7597_Y
+ connect \Y $ternary$libresoc.v:151927$7545_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100"
- cell $mux $ternary$libresoc.v:152264$7598
+ cell $mux $ternary$libresoc.v:151928$7546
parameter \WIDTH 1
connect \A \$20
connect \B \$18
connect \S \bit_b
- connect \Y $ternary$libresoc.v:152264$7598_Y
+ connect \Y $ternary$libresoc.v:151928$7546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $mux $ternary$libresoc.v:152266$7601
+ cell $mux $ternary$libresoc.v:151930$7549
parameter \WIDTH 64
connect \A \rb
connect \B \ra
connect \S \cr_bit
- connect \Y $ternary$libresoc.v:152266$7601_Y
+ connect \Y $ternary$libresoc.v:151930$7549_Y
end
- attribute \src "libresoc.v:151988.7-151988.20"
- process $proc$libresoc.v:151988$7624
+ attribute \src "libresoc.v:151652.7-151652.20"
+ process $proc$libresoc.v:151652$7572
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:152269.3-152303.6"
- process $proc$libresoc.v:152269$7606
+ attribute \src "libresoc.v:151933.3-151967.6"
+ process $proc$libresoc.v:151933$7554
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0]
- assign $0\cr_a$6[3:0]$7607 $1\cr_a$6[3:0]$7608
- attribute \src "libresoc.v:152270.5-152270.29"
+ assign $0\cr_a$6[3:0]$7555 $1\cr_a$6[3:0]$7556
+ attribute \src "libresoc.v:151934.5-151934.29"
switch \initial
- attribute \src "libresoc.v:152270.9-152270.17"
+ attribute \src "libresoc.v:151934.9-151934.17"
case 1'1
case
end
case 7'0101010
assign { } { }
assign { } { }
- assign $1\cr_a$6[3:0]$7608 \$7 [3:0]
+ assign $1\cr_a$6[3:0]$7556 \$7 [3:0]
assign $1\cr_a_ok[0:0] 1'1
attribute \src "libresoc.v:0.0-0.0"
case 7'1000101
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_a$6[3:0]$7608 $2\cr_a$6[3:0]$7609
+ assign $1\cr_a$6[3:0]$7556 $2\cr_a$6[3:0]$7557
assign $1\cr_a_ok[0:0] 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105"
switch \bt
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $2\cr_a$6[3:0]$7609 [3:1] \cr_c [3:1]
- assign $2\cr_a$6[3:0]$7609 [0] \bit_o
+ assign $2\cr_a$6[3:0]$7557 [3:1] \cr_c [3:1]
+ assign $2\cr_a$6[3:0]$7557 [0] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'01
- assign { $2\cr_a$6[3:0]$7609 [3:2] $2\cr_a$6[3:0]$7609 [0] } { \cr_c [3:2] \cr_c [0] }
- assign $2\cr_a$6[3:0]$7609 [1] \bit_o
+ assign { $2\cr_a$6[3:0]$7557 [3:2] $2\cr_a$6[3:0]$7557 [0] } { \cr_c [3:2] \cr_c [0] }
+ assign $2\cr_a$6[3:0]$7557 [1] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'10
- assign { $2\cr_a$6[3:0]$7609 [3] $2\cr_a$6[3:0]$7609 [1:0] } { \cr_c [3] \cr_c [1:0] }
- assign $2\cr_a$6[3:0]$7609 [2] \bit_o
+ assign { $2\cr_a$6[3:0]$7557 [3] $2\cr_a$6[3:0]$7557 [1:0] } { \cr_c [3] \cr_c [1:0] }
+ assign $2\cr_a$6[3:0]$7557 [2] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'--
- assign $2\cr_a$6[3:0]$7609 [2:0] \cr_c [2:0]
- assign $2\cr_a$6[3:0]$7609 [3] \bit_o
+ assign $2\cr_a$6[3:0]$7557 [2:0] \cr_c [2:0]
+ assign $2\cr_a$6[3:0]$7557 [3] \bit_o
case
- assign $2\cr_a$6[3:0]$7609 \cr_c
+ assign $2\cr_a$6[3:0]$7557 \cr_c
end
case
assign $1\cr_a_ok[0:0] 1'0
- assign $1\cr_a$6[3:0]$7608 4'0000
+ assign $1\cr_a$6[3:0]$7556 4'0000
end
sync always
update \cr_a_ok $0\cr_a_ok[0:0]
- update \cr_a$6 $0\cr_a$6[3:0]$7607
+ update \cr_a$6 $0\cr_a$6[3:0]$7555
end
- attribute \src "libresoc.v:152304.3-152322.6"
- process $proc$libresoc.v:152304$7610
+ attribute \src "libresoc.v:151968.3-151986.6"
+ process $proc$libresoc.v:151968$7558
assign { } { }
assign { } { }
assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:152305.5-152305.29"
+ attribute \src "libresoc.v:151969.5-151969.29"
switch \initial
- attribute \src "libresoc.v:152305.9-152305.17"
+ attribute \src "libresoc.v:151969.9-151969.17"
case 1'1
case
end
sync always
update \full_cr_ok $0\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:152323.3-152376.6"
- process $proc$libresoc.v:152323$7611
+ attribute \src "libresoc.v:151987.3-152040.6"
+ process $proc$libresoc.v:151987$7559
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:152324.5-152324.29"
+ attribute \src "libresoc.v:151988.5-151988.29"
switch \initial
- attribute \src "libresoc.v:152324.9-152324.17"
+ attribute \src "libresoc.v:151988.9-151988.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:152377.3-152403.6"
- process $proc$libresoc.v:152377$7612
+ attribute \src "libresoc.v:152041.3-152067.6"
+ process $proc$libresoc.v:152041$7560
assign { } { }
assign { } { }
assign $0\BC[1:0] $1\BC[1:0]
- attribute \src "libresoc.v:152378.5-152378.29"
+ attribute \src "libresoc.v:152042.5-152042.29"
switch \initial
- attribute \src "libresoc.v:152378.9-152378.17"
+ attribute \src "libresoc.v:152042.9-152042.17"
case 1'1
case
end
sync always
update \BC $0\BC[1:0]
end
- attribute \src "libresoc.v:152404.3-152440.6"
- process $proc$libresoc.v:152404$7613
+ attribute \src "libresoc.v:152068.3-152104.6"
+ process $proc$libresoc.v:152068$7561
assign { } { }
assign { } { }
assign $0\cr_bit[0:0] $1\cr_bit[0:0]
- attribute \src "libresoc.v:152405.5-152405.29"
+ attribute \src "libresoc.v:152069.5-152069.29"
switch \initial
- attribute \src "libresoc.v:152405.9-152405.17"
+ attribute \src "libresoc.v:152069.9-152069.17"
case 1'1
case
end
sync always
update \cr_bit $0\cr_bit[0:0]
end
- attribute \src "libresoc.v:152441.3-152455.6"
- process $proc$libresoc.v:152441$7614
+ attribute \src "libresoc.v:152105.3-152119.6"
+ process $proc$libresoc.v:152105$7562
assign { } { }
assign { } { }
assign $0\lut[3:0] $1\lut[3:0]
- attribute \src "libresoc.v:152442.5-152442.29"
+ attribute \src "libresoc.v:152106.5-152106.29"
switch \initial
- attribute \src "libresoc.v:152442.9-152442.17"
+ attribute \src "libresoc.v:152106.9-152106.17"
case 1'1
case
end
sync always
update \lut $0\lut[3:0]
end
- attribute \src "libresoc.v:152456.3-152470.6"
- process $proc$libresoc.v:152456$7615
+ attribute \src "libresoc.v:152120.3-152134.6"
+ process $proc$libresoc.v:152120$7563
assign { } { }
assign { } { }
assign $0\bt[1:0] $1\bt[1:0]
- attribute \src "libresoc.v:152457.5-152457.29"
+ attribute \src "libresoc.v:152121.5-152121.29"
switch \initial
- attribute \src "libresoc.v:152457.9-152457.17"
+ attribute \src "libresoc.v:152121.9-152121.17"
case 1'1
case
end
sync always
update \bt $0\bt[1:0]
end
- attribute \src "libresoc.v:152471.3-152485.6"
- process $proc$libresoc.v:152471$7616
+ attribute \src "libresoc.v:152135.3-152149.6"
+ process $proc$libresoc.v:152135$7564
assign { } { }
assign { } { }
assign $0\ba[1:0] $1\ba[1:0]
- attribute \src "libresoc.v:152472.5-152472.29"
+ attribute \src "libresoc.v:152136.5-152136.29"
switch \initial
- attribute \src "libresoc.v:152472.9-152472.17"
+ attribute \src "libresoc.v:152136.9-152136.17"
case 1'1
case
end
sync always
update \ba $0\ba[1:0]
end
- attribute \src "libresoc.v:152486.3-152500.6"
- process $proc$libresoc.v:152486$7617
+ attribute \src "libresoc.v:152150.3-152164.6"
+ process $proc$libresoc.v:152150$7565
assign { } { }
assign { } { }
assign $0\bb[1:0] $1\bb[1:0]
- attribute \src "libresoc.v:152487.5-152487.29"
+ attribute \src "libresoc.v:152151.5-152151.29"
switch \initial
- attribute \src "libresoc.v:152487.9-152487.17"
+ attribute \src "libresoc.v:152151.9-152151.17"
case 1'1
case
end
sync always
update \bb $0\bb[1:0]
end
- attribute \src "libresoc.v:152501.3-152525.6"
- process $proc$libresoc.v:152501$7618
+ attribute \src "libresoc.v:152165.3-152189.6"
+ process $proc$libresoc.v:152165$7566
assign { } { }
assign { } { }
assign $0\bit_a[0:0] $1\bit_a[0:0]
- attribute \src "libresoc.v:152502.5-152502.29"
+ attribute \src "libresoc.v:152166.5-152166.29"
switch \initial
- attribute \src "libresoc.v:152502.9-152502.17"
+ attribute \src "libresoc.v:152166.9-152166.17"
case 1'1
case
end
sync always
update \bit_a $0\bit_a[0:0]
end
- attribute \src "libresoc.v:152526.3-152550.6"
- process $proc$libresoc.v:152526$7619
+ attribute \src "libresoc.v:152190.3-152214.6"
+ process $proc$libresoc.v:152190$7567
assign { } { }
assign { } { }
assign $0\bit_b[0:0] $1\bit_b[0:0]
- attribute \src "libresoc.v:152527.5-152527.29"
+ attribute \src "libresoc.v:152191.5-152191.29"
switch \initial
- attribute \src "libresoc.v:152527.9-152527.17"
+ attribute \src "libresoc.v:152191.9-152191.17"
case 1'1
case
end
sync always
update \bit_b $0\bit_b[0:0]
end
- attribute \src "libresoc.v:152551.3-152565.6"
- process $proc$libresoc.v:152551$7620
+ attribute \src "libresoc.v:152215.3-152229.6"
+ process $proc$libresoc.v:152215$7568
assign { } { }
assign { } { }
assign $0\bit_o[0:0] $1\bit_o[0:0]
- attribute \src "libresoc.v:152552.5-152552.29"
+ attribute \src "libresoc.v:152216.5-152216.29"
switch \initial
- attribute \src "libresoc.v:152552.9-152552.17"
+ attribute \src "libresoc.v:152216.9-152216.17"
case 1'1
case
end
sync always
update \bit_o $0\bit_o[0:0]
end
- attribute \src "libresoc.v:152566.3-152584.6"
- process $proc$libresoc.v:152566$7621
+ attribute \src "libresoc.v:152230.3-152248.6"
+ process $proc$libresoc.v:152230$7569
assign { } { }
assign { } { }
- assign $0\full_cr$5[31:0]$7622 $1\full_cr$5[31:0]$7623
- attribute \src "libresoc.v:152567.5-152567.29"
+ assign $0\full_cr$5[31:0]$7570 $1\full_cr$5[31:0]$7571
+ attribute \src "libresoc.v:152231.5-152231.29"
switch \initial
- attribute \src "libresoc.v:152567.9-152567.17"
+ attribute \src "libresoc.v:152231.9-152231.17"
case 1'1
case
end
switch \cr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0101010
- assign $1\full_cr$5[31:0]$7623 0
+ assign $1\full_cr$5[31:0]$7571 0
attribute \src "libresoc.v:0.0-0.0"
case 7'1000101
- assign $1\full_cr$5[31:0]$7623 0
+ assign $1\full_cr$5[31:0]$7571 0
attribute \src "libresoc.v:0.0-0.0"
case 7'0110000
assign { } { }
- assign $1\full_cr$5[31:0]$7623 \ra [31:0]
+ assign $1\full_cr$5[31:0]$7571 \ra [31:0]
case
- assign $1\full_cr$5[31:0]$7623 0
+ assign $1\full_cr$5[31:0]$7571 0
end
sync always
- update \full_cr$5 $0\full_cr$5[31:0]$7622
+ update \full_cr$5 $0\full_cr$5[31:0]$7570
end
- connect \$10 $sub$libresoc.v:152259$7593_Y
- connect \$13 $sub$libresoc.v:152260$7594_Y
- connect \$16 $sub$libresoc.v:152261$7595_Y
- connect \$18 $ternary$libresoc.v:152262$7596_Y
- connect \$20 $ternary$libresoc.v:152263$7597_Y
- connect \$22 $ternary$libresoc.v:152264$7598_Y
- connect \$24 $pos$libresoc.v:152265$7600_Y
- connect \$27 $ternary$libresoc.v:152266$7601_Y
- connect \$26 $pos$libresoc.v:152267$7603_Y
- connect \$7 $pos$libresoc.v:152268$7605_Y
+ connect \$10 $sub$libresoc.v:151923$7541_Y
+ connect \$13 $sub$libresoc.v:151924$7542_Y
+ connect \$16 $sub$libresoc.v:151925$7543_Y
+ connect \$18 $ternary$libresoc.v:151926$7544_Y
+ connect \$20 $ternary$libresoc.v:151927$7545_Y
+ connect \$22 $ternary$libresoc.v:151928$7546_Y
+ connect \$24 $pos$libresoc.v:151929$7548_Y
+ connect \$27 $ternary$libresoc.v:151930$7549_Y
+ connect \$26 $pos$libresoc.v:151931$7551_Y
+ connect \$7 $pos$libresoc.v:151932$7553_Y
connect \$9 \$10
connect \$12 \$13
connect \$15 \$16
connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
connect \muxid$1 \muxid
end
-attribute \src "libresoc.v:152594.1-153755.10"
+attribute \src "libresoc.v:152258.1-153419.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0"
attribute \generator "nMigen"
module \mul0
- attribute \src "libresoc.v:153326.3-153327.25"
+ attribute \src "libresoc.v:152990.3-152991.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:153324.3-153325.40"
+ attribute \src "libresoc.v:152988.3-152989.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:153667.3-153675.6"
- wire $0\alu_l_r_alu$next[0:0]$7830
- attribute \src "libresoc.v:153252.3-153253.39"
+ attribute \src "libresoc.v:153331.3-153339.6"
+ wire $0\alu_l_r_alu$next[0:0]$7778
+ attribute \src "libresoc.v:152916.3-152917.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755
- attribute \src "libresoc.v:153280.3-153281.65"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703
+ attribute \src "libresoc.v:152944.3-152945.65"
wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756
- attribute \src "libresoc.v:153282.3-153283.79"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704
+ attribute \src "libresoc.v:152946.3-152947.79"
wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757
- attribute \src "libresoc.v:153284.3-153285.75"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705
+ attribute \src "libresoc.v:152948.3-152949.75"
wire $0\alu_mul0_mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7758
- attribute \src "libresoc.v:153300.3-153301.59"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7706
+ attribute \src "libresoc.v:152964.3-152965.59"
wire width 32 $0\alu_mul0_mul_op__insn[31:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7759
- attribute \src "libresoc.v:153278.3-153279.69"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7707
+ attribute \src "libresoc.v:152942.3-152943.69"
wire width 7 $0\alu_mul0_mul_op__insn_type[6:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760
- attribute \src "libresoc.v:153296.3-153297.67"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708
+ attribute \src "libresoc.v:152960.3-152961.67"
wire $0\alu_mul0_mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7761
- attribute \src "libresoc.v:153298.3-153299.69"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7709
+ attribute \src "libresoc.v:152962.3-152963.69"
wire $0\alu_mul0_mul_op__is_signed[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762
- attribute \src "libresoc.v:153290.3-153291.63"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710
+ attribute \src "libresoc.v:152954.3-152955.63"
wire $0\alu_mul0_mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763
- attribute \src "libresoc.v:153292.3-153293.63"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711
+ attribute \src "libresoc.v:152956.3-152957.63"
wire $0\alu_mul0_mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764
- attribute \src "libresoc.v:153288.3-153289.63"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712
+ attribute \src "libresoc.v:152952.3-152953.63"
wire $0\alu_mul0_mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765
- attribute \src "libresoc.v:153286.3-153287.63"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713
+ attribute \src "libresoc.v:152950.3-152951.63"
wire $0\alu_mul0_mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766
- attribute \src "libresoc.v:153294.3-153295.69"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714
+ attribute \src "libresoc.v:152958.3-152959.69"
wire $0\alu_mul0_mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:153658.3-153666.6"
- wire $0\alui_l_r_alui$next[0:0]$7827
- attribute \src "libresoc.v:153254.3-153255.43"
+ attribute \src "libresoc.v:153322.3-153330.6"
+ wire $0\alui_l_r_alui$next[0:0]$7775
+ attribute \src "libresoc.v:152918.3-152919.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:153540.3-153561.6"
- wire width 64 $0\data_r0__o$next[63:0]$7786
- attribute \src "libresoc.v:153274.3-153275.37"
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire width 64 $0\data_r0__o$next[63:0]$7734
+ attribute \src "libresoc.v:152938.3-152939.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:153540.3-153561.6"
- wire $0\data_r0__o_ok$next[0:0]$7787
- attribute \src "libresoc.v:153276.3-153277.43"
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire $0\data_r0__o_ok$next[0:0]$7735
+ attribute \src "libresoc.v:152940.3-152941.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:153562.3-153583.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$7794
- attribute \src "libresoc.v:153270.3-153271.43"
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$7742
+ attribute \src "libresoc.v:152934.3-152935.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:153562.3-153583.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$7795
- attribute \src "libresoc.v:153272.3-153273.49"
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$7743
+ attribute \src "libresoc.v:152936.3-152937.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:153584.3-153605.6"
- wire width 2 $0\data_r2__xer_ov$next[1:0]$7802
- attribute \src "libresoc.v:153266.3-153267.47"
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire width 2 $0\data_r2__xer_ov$next[1:0]$7750
+ attribute \src "libresoc.v:152930.3-152931.47"
wire width 2 $0\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:153584.3-153605.6"
- wire $0\data_r2__xer_ov_ok$next[0:0]$7803
- attribute \src "libresoc.v:153268.3-153269.53"
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire $0\data_r2__xer_ov_ok$next[0:0]$7751
+ attribute \src "libresoc.v:152932.3-152933.53"
wire $0\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $0\data_r3__xer_so$next[0:0]$7810
- attribute \src "libresoc.v:153262.3-153263.47"
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $0\data_r3__xer_so$next[0:0]$7758
+ attribute \src "libresoc.v:152926.3-152927.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$7811
- attribute \src "libresoc.v:153264.3-153265.53"
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$7759
+ attribute \src "libresoc.v:152928.3-152929.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:153676.3-153685.6"
+ attribute \src "libresoc.v:153340.3-153349.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:153686.3-153695.6"
+ attribute \src "libresoc.v:153350.3-153359.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:153696.3-153705.6"
+ attribute \src "libresoc.v:153360.3-153369.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:153706.3-153715.6"
+ attribute \src "libresoc.v:153370.3-153379.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:152595.7-152595.20"
+ attribute \src "libresoc.v:152259.7-152259.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:153462.3-153470.6"
- wire $0\opc_l_r_opc$next[0:0]$7740
- attribute \src "libresoc.v:153310.3-153311.39"
+ attribute \src "libresoc.v:153126.3-153134.6"
+ wire $0\opc_l_r_opc$next[0:0]$7688
+ attribute \src "libresoc.v:152974.3-152975.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:153453.3-153461.6"
- wire $0\opc_l_s_opc$next[0:0]$7737
- attribute \src "libresoc.v:153312.3-153313.39"
+ attribute \src "libresoc.v:153117.3-153125.6"
+ wire $0\opc_l_s_opc$next[0:0]$7685
+ attribute \src "libresoc.v:152976.3-152977.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:153716.3-153724.6"
- wire width 4 $0\prev_wr_go$next[3:0]$7837
- attribute \src "libresoc.v:153322.3-153323.37"
+ attribute \src "libresoc.v:153380.3-153388.6"
+ wire width 4 $0\prev_wr_go$next[3:0]$7785
+ attribute \src "libresoc.v:152986.3-152987.37"
wire width 4 $0\prev_wr_go[3:0]
- attribute \src "libresoc.v:153407.3-153416.6"
+ attribute \src "libresoc.v:153071.3-153080.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:153498.3-153506.6"
- wire width 4 $0\req_l_r_req$next[3:0]$7752
- attribute \src "libresoc.v:153302.3-153303.39"
+ attribute \src "libresoc.v:153162.3-153170.6"
+ wire width 4 $0\req_l_r_req$next[3:0]$7700
+ attribute \src "libresoc.v:152966.3-152967.39"
wire width 4 $0\req_l_r_req[3:0]
- attribute \src "libresoc.v:153489.3-153497.6"
- wire width 4 $0\req_l_s_req$next[3:0]$7749
- attribute \src "libresoc.v:153304.3-153305.39"
+ attribute \src "libresoc.v:153153.3-153161.6"
+ wire width 4 $0\req_l_s_req$next[3:0]$7697
+ attribute \src "libresoc.v:152968.3-152969.39"
wire width 4 $0\req_l_s_req[3:0]
- attribute \src "libresoc.v:153426.3-153434.6"
- wire $0\rok_l_r_rdok$next[0:0]$7728
- attribute \src "libresoc.v:153318.3-153319.41"
+ attribute \src "libresoc.v:153090.3-153098.6"
+ wire $0\rok_l_r_rdok$next[0:0]$7676
+ attribute \src "libresoc.v:152982.3-152983.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:153417.3-153425.6"
- wire $0\rok_l_s_rdok$next[0:0]$7725
- attribute \src "libresoc.v:153320.3-153321.41"
+ attribute \src "libresoc.v:153081.3-153089.6"
+ wire $0\rok_l_s_rdok$next[0:0]$7673
+ attribute \src "libresoc.v:152984.3-152985.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:153444.3-153452.6"
- wire $0\rst_l_r_rst$next[0:0]$7734
- attribute \src "libresoc.v:153314.3-153315.39"
+ attribute \src "libresoc.v:153108.3-153116.6"
+ wire $0\rst_l_r_rst$next[0:0]$7682
+ attribute \src "libresoc.v:152978.3-152979.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:153435.3-153443.6"
- wire $0\rst_l_s_rst$next[0:0]$7731
- attribute \src "libresoc.v:153316.3-153317.39"
+ attribute \src "libresoc.v:153099.3-153107.6"
+ wire $0\rst_l_s_rst$next[0:0]$7679
+ attribute \src "libresoc.v:152980.3-152981.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:153480.3-153488.6"
- wire width 3 $0\src_l_r_src$next[2:0]$7746
- attribute \src "libresoc.v:153306.3-153307.39"
+ attribute \src "libresoc.v:153144.3-153152.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$7694
+ attribute \src "libresoc.v:152970.3-152971.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:153471.3-153479.6"
- wire width 3 $0\src_l_s_src$next[2:0]$7743
- attribute \src "libresoc.v:153308.3-153309.39"
+ attribute \src "libresoc.v:153135.3-153143.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$7691
+ attribute \src "libresoc.v:152972.3-152973.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:153628.3-153637.6"
- wire width 64 $0\src_r0$next[63:0]$7818
- attribute \src "libresoc.v:153260.3-153261.29"
+ attribute \src "libresoc.v:153292.3-153301.6"
+ wire width 64 $0\src_r0$next[63:0]$7766
+ attribute \src "libresoc.v:152924.3-152925.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:153638.3-153647.6"
- wire width 64 $0\src_r1$next[63:0]$7821
- attribute \src "libresoc.v:153258.3-153259.29"
+ attribute \src "libresoc.v:153302.3-153311.6"
+ wire width 64 $0\src_r1$next[63:0]$7769
+ attribute \src "libresoc.v:152922.3-152923.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:153648.3-153657.6"
- wire $0\src_r2$next[0:0]$7824
- attribute \src "libresoc.v:153256.3-153257.29"
+ attribute \src "libresoc.v:153312.3-153321.6"
+ wire $0\src_r2$next[0:0]$7772
+ attribute \src "libresoc.v:152920.3-152921.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:152719.7-152719.24"
+ attribute \src "libresoc.v:152383.7-152383.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:152729.7-152729.26"
+ attribute \src "libresoc.v:152393.7-152393.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:153667.3-153675.6"
- wire $1\alu_l_r_alu$next[0:0]$7831
- attribute \src "libresoc.v:152737.7-152737.25"
+ attribute \src "libresoc.v:153331.3-153339.6"
+ wire $1\alu_l_r_alu$next[0:0]$7779
+ attribute \src "libresoc.v:152401.7-152401.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767
- attribute \src "libresoc.v:152760.14-152760.49"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715
+ attribute \src "libresoc.v:152424.14-152424.49"
wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768
- attribute \src "libresoc.v:152764.14-152764.68"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716
+ attribute \src "libresoc.v:152428.14-152428.68"
wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769
- attribute \src "libresoc.v:152768.7-152768.43"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717
+ attribute \src "libresoc.v:152432.7-152432.43"
wire $1\alu_mul0_mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7770
- attribute \src "libresoc.v:152772.14-152772.43"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7718
+ attribute \src "libresoc.v:152436.14-152436.43"
wire width 32 $1\alu_mul0_mul_op__insn[31:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771
- attribute \src "libresoc.v:152851.13-152851.47"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719
+ attribute \src "libresoc.v:152515.13-152515.47"
wire width 7 $1\alu_mul0_mul_op__insn_type[6:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772
- attribute \src "libresoc.v:152855.7-152855.39"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720
+ attribute \src "libresoc.v:152519.7-152519.39"
wire $1\alu_mul0_mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7773
- attribute \src "libresoc.v:152859.7-152859.40"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7721
+ attribute \src "libresoc.v:152523.7-152523.40"
wire $1\alu_mul0_mul_op__is_signed[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774
- attribute \src "libresoc.v:152863.7-152863.37"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722
+ attribute \src "libresoc.v:152527.7-152527.37"
wire $1\alu_mul0_mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775
- attribute \src "libresoc.v:152867.7-152867.37"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723
+ attribute \src "libresoc.v:152531.7-152531.37"
wire $1\alu_mul0_mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776
- attribute \src "libresoc.v:152871.7-152871.37"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724
+ attribute \src "libresoc.v:152535.7-152535.37"
wire $1\alu_mul0_mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777
- attribute \src "libresoc.v:152875.7-152875.37"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725
+ attribute \src "libresoc.v:152539.7-152539.37"
wire $1\alu_mul0_mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778
- attribute \src "libresoc.v:152879.7-152879.40"
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726
+ attribute \src "libresoc.v:152543.7-152543.40"
wire $1\alu_mul0_mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:153658.3-153666.6"
- wire $1\alui_l_r_alui$next[0:0]$7828
- attribute \src "libresoc.v:152909.7-152909.27"
+ attribute \src "libresoc.v:153322.3-153330.6"
+ wire $1\alui_l_r_alui$next[0:0]$7776
+ attribute \src "libresoc.v:152573.7-152573.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:153540.3-153561.6"
- wire width 64 $1\data_r0__o$next[63:0]$7788
- attribute \src "libresoc.v:152943.14-152943.47"
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire width 64 $1\data_r0__o$next[63:0]$7736
+ attribute \src "libresoc.v:152607.14-152607.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:153540.3-153561.6"
- wire $1\data_r0__o_ok$next[0:0]$7789
- attribute \src "libresoc.v:152947.7-152947.27"
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire $1\data_r0__o_ok$next[0:0]$7737
+ attribute \src "libresoc.v:152611.7-152611.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:153562.3-153583.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$7796
- attribute \src "libresoc.v:152951.13-152951.33"
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$7744
+ attribute \src "libresoc.v:152615.13-152615.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:153562.3-153583.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$7797
- attribute \src "libresoc.v:152955.7-152955.30"
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$7745
+ attribute \src "libresoc.v:152619.7-152619.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:153584.3-153605.6"
- wire width 2 $1\data_r2__xer_ov$next[1:0]$7804
- attribute \src "libresoc.v:152959.13-152959.35"
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire width 2 $1\data_r2__xer_ov$next[1:0]$7752
+ attribute \src "libresoc.v:152623.13-152623.35"
wire width 2 $1\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:153584.3-153605.6"
- wire $1\data_r2__xer_ov_ok$next[0:0]$7805
- attribute \src "libresoc.v:152963.7-152963.32"
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire $1\data_r2__xer_ov_ok$next[0:0]$7753
+ attribute \src "libresoc.v:152627.7-152627.32"
wire $1\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $1\data_r3__xer_so$next[0:0]$7812
- attribute \src "libresoc.v:152967.7-152967.29"
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $1\data_r3__xer_so$next[0:0]$7760
+ attribute \src "libresoc.v:152631.7-152631.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$7813
- attribute \src "libresoc.v:152971.7-152971.32"
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$7761
+ attribute \src "libresoc.v:152635.7-152635.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:153676.3-153685.6"
+ attribute \src "libresoc.v:153340.3-153349.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:153686.3-153695.6"
+ attribute \src "libresoc.v:153350.3-153359.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:153696.3-153705.6"
+ attribute \src "libresoc.v:153360.3-153369.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:153706.3-153715.6"
+ attribute \src "libresoc.v:153370.3-153379.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:153462.3-153470.6"
- wire $1\opc_l_r_opc$next[0:0]$7741
- attribute \src "libresoc.v:152991.7-152991.25"
+ attribute \src "libresoc.v:153126.3-153134.6"
+ wire $1\opc_l_r_opc$next[0:0]$7689
+ attribute \src "libresoc.v:152655.7-152655.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:153453.3-153461.6"
- wire $1\opc_l_s_opc$next[0:0]$7738
- attribute \src "libresoc.v:152995.7-152995.25"
+ attribute \src "libresoc.v:153117.3-153125.6"
+ wire $1\opc_l_s_opc$next[0:0]$7686
+ attribute \src "libresoc.v:152659.7-152659.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:153716.3-153724.6"
- wire width 4 $1\prev_wr_go$next[3:0]$7838
- attribute \src "libresoc.v:153113.13-153113.30"
+ attribute \src "libresoc.v:153380.3-153388.6"
+ wire width 4 $1\prev_wr_go$next[3:0]$7786
+ attribute \src "libresoc.v:152777.13-152777.30"
wire width 4 $1\prev_wr_go[3:0]
- attribute \src "libresoc.v:153407.3-153416.6"
+ attribute \src "libresoc.v:153071.3-153080.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:153498.3-153506.6"
- wire width 4 $1\req_l_r_req$next[3:0]$7753
- attribute \src "libresoc.v:153121.13-153121.31"
+ attribute \src "libresoc.v:153162.3-153170.6"
+ wire width 4 $1\req_l_r_req$next[3:0]$7701
+ attribute \src "libresoc.v:152785.13-152785.31"
wire width 4 $1\req_l_r_req[3:0]
- attribute \src "libresoc.v:153489.3-153497.6"
- wire width 4 $1\req_l_s_req$next[3:0]$7750
- attribute \src "libresoc.v:153125.13-153125.31"
+ attribute \src "libresoc.v:153153.3-153161.6"
+ wire width 4 $1\req_l_s_req$next[3:0]$7698
+ attribute \src "libresoc.v:152789.13-152789.31"
wire width 4 $1\req_l_s_req[3:0]
- attribute \src "libresoc.v:153426.3-153434.6"
- wire $1\rok_l_r_rdok$next[0:0]$7729
- attribute \src "libresoc.v:153137.7-153137.26"
+ attribute \src "libresoc.v:153090.3-153098.6"
+ wire $1\rok_l_r_rdok$next[0:0]$7677
+ attribute \src "libresoc.v:152801.7-152801.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:153417.3-153425.6"
- wire $1\rok_l_s_rdok$next[0:0]$7726
- attribute \src "libresoc.v:153141.7-153141.26"
+ attribute \src "libresoc.v:153081.3-153089.6"
+ wire $1\rok_l_s_rdok$next[0:0]$7674
+ attribute \src "libresoc.v:152805.7-152805.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:153444.3-153452.6"
- wire $1\rst_l_r_rst$next[0:0]$7735
- attribute \src "libresoc.v:153145.7-153145.25"
+ attribute \src "libresoc.v:153108.3-153116.6"
+ wire $1\rst_l_r_rst$next[0:0]$7683
+ attribute \src "libresoc.v:152809.7-152809.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:153435.3-153443.6"
- wire $1\rst_l_s_rst$next[0:0]$7732
- attribute \src "libresoc.v:153149.7-153149.25"
+ attribute \src "libresoc.v:153099.3-153107.6"
+ wire $1\rst_l_s_rst$next[0:0]$7680
+ attribute \src "libresoc.v:152813.7-152813.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:153480.3-153488.6"
- wire width 3 $1\src_l_r_src$next[2:0]$7747
- attribute \src "libresoc.v:153163.13-153163.31"
+ attribute \src "libresoc.v:153144.3-153152.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$7695
+ attribute \src "libresoc.v:152827.13-152827.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:153471.3-153479.6"
- wire width 3 $1\src_l_s_src$next[2:0]$7744
- attribute \src "libresoc.v:153167.13-153167.31"
+ attribute \src "libresoc.v:153135.3-153143.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$7692
+ attribute \src "libresoc.v:152831.13-152831.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:153628.3-153637.6"
- wire width 64 $1\src_r0$next[63:0]$7819
- attribute \src "libresoc.v:153173.14-153173.43"
+ attribute \src "libresoc.v:153292.3-153301.6"
+ wire width 64 $1\src_r0$next[63:0]$7767
+ attribute \src "libresoc.v:152837.14-152837.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:153638.3-153647.6"
- wire width 64 $1\src_r1$next[63:0]$7822
- attribute \src "libresoc.v:153177.14-153177.43"
+ attribute \src "libresoc.v:153302.3-153311.6"
+ wire width 64 $1\src_r1$next[63:0]$7770
+ attribute \src "libresoc.v:152841.14-152841.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:153648.3-153657.6"
- wire $1\src_r2$next[0:0]$7825
- attribute \src "libresoc.v:153181.7-153181.20"
+ attribute \src "libresoc.v:153312.3-153321.6"
+ wire $1\src_r2$next[0:0]$7773
+ attribute \src "libresoc.v:152845.7-152845.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:153507.3-153539.6"
- wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783
- attribute \src "libresoc.v:153507.3-153539.6"
- wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784
- attribute \src "libresoc.v:153540.3-153561.6"
- wire width 64 $2\data_r0__o$next[63:0]$7790
- attribute \src "libresoc.v:153540.3-153561.6"
- wire $2\data_r0__o_ok$next[0:0]$7791
- attribute \src "libresoc.v:153562.3-153583.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$7798
- attribute \src "libresoc.v:153562.3-153583.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$7799
- attribute \src "libresoc.v:153584.3-153605.6"
- wire width 2 $2\data_r2__xer_ov$next[1:0]$7806
- attribute \src "libresoc.v:153584.3-153605.6"
- wire $2\data_r2__xer_ov_ok$next[0:0]$7807
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $2\data_r3__xer_so$next[0:0]$7814
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$7815
- attribute \src "libresoc.v:153540.3-153561.6"
- wire $3\data_r0__o_ok$next[0:0]$7792
- attribute \src "libresoc.v:153562.3-153583.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$7800
- attribute \src "libresoc.v:153584.3-153605.6"
- wire $3\data_r2__xer_ov_ok$next[0:0]$7808
- attribute \src "libresoc.v:153606.3-153627.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$7816
- attribute \src "libresoc.v:153192.19-153192.113"
- wire width 3 $and$libresoc.v:153192$7625_Y
- attribute \src "libresoc.v:153193.19-153193.125"
- wire $and$libresoc.v:153193$7626_Y
- attribute \src "libresoc.v:153194.19-153194.125"
- wire $and$libresoc.v:153194$7627_Y
- attribute \src "libresoc.v:153195.19-153195.125"
- wire $and$libresoc.v:153195$7628_Y
- attribute \src "libresoc.v:153196.19-153196.125"
- wire $and$libresoc.v:153196$7629_Y
- attribute \src "libresoc.v:153197.18-153197.110"
- wire $and$libresoc.v:153197$7630_Y
- attribute \src "libresoc.v:153198.19-153198.149"
- wire width 4 $and$libresoc.v:153198$7631_Y
- attribute \src "libresoc.v:153199.19-153199.121"
- wire width 4 $and$libresoc.v:153199$7632_Y
- attribute \src "libresoc.v:153200.19-153200.127"
- wire $and$libresoc.v:153200$7633_Y
- attribute \src "libresoc.v:153201.19-153201.127"
- wire $and$libresoc.v:153201$7634_Y
- attribute \src "libresoc.v:153202.19-153202.127"
- wire $and$libresoc.v:153202$7635_Y
- attribute \src "libresoc.v:153203.19-153203.127"
- wire $and$libresoc.v:153203$7636_Y
- attribute \src "libresoc.v:153205.18-153205.98"
- wire $and$libresoc.v:153205$7638_Y
- attribute \src "libresoc.v:153207.18-153207.100"
- wire $and$libresoc.v:153207$7640_Y
- attribute \src "libresoc.v:153208.18-153208.160"
- wire width 4 $and$libresoc.v:153208$7641_Y
- attribute \src "libresoc.v:153210.18-153210.119"
- wire width 4 $and$libresoc.v:153210$7643_Y
- attribute \src "libresoc.v:153213.17-153213.123"
- wire $and$libresoc.v:153213$7646_Y
- attribute \src "libresoc.v:153214.18-153214.116"
- wire $and$libresoc.v:153214$7647_Y
- attribute \src "libresoc.v:153219.18-153219.113"
- wire $and$libresoc.v:153219$7652_Y
- attribute \src "libresoc.v:153220.18-153220.125"
- wire width 4 $and$libresoc.v:153220$7653_Y
- attribute \src "libresoc.v:153222.18-153222.112"
- wire $and$libresoc.v:153222$7655_Y
- attribute \src "libresoc.v:153224.18-153224.126"
- wire $and$libresoc.v:153224$7657_Y
- attribute \src "libresoc.v:153225.18-153225.126"
- wire $and$libresoc.v:153225$7658_Y
- attribute \src "libresoc.v:153226.18-153226.117"
- wire $and$libresoc.v:153226$7659_Y
- attribute \src "libresoc.v:153232.18-153232.130"
- wire $and$libresoc.v:153232$7665_Y
- attribute \src "libresoc.v:153233.18-153233.124"
- wire width 4 $and$libresoc.v:153233$7666_Y
- attribute \src "libresoc.v:153235.18-153235.116"
- wire $and$libresoc.v:153235$7668_Y
- attribute \src "libresoc.v:153236.18-153236.119"
- wire $and$libresoc.v:153236$7669_Y
- attribute \src "libresoc.v:153237.18-153237.121"
- wire $and$libresoc.v:153237$7670_Y
- attribute \src "libresoc.v:153238.18-153238.121"
- wire $and$libresoc.v:153238$7671_Y
- attribute \src "libresoc.v:153245.18-153245.134"
- wire $and$libresoc.v:153245$7678_Y
- attribute \src "libresoc.v:153247.18-153247.132"
- wire $and$libresoc.v:153247$7680_Y
- attribute \src "libresoc.v:153248.18-153248.149"
- wire width 3 $and$libresoc.v:153248$7681_Y
- attribute \src "libresoc.v:153250.18-153250.129"
- wire width 3 $and$libresoc.v:153250$7683_Y
- attribute \src "libresoc.v:153221.18-153221.113"
- wire $eq$libresoc.v:153221$7654_Y
- attribute \src "libresoc.v:153223.18-153223.119"
- wire $eq$libresoc.v:153223$7656_Y
- attribute \src "libresoc.v:153204.18-153204.97"
- wire $not$libresoc.v:153204$7637_Y
- attribute \src "libresoc.v:153206.18-153206.99"
- wire $not$libresoc.v:153206$7639_Y
- attribute \src "libresoc.v:153209.18-153209.113"
- wire width 4 $not$libresoc.v:153209$7642_Y
- attribute \src "libresoc.v:153212.18-153212.106"
- wire $not$libresoc.v:153212$7645_Y
- attribute \src "libresoc.v:153218.18-153218.120"
- wire $not$libresoc.v:153218$7651_Y
- attribute \src "libresoc.v:153229.17-153229.113"
- wire width 3 $not$libresoc.v:153229$7662_Y
- attribute \src "libresoc.v:153249.18-153249.131"
- wire $not$libresoc.v:153249$7682_Y
- attribute \src "libresoc.v:153251.18-153251.114"
- wire width 3 $not$libresoc.v:153251$7684_Y
- attribute \src "libresoc.v:153217.18-153217.112"
- wire $or$libresoc.v:153217$7650_Y
- attribute \src "libresoc.v:153227.18-153227.122"
- wire $or$libresoc.v:153227$7660_Y
- attribute \src "libresoc.v:153228.18-153228.124"
- wire $or$libresoc.v:153228$7661_Y
- attribute \src "libresoc.v:153230.18-153230.168"
- wire width 4 $or$libresoc.v:153230$7663_Y
- attribute \src "libresoc.v:153231.18-153231.155"
- wire width 3 $or$libresoc.v:153231$7664_Y
- attribute \src "libresoc.v:153234.18-153234.120"
- wire width 4 $or$libresoc.v:153234$7667_Y
- attribute \src "libresoc.v:153240.17-153240.117"
- wire width 3 $or$libresoc.v:153240$7673_Y
- attribute \src "libresoc.v:153246.17-153246.104"
- wire $reduce_and$libresoc.v:153246$7679_Y
- attribute \src "libresoc.v:153211.18-153211.106"
- wire $reduce_or$libresoc.v:153211$7644_Y
- attribute \src "libresoc.v:153215.18-153215.113"
- wire $reduce_or$libresoc.v:153215$7648_Y
- attribute \src "libresoc.v:153216.18-153216.112"
- wire $reduce_or$libresoc.v:153216$7649_Y
- attribute \src "libresoc.v:153239.18-153239.160"
- wire $ternary$libresoc.v:153239$7672_Y
- attribute \src "libresoc.v:153241.18-153241.172"
- wire width 64 $ternary$libresoc.v:153241$7674_Y
- attribute \src "libresoc.v:153242.18-153242.118"
- wire width 64 $ternary$libresoc.v:153242$7675_Y
- attribute \src "libresoc.v:153243.18-153243.115"
- wire width 64 $ternary$libresoc.v:153243$7676_Y
- attribute \src "libresoc.v:153244.18-153244.118"
- wire $ternary$libresoc.v:153244$7677_Y
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731
+ attribute \src "libresoc.v:153171.3-153203.6"
+ wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire width 64 $2\data_r0__o$next[63:0]$7738
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire $2\data_r0__o_ok$next[0:0]$7739
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$7746
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$7747
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire width 2 $2\data_r2__xer_ov$next[1:0]$7754
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire $2\data_r2__xer_ov_ok$next[0:0]$7755
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $2\data_r3__xer_so$next[0:0]$7762
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$7763
+ attribute \src "libresoc.v:153204.3-153225.6"
+ wire $3\data_r0__o_ok$next[0:0]$7740
+ attribute \src "libresoc.v:153226.3-153247.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$7748
+ attribute \src "libresoc.v:153248.3-153269.6"
+ wire $3\data_r2__xer_ov_ok$next[0:0]$7756
+ attribute \src "libresoc.v:153270.3-153291.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$7764
+ attribute \src "libresoc.v:152856.19-152856.113"
+ wire width 3 $and$libresoc.v:152856$7573_Y
+ attribute \src "libresoc.v:152857.19-152857.125"
+ wire $and$libresoc.v:152857$7574_Y
+ attribute \src "libresoc.v:152858.19-152858.125"
+ wire $and$libresoc.v:152858$7575_Y
+ attribute \src "libresoc.v:152859.19-152859.125"
+ wire $and$libresoc.v:152859$7576_Y
+ attribute \src "libresoc.v:152860.19-152860.125"
+ wire $and$libresoc.v:152860$7577_Y
+ attribute \src "libresoc.v:152861.18-152861.110"
+ wire $and$libresoc.v:152861$7578_Y
+ attribute \src "libresoc.v:152862.19-152862.149"
+ wire width 4 $and$libresoc.v:152862$7579_Y
+ attribute \src "libresoc.v:152863.19-152863.121"
+ wire width 4 $and$libresoc.v:152863$7580_Y
+ attribute \src "libresoc.v:152864.19-152864.127"
+ wire $and$libresoc.v:152864$7581_Y
+ attribute \src "libresoc.v:152865.19-152865.127"
+ wire $and$libresoc.v:152865$7582_Y
+ attribute \src "libresoc.v:152866.19-152866.127"
+ wire $and$libresoc.v:152866$7583_Y
+ attribute \src "libresoc.v:152867.19-152867.127"
+ wire $and$libresoc.v:152867$7584_Y
+ attribute \src "libresoc.v:152869.18-152869.98"
+ wire $and$libresoc.v:152869$7586_Y
+ attribute \src "libresoc.v:152871.18-152871.100"
+ wire $and$libresoc.v:152871$7588_Y
+ attribute \src "libresoc.v:152872.18-152872.160"
+ wire width 4 $and$libresoc.v:152872$7589_Y
+ attribute \src "libresoc.v:152874.18-152874.119"
+ wire width 4 $and$libresoc.v:152874$7591_Y
+ attribute \src "libresoc.v:152877.17-152877.123"
+ wire $and$libresoc.v:152877$7594_Y
+ attribute \src "libresoc.v:152878.18-152878.116"
+ wire $and$libresoc.v:152878$7595_Y
+ attribute \src "libresoc.v:152883.18-152883.113"
+ wire $and$libresoc.v:152883$7600_Y
+ attribute \src "libresoc.v:152884.18-152884.125"
+ wire width 4 $and$libresoc.v:152884$7601_Y
+ attribute \src "libresoc.v:152886.18-152886.112"
+ wire $and$libresoc.v:152886$7603_Y
+ attribute \src "libresoc.v:152888.18-152888.126"
+ wire $and$libresoc.v:152888$7605_Y
+ attribute \src "libresoc.v:152889.18-152889.126"
+ wire $and$libresoc.v:152889$7606_Y
+ attribute \src "libresoc.v:152890.18-152890.117"
+ wire $and$libresoc.v:152890$7607_Y
+ attribute \src "libresoc.v:152896.18-152896.130"
+ wire $and$libresoc.v:152896$7613_Y
+ attribute \src "libresoc.v:152897.18-152897.124"
+ wire width 4 $and$libresoc.v:152897$7614_Y
+ attribute \src "libresoc.v:152899.18-152899.116"
+ wire $and$libresoc.v:152899$7616_Y
+ attribute \src "libresoc.v:152900.18-152900.119"
+ wire $and$libresoc.v:152900$7617_Y
+ attribute \src "libresoc.v:152901.18-152901.121"
+ wire $and$libresoc.v:152901$7618_Y
+ attribute \src "libresoc.v:152902.18-152902.121"
+ wire $and$libresoc.v:152902$7619_Y
+ attribute \src "libresoc.v:152909.18-152909.134"
+ wire $and$libresoc.v:152909$7626_Y
+ attribute \src "libresoc.v:152911.18-152911.132"
+ wire $and$libresoc.v:152911$7628_Y
+ attribute \src "libresoc.v:152912.18-152912.149"
+ wire width 3 $and$libresoc.v:152912$7629_Y
+ attribute \src "libresoc.v:152914.18-152914.129"
+ wire width 3 $and$libresoc.v:152914$7631_Y
+ attribute \src "libresoc.v:152885.18-152885.113"
+ wire $eq$libresoc.v:152885$7602_Y
+ attribute \src "libresoc.v:152887.18-152887.119"
+ wire $eq$libresoc.v:152887$7604_Y
+ attribute \src "libresoc.v:152868.18-152868.97"
+ wire $not$libresoc.v:152868$7585_Y
+ attribute \src "libresoc.v:152870.18-152870.99"
+ wire $not$libresoc.v:152870$7587_Y
+ attribute \src "libresoc.v:152873.18-152873.113"
+ wire width 4 $not$libresoc.v:152873$7590_Y
+ attribute \src "libresoc.v:152876.18-152876.106"
+ wire $not$libresoc.v:152876$7593_Y
+ attribute \src "libresoc.v:152882.18-152882.120"
+ wire $not$libresoc.v:152882$7599_Y
+ attribute \src "libresoc.v:152893.17-152893.113"
+ wire width 3 $not$libresoc.v:152893$7610_Y
+ attribute \src "libresoc.v:152913.18-152913.131"
+ wire $not$libresoc.v:152913$7630_Y
+ attribute \src "libresoc.v:152915.18-152915.114"
+ wire width 3 $not$libresoc.v:152915$7632_Y
+ attribute \src "libresoc.v:152881.18-152881.112"
+ wire $or$libresoc.v:152881$7598_Y
+ attribute \src "libresoc.v:152891.18-152891.122"
+ wire $or$libresoc.v:152891$7608_Y
+ attribute \src "libresoc.v:152892.18-152892.124"
+ wire $or$libresoc.v:152892$7609_Y
+ attribute \src "libresoc.v:152894.18-152894.168"
+ wire width 4 $or$libresoc.v:152894$7611_Y
+ attribute \src "libresoc.v:152895.18-152895.155"
+ wire width 3 $or$libresoc.v:152895$7612_Y
+ attribute \src "libresoc.v:152898.18-152898.120"
+ wire width 4 $or$libresoc.v:152898$7615_Y
+ attribute \src "libresoc.v:152904.17-152904.117"
+ wire width 3 $or$libresoc.v:152904$7621_Y
+ attribute \src "libresoc.v:152910.17-152910.104"
+ wire $reduce_and$libresoc.v:152910$7627_Y
+ attribute \src "libresoc.v:152875.18-152875.106"
+ wire $reduce_or$libresoc.v:152875$7592_Y
+ attribute \src "libresoc.v:152879.18-152879.113"
+ wire $reduce_or$libresoc.v:152879$7596_Y
+ attribute \src "libresoc.v:152880.18-152880.112"
+ wire $reduce_or$libresoc.v:152880$7597_Y
+ attribute \src "libresoc.v:152903.18-152903.160"
+ wire $ternary$libresoc.v:152903$7620_Y
+ attribute \src "libresoc.v:152905.18-152905.172"
+ wire width 64 $ternary$libresoc.v:152905$7622_Y
+ attribute \src "libresoc.v:152906.18-152906.118"
+ wire width 64 $ternary$libresoc.v:152906$7623_Y
+ attribute \src "libresoc.v:152907.18-152907.115"
+ wire width 64 $ternary$libresoc.v:152907$7624_Y
+ attribute \src "libresoc.v:152908.18-152908.118"
+ wire $ternary$libresoc.v:152908$7625_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 26 \cr_a_ok
wire width 2 output 29 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire output 31 \dest4_o
- attribute \src "libresoc.v:152595.7-152595.15"
+ attribute \src "libresoc.v:152259.7-152259.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 22 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 19 \src1_i
+ wire width 64 input 20 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 20 \src2_i
+ wire width 64 input 19 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 21 \src3_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 30 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:153192$7625
+ cell $and $and$libresoc.v:152856$7573
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$96
connect \B \$98
- connect \Y $and$libresoc.v:153192$7625_Y
+ connect \Y $and$libresoc.v:152856$7573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:153193$7626
+ cell $and $and$libresoc.v:152857$7574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:153193$7626_Y
+ connect \Y $and$libresoc.v:152857$7574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:153194$7627
+ cell $and $and$libresoc.v:152858$7575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:153194$7627_Y
+ connect \Y $and$libresoc.v:152858$7575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:153195$7628
+ cell $and $and$libresoc.v:152859$7576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:153195$7628_Y
+ connect \Y $and$libresoc.v:152859$7576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:153196$7629
+ cell $and $and$libresoc.v:152860$7577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:153196$7629_Y
+ connect \Y $and$libresoc.v:152860$7577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:153197$7630
+ cell $and $and$libresoc.v:152861$7578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:153197$7630_Y
+ connect \Y $and$libresoc.v:152861$7578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:153198$7631
+ cell $and $and$libresoc.v:152862$7579
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B { \$102 \$104 \$106 \$108 }
- connect \Y $and$libresoc.v:153198$7631_Y
+ connect \Y $and$libresoc.v:152862$7579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:153199$7632
+ cell $and $and$libresoc.v:152863$7580
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$110
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:153199$7632_Y
+ connect \Y $and$libresoc.v:152863$7580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:153200$7633
+ cell $and $and$libresoc.v:152864$7581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153200$7633_Y
+ connect \Y $and$libresoc.v:152864$7581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:153201$7634
+ cell $and $and$libresoc.v:152865$7582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153201$7634_Y
+ connect \Y $and$libresoc.v:152865$7582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:153202$7635
+ cell $and $and$libresoc.v:152866$7583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153202$7635_Y
+ connect \Y $and$libresoc.v:152866$7583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:153203$7636
+ cell $and $and$libresoc.v:152867$7584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153203$7636_Y
+ connect \Y $and$libresoc.v:152867$7584_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:153205$7638
+ cell $and $and$libresoc.v:152869$7586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:153205$7638_Y
+ connect \Y $and$libresoc.v:152869$7586_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:153207$7640
+ cell $and $and$libresoc.v:152871$7588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:153207$7640_Y
+ connect \Y $and$libresoc.v:152871$7588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:153208$7641
+ cell $and $and$libresoc.v:152872$7589
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:153208$7641_Y
+ connect \Y $and$libresoc.v:152872$7589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:153210$7643
+ cell $and $and$libresoc.v:152874$7591
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:153210$7643_Y
+ connect \Y $and$libresoc.v:152874$7591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:153213$7646
+ cell $and $and$libresoc.v:152877$7594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:153213$7646_Y
+ connect \Y $and$libresoc.v:152877$7594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:153214$7647
+ cell $and $and$libresoc.v:152878$7595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:153214$7647_Y
+ connect \Y $and$libresoc.v:152878$7595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:153219$7652
+ cell $and $and$libresoc.v:152883$7600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:153219$7652_Y
+ connect \Y $and$libresoc.v:152883$7600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:153220$7653
+ cell $and $and$libresoc.v:152884$7601
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:153220$7653_Y
+ connect \Y $and$libresoc.v:152884$7601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:153222$7655
+ cell $and $and$libresoc.v:152886$7603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:153222$7655_Y
+ connect \Y $and$libresoc.v:152886$7603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:153224$7657
+ cell $and $and$libresoc.v:152888$7605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_mul0_n_ready_i
- connect \Y $and$libresoc.v:153224$7657_Y
+ connect \Y $and$libresoc.v:152888$7605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:153225$7658
+ cell $and $and$libresoc.v:152889$7606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_mul0_n_valid_o
- connect \Y $and$libresoc.v:153225$7658_Y
+ connect \Y $and$libresoc.v:152889$7606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:153226$7659
+ cell $and $and$libresoc.v:152890$7607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153226$7659_Y
+ connect \Y $and$libresoc.v:152890$7607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:153232$7665
+ cell $and $and$libresoc.v:152896$7613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153232$7665_Y
+ connect \Y $and$libresoc.v:152896$7613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:153233$7666
+ cell $and $and$libresoc.v:152897$7614
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:153233$7666_Y
+ connect \Y $and$libresoc.v:152897$7614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:153235$7668
+ cell $and $and$libresoc.v:152899$7616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153235$7668_Y
+ connect \Y $and$libresoc.v:152899$7616_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:153236$7669
+ cell $and $and$libresoc.v:152900$7617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153236$7669_Y
+ connect \Y $and$libresoc.v:152900$7617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:153237$7670
+ cell $and $and$libresoc.v:152901$7618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153237$7670_Y
+ connect \Y $and$libresoc.v:152901$7618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:153238$7671
+ cell $and $and$libresoc.v:152902$7619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:153238$7671_Y
+ connect \Y $and$libresoc.v:152902$7619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:153245$7678
+ cell $and $and$libresoc.v:152909$7626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:153245$7678_Y
+ connect \Y $and$libresoc.v:152909$7626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:153247$7680
+ cell $and $and$libresoc.v:152911$7628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:153247$7680_Y
+ connect \Y $and$libresoc.v:152911$7628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:153248$7681
+ cell $and $and$libresoc.v:152912$7629
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:153248$7681_Y
+ connect \Y $and$libresoc.v:152912$7629_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:153250$7683
+ cell $and $and$libresoc.v:152914$7631
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$92
connect \B { 1'1 \$94 1'1 }
- connect \Y $and$libresoc.v:153250$7683_Y
+ connect \Y $and$libresoc.v:152914$7631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:153221$7654
+ cell $eq $eq$libresoc.v:152885$7602
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:153221$7654_Y
+ connect \Y $eq$libresoc.v:152885$7602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:153223$7656
+ cell $eq $eq$libresoc.v:152887$7604
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:153223$7656_Y
+ connect \Y $eq$libresoc.v:152887$7604_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:153204$7637
+ cell $not $not$libresoc.v:152868$7585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:153204$7637_Y
+ connect \Y $not$libresoc.v:152868$7585_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:153206$7639
+ cell $not $not$libresoc.v:152870$7587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:153206$7639_Y
+ connect \Y $not$libresoc.v:152870$7587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:153209$7642
+ cell $not $not$libresoc.v:152873$7590
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:153209$7642_Y
+ connect \Y $not$libresoc.v:152873$7590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:153212$7645
+ cell $not $not$libresoc.v:152876$7593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:153212$7645_Y
+ connect \Y $not$libresoc.v:152876$7593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:153218$7651
+ cell $not $not$libresoc.v:152882$7599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_ready_i
- connect \Y $not$libresoc.v:153218$7651_Y
+ connect \Y $not$libresoc.v:152882$7599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:153229$7662
+ cell $not $not$libresoc.v:152893$7610
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:153229$7662_Y
+ connect \Y $not$libresoc.v:152893$7610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:153249$7682
+ cell $not $not$libresoc.v:152913$7630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_mul0_mul_op__imm_data__ok
- connect \Y $not$libresoc.v:153249$7682_Y
+ connect \Y $not$libresoc.v:152913$7630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:153251$7684
+ cell $not $not$libresoc.v:152915$7632
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:153251$7684_Y
+ connect \Y $not$libresoc.v:152915$7632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:153217$7650
+ cell $or $or$libresoc.v:152881$7598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:153217$7650_Y
+ connect \Y $or$libresoc.v:152881$7598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:153227$7660
+ cell $or $or$libresoc.v:152891$7608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:153227$7660_Y
+ connect \Y $or$libresoc.v:152891$7608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:153228$7661
+ cell $or $or$libresoc.v:152892$7609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:153228$7661_Y
+ connect \Y $or$libresoc.v:152892$7609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:153230$7663
+ cell $or $or$libresoc.v:152894$7611
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:153230$7663_Y
+ connect \Y $or$libresoc.v:152894$7611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:153231$7664
+ cell $or $or$libresoc.v:152895$7612
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:153231$7664_Y
+ connect \Y $or$libresoc.v:152895$7612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:153234$7667
+ cell $or $or$libresoc.v:152898$7615
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:153234$7667_Y
+ connect \Y $or$libresoc.v:152898$7615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:153240$7673
+ cell $or $or$libresoc.v:152904$7621
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:153240$7673_Y
+ connect \Y $or$libresoc.v:152904$7621_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:153246$7679
+ cell $reduce_and $reduce_and$libresoc.v:152910$7627
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:153246$7679_Y
+ connect \Y $reduce_and$libresoc.v:152910$7627_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:153211$7644
+ cell $reduce_or $reduce_or$libresoc.v:152875$7592
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:153211$7644_Y
+ connect \Y $reduce_or$libresoc.v:152875$7592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:153215$7648
+ cell $reduce_or $reduce_or$libresoc.v:152879$7596
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:153215$7648_Y
+ connect \Y $reduce_or$libresoc.v:152879$7596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:153216$7649
+ cell $reduce_or $reduce_or$libresoc.v:152880$7597
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:153216$7649_Y
+ connect \Y $reduce_or$libresoc.v:152880$7597_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:153239$7672
+ cell $mux $ternary$libresoc.v:152903$7620
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_mul0_mul_op__imm_data__ok
- connect \Y $ternary$libresoc.v:153239$7672_Y
+ connect \Y $ternary$libresoc.v:152903$7620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:153241$7674
+ cell $mux $ternary$libresoc.v:152905$7622
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_mul0_mul_op__imm_data__data
connect \S \alu_mul0_mul_op__imm_data__ok
- connect \Y $ternary$libresoc.v:153241$7674_Y
+ connect \Y $ternary$libresoc.v:152905$7622_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:153242$7675
+ cell $mux $ternary$libresoc.v:152906$7623
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:153242$7675_Y
+ connect \Y $ternary$libresoc.v:152906$7623_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:153243$7676
+ cell $mux $ternary$libresoc.v:152907$7624
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:153243$7676_Y
+ connect \Y $ternary$libresoc.v:152907$7624_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:153244$7677
+ cell $mux $ternary$libresoc.v:152908$7625
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:153244$7677_Y
+ connect \Y $ternary$libresoc.v:152908$7625_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153328.15-153334.4"
+ attribute \src "libresoc.v:152992.15-152998.4"
cell \alu_l$107 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153335.12-153365.4"
+ attribute \src "libresoc.v:152999.12-153029.4"
cell \alu_mul0 \alu_mul0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153366.16-153372.4"
+ attribute \src "libresoc.v:153030.16-153036.4"
cell \alui_l$106 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153373.15-153379.4"
+ attribute \src "libresoc.v:153037.15-153043.4"
cell \opc_l$102 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153380.15-153386.4"
+ attribute \src "libresoc.v:153044.15-153050.4"
cell \req_l$103 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153387.15-153393.4"
+ attribute \src "libresoc.v:153051.15-153057.4"
cell \rok_l$105 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153394.15-153399.4"
+ attribute \src "libresoc.v:153058.15-153063.4"
cell \rst_l$104 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153400.15-153406.4"
+ attribute \src "libresoc.v:153064.15-153070.4"
cell \src_l$101 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:152595.7-152595.20"
- process $proc$libresoc.v:152595$7839
+ attribute \src "libresoc.v:152259.7-152259.20"
+ process $proc$libresoc.v:152259$7787
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:152719.7-152719.24"
- process $proc$libresoc.v:152719$7840
+ attribute \src "libresoc.v:152383.7-152383.24"
+ process $proc$libresoc.v:152383$7788
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:152729.7-152729.26"
- process $proc$libresoc.v:152729$7841
+ attribute \src "libresoc.v:152393.7-152393.26"
+ process $proc$libresoc.v:152393$7789
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:152737.7-152737.25"
- process $proc$libresoc.v:152737$7842
+ attribute \src "libresoc.v:152401.7-152401.25"
+ process $proc$libresoc.v:152401$7790
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:152760.14-152760.49"
- process $proc$libresoc.v:152760$7843
+ attribute \src "libresoc.v:152424.14-152424.49"
+ process $proc$libresoc.v:152424$7791
assign { } { }
assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:152764.14-152764.68"
- process $proc$libresoc.v:152764$7844
+ attribute \src "libresoc.v:152428.14-152428.68"
+ process $proc$libresoc.v:152428$7792
assign { } { }
assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:152768.7-152768.43"
- process $proc$libresoc.v:152768$7845
+ attribute \src "libresoc.v:152432.7-152432.43"
+ process $proc$libresoc.v:152432$7793
assign { } { }
assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:152772.14-152772.43"
- process $proc$libresoc.v:152772$7846
+ attribute \src "libresoc.v:152436.14-152436.43"
+ process $proc$libresoc.v:152436$7794
assign { } { }
assign $1\alu_mul0_mul_op__insn[31:0] 0
sync always
sync init
update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0]
end
- attribute \src "libresoc.v:152851.13-152851.47"
- process $proc$libresoc.v:152851$7847
+ attribute \src "libresoc.v:152515.13-152515.47"
+ process $proc$libresoc.v:152515$7795
assign { } { }
assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:152855.7-152855.39"
- process $proc$libresoc.v:152855$7848
+ attribute \src "libresoc.v:152519.7-152519.39"
+ process $proc$libresoc.v:152519$7796
assign { } { }
assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:152859.7-152859.40"
- process $proc$libresoc.v:152859$7849
+ attribute \src "libresoc.v:152523.7-152523.40"
+ process $proc$libresoc.v:152523$7797
assign { } { }
assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:152863.7-152863.37"
- process $proc$libresoc.v:152863$7850
+ attribute \src "libresoc.v:152527.7-152527.37"
+ process $proc$libresoc.v:152527$7798
assign { } { }
assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:152867.7-152867.37"
- process $proc$libresoc.v:152867$7851
+ attribute \src "libresoc.v:152531.7-152531.37"
+ process $proc$libresoc.v:152531$7799
assign { } { }
assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:152871.7-152871.37"
- process $proc$libresoc.v:152871$7852
+ attribute \src "libresoc.v:152535.7-152535.37"
+ process $proc$libresoc.v:152535$7800
assign { } { }
assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:152875.7-152875.37"
- process $proc$libresoc.v:152875$7853
+ attribute \src "libresoc.v:152539.7-152539.37"
+ process $proc$libresoc.v:152539$7801
assign { } { }
assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:152879.7-152879.40"
- process $proc$libresoc.v:152879$7854
+ attribute \src "libresoc.v:152543.7-152543.40"
+ process $proc$libresoc.v:152543$7802
assign { } { }
assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:152909.7-152909.27"
- process $proc$libresoc.v:152909$7855
+ attribute \src "libresoc.v:152573.7-152573.27"
+ process $proc$libresoc.v:152573$7803
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:152943.14-152943.47"
- process $proc$libresoc.v:152943$7856
+ attribute \src "libresoc.v:152607.14-152607.47"
+ process $proc$libresoc.v:152607$7804
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:152947.7-152947.27"
- process $proc$libresoc.v:152947$7857
+ attribute \src "libresoc.v:152611.7-152611.27"
+ process $proc$libresoc.v:152611$7805
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:152951.13-152951.33"
- process $proc$libresoc.v:152951$7858
+ attribute \src "libresoc.v:152615.13-152615.33"
+ process $proc$libresoc.v:152615$7806
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:152955.7-152955.30"
- process $proc$libresoc.v:152955$7859
+ attribute \src "libresoc.v:152619.7-152619.30"
+ process $proc$libresoc.v:152619$7807
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:152959.13-152959.35"
- process $proc$libresoc.v:152959$7860
+ attribute \src "libresoc.v:152623.13-152623.35"
+ process $proc$libresoc.v:152623$7808
assign { } { }
assign $1\data_r2__xer_ov[1:0] 2'00
sync always
sync init
update \data_r2__xer_ov $1\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:152963.7-152963.32"
- process $proc$libresoc.v:152963$7861
+ attribute \src "libresoc.v:152627.7-152627.32"
+ process $proc$libresoc.v:152627$7809
assign { } { }
assign $1\data_r2__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:152967.7-152967.29"
- process $proc$libresoc.v:152967$7862
+ attribute \src "libresoc.v:152631.7-152631.29"
+ process $proc$libresoc.v:152631$7810
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:152971.7-152971.32"
- process $proc$libresoc.v:152971$7863
+ attribute \src "libresoc.v:152635.7-152635.32"
+ process $proc$libresoc.v:152635$7811
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:152991.7-152991.25"
- process $proc$libresoc.v:152991$7864
+ attribute \src "libresoc.v:152655.7-152655.25"
+ process $proc$libresoc.v:152655$7812
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:152995.7-152995.25"
- process $proc$libresoc.v:152995$7865
+ attribute \src "libresoc.v:152659.7-152659.25"
+ process $proc$libresoc.v:152659$7813
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:153113.13-153113.30"
- process $proc$libresoc.v:153113$7866
+ attribute \src "libresoc.v:152777.13-152777.30"
+ process $proc$libresoc.v:152777$7814
assign { } { }
assign $1\prev_wr_go[3:0] 4'0000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:153121.13-153121.31"
- process $proc$libresoc.v:153121$7867
+ attribute \src "libresoc.v:152785.13-152785.31"
+ process $proc$libresoc.v:152785$7815
assign { } { }
assign $1\req_l_r_req[3:0] 4'1111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:153125.13-153125.31"
- process $proc$libresoc.v:153125$7868
+ attribute \src "libresoc.v:152789.13-152789.31"
+ process $proc$libresoc.v:152789$7816
assign { } { }
assign $1\req_l_s_req[3:0] 4'0000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:153137.7-153137.26"
- process $proc$libresoc.v:153137$7869
+ attribute \src "libresoc.v:152801.7-152801.26"
+ process $proc$libresoc.v:152801$7817
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:153141.7-153141.26"
- process $proc$libresoc.v:153141$7870
+ attribute \src "libresoc.v:152805.7-152805.26"
+ process $proc$libresoc.v:152805$7818
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:153145.7-153145.25"
- process $proc$libresoc.v:153145$7871
+ attribute \src "libresoc.v:152809.7-152809.25"
+ process $proc$libresoc.v:152809$7819
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:153149.7-153149.25"
- process $proc$libresoc.v:153149$7872
+ attribute \src "libresoc.v:152813.7-152813.25"
+ process $proc$libresoc.v:152813$7820
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:153163.13-153163.31"
- process $proc$libresoc.v:153163$7873
+ attribute \src "libresoc.v:152827.13-152827.31"
+ process $proc$libresoc.v:152827$7821
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:153167.13-153167.31"
- process $proc$libresoc.v:153167$7874
+ attribute \src "libresoc.v:152831.13-152831.31"
+ process $proc$libresoc.v:152831$7822
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:153173.14-153173.43"
- process $proc$libresoc.v:153173$7875
+ attribute \src "libresoc.v:152837.14-152837.43"
+ process $proc$libresoc.v:152837$7823
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:153177.14-153177.43"
- process $proc$libresoc.v:153177$7876
+ attribute \src "libresoc.v:152841.14-152841.43"
+ process $proc$libresoc.v:152841$7824
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:153181.7-153181.20"
- process $proc$libresoc.v:153181$7877
+ attribute \src "libresoc.v:152845.7-152845.20"
+ process $proc$libresoc.v:152845$7825
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:153252.3-153253.39"
- process $proc$libresoc.v:153252$7685
+ attribute \src "libresoc.v:152916.3-152917.39"
+ process $proc$libresoc.v:152916$7633
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:153254.3-153255.43"
- process $proc$libresoc.v:153254$7686
+ attribute \src "libresoc.v:152918.3-152919.43"
+ process $proc$libresoc.v:152918$7634
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:153256.3-153257.29"
- process $proc$libresoc.v:153256$7687
+ attribute \src "libresoc.v:152920.3-152921.29"
+ process $proc$libresoc.v:152920$7635
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:153258.3-153259.29"
- process $proc$libresoc.v:153258$7688
+ attribute \src "libresoc.v:152922.3-152923.29"
+ process $proc$libresoc.v:152922$7636
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:153260.3-153261.29"
- process $proc$libresoc.v:153260$7689
+ attribute \src "libresoc.v:152924.3-152925.29"
+ process $proc$libresoc.v:152924$7637
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:153262.3-153263.47"
- process $proc$libresoc.v:153262$7690
+ attribute \src "libresoc.v:152926.3-152927.47"
+ process $proc$libresoc.v:152926$7638
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:153264.3-153265.53"
- process $proc$libresoc.v:153264$7691
+ attribute \src "libresoc.v:152928.3-152929.53"
+ process $proc$libresoc.v:152928$7639
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:153266.3-153267.47"
- process $proc$libresoc.v:153266$7692
+ attribute \src "libresoc.v:152930.3-152931.47"
+ process $proc$libresoc.v:152930$7640
assign { } { }
assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next
sync posedge \coresync_clk
update \data_r2__xer_ov $0\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:153268.3-153269.53"
- process $proc$libresoc.v:153268$7693
+ attribute \src "libresoc.v:152932.3-152933.53"
+ process $proc$libresoc.v:152932$7641
assign { } { }
assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:153270.3-153271.43"
- process $proc$libresoc.v:153270$7694
+ attribute \src "libresoc.v:152934.3-152935.43"
+ process $proc$libresoc.v:152934$7642
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:153272.3-153273.49"
- process $proc$libresoc.v:153272$7695
+ attribute \src "libresoc.v:152936.3-152937.49"
+ process $proc$libresoc.v:152936$7643
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:153274.3-153275.37"
- process $proc$libresoc.v:153274$7696
+ attribute \src "libresoc.v:152938.3-152939.37"
+ process $proc$libresoc.v:152938$7644
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:153276.3-153277.43"
- process $proc$libresoc.v:153276$7697
+ attribute \src "libresoc.v:152940.3-152941.43"
+ process $proc$libresoc.v:152940$7645
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:153278.3-153279.69"
- process $proc$libresoc.v:153278$7698
+ attribute \src "libresoc.v:152942.3-152943.69"
+ process $proc$libresoc.v:152942$7646
assign { } { }
assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:153280.3-153281.65"
- process $proc$libresoc.v:153280$7699
+ attribute \src "libresoc.v:152944.3-152945.65"
+ process $proc$libresoc.v:152944$7647
assign { } { }
assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:153282.3-153283.79"
- process $proc$libresoc.v:153282$7700
+ attribute \src "libresoc.v:152946.3-152947.79"
+ process $proc$libresoc.v:152946$7648
assign { } { }
assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:153284.3-153285.75"
- process $proc$libresoc.v:153284$7701
+ attribute \src "libresoc.v:152948.3-152949.75"
+ process $proc$libresoc.v:152948$7649
assign { } { }
assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:153286.3-153287.63"
- process $proc$libresoc.v:153286$7702
+ attribute \src "libresoc.v:152950.3-152951.63"
+ process $proc$libresoc.v:152950$7650
assign { } { }
assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:153288.3-153289.63"
- process $proc$libresoc.v:153288$7703
+ attribute \src "libresoc.v:152952.3-152953.63"
+ process $proc$libresoc.v:152952$7651
assign { } { }
assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:153290.3-153291.63"
- process $proc$libresoc.v:153290$7704
+ attribute \src "libresoc.v:152954.3-152955.63"
+ process $proc$libresoc.v:152954$7652
assign { } { }
assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:153292.3-153293.63"
- process $proc$libresoc.v:153292$7705
+ attribute \src "libresoc.v:152956.3-152957.63"
+ process $proc$libresoc.v:152956$7653
assign { } { }
assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:153294.3-153295.69"
- process $proc$libresoc.v:153294$7706
+ attribute \src "libresoc.v:152958.3-152959.69"
+ process $proc$libresoc.v:152958$7654
assign { } { }
assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:153296.3-153297.67"
- process $proc$libresoc.v:153296$7707
+ attribute \src "libresoc.v:152960.3-152961.67"
+ process $proc$libresoc.v:152960$7655
assign { } { }
assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:153298.3-153299.69"
- process $proc$libresoc.v:153298$7708
+ attribute \src "libresoc.v:152962.3-152963.69"
+ process $proc$libresoc.v:152962$7656
assign { } { }
assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:153300.3-153301.59"
- process $proc$libresoc.v:153300$7709
+ attribute \src "libresoc.v:152964.3-152965.59"
+ process $proc$libresoc.v:152964$7657
assign { } { }
assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0]
end
- attribute \src "libresoc.v:153302.3-153303.39"
- process $proc$libresoc.v:153302$7710
+ attribute \src "libresoc.v:152966.3-152967.39"
+ process $proc$libresoc.v:152966$7658
assign { } { }
assign $0\req_l_r_req[3:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:153304.3-153305.39"
- process $proc$libresoc.v:153304$7711
+ attribute \src "libresoc.v:152968.3-152969.39"
+ process $proc$libresoc.v:152968$7659
assign { } { }
assign $0\req_l_s_req[3:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:153306.3-153307.39"
- process $proc$libresoc.v:153306$7712
+ attribute \src "libresoc.v:152970.3-152971.39"
+ process $proc$libresoc.v:152970$7660
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:153308.3-153309.39"
- process $proc$libresoc.v:153308$7713
+ attribute \src "libresoc.v:152972.3-152973.39"
+ process $proc$libresoc.v:152972$7661
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:153310.3-153311.39"
- process $proc$libresoc.v:153310$7714
+ attribute \src "libresoc.v:152974.3-152975.39"
+ process $proc$libresoc.v:152974$7662
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:153312.3-153313.39"
- process $proc$libresoc.v:153312$7715
+ attribute \src "libresoc.v:152976.3-152977.39"
+ process $proc$libresoc.v:152976$7663
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:153314.3-153315.39"
- process $proc$libresoc.v:153314$7716
+ attribute \src "libresoc.v:152978.3-152979.39"
+ process $proc$libresoc.v:152978$7664
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:153316.3-153317.39"
- process $proc$libresoc.v:153316$7717
+ attribute \src "libresoc.v:152980.3-152981.39"
+ process $proc$libresoc.v:152980$7665
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:153318.3-153319.41"
- process $proc$libresoc.v:153318$7718
+ attribute \src "libresoc.v:152982.3-152983.41"
+ process $proc$libresoc.v:152982$7666
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:153320.3-153321.41"
- process $proc$libresoc.v:153320$7719
+ attribute \src "libresoc.v:152984.3-152985.41"
+ process $proc$libresoc.v:152984$7667
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:153322.3-153323.37"
- process $proc$libresoc.v:153322$7720
+ attribute \src "libresoc.v:152986.3-152987.37"
+ process $proc$libresoc.v:152986$7668
assign { } { }
assign $0\prev_wr_go[3:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:153324.3-153325.40"
- process $proc$libresoc.v:153324$7721
+ attribute \src "libresoc.v:152988.3-152989.40"
+ process $proc$libresoc.v:152988$7669
assign { } { }
assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:153326.3-153327.25"
- process $proc$libresoc.v:153326$7722
+ attribute \src "libresoc.v:152990.3-152991.25"
+ process $proc$libresoc.v:152990$7670
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:153407.3-153416.6"
- process $proc$libresoc.v:153407$7723
+ attribute \src "libresoc.v:153071.3-153080.6"
+ process $proc$libresoc.v:153071$7671
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:153408.5-153408.29"
+ attribute \src "libresoc.v:153072.5-153072.29"
switch \initial
- attribute \src "libresoc.v:153408.9-153408.17"
+ attribute \src "libresoc.v:153072.9-153072.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:153417.3-153425.6"
- process $proc$libresoc.v:153417$7724
+ attribute \src "libresoc.v:153081.3-153089.6"
+ process $proc$libresoc.v:153081$7672
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$7725 $1\rok_l_s_rdok$next[0:0]$7726
- attribute \src "libresoc.v:153418.5-153418.29"
+ assign $0\rok_l_s_rdok$next[0:0]$7673 $1\rok_l_s_rdok$next[0:0]$7674
+ attribute \src "libresoc.v:153082.5-153082.29"
switch \initial
- attribute \src "libresoc.v:153418.9-153418.17"
+ attribute \src "libresoc.v:153082.9-153082.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$7726 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$7674 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$7726 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$7674 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7725
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7673
end
- attribute \src "libresoc.v:153426.3-153434.6"
- process $proc$libresoc.v:153426$7727
+ attribute \src "libresoc.v:153090.3-153098.6"
+ process $proc$libresoc.v:153090$7675
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$7728 $1\rok_l_r_rdok$next[0:0]$7729
- attribute \src "libresoc.v:153427.5-153427.29"
+ assign $0\rok_l_r_rdok$next[0:0]$7676 $1\rok_l_r_rdok$next[0:0]$7677
+ attribute \src "libresoc.v:153091.5-153091.29"
switch \initial
- attribute \src "libresoc.v:153427.9-153427.17"
+ attribute \src "libresoc.v:153091.9-153091.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$7729 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$7677 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$7729 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$7677 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7728
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7676
end
- attribute \src "libresoc.v:153435.3-153443.6"
- process $proc$libresoc.v:153435$7730
+ attribute \src "libresoc.v:153099.3-153107.6"
+ process $proc$libresoc.v:153099$7678
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$7731 $1\rst_l_s_rst$next[0:0]$7732
- attribute \src "libresoc.v:153436.5-153436.29"
+ assign $0\rst_l_s_rst$next[0:0]$7679 $1\rst_l_s_rst$next[0:0]$7680
+ attribute \src "libresoc.v:153100.5-153100.29"
switch \initial
- attribute \src "libresoc.v:153436.9-153436.17"
+ attribute \src "libresoc.v:153100.9-153100.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$7732 1'0
+ assign $1\rst_l_s_rst$next[0:0]$7680 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$7732 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$7680 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7731
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7679
end
- attribute \src "libresoc.v:153444.3-153452.6"
- process $proc$libresoc.v:153444$7733
+ attribute \src "libresoc.v:153108.3-153116.6"
+ process $proc$libresoc.v:153108$7681
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$7734 $1\rst_l_r_rst$next[0:0]$7735
- attribute \src "libresoc.v:153445.5-153445.29"
+ assign $0\rst_l_r_rst$next[0:0]$7682 $1\rst_l_r_rst$next[0:0]$7683
+ attribute \src "libresoc.v:153109.5-153109.29"
switch \initial
- attribute \src "libresoc.v:153445.9-153445.17"
+ attribute \src "libresoc.v:153109.9-153109.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$7735 1'1
+ assign $1\rst_l_r_rst$next[0:0]$7683 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$7735 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$7683 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7734
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7682
end
- attribute \src "libresoc.v:153453.3-153461.6"
- process $proc$libresoc.v:153453$7736
+ attribute \src "libresoc.v:153117.3-153125.6"
+ process $proc$libresoc.v:153117$7684
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$7737 $1\opc_l_s_opc$next[0:0]$7738
- attribute \src "libresoc.v:153454.5-153454.29"
+ assign $0\opc_l_s_opc$next[0:0]$7685 $1\opc_l_s_opc$next[0:0]$7686
+ attribute \src "libresoc.v:153118.5-153118.29"
switch \initial
- attribute \src "libresoc.v:153454.9-153454.17"
+ attribute \src "libresoc.v:153118.9-153118.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$7738 1'0
+ assign $1\opc_l_s_opc$next[0:0]$7686 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$7738 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$7686 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7737
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7685
end
- attribute \src "libresoc.v:153462.3-153470.6"
- process $proc$libresoc.v:153462$7739
+ attribute \src "libresoc.v:153126.3-153134.6"
+ process $proc$libresoc.v:153126$7687
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$7740 $1\opc_l_r_opc$next[0:0]$7741
- attribute \src "libresoc.v:153463.5-153463.29"
+ assign $0\opc_l_r_opc$next[0:0]$7688 $1\opc_l_r_opc$next[0:0]$7689
+ attribute \src "libresoc.v:153127.5-153127.29"
switch \initial
- attribute \src "libresoc.v:153463.9-153463.17"
+ attribute \src "libresoc.v:153127.9-153127.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$7741 1'1
+ assign $1\opc_l_r_opc$next[0:0]$7689 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$7741 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$7689 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7740
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7688
end
- attribute \src "libresoc.v:153471.3-153479.6"
- process $proc$libresoc.v:153471$7742
+ attribute \src "libresoc.v:153135.3-153143.6"
+ process $proc$libresoc.v:153135$7690
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$7743 $1\src_l_s_src$next[2:0]$7744
- attribute \src "libresoc.v:153472.5-153472.29"
+ assign $0\src_l_s_src$next[2:0]$7691 $1\src_l_s_src$next[2:0]$7692
+ attribute \src "libresoc.v:153136.5-153136.29"
switch \initial
- attribute \src "libresoc.v:153472.9-153472.17"
+ attribute \src "libresoc.v:153136.9-153136.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$7744 3'000
+ assign $1\src_l_s_src$next[2:0]$7692 3'000
case
- assign $1\src_l_s_src$next[2:0]$7744 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$7692 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7743
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7691
end
- attribute \src "libresoc.v:153480.3-153488.6"
- process $proc$libresoc.v:153480$7745
+ attribute \src "libresoc.v:153144.3-153152.6"
+ process $proc$libresoc.v:153144$7693
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$7746 $1\src_l_r_src$next[2:0]$7747
- attribute \src "libresoc.v:153481.5-153481.29"
+ assign $0\src_l_r_src$next[2:0]$7694 $1\src_l_r_src$next[2:0]$7695
+ attribute \src "libresoc.v:153145.5-153145.29"
switch \initial
- attribute \src "libresoc.v:153481.9-153481.17"
+ attribute \src "libresoc.v:153145.9-153145.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$7747 3'111
+ assign $1\src_l_r_src$next[2:0]$7695 3'111
case
- assign $1\src_l_r_src$next[2:0]$7747 \reset_r
+ assign $1\src_l_r_src$next[2:0]$7695 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7746
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7694
end
- attribute \src "libresoc.v:153489.3-153497.6"
- process $proc$libresoc.v:153489$7748
+ attribute \src "libresoc.v:153153.3-153161.6"
+ process $proc$libresoc.v:153153$7696
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[3:0]$7749 $1\req_l_s_req$next[3:0]$7750
- attribute \src "libresoc.v:153490.5-153490.29"
+ assign $0\req_l_s_req$next[3:0]$7697 $1\req_l_s_req$next[3:0]$7698
+ attribute \src "libresoc.v:153154.5-153154.29"
switch \initial
- attribute \src "libresoc.v:153490.9-153490.17"
+ attribute \src "libresoc.v:153154.9-153154.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[3:0]$7750 4'0000
+ assign $1\req_l_s_req$next[3:0]$7698 4'0000
case
- assign $1\req_l_s_req$next[3:0]$7750 \$66
+ assign $1\req_l_s_req$next[3:0]$7698 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7749
+ update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7697
end
- attribute \src "libresoc.v:153498.3-153506.6"
- process $proc$libresoc.v:153498$7751
+ attribute \src "libresoc.v:153162.3-153170.6"
+ process $proc$libresoc.v:153162$7699
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[3:0]$7752 $1\req_l_r_req$next[3:0]$7753
- attribute \src "libresoc.v:153499.5-153499.29"
+ assign $0\req_l_r_req$next[3:0]$7700 $1\req_l_r_req$next[3:0]$7701
+ attribute \src "libresoc.v:153163.5-153163.29"
switch \initial
- attribute \src "libresoc.v:153499.9-153499.17"
+ attribute \src "libresoc.v:153163.9-153163.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[3:0]$7753 4'1111
+ assign $1\req_l_r_req$next[3:0]$7701 4'1111
case
- assign $1\req_l_r_req$next[3:0]$7753 \$68
+ assign $1\req_l_r_req$next[3:0]$7701 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7752
+ update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7700
end
- attribute \src "libresoc.v:153507.3-153539.6"
- process $proc$libresoc.v:153507$7754
+ attribute \src "libresoc.v:153171.3-153203.6"
+ process $proc$libresoc.v:153171$7702
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767
+ assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__insn$next[31:0]$7758 $1\alu_mul0_mul_op__insn$next[31:0]$7770
- assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7759 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771
- assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772
- assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7761 $1\alu_mul0_mul_op__is_signed$next[0:0]$7773
+ assign $0\alu_mul0_mul_op__insn$next[31:0]$7706 $1\alu_mul0_mul_op__insn$next[31:0]$7718
+ assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719
+ assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720
+ assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778
- assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779
- assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780
- assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781
- assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782
- assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783
- assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784
- attribute \src "libresoc.v:153508.5-153508.29"
+ assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726
+ assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727
+ assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728
+ assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729
+ assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730
+ assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731
+ assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732
+ attribute \src "libresoc.v:153172.5-153172.29"
switch \initial
- attribute \src "libresoc.v:153508.9-153508.17"
+ attribute \src "libresoc.v:153172.9-153172.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_mul0_mul_op__insn$next[31:0]$7770 $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
+ assign { $1\alu_mul0_mul_op__insn$next[31:0]$7718 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
case
- assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 \alu_mul0_mul_op__fn_unit
- assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 \alu_mul0_mul_op__imm_data__data
- assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 \alu_mul0_mul_op__imm_data__ok
- assign $1\alu_mul0_mul_op__insn$next[31:0]$7770 \alu_mul0_mul_op__insn
- assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 \alu_mul0_mul_op__insn_type
- assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 \alu_mul0_mul_op__is_32bit
- assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 \alu_mul0_mul_op__is_signed
- assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 \alu_mul0_mul_op__oe__oe
- assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 \alu_mul0_mul_op__oe__ok
- assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 \alu_mul0_mul_op__rc__ok
- assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 \alu_mul0_mul_op__rc__rc
- assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 \alu_mul0_mul_op__write_cr0
+ assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 \alu_mul0_mul_op__fn_unit
+ assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 \alu_mul0_mul_op__imm_data__data
+ assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 \alu_mul0_mul_op__imm_data__ok
+ assign $1\alu_mul0_mul_op__insn$next[31:0]$7718 \alu_mul0_mul_op__insn
+ assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 \alu_mul0_mul_op__insn_type
+ assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 \alu_mul0_mul_op__is_32bit
+ assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 \alu_mul0_mul_op__is_signed
+ assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 \alu_mul0_mul_op__oe__oe
+ assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 \alu_mul0_mul_op__oe__ok
+ assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 \alu_mul0_mul_op__rc__ok
+ assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 \alu_mul0_mul_op__rc__rc
+ assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 \alu_mul0_mul_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 1'0
- assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 1'0
- assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 1'0
- assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 1'0
- assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 1'0
+ assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 1'0
+ assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 1'0
+ assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 1'0
+ assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 1'0
+ assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 1'0
case
- assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768
- assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769
- assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774
- assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775
- assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776
- assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777
+ assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716
+ assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717
+ assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722
+ assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723
+ assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724
+ assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725
end
sync always
- update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755
- update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756
- update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757
- update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7758
- update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7759
- update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760
- update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7761
- update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762
- update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763
- update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764
- update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765
- update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766
+ update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703
+ update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704
+ update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705
+ update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7706
+ update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7707
+ update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708
+ update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7709
+ update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710
+ update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711
+ update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712
+ update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713
+ update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714
end
- attribute \src "libresoc.v:153540.3-153561.6"
- process $proc$libresoc.v:153540$7785
+ attribute \src "libresoc.v:153204.3-153225.6"
+ process $proc$libresoc.v:153204$7733
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$7786 $2\data_r0__o$next[63:0]$7790
+ assign $0\data_r0__o$next[63:0]$7734 $2\data_r0__o$next[63:0]$7738
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$7787 $3\data_r0__o_ok$next[0:0]$7792
- attribute \src "libresoc.v:153541.5-153541.29"
+ assign $0\data_r0__o_ok$next[0:0]$7735 $3\data_r0__o_ok$next[0:0]$7740
+ attribute \src "libresoc.v:153205.5-153205.29"
switch \initial
- attribute \src "libresoc.v:153541.9-153541.17"
+ attribute \src "libresoc.v:153205.9-153205.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$7789 $1\data_r0__o$next[63:0]$7788 } { \o_ok \alu_mul0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$7737 $1\data_r0__o$next[63:0]$7736 } { \o_ok \alu_mul0_o }
case
- assign $1\data_r0__o$next[63:0]$7788 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$7789 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$7736 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$7737 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$7791 $2\data_r0__o$next[63:0]$7790 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$7739 $2\data_r0__o$next[63:0]$7738 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$7790 $1\data_r0__o$next[63:0]$7788
- assign $2\data_r0__o_ok$next[0:0]$7791 $1\data_r0__o_ok$next[0:0]$7789
+ assign $2\data_r0__o$next[63:0]$7738 $1\data_r0__o$next[63:0]$7736
+ assign $2\data_r0__o_ok$next[0:0]$7739 $1\data_r0__o_ok$next[0:0]$7737
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$7792 1'0
+ assign $3\data_r0__o_ok$next[0:0]$7740 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$7792 $2\data_r0__o_ok$next[0:0]$7791
+ assign $3\data_r0__o_ok$next[0:0]$7740 $2\data_r0__o_ok$next[0:0]$7739
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$7786
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7787
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$7734
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7735
end
- attribute \src "libresoc.v:153562.3-153583.6"
- process $proc$libresoc.v:153562$7793
+ attribute \src "libresoc.v:153226.3-153247.6"
+ process $proc$libresoc.v:153226$7741
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$7794 $2\data_r1__cr_a$next[3:0]$7798
+ assign $0\data_r1__cr_a$next[3:0]$7742 $2\data_r1__cr_a$next[3:0]$7746
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$7795 $3\data_r1__cr_a_ok$next[0:0]$7800
- attribute \src "libresoc.v:153563.5-153563.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$7743 $3\data_r1__cr_a_ok$next[0:0]$7748
+ attribute \src "libresoc.v:153227.5-153227.29"
switch \initial
- attribute \src "libresoc.v:153563.9-153563.17"
+ attribute \src "libresoc.v:153227.9-153227.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$7797 $1\data_r1__cr_a$next[3:0]$7796 } { \cr_a_ok \alu_mul0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$7745 $1\data_r1__cr_a$next[3:0]$7744 } { \cr_a_ok \alu_mul0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$7796 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$7797 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$7744 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$7745 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$7799 $2\data_r1__cr_a$next[3:0]$7798 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$7747 $2\data_r1__cr_a$next[3:0]$7746 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$7798 $1\data_r1__cr_a$next[3:0]$7796
- assign $2\data_r1__cr_a_ok$next[0:0]$7799 $1\data_r1__cr_a_ok$next[0:0]$7797
+ assign $2\data_r1__cr_a$next[3:0]$7746 $1\data_r1__cr_a$next[3:0]$7744
+ assign $2\data_r1__cr_a_ok$next[0:0]$7747 $1\data_r1__cr_a_ok$next[0:0]$7745
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$7800 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$7748 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$7800 $2\data_r1__cr_a_ok$next[0:0]$7799
+ assign $3\data_r1__cr_a_ok$next[0:0]$7748 $2\data_r1__cr_a_ok$next[0:0]$7747
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7794
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7795
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7742
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7743
end
- attribute \src "libresoc.v:153584.3-153605.6"
- process $proc$libresoc.v:153584$7801
+ attribute \src "libresoc.v:153248.3-153269.6"
+ process $proc$libresoc.v:153248$7749
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ov$next[1:0]$7802 $2\data_r2__xer_ov$next[1:0]$7806
+ assign $0\data_r2__xer_ov$next[1:0]$7750 $2\data_r2__xer_ov$next[1:0]$7754
assign { } { }
- assign $0\data_r2__xer_ov_ok$next[0:0]$7803 $3\data_r2__xer_ov_ok$next[0:0]$7808
- attribute \src "libresoc.v:153585.5-153585.29"
+ assign $0\data_r2__xer_ov_ok$next[0:0]$7751 $3\data_r2__xer_ov_ok$next[0:0]$7756
+ attribute \src "libresoc.v:153249.5-153249.29"
switch \initial
- attribute \src "libresoc.v:153585.9-153585.17"
+ attribute \src "libresoc.v:153249.9-153249.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ov_ok$next[0:0]$7805 $1\data_r2__xer_ov$next[1:0]$7804 } { \xer_ov_ok \alu_mul0_xer_ov }
+ assign { $1\data_r2__xer_ov_ok$next[0:0]$7753 $1\data_r2__xer_ov$next[1:0]$7752 } { \xer_ov_ok \alu_mul0_xer_ov }
case
- assign $1\data_r2__xer_ov$next[1:0]$7804 \data_r2__xer_ov
- assign $1\data_r2__xer_ov_ok$next[0:0]$7805 \data_r2__xer_ov_ok
+ assign $1\data_r2__xer_ov$next[1:0]$7752 \data_r2__xer_ov
+ assign $1\data_r2__xer_ov_ok$next[0:0]$7753 \data_r2__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ov_ok$next[0:0]$7807 $2\data_r2__xer_ov$next[1:0]$7806 } 3'000
+ assign { $2\data_r2__xer_ov_ok$next[0:0]$7755 $2\data_r2__xer_ov$next[1:0]$7754 } 3'000
case
- assign $2\data_r2__xer_ov$next[1:0]$7806 $1\data_r2__xer_ov$next[1:0]$7804
- assign $2\data_r2__xer_ov_ok$next[0:0]$7807 $1\data_r2__xer_ov_ok$next[0:0]$7805
+ assign $2\data_r2__xer_ov$next[1:0]$7754 $1\data_r2__xer_ov$next[1:0]$7752
+ assign $2\data_r2__xer_ov_ok$next[0:0]$7755 $1\data_r2__xer_ov_ok$next[0:0]$7753
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ov_ok$next[0:0]$7808 1'0
+ assign $3\data_r2__xer_ov_ok$next[0:0]$7756 1'0
case
- assign $3\data_r2__xer_ov_ok$next[0:0]$7808 $2\data_r2__xer_ov_ok$next[0:0]$7807
+ assign $3\data_r2__xer_ov_ok$next[0:0]$7756 $2\data_r2__xer_ov_ok$next[0:0]$7755
end
sync always
- update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7802
- update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7803
+ update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7750
+ update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7751
end
- attribute \src "libresoc.v:153606.3-153627.6"
- process $proc$libresoc.v:153606$7809
+ attribute \src "libresoc.v:153270.3-153291.6"
+ process $proc$libresoc.v:153270$7757
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$7810 $2\data_r3__xer_so$next[0:0]$7814
+ assign $0\data_r3__xer_so$next[0:0]$7758 $2\data_r3__xer_so$next[0:0]$7762
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$7811 $3\data_r3__xer_so_ok$next[0:0]$7816
- attribute \src "libresoc.v:153607.5-153607.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$7759 $3\data_r3__xer_so_ok$next[0:0]$7764
+ attribute \src "libresoc.v:153271.5-153271.29"
switch \initial
- attribute \src "libresoc.v:153607.9-153607.17"
+ attribute \src "libresoc.v:153271.9-153271.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$7813 $1\data_r3__xer_so$next[0:0]$7812 } { \xer_so_ok \alu_mul0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$7761 $1\data_r3__xer_so$next[0:0]$7760 } { \xer_so_ok \alu_mul0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$7812 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$7813 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$7760 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$7761 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$7815 $2\data_r3__xer_so$next[0:0]$7814 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$7763 $2\data_r3__xer_so$next[0:0]$7762 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$7814 $1\data_r3__xer_so$next[0:0]$7812
- assign $2\data_r3__xer_so_ok$next[0:0]$7815 $1\data_r3__xer_so_ok$next[0:0]$7813
+ assign $2\data_r3__xer_so$next[0:0]$7762 $1\data_r3__xer_so$next[0:0]$7760
+ assign $2\data_r3__xer_so_ok$next[0:0]$7763 $1\data_r3__xer_so_ok$next[0:0]$7761
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$7816 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$7764 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$7816 $2\data_r3__xer_so_ok$next[0:0]$7815
+ assign $3\data_r3__xer_so_ok$next[0:0]$7764 $2\data_r3__xer_so_ok$next[0:0]$7763
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7810
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7811
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7758
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7759
end
- attribute \src "libresoc.v:153628.3-153637.6"
- process $proc$libresoc.v:153628$7817
+ attribute \src "libresoc.v:153292.3-153301.6"
+ process $proc$libresoc.v:153292$7765
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$7818 $1\src_r0$next[63:0]$7819
- attribute \src "libresoc.v:153629.5-153629.29"
+ assign $0\src_r0$next[63:0]$7766 $1\src_r0$next[63:0]$7767
+ attribute \src "libresoc.v:153293.5-153293.29"
switch \initial
- attribute \src "libresoc.v:153629.9-153629.17"
+ attribute \src "libresoc.v:153293.9-153293.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$7819 \src1_i
+ assign $1\src_r0$next[63:0]$7767 \src1_i
case
- assign $1\src_r0$next[63:0]$7819 \src_r0
+ assign $1\src_r0$next[63:0]$7767 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$7818
+ update \src_r0$next $0\src_r0$next[63:0]$7766
end
- attribute \src "libresoc.v:153638.3-153647.6"
- process $proc$libresoc.v:153638$7820
+ attribute \src "libresoc.v:153302.3-153311.6"
+ process $proc$libresoc.v:153302$7768
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$7821 $1\src_r1$next[63:0]$7822
- attribute \src "libresoc.v:153639.5-153639.29"
+ assign $0\src_r1$next[63:0]$7769 $1\src_r1$next[63:0]$7770
+ attribute \src "libresoc.v:153303.5-153303.29"
switch \initial
- attribute \src "libresoc.v:153639.9-153639.17"
+ attribute \src "libresoc.v:153303.9-153303.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$7822 \src_or_imm
+ assign $1\src_r1$next[63:0]$7770 \src_or_imm
case
- assign $1\src_r1$next[63:0]$7822 \src_r1
+ assign $1\src_r1$next[63:0]$7770 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$7821
+ update \src_r1$next $0\src_r1$next[63:0]$7769
end
- attribute \src "libresoc.v:153648.3-153657.6"
- process $proc$libresoc.v:153648$7823
+ attribute \src "libresoc.v:153312.3-153321.6"
+ process $proc$libresoc.v:153312$7771
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$7824 $1\src_r2$next[0:0]$7825
- attribute \src "libresoc.v:153649.5-153649.29"
+ assign $0\src_r2$next[0:0]$7772 $1\src_r2$next[0:0]$7773
+ attribute \src "libresoc.v:153313.5-153313.29"
switch \initial
- attribute \src "libresoc.v:153649.9-153649.17"
+ attribute \src "libresoc.v:153313.9-153313.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$7825 \src3_i
+ assign $1\src_r2$next[0:0]$7773 \src3_i
case
- assign $1\src_r2$next[0:0]$7825 \src_r2
+ assign $1\src_r2$next[0:0]$7773 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$7824
+ update \src_r2$next $0\src_r2$next[0:0]$7772
end
- attribute \src "libresoc.v:153658.3-153666.6"
- process $proc$libresoc.v:153658$7826
+ attribute \src "libresoc.v:153322.3-153330.6"
+ process $proc$libresoc.v:153322$7774
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$7827 $1\alui_l_r_alui$next[0:0]$7828
- attribute \src "libresoc.v:153659.5-153659.29"
+ assign $0\alui_l_r_alui$next[0:0]$7775 $1\alui_l_r_alui$next[0:0]$7776
+ attribute \src "libresoc.v:153323.5-153323.29"
switch \initial
- attribute \src "libresoc.v:153659.9-153659.17"
+ attribute \src "libresoc.v:153323.9-153323.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$7828 1'1
+ assign $1\alui_l_r_alui$next[0:0]$7776 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$7828 \$88
+ assign $1\alui_l_r_alui$next[0:0]$7776 \$88
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7827
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7775
end
- attribute \src "libresoc.v:153667.3-153675.6"
- process $proc$libresoc.v:153667$7829
+ attribute \src "libresoc.v:153331.3-153339.6"
+ process $proc$libresoc.v:153331$7777
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$7830 $1\alu_l_r_alu$next[0:0]$7831
- attribute \src "libresoc.v:153668.5-153668.29"
+ assign $0\alu_l_r_alu$next[0:0]$7778 $1\alu_l_r_alu$next[0:0]$7779
+ attribute \src "libresoc.v:153332.5-153332.29"
switch \initial
- attribute \src "libresoc.v:153668.9-153668.17"
+ attribute \src "libresoc.v:153332.9-153332.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$7831 1'1
+ assign $1\alu_l_r_alu$next[0:0]$7779 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$7831 \$90
+ assign $1\alu_l_r_alu$next[0:0]$7779 \$90
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7830
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7778
end
- attribute \src "libresoc.v:153676.3-153685.6"
- process $proc$libresoc.v:153676$7832
+ attribute \src "libresoc.v:153340.3-153349.6"
+ process $proc$libresoc.v:153340$7780
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:153677.5-153677.29"
+ attribute \src "libresoc.v:153341.5-153341.29"
switch \initial
- attribute \src "libresoc.v:153677.9-153677.17"
+ attribute \src "libresoc.v:153341.9-153341.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:153686.3-153695.6"
- process $proc$libresoc.v:153686$7833
+ attribute \src "libresoc.v:153350.3-153359.6"
+ process $proc$libresoc.v:153350$7781
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:153687.5-153687.29"
+ attribute \src "libresoc.v:153351.5-153351.29"
switch \initial
- attribute \src "libresoc.v:153687.9-153687.17"
+ attribute \src "libresoc.v:153351.9-153351.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:153696.3-153705.6"
- process $proc$libresoc.v:153696$7834
+ attribute \src "libresoc.v:153360.3-153369.6"
+ process $proc$libresoc.v:153360$7782
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:153697.5-153697.29"
+ attribute \src "libresoc.v:153361.5-153361.29"
switch \initial
- attribute \src "libresoc.v:153697.9-153697.17"
+ attribute \src "libresoc.v:153361.9-153361.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:153706.3-153715.6"
- process $proc$libresoc.v:153706$7835
+ attribute \src "libresoc.v:153370.3-153379.6"
+ process $proc$libresoc.v:153370$7783
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:153707.5-153707.29"
+ attribute \src "libresoc.v:153371.5-153371.29"
switch \initial
- attribute \src "libresoc.v:153707.9-153707.17"
+ attribute \src "libresoc.v:153371.9-153371.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:153716.3-153724.6"
- process $proc$libresoc.v:153716$7836
+ attribute \src "libresoc.v:153380.3-153388.6"
+ process $proc$libresoc.v:153380$7784
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[3:0]$7837 $1\prev_wr_go$next[3:0]$7838
- attribute \src "libresoc.v:153717.5-153717.29"
+ assign $0\prev_wr_go$next[3:0]$7785 $1\prev_wr_go$next[3:0]$7786
+ attribute \src "libresoc.v:153381.5-153381.29"
switch \initial
- attribute \src "libresoc.v:153717.9-153717.17"
+ attribute \src "libresoc.v:153381.9-153381.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[3:0]$7838 4'0000
- case
- assign $1\prev_wr_go$next[3:0]$7838 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7837
- end
- connect \$100 $and$libresoc.v:153192$7625_Y
- connect \$102 $and$libresoc.v:153193$7626_Y
- connect \$104 $and$libresoc.v:153194$7627_Y
- connect \$106 $and$libresoc.v:153195$7628_Y
- connect \$108 $and$libresoc.v:153196$7629_Y
- connect \$10 $and$libresoc.v:153197$7630_Y
- connect \$110 $and$libresoc.v:153198$7631_Y
- connect \$112 $and$libresoc.v:153199$7632_Y
- connect \$114 $and$libresoc.v:153200$7633_Y
- connect \$116 $and$libresoc.v:153201$7634_Y
- connect \$118 $and$libresoc.v:153202$7635_Y
- connect \$120 $and$libresoc.v:153203$7636_Y
- connect \$12 $not$libresoc.v:153204$7637_Y
- connect \$14 $and$libresoc.v:153205$7638_Y
- connect \$16 $not$libresoc.v:153206$7639_Y
- connect \$18 $and$libresoc.v:153207$7640_Y
- connect \$20 $and$libresoc.v:153208$7641_Y
- connect \$24 $not$libresoc.v:153209$7642_Y
- connect \$26 $and$libresoc.v:153210$7643_Y
- connect \$23 $reduce_or$libresoc.v:153211$7644_Y
- connect \$22 $not$libresoc.v:153212$7645_Y
- connect \$2 $and$libresoc.v:153213$7646_Y
- connect \$30 $and$libresoc.v:153214$7647_Y
- connect \$32 $reduce_or$libresoc.v:153215$7648_Y
- connect \$34 $reduce_or$libresoc.v:153216$7649_Y
- connect \$36 $or$libresoc.v:153217$7650_Y
- connect \$38 $not$libresoc.v:153218$7651_Y
- connect \$40 $and$libresoc.v:153219$7652_Y
- connect \$42 $and$libresoc.v:153220$7653_Y
- connect \$44 $eq$libresoc.v:153221$7654_Y
- connect \$46 $and$libresoc.v:153222$7655_Y
- connect \$48 $eq$libresoc.v:153223$7656_Y
- connect \$50 $and$libresoc.v:153224$7657_Y
- connect \$52 $and$libresoc.v:153225$7658_Y
- connect \$54 $and$libresoc.v:153226$7659_Y
- connect \$56 $or$libresoc.v:153227$7660_Y
- connect \$58 $or$libresoc.v:153228$7661_Y
- connect \$5 $not$libresoc.v:153229$7662_Y
- connect \$60 $or$libresoc.v:153230$7663_Y
- connect \$62 $or$libresoc.v:153231$7664_Y
- connect \$64 $and$libresoc.v:153232$7665_Y
- connect \$66 $and$libresoc.v:153233$7666_Y
- connect \$68 $or$libresoc.v:153234$7667_Y
- connect \$70 $and$libresoc.v:153235$7668_Y
- connect \$72 $and$libresoc.v:153236$7669_Y
- connect \$74 $and$libresoc.v:153237$7670_Y
- connect \$76 $and$libresoc.v:153238$7671_Y
- connect \$78 $ternary$libresoc.v:153239$7672_Y
- connect \$7 $or$libresoc.v:153240$7673_Y
- connect \$80 $ternary$libresoc.v:153241$7674_Y
- connect \$82 $ternary$libresoc.v:153242$7675_Y
- connect \$84 $ternary$libresoc.v:153243$7676_Y
- connect \$86 $ternary$libresoc.v:153244$7677_Y
- connect \$88 $and$libresoc.v:153245$7678_Y
- connect \$4 $reduce_and$libresoc.v:153246$7679_Y
- connect \$90 $and$libresoc.v:153247$7680_Y
- connect \$92 $and$libresoc.v:153248$7681_Y
- connect \$94 $not$libresoc.v:153249$7682_Y
- connect \$96 $and$libresoc.v:153250$7683_Y
- connect \$98 $not$libresoc.v:153251$7684_Y
+ assign $1\prev_wr_go$next[3:0]$7786 4'0000
+ case
+ assign $1\prev_wr_go$next[3:0]$7786 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7785
+ end
+ connect \$100 $and$libresoc.v:152856$7573_Y
+ connect \$102 $and$libresoc.v:152857$7574_Y
+ connect \$104 $and$libresoc.v:152858$7575_Y
+ connect \$106 $and$libresoc.v:152859$7576_Y
+ connect \$108 $and$libresoc.v:152860$7577_Y
+ connect \$10 $and$libresoc.v:152861$7578_Y
+ connect \$110 $and$libresoc.v:152862$7579_Y
+ connect \$112 $and$libresoc.v:152863$7580_Y
+ connect \$114 $and$libresoc.v:152864$7581_Y
+ connect \$116 $and$libresoc.v:152865$7582_Y
+ connect \$118 $and$libresoc.v:152866$7583_Y
+ connect \$120 $and$libresoc.v:152867$7584_Y
+ connect \$12 $not$libresoc.v:152868$7585_Y
+ connect \$14 $and$libresoc.v:152869$7586_Y
+ connect \$16 $not$libresoc.v:152870$7587_Y
+ connect \$18 $and$libresoc.v:152871$7588_Y
+ connect \$20 $and$libresoc.v:152872$7589_Y
+ connect \$24 $not$libresoc.v:152873$7590_Y
+ connect \$26 $and$libresoc.v:152874$7591_Y
+ connect \$23 $reduce_or$libresoc.v:152875$7592_Y
+ connect \$22 $not$libresoc.v:152876$7593_Y
+ connect \$2 $and$libresoc.v:152877$7594_Y
+ connect \$30 $and$libresoc.v:152878$7595_Y
+ connect \$32 $reduce_or$libresoc.v:152879$7596_Y
+ connect \$34 $reduce_or$libresoc.v:152880$7597_Y
+ connect \$36 $or$libresoc.v:152881$7598_Y
+ connect \$38 $not$libresoc.v:152882$7599_Y
+ connect \$40 $and$libresoc.v:152883$7600_Y
+ connect \$42 $and$libresoc.v:152884$7601_Y
+ connect \$44 $eq$libresoc.v:152885$7602_Y
+ connect \$46 $and$libresoc.v:152886$7603_Y
+ connect \$48 $eq$libresoc.v:152887$7604_Y
+ connect \$50 $and$libresoc.v:152888$7605_Y
+ connect \$52 $and$libresoc.v:152889$7606_Y
+ connect \$54 $and$libresoc.v:152890$7607_Y
+ connect \$56 $or$libresoc.v:152891$7608_Y
+ connect \$58 $or$libresoc.v:152892$7609_Y
+ connect \$5 $not$libresoc.v:152893$7610_Y
+ connect \$60 $or$libresoc.v:152894$7611_Y
+ connect \$62 $or$libresoc.v:152895$7612_Y
+ connect \$64 $and$libresoc.v:152896$7613_Y
+ connect \$66 $and$libresoc.v:152897$7614_Y
+ connect \$68 $or$libresoc.v:152898$7615_Y
+ connect \$70 $and$libresoc.v:152899$7616_Y
+ connect \$72 $and$libresoc.v:152900$7617_Y
+ connect \$74 $and$libresoc.v:152901$7618_Y
+ connect \$76 $and$libresoc.v:152902$7619_Y
+ connect \$78 $ternary$libresoc.v:152903$7620_Y
+ connect \$7 $or$libresoc.v:152904$7621_Y
+ connect \$80 $ternary$libresoc.v:152905$7622_Y
+ connect \$82 $ternary$libresoc.v:152906$7623_Y
+ connect \$84 $ternary$libresoc.v:152907$7624_Y
+ connect \$86 $ternary$libresoc.v:152908$7625_Y
+ connect \$88 $and$libresoc.v:152909$7626_Y
+ connect \$4 $reduce_and$libresoc.v:152910$7627_Y
+ connect \$90 $and$libresoc.v:152911$7628_Y
+ connect \$92 $and$libresoc.v:152912$7629_Y
+ connect \$94 $not$libresoc.v:152913$7630_Y
+ connect \$96 $and$libresoc.v:152914$7631_Y
+ connect \$98 $not$libresoc.v:152915$7632_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$112
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:153759.1-154092.10"
+attribute \src "libresoc.v:153423.1-153756.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
attribute \generator "nMigen"
module \mul1
- attribute \src "libresoc.v:154059.18-154059.116"
- wire $and$libresoc.v:154059$7879_Y
- attribute \src "libresoc.v:154061.18-154061.116"
- wire $and$libresoc.v:154061$7881_Y
- attribute \src "libresoc.v:154062.18-154062.117"
- wire $and$libresoc.v:154062$7882_Y
- attribute \src "libresoc.v:154063.18-154063.117"
- wire $and$libresoc.v:154063$7883_Y
- attribute \src "libresoc.v:154066.18-154066.95"
- wire width 65 $extend$libresoc.v:154066$7886_Y
- attribute \src "libresoc.v:154067.18-154067.91"
- wire width 65 $extend$libresoc.v:154067$7888_Y
- attribute \src "libresoc.v:154069.18-154069.95"
- wire width 65 $extend$libresoc.v:154069$7891_Y
- attribute \src "libresoc.v:154070.18-154070.91"
- wire width 65 $extend$libresoc.v:154070$7893_Y
- attribute \src "libresoc.v:154066.18-154066.95"
- wire width 65 $neg$libresoc.v:154066$7887_Y
- attribute \src "libresoc.v:154069.18-154069.95"
- wire width 65 $neg$libresoc.v:154069$7892_Y
- attribute \src "libresoc.v:154067.18-154067.91"
- wire width 65 $pos$libresoc.v:154067$7889_Y
- attribute \src "libresoc.v:154070.18-154070.91"
- wire width 65 $pos$libresoc.v:154070$7894_Y
- attribute \src "libresoc.v:154058.18-154058.125"
- wire $ternary$libresoc.v:154058$7878_Y
- attribute \src "libresoc.v:154060.18-154060.125"
- wire $ternary$libresoc.v:154060$7880_Y
- attribute \src "libresoc.v:154068.18-154068.112"
- wire width 65 $ternary$libresoc.v:154068$7890_Y
- attribute \src "libresoc.v:154071.18-154071.112"
- wire width 65 $ternary$libresoc.v:154071$7895_Y
- attribute \src "libresoc.v:154072.18-154072.116"
- wire width 32 $ternary$libresoc.v:154072$7896_Y
- attribute \src "libresoc.v:154073.18-154073.116"
- wire width 32 $ternary$libresoc.v:154073$7897_Y
- attribute \src "libresoc.v:154064.18-154064.106"
- wire $xor$libresoc.v:154064$7884_Y
- attribute \src "libresoc.v:154065.18-154065.110"
- wire $xor$libresoc.v:154065$7885_Y
+ attribute \src "libresoc.v:153723.18-153723.116"
+ wire $and$libresoc.v:153723$7827_Y
+ attribute \src "libresoc.v:153725.18-153725.116"
+ wire $and$libresoc.v:153725$7829_Y
+ attribute \src "libresoc.v:153726.18-153726.117"
+ wire $and$libresoc.v:153726$7830_Y
+ attribute \src "libresoc.v:153727.18-153727.117"
+ wire $and$libresoc.v:153727$7831_Y
+ attribute \src "libresoc.v:153730.18-153730.95"
+ wire width 65 $extend$libresoc.v:153730$7834_Y
+ attribute \src "libresoc.v:153731.18-153731.91"
+ wire width 65 $extend$libresoc.v:153731$7836_Y
+ attribute \src "libresoc.v:153733.18-153733.95"
+ wire width 65 $extend$libresoc.v:153733$7839_Y
+ attribute \src "libresoc.v:153734.18-153734.91"
+ wire width 65 $extend$libresoc.v:153734$7841_Y
+ attribute \src "libresoc.v:153730.18-153730.95"
+ wire width 65 $neg$libresoc.v:153730$7835_Y
+ attribute \src "libresoc.v:153733.18-153733.95"
+ wire width 65 $neg$libresoc.v:153733$7840_Y
+ attribute \src "libresoc.v:153731.18-153731.91"
+ wire width 65 $pos$libresoc.v:153731$7837_Y
+ attribute \src "libresoc.v:153734.18-153734.91"
+ wire width 65 $pos$libresoc.v:153734$7842_Y
+ attribute \src "libresoc.v:153722.18-153722.125"
+ wire $ternary$libresoc.v:153722$7826_Y
+ attribute \src "libresoc.v:153724.18-153724.125"
+ wire $ternary$libresoc.v:153724$7828_Y
+ attribute \src "libresoc.v:153732.18-153732.112"
+ wire width 65 $ternary$libresoc.v:153732$7838_Y
+ attribute \src "libresoc.v:153735.18-153735.112"
+ wire width 65 $ternary$libresoc.v:153735$7843_Y
+ attribute \src "libresoc.v:153736.18-153736.116"
+ wire width 32 $ternary$libresoc.v:153736$7844_Y
+ attribute \src "libresoc.v:153737.18-153737.116"
+ wire width 32 $ternary$libresoc.v:153737$7845_Y
+ attribute \src "libresoc.v:153728.18-153728.106"
+ wire $xor$libresoc.v:153728$7832_Y
+ attribute \src "libresoc.v:153729.18-153729.110"
+ wire $xor$libresoc.v:153729$7833_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
wire \$17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 31 \xer_so$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
- cell $and $and$libresoc.v:154059$7879
+ cell $and $and$libresoc.v:153723$7827
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$17
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:154059$7879_Y
+ connect \Y $and$libresoc.v:153723$7827_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
- cell $and $and$libresoc.v:154061$7881
+ cell $and $and$libresoc.v:153725$7829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$21
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:154061$7881_Y
+ connect \Y $and$libresoc.v:153725$7829_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
- cell $and $and$libresoc.v:154062$7882
+ cell $and $and$libresoc.v:153726$7830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31]
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:154062$7882_Y
+ connect \Y $and$libresoc.v:153726$7830_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
- cell $and $and$libresoc.v:154063$7883
+ cell $and $and$libresoc.v:153727$7831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rb [31]
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:154063$7883_Y
+ connect \Y $and$libresoc.v:153727$7831_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $pos $extend$libresoc.v:154066$7886
+ cell $pos $extend$libresoc.v:153730$7834
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:154066$7886_Y
+ connect \Y $extend$libresoc.v:153730$7834_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:154067$7888
+ cell $pos $extend$libresoc.v:153731$7836
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:154067$7888_Y
+ connect \Y $extend$libresoc.v:153731$7836_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $pos $extend$libresoc.v:154069$7891
+ cell $pos $extend$libresoc.v:153733$7839
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:154069$7891_Y
+ connect \Y $extend$libresoc.v:153733$7839_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:154070$7893
+ cell $pos $extend$libresoc.v:153734$7841
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:154070$7893_Y
+ connect \Y $extend$libresoc.v:153734$7841_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $neg $neg$libresoc.v:154066$7887
+ cell $neg $neg$libresoc.v:153730$7835
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:154066$7886_Y
- connect \Y $neg$libresoc.v:154066$7887_Y
+ connect \A $extend$libresoc.v:153730$7834_Y
+ connect \Y $neg$libresoc.v:153730$7835_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $neg $neg$libresoc.v:154069$7892
+ cell $neg $neg$libresoc.v:153733$7840
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:154069$7891_Y
- connect \Y $neg$libresoc.v:154069$7892_Y
+ connect \A $extend$libresoc.v:153733$7839_Y
+ connect \Y $neg$libresoc.v:153733$7840_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:154067$7889
+ cell $pos $pos$libresoc.v:153731$7837
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:154067$7888_Y
- connect \Y $pos$libresoc.v:154067$7889_Y
+ connect \A $extend$libresoc.v:153731$7836_Y
+ connect \Y $pos$libresoc.v:153731$7837_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:154070$7894
+ cell $pos $pos$libresoc.v:153734$7842
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:154070$7893_Y
- connect \Y $pos$libresoc.v:154070$7894_Y
+ connect \A $extend$libresoc.v:153734$7841_Y
+ connect \Y $pos$libresoc.v:153734$7842_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
- cell $mux $ternary$libresoc.v:154058$7878
+ cell $mux $ternary$libresoc.v:153722$7826
parameter \WIDTH 1
connect \A \ra [63]
connect \B \ra [31]
connect \S \mul_op__is_32bit
- connect \Y $ternary$libresoc.v:154058$7878_Y
+ connect \Y $ternary$libresoc.v:153722$7826_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
- cell $mux $ternary$libresoc.v:154060$7880
+ cell $mux $ternary$libresoc.v:153724$7828
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \mul_op__is_32bit
- connect \Y $ternary$libresoc.v:154060$7880_Y
+ connect \Y $ternary$libresoc.v:153724$7828_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $mux $ternary$libresoc.v:154068$7890
+ cell $mux $ternary$libresoc.v:153732$7838
parameter \WIDTH 65
connect \A \$36
connect \B \$34
connect \S \sign_a
- connect \Y $ternary$libresoc.v:154068$7890_Y
+ connect \Y $ternary$libresoc.v:153732$7838_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $mux $ternary$libresoc.v:154071$7895
+ cell $mux $ternary$libresoc.v:153735$7843
parameter \WIDTH 65
connect \A \$43
connect \B \$41
connect \S \sign_b
- connect \Y $ternary$libresoc.v:154071$7895_Y
+ connect \Y $ternary$libresoc.v:153735$7843_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:154072$7896
+ cell $mux $ternary$libresoc.v:153736$7844
parameter \WIDTH 32
connect \A \abs_a [63:32]
connect \B 0
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:154072$7896_Y
+ connect \Y $ternary$libresoc.v:153736$7844_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:154073$7897
+ cell $mux $ternary$libresoc.v:153737$7845
parameter \WIDTH 32
connect \A \abs_b [63:32]
connect \B 0
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:154073$7897_Y
+ connect \Y $ternary$libresoc.v:153737$7845_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
- cell $xor $xor$libresoc.v:154064$7884
+ cell $xor $xor$libresoc.v:153728$7832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sign_a
connect \B \sign_b
- connect \Y $xor$libresoc.v:154064$7884_Y
+ connect \Y $xor$libresoc.v:153728$7832_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
- cell $xor $xor$libresoc.v:154065$7885
+ cell $xor $xor$libresoc.v:153729$7833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sign32_a
connect \B \sign32_b
- connect \Y $xor$libresoc.v:154065$7885_Y
- end
- connect \$17 $ternary$libresoc.v:154058$7878_Y
- connect \$19 $and$libresoc.v:154059$7879_Y
- connect \$21 $ternary$libresoc.v:154060$7880_Y
- connect \$23 $and$libresoc.v:154061$7881_Y
- connect \$25 $and$libresoc.v:154062$7882_Y
- connect \$27 $and$libresoc.v:154063$7883_Y
- connect \$29 $xor$libresoc.v:154064$7884_Y
- connect \$31 $xor$libresoc.v:154065$7885_Y
- connect \$34 $neg$libresoc.v:154066$7887_Y
- connect \$36 $pos$libresoc.v:154067$7889_Y
- connect \$38 $ternary$libresoc.v:154068$7890_Y
- connect \$41 $neg$libresoc.v:154069$7892_Y
- connect \$43 $pos$libresoc.v:154070$7894_Y
- connect \$45 $ternary$libresoc.v:154071$7895_Y
- connect \$47 $ternary$libresoc.v:154072$7896_Y
- connect \$49 $ternary$libresoc.v:154073$7897_Y
+ connect \Y $xor$libresoc.v:153729$7833_Y
+ end
+ connect \$17 $ternary$libresoc.v:153722$7826_Y
+ connect \$19 $and$libresoc.v:153723$7827_Y
+ connect \$21 $ternary$libresoc.v:153724$7828_Y
+ connect \$23 $and$libresoc.v:153725$7829_Y
+ connect \$25 $and$libresoc.v:153726$7830_Y
+ connect \$27 $and$libresoc.v:153727$7831_Y
+ connect \$29 $xor$libresoc.v:153728$7832_Y
+ connect \$31 $xor$libresoc.v:153729$7833_Y
+ connect \$34 $neg$libresoc.v:153730$7835_Y
+ connect \$36 $pos$libresoc.v:153731$7837_Y
+ connect \$38 $ternary$libresoc.v:153732$7838_Y
+ connect \$41 $neg$libresoc.v:153733$7840_Y
+ connect \$43 $pos$libresoc.v:153734$7842_Y
+ connect \$45 $ternary$libresoc.v:153735$7843_Y
+ connect \$47 $ternary$libresoc.v:153736$7844_Y
+ connect \$49 $ternary$libresoc.v:153737$7845_Y
connect \$33 \$38
connect \$40 \$45
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \sign_a \$19
connect \is_32bit \mul_op__is_32bit
end
-attribute \src "libresoc.v:154096.1-154359.10"
+attribute \src "libresoc.v:153760.1-154023.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
attribute \generator "nMigen"
module \mul2
- attribute \src "libresoc.v:154352.18-154352.98"
- wire width 129 $extend$libresoc.v:154352$7899_Y
- attribute \src "libresoc.v:154351.18-154351.99"
- wire width 128 $mul$libresoc.v:154351$7898_Y
- attribute \src "libresoc.v:154352.18-154352.98"
- wire width 129 $pos$libresoc.v:154352$7900_Y
+ attribute \src "libresoc.v:154016.18-154016.98"
+ wire width 129 $extend$libresoc.v:154016$7847_Y
+ attribute \src "libresoc.v:154015.18-154015.99"
+ wire width 128 $mul$libresoc.v:154015$7846_Y
+ attribute \src "libresoc.v:154016.18-154016.98"
+ wire width 129 $pos$libresoc.v:154016$7848_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
wire width 129 \$17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 32 \xer_so$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $pos $extend$libresoc.v:154352$7899
+ cell $pos $extend$libresoc.v:154016$7847
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \Y_WIDTH 129
connect \A \$18
- connect \Y $extend$libresoc.v:154352$7899_Y
+ connect \Y $extend$libresoc.v:154016$7847_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $mul $mul$libresoc.v:154351$7898
+ cell $mul $mul$libresoc.v:154015$7846
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 128
connect \A \ra
connect \B \rb
- connect \Y $mul$libresoc.v:154351$7898_Y
+ connect \Y $mul$libresoc.v:154015$7846_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $pos $pos$libresoc.v:154352$7900
+ cell $pos $pos$libresoc.v:154016$7848
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 129
- connect \A $extend$libresoc.v:154352$7899_Y
- connect \Y $pos$libresoc.v:154352$7900_Y
+ connect \A $extend$libresoc.v:154016$7847_Y
+ connect \Y $pos$libresoc.v:154016$7848_Y
end
- connect \$18 $mul$libresoc.v:154351$7898_Y
- connect \$17 $pos$libresoc.v:154352$7900_Y
+ connect \$18 $mul$libresoc.v:154015$7846_Y
+ connect \$17 $pos$libresoc.v:154016$7848_Y
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$14 \xer_so
connect \neg_res$15 \neg_res
connect \o \$17
end
-attribute \src "libresoc.v:154363.1-154772.10"
+attribute \src "libresoc.v:154027.1-154436.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
attribute \generator "nMigen"
module \mul3
- attribute \src "libresoc.v:154364.7-154364.20"
+ attribute \src "libresoc.v:154028.7-154028.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:154701.3-154727.6"
+ attribute \src "libresoc.v:154365.3-154391.6"
wire $0\mul_ov[0:0]
- attribute \src "libresoc.v:154663.3-154681.6"
- wire width 64 $0\o$14[63:0]$7917
- attribute \src "libresoc.v:154682.3-154700.6"
+ attribute \src "libresoc.v:154327.3-154345.6"
+ wire width 64 $0\o$14[63:0]$7865
+ attribute \src "libresoc.v:154346.3-154364.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:154728.3-154746.6"
+ attribute \src "libresoc.v:154392.3-154410.6"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:154747.3-154765.6"
+ attribute \src "libresoc.v:154411.3-154429.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:154701.3-154727.6"
+ attribute \src "libresoc.v:154365.3-154391.6"
wire $1\mul_ov[0:0]
- attribute \src "libresoc.v:154663.3-154681.6"
- wire width 64 $1\o$14[63:0]$7918
- attribute \src "libresoc.v:154682.3-154700.6"
+ attribute \src "libresoc.v:154327.3-154345.6"
+ wire width 64 $1\o$14[63:0]$7866
+ attribute \src "libresoc.v:154346.3-154364.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:154728.3-154746.6"
+ attribute \src "libresoc.v:154392.3-154410.6"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:154747.3-154765.6"
+ attribute \src "libresoc.v:154411.3-154429.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:154701.3-154727.6"
+ attribute \src "libresoc.v:154365.3-154391.6"
wire $2\mul_ov[0:0]
- attribute \src "libresoc.v:154657.18-154657.104"
- wire $and$libresoc.v:154657$7909_Y
- attribute \src "libresoc.v:154661.18-154661.104"
- wire $and$libresoc.v:154661$7913_Y
- attribute \src "libresoc.v:154651.18-154651.95"
- wire width 130 $extend$libresoc.v:154651$7901_Y
- attribute \src "libresoc.v:154652.18-154652.90"
- wire width 130 $extend$libresoc.v:154652$7903_Y
- attribute \src "libresoc.v:154662.18-154662.95"
- wire width 2 $extend$libresoc.v:154662$7914_Y
- attribute \src "libresoc.v:154651.18-154651.95"
- wire width 130 $neg$libresoc.v:154651$7902_Y
- attribute \src "libresoc.v:154656.18-154656.98"
- wire $not$libresoc.v:154656$7908_Y
- attribute \src "libresoc.v:154660.18-154660.98"
- wire $not$libresoc.v:154660$7912_Y
- attribute \src "libresoc.v:154652.18-154652.90"
- wire width 130 $pos$libresoc.v:154652$7904_Y
- attribute \src "libresoc.v:154662.18-154662.95"
- wire width 2 $pos$libresoc.v:154662$7915_Y
- attribute \src "libresoc.v:154655.18-154655.106"
- wire $reduce_and$libresoc.v:154655$7907_Y
- attribute \src "libresoc.v:154659.18-154659.107"
- wire $reduce_and$libresoc.v:154659$7911_Y
- attribute \src "libresoc.v:154654.18-154654.106"
- wire $reduce_or$libresoc.v:154654$7906_Y
- attribute \src "libresoc.v:154658.18-154658.107"
- wire $reduce_or$libresoc.v:154658$7910_Y
- attribute \src "libresoc.v:154653.18-154653.114"
- wire width 130 $ternary$libresoc.v:154653$7905_Y
+ attribute \src "libresoc.v:154321.18-154321.104"
+ wire $and$libresoc.v:154321$7857_Y
+ attribute \src "libresoc.v:154325.18-154325.104"
+ wire $and$libresoc.v:154325$7861_Y
+ attribute \src "libresoc.v:154315.18-154315.95"
+ wire width 130 $extend$libresoc.v:154315$7849_Y
+ attribute \src "libresoc.v:154316.18-154316.90"
+ wire width 130 $extend$libresoc.v:154316$7851_Y
+ attribute \src "libresoc.v:154326.18-154326.95"
+ wire width 2 $extend$libresoc.v:154326$7862_Y
+ attribute \src "libresoc.v:154315.18-154315.95"
+ wire width 130 $neg$libresoc.v:154315$7850_Y
+ attribute \src "libresoc.v:154320.18-154320.98"
+ wire $not$libresoc.v:154320$7856_Y
+ attribute \src "libresoc.v:154324.18-154324.98"
+ wire $not$libresoc.v:154324$7860_Y
+ attribute \src "libresoc.v:154316.18-154316.90"
+ wire width 130 $pos$libresoc.v:154316$7852_Y
+ attribute \src "libresoc.v:154326.18-154326.95"
+ wire width 2 $pos$libresoc.v:154326$7863_Y
+ attribute \src "libresoc.v:154319.18-154319.106"
+ wire $reduce_and$libresoc.v:154319$7855_Y
+ attribute \src "libresoc.v:154323.18-154323.107"
+ wire $reduce_and$libresoc.v:154323$7859_Y
+ attribute \src "libresoc.v:154318.18-154318.106"
+ wire $reduce_or$libresoc.v:154318$7854_Y
+ attribute \src "libresoc.v:154322.18-154322.107"
+ wire $reduce_or$libresoc.v:154322$7858_Y
+ attribute \src "libresoc.v:154317.18-154317.114"
+ wire width 130 $ternary$libresoc.v:154317$7853_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
wire width 130 \$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
wire \$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \$39
- attribute \src "libresoc.v:154364.7-154364.15"
+ attribute \src "libresoc.v:154028.7-154028.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
wire \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 34 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $and $and$libresoc.v:154657$7909
+ cell $and $and$libresoc.v:154321$7857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $and$libresoc.v:154657$7909_Y
+ connect \Y $and$libresoc.v:154321$7857_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $and $and$libresoc.v:154661$7913
+ cell $and $and$libresoc.v:154325$7861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $and$libresoc.v:154661$7913_Y
+ connect \Y $and$libresoc.v:154325$7861_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $pos $extend$libresoc.v:154651$7901
+ cell $pos $extend$libresoc.v:154315$7849
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 130
connect \A \o
- connect \Y $extend$libresoc.v:154651$7901_Y
+ connect \Y $extend$libresoc.v:154315$7849_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:154652$7903
+ cell $pos $extend$libresoc.v:154316$7851
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 130
connect \A \o
- connect \Y $extend$libresoc.v:154652$7903_Y
+ connect \Y $extend$libresoc.v:154316$7851_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:154662$7914
+ cell $pos $extend$libresoc.v:154326$7862
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 2
connect \A \xer_so
- connect \Y $extend$libresoc.v:154662$7914_Y
+ connect \Y $extend$libresoc.v:154326$7862_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $neg $neg$libresoc.v:154651$7902
+ cell $neg $neg$libresoc.v:154315$7850
parameter \A_SIGNED 0
parameter \A_WIDTH 130
parameter \Y_WIDTH 130
- connect \A $extend$libresoc.v:154651$7901_Y
- connect \Y $neg$libresoc.v:154651$7902_Y
+ connect \A $extend$libresoc.v:154315$7849_Y
+ connect \Y $neg$libresoc.v:154315$7850_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $not $not$libresoc.v:154656$7908
+ cell $not $not$libresoc.v:154320$7856
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $not$libresoc.v:154656$7908_Y
+ connect \Y $not$libresoc.v:154320$7856_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $not $not$libresoc.v:154660$7912
+ cell $not $not$libresoc.v:154324$7860
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$34
- connect \Y $not$libresoc.v:154660$7912_Y
+ connect \Y $not$libresoc.v:154324$7860_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:154652$7904
+ cell $pos $pos$libresoc.v:154316$7852
parameter \A_SIGNED 0
parameter \A_WIDTH 130
parameter \Y_WIDTH 130
- connect \A $extend$libresoc.v:154652$7903_Y
- connect \Y $pos$libresoc.v:154652$7904_Y
+ connect \A $extend$libresoc.v:154316$7851_Y
+ connect \Y $pos$libresoc.v:154316$7852_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:154662$7915
+ cell $pos $pos$libresoc.v:154326$7863
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $extend$libresoc.v:154662$7914_Y
- connect \Y $pos$libresoc.v:154662$7915_Y
+ connect \A $extend$libresoc.v:154326$7862_Y
+ connect \Y $pos$libresoc.v:154326$7863_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $reduce_and $reduce_and$libresoc.v:154655$7907
+ cell $reduce_and $reduce_and$libresoc.v:154319$7855
parameter \A_SIGNED 0
parameter \A_WIDTH 33
parameter \Y_WIDTH 1
connect \A \mul_o [63:31]
- connect \Y $reduce_and$libresoc.v:154655$7907_Y
+ connect \Y $reduce_and$libresoc.v:154319$7855_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $reduce_and $reduce_and$libresoc.v:154659$7911
+ cell $reduce_and $reduce_and$libresoc.v:154323$7859
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 1
connect \A \mul_o [127:63]
- connect \Y $reduce_and$libresoc.v:154659$7911_Y
+ connect \Y $reduce_and$libresoc.v:154323$7859_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $reduce_or $reduce_or$libresoc.v:154654$7906
+ cell $reduce_or $reduce_or$libresoc.v:154318$7854
parameter \A_SIGNED 0
parameter \A_WIDTH 33
parameter \Y_WIDTH 1
connect \A \mul_o [63:31]
- connect \Y $reduce_or$libresoc.v:154654$7906_Y
+ connect \Y $reduce_or$libresoc.v:154318$7854_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $reduce_or $reduce_or$libresoc.v:154658$7910
+ cell $reduce_or $reduce_or$libresoc.v:154322$7858
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 1
connect \A \mul_o [127:63]
- connect \Y $reduce_or$libresoc.v:154658$7910_Y
+ connect \Y $reduce_or$libresoc.v:154322$7858_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $mux $ternary$libresoc.v:154653$7905
+ cell $mux $ternary$libresoc.v:154317$7853
parameter \WIDTH 130
connect \A \$19
connect \B \$17
connect \S \neg_res
- connect \Y $ternary$libresoc.v:154653$7905_Y
+ connect \Y $ternary$libresoc.v:154317$7853_Y
end
- attribute \src "libresoc.v:154364.7-154364.20"
- process $proc$libresoc.v:154364$7923
+ attribute \src "libresoc.v:154028.7-154028.20"
+ process $proc$libresoc.v:154028$7871
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:154663.3-154681.6"
- process $proc$libresoc.v:154663$7916
+ attribute \src "libresoc.v:154327.3-154345.6"
+ process $proc$libresoc.v:154327$7864
assign { } { }
assign { } { }
- assign $0\o$14[63:0]$7917 $1\o$14[63:0]$7918
- attribute \src "libresoc.v:154664.5-154664.29"
+ assign $0\o$14[63:0]$7865 $1\o$14[63:0]$7866
+ attribute \src "libresoc.v:154328.5-154328.29"
switch \initial
- attribute \src "libresoc.v:154664.9-154664.17"
+ attribute \src "libresoc.v:154328.9-154328.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110100
assign { } { }
- assign $1\o$14[63:0]$7918 { \mul_o [63:32] \mul_o [63:32] }
+ assign $1\o$14[63:0]$7866 { \mul_o [63:32] \mul_o [63:32] }
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011
assign { } { }
- assign $1\o$14[63:0]$7918 \mul_o [127:64]
+ assign $1\o$14[63:0]$7866 \mul_o [127:64]
attribute \src "libresoc.v:0.0-0.0"
case 7'0110010
assign { } { }
- assign $1\o$14[63:0]$7918 \mul_o [63:0]
+ assign $1\o$14[63:0]$7866 \mul_o [63:0]
case
- assign $1\o$14[63:0]$7918 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\o$14[63:0]$7866 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \o$14 $0\o$14[63:0]$7917
+ update \o$14 $0\o$14[63:0]$7865
end
- attribute \src "libresoc.v:154682.3-154700.6"
- process $proc$libresoc.v:154682$7919
+ attribute \src "libresoc.v:154346.3-154364.6"
+ process $proc$libresoc.v:154346$7867
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:154683.5-154683.29"
+ attribute \src "libresoc.v:154347.5-154347.29"
switch \initial
- attribute \src "libresoc.v:154683.9-154683.17"
+ attribute \src "libresoc.v:154347.9-154347.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:154701.3-154727.6"
- process $proc$libresoc.v:154701$7920
+ attribute \src "libresoc.v:154365.3-154391.6"
+ process $proc$libresoc.v:154365$7868
assign { } { }
assign { } { }
assign $0\mul_ov[0:0] $1\mul_ov[0:0]
- attribute \src "libresoc.v:154702.5-154702.29"
+ attribute \src "libresoc.v:154366.5-154366.29"
switch \initial
- attribute \src "libresoc.v:154702.9-154702.17"
+ attribute \src "libresoc.v:154366.9-154366.17"
case 1'1
case
end
sync always
update \mul_ov $0\mul_ov[0:0]
end
- attribute \src "libresoc.v:154728.3-154746.6"
- process $proc$libresoc.v:154728$7921
+ attribute \src "libresoc.v:154392.3-154410.6"
+ process $proc$libresoc.v:154392$7869
assign { } { }
assign { } { }
assign $0\xer_ov[1:0] $1\xer_ov[1:0]
- attribute \src "libresoc.v:154729.5-154729.29"
+ attribute \src "libresoc.v:154393.5-154393.29"
switch \initial
- attribute \src "libresoc.v:154729.9-154729.17"
+ attribute \src "libresoc.v:154393.9-154393.17"
case 1'1
case
end
sync always
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:154747.3-154765.6"
- process $proc$libresoc.v:154747$7922
+ attribute \src "libresoc.v:154411.3-154429.6"
+ process $proc$libresoc.v:154411$7870
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:154748.5-154748.29"
+ attribute \src "libresoc.v:154412.5-154412.29"
switch \initial
- attribute \src "libresoc.v:154748.9-154748.17"
+ attribute \src "libresoc.v:154412.9-154412.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$17 $neg$libresoc.v:154651$7902_Y
- connect \$19 $pos$libresoc.v:154652$7904_Y
- connect \$21 $ternary$libresoc.v:154653$7905_Y
- connect \$23 $reduce_or$libresoc.v:154654$7906_Y
- connect \$26 $reduce_and$libresoc.v:154655$7907_Y
- connect \$25 $not$libresoc.v:154656$7908_Y
- connect \$29 $and$libresoc.v:154657$7909_Y
- connect \$31 $reduce_or$libresoc.v:154658$7910_Y
- connect \$34 $reduce_and$libresoc.v:154659$7911_Y
- connect \$33 $not$libresoc.v:154660$7912_Y
- connect \$37 $and$libresoc.v:154661$7913_Y
- connect \$39 $pos$libresoc.v:154662$7915_Y
+ connect \$17 $neg$libresoc.v:154315$7850_Y
+ connect \$19 $pos$libresoc.v:154316$7852_Y
+ connect \$21 $ternary$libresoc.v:154317$7853_Y
+ connect \$23 $reduce_or$libresoc.v:154318$7854_Y
+ connect \$26 $reduce_and$libresoc.v:154319$7855_Y
+ connect \$25 $not$libresoc.v:154320$7856_Y
+ connect \$29 $and$libresoc.v:154321$7857_Y
+ connect \$31 $reduce_or$libresoc.v:154322$7858_Y
+ connect \$34 $reduce_and$libresoc.v:154323$7859_Y
+ connect \$33 $not$libresoc.v:154324$7860_Y
+ connect \$37 $and$libresoc.v:154325$7861_Y
+ connect \$39 $pos$libresoc.v:154326$7863_Y
connect \$16 \$21
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \mul_o \$21 [128:0]
connect \is_32bit \mul_op__is_32bit
end
-attribute \src "libresoc.v:154776.1-155993.10"
+attribute \src "libresoc.v:154440.1-155657.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1"
attribute \generator "nMigen"
module \mul_pipe1
- attribute \src "libresoc.v:154777.7-154777.20"
+ attribute \src "libresoc.v:154441.7-154441.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 14 $0\mul_op__fn_unit$next[13:0]$7952
- attribute \src "libresoc.v:155735.3-155736.47"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 14 $0\mul_op__fn_unit$next[13:0]$7900
+ attribute \src "libresoc.v:155399.3-155400.47"
wire width 14 $0\mul_op__fn_unit[13:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 64 $0\mul_op__imm_data__data$next[63:0]$7953
- attribute \src "libresoc.v:155737.3-155738.61"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 64 $0\mul_op__imm_data__data$next[63:0]$7901
+ attribute \src "libresoc.v:155401.3-155402.61"
wire width 64 $0\mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__imm_data__ok$next[0:0]$7954
- attribute \src "libresoc.v:155739.3-155740.57"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__imm_data__ok$next[0:0]$7902
+ attribute \src "libresoc.v:155403.3-155404.57"
wire $0\mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 32 $0\mul_op__insn$next[31:0]$7955
- attribute \src "libresoc.v:155755.3-155756.41"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 32 $0\mul_op__insn$next[31:0]$7903
+ attribute \src "libresoc.v:155419.3-155420.41"
wire width 32 $0\mul_op__insn[31:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 7 $0\mul_op__insn_type$next[6:0]$7956
- attribute \src "libresoc.v:155733.3-155734.51"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 7 $0\mul_op__insn_type$next[6:0]$7904
+ attribute \src "libresoc.v:155397.3-155398.51"
wire width 7 $0\mul_op__insn_type[6:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__is_32bit$next[0:0]$7957
- attribute \src "libresoc.v:155751.3-155752.49"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__is_32bit$next[0:0]$7905
+ attribute \src "libresoc.v:155415.3-155416.49"
wire $0\mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__is_signed$next[0:0]$7958
- attribute \src "libresoc.v:155753.3-155754.51"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__is_signed$next[0:0]$7906
+ attribute \src "libresoc.v:155417.3-155418.51"
wire $0\mul_op__is_signed[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__oe__oe$next[0:0]$7959
- attribute \src "libresoc.v:155745.3-155746.45"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__oe__oe$next[0:0]$7907
+ attribute \src "libresoc.v:155409.3-155410.45"
wire $0\mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__oe__ok$next[0:0]$7960
- attribute \src "libresoc.v:155747.3-155748.45"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__oe__ok$next[0:0]$7908
+ attribute \src "libresoc.v:155411.3-155412.45"
wire $0\mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__rc__ok$next[0:0]$7961
- attribute \src "libresoc.v:155743.3-155744.45"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__rc__ok$next[0:0]$7909
+ attribute \src "libresoc.v:155407.3-155408.45"
wire $0\mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__rc__rc$next[0:0]$7962
- attribute \src "libresoc.v:155741.3-155742.45"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__rc__rc$next[0:0]$7910
+ attribute \src "libresoc.v:155405.3-155406.45"
wire $0\mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $0\mul_op__write_cr0$next[0:0]$7963
- attribute \src "libresoc.v:155749.3-155750.51"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $0\mul_op__write_cr0$next[0:0]$7911
+ attribute \src "libresoc.v:155413.3-155414.51"
wire $0\mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:155857.3-155869.6"
- wire width 2 $0\muxid$next[1:0]$7949
- attribute \src "libresoc.v:155757.3-155758.27"
+ attribute \src "libresoc.v:155521.3-155533.6"
+ wire width 2 $0\muxid$next[1:0]$7897
+ attribute \src "libresoc.v:155421.3-155422.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:155945.3-155957.6"
- wire $0\neg_res$next[0:0]$7992
- attribute \src "libresoc.v:155958.3-155970.6"
- wire $0\neg_res32$next[0:0]$7995
- attribute \src "libresoc.v:155723.3-155724.35"
+ attribute \src "libresoc.v:155609.3-155621.6"
+ wire $0\neg_res$next[0:0]$7940
+ attribute \src "libresoc.v:155622.3-155634.6"
+ wire $0\neg_res32$next[0:0]$7943
+ attribute \src "libresoc.v:155387.3-155388.35"
wire $0\neg_res32[0:0]
- attribute \src "libresoc.v:155725.3-155726.31"
+ attribute \src "libresoc.v:155389.3-155390.31"
wire $0\neg_res[0:0]
- attribute \src "libresoc.v:155839.3-155856.6"
- wire $0\r_busy$next[0:0]$7945
- attribute \src "libresoc.v:155759.3-155760.29"
+ attribute \src "libresoc.v:155503.3-155520.6"
+ wire $0\r_busy$next[0:0]$7893
+ attribute \src "libresoc.v:155423.3-155424.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:155906.3-155918.6"
- wire width 64 $0\ra$next[63:0]$7983
- attribute \src "libresoc.v:155731.3-155732.21"
+ attribute \src "libresoc.v:155570.3-155582.6"
+ wire width 64 $0\ra$next[63:0]$7931
+ attribute \src "libresoc.v:155395.3-155396.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:155919.3-155931.6"
- wire width 64 $0\rb$next[63:0]$7986
- attribute \src "libresoc.v:155729.3-155730.21"
+ attribute \src "libresoc.v:155583.3-155595.6"
+ wire width 64 $0\rb$next[63:0]$7934
+ attribute \src "libresoc.v:155393.3-155394.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:155932.3-155944.6"
- wire $0\xer_so$next[0:0]$7989
- attribute \src "libresoc.v:155727.3-155728.29"
+ attribute \src "libresoc.v:155596.3-155608.6"
+ wire $0\xer_so$next[0:0]$7937
+ attribute \src "libresoc.v:155391.3-155392.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 14 $1\mul_op__fn_unit$next[13:0]$7964
- attribute \src "libresoc.v:155293.14-155293.40"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 14 $1\mul_op__fn_unit$next[13:0]$7912
+ attribute \src "libresoc.v:154957.14-154957.40"
wire width 14 $1\mul_op__fn_unit[13:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 64 $1\mul_op__imm_data__data$next[63:0]$7965
- attribute \src "libresoc.v:155332.14-155332.59"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 64 $1\mul_op__imm_data__data$next[63:0]$7913
+ attribute \src "libresoc.v:154996.14-154996.59"
wire width 64 $1\mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__imm_data__ok$next[0:0]$7966
- attribute \src "libresoc.v:155341.7-155341.34"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__imm_data__ok$next[0:0]$7914
+ attribute \src "libresoc.v:155005.7-155005.34"
wire $1\mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 32 $1\mul_op__insn$next[31:0]$7967
- attribute \src "libresoc.v:155350.14-155350.34"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 32 $1\mul_op__insn$next[31:0]$7915
+ attribute \src "libresoc.v:155014.14-155014.34"
wire width 32 $1\mul_op__insn[31:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 7 $1\mul_op__insn_type$next[6:0]$7968
- attribute \src "libresoc.v:155434.13-155434.38"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 7 $1\mul_op__insn_type$next[6:0]$7916
+ attribute \src "libresoc.v:155098.13-155098.38"
wire width 7 $1\mul_op__insn_type[6:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__is_32bit$next[0:0]$7969
- attribute \src "libresoc.v:155593.7-155593.30"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__is_32bit$next[0:0]$7917
+ attribute \src "libresoc.v:155257.7-155257.30"
wire $1\mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__is_signed$next[0:0]$7970
- attribute \src "libresoc.v:155602.7-155602.31"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__is_signed$next[0:0]$7918
+ attribute \src "libresoc.v:155266.7-155266.31"
wire $1\mul_op__is_signed[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__oe__oe$next[0:0]$7971
- attribute \src "libresoc.v:155611.7-155611.28"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__oe__oe$next[0:0]$7919
+ attribute \src "libresoc.v:155275.7-155275.28"
wire $1\mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__oe__ok$next[0:0]$7972
- attribute \src "libresoc.v:155620.7-155620.28"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__oe__ok$next[0:0]$7920
+ attribute \src "libresoc.v:155284.7-155284.28"
wire $1\mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__rc__ok$next[0:0]$7973
- attribute \src "libresoc.v:155629.7-155629.28"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__rc__ok$next[0:0]$7921
+ attribute \src "libresoc.v:155293.7-155293.28"
wire $1\mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__rc__rc$next[0:0]$7974
- attribute \src "libresoc.v:155638.7-155638.28"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__rc__rc$next[0:0]$7922
+ attribute \src "libresoc.v:155302.7-155302.28"
wire $1\mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $1\mul_op__write_cr0$next[0:0]$7975
- attribute \src "libresoc.v:155647.7-155647.31"
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $1\mul_op__write_cr0$next[0:0]$7923
+ attribute \src "libresoc.v:155311.7-155311.31"
wire $1\mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:155857.3-155869.6"
- wire width 2 $1\muxid$next[1:0]$7950
- attribute \src "libresoc.v:155656.13-155656.25"
+ attribute \src "libresoc.v:155521.3-155533.6"
+ wire width 2 $1\muxid$next[1:0]$7898
+ attribute \src "libresoc.v:155320.13-155320.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:155945.3-155957.6"
- wire $1\neg_res$next[0:0]$7993
- attribute \src "libresoc.v:155958.3-155970.6"
- wire $1\neg_res32$next[0:0]$7996
- attribute \src "libresoc.v:155678.7-155678.23"
+ attribute \src "libresoc.v:155609.3-155621.6"
+ wire $1\neg_res$next[0:0]$7941
+ attribute \src "libresoc.v:155622.3-155634.6"
+ wire $1\neg_res32$next[0:0]$7944
+ attribute \src "libresoc.v:155342.7-155342.23"
wire $1\neg_res32[0:0]
- attribute \src "libresoc.v:155671.7-155671.21"
+ attribute \src "libresoc.v:155335.7-155335.21"
wire $1\neg_res[0:0]
- attribute \src "libresoc.v:155839.3-155856.6"
- wire $1\r_busy$next[0:0]$7946
- attribute \src "libresoc.v:155692.7-155692.20"
+ attribute \src "libresoc.v:155503.3-155520.6"
+ wire $1\r_busy$next[0:0]$7894
+ attribute \src "libresoc.v:155356.7-155356.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:155906.3-155918.6"
- wire width 64 $1\ra$next[63:0]$7984
- attribute \src "libresoc.v:155697.14-155697.39"
+ attribute \src "libresoc.v:155570.3-155582.6"
+ wire width 64 $1\ra$next[63:0]$7932
+ attribute \src "libresoc.v:155361.14-155361.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:155919.3-155931.6"
- wire width 64 $1\rb$next[63:0]$7987
- attribute \src "libresoc.v:155706.14-155706.39"
+ attribute \src "libresoc.v:155583.3-155595.6"
+ wire width 64 $1\rb$next[63:0]$7935
+ attribute \src "libresoc.v:155370.14-155370.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:155932.3-155944.6"
- wire $1\xer_so$next[0:0]$7990
- attribute \src "libresoc.v:155715.7-155715.20"
+ attribute \src "libresoc.v:155596.3-155608.6"
+ wire $1\xer_so$next[0:0]$7938
+ attribute \src "libresoc.v:155379.7-155379.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:155870.3-155905.6"
- wire width 64 $2\mul_op__imm_data__data$next[63:0]$7976
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $2\mul_op__imm_data__ok$next[0:0]$7977
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $2\mul_op__oe__oe$next[0:0]$7978
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $2\mul_op__oe__ok$next[0:0]$7979
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $2\mul_op__rc__ok$next[0:0]$7980
- attribute \src "libresoc.v:155870.3-155905.6"
- wire $2\mul_op__rc__rc$next[0:0]$7981
- attribute \src "libresoc.v:155839.3-155856.6"
- wire $2\r_busy$next[0:0]$7947
- attribute \src "libresoc.v:155722.18-155722.118"
- wire $and$libresoc.v:155722$7924_Y
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire width 64 $2\mul_op__imm_data__data$next[63:0]$7924
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $2\mul_op__imm_data__ok$next[0:0]$7925
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $2\mul_op__oe__oe$next[0:0]$7926
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $2\mul_op__oe__ok$next[0:0]$7927
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $2\mul_op__rc__ok$next[0:0]$7928
+ attribute \src "libresoc.v:155534.3-155569.6"
+ wire $2\mul_op__rc__rc$next[0:0]$7929
+ attribute \src "libresoc.v:155503.3-155520.6"
+ wire $2\r_busy$next[0:0]$7895
+ attribute \src "libresoc.v:155386.18-155386.118"
+ wire $and$libresoc.v:155386$7872_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:154777.7-154777.15"
+ attribute \src "libresoc.v:154441.7-154441.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:155722$7924
+ cell $and $and$libresoc.v:155386$7872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$49
connect \B \p_ready_o
- connect \Y $and$libresoc.v:155722$7924_Y
+ connect \Y $and$libresoc.v:155386$7872_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155761.14-155794.4"
+ attribute \src "libresoc.v:155425.14-155458.4"
cell \input$95 \input
connect \mul_op__fn_unit \input_mul_op__fn_unit
connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19
connect \xer_so$16 \input_xer_so$32
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155795.8-155830.4"
+ attribute \src "libresoc.v:155459.8-155494.4"
cell \mul1 \mul1
connect \mul_op__fn_unit \mul1_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35
connect \xer_so$16 \mul1_xer_so$48
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155831.10-155834.4"
+ attribute \src "libresoc.v:155495.10-155498.4"
cell \n$94 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155835.10-155838.4"
+ attribute \src "libresoc.v:155499.10-155502.4"
cell \p$93 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:154777.7-154777.20"
- process $proc$libresoc.v:154777$7997
+ attribute \src "libresoc.v:154441.7-154441.20"
+ process $proc$libresoc.v:154441$7945
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:155293.14-155293.40"
- process $proc$libresoc.v:155293$7998
+ attribute \src "libresoc.v:154957.14-154957.40"
+ process $proc$libresoc.v:154957$7946
assign { } { }
assign $1\mul_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \mul_op__fn_unit $1\mul_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:155332.14-155332.59"
- process $proc$libresoc.v:155332$7999
+ attribute \src "libresoc.v:154996.14-154996.59"
+ process $proc$libresoc.v:154996$7947
assign { } { }
assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:155341.7-155341.34"
- process $proc$libresoc.v:155341$8000
+ attribute \src "libresoc.v:155005.7-155005.34"
+ process $proc$libresoc.v:155005$7948
assign { } { }
assign $1\mul_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:155350.14-155350.34"
- process $proc$libresoc.v:155350$8001
+ attribute \src "libresoc.v:155014.14-155014.34"
+ process $proc$libresoc.v:155014$7949
assign { } { }
assign $1\mul_op__insn[31:0] 0
sync always
sync init
update \mul_op__insn $1\mul_op__insn[31:0]
end
- attribute \src "libresoc.v:155434.13-155434.38"
- process $proc$libresoc.v:155434$8002
+ attribute \src "libresoc.v:155098.13-155098.38"
+ process $proc$libresoc.v:155098$7950
assign { } { }
assign $1\mul_op__insn_type[6:0] 7'0000000
sync always
sync init
update \mul_op__insn_type $1\mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:155593.7-155593.30"
- process $proc$libresoc.v:155593$8003
+ attribute \src "libresoc.v:155257.7-155257.30"
+ process $proc$libresoc.v:155257$7951
assign { } { }
assign $1\mul_op__is_32bit[0:0] 1'0
sync always
sync init
update \mul_op__is_32bit $1\mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:155602.7-155602.31"
- process $proc$libresoc.v:155602$8004
+ attribute \src "libresoc.v:155266.7-155266.31"
+ process $proc$libresoc.v:155266$7952
assign { } { }
assign $1\mul_op__is_signed[0:0] 1'0
sync always
sync init
update \mul_op__is_signed $1\mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:155611.7-155611.28"
- process $proc$libresoc.v:155611$8005
+ attribute \src "libresoc.v:155275.7-155275.28"
+ process $proc$libresoc.v:155275$7953
assign { } { }
assign $1\mul_op__oe__oe[0:0] 1'0
sync always
sync init
update \mul_op__oe__oe $1\mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:155620.7-155620.28"
- process $proc$libresoc.v:155620$8006
+ attribute \src "libresoc.v:155284.7-155284.28"
+ process $proc$libresoc.v:155284$7954
assign { } { }
assign $1\mul_op__oe__ok[0:0] 1'0
sync always
sync init
update \mul_op__oe__ok $1\mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:155629.7-155629.28"
- process $proc$libresoc.v:155629$8007
+ attribute \src "libresoc.v:155293.7-155293.28"
+ process $proc$libresoc.v:155293$7955
assign { } { }
assign $1\mul_op__rc__ok[0:0] 1'0
sync always
sync init
update \mul_op__rc__ok $1\mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:155638.7-155638.28"
- process $proc$libresoc.v:155638$8008
+ attribute \src "libresoc.v:155302.7-155302.28"
+ process $proc$libresoc.v:155302$7956
assign { } { }
assign $1\mul_op__rc__rc[0:0] 1'0
sync always
sync init
update \mul_op__rc__rc $1\mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:155647.7-155647.31"
- process $proc$libresoc.v:155647$8009
+ attribute \src "libresoc.v:155311.7-155311.31"
+ process $proc$libresoc.v:155311$7957
assign { } { }
assign $1\mul_op__write_cr0[0:0] 1'0
sync always
sync init
update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:155656.13-155656.25"
- process $proc$libresoc.v:155656$8010
+ attribute \src "libresoc.v:155320.13-155320.25"
+ process $proc$libresoc.v:155320$7958
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:155671.7-155671.21"
- process $proc$libresoc.v:155671$8011
+ attribute \src "libresoc.v:155335.7-155335.21"
+ process $proc$libresoc.v:155335$7959
assign { } { }
assign $1\neg_res[0:0] 1'0
sync always
sync init
update \neg_res $1\neg_res[0:0]
end
- attribute \src "libresoc.v:155678.7-155678.23"
- process $proc$libresoc.v:155678$8012
+ attribute \src "libresoc.v:155342.7-155342.23"
+ process $proc$libresoc.v:155342$7960
assign { } { }
assign $1\neg_res32[0:0] 1'0
sync always
sync init
update \neg_res32 $1\neg_res32[0:0]
end
- attribute \src "libresoc.v:155692.7-155692.20"
- process $proc$libresoc.v:155692$8013
+ attribute \src "libresoc.v:155356.7-155356.20"
+ process $proc$libresoc.v:155356$7961
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:155697.14-155697.39"
- process $proc$libresoc.v:155697$8014
+ attribute \src "libresoc.v:155361.14-155361.39"
+ process $proc$libresoc.v:155361$7962
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:155706.14-155706.39"
- process $proc$libresoc.v:155706$8015
+ attribute \src "libresoc.v:155370.14-155370.39"
+ process $proc$libresoc.v:155370$7963
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:155715.7-155715.20"
- process $proc$libresoc.v:155715$8016
+ attribute \src "libresoc.v:155379.7-155379.20"
+ process $proc$libresoc.v:155379$7964
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:155723.3-155724.35"
- process $proc$libresoc.v:155723$7925
+ attribute \src "libresoc.v:155387.3-155388.35"
+ process $proc$libresoc.v:155387$7873
assign { } { }
assign $0\neg_res32[0:0] \neg_res32$next
sync posedge \coresync_clk
update \neg_res32 $0\neg_res32[0:0]
end
- attribute \src "libresoc.v:155725.3-155726.31"
- process $proc$libresoc.v:155725$7926
+ attribute \src "libresoc.v:155389.3-155390.31"
+ process $proc$libresoc.v:155389$7874
assign { } { }
assign $0\neg_res[0:0] \neg_res$next
sync posedge \coresync_clk
update \neg_res $0\neg_res[0:0]
end
- attribute \src "libresoc.v:155727.3-155728.29"
- process $proc$libresoc.v:155727$7927
+ attribute \src "libresoc.v:155391.3-155392.29"
+ process $proc$libresoc.v:155391$7875
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:155729.3-155730.21"
- process $proc$libresoc.v:155729$7928
+ attribute \src "libresoc.v:155393.3-155394.21"
+ process $proc$libresoc.v:155393$7876
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:155731.3-155732.21"
- process $proc$libresoc.v:155731$7929
+ attribute \src "libresoc.v:155395.3-155396.21"
+ process $proc$libresoc.v:155395$7877
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:155733.3-155734.51"
- process $proc$libresoc.v:155733$7930
+ attribute \src "libresoc.v:155397.3-155398.51"
+ process $proc$libresoc.v:155397$7878
assign { } { }
assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next
sync posedge \coresync_clk
update \mul_op__insn_type $0\mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:155735.3-155736.47"
- process $proc$libresoc.v:155735$7931
+ attribute \src "libresoc.v:155399.3-155400.47"
+ process $proc$libresoc.v:155399$7879
assign { } { }
assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next
sync posedge \coresync_clk
update \mul_op__fn_unit $0\mul_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:155737.3-155738.61"
- process $proc$libresoc.v:155737$7932
+ attribute \src "libresoc.v:155401.3-155402.61"
+ process $proc$libresoc.v:155401$7880
assign { } { }
assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next
sync posedge \coresync_clk
update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:155739.3-155740.57"
- process $proc$libresoc.v:155739$7933
+ attribute \src "libresoc.v:155403.3-155404.57"
+ process $proc$libresoc.v:155403$7881
assign { } { }
assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next
sync posedge \coresync_clk
update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:155741.3-155742.45"
- process $proc$libresoc.v:155741$7934
+ attribute \src "libresoc.v:155405.3-155406.45"
+ process $proc$libresoc.v:155405$7882
assign { } { }
assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next
sync posedge \coresync_clk
update \mul_op__rc__rc $0\mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:155743.3-155744.45"
- process $proc$libresoc.v:155743$7935
+ attribute \src "libresoc.v:155407.3-155408.45"
+ process $proc$libresoc.v:155407$7883
assign { } { }
assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next
sync posedge \coresync_clk
update \mul_op__rc__ok $0\mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:155745.3-155746.45"
- process $proc$libresoc.v:155745$7936
+ attribute \src "libresoc.v:155409.3-155410.45"
+ process $proc$libresoc.v:155409$7884
assign { } { }
assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next
sync posedge \coresync_clk
update \mul_op__oe__oe $0\mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:155747.3-155748.45"
- process $proc$libresoc.v:155747$7937
+ attribute \src "libresoc.v:155411.3-155412.45"
+ process $proc$libresoc.v:155411$7885
assign { } { }
assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next
sync posedge \coresync_clk
update \mul_op__oe__ok $0\mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:155749.3-155750.51"
- process $proc$libresoc.v:155749$7938
+ attribute \src "libresoc.v:155413.3-155414.51"
+ process $proc$libresoc.v:155413$7886
assign { } { }
assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next
sync posedge \coresync_clk
update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:155751.3-155752.49"
- process $proc$libresoc.v:155751$7939
+ attribute \src "libresoc.v:155415.3-155416.49"
+ process $proc$libresoc.v:155415$7887
assign { } { }
assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next
sync posedge \coresync_clk
update \mul_op__is_32bit $0\mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:155753.3-155754.51"
- process $proc$libresoc.v:155753$7940
+ attribute \src "libresoc.v:155417.3-155418.51"
+ process $proc$libresoc.v:155417$7888
assign { } { }
assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next
sync posedge \coresync_clk
update \mul_op__is_signed $0\mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:155755.3-155756.41"
- process $proc$libresoc.v:155755$7941
+ attribute \src "libresoc.v:155419.3-155420.41"
+ process $proc$libresoc.v:155419$7889
assign { } { }
assign $0\mul_op__insn[31:0] \mul_op__insn$next
sync posedge \coresync_clk
update \mul_op__insn $0\mul_op__insn[31:0]
end
- attribute \src "libresoc.v:155757.3-155758.27"
- process $proc$libresoc.v:155757$7942
+ attribute \src "libresoc.v:155421.3-155422.27"
+ process $proc$libresoc.v:155421$7890
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:155759.3-155760.29"
- process $proc$libresoc.v:155759$7943
+ attribute \src "libresoc.v:155423.3-155424.29"
+ process $proc$libresoc.v:155423$7891
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:155839.3-155856.6"
- process $proc$libresoc.v:155839$7944
+ attribute \src "libresoc.v:155503.3-155520.6"
+ process $proc$libresoc.v:155503$7892
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$7945 $2\r_busy$next[0:0]$7947
- attribute \src "libresoc.v:155840.5-155840.29"
+ assign $0\r_busy$next[0:0]$7893 $2\r_busy$next[0:0]$7895
+ attribute \src "libresoc.v:155504.5-155504.29"
switch \initial
- attribute \src "libresoc.v:155840.9-155840.17"
+ attribute \src "libresoc.v:155504.9-155504.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$7946 1'1
+ assign $1\r_busy$next[0:0]$7894 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$7946 1'0
+ assign $1\r_busy$next[0:0]$7894 1'0
case
- assign $1\r_busy$next[0:0]$7946 \r_busy
+ assign $1\r_busy$next[0:0]$7894 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$7947 1'0
+ assign $2\r_busy$next[0:0]$7895 1'0
case
- assign $2\r_busy$next[0:0]$7947 $1\r_busy$next[0:0]$7946
+ assign $2\r_busy$next[0:0]$7895 $1\r_busy$next[0:0]$7894
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$7945
+ update \r_busy$next $0\r_busy$next[0:0]$7893
end
- attribute \src "libresoc.v:155857.3-155869.6"
- process $proc$libresoc.v:155857$7948
+ attribute \src "libresoc.v:155521.3-155533.6"
+ process $proc$libresoc.v:155521$7896
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$7949 $1\muxid$next[1:0]$7950
- attribute \src "libresoc.v:155858.5-155858.29"
+ assign $0\muxid$next[1:0]$7897 $1\muxid$next[1:0]$7898
+ attribute \src "libresoc.v:155522.5-155522.29"
switch \initial
- attribute \src "libresoc.v:155858.9-155858.17"
+ attribute \src "libresoc.v:155522.9-155522.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$7950 \muxid$52
+ assign $1\muxid$next[1:0]$7898 \muxid$52
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$7950 \muxid$52
+ assign $1\muxid$next[1:0]$7898 \muxid$52
case
- assign $1\muxid$next[1:0]$7950 \muxid
+ assign $1\muxid$next[1:0]$7898 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$7949
+ update \muxid$next $0\muxid$next[1:0]$7897
end
- attribute \src "libresoc.v:155870.3-155905.6"
- process $proc$libresoc.v:155870$7951
+ attribute \src "libresoc.v:155534.3-155569.6"
+ process $proc$libresoc.v:155534$7899
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$next[13:0]$7952 $1\mul_op__fn_unit$next[13:0]$7964
+ assign $0\mul_op__fn_unit$next[13:0]$7900 $1\mul_op__fn_unit$next[13:0]$7912
assign { } { }
assign { } { }
- assign $0\mul_op__insn$next[31:0]$7955 $1\mul_op__insn$next[31:0]$7967
- assign $0\mul_op__insn_type$next[6:0]$7956 $1\mul_op__insn_type$next[6:0]$7968
- assign $0\mul_op__is_32bit$next[0:0]$7957 $1\mul_op__is_32bit$next[0:0]$7969
- assign $0\mul_op__is_signed$next[0:0]$7958 $1\mul_op__is_signed$next[0:0]$7970
+ assign $0\mul_op__insn$next[31:0]$7903 $1\mul_op__insn$next[31:0]$7915
+ assign $0\mul_op__insn_type$next[6:0]$7904 $1\mul_op__insn_type$next[6:0]$7916
+ assign $0\mul_op__is_32bit$next[0:0]$7905 $1\mul_op__is_32bit$next[0:0]$7917
+ assign $0\mul_op__is_signed$next[0:0]$7906 $1\mul_op__is_signed$next[0:0]$7918
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$next[0:0]$7963 $1\mul_op__write_cr0$next[0:0]$7975
- assign $0\mul_op__imm_data__data$next[63:0]$7953 $2\mul_op__imm_data__data$next[63:0]$7976
- assign $0\mul_op__imm_data__ok$next[0:0]$7954 $2\mul_op__imm_data__ok$next[0:0]$7977
- assign $0\mul_op__oe__oe$next[0:0]$7959 $2\mul_op__oe__oe$next[0:0]$7978
- assign $0\mul_op__oe__ok$next[0:0]$7960 $2\mul_op__oe__ok$next[0:0]$7979
- assign $0\mul_op__rc__ok$next[0:0]$7961 $2\mul_op__rc__ok$next[0:0]$7980
- assign $0\mul_op__rc__rc$next[0:0]$7962 $2\mul_op__rc__rc$next[0:0]$7981
- attribute \src "libresoc.v:155871.5-155871.29"
+ assign $0\mul_op__write_cr0$next[0:0]$7911 $1\mul_op__write_cr0$next[0:0]$7923
+ assign $0\mul_op__imm_data__data$next[63:0]$7901 $2\mul_op__imm_data__data$next[63:0]$7924
+ assign $0\mul_op__imm_data__ok$next[0:0]$7902 $2\mul_op__imm_data__ok$next[0:0]$7925
+ assign $0\mul_op__oe__oe$next[0:0]$7907 $2\mul_op__oe__oe$next[0:0]$7926
+ assign $0\mul_op__oe__ok$next[0:0]$7908 $2\mul_op__oe__ok$next[0:0]$7927
+ assign $0\mul_op__rc__ok$next[0:0]$7909 $2\mul_op__rc__ok$next[0:0]$7928
+ assign $0\mul_op__rc__rc$next[0:0]$7910 $2\mul_op__rc__rc$next[0:0]$7929
+ attribute \src "libresoc.v:155535.5-155535.29"
switch \initial
- attribute \src "libresoc.v:155871.9-155871.17"
+ attribute \src "libresoc.v:155535.9-155535.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$next[31:0]$7967 $1\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__oe__ok$next[0:0]$7972 $1\mul_op__oe__oe$next[0:0]$7971 $1\mul_op__rc__ok$next[0:0]$7973 $1\mul_op__rc__rc$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7966 $1\mul_op__imm_data__data$next[63:0]$7965 $1\mul_op__fn_unit$next[13:0]$7964 $1\mul_op__insn_type$next[6:0]$7968 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
+ assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$next[31:0]$7967 $1\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__oe__ok$next[0:0]$7972 $1\mul_op__oe__oe$next[0:0]$7971 $1\mul_op__rc__ok$next[0:0]$7973 $1\mul_op__rc__rc$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7966 $1\mul_op__imm_data__data$next[63:0]$7965 $1\mul_op__fn_unit$next[13:0]$7964 $1\mul_op__insn_type$next[6:0]$7968 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
+ assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
case
- assign $1\mul_op__fn_unit$next[13:0]$7964 \mul_op__fn_unit
- assign $1\mul_op__imm_data__data$next[63:0]$7965 \mul_op__imm_data__data
- assign $1\mul_op__imm_data__ok$next[0:0]$7966 \mul_op__imm_data__ok
- assign $1\mul_op__insn$next[31:0]$7967 \mul_op__insn
- assign $1\mul_op__insn_type$next[6:0]$7968 \mul_op__insn_type
- assign $1\mul_op__is_32bit$next[0:0]$7969 \mul_op__is_32bit
- assign $1\mul_op__is_signed$next[0:0]$7970 \mul_op__is_signed
- assign $1\mul_op__oe__oe$next[0:0]$7971 \mul_op__oe__oe
- assign $1\mul_op__oe__ok$next[0:0]$7972 \mul_op__oe__ok
- assign $1\mul_op__rc__ok$next[0:0]$7973 \mul_op__rc__ok
- assign $1\mul_op__rc__rc$next[0:0]$7974 \mul_op__rc__rc
- assign $1\mul_op__write_cr0$next[0:0]$7975 \mul_op__write_cr0
+ assign $1\mul_op__fn_unit$next[13:0]$7912 \mul_op__fn_unit
+ assign $1\mul_op__imm_data__data$next[63:0]$7913 \mul_op__imm_data__data
+ assign $1\mul_op__imm_data__ok$next[0:0]$7914 \mul_op__imm_data__ok
+ assign $1\mul_op__insn$next[31:0]$7915 \mul_op__insn
+ assign $1\mul_op__insn_type$next[6:0]$7916 \mul_op__insn_type
+ assign $1\mul_op__is_32bit$next[0:0]$7917 \mul_op__is_32bit
+ assign $1\mul_op__is_signed$next[0:0]$7918 \mul_op__is_signed
+ assign $1\mul_op__oe__oe$next[0:0]$7919 \mul_op__oe__oe
+ assign $1\mul_op__oe__ok$next[0:0]$7920 \mul_op__oe__ok
+ assign $1\mul_op__rc__ok$next[0:0]$7921 \mul_op__rc__ok
+ assign $1\mul_op__rc__rc$next[0:0]$7922 \mul_op__rc__rc
+ assign $1\mul_op__write_cr0$next[0:0]$7923 \mul_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$next[63:0]$7976 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$next[0:0]$7977 1'0
- assign $2\mul_op__rc__rc$next[0:0]$7981 1'0
- assign $2\mul_op__rc__ok$next[0:0]$7980 1'0
- assign $2\mul_op__oe__oe$next[0:0]$7978 1'0
- assign $2\mul_op__oe__ok$next[0:0]$7979 1'0
+ assign $2\mul_op__imm_data__data$next[63:0]$7924 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$next[0:0]$7925 1'0
+ assign $2\mul_op__rc__rc$next[0:0]$7929 1'0
+ assign $2\mul_op__rc__ok$next[0:0]$7928 1'0
+ assign $2\mul_op__oe__oe$next[0:0]$7926 1'0
+ assign $2\mul_op__oe__ok$next[0:0]$7927 1'0
case
- assign $2\mul_op__imm_data__data$next[63:0]$7976 $1\mul_op__imm_data__data$next[63:0]$7965
- assign $2\mul_op__imm_data__ok$next[0:0]$7977 $1\mul_op__imm_data__ok$next[0:0]$7966
- assign $2\mul_op__oe__oe$next[0:0]$7978 $1\mul_op__oe__oe$next[0:0]$7971
- assign $2\mul_op__oe__ok$next[0:0]$7979 $1\mul_op__oe__ok$next[0:0]$7972
- assign $2\mul_op__rc__ok$next[0:0]$7980 $1\mul_op__rc__ok$next[0:0]$7973
- assign $2\mul_op__rc__rc$next[0:0]$7981 $1\mul_op__rc__rc$next[0:0]$7974
+ assign $2\mul_op__imm_data__data$next[63:0]$7924 $1\mul_op__imm_data__data$next[63:0]$7913
+ assign $2\mul_op__imm_data__ok$next[0:0]$7925 $1\mul_op__imm_data__ok$next[0:0]$7914
+ assign $2\mul_op__oe__oe$next[0:0]$7926 $1\mul_op__oe__oe$next[0:0]$7919
+ assign $2\mul_op__oe__ok$next[0:0]$7927 $1\mul_op__oe__ok$next[0:0]$7920
+ assign $2\mul_op__rc__ok$next[0:0]$7928 $1\mul_op__rc__ok$next[0:0]$7921
+ assign $2\mul_op__rc__rc$next[0:0]$7929 $1\mul_op__rc__rc$next[0:0]$7922
end
sync always
- update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7952
- update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7953
- update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7954
- update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7955
- update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7956
- update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7957
- update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7958
- update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7959
- update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7960
- update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7961
- update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7962
- update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7963
+ update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7900
+ update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7901
+ update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7902
+ update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7903
+ update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7904
+ update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7905
+ update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7906
+ update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7907
+ update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7908
+ update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7909
+ update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7910
+ update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7911
end
- attribute \src "libresoc.v:155906.3-155918.6"
- process $proc$libresoc.v:155906$7982
+ attribute \src "libresoc.v:155570.3-155582.6"
+ process $proc$libresoc.v:155570$7930
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$7983 $1\ra$next[63:0]$7984
- attribute \src "libresoc.v:155907.5-155907.29"
+ assign $0\ra$next[63:0]$7931 $1\ra$next[63:0]$7932
+ attribute \src "libresoc.v:155571.5-155571.29"
switch \initial
- attribute \src "libresoc.v:155907.9-155907.17"
+ attribute \src "libresoc.v:155571.9-155571.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$7984 \ra$65
+ assign $1\ra$next[63:0]$7932 \ra$65
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$7984 \ra$65
+ assign $1\ra$next[63:0]$7932 \ra$65
case
- assign $1\ra$next[63:0]$7984 \ra
+ assign $1\ra$next[63:0]$7932 \ra
end
sync always
- update \ra$next $0\ra$next[63:0]$7983
+ update \ra$next $0\ra$next[63:0]$7931
end
- attribute \src "libresoc.v:155919.3-155931.6"
- process $proc$libresoc.v:155919$7985
+ attribute \src "libresoc.v:155583.3-155595.6"
+ process $proc$libresoc.v:155583$7933
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$7986 $1\rb$next[63:0]$7987
- attribute \src "libresoc.v:155920.5-155920.29"
+ assign $0\rb$next[63:0]$7934 $1\rb$next[63:0]$7935
+ attribute \src "libresoc.v:155584.5-155584.29"
switch \initial
- attribute \src "libresoc.v:155920.9-155920.17"
+ attribute \src "libresoc.v:155584.9-155584.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$7987 \rb$66
+ assign $1\rb$next[63:0]$7935 \rb$66
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$7987 \rb$66
+ assign $1\rb$next[63:0]$7935 \rb$66
case
- assign $1\rb$next[63:0]$7987 \rb
+ assign $1\rb$next[63:0]$7935 \rb
end
sync always
- update \rb$next $0\rb$next[63:0]$7986
+ update \rb$next $0\rb$next[63:0]$7934
end
- attribute \src "libresoc.v:155932.3-155944.6"
- process $proc$libresoc.v:155932$7988
+ attribute \src "libresoc.v:155596.3-155608.6"
+ process $proc$libresoc.v:155596$7936
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$7989 $1\xer_so$next[0:0]$7990
- attribute \src "libresoc.v:155933.5-155933.29"
+ assign $0\xer_so$next[0:0]$7937 $1\xer_so$next[0:0]$7938
+ attribute \src "libresoc.v:155597.5-155597.29"
switch \initial
- attribute \src "libresoc.v:155933.9-155933.17"
+ attribute \src "libresoc.v:155597.9-155597.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$next[0:0]$7990 \xer_so$67
+ assign $1\xer_so$next[0:0]$7938 \xer_so$67
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$next[0:0]$7990 \xer_so$67
+ assign $1\xer_so$next[0:0]$7938 \xer_so$67
case
- assign $1\xer_so$next[0:0]$7990 \xer_so
+ assign $1\xer_so$next[0:0]$7938 \xer_so
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$7989
+ update \xer_so$next $0\xer_so$next[0:0]$7937
end
- attribute \src "libresoc.v:155945.3-155957.6"
- process $proc$libresoc.v:155945$7991
+ attribute \src "libresoc.v:155609.3-155621.6"
+ process $proc$libresoc.v:155609$7939
assign { } { }
assign { } { }
- assign $0\neg_res$next[0:0]$7992 $1\neg_res$next[0:0]$7993
- attribute \src "libresoc.v:155946.5-155946.29"
+ assign $0\neg_res$next[0:0]$7940 $1\neg_res$next[0:0]$7941
+ attribute \src "libresoc.v:155610.5-155610.29"
switch \initial
- attribute \src "libresoc.v:155946.9-155946.17"
+ attribute \src "libresoc.v:155610.9-155610.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res$next[0:0]$7993 \neg_res$68
+ assign $1\neg_res$next[0:0]$7941 \neg_res$68
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res$next[0:0]$7993 \neg_res$68
+ assign $1\neg_res$next[0:0]$7941 \neg_res$68
case
- assign $1\neg_res$next[0:0]$7993 \neg_res
+ assign $1\neg_res$next[0:0]$7941 \neg_res
end
sync always
- update \neg_res$next $0\neg_res$next[0:0]$7992
+ update \neg_res$next $0\neg_res$next[0:0]$7940
end
- attribute \src "libresoc.v:155958.3-155970.6"
- process $proc$libresoc.v:155958$7994
+ attribute \src "libresoc.v:155622.3-155634.6"
+ process $proc$libresoc.v:155622$7942
assign { } { }
assign { } { }
- assign $0\neg_res32$next[0:0]$7995 $1\neg_res32$next[0:0]$7996
- attribute \src "libresoc.v:155959.5-155959.29"
+ assign $0\neg_res32$next[0:0]$7943 $1\neg_res32$next[0:0]$7944
+ attribute \src "libresoc.v:155623.5-155623.29"
switch \initial
- attribute \src "libresoc.v:155959.9-155959.17"
+ attribute \src "libresoc.v:155623.9-155623.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res32$next[0:0]$7996 \neg_res32$69
+ assign $1\neg_res32$next[0:0]$7944 \neg_res32$69
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res32$next[0:0]$7996 \neg_res32$69
+ assign $1\neg_res32$next[0:0]$7944 \neg_res32$69
case
- assign $1\neg_res32$next[0:0]$7996 \neg_res32
+ assign $1\neg_res32$next[0:0]$7944 \neg_res32
end
sync always
- update \neg_res32$next $0\neg_res32$next[0:0]$7995
+ update \neg_res32$next $0\neg_res32$next[0:0]$7943
end
- connect \$50 $and$libresoc.v:155722$7924_Y
+ connect \$50 $and$libresoc.v:155386$7872_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \neg_res32$69 \mul1_neg_res32
connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:155997.1-156917.10"
+attribute \src "libresoc.v:155661.1-156581.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2"
attribute \generator "nMigen"
module \mul_pipe2
- attribute \src "libresoc.v:155998.7-155998.20"
+ attribute \src "libresoc.v:155662.7-155662.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8060
- attribute \src "libresoc.v:156709.3-156710.53"
- wire width 14 $0\mul_op__fn_unit$3[13:0]$8028
- attribute \src "libresoc.v:156289.14-156289.44"
- wire width 14 $0\mul_op__fn_unit$3[13:0]$8104
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8061
- attribute \src "libresoc.v:156711.3-156712.67"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8030
- attribute \src "libresoc.v:156315.14-156315.63"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8106
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__imm_data__ok$5$next[0:0]$8062
- attribute \src "libresoc.v:156713.3-156714.63"
- wire $0\mul_op__imm_data__ok$5[0:0]$8032
- attribute \src "libresoc.v:156324.7-156324.38"
- wire $0\mul_op__imm_data__ok$5[0:0]$8108
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 32 $0\mul_op__insn$13$next[31:0]$8063
- attribute \src "libresoc.v:156729.3-156730.49"
- wire width 32 $0\mul_op__insn$13[31:0]$8048
- attribute \src "libresoc.v:156331.14-156331.39"
- wire width 32 $0\mul_op__insn$13[31:0]$8110
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 7 $0\mul_op__insn_type$2$next[6:0]$8064
- attribute \src "libresoc.v:156707.3-156708.57"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8026
- attribute \src "libresoc.v:156490.13-156490.42"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8112
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__is_32bit$11$next[0:0]$8065
- attribute \src "libresoc.v:156725.3-156726.57"
- wire $0\mul_op__is_32bit$11[0:0]$8044
- attribute \src "libresoc.v:156574.7-156574.35"
- wire $0\mul_op__is_32bit$11[0:0]$8114
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__is_signed$12$next[0:0]$8066
- attribute \src "libresoc.v:156727.3-156728.59"
- wire $0\mul_op__is_signed$12[0:0]$8046
- attribute \src "libresoc.v:156583.7-156583.36"
- wire $0\mul_op__is_signed$12[0:0]$8116
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__oe__oe$8$next[0:0]$8067
- attribute \src "libresoc.v:156719.3-156720.51"
- wire $0\mul_op__oe__oe$8[0:0]$8038
- attribute \src "libresoc.v:156594.7-156594.32"
- wire $0\mul_op__oe__oe$8[0:0]$8118
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__oe__ok$9$next[0:0]$8068
- attribute \src "libresoc.v:156721.3-156722.51"
- wire $0\mul_op__oe__ok$9[0:0]$8040
- attribute \src "libresoc.v:156603.7-156603.32"
- wire $0\mul_op__oe__ok$9[0:0]$8120
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__rc__ok$7$next[0:0]$8069
- attribute \src "libresoc.v:156717.3-156718.51"
- wire $0\mul_op__rc__ok$7[0:0]$8036
- attribute \src "libresoc.v:156612.7-156612.32"
- wire $0\mul_op__rc__ok$7[0:0]$8122
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__rc__rc$6$next[0:0]$8070
- attribute \src "libresoc.v:156715.3-156716.51"
- wire $0\mul_op__rc__rc$6[0:0]$8034
- attribute \src "libresoc.v:156621.7-156621.32"
- wire $0\mul_op__rc__rc$6[0:0]$8124
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $0\mul_op__write_cr0$10$next[0:0]$8071
- attribute \src "libresoc.v:156723.3-156724.59"
- wire $0\mul_op__write_cr0$10[0:0]$8042
- attribute \src "libresoc.v:156628.7-156628.36"
- wire $0\mul_op__write_cr0$10[0:0]$8126
- attribute \src "libresoc.v:156798.3-156810.6"
- wire width 2 $0\muxid$1$next[1:0]$8057
- attribute \src "libresoc.v:156731.3-156732.33"
- wire width 2 $0\muxid$1[1:0]$8050
- attribute \src "libresoc.v:156637.13-156637.29"
- wire width 2 $0\muxid$1[1:0]$8128
- attribute \src "libresoc.v:156873.3-156885.6"
- wire $0\neg_res$15$next[0:0]$8097
- attribute \src "libresoc.v:156701.3-156702.39"
- wire $0\neg_res$15[0:0]$8021
- attribute \src "libresoc.v:156652.7-156652.26"
- wire $0\neg_res$15[0:0]$8130
- attribute \src "libresoc.v:156886.3-156898.6"
- wire $0\neg_res32$16$next[0:0]$8100
- attribute \src "libresoc.v:156699.3-156700.43"
- wire $0\neg_res32$16[0:0]$8019
- attribute \src "libresoc.v:156661.7-156661.28"
- wire $0\neg_res32$16[0:0]$8132
- attribute \src "libresoc.v:156847.3-156859.6"
- wire width 129 $0\o$next[128:0]$8091
- attribute \src "libresoc.v:156705.3-156706.19"
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8008
+ attribute \src "libresoc.v:156373.3-156374.53"
+ wire width 14 $0\mul_op__fn_unit$3[13:0]$7976
+ attribute \src "libresoc.v:155953.14-155953.44"
+ wire width 14 $0\mul_op__fn_unit$3[13:0]$8052
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8009
+ attribute \src "libresoc.v:156375.3-156376.67"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$7978
+ attribute \src "libresoc.v:155979.14-155979.63"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8054
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__imm_data__ok$5$next[0:0]$8010
+ attribute \src "libresoc.v:156377.3-156378.63"
+ wire $0\mul_op__imm_data__ok$5[0:0]$7980
+ attribute \src "libresoc.v:155988.7-155988.38"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8056
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 32 $0\mul_op__insn$13$next[31:0]$8011
+ attribute \src "libresoc.v:156393.3-156394.49"
+ wire width 32 $0\mul_op__insn$13[31:0]$7996
+ attribute \src "libresoc.v:155995.14-155995.39"
+ wire width 32 $0\mul_op__insn$13[31:0]$8058
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 7 $0\mul_op__insn_type$2$next[6:0]$8012
+ attribute \src "libresoc.v:156371.3-156372.57"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$7974
+ attribute \src "libresoc.v:156154.13-156154.42"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8060
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__is_32bit$11$next[0:0]$8013
+ attribute \src "libresoc.v:156389.3-156390.57"
+ wire $0\mul_op__is_32bit$11[0:0]$7992
+ attribute \src "libresoc.v:156238.7-156238.35"
+ wire $0\mul_op__is_32bit$11[0:0]$8062
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__is_signed$12$next[0:0]$8014
+ attribute \src "libresoc.v:156391.3-156392.59"
+ wire $0\mul_op__is_signed$12[0:0]$7994
+ attribute \src "libresoc.v:156247.7-156247.36"
+ wire $0\mul_op__is_signed$12[0:0]$8064
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__oe__oe$8$next[0:0]$8015
+ attribute \src "libresoc.v:156383.3-156384.51"
+ wire $0\mul_op__oe__oe$8[0:0]$7986
+ attribute \src "libresoc.v:156258.7-156258.32"
+ wire $0\mul_op__oe__oe$8[0:0]$8066
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__oe__ok$9$next[0:0]$8016
+ attribute \src "libresoc.v:156385.3-156386.51"
+ wire $0\mul_op__oe__ok$9[0:0]$7988
+ attribute \src "libresoc.v:156267.7-156267.32"
+ wire $0\mul_op__oe__ok$9[0:0]$8068
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__rc__ok$7$next[0:0]$8017
+ attribute \src "libresoc.v:156381.3-156382.51"
+ wire $0\mul_op__rc__ok$7[0:0]$7984
+ attribute \src "libresoc.v:156276.7-156276.32"
+ wire $0\mul_op__rc__ok$7[0:0]$8070
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__rc__rc$6$next[0:0]$8018
+ attribute \src "libresoc.v:156379.3-156380.51"
+ wire $0\mul_op__rc__rc$6[0:0]$7982
+ attribute \src "libresoc.v:156285.7-156285.32"
+ wire $0\mul_op__rc__rc$6[0:0]$8072
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $0\mul_op__write_cr0$10$next[0:0]$8019
+ attribute \src "libresoc.v:156387.3-156388.59"
+ wire $0\mul_op__write_cr0$10[0:0]$7990
+ attribute \src "libresoc.v:156292.7-156292.36"
+ wire $0\mul_op__write_cr0$10[0:0]$8074
+ attribute \src "libresoc.v:156462.3-156474.6"
+ wire width 2 $0\muxid$1$next[1:0]$8005
+ attribute \src "libresoc.v:156395.3-156396.33"
+ wire width 2 $0\muxid$1[1:0]$7998
+ attribute \src "libresoc.v:156301.13-156301.29"
+ wire width 2 $0\muxid$1[1:0]$8076
+ attribute \src "libresoc.v:156537.3-156549.6"
+ wire $0\neg_res$15$next[0:0]$8045
+ attribute \src "libresoc.v:156365.3-156366.39"
+ wire $0\neg_res$15[0:0]$7969
+ attribute \src "libresoc.v:156316.7-156316.26"
+ wire $0\neg_res$15[0:0]$8078
+ attribute \src "libresoc.v:156550.3-156562.6"
+ wire $0\neg_res32$16$next[0:0]$8048
+ attribute \src "libresoc.v:156363.3-156364.43"
+ wire $0\neg_res32$16[0:0]$7967
+ attribute \src "libresoc.v:156325.7-156325.28"
+ wire $0\neg_res32$16[0:0]$8080
+ attribute \src "libresoc.v:156511.3-156523.6"
+ wire width 129 $0\o$next[128:0]$8039
+ attribute \src "libresoc.v:156369.3-156370.19"
wire width 129 $0\o[128:0]
- attribute \src "libresoc.v:156780.3-156797.6"
- wire $0\r_busy$next[0:0]$8053
- attribute \src "libresoc.v:156733.3-156734.29"
+ attribute \src "libresoc.v:156444.3-156461.6"
+ wire $0\r_busy$next[0:0]$8001
+ attribute \src "libresoc.v:156397.3-156398.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:156860.3-156872.6"
- wire $0\xer_so$14$next[0:0]$8094
- attribute \src "libresoc.v:156703.3-156704.37"
- wire $0\xer_so$14[0:0]$8023
- attribute \src "libresoc.v:156693.7-156693.25"
- wire $0\xer_so$14[0:0]$8136
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8072
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8073
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__imm_data__ok$5$next[0:0]$8074
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 32 $1\mul_op__insn$13$next[31:0]$8075
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 7 $1\mul_op__insn_type$2$next[6:0]$8076
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__is_32bit$11$next[0:0]$8077
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__is_signed$12$next[0:0]$8078
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__oe__oe$8$next[0:0]$8079
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__oe__ok$9$next[0:0]$8080
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__rc__ok$7$next[0:0]$8081
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__rc__rc$6$next[0:0]$8082
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $1\mul_op__write_cr0$10$next[0:0]$8083
- attribute \src "libresoc.v:156798.3-156810.6"
- wire width 2 $1\muxid$1$next[1:0]$8058
- attribute \src "libresoc.v:156873.3-156885.6"
- wire $1\neg_res$15$next[0:0]$8098
- attribute \src "libresoc.v:156886.3-156898.6"
- wire $1\neg_res32$16$next[0:0]$8101
- attribute \src "libresoc.v:156847.3-156859.6"
- wire width 129 $1\o$next[128:0]$8092
- attribute \src "libresoc.v:156668.15-156668.57"
+ attribute \src "libresoc.v:156524.3-156536.6"
+ wire $0\xer_so$14$next[0:0]$8042
+ attribute \src "libresoc.v:156367.3-156368.37"
+ wire $0\xer_so$14[0:0]$7971
+ attribute \src "libresoc.v:156357.7-156357.25"
+ wire $0\xer_so$14[0:0]$8084
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8020
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8021
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__imm_data__ok$5$next[0:0]$8022
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 32 $1\mul_op__insn$13$next[31:0]$8023
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 7 $1\mul_op__insn_type$2$next[6:0]$8024
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__is_32bit$11$next[0:0]$8025
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__is_signed$12$next[0:0]$8026
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__oe__oe$8$next[0:0]$8027
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__oe__ok$9$next[0:0]$8028
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__rc__ok$7$next[0:0]$8029
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__rc__rc$6$next[0:0]$8030
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $1\mul_op__write_cr0$10$next[0:0]$8031
+ attribute \src "libresoc.v:156462.3-156474.6"
+ wire width 2 $1\muxid$1$next[1:0]$8006
+ attribute \src "libresoc.v:156537.3-156549.6"
+ wire $1\neg_res$15$next[0:0]$8046
+ attribute \src "libresoc.v:156550.3-156562.6"
+ wire $1\neg_res32$16$next[0:0]$8049
+ attribute \src "libresoc.v:156511.3-156523.6"
+ wire width 129 $1\o$next[128:0]$8040
+ attribute \src "libresoc.v:156332.15-156332.57"
wire width 129 $1\o[128:0]
- attribute \src "libresoc.v:156780.3-156797.6"
- wire $1\r_busy$next[0:0]$8054
- attribute \src "libresoc.v:156682.7-156682.20"
+ attribute \src "libresoc.v:156444.3-156461.6"
+ wire $1\r_busy$next[0:0]$8002
+ attribute \src "libresoc.v:156346.7-156346.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:156860.3-156872.6"
- wire $1\xer_so$14$next[0:0]$8095
- attribute \src "libresoc.v:156811.3-156846.6"
- wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8084
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $2\mul_op__imm_data__ok$5$next[0:0]$8085
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $2\mul_op__oe__oe$8$next[0:0]$8086
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $2\mul_op__oe__ok$9$next[0:0]$8087
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $2\mul_op__rc__ok$7$next[0:0]$8088
- attribute \src "libresoc.v:156811.3-156846.6"
- wire $2\mul_op__rc__rc$6$next[0:0]$8089
- attribute \src "libresoc.v:156780.3-156797.6"
- wire $2\r_busy$next[0:0]$8055
- attribute \src "libresoc.v:156698.18-156698.118"
- wire $and$libresoc.v:156698$8017_Y
+ attribute \src "libresoc.v:156524.3-156536.6"
+ wire $1\xer_so$14$next[0:0]$8043
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8032
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $2\mul_op__imm_data__ok$5$next[0:0]$8033
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $2\mul_op__oe__oe$8$next[0:0]$8034
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $2\mul_op__oe__ok$9$next[0:0]$8035
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $2\mul_op__rc__ok$7$next[0:0]$8036
+ attribute \src "libresoc.v:156475.3-156510.6"
+ wire $2\mul_op__rc__rc$6$next[0:0]$8037
+ attribute \src "libresoc.v:156444.3-156461.6"
+ wire $2\r_busy$next[0:0]$8003
+ attribute \src "libresoc.v:156362.18-156362.118"
+ wire $and$libresoc.v:156362$7965_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:155998.7-155998.15"
+ attribute \src "libresoc.v:155662.7-155662.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$50
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:156698$8017
+ cell $and $and$libresoc.v:156362$7965
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$33
connect \B \p_ready_o
- connect \Y $and$libresoc.v:156698$8017_Y
+ connect \Y $and$libresoc.v:156362$7965_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:156735.8-156771.4"
+ attribute \src "libresoc.v:156399.8-156435.4"
cell \mul2 \mul2
connect \mul_op__fn_unit \mul2_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19
connect \xer_so$14 \mul2_xer_so$30
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:156772.10-156775.4"
+ attribute \src "libresoc.v:156436.10-156439.4"
cell \n$97 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:156776.10-156779.4"
+ attribute \src "libresoc.v:156440.10-156443.4"
cell \p$96 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:155998.7-155998.20"
- process $proc$libresoc.v:155998$8102
+ attribute \src "libresoc.v:155662.7-155662.20"
+ process $proc$libresoc.v:155662$8050
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156289.14-156289.44"
- process $proc$libresoc.v:156289$8103
+ attribute \src "libresoc.v:155953.14-155953.44"
+ process $proc$libresoc.v:155953$8051
assign { } { }
- assign $0\mul_op__fn_unit$3[13:0]$8104 14'00000000000000
+ assign $0\mul_op__fn_unit$3[13:0]$8052 14'00000000000000
sync always
sync init
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8104
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8052
end
- attribute \src "libresoc.v:156315.14-156315.63"
- process $proc$libresoc.v:156315$8105
+ attribute \src "libresoc.v:155979.14-155979.63"
+ process $proc$libresoc.v:155979$8053
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8106 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\mul_op__imm_data__data$4[63:0]$8054 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8106
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8054
end
- attribute \src "libresoc.v:156324.7-156324.38"
- process $proc$libresoc.v:156324$8107
+ attribute \src "libresoc.v:155988.7-155988.38"
+ process $proc$libresoc.v:155988$8055
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8108 1'0
+ assign $0\mul_op__imm_data__ok$5[0:0]$8056 1'0
sync always
sync init
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8108
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8056
end
- attribute \src "libresoc.v:156331.14-156331.39"
- process $proc$libresoc.v:156331$8109
+ attribute \src "libresoc.v:155995.14-155995.39"
+ process $proc$libresoc.v:155995$8057
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8110 0
+ assign $0\mul_op__insn$13[31:0]$8058 0
sync always
sync init
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8110
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8058
end
- attribute \src "libresoc.v:156490.13-156490.42"
- process $proc$libresoc.v:156490$8111
+ attribute \src "libresoc.v:156154.13-156154.42"
+ process $proc$libresoc.v:156154$8059
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8112 7'0000000
+ assign $0\mul_op__insn_type$2[6:0]$8060 7'0000000
sync always
sync init
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8112
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8060
end
- attribute \src "libresoc.v:156574.7-156574.35"
- process $proc$libresoc.v:156574$8113
+ attribute \src "libresoc.v:156238.7-156238.35"
+ process $proc$libresoc.v:156238$8061
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8114 1'0
+ assign $0\mul_op__is_32bit$11[0:0]$8062 1'0
sync always
sync init
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8114
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8062
end
- attribute \src "libresoc.v:156583.7-156583.36"
- process $proc$libresoc.v:156583$8115
+ attribute \src "libresoc.v:156247.7-156247.36"
+ process $proc$libresoc.v:156247$8063
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8116 1'0
+ assign $0\mul_op__is_signed$12[0:0]$8064 1'0
sync always
sync init
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8116
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8064
end
- attribute \src "libresoc.v:156594.7-156594.32"
- process $proc$libresoc.v:156594$8117
+ attribute \src "libresoc.v:156258.7-156258.32"
+ process $proc$libresoc.v:156258$8065
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8118 1'0
+ assign $0\mul_op__oe__oe$8[0:0]$8066 1'0
sync always
sync init
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8118
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8066
end
- attribute \src "libresoc.v:156603.7-156603.32"
- process $proc$libresoc.v:156603$8119
+ attribute \src "libresoc.v:156267.7-156267.32"
+ process $proc$libresoc.v:156267$8067
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8120 1'0
+ assign $0\mul_op__oe__ok$9[0:0]$8068 1'0
sync always
sync init
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8120
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8068
end
- attribute \src "libresoc.v:156612.7-156612.32"
- process $proc$libresoc.v:156612$8121
+ attribute \src "libresoc.v:156276.7-156276.32"
+ process $proc$libresoc.v:156276$8069
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8122 1'0
+ assign $0\mul_op__rc__ok$7[0:0]$8070 1'0
sync always
sync init
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8122
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8070
end
- attribute \src "libresoc.v:156621.7-156621.32"
- process $proc$libresoc.v:156621$8123
+ attribute \src "libresoc.v:156285.7-156285.32"
+ process $proc$libresoc.v:156285$8071
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8124 1'0
+ assign $0\mul_op__rc__rc$6[0:0]$8072 1'0
sync always
sync init
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8124
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8072
end
- attribute \src "libresoc.v:156628.7-156628.36"
- process $proc$libresoc.v:156628$8125
+ attribute \src "libresoc.v:156292.7-156292.36"
+ process $proc$libresoc.v:156292$8073
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8126 1'0
+ assign $0\mul_op__write_cr0$10[0:0]$8074 1'0
sync always
sync init
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8126
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8074
end
- attribute \src "libresoc.v:156637.13-156637.29"
- process $proc$libresoc.v:156637$8127
+ attribute \src "libresoc.v:156301.13-156301.29"
+ process $proc$libresoc.v:156301$8075
assign { } { }
- assign $0\muxid$1[1:0]$8128 2'00
+ assign $0\muxid$1[1:0]$8076 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8128
+ update \muxid$1 $0\muxid$1[1:0]$8076
end
- attribute \src "libresoc.v:156652.7-156652.26"
- process $proc$libresoc.v:156652$8129
+ attribute \src "libresoc.v:156316.7-156316.26"
+ process $proc$libresoc.v:156316$8077
assign { } { }
- assign $0\neg_res$15[0:0]$8130 1'0
+ assign $0\neg_res$15[0:0]$8078 1'0
sync always
sync init
- update \neg_res$15 $0\neg_res$15[0:0]$8130
+ update \neg_res$15 $0\neg_res$15[0:0]$8078
end
- attribute \src "libresoc.v:156661.7-156661.28"
- process $proc$libresoc.v:156661$8131
+ attribute \src "libresoc.v:156325.7-156325.28"
+ process $proc$libresoc.v:156325$8079
assign { } { }
- assign $0\neg_res32$16[0:0]$8132 1'0
+ assign $0\neg_res32$16[0:0]$8080 1'0
sync always
sync init
- update \neg_res32$16 $0\neg_res32$16[0:0]$8132
+ update \neg_res32$16 $0\neg_res32$16[0:0]$8080
end
- attribute \src "libresoc.v:156668.15-156668.57"
- process $proc$libresoc.v:156668$8133
+ attribute \src "libresoc.v:156332.15-156332.57"
+ process $proc$libresoc.v:156332$8081
assign { } { }
assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[128:0]
end
- attribute \src "libresoc.v:156682.7-156682.20"
- process $proc$libresoc.v:156682$8134
+ attribute \src "libresoc.v:156346.7-156346.20"
+ process $proc$libresoc.v:156346$8082
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:156693.7-156693.25"
- process $proc$libresoc.v:156693$8135
+ attribute \src "libresoc.v:156357.7-156357.25"
+ process $proc$libresoc.v:156357$8083
assign { } { }
- assign $0\xer_so$14[0:0]$8136 1'0
+ assign $0\xer_so$14[0:0]$8084 1'0
sync always
sync init
- update \xer_so$14 $0\xer_so$14[0:0]$8136
+ update \xer_so$14 $0\xer_so$14[0:0]$8084
end
- attribute \src "libresoc.v:156699.3-156700.43"
- process $proc$libresoc.v:156699$8018
+ attribute \src "libresoc.v:156363.3-156364.43"
+ process $proc$libresoc.v:156363$7966
assign { } { }
- assign $0\neg_res32$16[0:0]$8019 \neg_res32$16$next
+ assign $0\neg_res32$16[0:0]$7967 \neg_res32$16$next
sync posedge \coresync_clk
- update \neg_res32$16 $0\neg_res32$16[0:0]$8019
+ update \neg_res32$16 $0\neg_res32$16[0:0]$7967
end
- attribute \src "libresoc.v:156701.3-156702.39"
- process $proc$libresoc.v:156701$8020
+ attribute \src "libresoc.v:156365.3-156366.39"
+ process $proc$libresoc.v:156365$7968
assign { } { }
- assign $0\neg_res$15[0:0]$8021 \neg_res$15$next
+ assign $0\neg_res$15[0:0]$7969 \neg_res$15$next
sync posedge \coresync_clk
- update \neg_res$15 $0\neg_res$15[0:0]$8021
+ update \neg_res$15 $0\neg_res$15[0:0]$7969
end
- attribute \src "libresoc.v:156703.3-156704.37"
- process $proc$libresoc.v:156703$8022
+ attribute \src "libresoc.v:156367.3-156368.37"
+ process $proc$libresoc.v:156367$7970
assign { } { }
- assign $0\xer_so$14[0:0]$8023 \xer_so$14$next
+ assign $0\xer_so$14[0:0]$7971 \xer_so$14$next
sync posedge \coresync_clk
- update \xer_so$14 $0\xer_so$14[0:0]$8023
+ update \xer_so$14 $0\xer_so$14[0:0]$7971
end
- attribute \src "libresoc.v:156705.3-156706.19"
- process $proc$libresoc.v:156705$8024
+ attribute \src "libresoc.v:156369.3-156370.19"
+ process $proc$libresoc.v:156369$7972
assign { } { }
assign $0\o[128:0] \o$next
sync posedge \coresync_clk
update \o $0\o[128:0]
end
- attribute \src "libresoc.v:156707.3-156708.57"
- process $proc$libresoc.v:156707$8025
+ attribute \src "libresoc.v:156371.3-156372.57"
+ process $proc$libresoc.v:156371$7973
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8026 \mul_op__insn_type$2$next
+ assign $0\mul_op__insn_type$2[6:0]$7974 \mul_op__insn_type$2$next
sync posedge \coresync_clk
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8026
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7974
end
- attribute \src "libresoc.v:156709.3-156710.53"
- process $proc$libresoc.v:156709$8027
+ attribute \src "libresoc.v:156373.3-156374.53"
+ process $proc$libresoc.v:156373$7975
assign { } { }
- assign $0\mul_op__fn_unit$3[13:0]$8028 \mul_op__fn_unit$3$next
+ assign $0\mul_op__fn_unit$3[13:0]$7976 \mul_op__fn_unit$3$next
sync posedge \coresync_clk
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8028
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7976
end
- attribute \src "libresoc.v:156711.3-156712.67"
- process $proc$libresoc.v:156711$8029
+ attribute \src "libresoc.v:156375.3-156376.67"
+ process $proc$libresoc.v:156375$7977
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8030 \mul_op__imm_data__data$4$next
+ assign $0\mul_op__imm_data__data$4[63:0]$7978 \mul_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8030
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7978
end
- attribute \src "libresoc.v:156713.3-156714.63"
- process $proc$libresoc.v:156713$8031
+ attribute \src "libresoc.v:156377.3-156378.63"
+ process $proc$libresoc.v:156377$7979
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8032 \mul_op__imm_data__ok$5$next
+ assign $0\mul_op__imm_data__ok$5[0:0]$7980 \mul_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8032
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7980
end
- attribute \src "libresoc.v:156715.3-156716.51"
- process $proc$libresoc.v:156715$8033
+ attribute \src "libresoc.v:156379.3-156380.51"
+ process $proc$libresoc.v:156379$7981
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8034 \mul_op__rc__rc$6$next
+ assign $0\mul_op__rc__rc$6[0:0]$7982 \mul_op__rc__rc$6$next
sync posedge \coresync_clk
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8034
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7982
end
- attribute \src "libresoc.v:156717.3-156718.51"
- process $proc$libresoc.v:156717$8035
+ attribute \src "libresoc.v:156381.3-156382.51"
+ process $proc$libresoc.v:156381$7983
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8036 \mul_op__rc__ok$7$next
+ assign $0\mul_op__rc__ok$7[0:0]$7984 \mul_op__rc__ok$7$next
sync posedge \coresync_clk
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8036
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7984
end
- attribute \src "libresoc.v:156719.3-156720.51"
- process $proc$libresoc.v:156719$8037
+ attribute \src "libresoc.v:156383.3-156384.51"
+ process $proc$libresoc.v:156383$7985
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8038 \mul_op__oe__oe$8$next
+ assign $0\mul_op__oe__oe$8[0:0]$7986 \mul_op__oe__oe$8$next
sync posedge \coresync_clk
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8038
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7986
end
- attribute \src "libresoc.v:156721.3-156722.51"
- process $proc$libresoc.v:156721$8039
+ attribute \src "libresoc.v:156385.3-156386.51"
+ process $proc$libresoc.v:156385$7987
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8040 \mul_op__oe__ok$9$next
+ assign $0\mul_op__oe__ok$9[0:0]$7988 \mul_op__oe__ok$9$next
sync posedge \coresync_clk
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8040
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7988
end
- attribute \src "libresoc.v:156723.3-156724.59"
- process $proc$libresoc.v:156723$8041
+ attribute \src "libresoc.v:156387.3-156388.59"
+ process $proc$libresoc.v:156387$7989
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8042 \mul_op__write_cr0$10$next
+ assign $0\mul_op__write_cr0$10[0:0]$7990 \mul_op__write_cr0$10$next
sync posedge \coresync_clk
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8042
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7990
end
- attribute \src "libresoc.v:156725.3-156726.57"
- process $proc$libresoc.v:156725$8043
+ attribute \src "libresoc.v:156389.3-156390.57"
+ process $proc$libresoc.v:156389$7991
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8044 \mul_op__is_32bit$11$next
+ assign $0\mul_op__is_32bit$11[0:0]$7992 \mul_op__is_32bit$11$next
sync posedge \coresync_clk
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8044
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7992
end
- attribute \src "libresoc.v:156727.3-156728.59"
- process $proc$libresoc.v:156727$8045
+ attribute \src "libresoc.v:156391.3-156392.59"
+ process $proc$libresoc.v:156391$7993
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8046 \mul_op__is_signed$12$next
+ assign $0\mul_op__is_signed$12[0:0]$7994 \mul_op__is_signed$12$next
sync posedge \coresync_clk
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8046
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7994
end
- attribute \src "libresoc.v:156729.3-156730.49"
- process $proc$libresoc.v:156729$8047
+ attribute \src "libresoc.v:156393.3-156394.49"
+ process $proc$libresoc.v:156393$7995
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8048 \mul_op__insn$13$next
+ assign $0\mul_op__insn$13[31:0]$7996 \mul_op__insn$13$next
sync posedge \coresync_clk
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8048
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7996
end
- attribute \src "libresoc.v:156731.3-156732.33"
- process $proc$libresoc.v:156731$8049
+ attribute \src "libresoc.v:156395.3-156396.33"
+ process $proc$libresoc.v:156395$7997
assign { } { }
- assign $0\muxid$1[1:0]$8050 \muxid$1$next
+ assign $0\muxid$1[1:0]$7998 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8050
+ update \muxid$1 $0\muxid$1[1:0]$7998
end
- attribute \src "libresoc.v:156733.3-156734.29"
- process $proc$libresoc.v:156733$8051
+ attribute \src "libresoc.v:156397.3-156398.29"
+ process $proc$libresoc.v:156397$7999
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:156780.3-156797.6"
- process $proc$libresoc.v:156780$8052
+ attribute \src "libresoc.v:156444.3-156461.6"
+ process $proc$libresoc.v:156444$8000
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8053 $2\r_busy$next[0:0]$8055
- attribute \src "libresoc.v:156781.5-156781.29"
+ assign $0\r_busy$next[0:0]$8001 $2\r_busy$next[0:0]$8003
+ attribute \src "libresoc.v:156445.5-156445.29"
switch \initial
- attribute \src "libresoc.v:156781.9-156781.17"
+ attribute \src "libresoc.v:156445.9-156445.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8054 1'1
+ assign $1\r_busy$next[0:0]$8002 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8054 1'0
+ assign $1\r_busy$next[0:0]$8002 1'0
case
- assign $1\r_busy$next[0:0]$8054 \r_busy
+ assign $1\r_busy$next[0:0]$8002 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8055 1'0
+ assign $2\r_busy$next[0:0]$8003 1'0
case
- assign $2\r_busy$next[0:0]$8055 $1\r_busy$next[0:0]$8054
+ assign $2\r_busy$next[0:0]$8003 $1\r_busy$next[0:0]$8002
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8053
+ update \r_busy$next $0\r_busy$next[0:0]$8001
end
- attribute \src "libresoc.v:156798.3-156810.6"
- process $proc$libresoc.v:156798$8056
+ attribute \src "libresoc.v:156462.3-156474.6"
+ process $proc$libresoc.v:156462$8004
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8057 $1\muxid$1$next[1:0]$8058
- attribute \src "libresoc.v:156799.5-156799.29"
+ assign $0\muxid$1$next[1:0]$8005 $1\muxid$1$next[1:0]$8006
+ attribute \src "libresoc.v:156463.5-156463.29"
switch \initial
- attribute \src "libresoc.v:156799.9-156799.17"
+ attribute \src "libresoc.v:156463.9-156463.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8058 \muxid$36
+ assign $1\muxid$1$next[1:0]$8006 \muxid$36
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8058 \muxid$36
+ assign $1\muxid$1$next[1:0]$8006 \muxid$36
case
- assign $1\muxid$1$next[1:0]$8058 \muxid$1
+ assign $1\muxid$1$next[1:0]$8006 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8057
+ update \muxid$1$next $0\muxid$1$next[1:0]$8005
end
- attribute \src "libresoc.v:156811.3-156846.6"
- process $proc$libresoc.v:156811$8059
+ attribute \src "libresoc.v:156475.3-156510.6"
+ process $proc$libresoc.v:156475$8007
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$3$next[13:0]$8060 $1\mul_op__fn_unit$3$next[13:0]$8072
+ assign $0\mul_op__fn_unit$3$next[13:0]$8008 $1\mul_op__fn_unit$3$next[13:0]$8020
assign { } { }
assign { } { }
- assign $0\mul_op__insn$13$next[31:0]$8063 $1\mul_op__insn$13$next[31:0]$8075
- assign $0\mul_op__insn_type$2$next[6:0]$8064 $1\mul_op__insn_type$2$next[6:0]$8076
- assign $0\mul_op__is_32bit$11$next[0:0]$8065 $1\mul_op__is_32bit$11$next[0:0]$8077
- assign $0\mul_op__is_signed$12$next[0:0]$8066 $1\mul_op__is_signed$12$next[0:0]$8078
+ assign $0\mul_op__insn$13$next[31:0]$8011 $1\mul_op__insn$13$next[31:0]$8023
+ assign $0\mul_op__insn_type$2$next[6:0]$8012 $1\mul_op__insn_type$2$next[6:0]$8024
+ assign $0\mul_op__is_32bit$11$next[0:0]$8013 $1\mul_op__is_32bit$11$next[0:0]$8025
+ assign $0\mul_op__is_signed$12$next[0:0]$8014 $1\mul_op__is_signed$12$next[0:0]$8026
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$10$next[0:0]$8071 $1\mul_op__write_cr0$10$next[0:0]$8083
- assign $0\mul_op__imm_data__data$4$next[63:0]$8061 $2\mul_op__imm_data__data$4$next[63:0]$8084
- assign $0\mul_op__imm_data__ok$5$next[0:0]$8062 $2\mul_op__imm_data__ok$5$next[0:0]$8085
- assign $0\mul_op__oe__oe$8$next[0:0]$8067 $2\mul_op__oe__oe$8$next[0:0]$8086
- assign $0\mul_op__oe__ok$9$next[0:0]$8068 $2\mul_op__oe__ok$9$next[0:0]$8087
- assign $0\mul_op__rc__ok$7$next[0:0]$8069 $2\mul_op__rc__ok$7$next[0:0]$8088
- assign $0\mul_op__rc__rc$6$next[0:0]$8070 $2\mul_op__rc__rc$6$next[0:0]$8089
- attribute \src "libresoc.v:156812.5-156812.29"
+ assign $0\mul_op__write_cr0$10$next[0:0]$8019 $1\mul_op__write_cr0$10$next[0:0]$8031
+ assign $0\mul_op__imm_data__data$4$next[63:0]$8009 $2\mul_op__imm_data__data$4$next[63:0]$8032
+ assign $0\mul_op__imm_data__ok$5$next[0:0]$8010 $2\mul_op__imm_data__ok$5$next[0:0]$8033
+ assign $0\mul_op__oe__oe$8$next[0:0]$8015 $2\mul_op__oe__oe$8$next[0:0]$8034
+ assign $0\mul_op__oe__ok$9$next[0:0]$8016 $2\mul_op__oe__ok$9$next[0:0]$8035
+ assign $0\mul_op__rc__ok$7$next[0:0]$8017 $2\mul_op__rc__ok$7$next[0:0]$8036
+ assign $0\mul_op__rc__rc$6$next[0:0]$8018 $2\mul_op__rc__rc$6$next[0:0]$8037
+ attribute \src "libresoc.v:156476.5-156476.29"
switch \initial
- attribute \src "libresoc.v:156812.9-156812.17"
+ attribute \src "libresoc.v:156476.9-156476.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8075 $1\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__oe__ok$9$next[0:0]$8080 $1\mul_op__oe__oe$8$next[0:0]$8079 $1\mul_op__rc__ok$7$next[0:0]$8081 $1\mul_op__rc__rc$6$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8074 $1\mul_op__imm_data__data$4$next[63:0]$8073 $1\mul_op__fn_unit$3$next[13:0]$8072 $1\mul_op__insn_type$2$next[6:0]$8076 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
+ assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8075 $1\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__oe__ok$9$next[0:0]$8080 $1\mul_op__oe__oe$8$next[0:0]$8079 $1\mul_op__rc__ok$7$next[0:0]$8081 $1\mul_op__rc__rc$6$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8074 $1\mul_op__imm_data__data$4$next[63:0]$8073 $1\mul_op__fn_unit$3$next[13:0]$8072 $1\mul_op__insn_type$2$next[6:0]$8076 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
+ assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
case
- assign $1\mul_op__fn_unit$3$next[13:0]$8072 \mul_op__fn_unit$3
- assign $1\mul_op__imm_data__data$4$next[63:0]$8073 \mul_op__imm_data__data$4
- assign $1\mul_op__imm_data__ok$5$next[0:0]$8074 \mul_op__imm_data__ok$5
- assign $1\mul_op__insn$13$next[31:0]$8075 \mul_op__insn$13
- assign $1\mul_op__insn_type$2$next[6:0]$8076 \mul_op__insn_type$2
- assign $1\mul_op__is_32bit$11$next[0:0]$8077 \mul_op__is_32bit$11
- assign $1\mul_op__is_signed$12$next[0:0]$8078 \mul_op__is_signed$12
- assign $1\mul_op__oe__oe$8$next[0:0]$8079 \mul_op__oe__oe$8
- assign $1\mul_op__oe__ok$9$next[0:0]$8080 \mul_op__oe__ok$9
- assign $1\mul_op__rc__ok$7$next[0:0]$8081 \mul_op__rc__ok$7
- assign $1\mul_op__rc__rc$6$next[0:0]$8082 \mul_op__rc__rc$6
- assign $1\mul_op__write_cr0$10$next[0:0]$8083 \mul_op__write_cr0$10
+ assign $1\mul_op__fn_unit$3$next[13:0]$8020 \mul_op__fn_unit$3
+ assign $1\mul_op__imm_data__data$4$next[63:0]$8021 \mul_op__imm_data__data$4
+ assign $1\mul_op__imm_data__ok$5$next[0:0]$8022 \mul_op__imm_data__ok$5
+ assign $1\mul_op__insn$13$next[31:0]$8023 \mul_op__insn$13
+ assign $1\mul_op__insn_type$2$next[6:0]$8024 \mul_op__insn_type$2
+ assign $1\mul_op__is_32bit$11$next[0:0]$8025 \mul_op__is_32bit$11
+ assign $1\mul_op__is_signed$12$next[0:0]$8026 \mul_op__is_signed$12
+ assign $1\mul_op__oe__oe$8$next[0:0]$8027 \mul_op__oe__oe$8
+ assign $1\mul_op__oe__ok$9$next[0:0]$8028 \mul_op__oe__ok$9
+ assign $1\mul_op__rc__ok$7$next[0:0]$8029 \mul_op__rc__ok$7
+ assign $1\mul_op__rc__rc$6$next[0:0]$8030 \mul_op__rc__rc$6
+ assign $1\mul_op__write_cr0$10$next[0:0]$8031 \mul_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$4$next[63:0]$8084 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8085 1'0
- assign $2\mul_op__rc__rc$6$next[0:0]$8089 1'0
- assign $2\mul_op__rc__ok$7$next[0:0]$8088 1'0
- assign $2\mul_op__oe__oe$8$next[0:0]$8086 1'0
- assign $2\mul_op__oe__ok$9$next[0:0]$8087 1'0
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8032 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 1'0
+ assign $2\mul_op__rc__rc$6$next[0:0]$8037 1'0
+ assign $2\mul_op__rc__ok$7$next[0:0]$8036 1'0
+ assign $2\mul_op__oe__oe$8$next[0:0]$8034 1'0
+ assign $2\mul_op__oe__ok$9$next[0:0]$8035 1'0
case
- assign $2\mul_op__imm_data__data$4$next[63:0]$8084 $1\mul_op__imm_data__data$4$next[63:0]$8073
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8085 $1\mul_op__imm_data__ok$5$next[0:0]$8074
- assign $2\mul_op__oe__oe$8$next[0:0]$8086 $1\mul_op__oe__oe$8$next[0:0]$8079
- assign $2\mul_op__oe__ok$9$next[0:0]$8087 $1\mul_op__oe__ok$9$next[0:0]$8080
- assign $2\mul_op__rc__ok$7$next[0:0]$8088 $1\mul_op__rc__ok$7$next[0:0]$8081
- assign $2\mul_op__rc__rc$6$next[0:0]$8089 $1\mul_op__rc__rc$6$next[0:0]$8082
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8032 $1\mul_op__imm_data__data$4$next[63:0]$8021
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 $1\mul_op__imm_data__ok$5$next[0:0]$8022
+ assign $2\mul_op__oe__oe$8$next[0:0]$8034 $1\mul_op__oe__oe$8$next[0:0]$8027
+ assign $2\mul_op__oe__ok$9$next[0:0]$8035 $1\mul_op__oe__ok$9$next[0:0]$8028
+ assign $2\mul_op__rc__ok$7$next[0:0]$8036 $1\mul_op__rc__ok$7$next[0:0]$8029
+ assign $2\mul_op__rc__rc$6$next[0:0]$8037 $1\mul_op__rc__rc$6$next[0:0]$8030
end
sync always
- update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8060
- update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8061
- update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8062
- update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8063
- update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8064
- update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8065
- update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8066
- update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8067
- update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8068
- update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8069
- update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8070
- update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8071
+ update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8008
+ update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8009
+ update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8010
+ update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8011
+ update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8012
+ update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8013
+ update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8014
+ update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8015
+ update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8016
+ update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8017
+ update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8018
+ update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8019
end
- attribute \src "libresoc.v:156847.3-156859.6"
- process $proc$libresoc.v:156847$8090
+ attribute \src "libresoc.v:156511.3-156523.6"
+ process $proc$libresoc.v:156511$8038
assign { } { }
assign { } { }
- assign $0\o$next[128:0]$8091 $1\o$next[128:0]$8092
- attribute \src "libresoc.v:156848.5-156848.29"
+ assign $0\o$next[128:0]$8039 $1\o$next[128:0]$8040
+ attribute \src "libresoc.v:156512.5-156512.29"
switch \initial
- attribute \src "libresoc.v:156848.9-156848.17"
+ attribute \src "libresoc.v:156512.9-156512.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\o$next[128:0]$8092 \o$49
+ assign $1\o$next[128:0]$8040 \o$49
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\o$next[128:0]$8092 \o$49
+ assign $1\o$next[128:0]$8040 \o$49
case
- assign $1\o$next[128:0]$8092 \o
+ assign $1\o$next[128:0]$8040 \o
end
sync always
- update \o$next $0\o$next[128:0]$8091
+ update \o$next $0\o$next[128:0]$8039
end
- attribute \src "libresoc.v:156860.3-156872.6"
- process $proc$libresoc.v:156860$8093
+ attribute \src "libresoc.v:156524.3-156536.6"
+ process $proc$libresoc.v:156524$8041
assign { } { }
assign { } { }
- assign $0\xer_so$14$next[0:0]$8094 $1\xer_so$14$next[0:0]$8095
- attribute \src "libresoc.v:156861.5-156861.29"
+ assign $0\xer_so$14$next[0:0]$8042 $1\xer_so$14$next[0:0]$8043
+ attribute \src "libresoc.v:156525.5-156525.29"
switch \initial
- attribute \src "libresoc.v:156861.9-156861.17"
+ attribute \src "libresoc.v:156525.9-156525.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$14$next[0:0]$8095 \xer_so$50
+ assign $1\xer_so$14$next[0:0]$8043 \xer_so$50
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$14$next[0:0]$8095 \xer_so$50
+ assign $1\xer_so$14$next[0:0]$8043 \xer_so$50
case
- assign $1\xer_so$14$next[0:0]$8095 \xer_so$14
+ assign $1\xer_so$14$next[0:0]$8043 \xer_so$14
end
sync always
- update \xer_so$14$next $0\xer_so$14$next[0:0]$8094
+ update \xer_so$14$next $0\xer_so$14$next[0:0]$8042
end
- attribute \src "libresoc.v:156873.3-156885.6"
- process $proc$libresoc.v:156873$8096
+ attribute \src "libresoc.v:156537.3-156549.6"
+ process $proc$libresoc.v:156537$8044
assign { } { }
assign { } { }
- assign $0\neg_res$15$next[0:0]$8097 $1\neg_res$15$next[0:0]$8098
- attribute \src "libresoc.v:156874.5-156874.29"
+ assign $0\neg_res$15$next[0:0]$8045 $1\neg_res$15$next[0:0]$8046
+ attribute \src "libresoc.v:156538.5-156538.29"
switch \initial
- attribute \src "libresoc.v:156874.9-156874.17"
+ attribute \src "libresoc.v:156538.9-156538.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res$15$next[0:0]$8098 \neg_res$51
+ assign $1\neg_res$15$next[0:0]$8046 \neg_res$51
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res$15$next[0:0]$8098 \neg_res$51
+ assign $1\neg_res$15$next[0:0]$8046 \neg_res$51
case
- assign $1\neg_res$15$next[0:0]$8098 \neg_res$15
+ assign $1\neg_res$15$next[0:0]$8046 \neg_res$15
end
sync always
- update \neg_res$15$next $0\neg_res$15$next[0:0]$8097
+ update \neg_res$15$next $0\neg_res$15$next[0:0]$8045
end
- attribute \src "libresoc.v:156886.3-156898.6"
- process $proc$libresoc.v:156886$8099
+ attribute \src "libresoc.v:156550.3-156562.6"
+ process $proc$libresoc.v:156550$8047
assign { } { }
assign { } { }
- assign $0\neg_res32$16$next[0:0]$8100 $1\neg_res32$16$next[0:0]$8101
- attribute \src "libresoc.v:156887.5-156887.29"
+ assign $0\neg_res32$16$next[0:0]$8048 $1\neg_res32$16$next[0:0]$8049
+ attribute \src "libresoc.v:156551.5-156551.29"
switch \initial
- attribute \src "libresoc.v:156887.9-156887.17"
+ attribute \src "libresoc.v:156551.9-156551.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$52
+ assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$52
+ assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52
case
- assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$16
+ assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$16
end
sync always
- update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8100
+ update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8048
end
- connect \$34 $and$libresoc.v:156698$8017_Y
+ connect \$34 $and$libresoc.v:156362$7965_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \neg_res32$52 \mul2_neg_res32$32
connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \mul2_muxid \muxid
end
-attribute \src "libresoc.v:156921.1-158217.10"
+attribute \src "libresoc.v:156585.1-157881.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3"
attribute \generator "nMigen"
module \mul_pipe3
- attribute \src "libresoc.v:158135.3-158153.6"
- wire width 4 $0\cr_a$next[3:0]$8220
- attribute \src "libresoc.v:157927.3-157928.25"
+ attribute \src "libresoc.v:157799.3-157817.6"
+ wire width 4 $0\cr_a$next[3:0]$8168
+ attribute \src "libresoc.v:157591.3-157592.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:158135.3-158153.6"
- wire $0\cr_a_ok$next[0:0]$8221
- attribute \src "libresoc.v:157929.3-157930.31"
+ attribute \src "libresoc.v:157799.3-157817.6"
+ wire $0\cr_a_ok$next[0:0]$8169
+ attribute \src "libresoc.v:157593.3-157594.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:156922.7-156922.20"
+ attribute \src "libresoc.v:156586.7-156586.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8183
- attribute \src "libresoc.v:157937.3-157938.53"
- wire width 14 $0\mul_op__fn_unit$3[13:0]$8151
- attribute \src "libresoc.v:157233.14-157233.44"
- wire width 14 $0\mul_op__fn_unit$3[13:0]$8241
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8184
- attribute \src "libresoc.v:157939.3-157940.67"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8153
- attribute \src "libresoc.v:157257.14-157257.63"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8243
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__imm_data__ok$5$next[0:0]$8185
- attribute \src "libresoc.v:157941.3-157942.63"
- wire $0\mul_op__imm_data__ok$5[0:0]$8155
- attribute \src "libresoc.v:157266.7-157266.38"
- wire $0\mul_op__imm_data__ok$5[0:0]$8245
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 32 $0\mul_op__insn$13$next[31:0]$8186
- attribute \src "libresoc.v:157957.3-157958.49"
- wire width 32 $0\mul_op__insn$13[31:0]$8171
- attribute \src "libresoc.v:157275.14-157275.39"
- wire width 32 $0\mul_op__insn$13[31:0]$8247
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 7 $0\mul_op__insn_type$2$next[6:0]$8187
- attribute \src "libresoc.v:157935.3-157936.57"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8149
- attribute \src "libresoc.v:157434.13-157434.42"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8249
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__is_32bit$11$next[0:0]$8188
- attribute \src "libresoc.v:157953.3-157954.57"
- wire $0\mul_op__is_32bit$11[0:0]$8167
- attribute \src "libresoc.v:157518.7-157518.35"
- wire $0\mul_op__is_32bit$11[0:0]$8251
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__is_signed$12$next[0:0]$8189
- attribute \src "libresoc.v:157955.3-157956.59"
- wire $0\mul_op__is_signed$12[0:0]$8169
- attribute \src "libresoc.v:157527.7-157527.36"
- wire $0\mul_op__is_signed$12[0:0]$8253
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__oe__oe$8$next[0:0]$8190
- attribute \src "libresoc.v:157947.3-157948.51"
- wire $0\mul_op__oe__oe$8[0:0]$8161
- attribute \src "libresoc.v:157538.7-157538.32"
- wire $0\mul_op__oe__oe$8[0:0]$8255
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__oe__ok$9$next[0:0]$8191
- attribute \src "libresoc.v:157949.3-157950.51"
- wire $0\mul_op__oe__ok$9[0:0]$8163
- attribute \src "libresoc.v:157547.7-157547.32"
- wire $0\mul_op__oe__ok$9[0:0]$8257
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__rc__ok$7$next[0:0]$8192
- attribute \src "libresoc.v:157945.3-157946.51"
- wire $0\mul_op__rc__ok$7[0:0]$8159
- attribute \src "libresoc.v:157556.7-157556.32"
- wire $0\mul_op__rc__ok$7[0:0]$8259
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__rc__rc$6$next[0:0]$8193
- attribute \src "libresoc.v:157943.3-157944.51"
- wire $0\mul_op__rc__rc$6[0:0]$8157
- attribute \src "libresoc.v:157563.7-157563.32"
- wire $0\mul_op__rc__rc$6[0:0]$8261
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $0\mul_op__write_cr0$10$next[0:0]$8194
- attribute \src "libresoc.v:157951.3-157952.59"
- wire $0\mul_op__write_cr0$10[0:0]$8165
- attribute \src "libresoc.v:157572.7-157572.36"
- wire $0\mul_op__write_cr0$10[0:0]$8263
- attribute \src "libresoc.v:158067.3-158079.6"
- wire width 2 $0\muxid$1$next[1:0]$8180
- attribute \src "libresoc.v:157959.3-157960.33"
- wire width 2 $0\muxid$1[1:0]$8173
- attribute \src "libresoc.v:157581.13-157581.29"
- wire width 2 $0\muxid$1[1:0]$8265
- attribute \src "libresoc.v:158116.3-158134.6"
- wire width 64 $0\o$14$next[63:0]$8215
- attribute \src "libresoc.v:157931.3-157932.27"
- wire width 64 $0\o$14[63:0]$8146
- attribute \src "libresoc.v:157602.14-157602.43"
- wire width 64 $0\o$14[63:0]$8267
- attribute \src "libresoc.v:158116.3-158134.6"
- wire $0\o_ok$next[0:0]$8214
- attribute \src "libresoc.v:157933.3-157934.25"
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8131
+ attribute \src "libresoc.v:157601.3-157602.53"
+ wire width 14 $0\mul_op__fn_unit$3[13:0]$8099
+ attribute \src "libresoc.v:156897.14-156897.44"
+ wire width 14 $0\mul_op__fn_unit$3[13:0]$8189
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8132
+ attribute \src "libresoc.v:157603.3-157604.67"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8101
+ attribute \src "libresoc.v:156921.14-156921.63"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8191
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__imm_data__ok$5$next[0:0]$8133
+ attribute \src "libresoc.v:157605.3-157606.63"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8103
+ attribute \src "libresoc.v:156930.7-156930.38"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8193
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 32 $0\mul_op__insn$13$next[31:0]$8134
+ attribute \src "libresoc.v:157621.3-157622.49"
+ wire width 32 $0\mul_op__insn$13[31:0]$8119
+ attribute \src "libresoc.v:156939.14-156939.39"
+ wire width 32 $0\mul_op__insn$13[31:0]$8195
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 7 $0\mul_op__insn_type$2$next[6:0]$8135
+ attribute \src "libresoc.v:157599.3-157600.57"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8097
+ attribute \src "libresoc.v:157098.13-157098.42"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8197
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__is_32bit$11$next[0:0]$8136
+ attribute \src "libresoc.v:157617.3-157618.57"
+ wire $0\mul_op__is_32bit$11[0:0]$8115
+ attribute \src "libresoc.v:157182.7-157182.35"
+ wire $0\mul_op__is_32bit$11[0:0]$8199
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__is_signed$12$next[0:0]$8137
+ attribute \src "libresoc.v:157619.3-157620.59"
+ wire $0\mul_op__is_signed$12[0:0]$8117
+ attribute \src "libresoc.v:157191.7-157191.36"
+ wire $0\mul_op__is_signed$12[0:0]$8201
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__oe__oe$8$next[0:0]$8138
+ attribute \src "libresoc.v:157611.3-157612.51"
+ wire $0\mul_op__oe__oe$8[0:0]$8109
+ attribute \src "libresoc.v:157202.7-157202.32"
+ wire $0\mul_op__oe__oe$8[0:0]$8203
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__oe__ok$9$next[0:0]$8139
+ attribute \src "libresoc.v:157613.3-157614.51"
+ wire $0\mul_op__oe__ok$9[0:0]$8111
+ attribute \src "libresoc.v:157211.7-157211.32"
+ wire $0\mul_op__oe__ok$9[0:0]$8205
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__rc__ok$7$next[0:0]$8140
+ attribute \src "libresoc.v:157609.3-157610.51"
+ wire $0\mul_op__rc__ok$7[0:0]$8107
+ attribute \src "libresoc.v:157220.7-157220.32"
+ wire $0\mul_op__rc__ok$7[0:0]$8207
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__rc__rc$6$next[0:0]$8141
+ attribute \src "libresoc.v:157607.3-157608.51"
+ wire $0\mul_op__rc__rc$6[0:0]$8105
+ attribute \src "libresoc.v:157227.7-157227.32"
+ wire $0\mul_op__rc__rc$6[0:0]$8209
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $0\mul_op__write_cr0$10$next[0:0]$8142
+ attribute \src "libresoc.v:157615.3-157616.59"
+ wire $0\mul_op__write_cr0$10[0:0]$8113
+ attribute \src "libresoc.v:157236.7-157236.36"
+ wire $0\mul_op__write_cr0$10[0:0]$8211
+ attribute \src "libresoc.v:157731.3-157743.6"
+ wire width 2 $0\muxid$1$next[1:0]$8128
+ attribute \src "libresoc.v:157623.3-157624.33"
+ wire width 2 $0\muxid$1[1:0]$8121
+ attribute \src "libresoc.v:157245.13-157245.29"
+ wire width 2 $0\muxid$1[1:0]$8213
+ attribute \src "libresoc.v:157780.3-157798.6"
+ wire width 64 $0\o$14$next[63:0]$8163
+ attribute \src "libresoc.v:157595.3-157596.27"
+ wire width 64 $0\o$14[63:0]$8094
+ attribute \src "libresoc.v:157266.14-157266.43"
+ wire width 64 $0\o$14[63:0]$8215
+ attribute \src "libresoc.v:157780.3-157798.6"
+ wire $0\o_ok$next[0:0]$8162
+ attribute \src "libresoc.v:157597.3-157598.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:158049.3-158066.6"
- wire $0\r_busy$next[0:0]$8176
- attribute \src "libresoc.v:157961.3-157962.29"
+ attribute \src "libresoc.v:157713.3-157730.6"
+ wire $0\r_busy$next[0:0]$8124
+ attribute \src "libresoc.v:157625.3-157626.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:158154.3-158172.6"
- wire width 2 $0\xer_ov$next[1:0]$8226
- attribute \src "libresoc.v:157923.3-157924.29"
+ attribute \src "libresoc.v:157818.3-157836.6"
+ wire width 2 $0\xer_ov$next[1:0]$8174
+ attribute \src "libresoc.v:157587.3-157588.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:158154.3-158172.6"
- wire $0\xer_ov_ok$next[0:0]$8227
- attribute \src "libresoc.v:157925.3-157926.35"
+ attribute \src "libresoc.v:157818.3-157836.6"
+ wire $0\xer_ov_ok$next[0:0]$8175
+ attribute \src "libresoc.v:157589.3-157590.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:158173.3-158191.6"
- wire $0\xer_so$15$next[0:0]$8233
- attribute \src "libresoc.v:157919.3-157920.37"
- wire $0\xer_so$15[0:0]$8139
- attribute \src "libresoc.v:157904.7-157904.25"
- wire $0\xer_so$15[0:0]$8273
- attribute \src "libresoc.v:158173.3-158191.6"
- wire $0\xer_so_ok$next[0:0]$8232
- attribute \src "libresoc.v:157921.3-157922.35"
+ attribute \src "libresoc.v:157837.3-157855.6"
+ wire $0\xer_so$15$next[0:0]$8181
+ attribute \src "libresoc.v:157583.3-157584.37"
+ wire $0\xer_so$15[0:0]$8087
+ attribute \src "libresoc.v:157568.7-157568.25"
+ wire $0\xer_so$15[0:0]$8221
+ attribute \src "libresoc.v:157837.3-157855.6"
+ wire $0\xer_so_ok$next[0:0]$8180
+ attribute \src "libresoc.v:157585.3-157586.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:158135.3-158153.6"
- wire width 4 $1\cr_a$next[3:0]$8222
- attribute \src "libresoc.v:156931.13-156931.24"
+ attribute \src "libresoc.v:157799.3-157817.6"
+ wire width 4 $1\cr_a$next[3:0]$8170
+ attribute \src "libresoc.v:156595.13-156595.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:158135.3-158153.6"
- wire $1\cr_a_ok$next[0:0]$8223
- attribute \src "libresoc.v:156940.7-156940.21"
+ attribute \src "libresoc.v:157799.3-157817.6"
+ wire $1\cr_a_ok$next[0:0]$8171
+ attribute \src "libresoc.v:156604.7-156604.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8195
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8196
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__imm_data__ok$5$next[0:0]$8197
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 32 $1\mul_op__insn$13$next[31:0]$8198
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 7 $1\mul_op__insn_type$2$next[6:0]$8199
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__is_32bit$11$next[0:0]$8200
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__is_signed$12$next[0:0]$8201
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__oe__oe$8$next[0:0]$8202
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__oe__ok$9$next[0:0]$8203
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__rc__ok$7$next[0:0]$8204
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__rc__rc$6$next[0:0]$8205
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $1\mul_op__write_cr0$10$next[0:0]$8206
- attribute \src "libresoc.v:158067.3-158079.6"
- wire width 2 $1\muxid$1$next[1:0]$8181
- attribute \src "libresoc.v:158116.3-158134.6"
- wire width 64 $1\o$14$next[63:0]$8217
- attribute \src "libresoc.v:158116.3-158134.6"
- wire $1\o_ok$next[0:0]$8216
- attribute \src "libresoc.v:157609.7-157609.18"
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8143
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8144
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__imm_data__ok$5$next[0:0]$8145
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 32 $1\mul_op__insn$13$next[31:0]$8146
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 7 $1\mul_op__insn_type$2$next[6:0]$8147
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__is_32bit$11$next[0:0]$8148
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__is_signed$12$next[0:0]$8149
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__oe__oe$8$next[0:0]$8150
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__oe__ok$9$next[0:0]$8151
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__rc__ok$7$next[0:0]$8152
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__rc__rc$6$next[0:0]$8153
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $1\mul_op__write_cr0$10$next[0:0]$8154
+ attribute \src "libresoc.v:157731.3-157743.6"
+ wire width 2 $1\muxid$1$next[1:0]$8129
+ attribute \src "libresoc.v:157780.3-157798.6"
+ wire width 64 $1\o$14$next[63:0]$8165
+ attribute \src "libresoc.v:157780.3-157798.6"
+ wire $1\o_ok$next[0:0]$8164
+ attribute \src "libresoc.v:157273.7-157273.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:158049.3-158066.6"
- wire $1\r_busy$next[0:0]$8177
- attribute \src "libresoc.v:157881.7-157881.20"
+ attribute \src "libresoc.v:157713.3-157730.6"
+ wire $1\r_busy$next[0:0]$8125
+ attribute \src "libresoc.v:157545.7-157545.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:158154.3-158172.6"
- wire width 2 $1\xer_ov$next[1:0]$8228
- attribute \src "libresoc.v:157886.13-157886.26"
+ attribute \src "libresoc.v:157818.3-157836.6"
+ wire width 2 $1\xer_ov$next[1:0]$8176
+ attribute \src "libresoc.v:157550.13-157550.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:158154.3-158172.6"
- wire $1\xer_ov_ok$next[0:0]$8229
- attribute \src "libresoc.v:157893.7-157893.23"
+ attribute \src "libresoc.v:157818.3-157836.6"
+ wire $1\xer_ov_ok$next[0:0]$8177
+ attribute \src "libresoc.v:157557.7-157557.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:158173.3-158191.6"
- wire $1\xer_so$15$next[0:0]$8235
- attribute \src "libresoc.v:158173.3-158191.6"
- wire $1\xer_so_ok$next[0:0]$8234
- attribute \src "libresoc.v:157911.7-157911.23"
+ attribute \src "libresoc.v:157837.3-157855.6"
+ wire $1\xer_so$15$next[0:0]$8183
+ attribute \src "libresoc.v:157837.3-157855.6"
+ wire $1\xer_so_ok$next[0:0]$8182
+ attribute \src "libresoc.v:157575.7-157575.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:158135.3-158153.6"
- wire $2\cr_a_ok$next[0:0]$8224
- attribute \src "libresoc.v:158080.3-158115.6"
- wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8207
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $2\mul_op__imm_data__ok$5$next[0:0]$8208
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $2\mul_op__oe__oe$8$next[0:0]$8209
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $2\mul_op__oe__ok$9$next[0:0]$8210
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $2\mul_op__rc__ok$7$next[0:0]$8211
- attribute \src "libresoc.v:158080.3-158115.6"
- wire $2\mul_op__rc__rc$6$next[0:0]$8212
- attribute \src "libresoc.v:158116.3-158134.6"
- wire $2\o_ok$next[0:0]$8218
- attribute \src "libresoc.v:158049.3-158066.6"
- wire $2\r_busy$next[0:0]$8178
- attribute \src "libresoc.v:158154.3-158172.6"
- wire $2\xer_ov_ok$next[0:0]$8230
- attribute \src "libresoc.v:158173.3-158191.6"
- wire $2\xer_so_ok$next[0:0]$8236
- attribute \src "libresoc.v:157918.18-157918.118"
- wire $and$libresoc.v:157918$8137_Y
+ attribute \src "libresoc.v:157799.3-157817.6"
+ wire $2\cr_a_ok$next[0:0]$8172
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8155
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $2\mul_op__imm_data__ok$5$next[0:0]$8156
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $2\mul_op__oe__oe$8$next[0:0]$8157
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $2\mul_op__oe__ok$9$next[0:0]$8158
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $2\mul_op__rc__ok$7$next[0:0]$8159
+ attribute \src "libresoc.v:157744.3-157779.6"
+ wire $2\mul_op__rc__rc$6$next[0:0]$8160
+ attribute \src "libresoc.v:157780.3-157798.6"
+ wire $2\o_ok$next[0:0]$8166
+ attribute \src "libresoc.v:157713.3-157730.6"
+ wire $2\r_busy$next[0:0]$8126
+ attribute \src "libresoc.v:157818.3-157836.6"
+ wire $2\xer_ov_ok$next[0:0]$8178
+ attribute \src "libresoc.v:157837.3-157855.6"
+ wire $2\xer_so_ok$next[0:0]$8184
+ attribute \src "libresoc.v:157582.18-157582.118"
+ wire $and$libresoc.v:157582$8085_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 44 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 38 \cr_a
wire \cr_a_ok$74
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:156922.7-156922.15"
+ attribute \src "libresoc.v:156586.7-156586.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:157918$8137
+ cell $and $and$libresoc.v:157582$8085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$55
connect \B \p_ready_o
- connect \Y $and$libresoc.v:157918$8137_Y
+ connect \Y $and$libresoc.v:157582$8085_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:157963.8-157999.4"
+ attribute \src "libresoc.v:157627.8-157663.4"
cell \mul3 \mul3
connect \mul_op__fn_unit \mul3_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18
connect \xer_so_ok \mul3_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:158000.10-158003.4"
+ attribute \src "libresoc.v:157664.10-157667.4"
cell \n$99 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:158004.16-158044.4"
+ attribute \src "libresoc.v:157668.16-157708.4"
cell \output$100 \output
connect \cr_a \output_cr_a
connect \cr_a$16 \output_cr_a$46
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:158045.10-158048.4"
+ attribute \src "libresoc.v:157709.10-157712.4"
cell \p$98 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:156922.7-156922.20"
- process $proc$libresoc.v:156922$8237
+ attribute \src "libresoc.v:156586.7-156586.20"
+ process $proc$libresoc.v:156586$8185
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156931.13-156931.24"
- process $proc$libresoc.v:156931$8238
+ attribute \src "libresoc.v:156595.13-156595.24"
+ process $proc$libresoc.v:156595$8186
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:156940.7-156940.21"
- process $proc$libresoc.v:156940$8239
+ attribute \src "libresoc.v:156604.7-156604.21"
+ process $proc$libresoc.v:156604$8187
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:157233.14-157233.44"
- process $proc$libresoc.v:157233$8240
+ attribute \src "libresoc.v:156897.14-156897.44"
+ process $proc$libresoc.v:156897$8188
assign { } { }
- assign $0\mul_op__fn_unit$3[13:0]$8241 14'00000000000000
+ assign $0\mul_op__fn_unit$3[13:0]$8189 14'00000000000000
sync always
sync init
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8241
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8189
end
- attribute \src "libresoc.v:157257.14-157257.63"
- process $proc$libresoc.v:157257$8242
+ attribute \src "libresoc.v:156921.14-156921.63"
+ process $proc$libresoc.v:156921$8190
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8243 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\mul_op__imm_data__data$4[63:0]$8191 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8243
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8191
end
- attribute \src "libresoc.v:157266.7-157266.38"
- process $proc$libresoc.v:157266$8244
+ attribute \src "libresoc.v:156930.7-156930.38"
+ process $proc$libresoc.v:156930$8192
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8245 1'0
+ assign $0\mul_op__imm_data__ok$5[0:0]$8193 1'0
sync always
sync init
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8245
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8193
end
- attribute \src "libresoc.v:157275.14-157275.39"
- process $proc$libresoc.v:157275$8246
+ attribute \src "libresoc.v:156939.14-156939.39"
+ process $proc$libresoc.v:156939$8194
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8247 0
+ assign $0\mul_op__insn$13[31:0]$8195 0
sync always
sync init
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8247
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8195
end
- attribute \src "libresoc.v:157434.13-157434.42"
- process $proc$libresoc.v:157434$8248
+ attribute \src "libresoc.v:157098.13-157098.42"
+ process $proc$libresoc.v:157098$8196
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8249 7'0000000
+ assign $0\mul_op__insn_type$2[6:0]$8197 7'0000000
sync always
sync init
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8249
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8197
end
- attribute \src "libresoc.v:157518.7-157518.35"
- process $proc$libresoc.v:157518$8250
+ attribute \src "libresoc.v:157182.7-157182.35"
+ process $proc$libresoc.v:157182$8198
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8251 1'0
+ assign $0\mul_op__is_32bit$11[0:0]$8199 1'0
sync always
sync init
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8251
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8199
end
- attribute \src "libresoc.v:157527.7-157527.36"
- process $proc$libresoc.v:157527$8252
+ attribute \src "libresoc.v:157191.7-157191.36"
+ process $proc$libresoc.v:157191$8200
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8253 1'0
+ assign $0\mul_op__is_signed$12[0:0]$8201 1'0
sync always
sync init
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8253
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8201
end
- attribute \src "libresoc.v:157538.7-157538.32"
- process $proc$libresoc.v:157538$8254
+ attribute \src "libresoc.v:157202.7-157202.32"
+ process $proc$libresoc.v:157202$8202
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8255 1'0
+ assign $0\mul_op__oe__oe$8[0:0]$8203 1'0
sync always
sync init
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8255
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8203
end
- attribute \src "libresoc.v:157547.7-157547.32"
- process $proc$libresoc.v:157547$8256
+ attribute \src "libresoc.v:157211.7-157211.32"
+ process $proc$libresoc.v:157211$8204
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8257 1'0
+ assign $0\mul_op__oe__ok$9[0:0]$8205 1'0
sync always
sync init
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8257
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8205
end
- attribute \src "libresoc.v:157556.7-157556.32"
- process $proc$libresoc.v:157556$8258
+ attribute \src "libresoc.v:157220.7-157220.32"
+ process $proc$libresoc.v:157220$8206
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8259 1'0
+ assign $0\mul_op__rc__ok$7[0:0]$8207 1'0
sync always
sync init
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8259
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8207
end
- attribute \src "libresoc.v:157563.7-157563.32"
- process $proc$libresoc.v:157563$8260
+ attribute \src "libresoc.v:157227.7-157227.32"
+ process $proc$libresoc.v:157227$8208
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8261 1'0
+ assign $0\mul_op__rc__rc$6[0:0]$8209 1'0
sync always
sync init
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8261
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8209
end
- attribute \src "libresoc.v:157572.7-157572.36"
- process $proc$libresoc.v:157572$8262
+ attribute \src "libresoc.v:157236.7-157236.36"
+ process $proc$libresoc.v:157236$8210
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8263 1'0
+ assign $0\mul_op__write_cr0$10[0:0]$8211 1'0
sync always
sync init
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8263
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8211
end
- attribute \src "libresoc.v:157581.13-157581.29"
- process $proc$libresoc.v:157581$8264
+ attribute \src "libresoc.v:157245.13-157245.29"
+ process $proc$libresoc.v:157245$8212
assign { } { }
- assign $0\muxid$1[1:0]$8265 2'00
+ assign $0\muxid$1[1:0]$8213 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8265
+ update \muxid$1 $0\muxid$1[1:0]$8213
end
- attribute \src "libresoc.v:157602.14-157602.43"
- process $proc$libresoc.v:157602$8266
+ attribute \src "libresoc.v:157266.14-157266.43"
+ process $proc$libresoc.v:157266$8214
assign { } { }
- assign $0\o$14[63:0]$8267 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$14[63:0]$8215 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$14 $0\o$14[63:0]$8267
+ update \o$14 $0\o$14[63:0]$8215
end
- attribute \src "libresoc.v:157609.7-157609.18"
- process $proc$libresoc.v:157609$8268
+ attribute \src "libresoc.v:157273.7-157273.18"
+ process $proc$libresoc.v:157273$8216
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:157881.7-157881.20"
- process $proc$libresoc.v:157881$8269
+ attribute \src "libresoc.v:157545.7-157545.20"
+ process $proc$libresoc.v:157545$8217
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:157886.13-157886.26"
- process $proc$libresoc.v:157886$8270
+ attribute \src "libresoc.v:157550.13-157550.26"
+ process $proc$libresoc.v:157550$8218
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:157893.7-157893.23"
- process $proc$libresoc.v:157893$8271
+ attribute \src "libresoc.v:157557.7-157557.23"
+ process $proc$libresoc.v:157557$8219
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:157904.7-157904.25"
- process $proc$libresoc.v:157904$8272
+ attribute \src "libresoc.v:157568.7-157568.25"
+ process $proc$libresoc.v:157568$8220
assign { } { }
- assign $0\xer_so$15[0:0]$8273 1'0
+ assign $0\xer_so$15[0:0]$8221 1'0
sync always
sync init
- update \xer_so$15 $0\xer_so$15[0:0]$8273
+ update \xer_so$15 $0\xer_so$15[0:0]$8221
end
- attribute \src "libresoc.v:157911.7-157911.23"
- process $proc$libresoc.v:157911$8274
+ attribute \src "libresoc.v:157575.7-157575.23"
+ process $proc$libresoc.v:157575$8222
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:157919.3-157920.37"
- process $proc$libresoc.v:157919$8138
+ attribute \src "libresoc.v:157583.3-157584.37"
+ process $proc$libresoc.v:157583$8086
assign { } { }
- assign $0\xer_so$15[0:0]$8139 \xer_so$15$next
+ assign $0\xer_so$15[0:0]$8087 \xer_so$15$next
sync posedge \coresync_clk
- update \xer_so$15 $0\xer_so$15[0:0]$8139
+ update \xer_so$15 $0\xer_so$15[0:0]$8087
end
- attribute \src "libresoc.v:157921.3-157922.35"
- process $proc$libresoc.v:157921$8140
+ attribute \src "libresoc.v:157585.3-157586.35"
+ process $proc$libresoc.v:157585$8088
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:157923.3-157924.29"
- process $proc$libresoc.v:157923$8141
+ attribute \src "libresoc.v:157587.3-157588.29"
+ process $proc$libresoc.v:157587$8089
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:157925.3-157926.35"
- process $proc$libresoc.v:157925$8142
+ attribute \src "libresoc.v:157589.3-157590.35"
+ process $proc$libresoc.v:157589$8090
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:157927.3-157928.25"
- process $proc$libresoc.v:157927$8143
+ attribute \src "libresoc.v:157591.3-157592.25"
+ process $proc$libresoc.v:157591$8091
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:157929.3-157930.31"
- process $proc$libresoc.v:157929$8144
+ attribute \src "libresoc.v:157593.3-157594.31"
+ process $proc$libresoc.v:157593$8092
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:157931.3-157932.27"
- process $proc$libresoc.v:157931$8145
+ attribute \src "libresoc.v:157595.3-157596.27"
+ process $proc$libresoc.v:157595$8093
assign { } { }
- assign $0\o$14[63:0]$8146 \o$14$next
+ assign $0\o$14[63:0]$8094 \o$14$next
sync posedge \coresync_clk
- update \o$14 $0\o$14[63:0]$8146
+ update \o$14 $0\o$14[63:0]$8094
end
- attribute \src "libresoc.v:157933.3-157934.25"
- process $proc$libresoc.v:157933$8147
+ attribute \src "libresoc.v:157597.3-157598.25"
+ process $proc$libresoc.v:157597$8095
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:157935.3-157936.57"
- process $proc$libresoc.v:157935$8148
+ attribute \src "libresoc.v:157599.3-157600.57"
+ process $proc$libresoc.v:157599$8096
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8149 \mul_op__insn_type$2$next
+ assign $0\mul_op__insn_type$2[6:0]$8097 \mul_op__insn_type$2$next
sync posedge \coresync_clk
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8149
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8097
end
- attribute \src "libresoc.v:157937.3-157938.53"
- process $proc$libresoc.v:157937$8150
+ attribute \src "libresoc.v:157601.3-157602.53"
+ process $proc$libresoc.v:157601$8098
assign { } { }
- assign $0\mul_op__fn_unit$3[13:0]$8151 \mul_op__fn_unit$3$next
+ assign $0\mul_op__fn_unit$3[13:0]$8099 \mul_op__fn_unit$3$next
sync posedge \coresync_clk
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8151
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8099
end
- attribute \src "libresoc.v:157939.3-157940.67"
- process $proc$libresoc.v:157939$8152
+ attribute \src "libresoc.v:157603.3-157604.67"
+ process $proc$libresoc.v:157603$8100
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8153 \mul_op__imm_data__data$4$next
+ assign $0\mul_op__imm_data__data$4[63:0]$8101 \mul_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8153
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8101
end
- attribute \src "libresoc.v:157941.3-157942.63"
- process $proc$libresoc.v:157941$8154
+ attribute \src "libresoc.v:157605.3-157606.63"
+ process $proc$libresoc.v:157605$8102
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8155 \mul_op__imm_data__ok$5$next
+ assign $0\mul_op__imm_data__ok$5[0:0]$8103 \mul_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8155
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8103
end
- attribute \src "libresoc.v:157943.3-157944.51"
- process $proc$libresoc.v:157943$8156
+ attribute \src "libresoc.v:157607.3-157608.51"
+ process $proc$libresoc.v:157607$8104
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8157 \mul_op__rc__rc$6$next
+ assign $0\mul_op__rc__rc$6[0:0]$8105 \mul_op__rc__rc$6$next
sync posedge \coresync_clk
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8157
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8105
end
- attribute \src "libresoc.v:157945.3-157946.51"
- process $proc$libresoc.v:157945$8158
+ attribute \src "libresoc.v:157609.3-157610.51"
+ process $proc$libresoc.v:157609$8106
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8159 \mul_op__rc__ok$7$next
+ assign $0\mul_op__rc__ok$7[0:0]$8107 \mul_op__rc__ok$7$next
sync posedge \coresync_clk
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8159
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8107
end
- attribute \src "libresoc.v:157947.3-157948.51"
- process $proc$libresoc.v:157947$8160
+ attribute \src "libresoc.v:157611.3-157612.51"
+ process $proc$libresoc.v:157611$8108
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8161 \mul_op__oe__oe$8$next
+ assign $0\mul_op__oe__oe$8[0:0]$8109 \mul_op__oe__oe$8$next
sync posedge \coresync_clk
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8161
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8109
end
- attribute \src "libresoc.v:157949.3-157950.51"
- process $proc$libresoc.v:157949$8162
+ attribute \src "libresoc.v:157613.3-157614.51"
+ process $proc$libresoc.v:157613$8110
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8163 \mul_op__oe__ok$9$next
+ assign $0\mul_op__oe__ok$9[0:0]$8111 \mul_op__oe__ok$9$next
sync posedge \coresync_clk
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8163
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8111
end
- attribute \src "libresoc.v:157951.3-157952.59"
- process $proc$libresoc.v:157951$8164
+ attribute \src "libresoc.v:157615.3-157616.59"
+ process $proc$libresoc.v:157615$8112
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8165 \mul_op__write_cr0$10$next
+ assign $0\mul_op__write_cr0$10[0:0]$8113 \mul_op__write_cr0$10$next
sync posedge \coresync_clk
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8165
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8113
end
- attribute \src "libresoc.v:157953.3-157954.57"
- process $proc$libresoc.v:157953$8166
+ attribute \src "libresoc.v:157617.3-157618.57"
+ process $proc$libresoc.v:157617$8114
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8167 \mul_op__is_32bit$11$next
+ assign $0\mul_op__is_32bit$11[0:0]$8115 \mul_op__is_32bit$11$next
sync posedge \coresync_clk
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8167
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8115
end
- attribute \src "libresoc.v:157955.3-157956.59"
- process $proc$libresoc.v:157955$8168
+ attribute \src "libresoc.v:157619.3-157620.59"
+ process $proc$libresoc.v:157619$8116
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8169 \mul_op__is_signed$12$next
+ assign $0\mul_op__is_signed$12[0:0]$8117 \mul_op__is_signed$12$next
sync posedge \coresync_clk
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8169
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8117
end
- attribute \src "libresoc.v:157957.3-157958.49"
- process $proc$libresoc.v:157957$8170
+ attribute \src "libresoc.v:157621.3-157622.49"
+ process $proc$libresoc.v:157621$8118
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8171 \mul_op__insn$13$next
+ assign $0\mul_op__insn$13[31:0]$8119 \mul_op__insn$13$next
sync posedge \coresync_clk
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8171
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8119
end
- attribute \src "libresoc.v:157959.3-157960.33"
- process $proc$libresoc.v:157959$8172
+ attribute \src "libresoc.v:157623.3-157624.33"
+ process $proc$libresoc.v:157623$8120
assign { } { }
- assign $0\muxid$1[1:0]$8173 \muxid$1$next
+ assign $0\muxid$1[1:0]$8121 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8173
+ update \muxid$1 $0\muxid$1[1:0]$8121
end
- attribute \src "libresoc.v:157961.3-157962.29"
- process $proc$libresoc.v:157961$8174
+ attribute \src "libresoc.v:157625.3-157626.29"
+ process $proc$libresoc.v:157625$8122
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:158049.3-158066.6"
- process $proc$libresoc.v:158049$8175
+ attribute \src "libresoc.v:157713.3-157730.6"
+ process $proc$libresoc.v:157713$8123
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8176 $2\r_busy$next[0:0]$8178
- attribute \src "libresoc.v:158050.5-158050.29"
+ assign $0\r_busy$next[0:0]$8124 $2\r_busy$next[0:0]$8126
+ attribute \src "libresoc.v:157714.5-157714.29"
switch \initial
- attribute \src "libresoc.v:158050.9-158050.17"
+ attribute \src "libresoc.v:157714.9-157714.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8177 1'1
+ assign $1\r_busy$next[0:0]$8125 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8177 1'0
+ assign $1\r_busy$next[0:0]$8125 1'0
case
- assign $1\r_busy$next[0:0]$8177 \r_busy
+ assign $1\r_busy$next[0:0]$8125 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8178 1'0
+ assign $2\r_busy$next[0:0]$8126 1'0
case
- assign $2\r_busy$next[0:0]$8178 $1\r_busy$next[0:0]$8177
+ assign $2\r_busy$next[0:0]$8126 $1\r_busy$next[0:0]$8125
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8176
+ update \r_busy$next $0\r_busy$next[0:0]$8124
end
- attribute \src "libresoc.v:158067.3-158079.6"
- process $proc$libresoc.v:158067$8179
+ attribute \src "libresoc.v:157731.3-157743.6"
+ process $proc$libresoc.v:157731$8127
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8180 $1\muxid$1$next[1:0]$8181
- attribute \src "libresoc.v:158068.5-158068.29"
+ assign $0\muxid$1$next[1:0]$8128 $1\muxid$1$next[1:0]$8129
+ attribute \src "libresoc.v:157732.5-157732.29"
switch \initial
- attribute \src "libresoc.v:158068.9-158068.17"
+ attribute \src "libresoc.v:157732.9-157732.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8181 \muxid$58
+ assign $1\muxid$1$next[1:0]$8129 \muxid$58
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8181 \muxid$58
+ assign $1\muxid$1$next[1:0]$8129 \muxid$58
case
- assign $1\muxid$1$next[1:0]$8181 \muxid$1
+ assign $1\muxid$1$next[1:0]$8129 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8180
+ update \muxid$1$next $0\muxid$1$next[1:0]$8128
end
- attribute \src "libresoc.v:158080.3-158115.6"
- process $proc$libresoc.v:158080$8182
+ attribute \src "libresoc.v:157744.3-157779.6"
+ process $proc$libresoc.v:157744$8130
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$3$next[13:0]$8183 $1\mul_op__fn_unit$3$next[13:0]$8195
+ assign $0\mul_op__fn_unit$3$next[13:0]$8131 $1\mul_op__fn_unit$3$next[13:0]$8143
assign { } { }
assign { } { }
- assign $0\mul_op__insn$13$next[31:0]$8186 $1\mul_op__insn$13$next[31:0]$8198
- assign $0\mul_op__insn_type$2$next[6:0]$8187 $1\mul_op__insn_type$2$next[6:0]$8199
- assign $0\mul_op__is_32bit$11$next[0:0]$8188 $1\mul_op__is_32bit$11$next[0:0]$8200
- assign $0\mul_op__is_signed$12$next[0:0]$8189 $1\mul_op__is_signed$12$next[0:0]$8201
+ assign $0\mul_op__insn$13$next[31:0]$8134 $1\mul_op__insn$13$next[31:0]$8146
+ assign $0\mul_op__insn_type$2$next[6:0]$8135 $1\mul_op__insn_type$2$next[6:0]$8147
+ assign $0\mul_op__is_32bit$11$next[0:0]$8136 $1\mul_op__is_32bit$11$next[0:0]$8148
+ assign $0\mul_op__is_signed$12$next[0:0]$8137 $1\mul_op__is_signed$12$next[0:0]$8149
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$10$next[0:0]$8194 $1\mul_op__write_cr0$10$next[0:0]$8206
- assign $0\mul_op__imm_data__data$4$next[63:0]$8184 $2\mul_op__imm_data__data$4$next[63:0]$8207
- assign $0\mul_op__imm_data__ok$5$next[0:0]$8185 $2\mul_op__imm_data__ok$5$next[0:0]$8208
- assign $0\mul_op__oe__oe$8$next[0:0]$8190 $2\mul_op__oe__oe$8$next[0:0]$8209
- assign $0\mul_op__oe__ok$9$next[0:0]$8191 $2\mul_op__oe__ok$9$next[0:0]$8210
- assign $0\mul_op__rc__ok$7$next[0:0]$8192 $2\mul_op__rc__ok$7$next[0:0]$8211
- assign $0\mul_op__rc__rc$6$next[0:0]$8193 $2\mul_op__rc__rc$6$next[0:0]$8212
- attribute \src "libresoc.v:158081.5-158081.29"
+ assign $0\mul_op__write_cr0$10$next[0:0]$8142 $1\mul_op__write_cr0$10$next[0:0]$8154
+ assign $0\mul_op__imm_data__data$4$next[63:0]$8132 $2\mul_op__imm_data__data$4$next[63:0]$8155
+ assign $0\mul_op__imm_data__ok$5$next[0:0]$8133 $2\mul_op__imm_data__ok$5$next[0:0]$8156
+ assign $0\mul_op__oe__oe$8$next[0:0]$8138 $2\mul_op__oe__oe$8$next[0:0]$8157
+ assign $0\mul_op__oe__ok$9$next[0:0]$8139 $2\mul_op__oe__ok$9$next[0:0]$8158
+ assign $0\mul_op__rc__ok$7$next[0:0]$8140 $2\mul_op__rc__ok$7$next[0:0]$8159
+ assign $0\mul_op__rc__rc$6$next[0:0]$8141 $2\mul_op__rc__rc$6$next[0:0]$8160
+ attribute \src "libresoc.v:157745.5-157745.29"
switch \initial
- attribute \src "libresoc.v:158081.9-158081.17"
+ attribute \src "libresoc.v:157745.9-157745.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8198 $1\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__oe__ok$9$next[0:0]$8203 $1\mul_op__oe__oe$8$next[0:0]$8202 $1\mul_op__rc__ok$7$next[0:0]$8204 $1\mul_op__rc__rc$6$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8197 $1\mul_op__imm_data__data$4$next[63:0]$8196 $1\mul_op__fn_unit$3$next[13:0]$8195 $1\mul_op__insn_type$2$next[6:0]$8199 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
+ assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8198 $1\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__oe__ok$9$next[0:0]$8203 $1\mul_op__oe__oe$8$next[0:0]$8202 $1\mul_op__rc__ok$7$next[0:0]$8204 $1\mul_op__rc__rc$6$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8197 $1\mul_op__imm_data__data$4$next[63:0]$8196 $1\mul_op__fn_unit$3$next[13:0]$8195 $1\mul_op__insn_type$2$next[6:0]$8199 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
+ assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
case
- assign $1\mul_op__fn_unit$3$next[13:0]$8195 \mul_op__fn_unit$3
- assign $1\mul_op__imm_data__data$4$next[63:0]$8196 \mul_op__imm_data__data$4
- assign $1\mul_op__imm_data__ok$5$next[0:0]$8197 \mul_op__imm_data__ok$5
- assign $1\mul_op__insn$13$next[31:0]$8198 \mul_op__insn$13
- assign $1\mul_op__insn_type$2$next[6:0]$8199 \mul_op__insn_type$2
- assign $1\mul_op__is_32bit$11$next[0:0]$8200 \mul_op__is_32bit$11
- assign $1\mul_op__is_signed$12$next[0:0]$8201 \mul_op__is_signed$12
- assign $1\mul_op__oe__oe$8$next[0:0]$8202 \mul_op__oe__oe$8
- assign $1\mul_op__oe__ok$9$next[0:0]$8203 \mul_op__oe__ok$9
- assign $1\mul_op__rc__ok$7$next[0:0]$8204 \mul_op__rc__ok$7
- assign $1\mul_op__rc__rc$6$next[0:0]$8205 \mul_op__rc__rc$6
- assign $1\mul_op__write_cr0$10$next[0:0]$8206 \mul_op__write_cr0$10
+ assign $1\mul_op__fn_unit$3$next[13:0]$8143 \mul_op__fn_unit$3
+ assign $1\mul_op__imm_data__data$4$next[63:0]$8144 \mul_op__imm_data__data$4
+ assign $1\mul_op__imm_data__ok$5$next[0:0]$8145 \mul_op__imm_data__ok$5
+ assign $1\mul_op__insn$13$next[31:0]$8146 \mul_op__insn$13
+ assign $1\mul_op__insn_type$2$next[6:0]$8147 \mul_op__insn_type$2
+ assign $1\mul_op__is_32bit$11$next[0:0]$8148 \mul_op__is_32bit$11
+ assign $1\mul_op__is_signed$12$next[0:0]$8149 \mul_op__is_signed$12
+ assign $1\mul_op__oe__oe$8$next[0:0]$8150 \mul_op__oe__oe$8
+ assign $1\mul_op__oe__ok$9$next[0:0]$8151 \mul_op__oe__ok$9
+ assign $1\mul_op__rc__ok$7$next[0:0]$8152 \mul_op__rc__ok$7
+ assign $1\mul_op__rc__rc$6$next[0:0]$8153 \mul_op__rc__rc$6
+ assign $1\mul_op__write_cr0$10$next[0:0]$8154 \mul_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$4$next[63:0]$8207 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8208 1'0
- assign $2\mul_op__rc__rc$6$next[0:0]$8212 1'0
- assign $2\mul_op__rc__ok$7$next[0:0]$8211 1'0
- assign $2\mul_op__oe__oe$8$next[0:0]$8209 1'0
- assign $2\mul_op__oe__ok$9$next[0:0]$8210 1'0
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8155 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 1'0
+ assign $2\mul_op__rc__rc$6$next[0:0]$8160 1'0
+ assign $2\mul_op__rc__ok$7$next[0:0]$8159 1'0
+ assign $2\mul_op__oe__oe$8$next[0:0]$8157 1'0
+ assign $2\mul_op__oe__ok$9$next[0:0]$8158 1'0
case
- assign $2\mul_op__imm_data__data$4$next[63:0]$8207 $1\mul_op__imm_data__data$4$next[63:0]$8196
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8208 $1\mul_op__imm_data__ok$5$next[0:0]$8197
- assign $2\mul_op__oe__oe$8$next[0:0]$8209 $1\mul_op__oe__oe$8$next[0:0]$8202
- assign $2\mul_op__oe__ok$9$next[0:0]$8210 $1\mul_op__oe__ok$9$next[0:0]$8203
- assign $2\mul_op__rc__ok$7$next[0:0]$8211 $1\mul_op__rc__ok$7$next[0:0]$8204
- assign $2\mul_op__rc__rc$6$next[0:0]$8212 $1\mul_op__rc__rc$6$next[0:0]$8205
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8155 $1\mul_op__imm_data__data$4$next[63:0]$8144
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 $1\mul_op__imm_data__ok$5$next[0:0]$8145
+ assign $2\mul_op__oe__oe$8$next[0:0]$8157 $1\mul_op__oe__oe$8$next[0:0]$8150
+ assign $2\mul_op__oe__ok$9$next[0:0]$8158 $1\mul_op__oe__ok$9$next[0:0]$8151
+ assign $2\mul_op__rc__ok$7$next[0:0]$8159 $1\mul_op__rc__ok$7$next[0:0]$8152
+ assign $2\mul_op__rc__rc$6$next[0:0]$8160 $1\mul_op__rc__rc$6$next[0:0]$8153
end
sync always
- update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8183
- update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8184
- update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8185
- update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8186
- update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8187
- update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8188
- update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8189
- update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8190
- update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8191
- update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8192
- update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8193
- update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8194
+ update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8131
+ update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8132
+ update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8133
+ update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8134
+ update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8135
+ update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8136
+ update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8137
+ update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8138
+ update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8139
+ update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8140
+ update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8141
+ update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8142
end
- attribute \src "libresoc.v:158116.3-158134.6"
- process $proc$libresoc.v:158116$8213
+ attribute \src "libresoc.v:157780.3-157798.6"
+ process $proc$libresoc.v:157780$8161
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$14$next[63:0]$8215 $1\o$14$next[63:0]$8217
- assign $0\o_ok$next[0:0]$8214 $2\o_ok$next[0:0]$8218
- attribute \src "libresoc.v:158117.5-158117.29"
+ assign $0\o$14$next[63:0]$8163 $1\o$14$next[63:0]$8165
+ assign $0\o_ok$next[0:0]$8162 $2\o_ok$next[0:0]$8166
+ attribute \src "libresoc.v:157781.5-157781.29"
switch \initial
- attribute \src "libresoc.v:158117.9-158117.17"
+ attribute \src "libresoc.v:157781.9-157781.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8216 $1\o$14$next[63:0]$8217 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8216 $1\o$14$next[63:0]$8217 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 }
case
- assign $1\o_ok$next[0:0]$8216 \o_ok
- assign $1\o$14$next[63:0]$8217 \o$14
+ assign $1\o_ok$next[0:0]$8164 \o_ok
+ assign $1\o$14$next[63:0]$8165 \o$14
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8218 1'0
+ assign $2\o_ok$next[0:0]$8166 1'0
case
- assign $2\o_ok$next[0:0]$8218 $1\o_ok$next[0:0]$8216
+ assign $2\o_ok$next[0:0]$8166 $1\o_ok$next[0:0]$8164
end
sync always
- update \o_ok$next $0\o_ok$next[0:0]$8214
- update \o$14$next $0\o$14$next[63:0]$8215
+ update \o_ok$next $0\o_ok$next[0:0]$8162
+ update \o$14$next $0\o$14$next[63:0]$8163
end
- attribute \src "libresoc.v:158135.3-158153.6"
- process $proc$libresoc.v:158135$8219
+ attribute \src "libresoc.v:157799.3-157817.6"
+ process $proc$libresoc.v:157799$8167
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$8220 $1\cr_a$next[3:0]$8222
+ assign $0\cr_a$next[3:0]$8168 $1\cr_a$next[3:0]$8170
assign { } { }
- assign $0\cr_a_ok$next[0:0]$8221 $2\cr_a_ok$next[0:0]$8224
- attribute \src "libresoc.v:158136.5-158136.29"
+ assign $0\cr_a_ok$next[0:0]$8169 $2\cr_a_ok$next[0:0]$8172
+ attribute \src "libresoc.v:157800.5-157800.29"
switch \initial
- attribute \src "libresoc.v:158136.9-158136.17"
+ attribute \src "libresoc.v:157800.9-157800.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8223 $1\cr_a$next[3:0]$8222 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8223 $1\cr_a$next[3:0]$8222 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 }
case
- assign $1\cr_a$next[3:0]$8222 \cr_a
- assign $1\cr_a_ok$next[0:0]$8223 \cr_a_ok
+ assign $1\cr_a$next[3:0]$8170 \cr_a
+ assign $1\cr_a_ok$next[0:0]$8171 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$8224 1'0
+ assign $2\cr_a_ok$next[0:0]$8172 1'0
case
- assign $2\cr_a_ok$next[0:0]$8224 $1\cr_a_ok$next[0:0]$8223
+ assign $2\cr_a_ok$next[0:0]$8172 $1\cr_a_ok$next[0:0]$8171
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$8220
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8221
+ update \cr_a$next $0\cr_a$next[3:0]$8168
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8169
end
- attribute \src "libresoc.v:158154.3-158172.6"
- process $proc$libresoc.v:158154$8225
+ attribute \src "libresoc.v:157818.3-157836.6"
+ process $proc$libresoc.v:157818$8173
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$8226 $1\xer_ov$next[1:0]$8228
+ assign $0\xer_ov$next[1:0]$8174 $1\xer_ov$next[1:0]$8176
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$8227 $2\xer_ov_ok$next[0:0]$8230
- attribute \src "libresoc.v:158155.5-158155.29"
+ assign $0\xer_ov_ok$next[0:0]$8175 $2\xer_ov_ok$next[0:0]$8178
+ attribute \src "libresoc.v:157819.5-157819.29"
switch \initial
- attribute \src "libresoc.v:158155.9-158155.17"
+ attribute \src "libresoc.v:157819.9-157819.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8229 $1\xer_ov$next[1:0]$8228 } { \xer_ov_ok$76 \xer_ov$75 }
+ assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8229 $1\xer_ov$next[1:0]$8228 } { \xer_ov_ok$76 \xer_ov$75 }
+ assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 }
case
- assign $1\xer_ov$next[1:0]$8228 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$8229 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$8176 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$8177 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$8230 1'0
+ assign $2\xer_ov_ok$next[0:0]$8178 1'0
case
- assign $2\xer_ov_ok$next[0:0]$8230 $1\xer_ov_ok$next[0:0]$8229
+ assign $2\xer_ov_ok$next[0:0]$8178 $1\xer_ov_ok$next[0:0]$8177
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$8226
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8227
+ update \xer_ov$next $0\xer_ov$next[1:0]$8174
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8175
end
- attribute \src "libresoc.v:158173.3-158191.6"
- process $proc$libresoc.v:158173$8231
+ attribute \src "libresoc.v:157837.3-157855.6"
+ process $proc$libresoc.v:157837$8179
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$15$next[0:0]$8233 $1\xer_so$15$next[0:0]$8235
- assign $0\xer_so_ok$next[0:0]$8232 $2\xer_so_ok$next[0:0]$8236
- attribute \src "libresoc.v:158174.5-158174.29"
+ assign $0\xer_so$15$next[0:0]$8181 $1\xer_so$15$next[0:0]$8183
+ assign $0\xer_so_ok$next[0:0]$8180 $2\xer_so_ok$next[0:0]$8184
+ attribute \src "libresoc.v:157838.5-157838.29"
switch \initial
- attribute \src "libresoc.v:158174.9-158174.17"
+ attribute \src "libresoc.v:157838.9-157838.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8234 $1\xer_so$15$next[0:0]$8235 } { \xer_so_ok$78 \xer_so$77 }
+ assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8234 $1\xer_so$15$next[0:0]$8235 } { \xer_so_ok$78 \xer_so$77 }
+ assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 }
case
- assign $1\xer_so_ok$next[0:0]$8234 \xer_so_ok
- assign $1\xer_so$15$next[0:0]$8235 \xer_so$15
+ assign $1\xer_so_ok$next[0:0]$8182 \xer_so_ok
+ assign $1\xer_so$15$next[0:0]$8183 \xer_so$15
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$8236 1'0
+ assign $2\xer_so_ok$next[0:0]$8184 1'0
case
- assign $2\xer_so_ok$next[0:0]$8236 $1\xer_so_ok$next[0:0]$8234
+ assign $2\xer_so_ok$next[0:0]$8184 $1\xer_so_ok$next[0:0]$8182
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8232
- update \xer_so$15$next $0\xer_so$15$next[0:0]$8233
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8180
+ update \xer_so$15$next $0\xer_so$15$next[0:0]$8181
end
- connect \$56 $and$libresoc.v:157918$8137_Y
+ connect \$56 $and$libresoc.v:157582$8085_Y
connect \cr_a$51 4'0000
connect \cr_a_ok$52 1'0
connect \p_ready_o \n_i_rdy_data
connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \mul3_muxid \muxid
end
-attribute \src "libresoc.v:158221.1-158232.10"
+attribute \src "libresoc.v:157885.1-157896.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n"
attribute \generator "nMigen"
module \n
- attribute \src "libresoc.v:158230.17-158230.111"
- wire $and$libresoc.v:158230$8275_Y
+ attribute \src "libresoc.v:157894.17-157894.111"
+ wire $and$libresoc.v:157894$8223_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158230$8275
+ cell $and $and$libresoc.v:157894$8223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158230$8275_Y
+ connect \Y $and$libresoc.v:157894$8223_Y
end
- connect \$1 $and$libresoc.v:158230$8275_Y
+ connect \$1 $and$libresoc.v:157894$8223_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158236.1-158247.10"
+attribute \src "libresoc.v:157900.1-157911.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n"
attribute \generator "nMigen"
module \n$109
- attribute \src "libresoc.v:158245.17-158245.111"
- wire $and$libresoc.v:158245$8276_Y
+ attribute \src "libresoc.v:157909.17-157909.111"
+ wire $and$libresoc.v:157909$8224_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158245$8276
+ cell $and $and$libresoc.v:157909$8224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158245$8276_Y
+ connect \Y $and$libresoc.v:157909$8224_Y
end
- connect \$1 $and$libresoc.v:158245$8276_Y
+ connect \$1 $and$libresoc.v:157909$8224_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158251.1-158262.10"
+attribute \src "libresoc.v:157915.1-157926.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n"
attribute \generator "nMigen"
module \n$112
- attribute \src "libresoc.v:158260.17-158260.111"
- wire $and$libresoc.v:158260$8277_Y
+ attribute \src "libresoc.v:157924.17-157924.111"
+ wire $and$libresoc.v:157924$8225_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158260$8277
+ cell $and $and$libresoc.v:157924$8225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158260$8277_Y
+ connect \Y $and$libresoc.v:157924$8225_Y
end
- connect \$1 $and$libresoc.v:158260$8277_Y
+ connect \$1 $and$libresoc.v:157924$8225_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158266.1-158277.10"
+attribute \src "libresoc.v:157930.1-157941.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n"
attribute \generator "nMigen"
module \n$117
- attribute \src "libresoc.v:158275.17-158275.111"
- wire $and$libresoc.v:158275$8278_Y
+ attribute \src "libresoc.v:157939.17-157939.111"
+ wire $and$libresoc.v:157939$8226_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158275$8278
+ cell $and $and$libresoc.v:157939$8226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158275$8278_Y
+ connect \Y $and$libresoc.v:157939$8226_Y
end
- connect \$1 $and$libresoc.v:158275$8278_Y
+ connect \$1 $and$libresoc.v:157939$8226_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158281.1-158292.10"
+attribute \src "libresoc.v:157945.1-157956.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n"
attribute \generator "nMigen"
module \n$18
- attribute \src "libresoc.v:158290.17-158290.111"
- wire $and$libresoc.v:158290$8279_Y
+ attribute \src "libresoc.v:157954.17-157954.111"
+ wire $and$libresoc.v:157954$8227_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158290$8279
+ cell $and $and$libresoc.v:157954$8227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158290$8279_Y
+ connect \Y $and$libresoc.v:157954$8227_Y
end
- connect \$1 $and$libresoc.v:158290$8279_Y
+ connect \$1 $and$libresoc.v:157954$8227_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158296.1-158307.10"
+attribute \src "libresoc.v:157960.1-157971.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n"
attribute \generator "nMigen"
module \n$2
- attribute \src "libresoc.v:158305.17-158305.111"
- wire $and$libresoc.v:158305$8280_Y
+ attribute \src "libresoc.v:157969.17-157969.111"
+ wire $and$libresoc.v:157969$8228_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158305$8280
+ cell $and $and$libresoc.v:157969$8228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158305$8280_Y
+ connect \Y $and$libresoc.v:157969$8228_Y
end
- connect \$1 $and$libresoc.v:158305$8280_Y
+ connect \$1 $and$libresoc.v:157969$8228_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158311.1-158322.10"
+attribute \src "libresoc.v:157975.1-157986.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n"
attribute \generator "nMigen"
module \n$21
- attribute \src "libresoc.v:158320.17-158320.111"
- wire $and$libresoc.v:158320$8281_Y
+ attribute \src "libresoc.v:157984.17-157984.111"
+ wire $and$libresoc.v:157984$8229_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158320$8281
+ cell $and $and$libresoc.v:157984$8229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158320$8281_Y
+ connect \Y $and$libresoc.v:157984$8229_Y
end
- connect \$1 $and$libresoc.v:158320$8281_Y
+ connect \$1 $and$libresoc.v:157984$8229_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158326.1-158337.10"
+attribute \src "libresoc.v:157990.1-158001.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n"
attribute \generator "nMigen"
module \n$31
- attribute \src "libresoc.v:158335.17-158335.111"
- wire $and$libresoc.v:158335$8282_Y
+ attribute \src "libresoc.v:157999.17-157999.111"
+ wire $and$libresoc.v:157999$8230_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158335$8282
+ cell $and $and$libresoc.v:157999$8230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158335$8282_Y
+ connect \Y $and$libresoc.v:157999$8230_Y
end
- connect \$1 $and$libresoc.v:158335$8282_Y
+ connect \$1 $and$libresoc.v:157999$8230_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158341.1-158352.10"
+attribute \src "libresoc.v:158005.1-158016.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n"
attribute \generator "nMigen"
module \n$34
- attribute \src "libresoc.v:158350.17-158350.111"
- wire $and$libresoc.v:158350$8283_Y
+ attribute \src "libresoc.v:158014.17-158014.111"
+ wire $and$libresoc.v:158014$8231_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158350$8283
+ cell $and $and$libresoc.v:158014$8231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158350$8283_Y
+ connect \Y $and$libresoc.v:158014$8231_Y
end
- connect \$1 $and$libresoc.v:158350$8283_Y
+ connect \$1 $and$libresoc.v:158014$8231_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158356.1-158367.10"
+attribute \src "libresoc.v:158020.1-158031.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n"
attribute \generator "nMigen"
module \n$37
- attribute \src "libresoc.v:158365.17-158365.111"
- wire $and$libresoc.v:158365$8284_Y
+ attribute \src "libresoc.v:158029.17-158029.111"
+ wire $and$libresoc.v:158029$8232_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158365$8284
+ cell $and $and$libresoc.v:158029$8232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158365$8284_Y
+ connect \Y $and$libresoc.v:158029$8232_Y
end
- connect \$1 $and$libresoc.v:158365$8284_Y
+ connect \$1 $and$libresoc.v:158029$8232_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158371.1-158382.10"
+attribute \src "libresoc.v:158035.1-158046.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n"
attribute \generator "nMigen"
module \n$4
- attribute \src "libresoc.v:158380.17-158380.111"
- wire $and$libresoc.v:158380$8285_Y
+ attribute \src "libresoc.v:158044.17-158044.111"
+ wire $and$libresoc.v:158044$8233_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158380$8285
+ cell $and $and$libresoc.v:158044$8233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158380$8285_Y
+ connect \Y $and$libresoc.v:158044$8233_Y
end
- connect \$1 $and$libresoc.v:158380$8285_Y
+ connect \$1 $and$libresoc.v:158044$8233_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158386.1-158397.10"
+attribute \src "libresoc.v:158050.1-158061.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n"
attribute \generator "nMigen"
module \n$47
- attribute \src "libresoc.v:158395.17-158395.111"
- wire $and$libresoc.v:158395$8286_Y
+ attribute \src "libresoc.v:158059.17-158059.111"
+ wire $and$libresoc.v:158059$8234_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158395$8286
+ cell $and $and$libresoc.v:158059$8234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158395$8286_Y
+ connect \Y $and$libresoc.v:158059$8234_Y
end
- connect \$1 $and$libresoc.v:158395$8286_Y
+ connect \$1 $and$libresoc.v:158059$8234_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158401.1-158412.10"
+attribute \src "libresoc.v:158065.1-158076.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n"
attribute \generator "nMigen"
module \n$49
- attribute \src "libresoc.v:158410.17-158410.111"
- wire $and$libresoc.v:158410$8287_Y
+ attribute \src "libresoc.v:158074.17-158074.111"
+ wire $and$libresoc.v:158074$8235_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158410$8287
+ cell $and $and$libresoc.v:158074$8235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158410$8287_Y
+ connect \Y $and$libresoc.v:158074$8235_Y
end
- connect \$1 $and$libresoc.v:158410$8287_Y
+ connect \$1 $and$libresoc.v:158074$8235_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158416.1-158427.10"
+attribute \src "libresoc.v:158080.1-158091.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n"
attribute \generator "nMigen"
module \n$53
- attribute \src "libresoc.v:158425.17-158425.111"
- wire $and$libresoc.v:158425$8288_Y
+ attribute \src "libresoc.v:158089.17-158089.111"
+ wire $and$libresoc.v:158089$8236_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158425$8288
+ cell $and $and$libresoc.v:158089$8236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158425$8288_Y
+ connect \Y $and$libresoc.v:158089$8236_Y
end
- connect \$1 $and$libresoc.v:158425$8288_Y
+ connect \$1 $and$libresoc.v:158089$8236_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158431.1-158442.10"
+attribute \src "libresoc.v:158095.1-158106.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n"
attribute \generator "nMigen"
module \n$6
- attribute \src "libresoc.v:158440.17-158440.111"
- wire $and$libresoc.v:158440$8289_Y
+ attribute \src "libresoc.v:158104.17-158104.111"
+ wire $and$libresoc.v:158104$8237_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158440$8289
+ cell $and $and$libresoc.v:158104$8237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158440$8289_Y
+ connect \Y $and$libresoc.v:158104$8237_Y
end
- connect \$1 $and$libresoc.v:158440$8289_Y
+ connect \$1 $and$libresoc.v:158104$8237_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158446.1-158457.10"
+attribute \src "libresoc.v:158110.1-158121.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n"
attribute \generator "nMigen"
module \n$63
- attribute \src "libresoc.v:158455.17-158455.111"
- wire $and$libresoc.v:158455$8290_Y
+ attribute \src "libresoc.v:158119.17-158119.111"
+ wire $and$libresoc.v:158119$8238_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158455$8290
+ cell $and $and$libresoc.v:158119$8238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158455$8290_Y
+ connect \Y $and$libresoc.v:158119$8238_Y
end
- connect \$1 $and$libresoc.v:158455$8290_Y
+ connect \$1 $and$libresoc.v:158119$8238_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158461.1-158472.10"
+attribute \src "libresoc.v:158125.1-158136.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n"
attribute \generator "nMigen"
module \n$66
- attribute \src "libresoc.v:158470.17-158470.111"
- wire $and$libresoc.v:158470$8291_Y
+ attribute \src "libresoc.v:158134.17-158134.111"
+ wire $and$libresoc.v:158134$8239_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158470$8291
+ cell $and $and$libresoc.v:158134$8239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158470$8291_Y
+ connect \Y $and$libresoc.v:158134$8239_Y
end
- connect \$1 $and$libresoc.v:158470$8291_Y
+ connect \$1 $and$libresoc.v:158134$8239_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158476.1-158487.10"
+attribute \src "libresoc.v:158140.1-158151.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n"
attribute \generator "nMigen"
module \n$75
- attribute \src "libresoc.v:158485.17-158485.111"
- wire $and$libresoc.v:158485$8292_Y
+ attribute \src "libresoc.v:158149.17-158149.111"
+ wire $and$libresoc.v:158149$8240_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158485$8292
+ cell $and $and$libresoc.v:158149$8240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158485$8292_Y
+ connect \Y $and$libresoc.v:158149$8240_Y
end
- connect \$1 $and$libresoc.v:158485$8292_Y
+ connect \$1 $and$libresoc.v:158149$8240_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158491.1-158502.10"
+attribute \src "libresoc.v:158155.1-158166.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n"
attribute \generator "nMigen"
module \n$77
- attribute \src "libresoc.v:158500.17-158500.111"
- wire $and$libresoc.v:158500$8293_Y
+ attribute \src "libresoc.v:158164.17-158164.111"
+ wire $and$libresoc.v:158164$8241_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158500$8293
+ cell $and $and$libresoc.v:158164$8241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158500$8293_Y
+ connect \Y $and$libresoc.v:158164$8241_Y
end
- connect \$1 $and$libresoc.v:158500$8293_Y
+ connect \$1 $and$libresoc.v:158164$8241_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158506.1-158517.10"
+attribute \src "libresoc.v:158170.1-158181.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n"
attribute \generator "nMigen"
module \n$8
- attribute \src "libresoc.v:158515.17-158515.111"
- wire $and$libresoc.v:158515$8294_Y
+ attribute \src "libresoc.v:158179.17-158179.111"
+ wire $and$libresoc.v:158179$8242_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158515$8294
+ cell $and $and$libresoc.v:158179$8242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158515$8294_Y
+ connect \Y $and$libresoc.v:158179$8242_Y
end
- connect \$1 $and$libresoc.v:158515$8294_Y
+ connect \$1 $and$libresoc.v:158179$8242_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158521.1-158532.10"
+attribute \src "libresoc.v:158185.1-158196.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n"
attribute \generator "nMigen"
module \n$80
- attribute \src "libresoc.v:158530.17-158530.111"
- wire $and$libresoc.v:158530$8295_Y
+ attribute \src "libresoc.v:158194.17-158194.111"
+ wire $and$libresoc.v:158194$8243_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158530$8295
+ cell $and $and$libresoc.v:158194$8243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158530$8295_Y
+ connect \Y $and$libresoc.v:158194$8243_Y
end
- connect \$1 $and$libresoc.v:158530$8295_Y
+ connect \$1 $and$libresoc.v:158194$8243_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158536.1-158547.10"
+attribute \src "libresoc.v:158200.1-158211.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n"
attribute \generator "nMigen"
module \n$82
- attribute \src "libresoc.v:158545.17-158545.111"
- wire $and$libresoc.v:158545$8296_Y
+ attribute \src "libresoc.v:158209.17-158209.111"
+ wire $and$libresoc.v:158209$8244_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158545$8296
+ cell $and $and$libresoc.v:158209$8244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158545$8296_Y
+ connect \Y $and$libresoc.v:158209$8244_Y
end
- connect \$1 $and$libresoc.v:158545$8296_Y
+ connect \$1 $and$libresoc.v:158209$8244_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158551.1-158562.10"
+attribute \src "libresoc.v:158215.1-158226.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n"
attribute \generator "nMigen"
module \n$92
- attribute \src "libresoc.v:158560.17-158560.111"
- wire $and$libresoc.v:158560$8297_Y
+ attribute \src "libresoc.v:158224.17-158224.111"
+ wire $and$libresoc.v:158224$8245_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158560$8297
+ cell $and $and$libresoc.v:158224$8245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158560$8297_Y
+ connect \Y $and$libresoc.v:158224$8245_Y
end
- connect \$1 $and$libresoc.v:158560$8297_Y
+ connect \$1 $and$libresoc.v:158224$8245_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158566.1-158577.10"
+attribute \src "libresoc.v:158230.1-158241.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n"
attribute \generator "nMigen"
module \n$94
- attribute \src "libresoc.v:158575.17-158575.111"
- wire $and$libresoc.v:158575$8298_Y
+ attribute \src "libresoc.v:158239.17-158239.111"
+ wire $and$libresoc.v:158239$8246_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158575$8298
+ cell $and $and$libresoc.v:158239$8246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158575$8298_Y
+ connect \Y $and$libresoc.v:158239$8246_Y
end
- connect \$1 $and$libresoc.v:158575$8298_Y
+ connect \$1 $and$libresoc.v:158239$8246_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158581.1-158592.10"
+attribute \src "libresoc.v:158245.1-158256.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n"
attribute \generator "nMigen"
module \n$97
- attribute \src "libresoc.v:158590.17-158590.111"
- wire $and$libresoc.v:158590$8299_Y
+ attribute \src "libresoc.v:158254.17-158254.111"
+ wire $and$libresoc.v:158254$8247_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158590$8299
+ cell $and $and$libresoc.v:158254$8247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158590$8299_Y
+ connect \Y $and$libresoc.v:158254$8247_Y
end
- connect \$1 $and$libresoc.v:158590$8299_Y
+ connect \$1 $and$libresoc.v:158254$8247_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158596.1-158607.10"
+attribute \src "libresoc.v:158260.1-158271.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n"
attribute \generator "nMigen"
module \n$99
- attribute \src "libresoc.v:158605.17-158605.111"
- wire $and$libresoc.v:158605$8300_Y
+ attribute \src "libresoc.v:158269.17-158269.111"
+ wire $and$libresoc.v:158269$8248_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:158605$8300
+ cell $and $and$libresoc.v:158269$8248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:158605$8300_Y
+ connect \Y $and$libresoc.v:158269$8248_Y
end
- connect \$1 $and$libresoc.v:158605$8300_Y
+ connect \$1 $and$libresoc.v:158269$8248_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:158611.1-158669.10"
+attribute \src "libresoc.v:158275.1-158333.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l"
attribute \generator "nMigen"
module \opc_l
- attribute \src "libresoc.v:158612.7-158612.20"
+ attribute \src "libresoc.v:158276.7-158276.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158657.3-158665.6"
- wire $0\q_int$next[0:0]$8311
- attribute \src "libresoc.v:158655.3-158656.27"
+ attribute \src "libresoc.v:158321.3-158329.6"
+ wire $0\q_int$next[0:0]$8259
+ attribute \src "libresoc.v:158319.3-158320.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158657.3-158665.6"
- wire $1\q_int$next[0:0]$8312
- attribute \src "libresoc.v:158634.7-158634.19"
+ attribute \src "libresoc.v:158321.3-158329.6"
+ wire $1\q_int$next[0:0]$8260
+ attribute \src "libresoc.v:158298.7-158298.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158647.17-158647.96"
- wire $and$libresoc.v:158647$8301_Y
- attribute \src "libresoc.v:158652.17-158652.96"
- wire $and$libresoc.v:158652$8306_Y
- attribute \src "libresoc.v:158649.18-158649.93"
- wire $not$libresoc.v:158649$8303_Y
- attribute \src "libresoc.v:158651.17-158651.92"
- wire $not$libresoc.v:158651$8305_Y
- attribute \src "libresoc.v:158654.17-158654.92"
- wire $not$libresoc.v:158654$8308_Y
- attribute \src "libresoc.v:158648.18-158648.98"
- wire $or$libresoc.v:158648$8302_Y
- attribute \src "libresoc.v:158650.18-158650.99"
- wire $or$libresoc.v:158650$8304_Y
- attribute \src "libresoc.v:158653.17-158653.97"
- wire $or$libresoc.v:158653$8307_Y
+ attribute \src "libresoc.v:158311.17-158311.96"
+ wire $and$libresoc.v:158311$8249_Y
+ attribute \src "libresoc.v:158316.17-158316.96"
+ wire $and$libresoc.v:158316$8254_Y
+ attribute \src "libresoc.v:158313.18-158313.93"
+ wire $not$libresoc.v:158313$8251_Y
+ attribute \src "libresoc.v:158315.17-158315.92"
+ wire $not$libresoc.v:158315$8253_Y
+ attribute \src "libresoc.v:158318.17-158318.92"
+ wire $not$libresoc.v:158318$8256_Y
+ attribute \src "libresoc.v:158312.18-158312.98"
+ wire $or$libresoc.v:158312$8250_Y
+ attribute \src "libresoc.v:158314.18-158314.99"
+ wire $or$libresoc.v:158314$8252_Y
+ attribute \src "libresoc.v:158317.17-158317.97"
+ wire $or$libresoc.v:158317$8255_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158612.7-158612.15"
+ attribute \src "libresoc.v:158276.7-158276.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158647$8301
+ cell $and $and$libresoc.v:158311$8249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158647$8301_Y
+ connect \Y $and$libresoc.v:158311$8249_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158652$8306
+ cell $and $and$libresoc.v:158316$8254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158652$8306_Y
+ connect \Y $and$libresoc.v:158316$8254_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158649$8303
+ cell $not $not$libresoc.v:158313$8251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158649$8303_Y
+ connect \Y $not$libresoc.v:158313$8251_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158651$8305
+ cell $not $not$libresoc.v:158315$8253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158651$8305_Y
+ connect \Y $not$libresoc.v:158315$8253_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158654$8308
+ cell $not $not$libresoc.v:158318$8256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158654$8308_Y
+ connect \Y $not$libresoc.v:158318$8256_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158648$8302
+ cell $or $or$libresoc.v:158312$8250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158648$8302_Y
+ connect \Y $or$libresoc.v:158312$8250_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158650$8304
+ cell $or $or$libresoc.v:158314$8252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158650$8304_Y
+ connect \Y $or$libresoc.v:158314$8252_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158653$8307
+ cell $or $or$libresoc.v:158317$8255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158653$8307_Y
+ connect \Y $or$libresoc.v:158317$8255_Y
end
- attribute \src "libresoc.v:158612.7-158612.20"
- process $proc$libresoc.v:158612$8313
+ attribute \src "libresoc.v:158276.7-158276.20"
+ process $proc$libresoc.v:158276$8261
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158634.7-158634.19"
- process $proc$libresoc.v:158634$8314
+ attribute \src "libresoc.v:158298.7-158298.19"
+ process $proc$libresoc.v:158298$8262
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158655.3-158656.27"
- process $proc$libresoc.v:158655$8309
+ attribute \src "libresoc.v:158319.3-158320.27"
+ process $proc$libresoc.v:158319$8257
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158657.3-158665.6"
- process $proc$libresoc.v:158657$8310
+ attribute \src "libresoc.v:158321.3-158329.6"
+ process $proc$libresoc.v:158321$8258
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8311 $1\q_int$next[0:0]$8312
- attribute \src "libresoc.v:158658.5-158658.29"
+ assign $0\q_int$next[0:0]$8259 $1\q_int$next[0:0]$8260
+ attribute \src "libresoc.v:158322.5-158322.29"
switch \initial
- attribute \src "libresoc.v:158658.9-158658.17"
+ attribute \src "libresoc.v:158322.9-158322.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8312 1'0
+ assign $1\q_int$next[0:0]$8260 1'0
case
- assign $1\q_int$next[0:0]$8312 \$5
+ assign $1\q_int$next[0:0]$8260 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8311
+ update \q_int$next $0\q_int$next[0:0]$8259
end
- connect \$9 $and$libresoc.v:158647$8301_Y
- connect \$11 $or$libresoc.v:158648$8302_Y
- connect \$13 $not$libresoc.v:158649$8303_Y
- connect \$15 $or$libresoc.v:158650$8304_Y
- connect \$1 $not$libresoc.v:158651$8305_Y
- connect \$3 $and$libresoc.v:158652$8306_Y
- connect \$5 $or$libresoc.v:158653$8307_Y
- connect \$7 $not$libresoc.v:158654$8308_Y
+ connect \$9 $and$libresoc.v:158311$8249_Y
+ connect \$11 $or$libresoc.v:158312$8250_Y
+ connect \$13 $not$libresoc.v:158313$8251_Y
+ connect \$15 $or$libresoc.v:158314$8252_Y
+ connect \$1 $not$libresoc.v:158315$8253_Y
+ connect \$3 $and$libresoc.v:158316$8254_Y
+ connect \$5 $or$libresoc.v:158317$8255_Y
+ connect \$7 $not$libresoc.v:158318$8256_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158673.1-158731.10"
+attribute \src "libresoc.v:158337.1-158395.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l"
attribute \generator "nMigen"
module \opc_l$102
- attribute \src "libresoc.v:158674.7-158674.20"
+ attribute \src "libresoc.v:158338.7-158338.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158719.3-158727.6"
- wire $0\q_int$next[0:0]$8325
- attribute \src "libresoc.v:158717.3-158718.27"
+ attribute \src "libresoc.v:158383.3-158391.6"
+ wire $0\q_int$next[0:0]$8273
+ attribute \src "libresoc.v:158381.3-158382.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158719.3-158727.6"
- wire $1\q_int$next[0:0]$8326
- attribute \src "libresoc.v:158696.7-158696.19"
+ attribute \src "libresoc.v:158383.3-158391.6"
+ wire $1\q_int$next[0:0]$8274
+ attribute \src "libresoc.v:158360.7-158360.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158709.17-158709.96"
- wire $and$libresoc.v:158709$8315_Y
- attribute \src "libresoc.v:158714.17-158714.96"
- wire $and$libresoc.v:158714$8320_Y
- attribute \src "libresoc.v:158711.18-158711.93"
- wire $not$libresoc.v:158711$8317_Y
- attribute \src "libresoc.v:158713.17-158713.92"
- wire $not$libresoc.v:158713$8319_Y
- attribute \src "libresoc.v:158716.17-158716.92"
- wire $not$libresoc.v:158716$8322_Y
- attribute \src "libresoc.v:158710.18-158710.98"
- wire $or$libresoc.v:158710$8316_Y
- attribute \src "libresoc.v:158712.18-158712.99"
- wire $or$libresoc.v:158712$8318_Y
- attribute \src "libresoc.v:158715.17-158715.97"
- wire $or$libresoc.v:158715$8321_Y
+ attribute \src "libresoc.v:158373.17-158373.96"
+ wire $and$libresoc.v:158373$8263_Y
+ attribute \src "libresoc.v:158378.17-158378.96"
+ wire $and$libresoc.v:158378$8268_Y
+ attribute \src "libresoc.v:158375.18-158375.93"
+ wire $not$libresoc.v:158375$8265_Y
+ attribute \src "libresoc.v:158377.17-158377.92"
+ wire $not$libresoc.v:158377$8267_Y
+ attribute \src "libresoc.v:158380.17-158380.92"
+ wire $not$libresoc.v:158380$8270_Y
+ attribute \src "libresoc.v:158374.18-158374.98"
+ wire $or$libresoc.v:158374$8264_Y
+ attribute \src "libresoc.v:158376.18-158376.99"
+ wire $or$libresoc.v:158376$8266_Y
+ attribute \src "libresoc.v:158379.17-158379.97"
+ wire $or$libresoc.v:158379$8269_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158674.7-158674.15"
+ attribute \src "libresoc.v:158338.7-158338.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158709$8315
+ cell $and $and$libresoc.v:158373$8263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158709$8315_Y
+ connect \Y $and$libresoc.v:158373$8263_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158714$8320
+ cell $and $and$libresoc.v:158378$8268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158714$8320_Y
+ connect \Y $and$libresoc.v:158378$8268_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158711$8317
+ cell $not $not$libresoc.v:158375$8265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158711$8317_Y
+ connect \Y $not$libresoc.v:158375$8265_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158713$8319
+ cell $not $not$libresoc.v:158377$8267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158713$8319_Y
+ connect \Y $not$libresoc.v:158377$8267_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158716$8322
+ cell $not $not$libresoc.v:158380$8270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158716$8322_Y
+ connect \Y $not$libresoc.v:158380$8270_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158710$8316
+ cell $or $or$libresoc.v:158374$8264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158710$8316_Y
+ connect \Y $or$libresoc.v:158374$8264_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158712$8318
+ cell $or $or$libresoc.v:158376$8266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158712$8318_Y
+ connect \Y $or$libresoc.v:158376$8266_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158715$8321
+ cell $or $or$libresoc.v:158379$8269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158715$8321_Y
+ connect \Y $or$libresoc.v:158379$8269_Y
end
- attribute \src "libresoc.v:158674.7-158674.20"
- process $proc$libresoc.v:158674$8327
+ attribute \src "libresoc.v:158338.7-158338.20"
+ process $proc$libresoc.v:158338$8275
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158696.7-158696.19"
- process $proc$libresoc.v:158696$8328
+ attribute \src "libresoc.v:158360.7-158360.19"
+ process $proc$libresoc.v:158360$8276
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158717.3-158718.27"
- process $proc$libresoc.v:158717$8323
+ attribute \src "libresoc.v:158381.3-158382.27"
+ process $proc$libresoc.v:158381$8271
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158719.3-158727.6"
- process $proc$libresoc.v:158719$8324
+ attribute \src "libresoc.v:158383.3-158391.6"
+ process $proc$libresoc.v:158383$8272
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8325 $1\q_int$next[0:0]$8326
- attribute \src "libresoc.v:158720.5-158720.29"
+ assign $0\q_int$next[0:0]$8273 $1\q_int$next[0:0]$8274
+ attribute \src "libresoc.v:158384.5-158384.29"
switch \initial
- attribute \src "libresoc.v:158720.9-158720.17"
+ attribute \src "libresoc.v:158384.9-158384.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8326 1'0
+ assign $1\q_int$next[0:0]$8274 1'0
case
- assign $1\q_int$next[0:0]$8326 \$5
+ assign $1\q_int$next[0:0]$8274 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8325
+ update \q_int$next $0\q_int$next[0:0]$8273
end
- connect \$9 $and$libresoc.v:158709$8315_Y
- connect \$11 $or$libresoc.v:158710$8316_Y
- connect \$13 $not$libresoc.v:158711$8317_Y
- connect \$15 $or$libresoc.v:158712$8318_Y
- connect \$1 $not$libresoc.v:158713$8319_Y
- connect \$3 $and$libresoc.v:158714$8320_Y
- connect \$5 $or$libresoc.v:158715$8321_Y
- connect \$7 $not$libresoc.v:158716$8322_Y
+ connect \$9 $and$libresoc.v:158373$8263_Y
+ connect \$11 $or$libresoc.v:158374$8264_Y
+ connect \$13 $not$libresoc.v:158375$8265_Y
+ connect \$15 $or$libresoc.v:158376$8266_Y
+ connect \$1 $not$libresoc.v:158377$8267_Y
+ connect \$3 $and$libresoc.v:158378$8268_Y
+ connect \$5 $or$libresoc.v:158379$8269_Y
+ connect \$7 $not$libresoc.v:158380$8270_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158735.1-158793.10"
+attribute \src "libresoc.v:158399.1-158457.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l"
attribute \generator "nMigen"
module \opc_l$11
- attribute \src "libresoc.v:158736.7-158736.20"
+ attribute \src "libresoc.v:158400.7-158400.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158781.3-158789.6"
- wire $0\q_int$next[0:0]$8339
- attribute \src "libresoc.v:158779.3-158780.27"
+ attribute \src "libresoc.v:158445.3-158453.6"
+ wire $0\q_int$next[0:0]$8287
+ attribute \src "libresoc.v:158443.3-158444.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158781.3-158789.6"
- wire $1\q_int$next[0:0]$8340
- attribute \src "libresoc.v:158758.7-158758.19"
+ attribute \src "libresoc.v:158445.3-158453.6"
+ wire $1\q_int$next[0:0]$8288
+ attribute \src "libresoc.v:158422.7-158422.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158771.17-158771.96"
- wire $and$libresoc.v:158771$8329_Y
- attribute \src "libresoc.v:158776.17-158776.96"
- wire $and$libresoc.v:158776$8334_Y
- attribute \src "libresoc.v:158773.18-158773.93"
- wire $not$libresoc.v:158773$8331_Y
- attribute \src "libresoc.v:158775.17-158775.92"
- wire $not$libresoc.v:158775$8333_Y
- attribute \src "libresoc.v:158778.17-158778.92"
- wire $not$libresoc.v:158778$8336_Y
- attribute \src "libresoc.v:158772.18-158772.98"
- wire $or$libresoc.v:158772$8330_Y
- attribute \src "libresoc.v:158774.18-158774.99"
- wire $or$libresoc.v:158774$8332_Y
- attribute \src "libresoc.v:158777.17-158777.97"
- wire $or$libresoc.v:158777$8335_Y
+ attribute \src "libresoc.v:158435.17-158435.96"
+ wire $and$libresoc.v:158435$8277_Y
+ attribute \src "libresoc.v:158440.17-158440.96"
+ wire $and$libresoc.v:158440$8282_Y
+ attribute \src "libresoc.v:158437.18-158437.93"
+ wire $not$libresoc.v:158437$8279_Y
+ attribute \src "libresoc.v:158439.17-158439.92"
+ wire $not$libresoc.v:158439$8281_Y
+ attribute \src "libresoc.v:158442.17-158442.92"
+ wire $not$libresoc.v:158442$8284_Y
+ attribute \src "libresoc.v:158436.18-158436.98"
+ wire $or$libresoc.v:158436$8278_Y
+ attribute \src "libresoc.v:158438.18-158438.99"
+ wire $or$libresoc.v:158438$8280_Y
+ attribute \src "libresoc.v:158441.17-158441.97"
+ wire $or$libresoc.v:158441$8283_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158736.7-158736.15"
+ attribute \src "libresoc.v:158400.7-158400.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158771$8329
+ cell $and $and$libresoc.v:158435$8277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158771$8329_Y
+ connect \Y $and$libresoc.v:158435$8277_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158776$8334
+ cell $and $and$libresoc.v:158440$8282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158776$8334_Y
+ connect \Y $and$libresoc.v:158440$8282_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158773$8331
+ cell $not $not$libresoc.v:158437$8279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158773$8331_Y
+ connect \Y $not$libresoc.v:158437$8279_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158775$8333
+ cell $not $not$libresoc.v:158439$8281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158775$8333_Y
+ connect \Y $not$libresoc.v:158439$8281_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158778$8336
+ cell $not $not$libresoc.v:158442$8284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158778$8336_Y
+ connect \Y $not$libresoc.v:158442$8284_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158772$8330
+ cell $or $or$libresoc.v:158436$8278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158772$8330_Y
+ connect \Y $or$libresoc.v:158436$8278_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158774$8332
+ cell $or $or$libresoc.v:158438$8280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158774$8332_Y
+ connect \Y $or$libresoc.v:158438$8280_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158777$8335
+ cell $or $or$libresoc.v:158441$8283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158777$8335_Y
+ connect \Y $or$libresoc.v:158441$8283_Y
end
- attribute \src "libresoc.v:158736.7-158736.20"
- process $proc$libresoc.v:158736$8341
+ attribute \src "libresoc.v:158400.7-158400.20"
+ process $proc$libresoc.v:158400$8289
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158758.7-158758.19"
- process $proc$libresoc.v:158758$8342
+ attribute \src "libresoc.v:158422.7-158422.19"
+ process $proc$libresoc.v:158422$8290
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158779.3-158780.27"
- process $proc$libresoc.v:158779$8337
+ attribute \src "libresoc.v:158443.3-158444.27"
+ process $proc$libresoc.v:158443$8285
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158781.3-158789.6"
- process $proc$libresoc.v:158781$8338
+ attribute \src "libresoc.v:158445.3-158453.6"
+ process $proc$libresoc.v:158445$8286
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8339 $1\q_int$next[0:0]$8340
- attribute \src "libresoc.v:158782.5-158782.29"
+ assign $0\q_int$next[0:0]$8287 $1\q_int$next[0:0]$8288
+ attribute \src "libresoc.v:158446.5-158446.29"
switch \initial
- attribute \src "libresoc.v:158782.9-158782.17"
+ attribute \src "libresoc.v:158446.9-158446.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8340 1'0
+ assign $1\q_int$next[0:0]$8288 1'0
case
- assign $1\q_int$next[0:0]$8340 \$5
+ assign $1\q_int$next[0:0]$8288 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8339
+ update \q_int$next $0\q_int$next[0:0]$8287
end
- connect \$9 $and$libresoc.v:158771$8329_Y
- connect \$11 $or$libresoc.v:158772$8330_Y
- connect \$13 $not$libresoc.v:158773$8331_Y
- connect \$15 $or$libresoc.v:158774$8332_Y
- connect \$1 $not$libresoc.v:158775$8333_Y
- connect \$3 $and$libresoc.v:158776$8334_Y
- connect \$5 $or$libresoc.v:158777$8335_Y
- connect \$7 $not$libresoc.v:158778$8336_Y
+ connect \$9 $and$libresoc.v:158435$8277_Y
+ connect \$11 $or$libresoc.v:158436$8278_Y
+ connect \$13 $not$libresoc.v:158437$8279_Y
+ connect \$15 $or$libresoc.v:158438$8280_Y
+ connect \$1 $not$libresoc.v:158439$8281_Y
+ connect \$3 $and$libresoc.v:158440$8282_Y
+ connect \$5 $or$libresoc.v:158441$8283_Y
+ connect \$7 $not$libresoc.v:158442$8284_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158797.1-158855.10"
+attribute \src "libresoc.v:158461.1-158519.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l"
attribute \generator "nMigen"
module \opc_l$120
- attribute \src "libresoc.v:158798.7-158798.20"
+ attribute \src "libresoc.v:158462.7-158462.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158843.3-158851.6"
- wire $0\q_int$next[0:0]$8353
- attribute \src "libresoc.v:158841.3-158842.27"
+ attribute \src "libresoc.v:158507.3-158515.6"
+ wire $0\q_int$next[0:0]$8301
+ attribute \src "libresoc.v:158505.3-158506.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158843.3-158851.6"
- wire $1\q_int$next[0:0]$8354
- attribute \src "libresoc.v:158820.7-158820.19"
+ attribute \src "libresoc.v:158507.3-158515.6"
+ wire $1\q_int$next[0:0]$8302
+ attribute \src "libresoc.v:158484.7-158484.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158833.17-158833.96"
- wire $and$libresoc.v:158833$8343_Y
- attribute \src "libresoc.v:158838.17-158838.96"
- wire $and$libresoc.v:158838$8348_Y
- attribute \src "libresoc.v:158835.18-158835.93"
- wire $not$libresoc.v:158835$8345_Y
- attribute \src "libresoc.v:158837.17-158837.92"
- wire $not$libresoc.v:158837$8347_Y
- attribute \src "libresoc.v:158840.17-158840.92"
- wire $not$libresoc.v:158840$8350_Y
- attribute \src "libresoc.v:158834.18-158834.98"
- wire $or$libresoc.v:158834$8344_Y
- attribute \src "libresoc.v:158836.18-158836.99"
- wire $or$libresoc.v:158836$8346_Y
- attribute \src "libresoc.v:158839.17-158839.97"
- wire $or$libresoc.v:158839$8349_Y
+ attribute \src "libresoc.v:158497.17-158497.96"
+ wire $and$libresoc.v:158497$8291_Y
+ attribute \src "libresoc.v:158502.17-158502.96"
+ wire $and$libresoc.v:158502$8296_Y
+ attribute \src "libresoc.v:158499.18-158499.93"
+ wire $not$libresoc.v:158499$8293_Y
+ attribute \src "libresoc.v:158501.17-158501.92"
+ wire $not$libresoc.v:158501$8295_Y
+ attribute \src "libresoc.v:158504.17-158504.92"
+ wire $not$libresoc.v:158504$8298_Y
+ attribute \src "libresoc.v:158498.18-158498.98"
+ wire $or$libresoc.v:158498$8292_Y
+ attribute \src "libresoc.v:158500.18-158500.99"
+ wire $or$libresoc.v:158500$8294_Y
+ attribute \src "libresoc.v:158503.17-158503.97"
+ wire $or$libresoc.v:158503$8297_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158798.7-158798.15"
+ attribute \src "libresoc.v:158462.7-158462.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158833$8343
+ cell $and $and$libresoc.v:158497$8291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158833$8343_Y
+ connect \Y $and$libresoc.v:158497$8291_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158838$8348
+ cell $and $and$libresoc.v:158502$8296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158838$8348_Y
+ connect \Y $and$libresoc.v:158502$8296_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158835$8345
+ cell $not $not$libresoc.v:158499$8293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158835$8345_Y
+ connect \Y $not$libresoc.v:158499$8293_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158837$8347
+ cell $not $not$libresoc.v:158501$8295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158837$8347_Y
+ connect \Y $not$libresoc.v:158501$8295_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158840$8350
+ cell $not $not$libresoc.v:158504$8298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158840$8350_Y
+ connect \Y $not$libresoc.v:158504$8298_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158834$8344
+ cell $or $or$libresoc.v:158498$8292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158834$8344_Y
+ connect \Y $or$libresoc.v:158498$8292_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158836$8346
+ cell $or $or$libresoc.v:158500$8294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158836$8346_Y
+ connect \Y $or$libresoc.v:158500$8294_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158839$8349
+ cell $or $or$libresoc.v:158503$8297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158839$8349_Y
+ connect \Y $or$libresoc.v:158503$8297_Y
end
- attribute \src "libresoc.v:158798.7-158798.20"
- process $proc$libresoc.v:158798$8355
+ attribute \src "libresoc.v:158462.7-158462.20"
+ process $proc$libresoc.v:158462$8303
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158820.7-158820.19"
- process $proc$libresoc.v:158820$8356
+ attribute \src "libresoc.v:158484.7-158484.19"
+ process $proc$libresoc.v:158484$8304
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158841.3-158842.27"
- process $proc$libresoc.v:158841$8351
+ attribute \src "libresoc.v:158505.3-158506.27"
+ process $proc$libresoc.v:158505$8299
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158843.3-158851.6"
- process $proc$libresoc.v:158843$8352
+ attribute \src "libresoc.v:158507.3-158515.6"
+ process $proc$libresoc.v:158507$8300
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8353 $1\q_int$next[0:0]$8354
- attribute \src "libresoc.v:158844.5-158844.29"
+ assign $0\q_int$next[0:0]$8301 $1\q_int$next[0:0]$8302
+ attribute \src "libresoc.v:158508.5-158508.29"
switch \initial
- attribute \src "libresoc.v:158844.9-158844.17"
+ attribute \src "libresoc.v:158508.9-158508.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8354 1'0
+ assign $1\q_int$next[0:0]$8302 1'0
case
- assign $1\q_int$next[0:0]$8354 \$5
+ assign $1\q_int$next[0:0]$8302 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8353
+ update \q_int$next $0\q_int$next[0:0]$8301
end
- connect \$9 $and$libresoc.v:158833$8343_Y
- connect \$11 $or$libresoc.v:158834$8344_Y
- connect \$13 $not$libresoc.v:158835$8345_Y
- connect \$15 $or$libresoc.v:158836$8346_Y
- connect \$1 $not$libresoc.v:158837$8347_Y
- connect \$3 $and$libresoc.v:158838$8348_Y
- connect \$5 $or$libresoc.v:158839$8349_Y
- connect \$7 $not$libresoc.v:158840$8350_Y
+ connect \$9 $and$libresoc.v:158497$8291_Y
+ connect \$11 $or$libresoc.v:158498$8292_Y
+ connect \$13 $not$libresoc.v:158499$8293_Y
+ connect \$15 $or$libresoc.v:158500$8294_Y
+ connect \$1 $not$libresoc.v:158501$8295_Y
+ connect \$3 $and$libresoc.v:158502$8296_Y
+ connect \$5 $or$libresoc.v:158503$8297_Y
+ connect \$7 $not$libresoc.v:158504$8298_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158859.1-158917.10"
+attribute \src "libresoc.v:158523.1-158581.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l"
attribute \generator "nMigen"
module \opc_l$126
- attribute \src "libresoc.v:158860.7-158860.20"
+ attribute \src "libresoc.v:158524.7-158524.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158905.3-158913.6"
- wire $0\q_int$next[0:0]$8367
- attribute \src "libresoc.v:158903.3-158904.27"
+ attribute \src "libresoc.v:158569.3-158577.6"
+ wire $0\q_int$next[0:0]$8315
+ attribute \src "libresoc.v:158567.3-158568.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158905.3-158913.6"
- wire $1\q_int$next[0:0]$8368
- attribute \src "libresoc.v:158882.7-158882.19"
+ attribute \src "libresoc.v:158569.3-158577.6"
+ wire $1\q_int$next[0:0]$8316
+ attribute \src "libresoc.v:158546.7-158546.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158895.17-158895.96"
- wire $and$libresoc.v:158895$8357_Y
- attribute \src "libresoc.v:158900.17-158900.96"
- wire $and$libresoc.v:158900$8362_Y
- attribute \src "libresoc.v:158897.18-158897.93"
- wire $not$libresoc.v:158897$8359_Y
- attribute \src "libresoc.v:158899.17-158899.92"
- wire $not$libresoc.v:158899$8361_Y
- attribute \src "libresoc.v:158902.17-158902.92"
- wire $not$libresoc.v:158902$8364_Y
- attribute \src "libresoc.v:158896.18-158896.98"
- wire $or$libresoc.v:158896$8358_Y
- attribute \src "libresoc.v:158898.18-158898.99"
- wire $or$libresoc.v:158898$8360_Y
- attribute \src "libresoc.v:158901.17-158901.97"
- wire $or$libresoc.v:158901$8363_Y
+ attribute \src "libresoc.v:158559.17-158559.96"
+ wire $and$libresoc.v:158559$8305_Y
+ attribute \src "libresoc.v:158564.17-158564.96"
+ wire $and$libresoc.v:158564$8310_Y
+ attribute \src "libresoc.v:158561.18-158561.93"
+ wire $not$libresoc.v:158561$8307_Y
+ attribute \src "libresoc.v:158563.17-158563.92"
+ wire $not$libresoc.v:158563$8309_Y
+ attribute \src "libresoc.v:158566.17-158566.92"
+ wire $not$libresoc.v:158566$8312_Y
+ attribute \src "libresoc.v:158560.18-158560.98"
+ wire $or$libresoc.v:158560$8306_Y
+ attribute \src "libresoc.v:158562.18-158562.99"
+ wire $or$libresoc.v:158562$8308_Y
+ attribute \src "libresoc.v:158565.17-158565.97"
+ wire $or$libresoc.v:158565$8311_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158860.7-158860.15"
+ attribute \src "libresoc.v:158524.7-158524.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158895$8357
+ cell $and $and$libresoc.v:158559$8305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158895$8357_Y
+ connect \Y $and$libresoc.v:158559$8305_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158900$8362
+ cell $and $and$libresoc.v:158564$8310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158900$8362_Y
+ connect \Y $and$libresoc.v:158564$8310_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158897$8359
+ cell $not $not$libresoc.v:158561$8307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158897$8359_Y
+ connect \Y $not$libresoc.v:158561$8307_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158899$8361
+ cell $not $not$libresoc.v:158563$8309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158899$8361_Y
+ connect \Y $not$libresoc.v:158563$8309_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158902$8364
+ cell $not $not$libresoc.v:158566$8312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158902$8364_Y
+ connect \Y $not$libresoc.v:158566$8312_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158896$8358
+ cell $or $or$libresoc.v:158560$8306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158896$8358_Y
+ connect \Y $or$libresoc.v:158560$8306_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158898$8360
+ cell $or $or$libresoc.v:158562$8308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158898$8360_Y
+ connect \Y $or$libresoc.v:158562$8308_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158901$8363
+ cell $or $or$libresoc.v:158565$8311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158901$8363_Y
+ connect \Y $or$libresoc.v:158565$8311_Y
end
- attribute \src "libresoc.v:158860.7-158860.20"
- process $proc$libresoc.v:158860$8369
+ attribute \src "libresoc.v:158524.7-158524.20"
+ process $proc$libresoc.v:158524$8317
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158882.7-158882.19"
- process $proc$libresoc.v:158882$8370
+ attribute \src "libresoc.v:158546.7-158546.19"
+ process $proc$libresoc.v:158546$8318
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158903.3-158904.27"
- process $proc$libresoc.v:158903$8365
+ attribute \src "libresoc.v:158567.3-158568.27"
+ process $proc$libresoc.v:158567$8313
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158905.3-158913.6"
- process $proc$libresoc.v:158905$8366
+ attribute \src "libresoc.v:158569.3-158577.6"
+ process $proc$libresoc.v:158569$8314
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8367 $1\q_int$next[0:0]$8368
- attribute \src "libresoc.v:158906.5-158906.29"
+ assign $0\q_int$next[0:0]$8315 $1\q_int$next[0:0]$8316
+ attribute \src "libresoc.v:158570.5-158570.29"
switch \initial
- attribute \src "libresoc.v:158906.9-158906.17"
+ attribute \src "libresoc.v:158570.9-158570.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8368 1'0
+ assign $1\q_int$next[0:0]$8316 1'0
case
- assign $1\q_int$next[0:0]$8368 \$5
+ assign $1\q_int$next[0:0]$8316 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8367
+ update \q_int$next $0\q_int$next[0:0]$8315
end
- connect \$9 $and$libresoc.v:158895$8357_Y
- connect \$11 $or$libresoc.v:158896$8358_Y
- connect \$13 $not$libresoc.v:158897$8359_Y
- connect \$15 $or$libresoc.v:158898$8360_Y
- connect \$1 $not$libresoc.v:158899$8361_Y
- connect \$3 $and$libresoc.v:158900$8362_Y
- connect \$5 $or$libresoc.v:158901$8363_Y
- connect \$7 $not$libresoc.v:158902$8364_Y
+ connect \$9 $and$libresoc.v:158559$8305_Y
+ connect \$11 $or$libresoc.v:158560$8306_Y
+ connect \$13 $not$libresoc.v:158561$8307_Y
+ connect \$15 $or$libresoc.v:158562$8308_Y
+ connect \$1 $not$libresoc.v:158563$8309_Y
+ connect \$3 $and$libresoc.v:158564$8310_Y
+ connect \$5 $or$libresoc.v:158565$8311_Y
+ connect \$7 $not$libresoc.v:158566$8312_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158921.1-158979.10"
+attribute \src "libresoc.v:158585.1-158643.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l"
attribute \generator "nMigen"
module \opc_l$24
- attribute \src "libresoc.v:158922.7-158922.20"
+ attribute \src "libresoc.v:158586.7-158586.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158967.3-158975.6"
- wire $0\q_int$next[0:0]$8381
- attribute \src "libresoc.v:158965.3-158966.27"
+ attribute \src "libresoc.v:158631.3-158639.6"
+ wire $0\q_int$next[0:0]$8329
+ attribute \src "libresoc.v:158629.3-158630.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:158967.3-158975.6"
- wire $1\q_int$next[0:0]$8382
- attribute \src "libresoc.v:158944.7-158944.19"
+ attribute \src "libresoc.v:158631.3-158639.6"
+ wire $1\q_int$next[0:0]$8330
+ attribute \src "libresoc.v:158608.7-158608.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:158957.17-158957.96"
- wire $and$libresoc.v:158957$8371_Y
- attribute \src "libresoc.v:158962.17-158962.96"
- wire $and$libresoc.v:158962$8376_Y
- attribute \src "libresoc.v:158959.18-158959.93"
- wire $not$libresoc.v:158959$8373_Y
- attribute \src "libresoc.v:158961.17-158961.92"
- wire $not$libresoc.v:158961$8375_Y
- attribute \src "libresoc.v:158964.17-158964.92"
- wire $not$libresoc.v:158964$8378_Y
- attribute \src "libresoc.v:158958.18-158958.98"
- wire $or$libresoc.v:158958$8372_Y
- attribute \src "libresoc.v:158960.18-158960.99"
- wire $or$libresoc.v:158960$8374_Y
- attribute \src "libresoc.v:158963.17-158963.97"
- wire $or$libresoc.v:158963$8377_Y
+ attribute \src "libresoc.v:158621.17-158621.96"
+ wire $and$libresoc.v:158621$8319_Y
+ attribute \src "libresoc.v:158626.17-158626.96"
+ wire $and$libresoc.v:158626$8324_Y
+ attribute \src "libresoc.v:158623.18-158623.93"
+ wire $not$libresoc.v:158623$8321_Y
+ attribute \src "libresoc.v:158625.17-158625.92"
+ wire $not$libresoc.v:158625$8323_Y
+ attribute \src "libresoc.v:158628.17-158628.92"
+ wire $not$libresoc.v:158628$8326_Y
+ attribute \src "libresoc.v:158622.18-158622.98"
+ wire $or$libresoc.v:158622$8320_Y
+ attribute \src "libresoc.v:158624.18-158624.99"
+ wire $or$libresoc.v:158624$8322_Y
+ attribute \src "libresoc.v:158627.17-158627.97"
+ wire $or$libresoc.v:158627$8325_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158922.7-158922.15"
+ attribute \src "libresoc.v:158586.7-158586.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:158957$8371
+ cell $and $and$libresoc.v:158621$8319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:158957$8371_Y
+ connect \Y $and$libresoc.v:158621$8319_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:158962$8376
+ cell $and $and$libresoc.v:158626$8324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:158962$8376_Y
+ connect \Y $and$libresoc.v:158626$8324_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:158959$8373
+ cell $not $not$libresoc.v:158623$8321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:158959$8373_Y
+ connect \Y $not$libresoc.v:158623$8321_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:158961$8375
+ cell $not $not$libresoc.v:158625$8323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158961$8375_Y
+ connect \Y $not$libresoc.v:158625$8323_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:158964$8378
+ cell $not $not$libresoc.v:158628$8326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:158964$8378_Y
+ connect \Y $not$libresoc.v:158628$8326_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:158958$8372
+ cell $or $or$libresoc.v:158622$8320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:158958$8372_Y
+ connect \Y $or$libresoc.v:158622$8320_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:158960$8374
+ cell $or $or$libresoc.v:158624$8322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:158960$8374_Y
+ connect \Y $or$libresoc.v:158624$8322_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:158963$8377
+ cell $or $or$libresoc.v:158627$8325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:158963$8377_Y
+ connect \Y $or$libresoc.v:158627$8325_Y
end
- attribute \src "libresoc.v:158922.7-158922.20"
- process $proc$libresoc.v:158922$8383
+ attribute \src "libresoc.v:158586.7-158586.20"
+ process $proc$libresoc.v:158586$8331
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158944.7-158944.19"
- process $proc$libresoc.v:158944$8384
+ attribute \src "libresoc.v:158608.7-158608.19"
+ process $proc$libresoc.v:158608$8332
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:158965.3-158966.27"
- process $proc$libresoc.v:158965$8379
+ attribute \src "libresoc.v:158629.3-158630.27"
+ process $proc$libresoc.v:158629$8327
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:158967.3-158975.6"
- process $proc$libresoc.v:158967$8380
+ attribute \src "libresoc.v:158631.3-158639.6"
+ process $proc$libresoc.v:158631$8328
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8381 $1\q_int$next[0:0]$8382
- attribute \src "libresoc.v:158968.5-158968.29"
+ assign $0\q_int$next[0:0]$8329 $1\q_int$next[0:0]$8330
+ attribute \src "libresoc.v:158632.5-158632.29"
switch \initial
- attribute \src "libresoc.v:158968.9-158968.17"
+ attribute \src "libresoc.v:158632.9-158632.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8382 1'0
+ assign $1\q_int$next[0:0]$8330 1'0
case
- assign $1\q_int$next[0:0]$8382 \$5
+ assign $1\q_int$next[0:0]$8330 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8381
+ update \q_int$next $0\q_int$next[0:0]$8329
end
- connect \$9 $and$libresoc.v:158957$8371_Y
- connect \$11 $or$libresoc.v:158958$8372_Y
- connect \$13 $not$libresoc.v:158959$8373_Y
- connect \$15 $or$libresoc.v:158960$8374_Y
- connect \$1 $not$libresoc.v:158961$8375_Y
- connect \$3 $and$libresoc.v:158962$8376_Y
- connect \$5 $or$libresoc.v:158963$8377_Y
- connect \$7 $not$libresoc.v:158964$8378_Y
+ connect \$9 $and$libresoc.v:158621$8319_Y
+ connect \$11 $or$libresoc.v:158622$8320_Y
+ connect \$13 $not$libresoc.v:158623$8321_Y
+ connect \$15 $or$libresoc.v:158624$8322_Y
+ connect \$1 $not$libresoc.v:158625$8323_Y
+ connect \$3 $and$libresoc.v:158626$8324_Y
+ connect \$5 $or$libresoc.v:158627$8325_Y
+ connect \$7 $not$libresoc.v:158628$8326_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:158983.1-159041.10"
+attribute \src "libresoc.v:158647.1-158705.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l"
attribute \generator "nMigen"
module \opc_l$40
- attribute \src "libresoc.v:158984.7-158984.20"
+ attribute \src "libresoc.v:158648.7-158648.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159029.3-159037.6"
- wire $0\q_int$next[0:0]$8395
- attribute \src "libresoc.v:159027.3-159028.27"
+ attribute \src "libresoc.v:158693.3-158701.6"
+ wire $0\q_int$next[0:0]$8343
+ attribute \src "libresoc.v:158691.3-158692.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:159029.3-159037.6"
- wire $1\q_int$next[0:0]$8396
- attribute \src "libresoc.v:159006.7-159006.19"
+ attribute \src "libresoc.v:158693.3-158701.6"
+ wire $1\q_int$next[0:0]$8344
+ attribute \src "libresoc.v:158670.7-158670.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:159019.17-159019.96"
- wire $and$libresoc.v:159019$8385_Y
- attribute \src "libresoc.v:159024.17-159024.96"
- wire $and$libresoc.v:159024$8390_Y
- attribute \src "libresoc.v:159021.18-159021.93"
- wire $not$libresoc.v:159021$8387_Y
- attribute \src "libresoc.v:159023.17-159023.92"
- wire $not$libresoc.v:159023$8389_Y
- attribute \src "libresoc.v:159026.17-159026.92"
- wire $not$libresoc.v:159026$8392_Y
- attribute \src "libresoc.v:159020.18-159020.98"
- wire $or$libresoc.v:159020$8386_Y
- attribute \src "libresoc.v:159022.18-159022.99"
- wire $or$libresoc.v:159022$8388_Y
- attribute \src "libresoc.v:159025.17-159025.97"
- wire $or$libresoc.v:159025$8391_Y
+ attribute \src "libresoc.v:158683.17-158683.96"
+ wire $and$libresoc.v:158683$8333_Y
+ attribute \src "libresoc.v:158688.17-158688.96"
+ wire $and$libresoc.v:158688$8338_Y
+ attribute \src "libresoc.v:158685.18-158685.93"
+ wire $not$libresoc.v:158685$8335_Y
+ attribute \src "libresoc.v:158687.17-158687.92"
+ wire $not$libresoc.v:158687$8337_Y
+ attribute \src "libresoc.v:158690.17-158690.92"
+ wire $not$libresoc.v:158690$8340_Y
+ attribute \src "libresoc.v:158684.18-158684.98"
+ wire $or$libresoc.v:158684$8334_Y
+ attribute \src "libresoc.v:158686.18-158686.99"
+ wire $or$libresoc.v:158686$8336_Y
+ attribute \src "libresoc.v:158689.17-158689.97"
+ wire $or$libresoc.v:158689$8339_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:158984.7-158984.15"
+ attribute \src "libresoc.v:158648.7-158648.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:159019$8385
+ cell $and $and$libresoc.v:158683$8333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:159019$8385_Y
+ connect \Y $and$libresoc.v:158683$8333_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:159024$8390
+ cell $and $and$libresoc.v:158688$8338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:159024$8390_Y
+ connect \Y $and$libresoc.v:158688$8338_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:159021$8387
+ cell $not $not$libresoc.v:158685$8335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:159021$8387_Y
+ connect \Y $not$libresoc.v:158685$8335_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:159023$8389
+ cell $not $not$libresoc.v:158687$8337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159023$8389_Y
+ connect \Y $not$libresoc.v:158687$8337_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:159026$8392
+ cell $not $not$libresoc.v:158690$8340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159026$8392_Y
+ connect \Y $not$libresoc.v:158690$8340_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:159020$8386
+ cell $or $or$libresoc.v:158684$8334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:159020$8386_Y
+ connect \Y $or$libresoc.v:158684$8334_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:159022$8388
+ cell $or $or$libresoc.v:158686$8336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:159022$8388_Y
+ connect \Y $or$libresoc.v:158686$8336_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:159025$8391
+ cell $or $or$libresoc.v:158689$8339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:159025$8391_Y
+ connect \Y $or$libresoc.v:158689$8339_Y
end
- attribute \src "libresoc.v:158984.7-158984.20"
- process $proc$libresoc.v:158984$8397
+ attribute \src "libresoc.v:158648.7-158648.20"
+ process $proc$libresoc.v:158648$8345
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159006.7-159006.19"
- process $proc$libresoc.v:159006$8398
+ attribute \src "libresoc.v:158670.7-158670.19"
+ process $proc$libresoc.v:158670$8346
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:159027.3-159028.27"
- process $proc$libresoc.v:159027$8393
+ attribute \src "libresoc.v:158691.3-158692.27"
+ process $proc$libresoc.v:158691$8341
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:159029.3-159037.6"
- process $proc$libresoc.v:159029$8394
+ attribute \src "libresoc.v:158693.3-158701.6"
+ process $proc$libresoc.v:158693$8342
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8395 $1\q_int$next[0:0]$8396
- attribute \src "libresoc.v:159030.5-159030.29"
+ assign $0\q_int$next[0:0]$8343 $1\q_int$next[0:0]$8344
+ attribute \src "libresoc.v:158694.5-158694.29"
switch \initial
- attribute \src "libresoc.v:159030.9-159030.17"
+ attribute \src "libresoc.v:158694.9-158694.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8396 1'0
+ assign $1\q_int$next[0:0]$8344 1'0
case
- assign $1\q_int$next[0:0]$8396 \$5
+ assign $1\q_int$next[0:0]$8344 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8395
+ update \q_int$next $0\q_int$next[0:0]$8343
end
- connect \$9 $and$libresoc.v:159019$8385_Y
- connect \$11 $or$libresoc.v:159020$8386_Y
- connect \$13 $not$libresoc.v:159021$8387_Y
- connect \$15 $or$libresoc.v:159022$8388_Y
- connect \$1 $not$libresoc.v:159023$8389_Y
- connect \$3 $and$libresoc.v:159024$8390_Y
- connect \$5 $or$libresoc.v:159025$8391_Y
- connect \$7 $not$libresoc.v:159026$8392_Y
+ connect \$9 $and$libresoc.v:158683$8333_Y
+ connect \$11 $or$libresoc.v:158684$8334_Y
+ connect \$13 $not$libresoc.v:158685$8335_Y
+ connect \$15 $or$libresoc.v:158686$8336_Y
+ connect \$1 $not$libresoc.v:158687$8337_Y
+ connect \$3 $and$libresoc.v:158688$8338_Y
+ connect \$5 $or$libresoc.v:158689$8339_Y
+ connect \$7 $not$libresoc.v:158690$8340_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:159045.1-159103.10"
+attribute \src "libresoc.v:158709.1-158767.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l"
attribute \generator "nMigen"
module \opc_l$56
- attribute \src "libresoc.v:159046.7-159046.20"
+ attribute \src "libresoc.v:158710.7-158710.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159091.3-159099.6"
- wire $0\q_int$next[0:0]$8409
- attribute \src "libresoc.v:159089.3-159090.27"
+ attribute \src "libresoc.v:158755.3-158763.6"
+ wire $0\q_int$next[0:0]$8357
+ attribute \src "libresoc.v:158753.3-158754.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:159091.3-159099.6"
- wire $1\q_int$next[0:0]$8410
- attribute \src "libresoc.v:159068.7-159068.19"
+ attribute \src "libresoc.v:158755.3-158763.6"
+ wire $1\q_int$next[0:0]$8358
+ attribute \src "libresoc.v:158732.7-158732.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:159081.17-159081.96"
- wire $and$libresoc.v:159081$8399_Y
- attribute \src "libresoc.v:159086.17-159086.96"
- wire $and$libresoc.v:159086$8404_Y
- attribute \src "libresoc.v:159083.18-159083.93"
- wire $not$libresoc.v:159083$8401_Y
- attribute \src "libresoc.v:159085.17-159085.92"
- wire $not$libresoc.v:159085$8403_Y
- attribute \src "libresoc.v:159088.17-159088.92"
- wire $not$libresoc.v:159088$8406_Y
- attribute \src "libresoc.v:159082.18-159082.98"
- wire $or$libresoc.v:159082$8400_Y
- attribute \src "libresoc.v:159084.18-159084.99"
- wire $or$libresoc.v:159084$8402_Y
- attribute \src "libresoc.v:159087.17-159087.97"
- wire $or$libresoc.v:159087$8405_Y
+ attribute \src "libresoc.v:158745.17-158745.96"
+ wire $and$libresoc.v:158745$8347_Y
+ attribute \src "libresoc.v:158750.17-158750.96"
+ wire $and$libresoc.v:158750$8352_Y
+ attribute \src "libresoc.v:158747.18-158747.93"
+ wire $not$libresoc.v:158747$8349_Y
+ attribute \src "libresoc.v:158749.17-158749.92"
+ wire $not$libresoc.v:158749$8351_Y
+ attribute \src "libresoc.v:158752.17-158752.92"
+ wire $not$libresoc.v:158752$8354_Y
+ attribute \src "libresoc.v:158746.18-158746.98"
+ wire $or$libresoc.v:158746$8348_Y
+ attribute \src "libresoc.v:158748.18-158748.99"
+ wire $or$libresoc.v:158748$8350_Y
+ attribute \src "libresoc.v:158751.17-158751.97"
+ wire $or$libresoc.v:158751$8353_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:159046.7-159046.15"
+ attribute \src "libresoc.v:158710.7-158710.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:159081$8399
+ cell $and $and$libresoc.v:158745$8347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:159081$8399_Y
+ connect \Y $and$libresoc.v:158745$8347_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:159086$8404
+ cell $and $and$libresoc.v:158750$8352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:159086$8404_Y
+ connect \Y $and$libresoc.v:158750$8352_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:159083$8401
+ cell $not $not$libresoc.v:158747$8349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:159083$8401_Y
+ connect \Y $not$libresoc.v:158747$8349_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:159085$8403
+ cell $not $not$libresoc.v:158749$8351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159085$8403_Y
+ connect \Y $not$libresoc.v:158749$8351_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:159088$8406
+ cell $not $not$libresoc.v:158752$8354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159088$8406_Y
+ connect \Y $not$libresoc.v:158752$8354_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:159082$8400
+ cell $or $or$libresoc.v:158746$8348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:159082$8400_Y
+ connect \Y $or$libresoc.v:158746$8348_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:159084$8402
+ cell $or $or$libresoc.v:158748$8350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:159084$8402_Y
+ connect \Y $or$libresoc.v:158748$8350_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:159087$8405
+ cell $or $or$libresoc.v:158751$8353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:159087$8405_Y
+ connect \Y $or$libresoc.v:158751$8353_Y
end
- attribute \src "libresoc.v:159046.7-159046.20"
- process $proc$libresoc.v:159046$8411
+ attribute \src "libresoc.v:158710.7-158710.20"
+ process $proc$libresoc.v:158710$8359
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159068.7-159068.19"
- process $proc$libresoc.v:159068$8412
+ attribute \src "libresoc.v:158732.7-158732.19"
+ process $proc$libresoc.v:158732$8360
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:159089.3-159090.27"
- process $proc$libresoc.v:159089$8407
+ attribute \src "libresoc.v:158753.3-158754.27"
+ process $proc$libresoc.v:158753$8355
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:159091.3-159099.6"
- process $proc$libresoc.v:159091$8408
+ attribute \src "libresoc.v:158755.3-158763.6"
+ process $proc$libresoc.v:158755$8356
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8409 $1\q_int$next[0:0]$8410
- attribute \src "libresoc.v:159092.5-159092.29"
+ assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358
+ attribute \src "libresoc.v:158756.5-158756.29"
switch \initial
- attribute \src "libresoc.v:159092.9-159092.17"
+ attribute \src "libresoc.v:158756.9-158756.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8410 1'0
+ assign $1\q_int$next[0:0]$8358 1'0
case
- assign $1\q_int$next[0:0]$8410 \$5
+ assign $1\q_int$next[0:0]$8358 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8409
+ update \q_int$next $0\q_int$next[0:0]$8357
end
- connect \$9 $and$libresoc.v:159081$8399_Y
- connect \$11 $or$libresoc.v:159082$8400_Y
- connect \$13 $not$libresoc.v:159083$8401_Y
- connect \$15 $or$libresoc.v:159084$8402_Y
- connect \$1 $not$libresoc.v:159085$8403_Y
- connect \$3 $and$libresoc.v:159086$8404_Y
- connect \$5 $or$libresoc.v:159087$8405_Y
- connect \$7 $not$libresoc.v:159088$8406_Y
+ connect \$9 $and$libresoc.v:158745$8347_Y
+ connect \$11 $or$libresoc.v:158746$8348_Y
+ connect \$13 $not$libresoc.v:158747$8349_Y
+ connect \$15 $or$libresoc.v:158748$8350_Y
+ connect \$1 $not$libresoc.v:158749$8351_Y
+ connect \$3 $and$libresoc.v:158750$8352_Y
+ connect \$5 $or$libresoc.v:158751$8353_Y
+ connect \$7 $not$libresoc.v:158752$8354_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:159107.1-159165.10"
+attribute \src "libresoc.v:158771.1-158829.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l"
attribute \generator "nMigen"
module \opc_l$68
- attribute \src "libresoc.v:159108.7-159108.20"
+ attribute \src "libresoc.v:158772.7-158772.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159153.3-159161.6"
- wire $0\q_int$next[0:0]$8423
- attribute \src "libresoc.v:159151.3-159152.27"
+ attribute \src "libresoc.v:158817.3-158825.6"
+ wire $0\q_int$next[0:0]$8371
+ attribute \src "libresoc.v:158815.3-158816.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:159153.3-159161.6"
- wire $1\q_int$next[0:0]$8424
- attribute \src "libresoc.v:159130.7-159130.19"
+ attribute \src "libresoc.v:158817.3-158825.6"
+ wire $1\q_int$next[0:0]$8372
+ attribute \src "libresoc.v:158794.7-158794.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:159143.17-159143.96"
- wire $and$libresoc.v:159143$8413_Y
- attribute \src "libresoc.v:159148.17-159148.96"
- wire $and$libresoc.v:159148$8418_Y
- attribute \src "libresoc.v:159145.18-159145.93"
- wire $not$libresoc.v:159145$8415_Y
- attribute \src "libresoc.v:159147.17-159147.92"
- wire $not$libresoc.v:159147$8417_Y
- attribute \src "libresoc.v:159150.17-159150.92"
- wire $not$libresoc.v:159150$8420_Y
- attribute \src "libresoc.v:159144.18-159144.98"
- wire $or$libresoc.v:159144$8414_Y
- attribute \src "libresoc.v:159146.18-159146.99"
- wire $or$libresoc.v:159146$8416_Y
- attribute \src "libresoc.v:159149.17-159149.97"
- wire $or$libresoc.v:159149$8419_Y
+ attribute \src "libresoc.v:158807.17-158807.96"
+ wire $and$libresoc.v:158807$8361_Y
+ attribute \src "libresoc.v:158812.17-158812.96"
+ wire $and$libresoc.v:158812$8366_Y
+ attribute \src "libresoc.v:158809.18-158809.93"
+ wire $not$libresoc.v:158809$8363_Y
+ attribute \src "libresoc.v:158811.17-158811.92"
+ wire $not$libresoc.v:158811$8365_Y
+ attribute \src "libresoc.v:158814.17-158814.92"
+ wire $not$libresoc.v:158814$8368_Y
+ attribute \src "libresoc.v:158808.18-158808.98"
+ wire $or$libresoc.v:158808$8362_Y
+ attribute \src "libresoc.v:158810.18-158810.99"
+ wire $or$libresoc.v:158810$8364_Y
+ attribute \src "libresoc.v:158813.17-158813.97"
+ wire $or$libresoc.v:158813$8367_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:159108.7-159108.15"
+ attribute \src "libresoc.v:158772.7-158772.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:159143$8413
+ cell $and $and$libresoc.v:158807$8361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:159143$8413_Y
+ connect \Y $and$libresoc.v:158807$8361_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:159148$8418
+ cell $and $and$libresoc.v:158812$8366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:159148$8418_Y
+ connect \Y $and$libresoc.v:158812$8366_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:159145$8415
+ cell $not $not$libresoc.v:158809$8363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:159145$8415_Y
+ connect \Y $not$libresoc.v:158809$8363_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:159147$8417
+ cell $not $not$libresoc.v:158811$8365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159147$8417_Y
+ connect \Y $not$libresoc.v:158811$8365_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:159150$8420
+ cell $not $not$libresoc.v:158814$8368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159150$8420_Y
+ connect \Y $not$libresoc.v:158814$8368_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:159144$8414
+ cell $or $or$libresoc.v:158808$8362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:159144$8414_Y
+ connect \Y $or$libresoc.v:158808$8362_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:159146$8416
+ cell $or $or$libresoc.v:158810$8364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:159146$8416_Y
+ connect \Y $or$libresoc.v:158810$8364_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:159149$8419
+ cell $or $or$libresoc.v:158813$8367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:159149$8419_Y
+ connect \Y $or$libresoc.v:158813$8367_Y
end
- attribute \src "libresoc.v:159108.7-159108.20"
- process $proc$libresoc.v:159108$8425
+ attribute \src "libresoc.v:158772.7-158772.20"
+ process $proc$libresoc.v:158772$8373
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159130.7-159130.19"
- process $proc$libresoc.v:159130$8426
+ attribute \src "libresoc.v:158794.7-158794.19"
+ process $proc$libresoc.v:158794$8374
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:159151.3-159152.27"
- process $proc$libresoc.v:159151$8421
+ attribute \src "libresoc.v:158815.3-158816.27"
+ process $proc$libresoc.v:158815$8369
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:159153.3-159161.6"
- process $proc$libresoc.v:159153$8422
+ attribute \src "libresoc.v:158817.3-158825.6"
+ process $proc$libresoc.v:158817$8370
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8423 $1\q_int$next[0:0]$8424
- attribute \src "libresoc.v:159154.5-159154.29"
+ assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372
+ attribute \src "libresoc.v:158818.5-158818.29"
switch \initial
- attribute \src "libresoc.v:159154.9-159154.17"
+ attribute \src "libresoc.v:158818.9-158818.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8424 1'0
+ assign $1\q_int$next[0:0]$8372 1'0
case
- assign $1\q_int$next[0:0]$8424 \$5
+ assign $1\q_int$next[0:0]$8372 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8423
+ update \q_int$next $0\q_int$next[0:0]$8371
end
- connect \$9 $and$libresoc.v:159143$8413_Y
- connect \$11 $or$libresoc.v:159144$8414_Y
- connect \$13 $not$libresoc.v:159145$8415_Y
- connect \$15 $or$libresoc.v:159146$8416_Y
- connect \$1 $not$libresoc.v:159147$8417_Y
- connect \$3 $and$libresoc.v:159148$8418_Y
- connect \$5 $or$libresoc.v:159149$8419_Y
- connect \$7 $not$libresoc.v:159150$8420_Y
+ connect \$9 $and$libresoc.v:158807$8361_Y
+ connect \$11 $or$libresoc.v:158808$8362_Y
+ connect \$13 $not$libresoc.v:158809$8363_Y
+ connect \$15 $or$libresoc.v:158810$8364_Y
+ connect \$1 $not$libresoc.v:158811$8365_Y
+ connect \$3 $and$libresoc.v:158812$8366_Y
+ connect \$5 $or$libresoc.v:158813$8367_Y
+ connect \$7 $not$libresoc.v:158814$8368_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:159169.1-159227.10"
+attribute \src "libresoc.v:158833.1-158891.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l"
attribute \generator "nMigen"
module \opc_l$85
- attribute \src "libresoc.v:159170.7-159170.20"
+ attribute \src "libresoc.v:158834.7-158834.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159215.3-159223.6"
- wire $0\q_int$next[0:0]$8437
- attribute \src "libresoc.v:159213.3-159214.27"
+ attribute \src "libresoc.v:158879.3-158887.6"
+ wire $0\q_int$next[0:0]$8385
+ attribute \src "libresoc.v:158877.3-158878.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:159215.3-159223.6"
- wire $1\q_int$next[0:0]$8438
- attribute \src "libresoc.v:159192.7-159192.19"
+ attribute \src "libresoc.v:158879.3-158887.6"
+ wire $1\q_int$next[0:0]$8386
+ attribute \src "libresoc.v:158856.7-158856.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:159205.17-159205.96"
- wire $and$libresoc.v:159205$8427_Y
- attribute \src "libresoc.v:159210.17-159210.96"
- wire $and$libresoc.v:159210$8432_Y
- attribute \src "libresoc.v:159207.18-159207.93"
- wire $not$libresoc.v:159207$8429_Y
- attribute \src "libresoc.v:159209.17-159209.92"
- wire $not$libresoc.v:159209$8431_Y
- attribute \src "libresoc.v:159212.17-159212.92"
- wire $not$libresoc.v:159212$8434_Y
- attribute \src "libresoc.v:159206.18-159206.98"
- wire $or$libresoc.v:159206$8428_Y
- attribute \src "libresoc.v:159208.18-159208.99"
- wire $or$libresoc.v:159208$8430_Y
- attribute \src "libresoc.v:159211.17-159211.97"
- wire $or$libresoc.v:159211$8433_Y
+ attribute \src "libresoc.v:158869.17-158869.96"
+ wire $and$libresoc.v:158869$8375_Y
+ attribute \src "libresoc.v:158874.17-158874.96"
+ wire $and$libresoc.v:158874$8380_Y
+ attribute \src "libresoc.v:158871.18-158871.93"
+ wire $not$libresoc.v:158871$8377_Y
+ attribute \src "libresoc.v:158873.17-158873.92"
+ wire $not$libresoc.v:158873$8379_Y
+ attribute \src "libresoc.v:158876.17-158876.92"
+ wire $not$libresoc.v:158876$8382_Y
+ attribute \src "libresoc.v:158870.18-158870.98"
+ wire $or$libresoc.v:158870$8376_Y
+ attribute \src "libresoc.v:158872.18-158872.99"
+ wire $or$libresoc.v:158872$8378_Y
+ attribute \src "libresoc.v:158875.17-158875.97"
+ wire $or$libresoc.v:158875$8381_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:159170.7-159170.15"
+ attribute \src "libresoc.v:158834.7-158834.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:159205$8427
+ cell $and $and$libresoc.v:158869$8375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:159205$8427_Y
+ connect \Y $and$libresoc.v:158869$8375_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:159210$8432
+ cell $and $and$libresoc.v:158874$8380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:159210$8432_Y
+ connect \Y $and$libresoc.v:158874$8380_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:159207$8429
+ cell $not $not$libresoc.v:158871$8377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:159207$8429_Y
+ connect \Y $not$libresoc.v:158871$8377_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:159209$8431
+ cell $not $not$libresoc.v:158873$8379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159209$8431_Y
+ connect \Y $not$libresoc.v:158873$8379_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:159212$8434
+ cell $not $not$libresoc.v:158876$8382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:159212$8434_Y
+ connect \Y $not$libresoc.v:158876$8382_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:159206$8428
+ cell $or $or$libresoc.v:158870$8376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:159206$8428_Y
+ connect \Y $or$libresoc.v:158870$8376_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:159208$8430
+ cell $or $or$libresoc.v:158872$8378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:159208$8430_Y
+ connect \Y $or$libresoc.v:158872$8378_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:159211$8433
+ cell $or $or$libresoc.v:158875$8381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:159211$8433_Y
+ connect \Y $or$libresoc.v:158875$8381_Y
end
- attribute \src "libresoc.v:159170.7-159170.20"
- process $proc$libresoc.v:159170$8439
+ attribute \src "libresoc.v:158834.7-158834.20"
+ process $proc$libresoc.v:158834$8387
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159192.7-159192.19"
- process $proc$libresoc.v:159192$8440
+ attribute \src "libresoc.v:158856.7-158856.19"
+ process $proc$libresoc.v:158856$8388
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:159213.3-159214.27"
- process $proc$libresoc.v:159213$8435
+ attribute \src "libresoc.v:158877.3-158878.27"
+ process $proc$libresoc.v:158877$8383
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:159215.3-159223.6"
- process $proc$libresoc.v:159215$8436
+ attribute \src "libresoc.v:158879.3-158887.6"
+ process $proc$libresoc.v:158879$8384
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8437 $1\q_int$next[0:0]$8438
- attribute \src "libresoc.v:159216.5-159216.29"
+ assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386
+ attribute \src "libresoc.v:158880.5-158880.29"
switch \initial
- attribute \src "libresoc.v:159216.9-159216.17"
+ attribute \src "libresoc.v:158880.9-158880.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8438 1'0
+ assign $1\q_int$next[0:0]$8386 1'0
case
- assign $1\q_int$next[0:0]$8438 \$5
+ assign $1\q_int$next[0:0]$8386 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8437
+ update \q_int$next $0\q_int$next[0:0]$8385
end
- connect \$9 $and$libresoc.v:159205$8427_Y
- connect \$11 $or$libresoc.v:159206$8428_Y
- connect \$13 $not$libresoc.v:159207$8429_Y
- connect \$15 $or$libresoc.v:159208$8430_Y
- connect \$1 $not$libresoc.v:159209$8431_Y
- connect \$3 $and$libresoc.v:159210$8432_Y
- connect \$5 $or$libresoc.v:159211$8433_Y
- connect \$7 $not$libresoc.v:159212$8434_Y
+ connect \$9 $and$libresoc.v:158869$8375_Y
+ connect \$11 $or$libresoc.v:158870$8376_Y
+ connect \$13 $not$libresoc.v:158871$8377_Y
+ connect \$15 $or$libresoc.v:158872$8378_Y
+ connect \$1 $not$libresoc.v:158873$8379_Y
+ connect \$3 $and$libresoc.v:158874$8380_Y
+ connect \$5 $or$libresoc.v:158875$8381_Y
+ connect \$7 $not$libresoc.v:158876$8382_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:159231.1-159689.10"
+attribute \src "libresoc.v:158895.1-159353.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output"
attribute \generator "nMigen"
module \output
- attribute \src "libresoc.v:159608.3-159619.6"
+ attribute \src "libresoc.v:159272.3-159283.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:159232.7-159232.20"
+ attribute \src "libresoc.v:158896.7-158896.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159620.3-159631.6"
- wire width 65 $0\o$28[64:0]$8459
- attribute \src "libresoc.v:159596.3-159607.6"
+ attribute \src "libresoc.v:159284.3-159295.6"
+ wire width 65 $0\o$28[64:0]$8407
+ attribute \src "libresoc.v:159260.3-159271.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:159652.3-159661.6"
- wire width 2 $0\xer_ov$24[1:0]$8466
- attribute \src "libresoc.v:159662.3-159671.6"
+ attribute \src "libresoc.v:159316.3-159325.6"
+ wire width 2 $0\xer_ov$24[1:0]$8414
+ attribute \src "libresoc.v:159326.3-159335.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:159632.3-159641.6"
- wire $0\xer_so$25[0:0]$8462
- attribute \src "libresoc.v:159642.3-159651.6"
+ attribute \src "libresoc.v:159296.3-159305.6"
+ wire $0\xer_so$25[0:0]$8410
+ attribute \src "libresoc.v:159306.3-159315.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:159608.3-159619.6"
+ attribute \src "libresoc.v:159272.3-159283.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:159620.3-159631.6"
- wire width 65 $1\o$28[64:0]$8460
- attribute \src "libresoc.v:159596.3-159607.6"
+ attribute \src "libresoc.v:159284.3-159295.6"
+ wire width 65 $1\o$28[64:0]$8408
+ attribute \src "libresoc.v:159260.3-159271.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:159652.3-159661.6"
- wire width 2 $1\xer_ov$24[1:0]$8467
- attribute \src "libresoc.v:159662.3-159671.6"
+ attribute \src "libresoc.v:159316.3-159325.6"
+ wire width 2 $1\xer_ov$24[1:0]$8415
+ attribute \src "libresoc.v:159326.3-159335.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:159632.3-159641.6"
- wire $1\xer_so$25[0:0]$8463
- attribute \src "libresoc.v:159642.3-159651.6"
+ attribute \src "libresoc.v:159296.3-159305.6"
+ wire $1\xer_so$25[0:0]$8411
+ attribute \src "libresoc.v:159306.3-159315.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:159583.18-159583.128"
- wire $and$libresoc.v:159583$8441_Y
- attribute \src "libresoc.v:159591.18-159591.112"
- wire $and$libresoc.v:159591$8451_Y
- attribute \src "libresoc.v:159594.18-159594.125"
- wire $and$libresoc.v:159594$8454_Y
- attribute \src "libresoc.v:159587.18-159587.123"
- wire $eq$libresoc.v:159587$8447_Y
- attribute \src "libresoc.v:159588.18-159588.123"
- wire $eq$libresoc.v:159588$8448_Y
- attribute \src "libresoc.v:159585.18-159585.103"
- wire width 65 $extend$libresoc.v:159585$8443_Y
- attribute \src "libresoc.v:159586.18-159586.101"
- wire width 65 $extend$libresoc.v:159586$8445_Y
- attribute \src "libresoc.v:159584.18-159584.100"
- wire width 64 $not$libresoc.v:159584$8442_Y
- attribute \src "libresoc.v:159590.18-159590.107"
- wire $not$libresoc.v:159590$8450_Y
- attribute \src "libresoc.v:159593.18-159593.107"
- wire $not$libresoc.v:159593$8453_Y
- attribute \src "libresoc.v:159592.18-159592.115"
- wire $or$libresoc.v:159592$8452_Y
- attribute \src "libresoc.v:159595.18-159595.112"
- wire $or$libresoc.v:159595$8455_Y
- attribute \src "libresoc.v:159585.18-159585.103"
- wire width 65 $pos$libresoc.v:159585$8444_Y
- attribute \src "libresoc.v:159586.18-159586.101"
- wire width 65 $pos$libresoc.v:159586$8446_Y
- attribute \src "libresoc.v:159589.18-159589.105"
- wire $reduce_or$libresoc.v:159589$8449_Y
+ attribute \src "libresoc.v:159247.18-159247.128"
+ wire $and$libresoc.v:159247$8389_Y
+ attribute \src "libresoc.v:159255.18-159255.112"
+ wire $and$libresoc.v:159255$8399_Y
+ attribute \src "libresoc.v:159258.18-159258.125"
+ wire $and$libresoc.v:159258$8402_Y
+ attribute \src "libresoc.v:159251.18-159251.123"
+ wire $eq$libresoc.v:159251$8395_Y
+ attribute \src "libresoc.v:159252.18-159252.123"
+ wire $eq$libresoc.v:159252$8396_Y
+ attribute \src "libresoc.v:159249.18-159249.103"
+ wire width 65 $extend$libresoc.v:159249$8391_Y
+ attribute \src "libresoc.v:159250.18-159250.101"
+ wire width 65 $extend$libresoc.v:159250$8393_Y
+ attribute \src "libresoc.v:159248.18-159248.100"
+ wire width 64 $not$libresoc.v:159248$8390_Y
+ attribute \src "libresoc.v:159254.18-159254.107"
+ wire $not$libresoc.v:159254$8398_Y
+ attribute \src "libresoc.v:159257.18-159257.107"
+ wire $not$libresoc.v:159257$8401_Y
+ attribute \src "libresoc.v:159256.18-159256.115"
+ wire $or$libresoc.v:159256$8400_Y
+ attribute \src "libresoc.v:159259.18-159259.112"
+ wire $or$libresoc.v:159259$8403_Y
+ attribute \src "libresoc.v:159249.18-159249.103"
+ wire width 65 $pos$libresoc.v:159249$8392_Y
+ attribute \src "libresoc.v:159250.18-159250.101"
+ wire width 65 $pos$libresoc.v:159250$8394_Y
+ attribute \src "libresoc.v:159253.18-159253.105"
+ wire $reduce_or$libresoc.v:159253$8397_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 46 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 47 \cr_a_ok
- attribute \src "libresoc.v:159232.7-159232.15"
+ attribute \src "libresoc.v:158896.7-158896.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 53 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:159583$8441
+ cell $and $and$libresoc.v:159247$8389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__oe__oe
connect \B \alu_op__oe__ok
- connect \Y $and$libresoc.v:159583$8441_Y
+ connect \Y $and$libresoc.v:159247$8389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:159591$8451
+ cell $and $and$libresoc.v:159255$8399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$41
- connect \Y $and$libresoc.v:159591$8451_Y
+ connect \Y $and$libresoc.v:159255$8399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:159594$8454
+ cell $and $and$libresoc.v:159258$8402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__oe__oe
connect \B \alu_op__oe__ok
- connect \Y $and$libresoc.v:159594$8454_Y
+ connect \Y $and$libresoc.v:159258$8402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:159587$8447
+ cell $eq $eq$libresoc.v:159251$8395
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:159587$8447_Y
+ connect \Y $eq$libresoc.v:159251$8395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:159588$8448
+ cell $eq $eq$libresoc.v:159252$8396
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:159588$8448_Y
+ connect \Y $eq$libresoc.v:159252$8396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:159585$8443
+ cell $pos $extend$libresoc.v:159249$8391
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$30
- connect \Y $extend$libresoc.v:159585$8443_Y
+ connect \Y $extend$libresoc.v:159249$8391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:159586$8445
+ cell $pos $extend$libresoc.v:159250$8393
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:159586$8445_Y
+ connect \Y $extend$libresoc.v:159250$8393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:159584$8442
+ cell $not $not$libresoc.v:159248$8390
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:159584$8442_Y
+ connect \Y $not$libresoc.v:159248$8390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:159590$8450
+ cell $not $not$libresoc.v:159254$8398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:159590$8450_Y
+ connect \Y $not$libresoc.v:159254$8398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:159593$8453
+ cell $not $not$libresoc.v:159257$8401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:159593$8453_Y
+ connect \Y $not$libresoc.v:159257$8401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:159592$8452
+ cell $or $or$libresoc.v:159256$8400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:159592$8452_Y
+ connect \Y $or$libresoc.v:159256$8400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:159595$8455
+ cell $or $or$libresoc.v:159259$8403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:159595$8455_Y
+ connect \Y $or$libresoc.v:159259$8403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:159585$8444
+ cell $pos $pos$libresoc.v:159249$8392
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:159585$8443_Y
- connect \Y $pos$libresoc.v:159585$8444_Y
+ connect \A $extend$libresoc.v:159249$8391_Y
+ connect \Y $pos$libresoc.v:159249$8392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:159586$8446
+ cell $pos $pos$libresoc.v:159250$8394
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:159586$8445_Y
- connect \Y $pos$libresoc.v:159586$8446_Y
+ connect \A $extend$libresoc.v:159250$8393_Y
+ connect \Y $pos$libresoc.v:159250$8394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:159589$8449
+ cell $reduce_or $reduce_or$libresoc.v:159253$8397
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:159589$8449_Y
+ connect \Y $reduce_or$libresoc.v:159253$8397_Y
end
- attribute \src "libresoc.v:159232.7-159232.20"
- process $proc$libresoc.v:159232$8469
+ attribute \src "libresoc.v:158896.7-158896.20"
+ process $proc$libresoc.v:158896$8417
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159596.3-159607.6"
- process $proc$libresoc.v:159596$8456
+ attribute \src "libresoc.v:159260.3-159271.6"
+ process $proc$libresoc.v:159260$8404
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:159597.5-159597.29"
+ attribute \src "libresoc.v:159261.5-159261.29"
switch \initial
- attribute \src "libresoc.v:159597.9-159597.17"
+ attribute \src "libresoc.v:159261.9-159261.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:159608.3-159619.6"
- process $proc$libresoc.v:159608$8457
+ attribute \src "libresoc.v:159272.3-159283.6"
+ process $proc$libresoc.v:159272$8405
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:159609.5-159609.29"
+ attribute \src "libresoc.v:159273.5-159273.29"
switch \initial
- attribute \src "libresoc.v:159609.9-159609.17"
+ attribute \src "libresoc.v:159273.9-159273.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:159620.3-159631.6"
- process $proc$libresoc.v:159620$8458
+ attribute \src "libresoc.v:159284.3-159295.6"
+ process $proc$libresoc.v:159284$8406
assign { } { }
- assign $0\o$28[64:0]$8459 $1\o$28[64:0]$8460
- attribute \src "libresoc.v:159621.5-159621.29"
+ assign $0\o$28[64:0]$8407 $1\o$28[64:0]$8408
+ attribute \src "libresoc.v:159285.5-159285.29"
switch \initial
- attribute \src "libresoc.v:159621.9-159621.17"
+ attribute \src "libresoc.v:159285.9-159285.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$28[64:0]$8460 \$29
+ assign $1\o$28[64:0]$8408 \$29
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$28[64:0]$8460 \$33
+ assign $1\o$28[64:0]$8408 \$33
end
sync always
- update \o$28 $0\o$28[64:0]$8459
+ update \o$28 $0\o$28[64:0]$8407
end
- attribute \src "libresoc.v:159632.3-159641.6"
- process $proc$libresoc.v:159632$8461
+ attribute \src "libresoc.v:159296.3-159305.6"
+ process $proc$libresoc.v:159296$8409
assign { } { }
assign { } { }
- assign $0\xer_so$25[0:0]$8462 $1\xer_so$25[0:0]$8463
- attribute \src "libresoc.v:159633.5-159633.29"
+ assign $0\xer_so$25[0:0]$8410 $1\xer_so$25[0:0]$8411
+ attribute \src "libresoc.v:159297.5-159297.29"
switch \initial
- attribute \src "libresoc.v:159633.9-159633.17"
+ attribute \src "libresoc.v:159297.9-159297.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$25[0:0]$8463 \$52
+ assign $1\xer_so$25[0:0]$8411 \$52
case
- assign $1\xer_so$25[0:0]$8463 1'0
+ assign $1\xer_so$25[0:0]$8411 1'0
end
sync always
- update \xer_so$25 $0\xer_so$25[0:0]$8462
+ update \xer_so$25 $0\xer_so$25[0:0]$8410
end
- attribute \src "libresoc.v:159642.3-159651.6"
- process $proc$libresoc.v:159642$8464
+ attribute \src "libresoc.v:159306.3-159315.6"
+ process $proc$libresoc.v:159306$8412
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:159643.5-159643.29"
+ attribute \src "libresoc.v:159307.5-159307.29"
switch \initial
- attribute \src "libresoc.v:159643.9-159643.17"
+ attribute \src "libresoc.v:159307.9-159307.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:159652.3-159661.6"
- process $proc$libresoc.v:159652$8465
+ attribute \src "libresoc.v:159316.3-159325.6"
+ process $proc$libresoc.v:159316$8413
assign { } { }
assign { } { }
- assign $0\xer_ov$24[1:0]$8466 $1\xer_ov$24[1:0]$8467
- attribute \src "libresoc.v:159653.5-159653.29"
+ assign $0\xer_ov$24[1:0]$8414 $1\xer_ov$24[1:0]$8415
+ attribute \src "libresoc.v:159317.5-159317.29"
switch \initial
- attribute \src "libresoc.v:159653.9-159653.17"
+ attribute \src "libresoc.v:159317.9-159317.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$24[1:0]$8467 \xer_ov
+ assign $1\xer_ov$24[1:0]$8415 \xer_ov
case
- assign $1\xer_ov$24[1:0]$8467 2'00
+ assign $1\xer_ov$24[1:0]$8415 2'00
end
sync always
- update \xer_ov$24 $0\xer_ov$24[1:0]$8466
+ update \xer_ov$24 $0\xer_ov$24[1:0]$8414
end
- attribute \src "libresoc.v:159662.3-159671.6"
- process $proc$libresoc.v:159662$8468
+ attribute \src "libresoc.v:159326.3-159335.6"
+ process $proc$libresoc.v:159326$8416
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:159663.5-159663.29"
+ attribute \src "libresoc.v:159327.5-159327.29"
switch \initial
- attribute \src "libresoc.v:159663.9-159663.17"
+ attribute \src "libresoc.v:159327.9-159327.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$26 $and$libresoc.v:159583$8441_Y
- connect \$30 $not$libresoc.v:159584$8442_Y
- connect \$29 $pos$libresoc.v:159585$8444_Y
- connect \$33 $pos$libresoc.v:159586$8446_Y
- connect \$35 $eq$libresoc.v:159587$8447_Y
- connect \$37 $eq$libresoc.v:159588$8448_Y
- connect \$39 $reduce_or$libresoc.v:159589$8449_Y
- connect \$41 $not$libresoc.v:159590$8450_Y
- connect \$43 $and$libresoc.v:159591$8451_Y
- connect \$45 $or$libresoc.v:159592$8452_Y
- connect \$47 $not$libresoc.v:159593$8453_Y
- connect \$50 $and$libresoc.v:159594$8454_Y
- connect \$52 $or$libresoc.v:159595$8455_Y
+ connect \$26 $and$libresoc.v:159247$8389_Y
+ connect \$30 $not$libresoc.v:159248$8390_Y
+ connect \$29 $pos$libresoc.v:159249$8392_Y
+ connect \$33 $pos$libresoc.v:159250$8394_Y
+ connect \$35 $eq$libresoc.v:159251$8395_Y
+ connect \$37 $eq$libresoc.v:159252$8396_Y
+ connect \$39 $reduce_or$libresoc.v:159253$8397_Y
+ connect \$41 $not$libresoc.v:159254$8398_Y
+ connect \$43 $and$libresoc.v:159255$8399_Y
+ connect \$45 $or$libresoc.v:159256$8400_Y
+ connect \$47 $not$libresoc.v:159257$8401_Y
+ connect \$50 $and$libresoc.v:159258$8402_Y
+ connect \$52 $or$libresoc.v:159259$8403_Y
connect \oe$49 \$50
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \target \o$28 [63:0]
connect \oe \$26
end
-attribute \src "libresoc.v:159693.1-160094.10"
+attribute \src "libresoc.v:159357.1-159758.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output"
attribute \generator "nMigen"
module \output$100
- attribute \src "libresoc.v:160026.3-160037.6"
+ attribute \src "libresoc.v:159690.3-159701.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:159694.7-159694.20"
+ attribute \src "libresoc.v:159358.7-159358.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:160014.3-160025.6"
+ attribute \src "libresoc.v:159678.3-159689.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:160058.3-160067.6"
- wire width 2 $0\xer_ov$17[1:0]$8489
- attribute \src "libresoc.v:160068.3-160077.6"
+ attribute \src "libresoc.v:159722.3-159731.6"
+ wire width 2 $0\xer_ov$17[1:0]$8437
+ attribute \src "libresoc.v:159732.3-159741.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:160038.3-160047.6"
- wire $0\xer_so$18[0:0]$8485
- attribute \src "libresoc.v:160048.3-160057.6"
+ attribute \src "libresoc.v:159702.3-159711.6"
+ wire $0\xer_so$18[0:0]$8433
+ attribute \src "libresoc.v:159712.3-159721.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:160026.3-160037.6"
+ attribute \src "libresoc.v:159690.3-159701.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:160014.3-160025.6"
+ attribute \src "libresoc.v:159678.3-159689.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:160058.3-160067.6"
- wire width 2 $1\xer_ov$17[1:0]$8490
- attribute \src "libresoc.v:160068.3-160077.6"
+ attribute \src "libresoc.v:159722.3-159731.6"
+ wire width 2 $1\xer_ov$17[1:0]$8438
+ attribute \src "libresoc.v:159732.3-159741.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:160038.3-160047.6"
- wire $1\xer_so$18[0:0]$8486
- attribute \src "libresoc.v:160048.3-160057.6"
+ attribute \src "libresoc.v:159702.3-159711.6"
+ wire $1\xer_so$18[0:0]$8434
+ attribute \src "libresoc.v:159712.3-159721.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:160003.18-160003.128"
- wire $and$libresoc.v:160003$8470_Y
- attribute \src "libresoc.v:160009.18-160009.112"
- wire $and$libresoc.v:160009$8477_Y
- attribute \src "libresoc.v:160012.18-160012.125"
- wire $and$libresoc.v:160012$8480_Y
- attribute \src "libresoc.v:160005.18-160005.123"
- wire $eq$libresoc.v:160005$8473_Y
- attribute \src "libresoc.v:160006.18-160006.123"
- wire $eq$libresoc.v:160006$8474_Y
- attribute \src "libresoc.v:160004.18-160004.101"
- wire width 65 $extend$libresoc.v:160004$8471_Y
- attribute \src "libresoc.v:160008.18-160008.107"
- wire $not$libresoc.v:160008$8476_Y
- attribute \src "libresoc.v:160011.18-160011.107"
- wire $not$libresoc.v:160011$8479_Y
- attribute \src "libresoc.v:160010.18-160010.115"
- wire $or$libresoc.v:160010$8478_Y
- attribute \src "libresoc.v:160013.18-160013.112"
- wire $or$libresoc.v:160013$8481_Y
- attribute \src "libresoc.v:160004.18-160004.101"
- wire width 65 $pos$libresoc.v:160004$8472_Y
- attribute \src "libresoc.v:160007.18-160007.105"
- wire $reduce_or$libresoc.v:160007$8475_Y
+ attribute \src "libresoc.v:159667.18-159667.128"
+ wire $and$libresoc.v:159667$8418_Y
+ attribute \src "libresoc.v:159673.18-159673.112"
+ wire $and$libresoc.v:159673$8425_Y
+ attribute \src "libresoc.v:159676.18-159676.125"
+ wire $and$libresoc.v:159676$8428_Y
+ attribute \src "libresoc.v:159669.18-159669.123"
+ wire $eq$libresoc.v:159669$8421_Y
+ attribute \src "libresoc.v:159670.18-159670.123"
+ wire $eq$libresoc.v:159670$8422_Y
+ attribute \src "libresoc.v:159668.18-159668.101"
+ wire width 65 $extend$libresoc.v:159668$8419_Y
+ attribute \src "libresoc.v:159672.18-159672.107"
+ wire $not$libresoc.v:159672$8424_Y
+ attribute \src "libresoc.v:159675.18-159675.107"
+ wire $not$libresoc.v:159675$8427_Y
+ attribute \src "libresoc.v:159674.18-159674.115"
+ wire $or$libresoc.v:159674$8426_Y
+ attribute \src "libresoc.v:159677.18-159677.112"
+ wire $or$libresoc.v:159677$8429_Y
+ attribute \src "libresoc.v:159668.18-159668.101"
+ wire width 65 $pos$libresoc.v:159668$8420_Y
+ attribute \src "libresoc.v:159671.18-159671.105"
+ wire $reduce_or$libresoc.v:159671$8423_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 33 \cr_a$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 34 \cr_a_ok
- attribute \src "libresoc.v:159694.7-159694.15"
+ attribute \src "libresoc.v:159358.7-159358.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 38 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:160003$8470
+ cell $and $and$libresoc.v:159667$8418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__oe__oe
connect \B \mul_op__oe__ok
- connect \Y $and$libresoc.v:160003$8470_Y
+ connect \Y $and$libresoc.v:159667$8418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:160009$8477
+ cell $and $and$libresoc.v:159673$8425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$30
- connect \Y $and$libresoc.v:160009$8477_Y
+ connect \Y $and$libresoc.v:159673$8425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:160012$8480
+ cell $and $and$libresoc.v:159676$8428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__oe__oe
connect \B \mul_op__oe__ok
- connect \Y $and$libresoc.v:160012$8480_Y
+ connect \Y $and$libresoc.v:159676$8428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:160005$8473
+ cell $eq $eq$libresoc.v:159669$8421
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:160005$8473_Y
+ connect \Y $eq$libresoc.v:159669$8421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:160006$8474
+ cell $eq $eq$libresoc.v:159670$8422
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:160006$8474_Y
+ connect \Y $eq$libresoc.v:159670$8422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:160004$8471
+ cell $pos $extend$libresoc.v:159668$8419
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:160004$8471_Y
+ connect \Y $extend$libresoc.v:159668$8419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:160008$8476
+ cell $not $not$libresoc.v:159672$8424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:160008$8476_Y
+ connect \Y $not$libresoc.v:159672$8424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:160011$8479
+ cell $not $not$libresoc.v:159675$8427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:160011$8479_Y
+ connect \Y $not$libresoc.v:159675$8427_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:160010$8478
+ cell $or $or$libresoc.v:159674$8426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:160010$8478_Y
+ connect \Y $or$libresoc.v:159674$8426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:160013$8481
+ cell $or $or$libresoc.v:159677$8429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:160013$8481_Y
+ connect \Y $or$libresoc.v:159677$8429_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:160004$8472
+ cell $pos $pos$libresoc.v:159668$8420
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:160004$8471_Y
- connect \Y $pos$libresoc.v:160004$8472_Y
+ connect \A $extend$libresoc.v:159668$8419_Y
+ connect \Y $pos$libresoc.v:159668$8420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:160007$8475
+ cell $reduce_or $reduce_or$libresoc.v:159671$8423
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:160007$8475_Y
+ connect \Y $reduce_or$libresoc.v:159671$8423_Y
end
- attribute \src "libresoc.v:159694.7-159694.20"
- process $proc$libresoc.v:159694$8492
+ attribute \src "libresoc.v:159358.7-159358.20"
+ process $proc$libresoc.v:159358$8440
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:160014.3-160025.6"
- process $proc$libresoc.v:160014$8482
+ attribute \src "libresoc.v:159678.3-159689.6"
+ process $proc$libresoc.v:159678$8430
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:160015.5-160015.29"
+ attribute \src "libresoc.v:159679.5-159679.29"
switch \initial
- attribute \src "libresoc.v:160015.9-160015.17"
+ attribute \src "libresoc.v:159679.9-159679.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:160026.3-160037.6"
- process $proc$libresoc.v:160026$8483
+ attribute \src "libresoc.v:159690.3-159701.6"
+ process $proc$libresoc.v:159690$8431
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:160027.5-160027.29"
+ attribute \src "libresoc.v:159691.5-159691.29"
switch \initial
- attribute \src "libresoc.v:160027.9-160027.17"
+ attribute \src "libresoc.v:159691.9-159691.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:160038.3-160047.6"
- process $proc$libresoc.v:160038$8484
+ attribute \src "libresoc.v:159702.3-159711.6"
+ process $proc$libresoc.v:159702$8432
assign { } { }
assign { } { }
- assign $0\xer_so$18[0:0]$8485 $1\xer_so$18[0:0]$8486
- attribute \src "libresoc.v:160039.5-160039.29"
+ assign $0\xer_so$18[0:0]$8433 $1\xer_so$18[0:0]$8434
+ attribute \src "libresoc.v:159703.5-159703.29"
switch \initial
- attribute \src "libresoc.v:160039.9-160039.17"
+ attribute \src "libresoc.v:159703.9-159703.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$18[0:0]$8486 \$41
+ assign $1\xer_so$18[0:0]$8434 \$41
case
- assign $1\xer_so$18[0:0]$8486 1'0
+ assign $1\xer_so$18[0:0]$8434 1'0
end
sync always
- update \xer_so$18 $0\xer_so$18[0:0]$8485
+ update \xer_so$18 $0\xer_so$18[0:0]$8433
end
- attribute \src "libresoc.v:160048.3-160057.6"
- process $proc$libresoc.v:160048$8487
+ attribute \src "libresoc.v:159712.3-159721.6"
+ process $proc$libresoc.v:159712$8435
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:160049.5-160049.29"
+ attribute \src "libresoc.v:159713.5-159713.29"
switch \initial
- attribute \src "libresoc.v:160049.9-160049.17"
+ attribute \src "libresoc.v:159713.9-159713.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:160058.3-160067.6"
- process $proc$libresoc.v:160058$8488
+ attribute \src "libresoc.v:159722.3-159731.6"
+ process $proc$libresoc.v:159722$8436
assign { } { }
assign { } { }
- assign $0\xer_ov$17[1:0]$8489 $1\xer_ov$17[1:0]$8490
- attribute \src "libresoc.v:160059.5-160059.29"
+ assign $0\xer_ov$17[1:0]$8437 $1\xer_ov$17[1:0]$8438
+ attribute \src "libresoc.v:159723.5-159723.29"
switch \initial
- attribute \src "libresoc.v:160059.9-160059.17"
+ attribute \src "libresoc.v:159723.9-159723.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$17[1:0]$8490 \xer_ov
+ assign $1\xer_ov$17[1:0]$8438 \xer_ov
case
- assign $1\xer_ov$17[1:0]$8490 2'00
+ assign $1\xer_ov$17[1:0]$8438 2'00
end
sync always
- update \xer_ov$17 $0\xer_ov$17[1:0]$8489
+ update \xer_ov$17 $0\xer_ov$17[1:0]$8437
end
- attribute \src "libresoc.v:160068.3-160077.6"
- process $proc$libresoc.v:160068$8491
+ attribute \src "libresoc.v:159732.3-159741.6"
+ process $proc$libresoc.v:159732$8439
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:160069.5-160069.29"
+ attribute \src "libresoc.v:159733.5-159733.29"
switch \initial
- attribute \src "libresoc.v:160069.9-160069.17"
+ attribute \src "libresoc.v:159733.9-159733.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$19 $and$libresoc.v:160003$8470_Y
- connect \$22 $pos$libresoc.v:160004$8472_Y
- connect \$24 $eq$libresoc.v:160005$8473_Y
- connect \$26 $eq$libresoc.v:160006$8474_Y
- connect \$28 $reduce_or$libresoc.v:160007$8475_Y
- connect \$30 $not$libresoc.v:160008$8476_Y
- connect \$32 $and$libresoc.v:160009$8477_Y
- connect \$34 $or$libresoc.v:160010$8478_Y
- connect \$36 $not$libresoc.v:160011$8479_Y
- connect \$39 $and$libresoc.v:160012$8480_Y
- connect \$41 $or$libresoc.v:160013$8481_Y
+ connect \$19 $and$libresoc.v:159667$8418_Y
+ connect \$22 $pos$libresoc.v:159668$8420_Y
+ connect \$24 $eq$libresoc.v:159669$8421_Y
+ connect \$26 $eq$libresoc.v:159670$8422_Y
+ connect \$28 $reduce_or$libresoc.v:159671$8423_Y
+ connect \$30 $not$libresoc.v:159672$8424_Y
+ connect \$32 $and$libresoc.v:159673$8425_Y
+ connect \$34 $or$libresoc.v:159674$8426_Y
+ connect \$36 $not$libresoc.v:159675$8427_Y
+ connect \$39 $and$libresoc.v:159676$8428_Y
+ connect \$41 $or$libresoc.v:159677$8429_Y
connect \oe$38 \$39
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \o$21 \$22
connect \oe \$19
end
-attribute \src "libresoc.v:160098.1-160452.10"
+attribute \src "libresoc.v:159762.1-160116.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output"
attribute \generator "nMigen"
module \output$118
- attribute \src "libresoc.v:160424.3-160435.6"
+ attribute \src "libresoc.v:160088.3-160099.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:160099.7-160099.20"
+ attribute \src "libresoc.v:159763.7-159763.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:160424.3-160435.6"
+ attribute \src "libresoc.v:160088.3-160099.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:160421.18-160421.112"
- wire $and$libresoc.v:160421$8499_Y
- attribute \src "libresoc.v:160417.18-160417.122"
- wire $eq$libresoc.v:160417$8495_Y
- attribute \src "libresoc.v:160418.18-160418.122"
- wire $eq$libresoc.v:160418$8496_Y
- attribute \src "libresoc.v:160416.18-160416.101"
- wire width 65 $extend$libresoc.v:160416$8493_Y
- attribute \src "libresoc.v:160420.18-160420.107"
- wire $not$libresoc.v:160420$8498_Y
- attribute \src "libresoc.v:160423.18-160423.107"
- wire $not$libresoc.v:160423$8501_Y
- attribute \src "libresoc.v:160422.18-160422.115"
- wire $or$libresoc.v:160422$8500_Y
- attribute \src "libresoc.v:160416.18-160416.101"
- wire width 65 $pos$libresoc.v:160416$8494_Y
- attribute \src "libresoc.v:160419.18-160419.105"
- wire $reduce_or$libresoc.v:160419$8497_Y
+ attribute \src "libresoc.v:160085.18-160085.112"
+ wire $and$libresoc.v:160085$8447_Y
+ attribute \src "libresoc.v:160081.18-160081.122"
+ wire $eq$libresoc.v:160081$8443_Y
+ attribute \src "libresoc.v:160082.18-160082.122"
+ wire $eq$libresoc.v:160082$8444_Y
+ attribute \src "libresoc.v:160080.18-160080.101"
+ wire width 65 $extend$libresoc.v:160080$8441_Y
+ attribute \src "libresoc.v:160084.18-160084.107"
+ wire $not$libresoc.v:160084$8446_Y
+ attribute \src "libresoc.v:160087.18-160087.107"
+ wire $not$libresoc.v:160087$8449_Y
+ attribute \src "libresoc.v:160086.18-160086.115"
+ wire $or$libresoc.v:160086$8448_Y
+ attribute \src "libresoc.v:160080.18-160080.101"
+ wire width 65 $pos$libresoc.v:160080$8442_Y
+ attribute \src "libresoc.v:160083.18-160083.105"
+ wire $reduce_or$libresoc.v:160083$8445_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire width 4 output 43 \cr_a$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 44 \cr_a_ok
- attribute \src "libresoc.v:160099.7-160099.15"
+ attribute \src "libresoc.v:159763.7-159763.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 21 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:160421$8499
+ cell $and $and$libresoc.v:160085$8447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$32
- connect \Y $and$libresoc.v:160421$8499_Y
+ connect \Y $and$libresoc.v:160085$8447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:160417$8495
+ cell $eq $eq$libresoc.v:160081$8443
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:160417$8495_Y
+ connect \Y $eq$libresoc.v:160081$8443_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:160418$8496
+ cell $eq $eq$libresoc.v:160082$8444
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:160418$8496_Y
+ connect \Y $eq$libresoc.v:160082$8444_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:160416$8493
+ cell $pos $extend$libresoc.v:160080$8441
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:160416$8493_Y
+ connect \Y $extend$libresoc.v:160080$8441_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:160420$8498
+ cell $not $not$libresoc.v:160084$8446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:160420$8498_Y
+ connect \Y $not$libresoc.v:160084$8446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:160423$8501
+ cell $not $not$libresoc.v:160087$8449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:160423$8501_Y
+ connect \Y $not$libresoc.v:160087$8449_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:160422$8500
+ cell $or $or$libresoc.v:160086$8448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:160422$8500_Y
+ connect \Y $or$libresoc.v:160086$8448_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:160416$8494
+ cell $pos $pos$libresoc.v:160080$8442
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:160416$8493_Y
- connect \Y $pos$libresoc.v:160416$8494_Y
+ connect \A $extend$libresoc.v:160080$8441_Y
+ connect \Y $pos$libresoc.v:160080$8442_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:160419$8497
+ cell $reduce_or $reduce_or$libresoc.v:160083$8445
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:160419$8497_Y
+ connect \Y $reduce_or$libresoc.v:160083$8445_Y
end
- attribute \src "libresoc.v:160099.7-160099.20"
- process $proc$libresoc.v:160099$8503
+ attribute \src "libresoc.v:159763.7-159763.20"
+ process $proc$libresoc.v:159763$8451
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:160424.3-160435.6"
- process $proc$libresoc.v:160424$8502
+ attribute \src "libresoc.v:160088.3-160099.6"
+ process $proc$libresoc.v:160088$8450
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:160425.5-160425.29"
+ attribute \src "libresoc.v:160089.5-160089.29"
switch \initial
- attribute \src "libresoc.v:160425.9-160425.17"
+ attribute \src "libresoc.v:160089.9-160089.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- connect \$24 $pos$libresoc.v:160416$8494_Y
- connect \$26 $eq$libresoc.v:160417$8495_Y
- connect \$28 $eq$libresoc.v:160418$8496_Y
- connect \$30 $reduce_or$libresoc.v:160419$8497_Y
- connect \$32 $not$libresoc.v:160420$8498_Y
- connect \$34 $and$libresoc.v:160421$8499_Y
- connect \$36 $or$libresoc.v:160422$8500_Y
- connect \$38 $not$libresoc.v:160423$8501_Y
+ connect \$24 $pos$libresoc.v:160080$8442_Y
+ connect \$26 $eq$libresoc.v:160081$8443_Y
+ connect \$28 $eq$libresoc.v:160082$8444_Y
+ connect \$30 $reduce_or$libresoc.v:160083$8445_Y
+ connect \$32 $not$libresoc.v:160084$8446_Y
+ connect \$34 $and$libresoc.v:160085$8447_Y
+ connect \$36 $or$libresoc.v:160086$8448_Y
+ connect \$38 $not$libresoc.v:160087$8449_Y
connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \muxid$1 \muxid
connect \cr_a_ok \sr_op__write_cr0
connect \target \o$23 [63:0]
connect \o$23 \$24
end
-attribute \src "libresoc.v:160456.1-160823.10"
+attribute \src "libresoc.v:160120.1-160487.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output"
attribute \generator "nMigen"
module \output$54
- attribute \src "libresoc.v:160798.3-160809.6"
+ attribute \src "libresoc.v:160462.3-160473.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:160457.7-160457.20"
+ attribute \src "libresoc.v:160121.7-160121.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:160786.3-160797.6"
- wire width 65 $0\o$23[64:0]$8517
- attribute \src "libresoc.v:160798.3-160809.6"
+ attribute \src "libresoc.v:160450.3-160461.6"
+ wire width 65 $0\o$23[64:0]$8465
+ attribute \src "libresoc.v:160462.3-160473.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:160786.3-160797.6"
- wire width 65 $1\o$23[64:0]$8518
- attribute \src "libresoc.v:160783.18-160783.112"
- wire $and$libresoc.v:160783$8513_Y
- attribute \src "libresoc.v:160779.18-160779.127"
- wire $eq$libresoc.v:160779$8509_Y
- attribute \src "libresoc.v:160780.18-160780.127"
- wire $eq$libresoc.v:160780$8510_Y
- attribute \src "libresoc.v:160777.18-160777.103"
- wire width 65 $extend$libresoc.v:160777$8505_Y
- attribute \src "libresoc.v:160778.18-160778.101"
- wire width 65 $extend$libresoc.v:160778$8507_Y
- attribute \src "libresoc.v:160776.18-160776.100"
- wire width 64 $not$libresoc.v:160776$8504_Y
- attribute \src "libresoc.v:160782.18-160782.107"
- wire $not$libresoc.v:160782$8512_Y
- attribute \src "libresoc.v:160785.18-160785.107"
- wire $not$libresoc.v:160785$8515_Y
- attribute \src "libresoc.v:160784.18-160784.115"
- wire $or$libresoc.v:160784$8514_Y
- attribute \src "libresoc.v:160777.18-160777.103"
- wire width 65 $pos$libresoc.v:160777$8506_Y
- attribute \src "libresoc.v:160778.18-160778.101"
- wire width 65 $pos$libresoc.v:160778$8508_Y
- attribute \src "libresoc.v:160781.18-160781.105"
- wire $reduce_or$libresoc.v:160781$8511_Y
+ attribute \src "libresoc.v:160450.3-160461.6"
+ wire width 65 $1\o$23[64:0]$8466
+ attribute \src "libresoc.v:160447.18-160447.112"
+ wire $and$libresoc.v:160447$8461_Y
+ attribute \src "libresoc.v:160443.18-160443.127"
+ wire $eq$libresoc.v:160443$8457_Y
+ attribute \src "libresoc.v:160444.18-160444.127"
+ wire $eq$libresoc.v:160444$8458_Y
+ attribute \src "libresoc.v:160441.18-160441.103"
+ wire width 65 $extend$libresoc.v:160441$8453_Y
+ attribute \src "libresoc.v:160442.18-160442.101"
+ wire width 65 $extend$libresoc.v:160442$8455_Y
+ attribute \src "libresoc.v:160440.18-160440.100"
+ wire width 64 $not$libresoc.v:160440$8452_Y
+ attribute \src "libresoc.v:160446.18-160446.107"
+ wire $not$libresoc.v:160446$8460_Y
+ attribute \src "libresoc.v:160449.18-160449.107"
+ wire $not$libresoc.v:160449$8463_Y
+ attribute \src "libresoc.v:160448.18-160448.115"
+ wire $or$libresoc.v:160448$8462_Y
+ attribute \src "libresoc.v:160441.18-160441.103"
+ wire width 65 $pos$libresoc.v:160441$8454_Y
+ attribute \src "libresoc.v:160442.18-160442.101"
+ wire width 65 $pos$libresoc.v:160442$8456_Y
+ attribute \src "libresoc.v:160445.18-160445.105"
+ wire $reduce_or$libresoc.v:160445$8459_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 44 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 45 \cr_a_ok
- attribute \src "libresoc.v:160457.7-160457.15"
+ attribute \src "libresoc.v:160121.7-160121.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 22 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:160783$8513
+ cell $and $and$libresoc.v:160447$8461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$36
- connect \Y $and$libresoc.v:160783$8513_Y
+ connect \Y $and$libresoc.v:160447$8461_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:160779$8509
+ cell $eq $eq$libresoc.v:160443$8457
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:160779$8509_Y
+ connect \Y $eq$libresoc.v:160443$8457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:160780$8510
+ cell $eq $eq$libresoc.v:160444$8458
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:160780$8510_Y
+ connect \Y $eq$libresoc.v:160444$8458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:160777$8505
+ cell $pos $extend$libresoc.v:160441$8453
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$25
- connect \Y $extend$libresoc.v:160777$8505_Y
+ connect \Y $extend$libresoc.v:160441$8453_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:160778$8507
+ cell $pos $extend$libresoc.v:160442$8455
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:160778$8507_Y
+ connect \Y $extend$libresoc.v:160442$8455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:160776$8504
+ cell $not $not$libresoc.v:160440$8452
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:160776$8504_Y
+ connect \Y $not$libresoc.v:160440$8452_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:160782$8512
+ cell $not $not$libresoc.v:160446$8460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:160782$8512_Y
+ connect \Y $not$libresoc.v:160446$8460_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:160785$8515
+ cell $not $not$libresoc.v:160449$8463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:160785$8515_Y
+ connect \Y $not$libresoc.v:160449$8463_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:160784$8514
+ cell $or $or$libresoc.v:160448$8462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:160784$8514_Y
+ connect \Y $or$libresoc.v:160448$8462_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:160777$8506
+ cell $pos $pos$libresoc.v:160441$8454
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:160777$8505_Y
- connect \Y $pos$libresoc.v:160777$8506_Y
+ connect \A $extend$libresoc.v:160441$8453_Y
+ connect \Y $pos$libresoc.v:160441$8454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:160778$8508
+ cell $pos $pos$libresoc.v:160442$8456
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:160778$8507_Y
- connect \Y $pos$libresoc.v:160778$8508_Y
+ connect \A $extend$libresoc.v:160442$8455_Y
+ connect \Y $pos$libresoc.v:160442$8456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:160781$8511
+ cell $reduce_or $reduce_or$libresoc.v:160445$8459
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:160781$8511_Y
+ connect \Y $reduce_or$libresoc.v:160445$8459_Y
end
- attribute \src "libresoc.v:160457.7-160457.20"
- process $proc$libresoc.v:160457$8520
+ attribute \src "libresoc.v:160121.7-160121.20"
+ process $proc$libresoc.v:160121$8468
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:160786.3-160797.6"
- process $proc$libresoc.v:160786$8516
+ attribute \src "libresoc.v:160450.3-160461.6"
+ process $proc$libresoc.v:160450$8464
assign { } { }
- assign $0\o$23[64:0]$8517 $1\o$23[64:0]$8518
- attribute \src "libresoc.v:160787.5-160787.29"
+ assign $0\o$23[64:0]$8465 $1\o$23[64:0]$8466
+ attribute \src "libresoc.v:160451.5-160451.29"
switch \initial
- attribute \src "libresoc.v:160787.9-160787.17"
+ attribute \src "libresoc.v:160451.9-160451.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$23[64:0]$8518 \$24
+ assign $1\o$23[64:0]$8466 \$24
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$23[64:0]$8518 \$28
+ assign $1\o$23[64:0]$8466 \$28
end
sync always
- update \o$23 $0\o$23[64:0]$8517
+ update \o$23 $0\o$23[64:0]$8465
end
- attribute \src "libresoc.v:160798.3-160809.6"
- process $proc$libresoc.v:160798$8519
+ attribute \src "libresoc.v:160462.3-160473.6"
+ process $proc$libresoc.v:160462$8467
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:160799.5-160799.29"
+ attribute \src "libresoc.v:160463.5-160463.29"
switch \initial
- attribute \src "libresoc.v:160799.9-160799.17"
+ attribute \src "libresoc.v:160463.9-160463.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- connect \$25 $not$libresoc.v:160776$8504_Y
- connect \$24 $pos$libresoc.v:160777$8506_Y
- connect \$28 $pos$libresoc.v:160778$8508_Y
- connect \$30 $eq$libresoc.v:160779$8509_Y
- connect \$32 $eq$libresoc.v:160780$8510_Y
- connect \$34 $reduce_or$libresoc.v:160781$8511_Y
- connect \$36 $not$libresoc.v:160782$8512_Y
- connect \$38 $and$libresoc.v:160783$8513_Y
- connect \$40 $or$libresoc.v:160784$8514_Y
- connect \$42 $not$libresoc.v:160785$8515_Y
+ connect \$25 $not$libresoc.v:160440$8452_Y
+ connect \$24 $pos$libresoc.v:160441$8454_Y
+ connect \$28 $pos$libresoc.v:160442$8456_Y
+ connect \$30 $eq$libresoc.v:160443$8457_Y
+ connect \$32 $eq$libresoc.v:160444$8458_Y
+ connect \$34 $reduce_or$libresoc.v:160445$8459_Y
+ connect \$36 $not$libresoc.v:160446$8460_Y
+ connect \$38 $and$libresoc.v:160447$8461_Y
+ connect \$40 $or$libresoc.v:160448$8462_Y
+ connect \$42 $not$libresoc.v:160449$8463_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \cr_a_ok \logical_op__write_cr0
connect \is_cmp \$30
connect \target \o$23 [63:0]
end
-attribute \src "libresoc.v:160827.1-161277.10"
+attribute \src "libresoc.v:160491.1-160941.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output"
attribute \generator "nMigen"
module \output$83
- attribute \src "libresoc.v:161198.3-161209.6"
+ attribute \src "libresoc.v:160862.3-160873.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:160828.7-160828.20"
+ attribute \src "libresoc.v:160492.7-160492.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:161210.3-161221.6"
- wire width 65 $0\o$27[64:0]$8539
- attribute \src "libresoc.v:161186.3-161197.6"
+ attribute \src "libresoc.v:160874.3-160885.6"
+ wire width 65 $0\o$27[64:0]$8487
+ attribute \src "libresoc.v:160850.3-160861.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:161242.3-161251.6"
- wire width 2 $0\xer_ov$23[1:0]$8546
- attribute \src "libresoc.v:161252.3-161261.6"
+ attribute \src "libresoc.v:160906.3-160915.6"
+ wire width 2 $0\xer_ov$23[1:0]$8494
+ attribute \src "libresoc.v:160916.3-160925.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:161222.3-161231.6"
- wire $0\xer_so$24[0:0]$8542
- attribute \src "libresoc.v:161232.3-161241.6"
+ attribute \src "libresoc.v:160886.3-160895.6"
+ wire $0\xer_so$24[0:0]$8490
+ attribute \src "libresoc.v:160896.3-160905.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:161198.3-161209.6"
+ attribute \src "libresoc.v:160862.3-160873.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:161210.3-161221.6"
- wire width 65 $1\o$27[64:0]$8540
- attribute \src "libresoc.v:161186.3-161197.6"
+ attribute \src "libresoc.v:160874.3-160885.6"
+ wire width 65 $1\o$27[64:0]$8488
+ attribute \src "libresoc.v:160850.3-160861.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:161242.3-161251.6"
- wire width 2 $1\xer_ov$23[1:0]$8547
- attribute \src "libresoc.v:161252.3-161261.6"
+ attribute \src "libresoc.v:160906.3-160915.6"
+ wire width 2 $1\xer_ov$23[1:0]$8495
+ attribute \src "libresoc.v:160916.3-160925.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:161222.3-161231.6"
- wire $1\xer_so$24[0:0]$8543
- attribute \src "libresoc.v:161232.3-161241.6"
+ attribute \src "libresoc.v:160886.3-160895.6"
+ wire $1\xer_so$24[0:0]$8491
+ attribute \src "libresoc.v:160896.3-160905.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:161173.18-161173.136"
- wire $and$libresoc.v:161173$8521_Y
- attribute \src "libresoc.v:161181.18-161181.112"
- wire $and$libresoc.v:161181$8531_Y
- attribute \src "libresoc.v:161184.18-161184.133"
- wire $and$libresoc.v:161184$8534_Y
- attribute \src "libresoc.v:161177.18-161177.127"
- wire $eq$libresoc.v:161177$8527_Y
- attribute \src "libresoc.v:161178.18-161178.127"
- wire $eq$libresoc.v:161178$8528_Y
- attribute \src "libresoc.v:161175.18-161175.103"
- wire width 65 $extend$libresoc.v:161175$8523_Y
- attribute \src "libresoc.v:161176.18-161176.101"
- wire width 65 $extend$libresoc.v:161176$8525_Y
- attribute \src "libresoc.v:161174.18-161174.100"
- wire width 64 $not$libresoc.v:161174$8522_Y
- attribute \src "libresoc.v:161180.18-161180.107"
- wire $not$libresoc.v:161180$8530_Y
- attribute \src "libresoc.v:161183.18-161183.107"
- wire $not$libresoc.v:161183$8533_Y
- attribute \src "libresoc.v:161182.18-161182.115"
- wire $or$libresoc.v:161182$8532_Y
- attribute \src "libresoc.v:161185.18-161185.112"
- wire $or$libresoc.v:161185$8535_Y
- attribute \src "libresoc.v:161175.18-161175.103"
- wire width 65 $pos$libresoc.v:161175$8524_Y
- attribute \src "libresoc.v:161176.18-161176.101"
- wire width 65 $pos$libresoc.v:161176$8526_Y
- attribute \src "libresoc.v:161179.18-161179.105"
- wire $reduce_or$libresoc.v:161179$8529_Y
+ attribute \src "libresoc.v:160837.18-160837.136"
+ wire $and$libresoc.v:160837$8469_Y
+ attribute \src "libresoc.v:160845.18-160845.112"
+ wire $and$libresoc.v:160845$8479_Y
+ attribute \src "libresoc.v:160848.18-160848.133"
+ wire $and$libresoc.v:160848$8482_Y
+ attribute \src "libresoc.v:160841.18-160841.127"
+ wire $eq$libresoc.v:160841$8475_Y
+ attribute \src "libresoc.v:160842.18-160842.127"
+ wire $eq$libresoc.v:160842$8476_Y
+ attribute \src "libresoc.v:160839.18-160839.103"
+ wire width 65 $extend$libresoc.v:160839$8471_Y
+ attribute \src "libresoc.v:160840.18-160840.101"
+ wire width 65 $extend$libresoc.v:160840$8473_Y
+ attribute \src "libresoc.v:160838.18-160838.100"
+ wire width 64 $not$libresoc.v:160838$8470_Y
+ attribute \src "libresoc.v:160844.18-160844.107"
+ wire $not$libresoc.v:160844$8478_Y
+ attribute \src "libresoc.v:160847.18-160847.107"
+ wire $not$libresoc.v:160847$8481_Y
+ attribute \src "libresoc.v:160846.18-160846.115"
+ wire $or$libresoc.v:160846$8480_Y
+ attribute \src "libresoc.v:160849.18-160849.112"
+ wire $or$libresoc.v:160849$8483_Y
+ attribute \src "libresoc.v:160839.18-160839.103"
+ wire width 65 $pos$libresoc.v:160839$8472_Y
+ attribute \src "libresoc.v:160840.18-160840.101"
+ wire width 65 $pos$libresoc.v:160840$8474_Y
+ attribute \src "libresoc.v:160843.18-160843.105"
+ wire $reduce_or$libresoc.v:160843$8477_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 45 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 46 \cr_a_ok
- attribute \src "libresoc.v:160828.7-160828.15"
+ attribute \src "libresoc.v:160492.7-160492.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 50 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:161173$8521
+ cell $and $and$libresoc.v:160837$8469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__oe__oe
connect \B \logical_op__oe__ok
- connect \Y $and$libresoc.v:161173$8521_Y
+ connect \Y $and$libresoc.v:160837$8469_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:161181$8531
+ cell $and $and$libresoc.v:160845$8479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$40
- connect \Y $and$libresoc.v:161181$8531_Y
+ connect \Y $and$libresoc.v:160845$8479_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:161184$8534
+ cell $and $and$libresoc.v:160848$8482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__oe__oe
connect \B \logical_op__oe__ok
- connect \Y $and$libresoc.v:161184$8534_Y
+ connect \Y $and$libresoc.v:160848$8482_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:161177$8527
+ cell $eq $eq$libresoc.v:160841$8475
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:161177$8527_Y
+ connect \Y $eq$libresoc.v:160841$8475_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:161178$8528
+ cell $eq $eq$libresoc.v:160842$8476
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:161178$8528_Y
+ connect \Y $eq$libresoc.v:160842$8476_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:161175$8523
+ cell $pos $extend$libresoc.v:160839$8471
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$29
- connect \Y $extend$libresoc.v:161175$8523_Y
+ connect \Y $extend$libresoc.v:160839$8471_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:161176$8525
+ cell $pos $extend$libresoc.v:160840$8473
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:161176$8525_Y
+ connect \Y $extend$libresoc.v:160840$8473_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:161174$8522
+ cell $not $not$libresoc.v:160838$8470
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:161174$8522_Y
+ connect \Y $not$libresoc.v:160838$8470_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:161180$8530
+ cell $not $not$libresoc.v:160844$8478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:161180$8530_Y
+ connect \Y $not$libresoc.v:160844$8478_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:161183$8533
+ cell $not $not$libresoc.v:160847$8481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:161183$8533_Y
+ connect \Y $not$libresoc.v:160847$8481_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:161182$8532
+ cell $or $or$libresoc.v:160846$8480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:161182$8532_Y
+ connect \Y $or$libresoc.v:160846$8480_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:161185$8535
+ cell $or $or$libresoc.v:160849$8483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:161185$8535_Y
+ connect \Y $or$libresoc.v:160849$8483_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:161175$8524
+ cell $pos $pos$libresoc.v:160839$8472
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161175$8523_Y
- connect \Y $pos$libresoc.v:161175$8524_Y
+ connect \A $extend$libresoc.v:160839$8471_Y
+ connect \Y $pos$libresoc.v:160839$8472_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:161176$8526
+ cell $pos $pos$libresoc.v:160840$8474
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161176$8525_Y
- connect \Y $pos$libresoc.v:161176$8526_Y
+ connect \A $extend$libresoc.v:160840$8473_Y
+ connect \Y $pos$libresoc.v:160840$8474_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:161179$8529
+ cell $reduce_or $reduce_or$libresoc.v:160843$8477
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:161179$8529_Y
+ connect \Y $reduce_or$libresoc.v:160843$8477_Y
end
- attribute \src "libresoc.v:160828.7-160828.20"
- process $proc$libresoc.v:160828$8549
+ attribute \src "libresoc.v:160492.7-160492.20"
+ process $proc$libresoc.v:160492$8497
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:161186.3-161197.6"
- process $proc$libresoc.v:161186$8536
+ attribute \src "libresoc.v:160850.3-160861.6"
+ process $proc$libresoc.v:160850$8484
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:161187.5-161187.29"
+ attribute \src "libresoc.v:160851.5-160851.29"
switch \initial
- attribute \src "libresoc.v:161187.9-161187.17"
+ attribute \src "libresoc.v:160851.9-160851.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:161198.3-161209.6"
- process $proc$libresoc.v:161198$8537
+ attribute \src "libresoc.v:160862.3-160873.6"
+ process $proc$libresoc.v:160862$8485
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:161199.5-161199.29"
+ attribute \src "libresoc.v:160863.5-160863.29"
switch \initial
- attribute \src "libresoc.v:161199.9-161199.17"
+ attribute \src "libresoc.v:160863.9-160863.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:161210.3-161221.6"
- process $proc$libresoc.v:161210$8538
+ attribute \src "libresoc.v:160874.3-160885.6"
+ process $proc$libresoc.v:160874$8486
assign { } { }
- assign $0\o$27[64:0]$8539 $1\o$27[64:0]$8540
- attribute \src "libresoc.v:161211.5-161211.29"
+ assign $0\o$27[64:0]$8487 $1\o$27[64:0]$8488
+ attribute \src "libresoc.v:160875.5-160875.29"
switch \initial
- attribute \src "libresoc.v:161211.9-161211.17"
+ attribute \src "libresoc.v:160875.9-160875.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$27[64:0]$8540 \$28
+ assign $1\o$27[64:0]$8488 \$28
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$27[64:0]$8540 \$32
+ assign $1\o$27[64:0]$8488 \$32
end
sync always
- update \o$27 $0\o$27[64:0]$8539
+ update \o$27 $0\o$27[64:0]$8487
end
- attribute \src "libresoc.v:161222.3-161231.6"
- process $proc$libresoc.v:161222$8541
+ attribute \src "libresoc.v:160886.3-160895.6"
+ process $proc$libresoc.v:160886$8489
assign { } { }
assign { } { }
- assign $0\xer_so$24[0:0]$8542 $1\xer_so$24[0:0]$8543
- attribute \src "libresoc.v:161223.5-161223.29"
+ assign $0\xer_so$24[0:0]$8490 $1\xer_so$24[0:0]$8491
+ attribute \src "libresoc.v:160887.5-160887.29"
switch \initial
- attribute \src "libresoc.v:161223.9-161223.17"
+ attribute \src "libresoc.v:160887.9-160887.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$24[0:0]$8543 \$51
+ assign $1\xer_so$24[0:0]$8491 \$51
case
- assign $1\xer_so$24[0:0]$8543 1'0
+ assign $1\xer_so$24[0:0]$8491 1'0
end
sync always
- update \xer_so$24 $0\xer_so$24[0:0]$8542
+ update \xer_so$24 $0\xer_so$24[0:0]$8490
end
- attribute \src "libresoc.v:161232.3-161241.6"
- process $proc$libresoc.v:161232$8544
+ attribute \src "libresoc.v:160896.3-160905.6"
+ process $proc$libresoc.v:160896$8492
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:161233.5-161233.29"
+ attribute \src "libresoc.v:160897.5-160897.29"
switch \initial
- attribute \src "libresoc.v:161233.9-161233.17"
+ attribute \src "libresoc.v:160897.9-160897.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:161242.3-161251.6"
- process $proc$libresoc.v:161242$8545
+ attribute \src "libresoc.v:160906.3-160915.6"
+ process $proc$libresoc.v:160906$8493
assign { } { }
assign { } { }
- assign $0\xer_ov$23[1:0]$8546 $1\xer_ov$23[1:0]$8547
- attribute \src "libresoc.v:161243.5-161243.29"
+ assign $0\xer_ov$23[1:0]$8494 $1\xer_ov$23[1:0]$8495
+ attribute \src "libresoc.v:160907.5-160907.29"
switch \initial
- attribute \src "libresoc.v:161243.9-161243.17"
+ attribute \src "libresoc.v:160907.9-160907.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$23[1:0]$8547 \xer_ov
+ assign $1\xer_ov$23[1:0]$8495 \xer_ov
case
- assign $1\xer_ov$23[1:0]$8547 2'00
+ assign $1\xer_ov$23[1:0]$8495 2'00
end
sync always
- update \xer_ov$23 $0\xer_ov$23[1:0]$8546
+ update \xer_ov$23 $0\xer_ov$23[1:0]$8494
end
- attribute \src "libresoc.v:161252.3-161261.6"
- process $proc$libresoc.v:161252$8548
+ attribute \src "libresoc.v:160916.3-160925.6"
+ process $proc$libresoc.v:160916$8496
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:161253.5-161253.29"
+ attribute \src "libresoc.v:160917.5-160917.29"
switch \initial
- attribute \src "libresoc.v:161253.9-161253.17"
+ attribute \src "libresoc.v:160917.9-160917.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$25 $and$libresoc.v:161173$8521_Y
- connect \$29 $not$libresoc.v:161174$8522_Y
- connect \$28 $pos$libresoc.v:161175$8524_Y
- connect \$32 $pos$libresoc.v:161176$8526_Y
- connect \$34 $eq$libresoc.v:161177$8527_Y
- connect \$36 $eq$libresoc.v:161178$8528_Y
- connect \$38 $reduce_or$libresoc.v:161179$8529_Y
- connect \$40 $not$libresoc.v:161180$8530_Y
- connect \$42 $and$libresoc.v:161181$8531_Y
- connect \$44 $or$libresoc.v:161182$8532_Y
- connect \$46 $not$libresoc.v:161183$8533_Y
- connect \$49 $and$libresoc.v:161184$8534_Y
- connect \$51 $or$libresoc.v:161185$8535_Y
+ connect \$25 $and$libresoc.v:160837$8469_Y
+ connect \$29 $not$libresoc.v:160838$8470_Y
+ connect \$28 $pos$libresoc.v:160839$8472_Y
+ connect \$32 $pos$libresoc.v:160840$8474_Y
+ connect \$34 $eq$libresoc.v:160841$8475_Y
+ connect \$36 $eq$libresoc.v:160842$8476_Y
+ connect \$38 $reduce_or$libresoc.v:160843$8477_Y
+ connect \$40 $not$libresoc.v:160844$8478_Y
+ connect \$42 $and$libresoc.v:160845$8479_Y
+ connect \$44 $or$libresoc.v:160846$8480_Y
+ connect \$46 $not$libresoc.v:160847$8481_Y
+ connect \$49 $and$libresoc.v:160848$8482_Y
+ connect \$51 $or$libresoc.v:160849$8483_Y
connect \oe$48 \$49
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \target \o$27 [63:0]
connect \oe \$25
end
-attribute \src "libresoc.v:161281.1-161763.10"
+attribute \src "libresoc.v:160945.1-161427.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage"
attribute \generator "nMigen"
module \output_stage
- attribute \src "libresoc.v:161282.7-161282.20"
+ attribute \src "libresoc.v:160946.7-160946.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:161716.3-161749.6"
+ attribute \src "libresoc.v:161380.3-161413.6"
wire $0\ov[0:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:161716.3-161749.6"
+ attribute \src "libresoc.v:161380.3-161413.6"
wire $1\ov[0:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:161716.3-161749.6"
+ attribute \src "libresoc.v:161380.3-161413.6"
wire $2\ov[0:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $3\o[63:0]
- attribute \src "libresoc.v:161716.3-161749.6"
+ attribute \src "libresoc.v:161380.3-161413.6"
wire $3\ov[0:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $4\o[63:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $5\o[63:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $6\o[63:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $7\o[63:0]
- attribute \src "libresoc.v:161644.3-161715.6"
+ attribute \src "libresoc.v:161308.3-161379.6"
wire width 64 $8\o[63:0]
- attribute \src "libresoc.v:161635.18-161635.122"
- wire $and$libresoc.v:161635$8563_Y
- attribute \src "libresoc.v:161627.18-161627.109"
- wire width 65 $extend$libresoc.v:161627$8551_Y
- attribute \src "libresoc.v:161628.18-161628.100"
- wire width 65 $extend$libresoc.v:161628$8553_Y
- attribute \src "libresoc.v:161630.18-161630.113"
- wire width 65 $extend$libresoc.v:161630$8556_Y
- attribute \src "libresoc.v:161631.18-161631.104"
- wire width 65 $extend$libresoc.v:161631$8558_Y
- attribute \src "libresoc.v:161639.18-161639.114"
- wire width 64 $extend$libresoc.v:161639$8567_Y
- attribute \src "libresoc.v:161640.18-161640.114"
- wire width 64 $extend$libresoc.v:161640$8569_Y
- attribute \src "libresoc.v:161641.18-161641.114"
- wire width 64 $extend$libresoc.v:161641$8571_Y
- attribute \src "libresoc.v:161642.18-161642.114"
- wire width 64 $extend$libresoc.v:161642$8573_Y
- attribute \src "libresoc.v:161643.18-161643.115"
- wire width 64 $extend$libresoc.v:161643$8575_Y
- attribute \src "libresoc.v:161636.18-161636.128"
- wire $ne$libresoc.v:161636$8564_Y
- attribute \src "libresoc.v:161627.18-161627.109"
- wire width 65 $neg$libresoc.v:161627$8552_Y
- attribute \src "libresoc.v:161630.18-161630.113"
- wire width 65 $neg$libresoc.v:161630$8557_Y
- attribute \src "libresoc.v:161633.18-161633.116"
- wire $not$libresoc.v:161633$8561_Y
- attribute \src "libresoc.v:161638.18-161638.99"
- wire $not$libresoc.v:161638$8566_Y
- attribute \src "libresoc.v:161628.18-161628.100"
- wire width 65 $pos$libresoc.v:161628$8554_Y
- attribute \src "libresoc.v:161631.18-161631.104"
- wire width 65 $pos$libresoc.v:161631$8559_Y
- attribute \src "libresoc.v:161637.18-161637.118"
- wire width 64 signed $pos$libresoc.v:161637$8565_Y
- attribute \src "libresoc.v:161639.18-161639.114"
- wire width 64 $pos$libresoc.v:161639$8568_Y
- attribute \src "libresoc.v:161640.18-161640.114"
- wire width 64 $pos$libresoc.v:161640$8570_Y
- attribute \src "libresoc.v:161641.18-161641.114"
- wire width 64 $pos$libresoc.v:161641$8572_Y
- attribute \src "libresoc.v:161642.18-161642.114"
- wire width 64 $pos$libresoc.v:161642$8574_Y
- attribute \src "libresoc.v:161643.18-161643.115"
- wire width 64 $pos$libresoc.v:161643$8576_Y
- attribute \src "libresoc.v:161629.18-161629.121"
- wire width 65 $ternary$libresoc.v:161629$8555_Y
- attribute \src "libresoc.v:161632.18-161632.122"
- wire width 65 $ternary$libresoc.v:161632$8560_Y
- attribute \src "libresoc.v:161626.18-161626.120"
- wire $xor$libresoc.v:161626$8550_Y
- attribute \src "libresoc.v:161634.18-161634.127"
- wire $xor$libresoc.v:161634$8562_Y
+ attribute \src "libresoc.v:161299.18-161299.122"
+ wire $and$libresoc.v:161299$8511_Y
+ attribute \src "libresoc.v:161291.18-161291.109"
+ wire width 65 $extend$libresoc.v:161291$8499_Y
+ attribute \src "libresoc.v:161292.18-161292.100"
+ wire width 65 $extend$libresoc.v:161292$8501_Y
+ attribute \src "libresoc.v:161294.18-161294.113"
+ wire width 65 $extend$libresoc.v:161294$8504_Y
+ attribute \src "libresoc.v:161295.18-161295.104"
+ wire width 65 $extend$libresoc.v:161295$8506_Y
+ attribute \src "libresoc.v:161303.18-161303.114"
+ wire width 64 $extend$libresoc.v:161303$8515_Y
+ attribute \src "libresoc.v:161304.18-161304.114"
+ wire width 64 $extend$libresoc.v:161304$8517_Y
+ attribute \src "libresoc.v:161305.18-161305.114"
+ wire width 64 $extend$libresoc.v:161305$8519_Y
+ attribute \src "libresoc.v:161306.18-161306.114"
+ wire width 64 $extend$libresoc.v:161306$8521_Y
+ attribute \src "libresoc.v:161307.18-161307.115"
+ wire width 64 $extend$libresoc.v:161307$8523_Y
+ attribute \src "libresoc.v:161300.18-161300.128"
+ wire $ne$libresoc.v:161300$8512_Y
+ attribute \src "libresoc.v:161291.18-161291.109"
+ wire width 65 $neg$libresoc.v:161291$8500_Y
+ attribute \src "libresoc.v:161294.18-161294.113"
+ wire width 65 $neg$libresoc.v:161294$8505_Y
+ attribute \src "libresoc.v:161297.18-161297.116"
+ wire $not$libresoc.v:161297$8509_Y
+ attribute \src "libresoc.v:161302.18-161302.99"
+ wire $not$libresoc.v:161302$8514_Y
+ attribute \src "libresoc.v:161292.18-161292.100"
+ wire width 65 $pos$libresoc.v:161292$8502_Y
+ attribute \src "libresoc.v:161295.18-161295.104"
+ wire width 65 $pos$libresoc.v:161295$8507_Y
+ attribute \src "libresoc.v:161301.18-161301.118"
+ wire width 64 signed $pos$libresoc.v:161301$8513_Y
+ attribute \src "libresoc.v:161303.18-161303.114"
+ wire width 64 $pos$libresoc.v:161303$8516_Y
+ attribute \src "libresoc.v:161304.18-161304.114"
+ wire width 64 $pos$libresoc.v:161304$8518_Y
+ attribute \src "libresoc.v:161305.18-161305.114"
+ wire width 64 $pos$libresoc.v:161305$8520_Y
+ attribute \src "libresoc.v:161306.18-161306.114"
+ wire width 64 $pos$libresoc.v:161306$8522_Y
+ attribute \src "libresoc.v:161307.18-161307.115"
+ wire width 64 $pos$libresoc.v:161307$8524_Y
+ attribute \src "libresoc.v:161293.18-161293.121"
+ wire width 65 $ternary$libresoc.v:161293$8503_Y
+ attribute \src "libresoc.v:161296.18-161296.122"
+ wire width 65 $ternary$libresoc.v:161296$8508_Y
+ attribute \src "libresoc.v:161290.18-161290.120"
+ wire $xor$libresoc.v:161290$8498_Y
+ attribute \src "libresoc.v:161298.18-161298.127"
+ wire $xor$libresoc.v:161298$8510_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
wire \$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
wire input 21 \dividend_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
wire input 20 \divisor_neg
- attribute \src "libresoc.v:161282.7-161282.15"
+ attribute \src "libresoc.v:160946.7-160946.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 50 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
- cell $and $and$libresoc.v:161635$8563
+ cell $and $and$libresoc.v:161299$8511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__is_signed
connect \B \$38
- connect \Y $and$libresoc.v:161635$8563_Y
+ connect \Y $and$libresoc.v:161299$8511_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $pos $extend$libresoc.v:161627$8551
+ cell $pos $extend$libresoc.v:161291$8499
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \quotient_root
- connect \Y $extend$libresoc.v:161627$8551_Y
+ connect \Y $extend$libresoc.v:161291$8499_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
- cell $pos $extend$libresoc.v:161628$8553
+ cell $pos $extend$libresoc.v:161292$8501
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \quotient_root
- connect \Y $extend$libresoc.v:161628$8553_Y
+ connect \Y $extend$libresoc.v:161292$8501_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $pos $extend$libresoc.v:161630$8556
+ cell $pos $extend$libresoc.v:161294$8504
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \remainder [127:64]
- connect \Y $extend$libresoc.v:161630$8556_Y
+ connect \Y $extend$libresoc.v:161294$8504_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:161631$8558
+ cell $pos $extend$libresoc.v:161295$8506
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \remainder [127:64]
- connect \Y $extend$libresoc.v:161631$8558_Y
+ connect \Y $extend$libresoc.v:161295$8506_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
- cell $pos $extend$libresoc.v:161639$8567
+ cell $pos $extend$libresoc.v:161303$8515
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:161639$8567_Y
+ connect \Y $extend$libresoc.v:161303$8515_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110"
- cell $pos $extend$libresoc.v:161640$8569
+ cell $pos $extend$libresoc.v:161304$8517
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:161640$8569_Y
+ connect \Y $extend$libresoc.v:161304$8517_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
- cell $pos $extend$libresoc.v:161641$8571
+ cell $pos $extend$libresoc.v:161305$8519
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:161641$8571_Y
+ connect \Y $extend$libresoc.v:161305$8519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119"
- cell $pos $extend$libresoc.v:161642$8573
+ cell $pos $extend$libresoc.v:161306$8521
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:161642$8573_Y
+ connect \Y $extend$libresoc.v:161306$8521_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128"
- cell $pos $extend$libresoc.v:161643$8575
+ cell $pos $extend$libresoc.v:161307$8523
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \remainder_64 [31:0]
- connect \Y $extend$libresoc.v:161643$8575_Y
+ connect \Y $extend$libresoc.v:161307$8523_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
- cell $ne $ne$libresoc.v:161636$8564
+ cell $ne $ne$libresoc.v:161300$8512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \quotient_65 [32]
connect \B \quotient_65 [31]
- connect \Y $ne$libresoc.v:161636$8564_Y
+ connect \Y $ne$libresoc.v:161300$8512_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $neg $neg$libresoc.v:161627$8552
+ cell $neg $neg$libresoc.v:161291$8500
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161627$8551_Y
- connect \Y $neg$libresoc.v:161627$8552_Y
+ connect \A $extend$libresoc.v:161291$8499_Y
+ connect \Y $neg$libresoc.v:161291$8500_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $neg $neg$libresoc.v:161630$8557
+ cell $neg $neg$libresoc.v:161294$8505
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161630$8556_Y
- connect \Y $neg$libresoc.v:161630$8557_Y
+ connect \A $extend$libresoc.v:161294$8504_Y
+ connect \Y $neg$libresoc.v:161294$8505_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78"
- cell $not $not$libresoc.v:161633$8561
+ cell $not $not$libresoc.v:161297$8509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \logical_op__is_32bit
- connect \Y $not$libresoc.v:161633$8561_Y
+ connect \Y $not$libresoc.v:161297$8509_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102"
- cell $not $not$libresoc.v:161638$8566
+ cell $not $not$libresoc.v:161302$8514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ov
- connect \Y $not$libresoc.v:161638$8566_Y
+ connect \Y $not$libresoc.v:161302$8514_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
- cell $pos $pos$libresoc.v:161628$8554
+ cell $pos $pos$libresoc.v:161292$8502
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161628$8553_Y
- connect \Y $pos$libresoc.v:161628$8554_Y
+ connect \A $extend$libresoc.v:161292$8501_Y
+ connect \Y $pos$libresoc.v:161292$8502_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:161631$8559
+ cell $pos $pos$libresoc.v:161295$8507
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:161631$8558_Y
- connect \Y $pos$libresoc.v:161631$8559_Y
+ connect \A $extend$libresoc.v:161295$8506_Y
+ connect \Y $pos$libresoc.v:161295$8507_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97"
- cell $pos $pos$libresoc.v:161637$8565
+ cell $pos $pos$libresoc.v:161301$8513
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 }
- connect \Y $pos$libresoc.v:161637$8565_Y
+ connect \Y $pos$libresoc.v:161301$8513_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
- cell $pos $pos$libresoc.v:161639$8568
+ cell $pos $pos$libresoc.v:161303$8516
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:161639$8567_Y
- connect \Y $pos$libresoc.v:161639$8568_Y
+ connect \A $extend$libresoc.v:161303$8515_Y
+ connect \Y $pos$libresoc.v:161303$8516_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110"
- cell $pos $pos$libresoc.v:161640$8570
+ cell $pos $pos$libresoc.v:161304$8518
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:161640$8569_Y
- connect \Y $pos$libresoc.v:161640$8570_Y
+ connect \A $extend$libresoc.v:161304$8517_Y
+ connect \Y $pos$libresoc.v:161304$8518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
- cell $pos $pos$libresoc.v:161641$8572
+ cell $pos $pos$libresoc.v:161305$8520
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:161641$8571_Y
- connect \Y $pos$libresoc.v:161641$8572_Y
+ connect \A $extend$libresoc.v:161305$8519_Y
+ connect \Y $pos$libresoc.v:161305$8520_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119"
- cell $pos $pos$libresoc.v:161642$8574
+ cell $pos $pos$libresoc.v:161306$8522
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:161642$8573_Y
- connect \Y $pos$libresoc.v:161642$8574_Y
+ connect \A $extend$libresoc.v:161306$8521_Y
+ connect \Y $pos$libresoc.v:161306$8522_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128"
- cell $pos $pos$libresoc.v:161643$8576
+ cell $pos $pos$libresoc.v:161307$8524
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:161643$8575_Y
- connect \Y $pos$libresoc.v:161643$8576_Y
+ connect \A $extend$libresoc.v:161307$8523_Y
+ connect \Y $pos$libresoc.v:161307$8524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $mux $ternary$libresoc.v:161629$8555
+ cell $mux $ternary$libresoc.v:161293$8503
parameter \WIDTH 65
connect \A \$25
connect \B \$23
connect \S \quotient_neg
- connect \Y $ternary$libresoc.v:161629$8555_Y
+ connect \Y $ternary$libresoc.v:161293$8503_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $mux $ternary$libresoc.v:161632$8560
+ cell $mux $ternary$libresoc.v:161296$8508
parameter \WIDTH 65
connect \A \$32
connect \B \$30
connect \S \remainder_neg
- connect \Y $ternary$libresoc.v:161632$8560_Y
+ connect \Y $ternary$libresoc.v:161296$8508_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
- cell $xor $xor$libresoc.v:161626$8550
+ cell $xor $xor$libresoc.v:161290$8498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dividend_neg
connect \B \divisor_neg
- connect \Y $xor$libresoc.v:161626$8550_Y
+ connect \Y $xor$libresoc.v:161290$8498_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
- cell $xor $xor$libresoc.v:161634$8562
+ cell $xor $xor$libresoc.v:161298$8510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \quotient_65 [64]
connect \B \quotient_65 [63]
- connect \Y $xor$libresoc.v:161634$8562_Y
+ connect \Y $xor$libresoc.v:161298$8510_Y
end
- attribute \src "libresoc.v:161282.7-161282.20"
- process $proc$libresoc.v:161282$8579
+ attribute \src "libresoc.v:160946.7-160946.20"
+ process $proc$libresoc.v:160946$8527
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:161644.3-161715.6"
- process $proc$libresoc.v:161644$8577
+ attribute \src "libresoc.v:161308.3-161379.6"
+ process $proc$libresoc.v:161308$8525
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:161645.5-161645.29"
+ attribute \src "libresoc.v:161309.5-161309.29"
switch \initial
- attribute \src "libresoc.v:161645.9-161645.17"
+ attribute \src "libresoc.v:161309.9-161309.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:161716.3-161749.6"
- process $proc$libresoc.v:161716$8578
+ attribute \src "libresoc.v:161380.3-161413.6"
+ process $proc$libresoc.v:161380$8526
assign { } { }
assign $0\ov[0:0] $1\ov[0:0]
- attribute \src "libresoc.v:161717.5-161717.29"
+ attribute \src "libresoc.v:161381.5-161381.29"
switch \initial
- attribute \src "libresoc.v:161717.9-161717.17"
+ attribute \src "libresoc.v:161381.9-161381.17"
case 1'1
case
end
sync always
update \ov $0\ov[0:0]
end
- connect \$21 $xor$libresoc.v:161626$8550_Y
- connect \$23 $neg$libresoc.v:161627$8552_Y
- connect \$25 $pos$libresoc.v:161628$8554_Y
- connect \$27 $ternary$libresoc.v:161629$8555_Y
- connect \$30 $neg$libresoc.v:161630$8557_Y
- connect \$32 $pos$libresoc.v:161631$8559_Y
- connect \$34 $ternary$libresoc.v:161632$8560_Y
- connect \$36 $not$libresoc.v:161633$8561_Y
- connect \$38 $xor$libresoc.v:161634$8562_Y
- connect \$40 $and$libresoc.v:161635$8563_Y
- connect \$42 $ne$libresoc.v:161636$8564_Y
- connect \$44 $pos$libresoc.v:161637$8565_Y
- connect \$46 $not$libresoc.v:161638$8566_Y
- connect \$48 $pos$libresoc.v:161639$8568_Y
- connect \$50 $pos$libresoc.v:161640$8570_Y
- connect \$52 $pos$libresoc.v:161641$8572_Y
- connect \$54 $pos$libresoc.v:161642$8574_Y
- connect \$56 $pos$libresoc.v:161643$8576_Y
+ connect \$21 $xor$libresoc.v:161290$8498_Y
+ connect \$23 $neg$libresoc.v:161291$8500_Y
+ connect \$25 $pos$libresoc.v:161292$8502_Y
+ connect \$27 $ternary$libresoc.v:161293$8503_Y
+ connect \$30 $neg$libresoc.v:161294$8505_Y
+ connect \$32 $pos$libresoc.v:161295$8507_Y
+ connect \$34 $ternary$libresoc.v:161296$8508_Y
+ connect \$36 $not$libresoc.v:161297$8509_Y
+ connect \$38 $xor$libresoc.v:161298$8510_Y
+ connect \$40 $and$libresoc.v:161299$8511_Y
+ connect \$42 $ne$libresoc.v:161300$8512_Y
+ connect \$44 $pos$libresoc.v:161301$8513_Y
+ connect \$46 $not$libresoc.v:161302$8514_Y
+ connect \$48 $pos$libresoc.v:161303$8516_Y
+ connect \$50 $pos$libresoc.v:161304$8518_Y
+ connect \$52 $pos$libresoc.v:161305$8520_Y
+ connect \$54 $pos$libresoc.v:161306$8522_Y
+ connect \$56 $pos$libresoc.v:161307$8524_Y
connect \$29 \$34
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \remainder_neg \dividend_neg
connect \quotient_neg \$21
end
-attribute \src "libresoc.v:161767.1-161778.10"
+attribute \src "libresoc.v:161431.1-161442.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p"
attribute \generator "nMigen"
module \p
- attribute \src "libresoc.v:161776.17-161776.111"
- wire $and$libresoc.v:161776$8580_Y
+ attribute \src "libresoc.v:161440.17-161440.111"
+ wire $and$libresoc.v:161440$8528_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161776$8580
+ cell $and $and$libresoc.v:161440$8528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161776$8580_Y
+ connect \Y $and$libresoc.v:161440$8528_Y
end
- connect \$1 $and$libresoc.v:161776$8580_Y
+ connect \$1 $and$libresoc.v:161440$8528_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161782.1-161793.10"
+attribute \src "libresoc.v:161446.1-161457.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p"
attribute \generator "nMigen"
module \p$1
- attribute \src "libresoc.v:161791.17-161791.111"
- wire $and$libresoc.v:161791$8581_Y
+ attribute \src "libresoc.v:161455.17-161455.111"
+ wire $and$libresoc.v:161455$8529_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161791$8581
+ cell $and $and$libresoc.v:161455$8529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161791$8581_Y
+ connect \Y $and$libresoc.v:161455$8529_Y
end
- connect \$1 $and$libresoc.v:161791$8581_Y
+ connect \$1 $and$libresoc.v:161455$8529_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161797.1-161808.10"
+attribute \src "libresoc.v:161461.1-161472.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p"
attribute \generator "nMigen"
module \p$108
- attribute \src "libresoc.v:161806.17-161806.111"
- wire $and$libresoc.v:161806$8582_Y
+ attribute \src "libresoc.v:161470.17-161470.111"
+ wire $and$libresoc.v:161470$8530_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161806$8582
+ cell $and $and$libresoc.v:161470$8530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161806$8582_Y
+ connect \Y $and$libresoc.v:161470$8530_Y
end
- connect \$1 $and$libresoc.v:161806$8582_Y
+ connect \$1 $and$libresoc.v:161470$8530_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161812.1-161823.10"
+attribute \src "libresoc.v:161476.1-161487.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p"
attribute \generator "nMigen"
module \p$111
- attribute \src "libresoc.v:161821.17-161821.111"
- wire $and$libresoc.v:161821$8583_Y
+ attribute \src "libresoc.v:161485.17-161485.111"
+ wire $and$libresoc.v:161485$8531_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161821$8583
+ cell $and $and$libresoc.v:161485$8531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161821$8583_Y
+ connect \Y $and$libresoc.v:161485$8531_Y
end
- connect \$1 $and$libresoc.v:161821$8583_Y
+ connect \$1 $and$libresoc.v:161485$8531_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161827.1-161838.10"
+attribute \src "libresoc.v:161491.1-161502.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p"
attribute \generator "nMigen"
module \p$116
- attribute \src "libresoc.v:161836.17-161836.111"
- wire $and$libresoc.v:161836$8584_Y
+ attribute \src "libresoc.v:161500.17-161500.111"
+ wire $and$libresoc.v:161500$8532_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161836$8584
+ cell $and $and$libresoc.v:161500$8532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161836$8584_Y
+ connect \Y $and$libresoc.v:161500$8532_Y
end
- connect \$1 $and$libresoc.v:161836$8584_Y
+ connect \$1 $and$libresoc.v:161500$8532_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161842.1-161853.10"
+attribute \src "libresoc.v:161506.1-161517.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p"
attribute \generator "nMigen"
module \p$17
- attribute \src "libresoc.v:161851.17-161851.111"
- wire $and$libresoc.v:161851$8585_Y
+ attribute \src "libresoc.v:161515.17-161515.111"
+ wire $and$libresoc.v:161515$8533_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161851$8585
+ cell $and $and$libresoc.v:161515$8533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161851$8585_Y
+ connect \Y $and$libresoc.v:161515$8533_Y
end
- connect \$1 $and$libresoc.v:161851$8585_Y
+ connect \$1 $and$libresoc.v:161515$8533_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161857.1-161868.10"
+attribute \src "libresoc.v:161521.1-161532.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p"
attribute \generator "nMigen"
module \p$20
- attribute \src "libresoc.v:161866.17-161866.111"
- wire $and$libresoc.v:161866$8586_Y
+ attribute \src "libresoc.v:161530.17-161530.111"
+ wire $and$libresoc.v:161530$8534_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161866$8586
+ cell $and $and$libresoc.v:161530$8534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161866$8586_Y
+ connect \Y $and$libresoc.v:161530$8534_Y
end
- connect \$1 $and$libresoc.v:161866$8586_Y
+ connect \$1 $and$libresoc.v:161530$8534_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161872.1-161883.10"
+attribute \src "libresoc.v:161536.1-161547.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p"
attribute \generator "nMigen"
module \p$3
- attribute \src "libresoc.v:161881.17-161881.111"
- wire $and$libresoc.v:161881$8587_Y
+ attribute \src "libresoc.v:161545.17-161545.111"
+ wire $and$libresoc.v:161545$8535_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161881$8587
+ cell $and $and$libresoc.v:161545$8535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161881$8587_Y
+ connect \Y $and$libresoc.v:161545$8535_Y
end
- connect \$1 $and$libresoc.v:161881$8587_Y
+ connect \$1 $and$libresoc.v:161545$8535_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161887.1-161898.10"
+attribute \src "libresoc.v:161551.1-161562.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p"
attribute \generator "nMigen"
module \p$30
- attribute \src "libresoc.v:161896.17-161896.111"
- wire $and$libresoc.v:161896$8588_Y
+ attribute \src "libresoc.v:161560.17-161560.111"
+ wire $and$libresoc.v:161560$8536_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161896$8588
+ cell $and $and$libresoc.v:161560$8536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161896$8588_Y
+ connect \Y $and$libresoc.v:161560$8536_Y
end
- connect \$1 $and$libresoc.v:161896$8588_Y
+ connect \$1 $and$libresoc.v:161560$8536_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161902.1-161913.10"
+attribute \src "libresoc.v:161566.1-161577.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p"
attribute \generator "nMigen"
module \p$33
- attribute \src "libresoc.v:161911.17-161911.111"
- wire $and$libresoc.v:161911$8589_Y
+ attribute \src "libresoc.v:161575.17-161575.111"
+ wire $and$libresoc.v:161575$8537_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161911$8589
+ cell $and $and$libresoc.v:161575$8537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161911$8589_Y
+ connect \Y $and$libresoc.v:161575$8537_Y
end
- connect \$1 $and$libresoc.v:161911$8589_Y
+ connect \$1 $and$libresoc.v:161575$8537_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161917.1-161928.10"
+attribute \src "libresoc.v:161581.1-161592.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p"
attribute \generator "nMigen"
module \p$36
- attribute \src "libresoc.v:161926.17-161926.111"
- wire $and$libresoc.v:161926$8590_Y
+ attribute \src "libresoc.v:161590.17-161590.111"
+ wire $and$libresoc.v:161590$8538_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161926$8590
+ cell $and $and$libresoc.v:161590$8538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161926$8590_Y
+ connect \Y $and$libresoc.v:161590$8538_Y
end
- connect \$1 $and$libresoc.v:161926$8590_Y
+ connect \$1 $and$libresoc.v:161590$8538_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161932.1-161943.10"
+attribute \src "libresoc.v:161596.1-161607.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p"
attribute \generator "nMigen"
module \p$46
- attribute \src "libresoc.v:161941.17-161941.111"
- wire $and$libresoc.v:161941$8591_Y
+ attribute \src "libresoc.v:161605.17-161605.111"
+ wire $and$libresoc.v:161605$8539_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161941$8591
+ cell $and $and$libresoc.v:161605$8539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161941$8591_Y
+ connect \Y $and$libresoc.v:161605$8539_Y
end
- connect \$1 $and$libresoc.v:161941$8591_Y
+ connect \$1 $and$libresoc.v:161605$8539_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161947.1-161958.10"
+attribute \src "libresoc.v:161611.1-161622.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p"
attribute \generator "nMigen"
module \p$48
- attribute \src "libresoc.v:161956.17-161956.111"
- wire $and$libresoc.v:161956$8592_Y
+ attribute \src "libresoc.v:161620.17-161620.111"
+ wire $and$libresoc.v:161620$8540_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161956$8592
+ cell $and $and$libresoc.v:161620$8540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161956$8592_Y
+ connect \Y $and$libresoc.v:161620$8540_Y
end
- connect \$1 $and$libresoc.v:161956$8592_Y
+ connect \$1 $and$libresoc.v:161620$8540_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161962.1-161973.10"
+attribute \src "libresoc.v:161626.1-161637.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p"
attribute \generator "nMigen"
module \p$5
- attribute \src "libresoc.v:161971.17-161971.111"
- wire $and$libresoc.v:161971$8593_Y
+ attribute \src "libresoc.v:161635.17-161635.111"
+ wire $and$libresoc.v:161635$8541_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161971$8593
+ cell $and $and$libresoc.v:161635$8541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161971$8593_Y
+ connect \Y $and$libresoc.v:161635$8541_Y
end
- connect \$1 $and$libresoc.v:161971$8593_Y
+ connect \$1 $and$libresoc.v:161635$8541_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161977.1-161988.10"
+attribute \src "libresoc.v:161641.1-161652.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p"
attribute \generator "nMigen"
module \p$52
- attribute \src "libresoc.v:161986.17-161986.111"
- wire $and$libresoc.v:161986$8594_Y
+ attribute \src "libresoc.v:161650.17-161650.111"
+ wire $and$libresoc.v:161650$8542_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:161986$8594
+ cell $and $and$libresoc.v:161650$8542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161986$8594_Y
+ connect \Y $and$libresoc.v:161650$8542_Y
end
- connect \$1 $and$libresoc.v:161986$8594_Y
+ connect \$1 $and$libresoc.v:161650$8542_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:161992.1-162003.10"
+attribute \src "libresoc.v:161656.1-161667.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p"
attribute \generator "nMigen"
module \p$62
- attribute \src "libresoc.v:162001.17-162001.111"
- wire $and$libresoc.v:162001$8595_Y
+ attribute \src "libresoc.v:161665.17-161665.111"
+ wire $and$libresoc.v:161665$8543_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162001$8595
+ cell $and $and$libresoc.v:161665$8543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162001$8595_Y
+ connect \Y $and$libresoc.v:161665$8543_Y
end
- connect \$1 $and$libresoc.v:162001$8595_Y
+ connect \$1 $and$libresoc.v:161665$8543_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162007.1-162018.10"
+attribute \src "libresoc.v:161671.1-161682.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p"
attribute \generator "nMigen"
module \p$65
- attribute \src "libresoc.v:162016.17-162016.111"
- wire $and$libresoc.v:162016$8596_Y
+ attribute \src "libresoc.v:161680.17-161680.111"
+ wire $and$libresoc.v:161680$8544_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162016$8596
+ cell $and $and$libresoc.v:161680$8544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162016$8596_Y
+ connect \Y $and$libresoc.v:161680$8544_Y
end
- connect \$1 $and$libresoc.v:162016$8596_Y
+ connect \$1 $and$libresoc.v:161680$8544_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162022.1-162033.10"
+attribute \src "libresoc.v:161686.1-161697.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p"
attribute \generator "nMigen"
module \p$7
- attribute \src "libresoc.v:162031.17-162031.111"
- wire $and$libresoc.v:162031$8597_Y
+ attribute \src "libresoc.v:161695.17-161695.111"
+ wire $and$libresoc.v:161695$8545_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162031$8597
+ cell $and $and$libresoc.v:161695$8545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162031$8597_Y
+ connect \Y $and$libresoc.v:161695$8545_Y
end
- connect \$1 $and$libresoc.v:162031$8597_Y
+ connect \$1 $and$libresoc.v:161695$8545_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162037.1-162048.10"
+attribute \src "libresoc.v:161701.1-161712.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p"
attribute \generator "nMigen"
module \p$74
- attribute \src "libresoc.v:162046.17-162046.111"
- wire $and$libresoc.v:162046$8598_Y
+ attribute \src "libresoc.v:161710.17-161710.111"
+ wire $and$libresoc.v:161710$8546_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162046$8598
+ cell $and $and$libresoc.v:161710$8546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162046$8598_Y
+ connect \Y $and$libresoc.v:161710$8546_Y
end
- connect \$1 $and$libresoc.v:162046$8598_Y
+ connect \$1 $and$libresoc.v:161710$8546_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162052.1-162063.10"
+attribute \src "libresoc.v:161716.1-161727.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p"
attribute \generator "nMigen"
module \p$76
- attribute \src "libresoc.v:162061.17-162061.111"
- wire $and$libresoc.v:162061$8599_Y
+ attribute \src "libresoc.v:161725.17-161725.111"
+ wire $and$libresoc.v:161725$8547_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162061$8599
+ cell $and $and$libresoc.v:161725$8547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162061$8599_Y
+ connect \Y $and$libresoc.v:161725$8547_Y
end
- connect \$1 $and$libresoc.v:162061$8599_Y
+ connect \$1 $and$libresoc.v:161725$8547_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162067.1-162078.10"
+attribute \src "libresoc.v:161731.1-161742.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p"
attribute \generator "nMigen"
module \p$79
- attribute \src "libresoc.v:162076.17-162076.111"
- wire $and$libresoc.v:162076$8600_Y
+ attribute \src "libresoc.v:161740.17-161740.111"
+ wire $and$libresoc.v:161740$8548_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162076$8600
+ cell $and $and$libresoc.v:161740$8548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162076$8600_Y
+ connect \Y $and$libresoc.v:161740$8548_Y
end
- connect \$1 $and$libresoc.v:162076$8600_Y
+ connect \$1 $and$libresoc.v:161740$8548_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162082.1-162093.10"
+attribute \src "libresoc.v:161746.1-161757.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p"
attribute \generator "nMigen"
module \p$81
- attribute \src "libresoc.v:162091.17-162091.111"
- wire $and$libresoc.v:162091$8601_Y
+ attribute \src "libresoc.v:161755.17-161755.111"
+ wire $and$libresoc.v:161755$8549_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162091$8601
+ cell $and $and$libresoc.v:161755$8549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162091$8601_Y
+ connect \Y $and$libresoc.v:161755$8549_Y
end
- connect \$1 $and$libresoc.v:162091$8601_Y
+ connect \$1 $and$libresoc.v:161755$8549_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162097.1-162108.10"
+attribute \src "libresoc.v:161761.1-161772.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p"
attribute \generator "nMigen"
module \p$91
- attribute \src "libresoc.v:162106.17-162106.111"
- wire $and$libresoc.v:162106$8602_Y
+ attribute \src "libresoc.v:161770.17-161770.111"
+ wire $and$libresoc.v:161770$8550_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162106$8602
+ cell $and $and$libresoc.v:161770$8550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162106$8602_Y
+ connect \Y $and$libresoc.v:161770$8550_Y
end
- connect \$1 $and$libresoc.v:162106$8602_Y
+ connect \$1 $and$libresoc.v:161770$8550_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162112.1-162123.10"
+attribute \src "libresoc.v:161776.1-161787.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p"
attribute \generator "nMigen"
module \p$93
- attribute \src "libresoc.v:162121.17-162121.111"
- wire $and$libresoc.v:162121$8603_Y
+ attribute \src "libresoc.v:161785.17-161785.111"
+ wire $and$libresoc.v:161785$8551_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162121$8603
+ cell $and $and$libresoc.v:161785$8551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162121$8603_Y
+ connect \Y $and$libresoc.v:161785$8551_Y
end
- connect \$1 $and$libresoc.v:162121$8603_Y
+ connect \$1 $and$libresoc.v:161785$8551_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162127.1-162138.10"
+attribute \src "libresoc.v:161791.1-161802.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p"
attribute \generator "nMigen"
module \p$96
- attribute \src "libresoc.v:162136.17-162136.111"
- wire $and$libresoc.v:162136$8604_Y
+ attribute \src "libresoc.v:161800.17-161800.111"
+ wire $and$libresoc.v:161800$8552_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162136$8604
+ cell $and $and$libresoc.v:161800$8552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162136$8604_Y
+ connect \Y $and$libresoc.v:161800$8552_Y
end
- connect \$1 $and$libresoc.v:162136$8604_Y
+ connect \$1 $and$libresoc.v:161800$8552_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162142.1-162153.10"
+attribute \src "libresoc.v:161806.1-161817.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p"
attribute \generator "nMigen"
module \p$98
- attribute \src "libresoc.v:162151.17-162151.111"
- wire $and$libresoc.v:162151$8605_Y
+ attribute \src "libresoc.v:161815.17-161815.111"
+ wire $and$libresoc.v:161815$8553_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:162151$8605
+ cell $and $and$libresoc.v:161815$8553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162151$8605_Y
+ connect \Y $and$libresoc.v:161815$8553_Y
end
- connect \$1 $and$libresoc.v:162151$8605_Y
+ connect \$1 $and$libresoc.v:161815$8553_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:162157.1-162180.10"
+attribute \src "libresoc.v:161821.1-161844.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick"
attribute \generator "nMigen"
module \pick
- attribute \src "libresoc.v:162158.7-162158.20"
+ attribute \src "libresoc.v:161822.7-161822.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:162169.3-162178.6"
+ attribute \src "libresoc.v:161833.3-161842.6"
wire $0\o[0:0]
- attribute \src "libresoc.v:162169.3-162178.6"
+ attribute \src "libresoc.v:161833.3-161842.6"
wire $1\o[0:0]
- attribute \src "libresoc.v:162168.17-162168.95"
- wire $eq$libresoc.v:162168$8606_Y
+ attribute \src "libresoc.v:161832.17-161832.95"
+ wire $eq$libresoc.v:161832$8554_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
wire input 3 \i
- attribute \src "libresoc.v:162158.7-162158.15"
+ attribute \src "libresoc.v:161822.7-161822.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
wire output 2 \n
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
wire output 1 \o
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
- cell $eq $eq$libresoc.v:162168$8606
+ cell $eq $eq$libresoc.v:161832$8554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i
connect \B 1'0
- connect \Y $eq$libresoc.v:162168$8606_Y
+ connect \Y $eq$libresoc.v:161832$8554_Y
end
- attribute \src "libresoc.v:162158.7-162158.20"
- process $proc$libresoc.v:162158$8608
+ attribute \src "libresoc.v:161822.7-161822.20"
+ process $proc$libresoc.v:161822$8556
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:162169.3-162178.6"
- process $proc$libresoc.v:162169$8607
+ attribute \src "libresoc.v:161833.3-161842.6"
+ process $proc$libresoc.v:161833$8555
assign { } { }
assign { } { }
assign $0\o[0:0] $1\o[0:0]
- attribute \src "libresoc.v:162170.5-162170.29"
+ attribute \src "libresoc.v:161834.5-161834.29"
switch \initial
- attribute \src "libresoc.v:162170.9-162170.17"
+ attribute \src "libresoc.v:161834.9-161834.17"
case 1'1
case
end
sync always
update \o $0\o[0:0]
end
- connect \$1 $eq$libresoc.v:162168$8606_Y
+ connect \$1 $eq$libresoc.v:161832$8554_Y
connect \n \$1
end
-attribute \src "libresoc.v:162184.1-162998.10"
+attribute \src "libresoc.v:161848.1-162662.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem"
attribute \generator "nMigen"
module \pimem
- attribute \src "libresoc.v:162961.3-162976.6"
+ attribute \src "libresoc.v:162625.3-162640.6"
wire $0\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $0\adrok_l_s_addr_acked$next[0:0]$8698
- attribute \src "libresoc.v:162483.3-162484.57"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $0\adrok_l_s_addr_acked$next[0:0]$8646
+ attribute \src "libresoc.v:162147.3-162148.57"
wire $0\adrok_l_s_addr_acked[0:0]
- attribute \src "libresoc.v:162575.3-162583.6"
- wire $0\busy_delay$next[0:0]$8666
- attribute \src "libresoc.v:162481.3-162482.37"
+ attribute \src "libresoc.v:162239.3-162247.6"
+ wire $0\busy_delay$next[0:0]$8614
+ attribute \src "libresoc.v:162145.3-162146.37"
wire $0\busy_delay[0:0]
- attribute \src "libresoc.v:162909.3-162924.6"
+ attribute \src "libresoc.v:162573.3-162588.6"
wire $0\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:162899.3-162908.6"
+ attribute \src "libresoc.v:162563.3-162572.6"
wire $0\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:162889.3-162898.6"
+ attribute \src "libresoc.v:162553.3-162562.6"
wire $0\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:162870.3-162879.6"
+ attribute \src "libresoc.v:162534.3-162543.6"
wire $0\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $0\fsm_state$next[1:0]$8684
- attribute \src "libresoc.v:162473.3-162474.35"
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $0\fsm_state$next[1:0]$8632
+ attribute \src "libresoc.v:162137.3-162138.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:162185.7-162185.20"
+ attribute \src "libresoc.v:161849.7-161849.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:162771.3-162780.6"
+ attribute \src "libresoc.v:162435.3-162444.6"
wire $0\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:162479.3-162480.35"
+ attribute \src "libresoc.v:162143.3-162144.35"
wire $0\lds_dly[0:0]
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $0\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162761.3-162770.6"
+ attribute \src "libresoc.v:162425.3-162434.6"
wire width 64 $0\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:162781.3-162790.6"
+ attribute \src "libresoc.v:162445.3-162454.6"
wire $0\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:162610.3-162625.6"
+ attribute \src "libresoc.v:162274.3-162289.6"
wire width 4 $0\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:162594.3-162609.6"
+ attribute \src "libresoc.v:162258.3-162273.6"
wire width 4 $0\lenexp_len_i[3:0]
- attribute \src "libresoc.v:162880.3-162888.6"
- wire $0\lsui_active_dly$next[0:0]$8692
- attribute \src "libresoc.v:162471.3-162472.47"
+ attribute \src "libresoc.v:162544.3-162552.6"
+ wire $0\lsui_active_dly$next[0:0]$8640
+ attribute \src "libresoc.v:162135.3-162136.47"
wire $0\lsui_active_dly[0:0]
- attribute \src "libresoc.v:162811.3-162830.6"
+ attribute \src "libresoc.v:162475.3-162494.6"
wire $0\lsui_busy[0:0]
- attribute \src "libresoc.v:162475.3-162476.36"
+ attribute \src "libresoc.v:162139.3-162140.36"
wire $0\reset_delay[0:0]
- attribute \src "libresoc.v:162751.3-162760.6"
+ attribute \src "libresoc.v:162415.3-162424.6"
wire $0\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:162735.3-162750.6"
+ attribute \src "libresoc.v:162399.3-162414.6"
wire $0\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:162584.3-162593.6"
+ attribute \src "libresoc.v:162248.3-162257.6"
wire $0\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:162565.3-162574.6"
+ attribute \src "libresoc.v:162229.3-162238.6"
wire $0\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:162550.3-162564.6"
- wire $0\st_done_s_st_done$next[0:0]$8661
- attribute \src "libresoc.v:162485.3-162486.51"
+ attribute \src "libresoc.v:162214.3-162228.6"
+ wire $0\st_done_s_st_done$next[0:0]$8609
+ attribute \src "libresoc.v:162149.3-162150.51"
wire $0\st_done_s_st_done[0:0]
- attribute \src "libresoc.v:162791.3-162800.6"
+ attribute \src "libresoc.v:162455.3-162464.6"
wire width 64 $0\stdata[63:0]
- attribute \src "libresoc.v:162477.3-162478.35"
+ attribute \src "libresoc.v:162141.3-162142.35"
wire $0\sts_dly[0:0]
- attribute \src "libresoc.v:162626.3-162651.6"
+ attribute \src "libresoc.v:162290.3-162315.6"
wire $0\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162678.3-162703.6"
+ attribute \src "libresoc.v:162342.3-162367.6"
wire width 48 $0\x_addr_i[47:0]
- attribute \src "libresoc.v:162652.3-162677.6"
+ attribute \src "libresoc.v:162316.3-162341.6"
wire width 8 $0\x_mask_i[7:0]
- attribute \src "libresoc.v:162801.3-162810.6"
+ attribute \src "libresoc.v:162465.3-162474.6"
wire width 64 $0\x_st_data_i[63:0]
- attribute \src "libresoc.v:162961.3-162976.6"
+ attribute \src "libresoc.v:162625.3-162640.6"
wire $1\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $1\adrok_l_s_addr_acked$next[0:0]$8699
- attribute \src "libresoc.v:162279.7-162279.34"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $1\adrok_l_s_addr_acked$next[0:0]$8647
+ attribute \src "libresoc.v:161943.7-161943.34"
wire $1\adrok_l_s_addr_acked[0:0]
- attribute \src "libresoc.v:162575.3-162583.6"
- wire $1\busy_delay$next[0:0]$8667
- attribute \src "libresoc.v:162283.7-162283.24"
+ attribute \src "libresoc.v:162239.3-162247.6"
+ wire $1\busy_delay$next[0:0]$8615
+ attribute \src "libresoc.v:161947.7-161947.24"
wire $1\busy_delay[0:0]
- attribute \src "libresoc.v:162909.3-162924.6"
+ attribute \src "libresoc.v:162573.3-162588.6"
wire $1\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:162899.3-162908.6"
+ attribute \src "libresoc.v:162563.3-162572.6"
wire $1\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:162889.3-162898.6"
+ attribute \src "libresoc.v:162553.3-162562.6"
wire $1\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:162870.3-162879.6"
+ attribute \src "libresoc.v:162534.3-162543.6"
wire $1\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $1\fsm_state$next[1:0]$8685
- attribute \src "libresoc.v:162305.13-162305.29"
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $1\fsm_state$next[1:0]$8633
+ attribute \src "libresoc.v:161969.13-161969.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:162771.3-162780.6"
+ attribute \src "libresoc.v:162435.3-162444.6"
wire $1\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:162319.7-162319.21"
+ attribute \src "libresoc.v:161983.7-161983.21"
wire $1\lds_dly[0:0]
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162761.3-162770.6"
+ attribute \src "libresoc.v:162425.3-162434.6"
wire width 64 $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:162781.3-162790.6"
+ attribute \src "libresoc.v:162445.3-162454.6"
wire $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:162610.3-162625.6"
+ attribute \src "libresoc.v:162274.3-162289.6"
wire width 4 $1\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:162594.3-162609.6"
+ attribute \src "libresoc.v:162258.3-162273.6"
wire width 4 $1\lenexp_len_i[3:0]
- attribute \src "libresoc.v:162880.3-162888.6"
- wire $1\lsui_active_dly$next[0:0]$8693
- attribute \src "libresoc.v:162362.7-162362.29"
+ attribute \src "libresoc.v:162544.3-162552.6"
+ wire $1\lsui_active_dly$next[0:0]$8641
+ attribute \src "libresoc.v:162026.7-162026.29"
wire $1\lsui_active_dly[0:0]
- attribute \src "libresoc.v:162811.3-162830.6"
+ attribute \src "libresoc.v:162475.3-162494.6"
wire $1\lsui_busy[0:0]
- attribute \src "libresoc.v:162374.7-162374.25"
+ attribute \src "libresoc.v:162038.7-162038.25"
wire $1\reset_delay[0:0]
- attribute \src "libresoc.v:162751.3-162760.6"
+ attribute \src "libresoc.v:162415.3-162424.6"
wire $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:162735.3-162750.6"
+ attribute \src "libresoc.v:162399.3-162414.6"
wire $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:162584.3-162593.6"
+ attribute \src "libresoc.v:162248.3-162257.6"
wire $1\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:162565.3-162574.6"
+ attribute \src "libresoc.v:162229.3-162238.6"
wire $1\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:162550.3-162564.6"
- wire $1\st_done_s_st_done$next[0:0]$8662
- attribute \src "libresoc.v:162394.7-162394.31"
+ attribute \src "libresoc.v:162214.3-162228.6"
+ wire $1\st_done_s_st_done$next[0:0]$8610
+ attribute \src "libresoc.v:162058.7-162058.31"
wire $1\st_done_s_st_done[0:0]
- attribute \src "libresoc.v:162791.3-162800.6"
+ attribute \src "libresoc.v:162455.3-162464.6"
wire width 64 $1\stdata[63:0]
- attribute \src "libresoc.v:162402.7-162402.21"
+ attribute \src "libresoc.v:162066.7-162066.21"
wire $1\sts_dly[0:0]
- attribute \src "libresoc.v:162626.3-162651.6"
+ attribute \src "libresoc.v:162290.3-162315.6"
wire $1\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162678.3-162703.6"
+ attribute \src "libresoc.v:162342.3-162367.6"
wire width 48 $1\x_addr_i[47:0]
- attribute \src "libresoc.v:162652.3-162677.6"
+ attribute \src "libresoc.v:162316.3-162341.6"
wire width 8 $1\x_mask_i[7:0]
- attribute \src "libresoc.v:162801.3-162810.6"
+ attribute \src "libresoc.v:162465.3-162474.6"
wire width 64 $1\x_st_data_i[63:0]
- attribute \src "libresoc.v:162961.3-162976.6"
+ attribute \src "libresoc.v:162625.3-162640.6"
wire $2\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $2\adrok_l_s_addr_acked$next[0:0]$8700
- attribute \src "libresoc.v:162909.3-162924.6"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $2\adrok_l_s_addr_acked$next[0:0]$8648
+ attribute \src "libresoc.v:162573.3-162588.6"
wire $2\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $2\fsm_state$next[1:0]$8686
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $2\fsm_state$next[1:0]$8634
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $2\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162610.3-162625.6"
+ attribute \src "libresoc.v:162274.3-162289.6"
wire width 4 $2\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:162594.3-162609.6"
+ attribute \src "libresoc.v:162258.3-162273.6"
wire width 4 $2\lenexp_len_i[3:0]
- attribute \src "libresoc.v:162811.3-162830.6"
+ attribute \src "libresoc.v:162475.3-162494.6"
wire $2\lsui_busy[0:0]
- attribute \src "libresoc.v:162735.3-162750.6"
+ attribute \src "libresoc.v:162399.3-162414.6"
wire $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:162550.3-162564.6"
- wire $2\st_done_s_st_done$next[0:0]$8663
- attribute \src "libresoc.v:162626.3-162651.6"
+ attribute \src "libresoc.v:162214.3-162228.6"
+ wire $2\st_done_s_st_done$next[0:0]$8611
+ attribute \src "libresoc.v:162290.3-162315.6"
wire $2\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162678.3-162703.6"
+ attribute \src "libresoc.v:162342.3-162367.6"
wire width 48 $2\x_addr_i[47:0]
- attribute \src "libresoc.v:162652.3-162677.6"
+ attribute \src "libresoc.v:162316.3-162341.6"
wire width 8 $2\x_mask_i[7:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $3\adrok_l_s_addr_acked$next[0:0]$8701
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $3\fsm_state$next[1:0]$8687
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $3\adrok_l_s_addr_acked$next[0:0]$8649
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $3\fsm_state$next[1:0]$8635
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $3\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162626.3-162651.6"
+ attribute \src "libresoc.v:162290.3-162315.6"
wire $3\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162678.3-162703.6"
+ attribute \src "libresoc.v:162342.3-162367.6"
wire width 48 $3\x_addr_i[47:0]
- attribute \src "libresoc.v:162652.3-162677.6"
+ attribute \src "libresoc.v:162316.3-162341.6"
wire width 8 $3\x_mask_i[7:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $4\adrok_l_s_addr_acked$next[0:0]$8702
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $4\fsm_state$next[1:0]$8688
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $4\adrok_l_s_addr_acked$next[0:0]$8650
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $4\fsm_state$next[1:0]$8636
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $4\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162626.3-162651.6"
+ attribute \src "libresoc.v:162290.3-162315.6"
wire $4\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162678.3-162703.6"
+ attribute \src "libresoc.v:162342.3-162367.6"
wire width 48 $4\x_addr_i[47:0]
- attribute \src "libresoc.v:162652.3-162677.6"
+ attribute \src "libresoc.v:162316.3-162341.6"
wire width 8 $4\x_mask_i[7:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $5\adrok_l_s_addr_acked$next[0:0]$8703
- attribute \src "libresoc.v:162831.3-162869.6"
- wire width 2 $5\fsm_state$next[1:0]$8689
- attribute \src "libresoc.v:162704.3-162734.6"
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $5\adrok_l_s_addr_acked$next[0:0]$8651
+ attribute \src "libresoc.v:162495.3-162533.6"
+ wire width 2 $5\fsm_state$next[1:0]$8637
+ attribute \src "libresoc.v:162368.3-162398.6"
wire $5\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162925.3-162960.6"
- wire $6\adrok_l_s_addr_acked$next[0:0]$8704
- attribute \src "libresoc.v:162431.18-162431.115"
- wire $and$libresoc.v:162431$8610_Y
- attribute \src "libresoc.v:162433.18-162433.95"
- wire $and$libresoc.v:162433$8612_Y
- attribute \src "libresoc.v:162435.17-162435.138"
- wire $and$libresoc.v:162435$8614_Y
- attribute \src "libresoc.v:162436.18-162436.95"
- wire $and$libresoc.v:162436$8615_Y
- attribute \src "libresoc.v:162439.18-162439.136"
- wire $and$libresoc.v:162439$8620_Y
- attribute \src "libresoc.v:162440.18-162440.136"
- wire $and$libresoc.v:162440$8621_Y
- attribute \src "libresoc.v:162441.18-162441.136"
- wire $and$libresoc.v:162441$8622_Y
- attribute \src "libresoc.v:162442.18-162442.136"
- wire $and$libresoc.v:162442$8623_Y
- attribute \src "libresoc.v:162443.18-162443.136"
- wire $and$libresoc.v:162443$8624_Y
- attribute \src "libresoc.v:162448.18-162448.119"
- wire width 176 $and$libresoc.v:162448$8629_Y
- attribute \src "libresoc.v:162451.18-162451.136"
- wire $and$libresoc.v:162451$8632_Y
- attribute \src "libresoc.v:162452.18-162452.136"
- wire $and$libresoc.v:162452$8633_Y
- attribute \src "libresoc.v:162454.18-162454.139"
- wire $and$libresoc.v:162454$8635_Y
- attribute \src "libresoc.v:162458.18-162458.139"
- wire $and$libresoc.v:162458$8639_Y
- attribute \src "libresoc.v:162460.18-162460.114"
- wire $and$libresoc.v:162460$8641_Y
- attribute \src "libresoc.v:162462.18-162462.114"
- wire $and$libresoc.v:162462$8643_Y
- attribute \src "libresoc.v:162466.18-162466.103"
- wire $and$libresoc.v:162466$8647_Y
- attribute \src "libresoc.v:162467.17-162467.135"
- wire $and$libresoc.v:162467$8648_Y
- attribute \src "libresoc.v:162470.18-162470.103"
- wire $and$libresoc.v:162470$8651_Y
- attribute \src "libresoc.v:162437.18-162437.109"
- wire width 4 $extend$libresoc.v:162437$8616_Y
- attribute \src "libresoc.v:162438.18-162438.109"
- wire width 4 $extend$libresoc.v:162438$8618_Y
- attribute \src "libresoc.v:162449.18-162449.112"
- wire width 8 $mul$libresoc.v:162449$8630_Y
- attribute \src "libresoc.v:162455.18-162455.112"
- wire width 8 $mul$libresoc.v:162455$8636_Y
- attribute \src "libresoc.v:162430.17-162430.103"
- wire $not$libresoc.v:162430$8609_Y
- attribute \src "libresoc.v:162432.18-162432.94"
- wire $not$libresoc.v:162432$8611_Y
- attribute \src "libresoc.v:162434.18-162434.94"
- wire $not$libresoc.v:162434$8613_Y
- attribute \src "libresoc.v:162444.18-162444.102"
- wire $not$libresoc.v:162444$8625_Y
- attribute \src "libresoc.v:162447.18-162447.97"
- wire $not$libresoc.v:162447$8628_Y
- attribute \src "libresoc.v:162453.18-162453.102"
- wire $not$libresoc.v:162453$8634_Y
- attribute \src "libresoc.v:162456.17-162456.103"
- wire $not$libresoc.v:162456$8637_Y
- attribute \src "libresoc.v:162463.18-162463.101"
- wire $not$libresoc.v:162463$8644_Y
- attribute \src "libresoc.v:162464.18-162464.111"
- wire $not$libresoc.v:162464$8645_Y
- attribute \src "libresoc.v:162465.18-162465.110"
- wire $not$libresoc.v:162465$8646_Y
- attribute \src "libresoc.v:162468.18-162468.102"
- wire $not$libresoc.v:162468$8649_Y
- attribute \src "libresoc.v:162469.18-162469.102"
- wire $not$libresoc.v:162469$8650_Y
- attribute \src "libresoc.v:162445.18-162445.111"
- wire $or$libresoc.v:162445$8626_Y
- attribute \src "libresoc.v:162446.17-162446.130"
- wire $or$libresoc.v:162446$8627_Y
- attribute \src "libresoc.v:162459.18-162459.130"
- wire $or$libresoc.v:162459$8640_Y
- attribute \src "libresoc.v:162461.18-162461.130"
- wire $or$libresoc.v:162461$8642_Y
- attribute \src "libresoc.v:162437.18-162437.109"
- wire width 4 $pos$libresoc.v:162437$8617_Y
- attribute \src "libresoc.v:162438.18-162438.109"
- wire width 4 $pos$libresoc.v:162438$8619_Y
- attribute \src "libresoc.v:162457.18-162457.121"
- wire width 319 $sshl$libresoc.v:162457$8638_Y
- attribute \src "libresoc.v:162450.18-162450.106"
- wire width 176 $sshr$libresoc.v:162450$8631_Y
+ attribute \src "libresoc.v:162589.3-162624.6"
+ wire $6\adrok_l_s_addr_acked$next[0:0]$8652
+ attribute \src "libresoc.v:162095.18-162095.115"
+ wire $and$libresoc.v:162095$8558_Y
+ attribute \src "libresoc.v:162097.18-162097.95"
+ wire $and$libresoc.v:162097$8560_Y
+ attribute \src "libresoc.v:162099.17-162099.138"
+ wire $and$libresoc.v:162099$8562_Y
+ attribute \src "libresoc.v:162100.18-162100.95"
+ wire $and$libresoc.v:162100$8563_Y
+ attribute \src "libresoc.v:162103.18-162103.136"
+ wire $and$libresoc.v:162103$8568_Y
+ attribute \src "libresoc.v:162104.18-162104.136"
+ wire $and$libresoc.v:162104$8569_Y
+ attribute \src "libresoc.v:162105.18-162105.136"
+ wire $and$libresoc.v:162105$8570_Y
+ attribute \src "libresoc.v:162106.18-162106.136"
+ wire $and$libresoc.v:162106$8571_Y
+ attribute \src "libresoc.v:162107.18-162107.136"
+ wire $and$libresoc.v:162107$8572_Y
+ attribute \src "libresoc.v:162112.18-162112.119"
+ wire width 176 $and$libresoc.v:162112$8577_Y
+ attribute \src "libresoc.v:162115.18-162115.136"
+ wire $and$libresoc.v:162115$8580_Y
+ attribute \src "libresoc.v:162116.18-162116.136"
+ wire $and$libresoc.v:162116$8581_Y
+ attribute \src "libresoc.v:162118.18-162118.139"
+ wire $and$libresoc.v:162118$8583_Y
+ attribute \src "libresoc.v:162122.18-162122.139"
+ wire $and$libresoc.v:162122$8587_Y
+ attribute \src "libresoc.v:162124.18-162124.114"
+ wire $and$libresoc.v:162124$8589_Y
+ attribute \src "libresoc.v:162126.18-162126.114"
+ wire $and$libresoc.v:162126$8591_Y
+ attribute \src "libresoc.v:162130.18-162130.103"
+ wire $and$libresoc.v:162130$8595_Y
+ attribute \src "libresoc.v:162131.17-162131.135"
+ wire $and$libresoc.v:162131$8596_Y
+ attribute \src "libresoc.v:162134.18-162134.103"
+ wire $and$libresoc.v:162134$8599_Y
+ attribute \src "libresoc.v:162101.18-162101.109"
+ wire width 4 $extend$libresoc.v:162101$8564_Y
+ attribute \src "libresoc.v:162102.18-162102.109"
+ wire width 4 $extend$libresoc.v:162102$8566_Y
+ attribute \src "libresoc.v:162113.18-162113.112"
+ wire width 8 $mul$libresoc.v:162113$8578_Y
+ attribute \src "libresoc.v:162119.18-162119.112"
+ wire width 8 $mul$libresoc.v:162119$8584_Y
+ attribute \src "libresoc.v:162094.17-162094.103"
+ wire $not$libresoc.v:162094$8557_Y
+ attribute \src "libresoc.v:162096.18-162096.94"
+ wire $not$libresoc.v:162096$8559_Y
+ attribute \src "libresoc.v:162098.18-162098.94"
+ wire $not$libresoc.v:162098$8561_Y
+ attribute \src "libresoc.v:162108.18-162108.102"
+ wire $not$libresoc.v:162108$8573_Y
+ attribute \src "libresoc.v:162111.18-162111.97"
+ wire $not$libresoc.v:162111$8576_Y
+ attribute \src "libresoc.v:162117.18-162117.102"
+ wire $not$libresoc.v:162117$8582_Y
+ attribute \src "libresoc.v:162120.17-162120.103"
+ wire $not$libresoc.v:162120$8585_Y
+ attribute \src "libresoc.v:162127.18-162127.101"
+ wire $not$libresoc.v:162127$8592_Y
+ attribute \src "libresoc.v:162128.18-162128.111"
+ wire $not$libresoc.v:162128$8593_Y
+ attribute \src "libresoc.v:162129.18-162129.110"
+ wire $not$libresoc.v:162129$8594_Y
+ attribute \src "libresoc.v:162132.18-162132.102"
+ wire $not$libresoc.v:162132$8597_Y
+ attribute \src "libresoc.v:162133.18-162133.102"
+ wire $not$libresoc.v:162133$8598_Y
+ attribute \src "libresoc.v:162109.18-162109.111"
+ wire $or$libresoc.v:162109$8574_Y
+ attribute \src "libresoc.v:162110.17-162110.130"
+ wire $or$libresoc.v:162110$8575_Y
+ attribute \src "libresoc.v:162123.18-162123.130"
+ wire $or$libresoc.v:162123$8588_Y
+ attribute \src "libresoc.v:162125.18-162125.130"
+ wire $or$libresoc.v:162125$8590_Y
+ attribute \src "libresoc.v:162101.18-162101.109"
+ wire width 4 $pos$libresoc.v:162101$8565_Y
+ attribute \src "libresoc.v:162102.18-162102.109"
+ wire width 4 $pos$libresoc.v:162102$8567_Y
+ attribute \src "libresoc.v:162121.18-162121.121"
+ wire width 319 $sshl$libresoc.v:162121$8586_Y
+ attribute \src "libresoc.v:162114.18-162114.106"
+ wire width 176 $sshr$libresoc.v:162114$8579_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
wire \busy_l_r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \busy_l_s_busy
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \cyc_l_q_cyc
wire width 2 \fsm_state
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85"
wire width 2 \fsm_state$next
- attribute \src "libresoc.v:162185.7-162185.15"
+ attribute \src "libresoc.v:161849.7-161849.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \ld_active_q_ld_active
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57"
wire output 22 \x_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
- cell $and $and$libresoc.v:162431$8610
+ cell $and $and$libresoc.v:162095$8558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
connect \B \$9
- connect \Y $and$libresoc.v:162431$8610_Y
+ connect \Y $and$libresoc.v:162095$8558_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:162433$8612
+ cell $and $and$libresoc.v:162097$8560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lds
connect \B \$13
- connect \Y $and$libresoc.v:162433$8612_Y
+ connect \Y $and$libresoc.v:162097$8560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:162435$8614
+ cell $and $and$libresoc.v:162099$8562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:162435$8614_Y
+ connect \Y $and$libresoc.v:162099$8562_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:162436$8615
+ cell $and $and$libresoc.v:162100$8563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sts
connect \B \$17
- connect \Y $and$libresoc.v:162436$8615_Y
+ connect \Y $and$libresoc.v:162100$8563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:162439$8620
+ cell $and $and$libresoc.v:162103$8568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:162439$8620_Y
+ connect \Y $and$libresoc.v:162103$8568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:162440$8621
+ cell $and $and$libresoc.v:162104$8569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:162440$8621_Y
+ connect \Y $and$libresoc.v:162104$8569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:162441$8622
+ cell $and $and$libresoc.v:162105$8570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:162441$8622_Y
+ connect \Y $and$libresoc.v:162105$8570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:162442$8623
+ cell $and $and$libresoc.v:162106$8571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:162442$8623_Y
+ connect \Y $and$libresoc.v:162106$8571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:162443$8624
+ cell $and $and$libresoc.v:162107$8572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:162443$8624_Y
+ connect \Y $and$libresoc.v:162107$8572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
- cell $and $and$libresoc.v:162448$8629
+ cell $and $and$libresoc.v:162112$8577
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 176
connect \A \m_ld_data_o
connect \B \lenexp_rexp_o
- connect \Y $and$libresoc.v:162448$8629_Y
+ connect \Y $and$libresoc.v:162112$8577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:162451$8632
+ cell $and $and$libresoc.v:162115$8580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:162451$8632_Y
+ connect \Y $and$libresoc.v:162115$8580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:162452$8633
+ cell $and $and$libresoc.v:162116$8581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:162452$8633_Y
+ connect \Y $and$libresoc.v:162116$8581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:162454$8635
+ cell $and $and$libresoc.v:162118$8583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:162454$8635_Y
+ connect \Y $and$libresoc.v:162118$8583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:162458$8639
+ cell $and $and$libresoc.v:162122$8587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:162458$8639_Y
+ connect \Y $and$libresoc.v:162122$8587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $and $and$libresoc.v:162460$8641
+ cell $and $and$libresoc.v:162124$8589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$63
connect \B \valid_l_q_valid
- connect \Y $and$libresoc.v:162460$8641_Y
+ connect \Y $and$libresoc.v:162124$8589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $and $and$libresoc.v:162462$8643
+ cell $and $and$libresoc.v:162126$8591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$67
connect \B \valid_l_q_valid
- connect \Y $and$libresoc.v:162462$8643_Y
+ connect \Y $and$libresoc.v:162126$8591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $and $and$libresoc.v:162466$8647
+ cell $and $and$libresoc.v:162130$8595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \$75
- connect \Y $and$libresoc.v:162466$8647_Y
+ connect \Y $and$libresoc.v:162130$8595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:162467$8648
+ cell $and $and$libresoc.v:162131$8596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:162467$8648_Y
+ connect \Y $and$libresoc.v:162131$8596_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:162470$8651
+ cell $and $and$libresoc.v:162134$8599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lsui_active
connect \B \$81
- connect \Y $and$libresoc.v:162470$8651_Y
+ connect \Y $and$libresoc.v:162134$8599_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:162437$8616
+ cell $pos $extend$libresoc.v:162101$8564
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 4
connect \A \ldst_port0_addr_i [2:0]
- connect \Y $extend$libresoc.v:162437$8616_Y
+ connect \Y $extend$libresoc.v:162101$8564_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:162438$8618
+ cell $pos $extend$libresoc.v:162102$8566
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 4
connect \A \ldst_port0_addr_i [2:0]
- connect \Y $extend$libresoc.v:162438$8618_Y
+ connect \Y $extend$libresoc.v:162102$8566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258"
- cell $mul $mul$libresoc.v:162449$8630
+ cell $mul $mul$libresoc.v:162113$8578
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \lenexp_addr_i
connect \B 4'1000
- connect \Y $mul$libresoc.v:162449$8630_Y
+ connect \Y $mul$libresoc.v:162113$8578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
- cell $mul $mul$libresoc.v:162455$8636
+ cell $mul $mul$libresoc.v:162119$8584
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \lenexp_addr_i
connect \B 4'1000
- connect \Y $mul$libresoc.v:162455$8636_Y
+ connect \Y $mul$libresoc.v:162119$8584_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
- cell $not $not$libresoc.v:162430$8609
+ cell $not $not$libresoc.v:162094$8557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_delay
- connect \Y $not$libresoc.v:162430$8609_Y
+ connect \Y $not$libresoc.v:162094$8557_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:162432$8611
+ cell $not $not$libresoc.v:162096$8559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lds_dly
- connect \Y $not$libresoc.v:162432$8611_Y
+ connect \Y $not$libresoc.v:162096$8559_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:162434$8613
+ cell $not $not$libresoc.v:162098$8561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sts_dly
- connect \Y $not$libresoc.v:162434$8613_Y
+ connect \Y $not$libresoc.v:162098$8561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64"
- cell $not $not$libresoc.v:162444$8625
+ cell $not $not$libresoc.v:162108$8573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_busy
- connect \Y $not$libresoc.v:162444$8625_Y
+ connect \Y $not$libresoc.v:162108$8573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
- cell $not $not$libresoc.v:162447$8628
+ cell $not $not$libresoc.v:162111$8576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$38
- connect \Y $not$libresoc.v:162447$8628_Y
+ connect \Y $not$libresoc.v:162111$8576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64"
- cell $not $not$libresoc.v:162453$8634
+ cell $not $not$libresoc.v:162117$8582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_busy
- connect \Y $not$libresoc.v:162453$8634_Y
+ connect \Y $not$libresoc.v:162117$8582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
- cell $not $not$libresoc.v:162456$8637
+ cell $not $not$libresoc.v:162120$8585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_delay
- connect \Y $not$libresoc.v:162456$8637_Y
+ connect \Y $not$libresoc.v:162120$8585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
- cell $not $not$libresoc.v:162463$8644
+ cell $not $not$libresoc.v:162127$8592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_busy_o
- connect \Y $not$libresoc.v:162463$8644_Y
+ connect \Y $not$libresoc.v:162127$8592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $not $not$libresoc.v:162464$8645
+ cell $not $not$libresoc.v:162128$8593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_st_i
- connect \Y $not$libresoc.v:162464$8645_Y
+ connect \Y $not$libresoc.v:162128$8593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $not $not$libresoc.v:162465$8646
+ cell $not $not$libresoc.v:162129$8594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:162465$8646_Y
+ connect \Y $not$libresoc.v:162129$8594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108"
- cell $not $not$libresoc.v:162468$8649
+ cell $not $not$libresoc.v:162132$8597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_busy_o
- connect \Y $not$libresoc.v:162468$8649_Y
+ connect \Y $not$libresoc.v:162132$8597_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:162469$8650
+ cell $not $not$libresoc.v:162133$8598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_active_dly
- connect \Y $not$libresoc.v:162469$8650_Y
+ connect \Y $not$libresoc.v:162133$8598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
- cell $or $or$libresoc.v:162445$8626
+ cell $or $or$libresoc.v:162109$8574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_busy_o
connect \B \lsui_busy
- connect \Y $or$libresoc.v:162445$8626_Y
+ connect \Y $or$libresoc.v:162109$8574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223"
- cell $or $or$libresoc.v:162446$8627
+ cell $or $or$libresoc.v:162110$8575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:162446$8627_Y
+ connect \Y $or$libresoc.v:162110$8575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $or $or$libresoc.v:162459$8640
+ cell $or $or$libresoc.v:162123$8588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:162459$8640_Y
+ connect \Y $or$libresoc.v:162123$8588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $or $or$libresoc.v:162461$8642
+ cell $or $or$libresoc.v:162125$8590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:162461$8642_Y
+ connect \Y $or$libresoc.v:162125$8590_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:162437$8617
+ cell $pos $pos$libresoc.v:162101$8565
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $extend$libresoc.v:162437$8616_Y
- connect \Y $pos$libresoc.v:162437$8617_Y
+ connect \A $extend$libresoc.v:162101$8564_Y
+ connect \Y $pos$libresoc.v:162101$8565_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:162438$8619
+ cell $pos $pos$libresoc.v:162102$8567
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $extend$libresoc.v:162438$8618_Y
- connect \Y $pos$libresoc.v:162438$8619_Y
+ connect \A $extend$libresoc.v:162102$8566_Y
+ connect \Y $pos$libresoc.v:162102$8567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
- cell $sshl $sshl$libresoc.v:162457$8638
+ cell $sshl $sshl$libresoc.v:162121$8586
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 319
connect \A \ldst_port0_st_data_i
connect \B \$57
- connect \Y $sshl$libresoc.v:162457$8638_Y
+ connect \Y $sshl$libresoc.v:162121$8586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258"
- cell $sshr $sshr$libresoc.v:162450$8631
+ cell $sshr $sshr$libresoc.v:162114$8579
parameter \A_SIGNED 0
parameter \A_WIDTH 176
parameter \B_SIGNED 0
parameter \Y_WIDTH 176
connect \A \$42
connect \B \$44
- connect \Y $sshr$libresoc.v:162450$8631_Y
+ connect \Y $sshr$libresoc.v:162114$8579_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162487.11-162494.4"
+ attribute \src "libresoc.v:162151.11-162158.4"
cell \adrok_l \adrok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_addr_acked \adrok_l_s_addr_acked
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162495.10-162501.4"
+ attribute \src "libresoc.v:162159.10-162165.4"
cell \busy_l \busy_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_busy \busy_l_s_busy
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162502.9-162508.4"
+ attribute \src "libresoc.v:162166.9-162172.4"
cell \cyc_l \cyc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_cyc \cyc_l_s_cyc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162509.13-162515.4"
+ attribute \src "libresoc.v:162173.13-162179.4"
cell \ld_active \ld_active
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_ld_active \ld_active_s_ld_active
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162516.10-162521.4"
+ attribute \src "libresoc.v:162180.10-162185.4"
cell \lenexp \lenexp
connect \addr_i \lenexp_addr_i
connect \len_i \lenexp_len_i
connect \rexp_o \lenexp_rexp_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162522.11-162528.4"
+ attribute \src "libresoc.v:162186.11-162192.4"
cell \reset_l \reset_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_reset \reset_l_s_reset
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162529.13-162535.4"
+ attribute \src "libresoc.v:162193.13-162199.4"
cell \st_active \st_active
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_st_active \st_active_s_st_active
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162536.11-162542.4"
+ attribute \src "libresoc.v:162200.11-162206.4"
cell \st_done \st_done
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_st_done \st_done_s_st_done
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162543.11-162549.4"
+ attribute \src "libresoc.v:162207.11-162213.4"
cell \valid_l \valid_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_valid \valid_l_r_valid
connect \s_valid \valid_l_s_valid
end
- attribute \src "libresoc.v:162185.7-162185.20"
- process $proc$libresoc.v:162185$8706
+ attribute \src "libresoc.v:161849.7-161849.20"
+ process $proc$libresoc.v:161849$8654
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:162279.7-162279.34"
- process $proc$libresoc.v:162279$8707
+ attribute \src "libresoc.v:161943.7-161943.34"
+ process $proc$libresoc.v:161943$8655
assign { } { }
assign $1\adrok_l_s_addr_acked[0:0] 1'0
sync always
sync init
update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0]
end
- attribute \src "libresoc.v:162283.7-162283.24"
- process $proc$libresoc.v:162283$8708
+ attribute \src "libresoc.v:161947.7-161947.24"
+ process $proc$libresoc.v:161947$8656
assign { } { }
assign $1\busy_delay[0:0] 1'0
sync always
sync init
update \busy_delay $1\busy_delay[0:0]
end
- attribute \src "libresoc.v:162305.13-162305.29"
- process $proc$libresoc.v:162305$8709
+ attribute \src "libresoc.v:161969.13-161969.29"
+ process $proc$libresoc.v:161969$8657
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:162319.7-162319.21"
- process $proc$libresoc.v:162319$8710
+ attribute \src "libresoc.v:161983.7-161983.21"
+ process $proc$libresoc.v:161983$8658
assign { } { }
assign $1\lds_dly[0:0] 1'0
sync always
sync init
update \lds_dly $1\lds_dly[0:0]
end
- attribute \src "libresoc.v:162362.7-162362.29"
- process $proc$libresoc.v:162362$8711
+ attribute \src "libresoc.v:162026.7-162026.29"
+ process $proc$libresoc.v:162026$8659
assign { } { }
assign $1\lsui_active_dly[0:0] 1'0
sync always
sync init
update \lsui_active_dly $1\lsui_active_dly[0:0]
end
- attribute \src "libresoc.v:162374.7-162374.25"
- process $proc$libresoc.v:162374$8712
+ attribute \src "libresoc.v:162038.7-162038.25"
+ process $proc$libresoc.v:162038$8660
assign { } { }
assign $1\reset_delay[0:0] 1'0
sync always
sync init
update \reset_delay $1\reset_delay[0:0]
end
- attribute \src "libresoc.v:162394.7-162394.31"
- process $proc$libresoc.v:162394$8713
+ attribute \src "libresoc.v:162058.7-162058.31"
+ process $proc$libresoc.v:162058$8661
assign { } { }
assign $1\st_done_s_st_done[0:0] 1'0
sync always
sync init
update \st_done_s_st_done $1\st_done_s_st_done[0:0]
end
- attribute \src "libresoc.v:162402.7-162402.21"
- process $proc$libresoc.v:162402$8714
+ attribute \src "libresoc.v:162066.7-162066.21"
+ process $proc$libresoc.v:162066$8662
assign { } { }
assign $1\sts_dly[0:0] 1'0
sync always
sync init
update \sts_dly $1\sts_dly[0:0]
end
- attribute \src "libresoc.v:162471.3-162472.47"
- process $proc$libresoc.v:162471$8652
+ attribute \src "libresoc.v:162135.3-162136.47"
+ process $proc$libresoc.v:162135$8600
assign { } { }
assign $0\lsui_active_dly[0:0] \lsui_active_dly$next
sync posedge \coresync_clk
update \lsui_active_dly $0\lsui_active_dly[0:0]
end
- attribute \src "libresoc.v:162473.3-162474.35"
- process $proc$libresoc.v:162473$8653
+ attribute \src "libresoc.v:162137.3-162138.35"
+ process $proc$libresoc.v:162137$8601
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \coresync_clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:162475.3-162476.36"
- process $proc$libresoc.v:162475$8654
+ attribute \src "libresoc.v:162139.3-162140.36"
+ process $proc$libresoc.v:162139$8602
assign { } { }
assign $0\reset_delay[0:0] \reset_l_q_reset
sync posedge \coresync_clk
update \reset_delay $0\reset_delay[0:0]
end
- attribute \src "libresoc.v:162477.3-162478.35"
- process $proc$libresoc.v:162477$8655
+ attribute \src "libresoc.v:162141.3-162142.35"
+ process $proc$libresoc.v:162141$8603
assign { } { }
assign $0\sts_dly[0:0] \ldst_port0_is_st_i
sync posedge \coresync_clk
update \sts_dly $0\sts_dly[0:0]
end
- attribute \src "libresoc.v:162479.3-162480.35"
- process $proc$libresoc.v:162479$8656
+ attribute \src "libresoc.v:162143.3-162144.35"
+ process $proc$libresoc.v:162143$8604
assign { } { }
assign $0\lds_dly[0:0] \ldst_port0_is_ld_i
sync posedge \coresync_clk
update \lds_dly $0\lds_dly[0:0]
end
- attribute \src "libresoc.v:162481.3-162482.37"
- process $proc$libresoc.v:162481$8657
+ attribute \src "libresoc.v:162145.3-162146.37"
+ process $proc$libresoc.v:162145$8605
assign { } { }
assign $0\busy_delay[0:0] \busy_delay$next
sync posedge \coresync_clk
update \busy_delay $0\busy_delay[0:0]
end
- attribute \src "libresoc.v:162483.3-162484.57"
- process $proc$libresoc.v:162483$8658
+ attribute \src "libresoc.v:162147.3-162148.57"
+ process $proc$libresoc.v:162147$8606
assign { } { }
assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next
sync posedge \coresync_clk
update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0]
end
- attribute \src "libresoc.v:162485.3-162486.51"
- process $proc$libresoc.v:162485$8659
+ attribute \src "libresoc.v:162149.3-162150.51"
+ process $proc$libresoc.v:162149$8607
assign { } { }
assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next
sync posedge \coresync_clk
update \st_done_s_st_done $0\st_done_s_st_done[0:0]
end
- attribute \src "libresoc.v:162550.3-162564.6"
- process $proc$libresoc.v:162550$8660
+ attribute \src "libresoc.v:162214.3-162228.6"
+ process $proc$libresoc.v:162214$8608
assign { } { }
assign { } { }
assign { } { }
- assign $0\st_done_s_st_done$next[0:0]$8661 $2\st_done_s_st_done$next[0:0]$8663
- attribute \src "libresoc.v:162551.5-162551.29"
+ assign $0\st_done_s_st_done$next[0:0]$8609 $2\st_done_s_st_done$next[0:0]$8611
+ attribute \src "libresoc.v:162215.5-162215.29"
switch \initial
- attribute \src "libresoc.v:162551.9-162551.17"
+ attribute \src "libresoc.v:162215.9-162215.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\st_done_s_st_done$next[0:0]$8662 1'1
+ assign $1\st_done_s_st_done$next[0:0]$8610 1'1
case
- assign $1\st_done_s_st_done$next[0:0]$8662 1'0
+ assign $1\st_done_s_st_done$next[0:0]$8610 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\st_done_s_st_done$next[0:0]$8663 1'0
+ assign $2\st_done_s_st_done$next[0:0]$8611 1'0
case
- assign $2\st_done_s_st_done$next[0:0]$8663 $1\st_done_s_st_done$next[0:0]$8662
+ assign $2\st_done_s_st_done$next[0:0]$8611 $1\st_done_s_st_done$next[0:0]$8610
end
sync always
- update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8661
+ update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8609
end
- attribute \src "libresoc.v:162565.3-162574.6"
- process $proc$libresoc.v:162565$8664
+ attribute \src "libresoc.v:162229.3-162238.6"
+ process $proc$libresoc.v:162229$8612
assign { } { }
assign { } { }
assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:162566.5-162566.29"
+ attribute \src "libresoc.v:162230.5-162230.29"
switch \initial
- attribute \src "libresoc.v:162566.9-162566.17"
+ attribute \src "libresoc.v:162230.9-162230.17"
case 1'1
case
end
sync always
update \st_done_r_st_done $0\st_done_r_st_done[0:0]
end
- attribute \src "libresoc.v:162575.3-162583.6"
- process $proc$libresoc.v:162575$8665
+ attribute \src "libresoc.v:162239.3-162247.6"
+ process $proc$libresoc.v:162239$8613
assign { } { }
assign { } { }
- assign $0\busy_delay$next[0:0]$8666 $1\busy_delay$next[0:0]$8667
- attribute \src "libresoc.v:162576.5-162576.29"
+ assign $0\busy_delay$next[0:0]$8614 $1\busy_delay$next[0:0]$8615
+ attribute \src "libresoc.v:162240.5-162240.29"
switch \initial
- attribute \src "libresoc.v:162576.9-162576.17"
+ attribute \src "libresoc.v:162240.9-162240.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\busy_delay$next[0:0]$8667 1'0
+ assign $1\busy_delay$next[0:0]$8615 1'0
case
- assign $1\busy_delay$next[0:0]$8667 \ldst_port0_busy_o
+ assign $1\busy_delay$next[0:0]$8615 \ldst_port0_busy_o
end
sync always
- update \busy_delay$next $0\busy_delay$next[0:0]$8666
+ update \busy_delay$next $0\busy_delay$next[0:0]$8614
end
- attribute \src "libresoc.v:162584.3-162593.6"
- process $proc$libresoc.v:162584$8668
+ attribute \src "libresoc.v:162248.3-162257.6"
+ process $proc$libresoc.v:162248$8616
assign { } { }
assign { } { }
assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:162585.5-162585.29"
+ attribute \src "libresoc.v:162249.5-162249.29"
switch \initial
- attribute \src "libresoc.v:162585.9-162585.17"
+ attribute \src "libresoc.v:162249.9-162249.17"
case 1'1
case
end
sync always
update \st_active_r_st_active $0\st_active_r_st_active[0:0]
end
- attribute \src "libresoc.v:162594.3-162609.6"
- process $proc$libresoc.v:162594$8669
+ attribute \src "libresoc.v:162258.3-162273.6"
+ process $proc$libresoc.v:162258$8617
assign { } { }
assign { } { }
assign { } { }
assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0]
- attribute \src "libresoc.v:162595.5-162595.29"
+ attribute \src "libresoc.v:162259.5-162259.29"
switch \initial
- attribute \src "libresoc.v:162595.9-162595.17"
+ attribute \src "libresoc.v:162259.9-162259.17"
case 1'1
case
end
sync always
update \lenexp_len_i $0\lenexp_len_i[3:0]
end
- attribute \src "libresoc.v:162610.3-162625.6"
- process $proc$libresoc.v:162610$8670
+ attribute \src "libresoc.v:162274.3-162289.6"
+ process $proc$libresoc.v:162274$8618
assign { } { }
assign { } { }
assign { } { }
assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:162611.5-162611.29"
+ attribute \src "libresoc.v:162275.5-162275.29"
switch \initial
- attribute \src "libresoc.v:162611.9-162611.17"
+ attribute \src "libresoc.v:162275.9-162275.17"
case 1'1
case
end
sync always
update \lenexp_addr_i $0\lenexp_addr_i[3:0]
end
- attribute \src "libresoc.v:162626.3-162651.6"
- process $proc$libresoc.v:162626$8671
+ attribute \src "libresoc.v:162290.3-162315.6"
+ process $proc$libresoc.v:162290$8619
assign { } { }
assign { } { }
assign { } { }
assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:162627.5-162627.29"
+ attribute \src "libresoc.v:162291.5-162291.29"
switch \initial
- attribute \src "libresoc.v:162627.9-162627.17"
+ attribute \src "libresoc.v:162291.9-162291.17"
case 1'1
case
end
sync always
update \valid_l_s_valid $0\valid_l_s_valid[0:0]
end
- attribute \src "libresoc.v:162652.3-162677.6"
- process $proc$libresoc.v:162652$8672
+ attribute \src "libresoc.v:162316.3-162341.6"
+ process $proc$libresoc.v:162316$8620
assign { } { }
assign { } { }
assign { } { }
assign $0\x_mask_i[7:0] $3\x_mask_i[7:0]
- attribute \src "libresoc.v:162653.5-162653.29"
+ attribute \src "libresoc.v:162317.5-162317.29"
switch \initial
- attribute \src "libresoc.v:162653.9-162653.17"
+ attribute \src "libresoc.v:162317.9-162317.17"
case 1'1
case
end
sync always
update \x_mask_i $0\x_mask_i[7:0]
end
- attribute \src "libresoc.v:162678.3-162703.6"
- process $proc$libresoc.v:162678$8673
+ attribute \src "libresoc.v:162342.3-162367.6"
+ process $proc$libresoc.v:162342$8621
assign { } { }
assign { } { }
assign { } { }
assign $0\x_addr_i[47:0] $3\x_addr_i[47:0]
- attribute \src "libresoc.v:162679.5-162679.29"
+ attribute \src "libresoc.v:162343.5-162343.29"
switch \initial
- attribute \src "libresoc.v:162679.9-162679.17"
+ attribute \src "libresoc.v:162343.9-162343.17"
case 1'1
case
end
sync always
update \x_addr_i $0\x_addr_i[47:0]
end
- attribute \src "libresoc.v:162704.3-162734.6"
- process $proc$libresoc.v:162704$8674
+ attribute \src "libresoc.v:162368.3-162398.6"
+ process $proc$libresoc.v:162368$8622
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:162705.5-162705.29"
+ attribute \src "libresoc.v:162369.5-162369.29"
switch \initial
- attribute \src "libresoc.v:162705.9-162705.17"
+ attribute \src "libresoc.v:162369.9-162369.17"
case 1'1
case
end
sync always
update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0]
end
- attribute \src "libresoc.v:162735.3-162750.6"
- process $proc$libresoc.v:162735$8675
+ attribute \src "libresoc.v:162399.3-162414.6"
+ process $proc$libresoc.v:162399$8623
assign { } { }
assign { } { }
assign { } { }
assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:162736.5-162736.29"
+ attribute \src "libresoc.v:162400.5-162400.29"
switch \initial
- attribute \src "libresoc.v:162736.9-162736.17"
+ attribute \src "libresoc.v:162400.9-162400.17"
case 1'1
case
end
sync always
update \reset_l_s_reset $0\reset_l_s_reset[0:0]
end
- attribute \src "libresoc.v:162751.3-162760.6"
- process $proc$libresoc.v:162751$8676
+ attribute \src "libresoc.v:162415.3-162424.6"
+ process $proc$libresoc.v:162415$8624
assign { } { }
assign { } { }
assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:162752.5-162752.29"
+ attribute \src "libresoc.v:162416.5-162416.29"
switch \initial
- attribute \src "libresoc.v:162752.9-162752.17"
+ attribute \src "libresoc.v:162416.9-162416.17"
case 1'1
case
end
sync always
update \reset_l_r_reset $0\reset_l_r_reset[0:0]
end
- attribute \src "libresoc.v:162761.3-162770.6"
- process $proc$libresoc.v:162761$8677
+ attribute \src "libresoc.v:162425.3-162434.6"
+ process $proc$libresoc.v:162425$8625
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:162762.5-162762.29"
+ attribute \src "libresoc.v:162426.5-162426.29"
switch \initial
- attribute \src "libresoc.v:162762.9-162762.17"
+ attribute \src "libresoc.v:162426.9-162426.17"
case 1'1
case
end
sync always
update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0]
end
- attribute \src "libresoc.v:162771.3-162780.6"
- process $proc$libresoc.v:162771$8678
+ attribute \src "libresoc.v:162435.3-162444.6"
+ process $proc$libresoc.v:162435$8626
assign { } { }
assign { } { }
assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:162772.5-162772.29"
+ attribute \src "libresoc.v:162436.5-162436.29"
switch \initial
- attribute \src "libresoc.v:162772.9-162772.17"
+ attribute \src "libresoc.v:162436.9-162436.17"
case 1'1
case
end
sync always
update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0]
end
- attribute \src "libresoc.v:162781.3-162790.6"
- process $proc$libresoc.v:162781$8679
+ attribute \src "libresoc.v:162445.3-162454.6"
+ process $proc$libresoc.v:162445$8627
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:162782.5-162782.29"
+ attribute \src "libresoc.v:162446.5-162446.29"
switch \initial
- attribute \src "libresoc.v:162782.9-162782.17"
+ attribute \src "libresoc.v:162446.9-162446.17"
case 1'1
case
end
sync always
update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0]
end
- attribute \src "libresoc.v:162791.3-162800.6"
- process $proc$libresoc.v:162791$8680
+ attribute \src "libresoc.v:162455.3-162464.6"
+ process $proc$libresoc.v:162455$8628
assign { } { }
assign { } { }
assign $0\stdata[63:0] $1\stdata[63:0]
- attribute \src "libresoc.v:162792.5-162792.29"
+ attribute \src "libresoc.v:162456.5-162456.29"
switch \initial
- attribute \src "libresoc.v:162792.9-162792.17"
+ attribute \src "libresoc.v:162456.9-162456.17"
case 1'1
case
end
sync always
update \stdata $0\stdata[63:0]
end
- attribute \src "libresoc.v:162801.3-162810.6"
- process $proc$libresoc.v:162801$8681
+ attribute \src "libresoc.v:162465.3-162474.6"
+ process $proc$libresoc.v:162465$8629
assign { } { }
assign { } { }
assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0]
- attribute \src "libresoc.v:162802.5-162802.29"
+ attribute \src "libresoc.v:162466.5-162466.29"
switch \initial
- attribute \src "libresoc.v:162802.9-162802.17"
+ attribute \src "libresoc.v:162466.9-162466.17"
case 1'1
case
end
sync always
update \x_st_data_i $0\x_st_data_i[63:0]
end
- attribute \src "libresoc.v:162811.3-162830.6"
- process $proc$libresoc.v:162811$8682
+ attribute \src "libresoc.v:162475.3-162494.6"
+ process $proc$libresoc.v:162475$8630
assign { } { }
assign { } { }
assign $0\lsui_busy[0:0] $1\lsui_busy[0:0]
- attribute \src "libresoc.v:162812.5-162812.29"
+ attribute \src "libresoc.v:162476.5-162476.29"
switch \initial
- attribute \src "libresoc.v:162812.9-162812.17"
+ attribute \src "libresoc.v:162476.9-162476.17"
case 1'1
case
end
sync always
update \lsui_busy $0\lsui_busy[0:0]
end
- attribute \src "libresoc.v:162831.3-162869.6"
- process $proc$libresoc.v:162831$8683
+ attribute \src "libresoc.v:162495.3-162533.6"
+ process $proc$libresoc.v:162495$8631
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$8684 $5\fsm_state$next[1:0]$8689
- attribute \src "libresoc.v:162832.5-162832.29"
+ assign $0\fsm_state$next[1:0]$8632 $5\fsm_state$next[1:0]$8637
+ attribute \src "libresoc.v:162496.5-162496.29"
switch \initial
- attribute \src "libresoc.v:162832.9-162832.17"
+ attribute \src "libresoc.v:162496.9-162496.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$8685 $2\fsm_state$next[1:0]$8686
+ assign $1\fsm_state$next[1:0]$8633 $2\fsm_state$next[1:0]$8634
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
switch \$69
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$8686 2'01
+ assign $2\fsm_state$next[1:0]$8634 2'01
case
- assign $2\fsm_state$next[1:0]$8686 \fsm_state
+ assign $2\fsm_state$next[1:0]$8634 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$8685 $3\fsm_state$next[1:0]$8687
+ assign $1\fsm_state$next[1:0]$8633 $3\fsm_state$next[1:0]$8635
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
switch \$71
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$next[1:0]$8687 2'10
+ assign $3\fsm_state$next[1:0]$8635 2'10
case
- assign $3\fsm_state$next[1:0]$8687 \fsm_state
+ assign $3\fsm_state$next[1:0]$8635 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$8685 $4\fsm_state$next[1:0]$8688
+ assign $1\fsm_state$next[1:0]$8633 $4\fsm_state$next[1:0]$8636
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
switch \$77
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[1:0]$8688 2'00
+ assign $4\fsm_state$next[1:0]$8636 2'00
case
- assign $4\fsm_state$next[1:0]$8688 \fsm_state
+ assign $4\fsm_state$next[1:0]$8636 \fsm_state
end
case
- assign $1\fsm_state$next[1:0]$8685 \fsm_state
+ assign $1\fsm_state$next[1:0]$8633 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[1:0]$8689 2'00
+ assign $5\fsm_state$next[1:0]$8637 2'00
case
- assign $5\fsm_state$next[1:0]$8689 $1\fsm_state$next[1:0]$8685
+ assign $5\fsm_state$next[1:0]$8637 $1\fsm_state$next[1:0]$8633
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$8684
+ update \fsm_state$next $0\fsm_state$next[1:0]$8632
end
- attribute \src "libresoc.v:162870.3-162879.6"
- process $proc$libresoc.v:162870$8690
+ attribute \src "libresoc.v:162534.3-162543.6"
+ process $proc$libresoc.v:162534$8638
assign { } { }
assign { } { }
assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:162871.5-162871.29"
+ attribute \src "libresoc.v:162535.5-162535.29"
switch \initial
- attribute \src "libresoc.v:162871.9-162871.17"
+ attribute \src "libresoc.v:162535.9-162535.17"
case 1'1
case
end
sync always
update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0]
end
- attribute \src "libresoc.v:162880.3-162888.6"
- process $proc$libresoc.v:162880$8691
+ attribute \src "libresoc.v:162544.3-162552.6"
+ process $proc$libresoc.v:162544$8639
assign { } { }
assign { } { }
- assign $0\lsui_active_dly$next[0:0]$8692 $1\lsui_active_dly$next[0:0]$8693
- attribute \src "libresoc.v:162881.5-162881.29"
+ assign $0\lsui_active_dly$next[0:0]$8640 $1\lsui_active_dly$next[0:0]$8641
+ attribute \src "libresoc.v:162545.5-162545.29"
switch \initial
- attribute \src "libresoc.v:162881.9-162881.17"
+ attribute \src "libresoc.v:162545.9-162545.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\lsui_active_dly$next[0:0]$8693 1'0
+ assign $1\lsui_active_dly$next[0:0]$8641 1'0
case
- assign $1\lsui_active_dly$next[0:0]$8693 \lsui_active
+ assign $1\lsui_active_dly$next[0:0]$8641 \lsui_active
end
sync always
- update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8692
+ update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8640
end
- attribute \src "libresoc.v:162889.3-162898.6"
- process $proc$libresoc.v:162889$8694
+ attribute \src "libresoc.v:162553.3-162562.6"
+ process $proc$libresoc.v:162553$8642
assign { } { }
assign { } { }
assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:162890.5-162890.29"
+ attribute \src "libresoc.v:162554.5-162554.29"
switch \initial
- attribute \src "libresoc.v:162890.9-162890.17"
+ attribute \src "libresoc.v:162554.9-162554.17"
case 1'1
case
end
sync always
update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0]
end
- attribute \src "libresoc.v:162899.3-162908.6"
- process $proc$libresoc.v:162899$8695
+ attribute \src "libresoc.v:162563.3-162572.6"
+ process $proc$libresoc.v:162563$8643
assign { } { }
assign { } { }
assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:162900.5-162900.29"
+ attribute \src "libresoc.v:162564.5-162564.29"
switch \initial
- attribute \src "libresoc.v:162900.9-162900.17"
+ attribute \src "libresoc.v:162564.9-162564.17"
case 1'1
case
end
sync always
update \busy_l_s_busy $0\busy_l_s_busy[0:0]
end
- attribute \src "libresoc.v:162909.3-162924.6"
- process $proc$libresoc.v:162909$8696
+ attribute \src "libresoc.v:162573.3-162588.6"
+ process $proc$libresoc.v:162573$8644
assign { } { }
assign { } { }
assign { } { }
assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:162910.5-162910.29"
+ attribute \src "libresoc.v:162574.5-162574.29"
switch \initial
- attribute \src "libresoc.v:162910.9-162910.17"
+ attribute \src "libresoc.v:162574.9-162574.17"
case 1'1
case
end
sync always
update \busy_l_r_busy $0\busy_l_r_busy[0:0]
end
- attribute \src "libresoc.v:162925.3-162960.6"
- process $proc$libresoc.v:162925$8697
+ attribute \src "libresoc.v:162589.3-162624.6"
+ process $proc$libresoc.v:162589$8645
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\adrok_l_s_addr_acked$next[0:0]$8698 $6\adrok_l_s_addr_acked$next[0:0]$8704
- attribute \src "libresoc.v:162926.5-162926.29"
+ assign $0\adrok_l_s_addr_acked$next[0:0]$8646 $6\adrok_l_s_addr_acked$next[0:0]$8652
+ attribute \src "libresoc.v:162590.5-162590.29"
switch \initial
- attribute \src "libresoc.v:162926.9-162926.17"
+ attribute \src "libresoc.v:162590.9-162590.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\adrok_l_s_addr_acked$next[0:0]$8699 $2\adrok_l_s_addr_acked$next[0:0]$8700
+ assign $1\adrok_l_s_addr_acked$next[0:0]$8647 $2\adrok_l_s_addr_acked$next[0:0]$8648
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
switch \$7
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\adrok_l_s_addr_acked$next[0:0]$8700 1'1
+ assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'1
case
- assign $2\adrok_l_s_addr_acked$next[0:0]$8700 1'0
+ assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'0
end
case
- assign $1\adrok_l_s_addr_acked$next[0:0]$8699 1'0
+ assign $1\adrok_l_s_addr_acked$next[0:0]$8647 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
switch \st_active_q_st_active
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\adrok_l_s_addr_acked$next[0:0]$8701 $4\adrok_l_s_addr_acked$next[0:0]$8702
+ assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $4\adrok_l_s_addr_acked$next[0:0]$8650
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245"
switch \ldst_port0_addr_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\adrok_l_s_addr_acked$next[0:0]$8702 $5\adrok_l_s_addr_acked$next[0:0]$8703
+ assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $5\adrok_l_s_addr_acked$next[0:0]$8651
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247"
switch \adrok_l_qn_addr_acked
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\adrok_l_s_addr_acked$next[0:0]$8703 1'1
+ assign $5\adrok_l_s_addr_acked$next[0:0]$8651 1'1
case
- assign $5\adrok_l_s_addr_acked$next[0:0]$8703 $1\adrok_l_s_addr_acked$next[0:0]$8699
+ assign $5\adrok_l_s_addr_acked$next[0:0]$8651 $1\adrok_l_s_addr_acked$next[0:0]$8647
end
case
- assign $4\adrok_l_s_addr_acked$next[0:0]$8702 $1\adrok_l_s_addr_acked$next[0:0]$8699
+ assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $1\adrok_l_s_addr_acked$next[0:0]$8647
end
case
- assign $3\adrok_l_s_addr_acked$next[0:0]$8701 $1\adrok_l_s_addr_acked$next[0:0]$8699
+ assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $1\adrok_l_s_addr_acked$next[0:0]$8647
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\adrok_l_s_addr_acked$next[0:0]$8704 1'0
+ assign $6\adrok_l_s_addr_acked$next[0:0]$8652 1'0
case
- assign $6\adrok_l_s_addr_acked$next[0:0]$8704 $3\adrok_l_s_addr_acked$next[0:0]$8701
+ assign $6\adrok_l_s_addr_acked$next[0:0]$8652 $3\adrok_l_s_addr_acked$next[0:0]$8649
end
sync always
- update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8698
+ update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8646
end
- attribute \src "libresoc.v:162961.3-162976.6"
- process $proc$libresoc.v:162961$8705
+ attribute \src "libresoc.v:162625.3-162640.6"
+ process $proc$libresoc.v:162625$8653
assign { } { }
assign { } { }
assign { } { }
assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:162962.5-162962.29"
+ attribute \src "libresoc.v:162626.5-162626.29"
switch \initial
- attribute \src "libresoc.v:162962.9-162962.17"
+ attribute \src "libresoc.v:162626.9-162626.17"
case 1'1
case
end
sync always
update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0]
end
- connect \$9 $not$libresoc.v:162430$8609_Y
- connect \$11 $and$libresoc.v:162431$8610_Y
- connect \$13 $not$libresoc.v:162432$8611_Y
- connect \$15 $and$libresoc.v:162433$8612_Y
- connect \$17 $not$libresoc.v:162434$8613_Y
- connect \$1 $and$libresoc.v:162435$8614_Y
- connect \$19 $and$libresoc.v:162436$8615_Y
- connect \$21 $pos$libresoc.v:162437$8617_Y
- connect \$23 $pos$libresoc.v:162438$8619_Y
- connect \$25 $and$libresoc.v:162439$8620_Y
- connect \$27 $and$libresoc.v:162440$8621_Y
- connect \$29 $and$libresoc.v:162441$8622_Y
- connect \$31 $and$libresoc.v:162442$8623_Y
- connect \$33 $and$libresoc.v:162443$8624_Y
- connect \$35 $not$libresoc.v:162444$8625_Y
- connect \$38 $or$libresoc.v:162445$8626_Y
- connect \$3 $or$libresoc.v:162446$8627_Y
- connect \$37 $not$libresoc.v:162447$8628_Y
- connect \$42 $and$libresoc.v:162448$8629_Y
- connect \$44 $mul$libresoc.v:162449$8630_Y
- connect \$46 $sshr$libresoc.v:162450$8631_Y
- connect \$48 $and$libresoc.v:162451$8632_Y
- connect \$50 $and$libresoc.v:162452$8633_Y
- connect \$52 $not$libresoc.v:162453$8634_Y
- connect \$54 $and$libresoc.v:162454$8635_Y
- connect \$57 $mul$libresoc.v:162455$8636_Y
- connect \$5 $not$libresoc.v:162456$8637_Y
- connect \$59 $sshl$libresoc.v:162457$8638_Y
- connect \$61 $and$libresoc.v:162458$8639_Y
- connect \$63 $or$libresoc.v:162459$8640_Y
- connect \$65 $and$libresoc.v:162460$8641_Y
- connect \$67 $or$libresoc.v:162461$8642_Y
- connect \$69 $and$libresoc.v:162462$8643_Y
- connect \$71 $not$libresoc.v:162463$8644_Y
- connect \$73 $not$libresoc.v:162464$8645_Y
- connect \$75 $not$libresoc.v:162465$8646_Y
- connect \$77 $and$libresoc.v:162466$8647_Y
- connect \$7 $and$libresoc.v:162467$8648_Y
- connect \$79 $not$libresoc.v:162468$8649_Y
- connect \$81 $not$libresoc.v:162469$8650_Y
- connect \$83 $and$libresoc.v:162470$8651_Y
+ connect \$9 $not$libresoc.v:162094$8557_Y
+ connect \$11 $and$libresoc.v:162095$8558_Y
+ connect \$13 $not$libresoc.v:162096$8559_Y
+ connect \$15 $and$libresoc.v:162097$8560_Y
+ connect \$17 $not$libresoc.v:162098$8561_Y
+ connect \$1 $and$libresoc.v:162099$8562_Y
+ connect \$19 $and$libresoc.v:162100$8563_Y
+ connect \$21 $pos$libresoc.v:162101$8565_Y
+ connect \$23 $pos$libresoc.v:162102$8567_Y
+ connect \$25 $and$libresoc.v:162103$8568_Y
+ connect \$27 $and$libresoc.v:162104$8569_Y
+ connect \$29 $and$libresoc.v:162105$8570_Y
+ connect \$31 $and$libresoc.v:162106$8571_Y
+ connect \$33 $and$libresoc.v:162107$8572_Y
+ connect \$35 $not$libresoc.v:162108$8573_Y
+ connect \$38 $or$libresoc.v:162109$8574_Y
+ connect \$3 $or$libresoc.v:162110$8575_Y
+ connect \$37 $not$libresoc.v:162111$8576_Y
+ connect \$42 $and$libresoc.v:162112$8577_Y
+ connect \$44 $mul$libresoc.v:162113$8578_Y
+ connect \$46 $sshr$libresoc.v:162114$8579_Y
+ connect \$48 $and$libresoc.v:162115$8580_Y
+ connect \$50 $and$libresoc.v:162116$8581_Y
+ connect \$52 $not$libresoc.v:162117$8582_Y
+ connect \$54 $and$libresoc.v:162118$8583_Y
+ connect \$57 $mul$libresoc.v:162119$8584_Y
+ connect \$5 $not$libresoc.v:162120$8585_Y
+ connect \$59 $sshl$libresoc.v:162121$8586_Y
+ connect \$61 $and$libresoc.v:162122$8587_Y
+ connect \$63 $or$libresoc.v:162123$8588_Y
+ connect \$65 $and$libresoc.v:162124$8589_Y
+ connect \$67 $or$libresoc.v:162125$8590_Y
+ connect \$69 $and$libresoc.v:162126$8591_Y
+ connect \$71 $not$libresoc.v:162127$8592_Y
+ connect \$73 $not$libresoc.v:162128$8593_Y
+ connect \$75 $not$libresoc.v:162129$8594_Y
+ connect \$77 $and$libresoc.v:162130$8595_Y
+ connect \$7 $and$libresoc.v:162131$8596_Y
+ connect \$79 $not$libresoc.v:162132$8597_Y
+ connect \$81 $not$libresoc.v:162133$8598_Y
+ connect \$83 $and$libresoc.v:162134$8599_Y
connect \$41 \$46
connect \$56 \$59
connect \valid_l_r_valid \lsui_active_rise
connect \sts \ldst_port0_is_st_i
connect \lds \ldst_port0_is_ld_i
end
-attribute \src "libresoc.v:163002.1-163782.10"
+attribute \src "libresoc.v:162666.1-163446.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe"
attribute \generator "nMigen"
module \pipe
- attribute \src "libresoc.v:163745.3-163763.6"
- wire width 4 $0\cr_a$6$next[3:0]$8761
- attribute \src "libresoc.v:163609.3-163610.31"
- wire width 4 $0\cr_a$6[3:0]$8717
- attribute \src "libresoc.v:163016.13-163016.28"
- wire width 4 $0\cr_a$6[3:0]$8767
- attribute \src "libresoc.v:163745.3-163763.6"
- wire $0\cr_a_ok$next[0:0]$8760
- attribute \src "libresoc.v:163611.3-163612.31"
+ attribute \src "libresoc.v:163409.3-163427.6"
+ wire width 4 $0\cr_a$6$next[3:0]$8709
+ attribute \src "libresoc.v:163273.3-163274.31"
+ wire width 4 $0\cr_a$6[3:0]$8665
+ attribute \src "libresoc.v:162680.13-162680.28"
+ wire width 4 $0\cr_a$6[3:0]$8715
+ attribute \src "libresoc.v:163409.3-163427.6"
+ wire $0\cr_a_ok$next[0:0]$8708
+ attribute \src "libresoc.v:163275.3-163276.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8741
- attribute \src "libresoc.v:163623.3-163624.51"
- wire width 14 $0\cr_op__fn_unit$3[13:0]$8727
- attribute \src "libresoc.v:163081.14-163081.43"
- wire width 14 $0\cr_op__fn_unit$3[13:0]$8770
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 32 $0\cr_op__insn$4$next[31:0]$8742
- attribute \src "libresoc.v:163625.3-163626.45"
- wire width 32 $0\cr_op__insn$4[31:0]$8729
- attribute \src "libresoc.v:163090.14-163090.37"
- wire width 32 $0\cr_op__insn$4[31:0]$8772
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 7 $0\cr_op__insn_type$2$next[6:0]$8743
- attribute \src "libresoc.v:163621.3-163622.55"
- wire width 7 $0\cr_op__insn_type$2[6:0]$8725
- attribute \src "libresoc.v:163324.13-163324.41"
- wire width 7 $0\cr_op__insn_type$2[6:0]$8774
- attribute \src "libresoc.v:163726.3-163744.6"
- wire width 32 $0\full_cr$5$next[31:0]$8754
- attribute \src "libresoc.v:163613.3-163614.37"
- wire width 32 $0\full_cr$5[31:0]$8720
- attribute \src "libresoc.v:163333.14-163333.33"
- wire width 32 $0\full_cr$5[31:0]$8776
- attribute \src "libresoc.v:163726.3-163744.6"
- wire $0\full_cr_ok$next[0:0]$8755
- attribute \src "libresoc.v:163615.3-163616.37"
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8689
+ attribute \src "libresoc.v:163287.3-163288.51"
+ wire width 14 $0\cr_op__fn_unit$3[13:0]$8675
+ attribute \src "libresoc.v:162745.14-162745.43"
+ wire width 14 $0\cr_op__fn_unit$3[13:0]$8718
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 32 $0\cr_op__insn$4$next[31:0]$8690
+ attribute \src "libresoc.v:163289.3-163290.45"
+ wire width 32 $0\cr_op__insn$4[31:0]$8677
+ attribute \src "libresoc.v:162754.14-162754.37"
+ wire width 32 $0\cr_op__insn$4[31:0]$8720
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 7 $0\cr_op__insn_type$2$next[6:0]$8691
+ attribute \src "libresoc.v:163285.3-163286.55"
+ wire width 7 $0\cr_op__insn_type$2[6:0]$8673
+ attribute \src "libresoc.v:162988.13-162988.41"
+ wire width 7 $0\cr_op__insn_type$2[6:0]$8722
+ attribute \src "libresoc.v:163390.3-163408.6"
+ wire width 32 $0\full_cr$5$next[31:0]$8702
+ attribute \src "libresoc.v:163277.3-163278.37"
+ wire width 32 $0\full_cr$5[31:0]$8668
+ attribute \src "libresoc.v:162997.14-162997.33"
+ wire width 32 $0\full_cr$5[31:0]$8724
+ attribute \src "libresoc.v:163390.3-163408.6"
+ wire $0\full_cr_ok$next[0:0]$8703
+ attribute \src "libresoc.v:163279.3-163280.37"
wire $0\full_cr_ok[0:0]
- attribute \src "libresoc.v:163003.7-163003.20"
+ attribute \src "libresoc.v:162667.7-162667.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:163679.3-163691.6"
- wire width 2 $0\muxid$1$next[1:0]$8738
- attribute \src "libresoc.v:163627.3-163628.33"
- wire width 2 $0\muxid$1[1:0]$8731
- attribute \src "libresoc.v:163567.13-163567.29"
- wire width 2 $0\muxid$1[1:0]$8779
- attribute \src "libresoc.v:163707.3-163725.6"
- wire width 64 $0\o$next[63:0]$8748
- attribute \src "libresoc.v:163617.3-163618.19"
+ attribute \src "libresoc.v:163343.3-163355.6"
+ wire width 2 $0\muxid$1$next[1:0]$8686
+ attribute \src "libresoc.v:163291.3-163292.33"
+ wire width 2 $0\muxid$1[1:0]$8679
+ attribute \src "libresoc.v:163231.13-163231.29"
+ wire width 2 $0\muxid$1[1:0]$8727
+ attribute \src "libresoc.v:163371.3-163389.6"
+ wire width 64 $0\o$next[63:0]$8696
+ attribute \src "libresoc.v:163281.3-163282.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:163707.3-163725.6"
- wire $0\o_ok$next[0:0]$8749
- attribute \src "libresoc.v:163619.3-163620.25"
+ attribute \src "libresoc.v:163371.3-163389.6"
+ wire $0\o_ok$next[0:0]$8697
+ attribute \src "libresoc.v:163283.3-163284.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:163661.3-163678.6"
- wire $0\r_busy$next[0:0]$8734
- attribute \src "libresoc.v:163629.3-163630.29"
+ attribute \src "libresoc.v:163325.3-163342.6"
+ wire $0\r_busy$next[0:0]$8682
+ attribute \src "libresoc.v:163293.3-163294.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:163745.3-163763.6"
- wire width 4 $1\cr_a$6$next[3:0]$8763
- attribute \src "libresoc.v:163745.3-163763.6"
- wire $1\cr_a_ok$next[0:0]$8762
- attribute \src "libresoc.v:163021.7-163021.21"
+ attribute \src "libresoc.v:163409.3-163427.6"
+ wire width 4 $1\cr_a$6$next[3:0]$8711
+ attribute \src "libresoc.v:163409.3-163427.6"
+ wire $1\cr_a_ok$next[0:0]$8710
+ attribute \src "libresoc.v:162685.7-162685.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8744
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 32 $1\cr_op__insn$4$next[31:0]$8745
- attribute \src "libresoc.v:163692.3-163706.6"
- wire width 7 $1\cr_op__insn_type$2$next[6:0]$8746
- attribute \src "libresoc.v:163726.3-163744.6"
- wire width 32 $1\full_cr$5$next[31:0]$8756
- attribute \src "libresoc.v:163726.3-163744.6"
- wire $1\full_cr_ok$next[0:0]$8757
- attribute \src "libresoc.v:163338.7-163338.24"
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8692
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 32 $1\cr_op__insn$4$next[31:0]$8693
+ attribute \src "libresoc.v:163356.3-163370.6"
+ wire width 7 $1\cr_op__insn_type$2$next[6:0]$8694
+ attribute \src "libresoc.v:163390.3-163408.6"
+ wire width 32 $1\full_cr$5$next[31:0]$8704
+ attribute \src "libresoc.v:163390.3-163408.6"
+ wire $1\full_cr_ok$next[0:0]$8705
+ attribute \src "libresoc.v:163002.7-163002.24"
wire $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:163679.3-163691.6"
- wire width 2 $1\muxid$1$next[1:0]$8739
- attribute \src "libresoc.v:163707.3-163725.6"
- wire width 64 $1\o$next[63:0]$8750
- attribute \src "libresoc.v:163580.14-163580.38"
+ attribute \src "libresoc.v:163343.3-163355.6"
+ wire width 2 $1\muxid$1$next[1:0]$8687
+ attribute \src "libresoc.v:163371.3-163389.6"
+ wire width 64 $1\o$next[63:0]$8698
+ attribute \src "libresoc.v:163244.14-163244.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:163707.3-163725.6"
- wire $1\o_ok$next[0:0]$8751
- attribute \src "libresoc.v:163587.7-163587.18"
+ attribute \src "libresoc.v:163371.3-163389.6"
+ wire $1\o_ok$next[0:0]$8699
+ attribute \src "libresoc.v:163251.7-163251.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:163661.3-163678.6"
- wire $1\r_busy$next[0:0]$8735
- attribute \src "libresoc.v:163601.7-163601.20"
+ attribute \src "libresoc.v:163325.3-163342.6"
+ wire $1\r_busy$next[0:0]$8683
+ attribute \src "libresoc.v:163265.7-163265.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:163745.3-163763.6"
- wire $2\cr_a_ok$next[0:0]$8764
- attribute \src "libresoc.v:163726.3-163744.6"
- wire $2\full_cr_ok$next[0:0]$8758
- attribute \src "libresoc.v:163707.3-163725.6"
- wire $2\o_ok$next[0:0]$8752
- attribute \src "libresoc.v:163661.3-163678.6"
- wire $2\r_busy$next[0:0]$8736
- attribute \src "libresoc.v:163608.18-163608.118"
- wire $and$libresoc.v:163608$8715_Y
+ attribute \src "libresoc.v:163409.3-163427.6"
+ wire $2\cr_a_ok$next[0:0]$8712
+ attribute \src "libresoc.v:163390.3-163408.6"
+ wire $2\full_cr_ok$next[0:0]$8706
+ attribute \src "libresoc.v:163371.3-163389.6"
+ wire $2\o_ok$next[0:0]$8700
+ attribute \src "libresoc.v:163325.3-163342.6"
+ wire $2\r_busy$next[0:0]$8684
+ attribute \src "libresoc.v:163272.18-163272.118"
+ wire $and$libresoc.v:163272$8663_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 11 \cr_a
wire \full_cr_ok$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \full_cr_ok$next
- attribute \src "libresoc.v:163003.7-163003.15"
+ attribute \src "libresoc.v:162667.7-162667.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \main_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 9 \rb
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:163608$8715
+ cell $and $and$libresoc.v:163272$8663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$13
connect \B \p_ready_o
- connect \Y $and$libresoc.v:163608$8715_Y
+ connect \Y $and$libresoc.v:163272$8663_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:163631.12-163652.4"
+ attribute \src "libresoc.v:163295.12-163316.4"
cell \main$9 \main
connect \cr_a \main_cr_a
connect \cr_a$6 \main_cr_a$12
connect \rb \main_rb
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:163653.9-163656.4"
+ attribute \src "libresoc.v:163317.9-163320.4"
cell \n$8 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:163657.9-163660.4"
+ attribute \src "libresoc.v:163321.9-163324.4"
cell \p$7 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:163003.7-163003.20"
- process $proc$libresoc.v:163003$8765
+ attribute \src "libresoc.v:162667.7-162667.20"
+ process $proc$libresoc.v:162667$8713
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:163016.13-163016.28"
- process $proc$libresoc.v:163016$8766
+ attribute \src "libresoc.v:162680.13-162680.28"
+ process $proc$libresoc.v:162680$8714
assign { } { }
- assign $0\cr_a$6[3:0]$8767 4'0000
+ assign $0\cr_a$6[3:0]$8715 4'0000
sync always
sync init
- update \cr_a$6 $0\cr_a$6[3:0]$8767
+ update \cr_a$6 $0\cr_a$6[3:0]$8715
end
- attribute \src "libresoc.v:163021.7-163021.21"
- process $proc$libresoc.v:163021$8768
+ attribute \src "libresoc.v:162685.7-162685.21"
+ process $proc$libresoc.v:162685$8716
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:163081.14-163081.43"
- process $proc$libresoc.v:163081$8769
+ attribute \src "libresoc.v:162745.14-162745.43"
+ process $proc$libresoc.v:162745$8717
assign { } { }
- assign $0\cr_op__fn_unit$3[13:0]$8770 14'00000000000000
+ assign $0\cr_op__fn_unit$3[13:0]$8718 14'00000000000000
sync always
sync init
- update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8770
+ update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8718
end
- attribute \src "libresoc.v:163090.14-163090.37"
- process $proc$libresoc.v:163090$8771
+ attribute \src "libresoc.v:162754.14-162754.37"
+ process $proc$libresoc.v:162754$8719
assign { } { }
- assign $0\cr_op__insn$4[31:0]$8772 0
+ assign $0\cr_op__insn$4[31:0]$8720 0
sync always
sync init
- update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8772
+ update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8720
end
- attribute \src "libresoc.v:163324.13-163324.41"
- process $proc$libresoc.v:163324$8773
+ attribute \src "libresoc.v:162988.13-162988.41"
+ process $proc$libresoc.v:162988$8721
assign { } { }
- assign $0\cr_op__insn_type$2[6:0]$8774 7'0000000
+ assign $0\cr_op__insn_type$2[6:0]$8722 7'0000000
sync always
sync init
- update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8774
+ update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8722
end
- attribute \src "libresoc.v:163333.14-163333.33"
- process $proc$libresoc.v:163333$8775
+ attribute \src "libresoc.v:162997.14-162997.33"
+ process $proc$libresoc.v:162997$8723
assign { } { }
- assign $0\full_cr$5[31:0]$8776 0
+ assign $0\full_cr$5[31:0]$8724 0
sync always
sync init
- update \full_cr$5 $0\full_cr$5[31:0]$8776
+ update \full_cr$5 $0\full_cr$5[31:0]$8724
end
- attribute \src "libresoc.v:163338.7-163338.24"
- process $proc$libresoc.v:163338$8777
+ attribute \src "libresoc.v:163002.7-163002.24"
+ process $proc$libresoc.v:163002$8725
assign { } { }
assign $1\full_cr_ok[0:0] 1'0
sync always
sync init
update \full_cr_ok $1\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:163567.13-163567.29"
- process $proc$libresoc.v:163567$8778
+ attribute \src "libresoc.v:163231.13-163231.29"
+ process $proc$libresoc.v:163231$8726
assign { } { }
- assign $0\muxid$1[1:0]$8779 2'00
+ assign $0\muxid$1[1:0]$8727 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8779
+ update \muxid$1 $0\muxid$1[1:0]$8727
end
- attribute \src "libresoc.v:163580.14-163580.38"
- process $proc$libresoc.v:163580$8780
+ attribute \src "libresoc.v:163244.14-163244.38"
+ process $proc$libresoc.v:163244$8728
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:163587.7-163587.18"
- process $proc$libresoc.v:163587$8781
+ attribute \src "libresoc.v:163251.7-163251.18"
+ process $proc$libresoc.v:163251$8729
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:163601.7-163601.20"
- process $proc$libresoc.v:163601$8782
+ attribute \src "libresoc.v:163265.7-163265.20"
+ process $proc$libresoc.v:163265$8730
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:163609.3-163610.31"
- process $proc$libresoc.v:163609$8716
+ attribute \src "libresoc.v:163273.3-163274.31"
+ process $proc$libresoc.v:163273$8664
assign { } { }
- assign $0\cr_a$6[3:0]$8717 \cr_a$6$next
+ assign $0\cr_a$6[3:0]$8665 \cr_a$6$next
sync posedge \coresync_clk
- update \cr_a$6 $0\cr_a$6[3:0]$8717
+ update \cr_a$6 $0\cr_a$6[3:0]$8665
end
- attribute \src "libresoc.v:163611.3-163612.31"
- process $proc$libresoc.v:163611$8718
+ attribute \src "libresoc.v:163275.3-163276.31"
+ process $proc$libresoc.v:163275$8666
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:163613.3-163614.37"
- process $proc$libresoc.v:163613$8719
+ attribute \src "libresoc.v:163277.3-163278.37"
+ process $proc$libresoc.v:163277$8667
assign { } { }
- assign $0\full_cr$5[31:0]$8720 \full_cr$5$next
+ assign $0\full_cr$5[31:0]$8668 \full_cr$5$next
sync posedge \coresync_clk
- update \full_cr$5 $0\full_cr$5[31:0]$8720
+ update \full_cr$5 $0\full_cr$5[31:0]$8668
end
- attribute \src "libresoc.v:163615.3-163616.37"
- process $proc$libresoc.v:163615$8721
+ attribute \src "libresoc.v:163279.3-163280.37"
+ process $proc$libresoc.v:163279$8669
assign { } { }
assign $0\full_cr_ok[0:0] \full_cr_ok$next
sync posedge \coresync_clk
update \full_cr_ok $0\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:163617.3-163618.19"
- process $proc$libresoc.v:163617$8722
+ attribute \src "libresoc.v:163281.3-163282.19"
+ process $proc$libresoc.v:163281$8670
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:163619.3-163620.25"
- process $proc$libresoc.v:163619$8723
+ attribute \src "libresoc.v:163283.3-163284.25"
+ process $proc$libresoc.v:163283$8671
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:163621.3-163622.55"
- process $proc$libresoc.v:163621$8724
+ attribute \src "libresoc.v:163285.3-163286.55"
+ process $proc$libresoc.v:163285$8672
assign { } { }
- assign $0\cr_op__insn_type$2[6:0]$8725 \cr_op__insn_type$2$next
+ assign $0\cr_op__insn_type$2[6:0]$8673 \cr_op__insn_type$2$next
sync posedge \coresync_clk
- update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8725
+ update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8673
end
- attribute \src "libresoc.v:163623.3-163624.51"
- process $proc$libresoc.v:163623$8726
+ attribute \src "libresoc.v:163287.3-163288.51"
+ process $proc$libresoc.v:163287$8674
assign { } { }
- assign $0\cr_op__fn_unit$3[13:0]$8727 \cr_op__fn_unit$3$next
+ assign $0\cr_op__fn_unit$3[13:0]$8675 \cr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8727
+ update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8675
end
- attribute \src "libresoc.v:163625.3-163626.45"
- process $proc$libresoc.v:163625$8728
+ attribute \src "libresoc.v:163289.3-163290.45"
+ process $proc$libresoc.v:163289$8676
assign { } { }
- assign $0\cr_op__insn$4[31:0]$8729 \cr_op__insn$4$next
+ assign $0\cr_op__insn$4[31:0]$8677 \cr_op__insn$4$next
sync posedge \coresync_clk
- update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8729
+ update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8677
end
- attribute \src "libresoc.v:163627.3-163628.33"
- process $proc$libresoc.v:163627$8730
+ attribute \src "libresoc.v:163291.3-163292.33"
+ process $proc$libresoc.v:163291$8678
assign { } { }
- assign $0\muxid$1[1:0]$8731 \muxid$1$next
+ assign $0\muxid$1[1:0]$8679 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8731
+ update \muxid$1 $0\muxid$1[1:0]$8679
end
- attribute \src "libresoc.v:163629.3-163630.29"
- process $proc$libresoc.v:163629$8732
+ attribute \src "libresoc.v:163293.3-163294.29"
+ process $proc$libresoc.v:163293$8680
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:163661.3-163678.6"
- process $proc$libresoc.v:163661$8733
+ attribute \src "libresoc.v:163325.3-163342.6"
+ process $proc$libresoc.v:163325$8681
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8734 $2\r_busy$next[0:0]$8736
- attribute \src "libresoc.v:163662.5-163662.29"
+ assign $0\r_busy$next[0:0]$8682 $2\r_busy$next[0:0]$8684
+ attribute \src "libresoc.v:163326.5-163326.29"
switch \initial
- attribute \src "libresoc.v:163662.9-163662.17"
+ attribute \src "libresoc.v:163326.9-163326.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8735 1'1
+ assign $1\r_busy$next[0:0]$8683 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8735 1'0
+ assign $1\r_busy$next[0:0]$8683 1'0
case
- assign $1\r_busy$next[0:0]$8735 \r_busy
+ assign $1\r_busy$next[0:0]$8683 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8736 1'0
+ assign $2\r_busy$next[0:0]$8684 1'0
case
- assign $2\r_busy$next[0:0]$8736 $1\r_busy$next[0:0]$8735
+ assign $2\r_busy$next[0:0]$8684 $1\r_busy$next[0:0]$8683
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8734
+ update \r_busy$next $0\r_busy$next[0:0]$8682
end
- attribute \src "libresoc.v:163679.3-163691.6"
- process $proc$libresoc.v:163679$8737
+ attribute \src "libresoc.v:163343.3-163355.6"
+ process $proc$libresoc.v:163343$8685
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8738 $1\muxid$1$next[1:0]$8739
- attribute \src "libresoc.v:163680.5-163680.29"
+ assign $0\muxid$1$next[1:0]$8686 $1\muxid$1$next[1:0]$8687
+ attribute \src "libresoc.v:163344.5-163344.29"
switch \initial
- attribute \src "libresoc.v:163680.9-163680.17"
+ attribute \src "libresoc.v:163344.9-163344.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8739 \muxid$16
+ assign $1\muxid$1$next[1:0]$8687 \muxid$16
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8739 \muxid$16
+ assign $1\muxid$1$next[1:0]$8687 \muxid$16
case
- assign $1\muxid$1$next[1:0]$8739 \muxid$1
+ assign $1\muxid$1$next[1:0]$8687 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8738
+ update \muxid$1$next $0\muxid$1$next[1:0]$8686
end
- attribute \src "libresoc.v:163692.3-163706.6"
- process $proc$libresoc.v:163692$8740
+ attribute \src "libresoc.v:163356.3-163370.6"
+ process $proc$libresoc.v:163356$8688
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_op__fn_unit$3$next[13:0]$8741 $1\cr_op__fn_unit$3$next[13:0]$8744
- assign $0\cr_op__insn$4$next[31:0]$8742 $1\cr_op__insn$4$next[31:0]$8745
- assign $0\cr_op__insn_type$2$next[6:0]$8743 $1\cr_op__insn_type$2$next[6:0]$8746
- attribute \src "libresoc.v:163693.5-163693.29"
+ assign $0\cr_op__fn_unit$3$next[13:0]$8689 $1\cr_op__fn_unit$3$next[13:0]$8692
+ assign $0\cr_op__insn$4$next[31:0]$8690 $1\cr_op__insn$4$next[31:0]$8693
+ assign $0\cr_op__insn_type$2$next[6:0]$8691 $1\cr_op__insn_type$2$next[6:0]$8694
+ attribute \src "libresoc.v:163357.5-163357.29"
switch \initial
- attribute \src "libresoc.v:163693.9-163693.17"
+ attribute \src "libresoc.v:163357.9-163357.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\cr_op__insn$4$next[31:0]$8745 $1\cr_op__fn_unit$3$next[13:0]$8744 $1\cr_op__insn_type$2$next[6:0]$8746 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
+ assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
- assign { $1\cr_op__insn$4$next[31:0]$8745 $1\cr_op__fn_unit$3$next[13:0]$8744 $1\cr_op__insn_type$2$next[6:0]$8746 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
+ assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
case
- assign $1\cr_op__fn_unit$3$next[13:0]$8744 \cr_op__fn_unit$3
- assign $1\cr_op__insn$4$next[31:0]$8745 \cr_op__insn$4
- assign $1\cr_op__insn_type$2$next[6:0]$8746 \cr_op__insn_type$2
+ assign $1\cr_op__fn_unit$3$next[13:0]$8692 \cr_op__fn_unit$3
+ assign $1\cr_op__insn$4$next[31:0]$8693 \cr_op__insn$4
+ assign $1\cr_op__insn_type$2$next[6:0]$8694 \cr_op__insn_type$2
end
sync always
- update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8741
- update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8742
- update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8743
+ update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8689
+ update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8690
+ update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8691
end
- attribute \src "libresoc.v:163707.3-163725.6"
- process $proc$libresoc.v:163707$8747
+ attribute \src "libresoc.v:163371.3-163389.6"
+ process $proc$libresoc.v:163371$8695
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$8748 $1\o$next[63:0]$8750
+ assign $0\o$next[63:0]$8696 $1\o$next[63:0]$8698
assign { } { }
- assign $0\o_ok$next[0:0]$8749 $2\o_ok$next[0:0]$8752
- attribute \src "libresoc.v:163708.5-163708.29"
+ assign $0\o_ok$next[0:0]$8697 $2\o_ok$next[0:0]$8700
+ attribute \src "libresoc.v:163372.5-163372.29"
switch \initial
- attribute \src "libresoc.v:163708.9-163708.17"
+ attribute \src "libresoc.v:163372.9-163372.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8751 $1\o$next[63:0]$8750 } { \o_ok$21 \o$20 }
+ assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8751 $1\o$next[63:0]$8750 } { \o_ok$21 \o$20 }
+ assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 }
case
- assign $1\o$next[63:0]$8750 \o
- assign $1\o_ok$next[0:0]$8751 \o_ok
+ assign $1\o$next[63:0]$8698 \o
+ assign $1\o_ok$next[0:0]$8699 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8752 1'0
+ assign $2\o_ok$next[0:0]$8700 1'0
case
- assign $2\o_ok$next[0:0]$8752 $1\o_ok$next[0:0]$8751
+ assign $2\o_ok$next[0:0]$8700 $1\o_ok$next[0:0]$8699
end
sync always
- update \o$next $0\o$next[63:0]$8748
- update \o_ok$next $0\o_ok$next[0:0]$8749
+ update \o$next $0\o$next[63:0]$8696
+ update \o_ok$next $0\o_ok$next[0:0]$8697
end
- attribute \src "libresoc.v:163726.3-163744.6"
- process $proc$libresoc.v:163726$8753
+ attribute \src "libresoc.v:163390.3-163408.6"
+ process $proc$libresoc.v:163390$8701
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\full_cr$5$next[31:0]$8754 $1\full_cr$5$next[31:0]$8756
+ assign $0\full_cr$5$next[31:0]$8702 $1\full_cr$5$next[31:0]$8704
assign { } { }
- assign $0\full_cr_ok$next[0:0]$8755 $2\full_cr_ok$next[0:0]$8758
- attribute \src "libresoc.v:163727.5-163727.29"
+ assign $0\full_cr_ok$next[0:0]$8703 $2\full_cr_ok$next[0:0]$8706
+ attribute \src "libresoc.v:163391.5-163391.29"
switch \initial
- attribute \src "libresoc.v:163727.9-163727.17"
+ attribute \src "libresoc.v:163391.9-163391.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\full_cr_ok$next[0:0]$8757 $1\full_cr$5$next[31:0]$8756 } { \full_cr_ok$23 \full_cr$22 }
+ assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\full_cr_ok$next[0:0]$8757 $1\full_cr$5$next[31:0]$8756 } { \full_cr_ok$23 \full_cr$22 }
+ assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 }
case
- assign $1\full_cr$5$next[31:0]$8756 \full_cr$5
- assign $1\full_cr_ok$next[0:0]$8757 \full_cr_ok
+ assign $1\full_cr$5$next[31:0]$8704 \full_cr$5
+ assign $1\full_cr_ok$next[0:0]$8705 \full_cr_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\full_cr_ok$next[0:0]$8758 1'0
+ assign $2\full_cr_ok$next[0:0]$8706 1'0
case
- assign $2\full_cr_ok$next[0:0]$8758 $1\full_cr_ok$next[0:0]$8757
+ assign $2\full_cr_ok$next[0:0]$8706 $1\full_cr_ok$next[0:0]$8705
end
sync always
- update \full_cr$5$next $0\full_cr$5$next[31:0]$8754
- update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8755
+ update \full_cr$5$next $0\full_cr$5$next[31:0]$8702
+ update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8703
end
- attribute \src "libresoc.v:163745.3-163763.6"
- process $proc$libresoc.v:163745$8759
+ attribute \src "libresoc.v:163409.3-163427.6"
+ process $proc$libresoc.v:163409$8707
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$6$next[3:0]$8761 $1\cr_a$6$next[3:0]$8763
- assign $0\cr_a_ok$next[0:0]$8760 $2\cr_a_ok$next[0:0]$8764
- attribute \src "libresoc.v:163746.5-163746.29"
+ assign $0\cr_a$6$next[3:0]$8709 $1\cr_a$6$next[3:0]$8711
+ assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8712
+ attribute \src "libresoc.v:163410.5-163410.29"
switch \initial
- attribute \src "libresoc.v:163746.9-163746.17"
+ attribute \src "libresoc.v:163410.9-163410.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8762 $1\cr_a$6$next[3:0]$8763 } { \cr_a_ok$25 \cr_a$24 }
+ assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8762 $1\cr_a$6$next[3:0]$8763 } { \cr_a_ok$25 \cr_a$24 }
+ assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 }
case
- assign $1\cr_a_ok$next[0:0]$8762 \cr_a_ok
- assign $1\cr_a$6$next[3:0]$8763 \cr_a$6
+ assign $1\cr_a_ok$next[0:0]$8710 \cr_a_ok
+ assign $1\cr_a$6$next[3:0]$8711 \cr_a$6
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$8764 1'0
+ assign $2\cr_a_ok$next[0:0]$8712 1'0
case
- assign $2\cr_a_ok$next[0:0]$8764 $1\cr_a_ok$next[0:0]$8762
+ assign $2\cr_a_ok$next[0:0]$8712 $1\cr_a_ok$next[0:0]$8710
end
sync always
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8760
- update \cr_a$6$next $0\cr_a$6$next[3:0]$8761
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708
+ update \cr_a$6$next $0\cr_a$6$next[3:0]$8709
end
- connect \$14 $and$libresoc.v:163608$8715_Y
+ connect \$14 $and$libresoc.v:163272$8663_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 }
connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:163786.1-164646.10"
+attribute \src "libresoc.v:163450.1-164310.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe"
attribute \generator "nMigen"
module \pipe$19
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 64 $0\br_op__cia$2$next[63:0]$8819
- attribute \src "libresoc.v:164458.3-164459.43"
- wire width 64 $0\br_op__cia$2[63:0]$8793
- attribute \src "libresoc.v:163794.14-163794.51"
- wire width 64 $0\br_op__cia$2[63:0]$8857
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 14 $0\br_op__fn_unit$4$next[13:0]$8820
- attribute \src "libresoc.v:164462.3-164463.51"
- wire width 14 $0\br_op__fn_unit$4[13:0]$8797
- attribute \src "libresoc.v:163850.14-163850.43"
- wire width 14 $0\br_op__fn_unit$4[13:0]$8859
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8821
- attribute \src "libresoc.v:164466.3-164467.65"
- wire width 64 $0\br_op__imm_data__data$6[63:0]$8801
- attribute \src "libresoc.v:163859.14-163859.62"
- wire width 64 $0\br_op__imm_data__data$6[63:0]$8861
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $0\br_op__imm_data__ok$7$next[0:0]$8822
- attribute \src "libresoc.v:164468.3-164469.61"
- wire $0\br_op__imm_data__ok$7[0:0]$8803
- attribute \src "libresoc.v:163868.7-163868.37"
- wire $0\br_op__imm_data__ok$7[0:0]$8863
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 32 $0\br_op__insn$5$next[31:0]$8823
- attribute \src "libresoc.v:164464.3-164465.45"
- wire width 32 $0\br_op__insn$5[31:0]$8799
- attribute \src "libresoc.v:163877.14-163877.37"
- wire width 32 $0\br_op__insn$5[31:0]$8865
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 7 $0\br_op__insn_type$3$next[6:0]$8824
- attribute \src "libresoc.v:164460.3-164461.55"
- wire width 7 $0\br_op__insn_type$3[6:0]$8795
- attribute \src "libresoc.v:164111.13-164111.41"
- wire width 7 $0\br_op__insn_type$3[6:0]$8867
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $0\br_op__is_32bit$9$next[0:0]$8825
- attribute \src "libresoc.v:164472.3-164473.53"
- wire $0\br_op__is_32bit$9[0:0]$8807
- attribute \src "libresoc.v:164120.7-164120.33"
- wire $0\br_op__is_32bit$9[0:0]$8869
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $0\br_op__lk$8$next[0:0]$8826
- attribute \src "libresoc.v:164470.3-164471.41"
- wire $0\br_op__lk$8[0:0]$8805
- attribute \src "libresoc.v:164129.7-164129.27"
- wire $0\br_op__lk$8[0:0]$8871
- attribute \src "libresoc.v:164574.3-164592.6"
- wire width 64 $0\fast1$10$next[63:0]$8838
- attribute \src "libresoc.v:164454.3-164455.35"
- wire width 64 $0\fast1$10[63:0]$8790
- attribute \src "libresoc.v:164142.14-164142.47"
- wire width 64 $0\fast1$10[63:0]$8873
- attribute \src "libresoc.v:164574.3-164592.6"
- wire $0\fast1_ok$next[0:0]$8839
- attribute \src "libresoc.v:164456.3-164457.33"
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 64 $0\br_op__cia$2$next[63:0]$8767
+ attribute \src "libresoc.v:164122.3-164123.43"
+ wire width 64 $0\br_op__cia$2[63:0]$8741
+ attribute \src "libresoc.v:163458.14-163458.51"
+ wire width 64 $0\br_op__cia$2[63:0]$8805
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 14 $0\br_op__fn_unit$4$next[13:0]$8768
+ attribute \src "libresoc.v:164126.3-164127.51"
+ wire width 14 $0\br_op__fn_unit$4[13:0]$8745
+ attribute \src "libresoc.v:163514.14-163514.43"
+ wire width 14 $0\br_op__fn_unit$4[13:0]$8807
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8769
+ attribute \src "libresoc.v:164130.3-164131.65"
+ wire width 64 $0\br_op__imm_data__data$6[63:0]$8749
+ attribute \src "libresoc.v:163523.14-163523.62"
+ wire width 64 $0\br_op__imm_data__data$6[63:0]$8809
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $0\br_op__imm_data__ok$7$next[0:0]$8770
+ attribute \src "libresoc.v:164132.3-164133.61"
+ wire $0\br_op__imm_data__ok$7[0:0]$8751
+ attribute \src "libresoc.v:163532.7-163532.37"
+ wire $0\br_op__imm_data__ok$7[0:0]$8811
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 32 $0\br_op__insn$5$next[31:0]$8771
+ attribute \src "libresoc.v:164128.3-164129.45"
+ wire width 32 $0\br_op__insn$5[31:0]$8747
+ attribute \src "libresoc.v:163541.14-163541.37"
+ wire width 32 $0\br_op__insn$5[31:0]$8813
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 7 $0\br_op__insn_type$3$next[6:0]$8772
+ attribute \src "libresoc.v:164124.3-164125.55"
+ wire width 7 $0\br_op__insn_type$3[6:0]$8743
+ attribute \src "libresoc.v:163775.13-163775.41"
+ wire width 7 $0\br_op__insn_type$3[6:0]$8815
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $0\br_op__is_32bit$9$next[0:0]$8773
+ attribute \src "libresoc.v:164136.3-164137.53"
+ wire $0\br_op__is_32bit$9[0:0]$8755
+ attribute \src "libresoc.v:163784.7-163784.33"
+ wire $0\br_op__is_32bit$9[0:0]$8817
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $0\br_op__lk$8$next[0:0]$8774
+ attribute \src "libresoc.v:164134.3-164135.41"
+ wire $0\br_op__lk$8[0:0]$8753
+ attribute \src "libresoc.v:163793.7-163793.27"
+ wire $0\br_op__lk$8[0:0]$8819
+ attribute \src "libresoc.v:164238.3-164256.6"
+ wire width 64 $0\fast1$10$next[63:0]$8786
+ attribute \src "libresoc.v:164118.3-164119.35"
+ wire width 64 $0\fast1$10[63:0]$8738
+ attribute \src "libresoc.v:163806.14-163806.47"
+ wire width 64 $0\fast1$10[63:0]$8821
+ attribute \src "libresoc.v:164238.3-164256.6"
+ wire $0\fast1_ok$next[0:0]$8787
+ attribute \src "libresoc.v:164120.3-164121.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:164593.3-164611.6"
- wire width 64 $0\fast2$11$next[63:0]$8844
- attribute \src "libresoc.v:164450.3-164451.35"
- wire width 64 $0\fast2$11[63:0]$8787
- attribute \src "libresoc.v:164158.14-164158.47"
- wire width 64 $0\fast2$11[63:0]$8876
- attribute \src "libresoc.v:164593.3-164611.6"
- wire $0\fast2_ok$next[0:0]$8845
- attribute \src "libresoc.v:164452.3-164453.33"
+ attribute \src "libresoc.v:164257.3-164275.6"
+ wire width 64 $0\fast2$11$next[63:0]$8792
+ attribute \src "libresoc.v:164114.3-164115.35"
+ wire width 64 $0\fast2$11[63:0]$8735
+ attribute \src "libresoc.v:163822.14-163822.47"
+ wire width 64 $0\fast2$11[63:0]$8824
+ attribute \src "libresoc.v:164257.3-164275.6"
+ wire $0\fast2_ok$next[0:0]$8793
+ attribute \src "libresoc.v:164116.3-164117.33"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:163787.7-163787.20"
+ attribute \src "libresoc.v:163451.7-163451.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:164533.3-164545.6"
- wire width 2 $0\muxid$1$next[1:0]$8816
- attribute \src "libresoc.v:164474.3-164475.33"
- wire width 2 $0\muxid$1[1:0]$8809
- attribute \src "libresoc.v:164408.13-164408.29"
- wire width 2 $0\muxid$1[1:0]$8879
- attribute \src "libresoc.v:164612.3-164630.6"
- wire width 64 $0\nia$next[63:0]$8850
- attribute \src "libresoc.v:164446.3-164447.23"
+ attribute \src "libresoc.v:164197.3-164209.6"
+ wire width 2 $0\muxid$1$next[1:0]$8764
+ attribute \src "libresoc.v:164138.3-164139.33"
+ wire width 2 $0\muxid$1[1:0]$8757
+ attribute \src "libresoc.v:164072.13-164072.29"
+ wire width 2 $0\muxid$1[1:0]$8827
+ attribute \src "libresoc.v:164276.3-164294.6"
+ wire width 64 $0\nia$next[63:0]$8798
+ attribute \src "libresoc.v:164110.3-164111.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:164612.3-164630.6"
- wire $0\nia_ok$next[0:0]$8851
- attribute \src "libresoc.v:164448.3-164449.29"
+ attribute \src "libresoc.v:164276.3-164294.6"
+ wire $0\nia_ok$next[0:0]$8799
+ attribute \src "libresoc.v:164112.3-164113.29"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:164515.3-164532.6"
- wire $0\r_busy$next[0:0]$8812
- attribute \src "libresoc.v:164476.3-164477.29"
+ attribute \src "libresoc.v:164179.3-164196.6"
+ wire $0\r_busy$next[0:0]$8760
+ attribute \src "libresoc.v:164140.3-164141.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 64 $1\br_op__cia$2$next[63:0]$8827
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 14 $1\br_op__fn_unit$4$next[13:0]$8828
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8829
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $1\br_op__imm_data__ok$7$next[0:0]$8830
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 32 $1\br_op__insn$5$next[31:0]$8831
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 7 $1\br_op__insn_type$3$next[6:0]$8832
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $1\br_op__is_32bit$9$next[0:0]$8833
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $1\br_op__lk$8$next[0:0]$8834
- attribute \src "libresoc.v:164574.3-164592.6"
- wire width 64 $1\fast1$10$next[63:0]$8840
- attribute \src "libresoc.v:164574.3-164592.6"
- wire $1\fast1_ok$next[0:0]$8841
- attribute \src "libresoc.v:164149.7-164149.22"
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 64 $1\br_op__cia$2$next[63:0]$8775
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 14 $1\br_op__fn_unit$4$next[13:0]$8776
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8777
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $1\br_op__imm_data__ok$7$next[0:0]$8778
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 32 $1\br_op__insn$5$next[31:0]$8779
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 7 $1\br_op__insn_type$3$next[6:0]$8780
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $1\br_op__is_32bit$9$next[0:0]$8781
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $1\br_op__lk$8$next[0:0]$8782
+ attribute \src "libresoc.v:164238.3-164256.6"
+ wire width 64 $1\fast1$10$next[63:0]$8788
+ attribute \src "libresoc.v:164238.3-164256.6"
+ wire $1\fast1_ok$next[0:0]$8789
+ attribute \src "libresoc.v:163813.7-163813.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:164593.3-164611.6"
- wire width 64 $1\fast2$11$next[63:0]$8846
- attribute \src "libresoc.v:164593.3-164611.6"
- wire $1\fast2_ok$next[0:0]$8847
- attribute \src "libresoc.v:164165.7-164165.22"
+ attribute \src "libresoc.v:164257.3-164275.6"
+ wire width 64 $1\fast2$11$next[63:0]$8794
+ attribute \src "libresoc.v:164257.3-164275.6"
+ wire $1\fast2_ok$next[0:0]$8795
+ attribute \src "libresoc.v:163829.7-163829.22"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:164533.3-164545.6"
- wire width 2 $1\muxid$1$next[1:0]$8817
- attribute \src "libresoc.v:164612.3-164630.6"
- wire width 64 $1\nia$next[63:0]$8852
- attribute \src "libresoc.v:164421.14-164421.40"
+ attribute \src "libresoc.v:164197.3-164209.6"
+ wire width 2 $1\muxid$1$next[1:0]$8765
+ attribute \src "libresoc.v:164276.3-164294.6"
+ wire width 64 $1\nia$next[63:0]$8800
+ attribute \src "libresoc.v:164085.14-164085.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:164612.3-164630.6"
- wire $1\nia_ok$next[0:0]$8853
- attribute \src "libresoc.v:164428.7-164428.20"
+ attribute \src "libresoc.v:164276.3-164294.6"
+ wire $1\nia_ok$next[0:0]$8801
+ attribute \src "libresoc.v:164092.7-164092.20"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:164515.3-164532.6"
- wire $1\r_busy$next[0:0]$8813
- attribute \src "libresoc.v:164442.7-164442.20"
+ attribute \src "libresoc.v:164179.3-164196.6"
+ wire $1\r_busy$next[0:0]$8761
+ attribute \src "libresoc.v:164106.7-164106.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:164546.3-164573.6"
- wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8835
- attribute \src "libresoc.v:164546.3-164573.6"
- wire $2\br_op__imm_data__ok$7$next[0:0]$8836
- attribute \src "libresoc.v:164574.3-164592.6"
- wire $2\fast1_ok$next[0:0]$8842
- attribute \src "libresoc.v:164593.3-164611.6"
- wire $2\fast2_ok$next[0:0]$8848
- attribute \src "libresoc.v:164612.3-164630.6"
- wire $2\nia_ok$next[0:0]$8854
- attribute \src "libresoc.v:164515.3-164532.6"
- wire $2\r_busy$next[0:0]$8814
- attribute \src "libresoc.v:164445.18-164445.118"
- wire $and$libresoc.v:164445$8783_Y
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8783
+ attribute \src "libresoc.v:164210.3-164237.6"
+ wire $2\br_op__imm_data__ok$7$next[0:0]$8784
+ attribute \src "libresoc.v:164238.3-164256.6"
+ wire $2\fast1_ok$next[0:0]$8790
+ attribute \src "libresoc.v:164257.3-164275.6"
+ wire $2\fast2_ok$next[0:0]$8796
+ attribute \src "libresoc.v:164276.3-164294.6"
+ wire $2\nia_ok$next[0:0]$8802
+ attribute \src "libresoc.v:164179.3-164196.6"
+ wire $2\r_busy$next[0:0]$8762
+ attribute \src "libresoc.v:164109.18-164109.118"
+ wire $and$libresoc.v:164109$8731_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire output 25 \br_op__lk$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 15 \cr_a
wire \fast2_ok$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast2_ok$next
- attribute \src "libresoc.v:163787.7-163787.15"
+ attribute \src "libresoc.v:163451.7-163451.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 64 \main_br_op__cia
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire \r_busy$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:164445$8783
+ cell $and $and$libresoc.v:164109$8731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$23
connect \B \p_ready_o
- connect \Y $and$libresoc.v:164445$8783_Y
+ connect \Y $and$libresoc.v:164109$8731_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164478.13-164506.4"
+ attribute \src "libresoc.v:164142.13-164170.4"
cell \main$22 \main
connect \br_op__cia \main_br_op__cia
connect \br_op__cia$2 \main_br_op__cia$13
connect \nia_ok \main_nia_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164507.10-164510.4"
+ attribute \src "libresoc.v:164171.10-164174.4"
cell \n$21 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164511.10-164514.4"
+ attribute \src "libresoc.v:164175.10-164178.4"
cell \p$20 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:163787.7-163787.20"
- process $proc$libresoc.v:163787$8855
+ attribute \src "libresoc.v:163451.7-163451.20"
+ process $proc$libresoc.v:163451$8803
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:163794.14-163794.51"
- process $proc$libresoc.v:163794$8856
+ attribute \src "libresoc.v:163458.14-163458.51"
+ process $proc$libresoc.v:163458$8804
assign { } { }
- assign $0\br_op__cia$2[63:0]$8857 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\br_op__cia$2[63:0]$8805 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \br_op__cia$2 $0\br_op__cia$2[63:0]$8857
+ update \br_op__cia$2 $0\br_op__cia$2[63:0]$8805
end
- attribute \src "libresoc.v:163850.14-163850.43"
- process $proc$libresoc.v:163850$8858
+ attribute \src "libresoc.v:163514.14-163514.43"
+ process $proc$libresoc.v:163514$8806
assign { } { }
- assign $0\br_op__fn_unit$4[13:0]$8859 14'00000000000000
+ assign $0\br_op__fn_unit$4[13:0]$8807 14'00000000000000
sync always
sync init
- update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8859
+ update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8807
end
- attribute \src "libresoc.v:163859.14-163859.62"
- process $proc$libresoc.v:163859$8860
+ attribute \src "libresoc.v:163523.14-163523.62"
+ process $proc$libresoc.v:163523$8808
assign { } { }
- assign $0\br_op__imm_data__data$6[63:0]$8861 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\br_op__imm_data__data$6[63:0]$8809 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8861
+ update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8809
end
- attribute \src "libresoc.v:163868.7-163868.37"
- process $proc$libresoc.v:163868$8862
+ attribute \src "libresoc.v:163532.7-163532.37"
+ process $proc$libresoc.v:163532$8810
assign { } { }
- assign $0\br_op__imm_data__ok$7[0:0]$8863 1'0
+ assign $0\br_op__imm_data__ok$7[0:0]$8811 1'0
sync always
sync init
- update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8863
+ update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8811
end
- attribute \src "libresoc.v:163877.14-163877.37"
- process $proc$libresoc.v:163877$8864
+ attribute \src "libresoc.v:163541.14-163541.37"
+ process $proc$libresoc.v:163541$8812
assign { } { }
- assign $0\br_op__insn$5[31:0]$8865 0
+ assign $0\br_op__insn$5[31:0]$8813 0
sync always
sync init
- update \br_op__insn$5 $0\br_op__insn$5[31:0]$8865
+ update \br_op__insn$5 $0\br_op__insn$5[31:0]$8813
end
- attribute \src "libresoc.v:164111.13-164111.41"
- process $proc$libresoc.v:164111$8866
+ attribute \src "libresoc.v:163775.13-163775.41"
+ process $proc$libresoc.v:163775$8814
assign { } { }
- assign $0\br_op__insn_type$3[6:0]$8867 7'0000000
+ assign $0\br_op__insn_type$3[6:0]$8815 7'0000000
sync always
sync init
- update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8867
+ update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8815
end
- attribute \src "libresoc.v:164120.7-164120.33"
- process $proc$libresoc.v:164120$8868
+ attribute \src "libresoc.v:163784.7-163784.33"
+ process $proc$libresoc.v:163784$8816
assign { } { }
- assign $0\br_op__is_32bit$9[0:0]$8869 1'0
+ assign $0\br_op__is_32bit$9[0:0]$8817 1'0
sync always
sync init
- update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8869
+ update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8817
end
- attribute \src "libresoc.v:164129.7-164129.27"
- process $proc$libresoc.v:164129$8870
+ attribute \src "libresoc.v:163793.7-163793.27"
+ process $proc$libresoc.v:163793$8818
assign { } { }
- assign $0\br_op__lk$8[0:0]$8871 1'0
+ assign $0\br_op__lk$8[0:0]$8819 1'0
sync always
sync init
- update \br_op__lk$8 $0\br_op__lk$8[0:0]$8871
+ update \br_op__lk$8 $0\br_op__lk$8[0:0]$8819
end
- attribute \src "libresoc.v:164142.14-164142.47"
- process $proc$libresoc.v:164142$8872
+ attribute \src "libresoc.v:163806.14-163806.47"
+ process $proc$libresoc.v:163806$8820
assign { } { }
- assign $0\fast1$10[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$10[63:0]$8821 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$10 $0\fast1$10[63:0]$8873
+ update \fast1$10 $0\fast1$10[63:0]$8821
end
- attribute \src "libresoc.v:164149.7-164149.22"
- process $proc$libresoc.v:164149$8874
+ attribute \src "libresoc.v:163813.7-163813.22"
+ process $proc$libresoc.v:163813$8822
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:164158.14-164158.47"
- process $proc$libresoc.v:164158$8875
+ attribute \src "libresoc.v:163822.14-163822.47"
+ process $proc$libresoc.v:163822$8823
assign { } { }
- assign $0\fast2$11[63:0]$8876 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast2$11[63:0]$8824 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast2$11 $0\fast2$11[63:0]$8876
+ update \fast2$11 $0\fast2$11[63:0]$8824
end
- attribute \src "libresoc.v:164165.7-164165.22"
- process $proc$libresoc.v:164165$8877
+ attribute \src "libresoc.v:163829.7-163829.22"
+ process $proc$libresoc.v:163829$8825
assign { } { }
assign $1\fast2_ok[0:0] 1'0
sync always
sync init
update \fast2_ok $1\fast2_ok[0:0]
end
- attribute \src "libresoc.v:164408.13-164408.29"
- process $proc$libresoc.v:164408$8878
+ attribute \src "libresoc.v:164072.13-164072.29"
+ process $proc$libresoc.v:164072$8826
assign { } { }
- assign $0\muxid$1[1:0]$8879 2'00
+ assign $0\muxid$1[1:0]$8827 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8879
+ update \muxid$1 $0\muxid$1[1:0]$8827
end
- attribute \src "libresoc.v:164421.14-164421.40"
- process $proc$libresoc.v:164421$8880
+ attribute \src "libresoc.v:164085.14-164085.40"
+ process $proc$libresoc.v:164085$8828
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:164428.7-164428.20"
- process $proc$libresoc.v:164428$8881
+ attribute \src "libresoc.v:164092.7-164092.20"
+ process $proc$libresoc.v:164092$8829
assign { } { }
assign $1\nia_ok[0:0] 1'0
sync always
sync init
update \nia_ok $1\nia_ok[0:0]
end
- attribute \src "libresoc.v:164442.7-164442.20"
- process $proc$libresoc.v:164442$8882
+ attribute \src "libresoc.v:164106.7-164106.20"
+ process $proc$libresoc.v:164106$8830
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:164446.3-164447.23"
- process $proc$libresoc.v:164446$8784
+ attribute \src "libresoc.v:164110.3-164111.23"
+ process $proc$libresoc.v:164110$8732
assign { } { }
assign $0\nia[63:0] \nia$next
sync posedge \coresync_clk
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:164448.3-164449.29"
- process $proc$libresoc.v:164448$8785
+ attribute \src "libresoc.v:164112.3-164113.29"
+ process $proc$libresoc.v:164112$8733
assign { } { }
assign $0\nia_ok[0:0] \nia_ok$next
sync posedge \coresync_clk
update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:164450.3-164451.35"
- process $proc$libresoc.v:164450$8786
+ attribute \src "libresoc.v:164114.3-164115.35"
+ process $proc$libresoc.v:164114$8734
assign { } { }
- assign $0\fast2$11[63:0]$8787 \fast2$11$next
+ assign $0\fast2$11[63:0]$8735 \fast2$11$next
sync posedge \coresync_clk
- update \fast2$11 $0\fast2$11[63:0]$8787
+ update \fast2$11 $0\fast2$11[63:0]$8735
end
- attribute \src "libresoc.v:164452.3-164453.33"
- process $proc$libresoc.v:164452$8788
+ attribute \src "libresoc.v:164116.3-164117.33"
+ process $proc$libresoc.v:164116$8736
assign { } { }
assign $0\fast2_ok[0:0] \fast2_ok$next
sync posedge \coresync_clk
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:164454.3-164455.35"
- process $proc$libresoc.v:164454$8789
+ attribute \src "libresoc.v:164118.3-164119.35"
+ process $proc$libresoc.v:164118$8737
assign { } { }
- assign $0\fast1$10[63:0]$8790 \fast1$10$next
+ assign $0\fast1$10[63:0]$8738 \fast1$10$next
sync posedge \coresync_clk
- update \fast1$10 $0\fast1$10[63:0]$8790
+ update \fast1$10 $0\fast1$10[63:0]$8738
end
- attribute \src "libresoc.v:164456.3-164457.33"
- process $proc$libresoc.v:164456$8791
+ attribute \src "libresoc.v:164120.3-164121.33"
+ process $proc$libresoc.v:164120$8739
assign { } { }
assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:164458.3-164459.43"
- process $proc$libresoc.v:164458$8792
+ attribute \src "libresoc.v:164122.3-164123.43"
+ process $proc$libresoc.v:164122$8740
assign { } { }
- assign $0\br_op__cia$2[63:0]$8793 \br_op__cia$2$next
+ assign $0\br_op__cia$2[63:0]$8741 \br_op__cia$2$next
sync posedge \coresync_clk
- update \br_op__cia$2 $0\br_op__cia$2[63:0]$8793
+ update \br_op__cia$2 $0\br_op__cia$2[63:0]$8741
end
- attribute \src "libresoc.v:164460.3-164461.55"
- process $proc$libresoc.v:164460$8794
+ attribute \src "libresoc.v:164124.3-164125.55"
+ process $proc$libresoc.v:164124$8742
assign { } { }
- assign $0\br_op__insn_type$3[6:0]$8795 \br_op__insn_type$3$next
+ assign $0\br_op__insn_type$3[6:0]$8743 \br_op__insn_type$3$next
sync posedge \coresync_clk
- update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8795
+ update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8743
end
- attribute \src "libresoc.v:164462.3-164463.51"
- process $proc$libresoc.v:164462$8796
+ attribute \src "libresoc.v:164126.3-164127.51"
+ process $proc$libresoc.v:164126$8744
assign { } { }
- assign $0\br_op__fn_unit$4[13:0]$8797 \br_op__fn_unit$4$next
+ assign $0\br_op__fn_unit$4[13:0]$8745 \br_op__fn_unit$4$next
sync posedge \coresync_clk
- update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8797
+ update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8745
end
- attribute \src "libresoc.v:164464.3-164465.45"
- process $proc$libresoc.v:164464$8798
+ attribute \src "libresoc.v:164128.3-164129.45"
+ process $proc$libresoc.v:164128$8746
assign { } { }
- assign $0\br_op__insn$5[31:0]$8799 \br_op__insn$5$next
+ assign $0\br_op__insn$5[31:0]$8747 \br_op__insn$5$next
sync posedge \coresync_clk
- update \br_op__insn$5 $0\br_op__insn$5[31:0]$8799
+ update \br_op__insn$5 $0\br_op__insn$5[31:0]$8747
end
- attribute \src "libresoc.v:164466.3-164467.65"
- process $proc$libresoc.v:164466$8800
+ attribute \src "libresoc.v:164130.3-164131.65"
+ process $proc$libresoc.v:164130$8748
assign { } { }
- assign $0\br_op__imm_data__data$6[63:0]$8801 \br_op__imm_data__data$6$next
+ assign $0\br_op__imm_data__data$6[63:0]$8749 \br_op__imm_data__data$6$next
sync posedge \coresync_clk
- update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8801
+ update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8749
end
- attribute \src "libresoc.v:164468.3-164469.61"
- process $proc$libresoc.v:164468$8802
+ attribute \src "libresoc.v:164132.3-164133.61"
+ process $proc$libresoc.v:164132$8750
assign { } { }
- assign $0\br_op__imm_data__ok$7[0:0]$8803 \br_op__imm_data__ok$7$next
+ assign $0\br_op__imm_data__ok$7[0:0]$8751 \br_op__imm_data__ok$7$next
sync posedge \coresync_clk
- update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8803
+ update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8751
end
- attribute \src "libresoc.v:164470.3-164471.41"
- process $proc$libresoc.v:164470$8804
+ attribute \src "libresoc.v:164134.3-164135.41"
+ process $proc$libresoc.v:164134$8752
assign { } { }
- assign $0\br_op__lk$8[0:0]$8805 \br_op__lk$8$next
+ assign $0\br_op__lk$8[0:0]$8753 \br_op__lk$8$next
sync posedge \coresync_clk
- update \br_op__lk$8 $0\br_op__lk$8[0:0]$8805
+ update \br_op__lk$8 $0\br_op__lk$8[0:0]$8753
end
- attribute \src "libresoc.v:164472.3-164473.53"
- process $proc$libresoc.v:164472$8806
+ attribute \src "libresoc.v:164136.3-164137.53"
+ process $proc$libresoc.v:164136$8754
assign { } { }
- assign $0\br_op__is_32bit$9[0:0]$8807 \br_op__is_32bit$9$next
+ assign $0\br_op__is_32bit$9[0:0]$8755 \br_op__is_32bit$9$next
sync posedge \coresync_clk
- update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8807
+ update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8755
end
- attribute \src "libresoc.v:164474.3-164475.33"
- process $proc$libresoc.v:164474$8808
+ attribute \src "libresoc.v:164138.3-164139.33"
+ process $proc$libresoc.v:164138$8756
assign { } { }
- assign $0\muxid$1[1:0]$8809 \muxid$1$next
+ assign $0\muxid$1[1:0]$8757 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8809
+ update \muxid$1 $0\muxid$1[1:0]$8757
end
- attribute \src "libresoc.v:164476.3-164477.29"
- process $proc$libresoc.v:164476$8810
+ attribute \src "libresoc.v:164140.3-164141.29"
+ process $proc$libresoc.v:164140$8758
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:164515.3-164532.6"
- process $proc$libresoc.v:164515$8811
+ attribute \src "libresoc.v:164179.3-164196.6"
+ process $proc$libresoc.v:164179$8759
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8812 $2\r_busy$next[0:0]$8814
- attribute \src "libresoc.v:164516.5-164516.29"
+ assign $0\r_busy$next[0:0]$8760 $2\r_busy$next[0:0]$8762
+ attribute \src "libresoc.v:164180.5-164180.29"
switch \initial
- attribute \src "libresoc.v:164516.9-164516.17"
+ attribute \src "libresoc.v:164180.9-164180.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8813 1'1
+ assign $1\r_busy$next[0:0]$8761 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8813 1'0
+ assign $1\r_busy$next[0:0]$8761 1'0
case
- assign $1\r_busy$next[0:0]$8813 \r_busy
+ assign $1\r_busy$next[0:0]$8761 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8814 1'0
+ assign $2\r_busy$next[0:0]$8762 1'0
case
- assign $2\r_busy$next[0:0]$8814 $1\r_busy$next[0:0]$8813
+ assign $2\r_busy$next[0:0]$8762 $1\r_busy$next[0:0]$8761
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8812
+ update \r_busy$next $0\r_busy$next[0:0]$8760
end
- attribute \src "libresoc.v:164533.3-164545.6"
- process $proc$libresoc.v:164533$8815
+ attribute \src "libresoc.v:164197.3-164209.6"
+ process $proc$libresoc.v:164197$8763
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8816 $1\muxid$1$next[1:0]$8817
- attribute \src "libresoc.v:164534.5-164534.29"
+ assign $0\muxid$1$next[1:0]$8764 $1\muxid$1$next[1:0]$8765
+ attribute \src "libresoc.v:164198.5-164198.29"
switch \initial
- attribute \src "libresoc.v:164534.9-164534.17"
+ attribute \src "libresoc.v:164198.9-164198.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8817 \muxid$26
+ assign $1\muxid$1$next[1:0]$8765 \muxid$26
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8817 \muxid$26
+ assign $1\muxid$1$next[1:0]$8765 \muxid$26
case
- assign $1\muxid$1$next[1:0]$8817 \muxid$1
+ assign $1\muxid$1$next[1:0]$8765 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8816
+ update \muxid$1$next $0\muxid$1$next[1:0]$8764
end
- attribute \src "libresoc.v:164546.3-164573.6"
- process $proc$libresoc.v:164546$8818
+ attribute \src "libresoc.v:164210.3-164237.6"
+ process $proc$libresoc.v:164210$8766
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\br_op__cia$2$next[63:0]$8819 $1\br_op__cia$2$next[63:0]$8827
- assign $0\br_op__fn_unit$4$next[13:0]$8820 $1\br_op__fn_unit$4$next[13:0]$8828
+ assign $0\br_op__cia$2$next[63:0]$8767 $1\br_op__cia$2$next[63:0]$8775
+ assign $0\br_op__fn_unit$4$next[13:0]$8768 $1\br_op__fn_unit$4$next[13:0]$8776
assign { } { }
assign { } { }
- assign $0\br_op__insn$5$next[31:0]$8823 $1\br_op__insn$5$next[31:0]$8831
- assign $0\br_op__insn_type$3$next[6:0]$8824 $1\br_op__insn_type$3$next[6:0]$8832
- assign $0\br_op__is_32bit$9$next[0:0]$8825 $1\br_op__is_32bit$9$next[0:0]$8833
- assign $0\br_op__lk$8$next[0:0]$8826 $1\br_op__lk$8$next[0:0]$8834
- assign $0\br_op__imm_data__data$6$next[63:0]$8821 $2\br_op__imm_data__data$6$next[63:0]$8835
- assign $0\br_op__imm_data__ok$7$next[0:0]$8822 $2\br_op__imm_data__ok$7$next[0:0]$8836
- attribute \src "libresoc.v:164547.5-164547.29"
+ assign $0\br_op__insn$5$next[31:0]$8771 $1\br_op__insn$5$next[31:0]$8779
+ assign $0\br_op__insn_type$3$next[6:0]$8772 $1\br_op__insn_type$3$next[6:0]$8780
+ assign $0\br_op__is_32bit$9$next[0:0]$8773 $1\br_op__is_32bit$9$next[0:0]$8781
+ assign $0\br_op__lk$8$next[0:0]$8774 $1\br_op__lk$8$next[0:0]$8782
+ assign $0\br_op__imm_data__data$6$next[63:0]$8769 $2\br_op__imm_data__data$6$next[63:0]$8783
+ assign $0\br_op__imm_data__ok$7$next[0:0]$8770 $2\br_op__imm_data__ok$7$next[0:0]$8784
+ attribute \src "libresoc.v:164211.5-164211.29"
switch \initial
- attribute \src "libresoc.v:164547.9-164547.17"
+ attribute \src "libresoc.v:164211.9-164211.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\br_op__is_32bit$9$next[0:0]$8833 $1\br_op__lk$8$next[0:0]$8834 $1\br_op__imm_data__ok$7$next[0:0]$8830 $1\br_op__imm_data__data$6$next[63:0]$8829 $1\br_op__insn$5$next[31:0]$8831 $1\br_op__fn_unit$4$next[13:0]$8828 $1\br_op__insn_type$3$next[6:0]$8832 $1\br_op__cia$2$next[63:0]$8827 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
+ assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\br_op__is_32bit$9$next[0:0]$8833 $1\br_op__lk$8$next[0:0]$8834 $1\br_op__imm_data__ok$7$next[0:0]$8830 $1\br_op__imm_data__data$6$next[63:0]$8829 $1\br_op__insn$5$next[31:0]$8831 $1\br_op__fn_unit$4$next[13:0]$8828 $1\br_op__insn_type$3$next[6:0]$8832 $1\br_op__cia$2$next[63:0]$8827 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
+ assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
case
- assign $1\br_op__cia$2$next[63:0]$8827 \br_op__cia$2
- assign $1\br_op__fn_unit$4$next[13:0]$8828 \br_op__fn_unit$4
- assign $1\br_op__imm_data__data$6$next[63:0]$8829 \br_op__imm_data__data$6
- assign $1\br_op__imm_data__ok$7$next[0:0]$8830 \br_op__imm_data__ok$7
- assign $1\br_op__insn$5$next[31:0]$8831 \br_op__insn$5
- assign $1\br_op__insn_type$3$next[6:0]$8832 \br_op__insn_type$3
- assign $1\br_op__is_32bit$9$next[0:0]$8833 \br_op__is_32bit$9
- assign $1\br_op__lk$8$next[0:0]$8834 \br_op__lk$8
+ assign $1\br_op__cia$2$next[63:0]$8775 \br_op__cia$2
+ assign $1\br_op__fn_unit$4$next[13:0]$8776 \br_op__fn_unit$4
+ assign $1\br_op__imm_data__data$6$next[63:0]$8777 \br_op__imm_data__data$6
+ assign $1\br_op__imm_data__ok$7$next[0:0]$8778 \br_op__imm_data__ok$7
+ assign $1\br_op__insn$5$next[31:0]$8779 \br_op__insn$5
+ assign $1\br_op__insn_type$3$next[6:0]$8780 \br_op__insn_type$3
+ assign $1\br_op__is_32bit$9$next[0:0]$8781 \br_op__is_32bit$9
+ assign $1\br_op__lk$8$next[0:0]$8782 \br_op__lk$8
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
case 1'1
assign { } { }
assign { } { }
- assign $2\br_op__imm_data__data$6$next[63:0]$8835 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\br_op__imm_data__ok$7$next[0:0]$8836 1'0
+ assign $2\br_op__imm_data__data$6$next[63:0]$8783 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\br_op__imm_data__ok$7$next[0:0]$8784 1'0
case
- assign $2\br_op__imm_data__data$6$next[63:0]$8835 $1\br_op__imm_data__data$6$next[63:0]$8829
- assign $2\br_op__imm_data__ok$7$next[0:0]$8836 $1\br_op__imm_data__ok$7$next[0:0]$8830
+ assign $2\br_op__imm_data__data$6$next[63:0]$8783 $1\br_op__imm_data__data$6$next[63:0]$8777
+ assign $2\br_op__imm_data__ok$7$next[0:0]$8784 $1\br_op__imm_data__ok$7$next[0:0]$8778
end
sync always
- update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8819
- update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8820
- update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8821
- update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8822
- update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8823
- update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8824
- update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8825
- update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8826
+ update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8767
+ update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8768
+ update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8769
+ update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8770
+ update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8771
+ update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8772
+ update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8773
+ update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8774
end
- attribute \src "libresoc.v:164574.3-164592.6"
- process $proc$libresoc.v:164574$8837
+ attribute \src "libresoc.v:164238.3-164256.6"
+ process $proc$libresoc.v:164238$8785
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$10$next[63:0]$8838 $1\fast1$10$next[63:0]$8840
+ assign $0\fast1$10$next[63:0]$8786 $1\fast1$10$next[63:0]$8788
assign { } { }
- assign $0\fast1_ok$next[0:0]$8839 $2\fast1_ok$next[0:0]$8842
- attribute \src "libresoc.v:164575.5-164575.29"
+ assign $0\fast1_ok$next[0:0]$8787 $2\fast1_ok$next[0:0]$8790
+ attribute \src "libresoc.v:164239.5-164239.29"
switch \initial
- attribute \src "libresoc.v:164575.9-164575.17"
+ attribute \src "libresoc.v:164239.9-164239.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8841 $1\fast1$10$next[63:0]$8840 } { \fast1_ok$36 \fast1$35 }
+ assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8841 $1\fast1$10$next[63:0]$8840 } { \fast1_ok$36 \fast1$35 }
+ assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 }
case
- assign $1\fast1$10$next[63:0]$8840 \fast1$10
- assign $1\fast1_ok$next[0:0]$8841 \fast1_ok
+ assign $1\fast1$10$next[63:0]$8788 \fast1$10
+ assign $1\fast1_ok$next[0:0]$8789 \fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$8842 1'0
+ assign $2\fast1_ok$next[0:0]$8790 1'0
case
- assign $2\fast1_ok$next[0:0]$8842 $1\fast1_ok$next[0:0]$8841
+ assign $2\fast1_ok$next[0:0]$8790 $1\fast1_ok$next[0:0]$8789
end
sync always
- update \fast1$10$next $0\fast1$10$next[63:0]$8838
- update \fast1_ok$next $0\fast1_ok$next[0:0]$8839
+ update \fast1$10$next $0\fast1$10$next[63:0]$8786
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$8787
end
- attribute \src "libresoc.v:164593.3-164611.6"
- process $proc$libresoc.v:164593$8843
+ attribute \src "libresoc.v:164257.3-164275.6"
+ process $proc$libresoc.v:164257$8791
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast2$11$next[63:0]$8844 $1\fast2$11$next[63:0]$8846
+ assign $0\fast2$11$next[63:0]$8792 $1\fast2$11$next[63:0]$8794
assign { } { }
- assign $0\fast2_ok$next[0:0]$8845 $2\fast2_ok$next[0:0]$8848
- attribute \src "libresoc.v:164594.5-164594.29"
+ assign $0\fast2_ok$next[0:0]$8793 $2\fast2_ok$next[0:0]$8796
+ attribute \src "libresoc.v:164258.5-164258.29"
switch \initial
- attribute \src "libresoc.v:164594.9-164594.17"
+ attribute \src "libresoc.v:164258.9-164258.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$8847 $1\fast2$11$next[63:0]$8846 } { \fast2_ok$38 \fast2$37 }
+ assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$8847 $1\fast2$11$next[63:0]$8846 } { \fast2_ok$38 \fast2$37 }
+ assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 }
case
- assign $1\fast2$11$next[63:0]$8846 \fast2$11
- assign $1\fast2_ok$next[0:0]$8847 \fast2_ok
+ assign $1\fast2$11$next[63:0]$8794 \fast2$11
+ assign $1\fast2_ok$next[0:0]$8795 \fast2_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast2_ok$next[0:0]$8848 1'0
+ assign $2\fast2_ok$next[0:0]$8796 1'0
case
- assign $2\fast2_ok$next[0:0]$8848 $1\fast2_ok$next[0:0]$8847
+ assign $2\fast2_ok$next[0:0]$8796 $1\fast2_ok$next[0:0]$8795
end
sync always
- update \fast2$11$next $0\fast2$11$next[63:0]$8844
- update \fast2_ok$next $0\fast2_ok$next[0:0]$8845
+ update \fast2$11$next $0\fast2$11$next[63:0]$8792
+ update \fast2_ok$next $0\fast2_ok$next[0:0]$8793
end
- attribute \src "libresoc.v:164612.3-164630.6"
- process $proc$libresoc.v:164612$8849
+ attribute \src "libresoc.v:164276.3-164294.6"
+ process $proc$libresoc.v:164276$8797
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$8850 $1\nia$next[63:0]$8852
+ assign $0\nia$next[63:0]$8798 $1\nia$next[63:0]$8800
assign { } { }
- assign $0\nia_ok$next[0:0]$8851 $2\nia_ok$next[0:0]$8854
- attribute \src "libresoc.v:164613.5-164613.29"
+ assign $0\nia_ok$next[0:0]$8799 $2\nia_ok$next[0:0]$8802
+ attribute \src "libresoc.v:164277.5-164277.29"
switch \initial
- attribute \src "libresoc.v:164613.9-164613.17"
+ attribute \src "libresoc.v:164277.9-164277.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$8853 $1\nia$next[63:0]$8852 } { \nia_ok$40 \nia$39 }
+ assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$8853 $1\nia$next[63:0]$8852 } { \nia_ok$40 \nia$39 }
+ assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 }
case
- assign $1\nia$next[63:0]$8852 \nia
- assign $1\nia_ok$next[0:0]$8853 \nia_ok
+ assign $1\nia$next[63:0]$8800 \nia
+ assign $1\nia_ok$next[0:0]$8801 \nia_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\nia_ok$next[0:0]$8854 1'0
+ assign $2\nia_ok$next[0:0]$8802 1'0
case
- assign $2\nia_ok$next[0:0]$8854 $1\nia_ok$next[0:0]$8853
+ assign $2\nia_ok$next[0:0]$8802 $1\nia_ok$next[0:0]$8801
end
sync always
- update \nia$next $0\nia$next[63:0]$8850
- update \nia_ok$next $0\nia_ok$next[0:0]$8851
+ update \nia$next $0\nia$next[63:0]$8798
+ update \nia_ok$next $0\nia_ok$next[0:0]$8799
end
- connect \$24 $and$libresoc.v:164445$8783_Y
+ connect \$24 $and$libresoc.v:164109$8731_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia }
connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:164650.1-165580.10"
+attribute \src "libresoc.v:164314.1-165244.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe"
attribute \generator "nMigen"
module \pipe$64
- attribute \src "libresoc.v:165483.3-165501.6"
- wire width 64 $0\fast1$7$next[63:0]$8942
- attribute \src "libresoc.v:165336.3-165337.33"
- wire width 64 $0\fast1$7[63:0]$8894
- attribute \src "libresoc.v:164664.14-164664.46"
- wire width 64 $0\fast1$7[63:0]$8966
- attribute \src "libresoc.v:165483.3-165501.6"
- wire $0\fast1_ok$next[0:0]$8941
- attribute \src "libresoc.v:165338.3-165339.33"
+ attribute \src "libresoc.v:165147.3-165165.6"
+ wire width 64 $0\fast1$7$next[63:0]$8890
+ attribute \src "libresoc.v:165000.3-165001.33"
+ wire width 64 $0\fast1$7[63:0]$8842
+ attribute \src "libresoc.v:164328.14-164328.46"
+ wire width 64 $0\fast1$7[63:0]$8914
+ attribute \src "libresoc.v:165147.3-165165.6"
+ wire $0\fast1_ok$next[0:0]$8889
+ attribute \src "libresoc.v:165002.3-165003.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:164651.7-164651.20"
+ attribute \src "libresoc.v:164315.7-164315.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:165416.3-165428.6"
- wire width 2 $0\muxid$1$next[1:0]$8917
- attribute \src "libresoc.v:165356.3-165357.33"
- wire width 2 $0\muxid$1[1:0]$8910
- attribute \src "libresoc.v:164678.13-164678.29"
- wire width 2 $0\muxid$1[1:0]$8969
- attribute \src "libresoc.v:165445.3-165463.6"
- wire width 64 $0\o$next[63:0]$8929
- attribute \src "libresoc.v:165344.3-165345.19"
+ attribute \src "libresoc.v:165080.3-165092.6"
+ wire width 2 $0\muxid$1$next[1:0]$8865
+ attribute \src "libresoc.v:165020.3-165021.33"
+ wire width 2 $0\muxid$1[1:0]$8858
+ attribute \src "libresoc.v:164342.13-164342.29"
+ wire width 2 $0\muxid$1[1:0]$8917
+ attribute \src "libresoc.v:165109.3-165127.6"
+ wire width 64 $0\o$next[63:0]$8877
+ attribute \src "libresoc.v:165008.3-165009.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:165445.3-165463.6"
- wire $0\o_ok$next[0:0]$8930
- attribute \src "libresoc.v:165346.3-165347.25"
+ attribute \src "libresoc.v:165109.3-165127.6"
+ wire $0\o_ok$next[0:0]$8878
+ attribute \src "libresoc.v:165010.3-165011.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:165398.3-165415.6"
- wire $0\r_busy$next[0:0]$8913
- attribute \src "libresoc.v:165358.3-165359.29"
+ attribute \src "libresoc.v:165062.3-165079.6"
+ wire $0\r_busy$next[0:0]$8861
+ attribute \src "libresoc.v:165022.3-165023.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:165464.3-165482.6"
- wire width 64 $0\spr1$6$next[63:0]$8935
- attribute \src "libresoc.v:165340.3-165341.31"
- wire width 64 $0\spr1$6[63:0]$8897
- attribute \src "libresoc.v:164723.14-164723.45"
- wire width 64 $0\spr1$6[63:0]$8974
- attribute \src "libresoc.v:165464.3-165482.6"
- wire $0\spr1_ok$next[0:0]$8936
- attribute \src "libresoc.v:165342.3-165343.31"
+ attribute \src "libresoc.v:165128.3-165146.6"
+ wire width 64 $0\spr1$6$next[63:0]$8883
+ attribute \src "libresoc.v:165004.3-165005.31"
+ wire width 64 $0\spr1$6[63:0]$8845
+ attribute \src "libresoc.v:164387.14-164387.45"
+ wire width 64 $0\spr1$6[63:0]$8922
+ attribute \src "libresoc.v:165128.3-165146.6"
+ wire $0\spr1_ok$next[0:0]$8884
+ attribute \src "libresoc.v:165006.3-165007.31"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8920
- attribute \src "libresoc.v:165350.3-165351.53"
- wire width 14 $0\spr_op__fn_unit$3[13:0]$8904
- attribute \src "libresoc.v:165020.14-165020.44"
- wire width 14 $0\spr_op__fn_unit$3[13:0]$8977
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 32 $0\spr_op__insn$4$next[31:0]$8921
- attribute \src "libresoc.v:165352.3-165353.47"
- wire width 32 $0\spr_op__insn$4[31:0]$8906
- attribute \src "libresoc.v:165029.14-165029.38"
- wire width 32 $0\spr_op__insn$4[31:0]$8979
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 7 $0\spr_op__insn_type$2$next[6:0]$8922
- attribute \src "libresoc.v:165348.3-165349.57"
- wire width 7 $0\spr_op__insn_type$2[6:0]$8902
- attribute \src "libresoc.v:165186.13-165186.42"
- wire width 7 $0\spr_op__insn_type$2[6:0]$8981
- attribute \src "libresoc.v:165429.3-165444.6"
- wire $0\spr_op__is_32bit$5$next[0:0]$8923
- attribute \src "libresoc.v:165354.3-165355.55"
- wire $0\spr_op__is_32bit$5[0:0]$8908
- attribute \src "libresoc.v:165272.7-165272.34"
- wire $0\spr_op__is_32bit$5[0:0]$8983
- attribute \src "libresoc.v:165540.3-165558.6"
- wire width 2 $0\xer_ca$10$next[1:0]$8959
- attribute \src "libresoc.v:165324.3-165325.37"
- wire width 2 $0\xer_ca$10[1:0]$8885
- attribute \src "libresoc.v:165279.13-165279.31"
- wire width 2 $0\xer_ca$10[1:0]$8985
- attribute \src "libresoc.v:165540.3-165558.6"
- wire $0\xer_ca_ok$next[0:0]$8960
- attribute \src "libresoc.v:165326.3-165327.35"
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8868
+ attribute \src "libresoc.v:165014.3-165015.53"
+ wire width 14 $0\spr_op__fn_unit$3[13:0]$8852
+ attribute \src "libresoc.v:164684.14-164684.44"
+ wire width 14 $0\spr_op__fn_unit$3[13:0]$8925
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 32 $0\spr_op__insn$4$next[31:0]$8869
+ attribute \src "libresoc.v:165016.3-165017.47"
+ wire width 32 $0\spr_op__insn$4[31:0]$8854
+ attribute \src "libresoc.v:164693.14-164693.38"
+ wire width 32 $0\spr_op__insn$4[31:0]$8927
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 7 $0\spr_op__insn_type$2$next[6:0]$8870
+ attribute \src "libresoc.v:165012.3-165013.57"
+ wire width 7 $0\spr_op__insn_type$2[6:0]$8850
+ attribute \src "libresoc.v:164850.13-164850.42"
+ wire width 7 $0\spr_op__insn_type$2[6:0]$8929
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire $0\spr_op__is_32bit$5$next[0:0]$8871
+ attribute \src "libresoc.v:165018.3-165019.55"
+ wire $0\spr_op__is_32bit$5[0:0]$8856
+ attribute \src "libresoc.v:164936.7-164936.34"
+ wire $0\spr_op__is_32bit$5[0:0]$8931
+ attribute \src "libresoc.v:165204.3-165222.6"
+ wire width 2 $0\xer_ca$10$next[1:0]$8907
+ attribute \src "libresoc.v:164988.3-164989.37"
+ wire width 2 $0\xer_ca$10[1:0]$8833
+ attribute \src "libresoc.v:164943.13-164943.31"
+ wire width 2 $0\xer_ca$10[1:0]$8933
+ attribute \src "libresoc.v:165204.3-165222.6"
+ wire $0\xer_ca_ok$next[0:0]$8908
+ attribute \src "libresoc.v:164990.3-164991.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:165521.3-165539.6"
- wire width 2 $0\xer_ov$9$next[1:0]$8954
- attribute \src "libresoc.v:165328.3-165329.35"
- wire width 2 $0\xer_ov$9[1:0]$8888
- attribute \src "libresoc.v:165297.13-165297.30"
- wire width 2 $0\xer_ov$9[1:0]$8988
- attribute \src "libresoc.v:165521.3-165539.6"
- wire $0\xer_ov_ok$next[0:0]$8953
- attribute \src "libresoc.v:165330.3-165331.35"
+ attribute \src "libresoc.v:165185.3-165203.6"
+ wire width 2 $0\xer_ov$9$next[1:0]$8902
+ attribute \src "libresoc.v:164992.3-164993.35"
+ wire width 2 $0\xer_ov$9[1:0]$8836
+ attribute \src "libresoc.v:164961.13-164961.30"
+ wire width 2 $0\xer_ov$9[1:0]$8936
+ attribute \src "libresoc.v:165185.3-165203.6"
+ wire $0\xer_ov_ok$next[0:0]$8901
+ attribute \src "libresoc.v:164994.3-164995.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:165502.3-165520.6"
- wire $0\xer_so$8$next[0:0]$8948
- attribute \src "libresoc.v:165332.3-165333.35"
- wire $0\xer_so$8[0:0]$8891
- attribute \src "libresoc.v:165313.7-165313.24"
- wire $0\xer_so$8[0:0]$8991
- attribute \src "libresoc.v:165502.3-165520.6"
- wire $0\xer_so_ok$next[0:0]$8947
- attribute \src "libresoc.v:165334.3-165335.35"
+ attribute \src "libresoc.v:165166.3-165184.6"
+ wire $0\xer_so$8$next[0:0]$8896
+ attribute \src "libresoc.v:164996.3-164997.35"
+ wire $0\xer_so$8[0:0]$8839
+ attribute \src "libresoc.v:164977.7-164977.24"
+ wire $0\xer_so$8[0:0]$8939
+ attribute \src "libresoc.v:165166.3-165184.6"
+ wire $0\xer_so_ok$next[0:0]$8895
+ attribute \src "libresoc.v:164998.3-164999.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:165483.3-165501.6"
- wire width 64 $1\fast1$7$next[63:0]$8944
- attribute \src "libresoc.v:165483.3-165501.6"
- wire $1\fast1_ok$next[0:0]$8943
- attribute \src "libresoc.v:164669.7-164669.22"
+ attribute \src "libresoc.v:165147.3-165165.6"
+ wire width 64 $1\fast1$7$next[63:0]$8892
+ attribute \src "libresoc.v:165147.3-165165.6"
+ wire $1\fast1_ok$next[0:0]$8891
+ attribute \src "libresoc.v:164333.7-164333.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:165416.3-165428.6"
- wire width 2 $1\muxid$1$next[1:0]$8918
- attribute \src "libresoc.v:165445.3-165463.6"
- wire width 64 $1\o$next[63:0]$8931
- attribute \src "libresoc.v:164691.14-164691.38"
+ attribute \src "libresoc.v:165080.3-165092.6"
+ wire width 2 $1\muxid$1$next[1:0]$8866
+ attribute \src "libresoc.v:165109.3-165127.6"
+ wire width 64 $1\o$next[63:0]$8879
+ attribute \src "libresoc.v:164355.14-164355.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:165445.3-165463.6"
- wire $1\o_ok$next[0:0]$8932
- attribute \src "libresoc.v:164698.7-164698.18"
+ attribute \src "libresoc.v:165109.3-165127.6"
+ wire $1\o_ok$next[0:0]$8880
+ attribute \src "libresoc.v:164362.7-164362.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:165398.3-165415.6"
- wire $1\r_busy$next[0:0]$8914
- attribute \src "libresoc.v:164712.7-164712.20"
+ attribute \src "libresoc.v:165062.3-165079.6"
+ wire $1\r_busy$next[0:0]$8862
+ attribute \src "libresoc.v:164376.7-164376.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:165464.3-165482.6"
- wire width 64 $1\spr1$6$next[63:0]$8937
- attribute \src "libresoc.v:165464.3-165482.6"
- wire $1\spr1_ok$next[0:0]$8938
- attribute \src "libresoc.v:164728.7-164728.21"
+ attribute \src "libresoc.v:165128.3-165146.6"
+ wire width 64 $1\spr1$6$next[63:0]$8885
+ attribute \src "libresoc.v:165128.3-165146.6"
+ wire $1\spr1_ok$next[0:0]$8886
+ attribute \src "libresoc.v:164392.7-164392.21"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8924
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 32 $1\spr_op__insn$4$next[31:0]$8925
- attribute \src "libresoc.v:165429.3-165444.6"
- wire width 7 $1\spr_op__insn_type$2$next[6:0]$8926
- attribute \src "libresoc.v:165429.3-165444.6"
- wire $1\spr_op__is_32bit$5$next[0:0]$8927
- attribute \src "libresoc.v:165540.3-165558.6"
- wire width 2 $1\xer_ca$10$next[1:0]$8961
- attribute \src "libresoc.v:165540.3-165558.6"
- wire $1\xer_ca_ok$next[0:0]$8962
- attribute \src "libresoc.v:165286.7-165286.23"
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8872
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 32 $1\spr_op__insn$4$next[31:0]$8873
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire width 7 $1\spr_op__insn_type$2$next[6:0]$8874
+ attribute \src "libresoc.v:165093.3-165108.6"
+ wire $1\spr_op__is_32bit$5$next[0:0]$8875
+ attribute \src "libresoc.v:165204.3-165222.6"
+ wire width 2 $1\xer_ca$10$next[1:0]$8909
+ attribute \src "libresoc.v:165204.3-165222.6"
+ wire $1\xer_ca_ok$next[0:0]$8910
+ attribute \src "libresoc.v:164950.7-164950.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:165521.3-165539.6"
- wire width 2 $1\xer_ov$9$next[1:0]$8956
- attribute \src "libresoc.v:165521.3-165539.6"
- wire $1\xer_ov_ok$next[0:0]$8955
- attribute \src "libresoc.v:165302.7-165302.23"
+ attribute \src "libresoc.v:165185.3-165203.6"
+ wire width 2 $1\xer_ov$9$next[1:0]$8904
+ attribute \src "libresoc.v:165185.3-165203.6"
+ wire $1\xer_ov_ok$next[0:0]$8903
+ attribute \src "libresoc.v:164966.7-164966.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:165502.3-165520.6"
- wire $1\xer_so$8$next[0:0]$8950
- attribute \src "libresoc.v:165502.3-165520.6"
- wire $1\xer_so_ok$next[0:0]$8949
- attribute \src "libresoc.v:165318.7-165318.23"
+ attribute \src "libresoc.v:165166.3-165184.6"
+ wire $1\xer_so$8$next[0:0]$8898
+ attribute \src "libresoc.v:165166.3-165184.6"
+ wire $1\xer_so_ok$next[0:0]$8897
+ attribute \src "libresoc.v:164982.7-164982.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:165483.3-165501.6"
- wire $2\fast1_ok$next[0:0]$8945
- attribute \src "libresoc.v:165445.3-165463.6"
- wire $2\o_ok$next[0:0]$8933
- attribute \src "libresoc.v:165398.3-165415.6"
- wire $2\r_busy$next[0:0]$8915
- attribute \src "libresoc.v:165464.3-165482.6"
- wire $2\spr1_ok$next[0:0]$8939
- attribute \src "libresoc.v:165540.3-165558.6"
- wire $2\xer_ca_ok$next[0:0]$8963
- attribute \src "libresoc.v:165521.3-165539.6"
- wire $2\xer_ov_ok$next[0:0]$8957
- attribute \src "libresoc.v:165502.3-165520.6"
- wire $2\xer_so_ok$next[0:0]$8951
- attribute \src "libresoc.v:165323.18-165323.118"
- wire $and$libresoc.v:165323$8883_Y
+ attribute \src "libresoc.v:165147.3-165165.6"
+ wire $2\fast1_ok$next[0:0]$8893
+ attribute \src "libresoc.v:165109.3-165127.6"
+ wire $2\o_ok$next[0:0]$8881
+ attribute \src "libresoc.v:165062.3-165079.6"
+ wire $2\r_busy$next[0:0]$8863
+ attribute \src "libresoc.v:165128.3-165146.6"
+ wire $2\spr1_ok$next[0:0]$8887
+ attribute \src "libresoc.v:165204.3-165222.6"
+ wire $2\xer_ca_ok$next[0:0]$8911
+ attribute \src "libresoc.v:165185.3-165203.6"
+ wire $2\xer_ov_ok$next[0:0]$8905
+ attribute \src "libresoc.v:165166.3-165184.6"
+ wire $2\xer_so_ok$next[0:0]$8899
+ attribute \src "libresoc.v:164987.18-164987.118"
+ wire $and$libresoc.v:164987$8831_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 11 \fast1
wire \fast1_ok$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast1_ok$next
- attribute \src "libresoc.v:164651.7-164651.15"
+ attribute \src "libresoc.v:164315.7-164315.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:165323$8883
+ cell $and $and$libresoc.v:164987$8831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$21
connect \B \p_ready_o
- connect \Y $and$libresoc.v:165323$8883_Y
+ connect \Y $and$libresoc.v:164987$8831_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165360.10-165363.4"
+ attribute \src "libresoc.v:165024.10-165027.4"
cell \n$66 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165364.10-165367.4"
+ attribute \src "libresoc.v:165028.10-165031.4"
cell \p$65 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165368.12-165397.4"
+ attribute \src "libresoc.v:165032.12-165061.4"
cell \spr_main \spr_main
connect \fast1 \spr_main_fast1
connect \fast1$7 \spr_main_fast1$17
connect \xer_so$8 \spr_main_xer_so$18
connect \xer_so_ok \spr_main_xer_so_ok
end
- attribute \src "libresoc.v:164651.7-164651.20"
- process $proc$libresoc.v:164651$8964
+ attribute \src "libresoc.v:164315.7-164315.20"
+ process $proc$libresoc.v:164315$8912
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:164664.14-164664.46"
- process $proc$libresoc.v:164664$8965
+ attribute \src "libresoc.v:164328.14-164328.46"
+ process $proc$libresoc.v:164328$8913
assign { } { }
- assign $0\fast1$7[63:0]$8966 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$7[63:0]$8914 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$7 $0\fast1$7[63:0]$8966
+ update \fast1$7 $0\fast1$7[63:0]$8914
end
- attribute \src "libresoc.v:164669.7-164669.22"
- process $proc$libresoc.v:164669$8967
+ attribute \src "libresoc.v:164333.7-164333.22"
+ process $proc$libresoc.v:164333$8915
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:164678.13-164678.29"
- process $proc$libresoc.v:164678$8968
+ attribute \src "libresoc.v:164342.13-164342.29"
+ process $proc$libresoc.v:164342$8916
assign { } { }
- assign $0\muxid$1[1:0]$8969 2'00
+ assign $0\muxid$1[1:0]$8917 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8969
+ update \muxid$1 $0\muxid$1[1:0]$8917
end
- attribute \src "libresoc.v:164691.14-164691.38"
- process $proc$libresoc.v:164691$8970
+ attribute \src "libresoc.v:164355.14-164355.38"
+ process $proc$libresoc.v:164355$8918
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:164698.7-164698.18"
- process $proc$libresoc.v:164698$8971
+ attribute \src "libresoc.v:164362.7-164362.18"
+ process $proc$libresoc.v:164362$8919
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:164712.7-164712.20"
- process $proc$libresoc.v:164712$8972
+ attribute \src "libresoc.v:164376.7-164376.20"
+ process $proc$libresoc.v:164376$8920
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:164723.14-164723.45"
- process $proc$libresoc.v:164723$8973
+ attribute \src "libresoc.v:164387.14-164387.45"
+ process $proc$libresoc.v:164387$8921
assign { } { }
- assign $0\spr1$6[63:0]$8974 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\spr1$6[63:0]$8922 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \spr1$6 $0\spr1$6[63:0]$8974
+ update \spr1$6 $0\spr1$6[63:0]$8922
end
- attribute \src "libresoc.v:164728.7-164728.21"
- process $proc$libresoc.v:164728$8975
+ attribute \src "libresoc.v:164392.7-164392.21"
+ process $proc$libresoc.v:164392$8923
assign { } { }
assign $1\spr1_ok[0:0] 1'0
sync always
sync init
update \spr1_ok $1\spr1_ok[0:0]
end
- attribute \src "libresoc.v:165020.14-165020.44"
- process $proc$libresoc.v:165020$8976
+ attribute \src "libresoc.v:164684.14-164684.44"
+ process $proc$libresoc.v:164684$8924
assign { } { }
- assign $0\spr_op__fn_unit$3[13:0]$8977 14'00000000000000
+ assign $0\spr_op__fn_unit$3[13:0]$8925 14'00000000000000
sync always
sync init
- update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8977
+ update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8925
end
- attribute \src "libresoc.v:165029.14-165029.38"
- process $proc$libresoc.v:165029$8978
+ attribute \src "libresoc.v:164693.14-164693.38"
+ process $proc$libresoc.v:164693$8926
assign { } { }
- assign $0\spr_op__insn$4[31:0]$8979 0
+ assign $0\spr_op__insn$4[31:0]$8927 0
sync always
sync init
- update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8979
+ update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8927
end
- attribute \src "libresoc.v:165186.13-165186.42"
- process $proc$libresoc.v:165186$8980
+ attribute \src "libresoc.v:164850.13-164850.42"
+ process $proc$libresoc.v:164850$8928
assign { } { }
- assign $0\spr_op__insn_type$2[6:0]$8981 7'0000000
+ assign $0\spr_op__insn_type$2[6:0]$8929 7'0000000
sync always
sync init
- update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8981
+ update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8929
end
- attribute \src "libresoc.v:165272.7-165272.34"
- process $proc$libresoc.v:165272$8982
+ attribute \src "libresoc.v:164936.7-164936.34"
+ process $proc$libresoc.v:164936$8930
assign { } { }
- assign $0\spr_op__is_32bit$5[0:0]$8983 1'0
+ assign $0\spr_op__is_32bit$5[0:0]$8931 1'0
sync always
sync init
- update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8983
+ update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8931
end
- attribute \src "libresoc.v:165279.13-165279.31"
- process $proc$libresoc.v:165279$8984
+ attribute \src "libresoc.v:164943.13-164943.31"
+ process $proc$libresoc.v:164943$8932
assign { } { }
- assign $0\xer_ca$10[1:0]$8985 2'00
+ assign $0\xer_ca$10[1:0]$8933 2'00
sync always
sync init
- update \xer_ca$10 $0\xer_ca$10[1:0]$8985
+ update \xer_ca$10 $0\xer_ca$10[1:0]$8933
end
- attribute \src "libresoc.v:165286.7-165286.23"
- process $proc$libresoc.v:165286$8986
+ attribute \src "libresoc.v:164950.7-164950.23"
+ process $proc$libresoc.v:164950$8934
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:165297.13-165297.30"
- process $proc$libresoc.v:165297$8987
+ attribute \src "libresoc.v:164961.13-164961.30"
+ process $proc$libresoc.v:164961$8935
assign { } { }
- assign $0\xer_ov$9[1:0]$8988 2'00
+ assign $0\xer_ov$9[1:0]$8936 2'00
sync always
sync init
- update \xer_ov$9 $0\xer_ov$9[1:0]$8988
+ update \xer_ov$9 $0\xer_ov$9[1:0]$8936
end
- attribute \src "libresoc.v:165302.7-165302.23"
- process $proc$libresoc.v:165302$8989
+ attribute \src "libresoc.v:164966.7-164966.23"
+ process $proc$libresoc.v:164966$8937
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:165313.7-165313.24"
- process $proc$libresoc.v:165313$8990
+ attribute \src "libresoc.v:164977.7-164977.24"
+ process $proc$libresoc.v:164977$8938
assign { } { }
- assign $0\xer_so$8[0:0]$8991 1'0
+ assign $0\xer_so$8[0:0]$8939 1'0
sync always
sync init
- update \xer_so$8 $0\xer_so$8[0:0]$8991
+ update \xer_so$8 $0\xer_so$8[0:0]$8939
end
- attribute \src "libresoc.v:165318.7-165318.23"
- process $proc$libresoc.v:165318$8992
+ attribute \src "libresoc.v:164982.7-164982.23"
+ process $proc$libresoc.v:164982$8940
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:165324.3-165325.37"
- process $proc$libresoc.v:165324$8884
+ attribute \src "libresoc.v:164988.3-164989.37"
+ process $proc$libresoc.v:164988$8832
assign { } { }
- assign $0\xer_ca$10[1:0]$8885 \xer_ca$10$next
+ assign $0\xer_ca$10[1:0]$8833 \xer_ca$10$next
sync posedge \coresync_clk
- update \xer_ca$10 $0\xer_ca$10[1:0]$8885
+ update \xer_ca$10 $0\xer_ca$10[1:0]$8833
end
- attribute \src "libresoc.v:165326.3-165327.35"
- process $proc$libresoc.v:165326$8886
+ attribute \src "libresoc.v:164990.3-164991.35"
+ process $proc$libresoc.v:164990$8834
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:165328.3-165329.35"
- process $proc$libresoc.v:165328$8887
+ attribute \src "libresoc.v:164992.3-164993.35"
+ process $proc$libresoc.v:164992$8835
assign { } { }
- assign $0\xer_ov$9[1:0]$8888 \xer_ov$9$next
+ assign $0\xer_ov$9[1:0]$8836 \xer_ov$9$next
sync posedge \coresync_clk
- update \xer_ov$9 $0\xer_ov$9[1:0]$8888
+ update \xer_ov$9 $0\xer_ov$9[1:0]$8836
end
- attribute \src "libresoc.v:165330.3-165331.35"
- process $proc$libresoc.v:165330$8889
+ attribute \src "libresoc.v:164994.3-164995.35"
+ process $proc$libresoc.v:164994$8837
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:165332.3-165333.35"
- process $proc$libresoc.v:165332$8890
+ attribute \src "libresoc.v:164996.3-164997.35"
+ process $proc$libresoc.v:164996$8838
assign { } { }
- assign $0\xer_so$8[0:0]$8891 \xer_so$8$next
+ assign $0\xer_so$8[0:0]$8839 \xer_so$8$next
sync posedge \coresync_clk
- update \xer_so$8 $0\xer_so$8[0:0]$8891
+ update \xer_so$8 $0\xer_so$8[0:0]$8839
end
- attribute \src "libresoc.v:165334.3-165335.35"
- process $proc$libresoc.v:165334$8892
+ attribute \src "libresoc.v:164998.3-164999.35"
+ process $proc$libresoc.v:164998$8840
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:165336.3-165337.33"
- process $proc$libresoc.v:165336$8893
+ attribute \src "libresoc.v:165000.3-165001.33"
+ process $proc$libresoc.v:165000$8841
assign { } { }
- assign $0\fast1$7[63:0]$8894 \fast1$7$next
+ assign $0\fast1$7[63:0]$8842 \fast1$7$next
sync posedge \coresync_clk
- update \fast1$7 $0\fast1$7[63:0]$8894
+ update \fast1$7 $0\fast1$7[63:0]$8842
end
- attribute \src "libresoc.v:165338.3-165339.33"
- process $proc$libresoc.v:165338$8895
+ attribute \src "libresoc.v:165002.3-165003.33"
+ process $proc$libresoc.v:165002$8843
assign { } { }
assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:165340.3-165341.31"
- process $proc$libresoc.v:165340$8896
+ attribute \src "libresoc.v:165004.3-165005.31"
+ process $proc$libresoc.v:165004$8844
assign { } { }
- assign $0\spr1$6[63:0]$8897 \spr1$6$next
+ assign $0\spr1$6[63:0]$8845 \spr1$6$next
sync posedge \coresync_clk
- update \spr1$6 $0\spr1$6[63:0]$8897
+ update \spr1$6 $0\spr1$6[63:0]$8845
end
- attribute \src "libresoc.v:165342.3-165343.31"
- process $proc$libresoc.v:165342$8898
+ attribute \src "libresoc.v:165006.3-165007.31"
+ process $proc$libresoc.v:165006$8846
assign { } { }
assign $0\spr1_ok[0:0] \spr1_ok$next
sync posedge \coresync_clk
update \spr1_ok $0\spr1_ok[0:0]
end
- attribute \src "libresoc.v:165344.3-165345.19"
- process $proc$libresoc.v:165344$8899
+ attribute \src "libresoc.v:165008.3-165009.19"
+ process $proc$libresoc.v:165008$8847
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:165346.3-165347.25"
- process $proc$libresoc.v:165346$8900
+ attribute \src "libresoc.v:165010.3-165011.25"
+ process $proc$libresoc.v:165010$8848
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:165348.3-165349.57"
- process $proc$libresoc.v:165348$8901
+ attribute \src "libresoc.v:165012.3-165013.57"
+ process $proc$libresoc.v:165012$8849
assign { } { }
- assign $0\spr_op__insn_type$2[6:0]$8902 \spr_op__insn_type$2$next
+ assign $0\spr_op__insn_type$2[6:0]$8850 \spr_op__insn_type$2$next
sync posedge \coresync_clk
- update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8902
+ update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8850
end
- attribute \src "libresoc.v:165350.3-165351.53"
- process $proc$libresoc.v:165350$8903
+ attribute \src "libresoc.v:165014.3-165015.53"
+ process $proc$libresoc.v:165014$8851
assign { } { }
- assign $0\spr_op__fn_unit$3[13:0]$8904 \spr_op__fn_unit$3$next
+ assign $0\spr_op__fn_unit$3[13:0]$8852 \spr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8904
+ update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8852
end
- attribute \src "libresoc.v:165352.3-165353.47"
- process $proc$libresoc.v:165352$8905
+ attribute \src "libresoc.v:165016.3-165017.47"
+ process $proc$libresoc.v:165016$8853
assign { } { }
- assign $0\spr_op__insn$4[31:0]$8906 \spr_op__insn$4$next
+ assign $0\spr_op__insn$4[31:0]$8854 \spr_op__insn$4$next
sync posedge \coresync_clk
- update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8906
+ update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8854
end
- attribute \src "libresoc.v:165354.3-165355.55"
- process $proc$libresoc.v:165354$8907
+ attribute \src "libresoc.v:165018.3-165019.55"
+ process $proc$libresoc.v:165018$8855
assign { } { }
- assign $0\spr_op__is_32bit$5[0:0]$8908 \spr_op__is_32bit$5$next
+ assign $0\spr_op__is_32bit$5[0:0]$8856 \spr_op__is_32bit$5$next
sync posedge \coresync_clk
- update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8908
+ update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8856
end
- attribute \src "libresoc.v:165356.3-165357.33"
- process $proc$libresoc.v:165356$8909
+ attribute \src "libresoc.v:165020.3-165021.33"
+ process $proc$libresoc.v:165020$8857
assign { } { }
- assign $0\muxid$1[1:0]$8910 \muxid$1$next
+ assign $0\muxid$1[1:0]$8858 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8910
+ update \muxid$1 $0\muxid$1[1:0]$8858
end
- attribute \src "libresoc.v:165358.3-165359.29"
- process $proc$libresoc.v:165358$8911
+ attribute \src "libresoc.v:165022.3-165023.29"
+ process $proc$libresoc.v:165022$8859
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:165398.3-165415.6"
- process $proc$libresoc.v:165398$8912
+ attribute \src "libresoc.v:165062.3-165079.6"
+ process $proc$libresoc.v:165062$8860
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8913 $2\r_busy$next[0:0]$8915
- attribute \src "libresoc.v:165399.5-165399.29"
+ assign $0\r_busy$next[0:0]$8861 $2\r_busy$next[0:0]$8863
+ attribute \src "libresoc.v:165063.5-165063.29"
switch \initial
- attribute \src "libresoc.v:165399.9-165399.17"
+ attribute \src "libresoc.v:165063.9-165063.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8914 1'1
+ assign $1\r_busy$next[0:0]$8862 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8914 1'0
+ assign $1\r_busy$next[0:0]$8862 1'0
case
- assign $1\r_busy$next[0:0]$8914 \r_busy
+ assign $1\r_busy$next[0:0]$8862 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8915 1'0
+ assign $2\r_busy$next[0:0]$8863 1'0
case
- assign $2\r_busy$next[0:0]$8915 $1\r_busy$next[0:0]$8914
+ assign $2\r_busy$next[0:0]$8863 $1\r_busy$next[0:0]$8862
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8913
+ update \r_busy$next $0\r_busy$next[0:0]$8861
end
- attribute \src "libresoc.v:165416.3-165428.6"
- process $proc$libresoc.v:165416$8916
+ attribute \src "libresoc.v:165080.3-165092.6"
+ process $proc$libresoc.v:165080$8864
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8917 $1\muxid$1$next[1:0]$8918
- attribute \src "libresoc.v:165417.5-165417.29"
+ assign $0\muxid$1$next[1:0]$8865 $1\muxid$1$next[1:0]$8866
+ attribute \src "libresoc.v:165081.5-165081.29"
switch \initial
- attribute \src "libresoc.v:165417.9-165417.17"
+ attribute \src "libresoc.v:165081.9-165081.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8918 \muxid$24
+ assign $1\muxid$1$next[1:0]$8866 \muxid$24
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8918 \muxid$24
+ assign $1\muxid$1$next[1:0]$8866 \muxid$24
case
- assign $1\muxid$1$next[1:0]$8918 \muxid$1
+ assign $1\muxid$1$next[1:0]$8866 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8917
+ update \muxid$1$next $0\muxid$1$next[1:0]$8865
end
- attribute \src "libresoc.v:165429.3-165444.6"
- process $proc$libresoc.v:165429$8919
+ attribute \src "libresoc.v:165093.3-165108.6"
+ process $proc$libresoc.v:165093$8867
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\spr_op__fn_unit$3$next[13:0]$8920 $1\spr_op__fn_unit$3$next[13:0]$8924
- assign $0\spr_op__insn$4$next[31:0]$8921 $1\spr_op__insn$4$next[31:0]$8925
- assign $0\spr_op__insn_type$2$next[6:0]$8922 $1\spr_op__insn_type$2$next[6:0]$8926
- assign $0\spr_op__is_32bit$5$next[0:0]$8923 $1\spr_op__is_32bit$5$next[0:0]$8927
- attribute \src "libresoc.v:165430.5-165430.29"
+ assign $0\spr_op__fn_unit$3$next[13:0]$8868 $1\spr_op__fn_unit$3$next[13:0]$8872
+ assign $0\spr_op__insn$4$next[31:0]$8869 $1\spr_op__insn$4$next[31:0]$8873
+ assign $0\spr_op__insn_type$2$next[6:0]$8870 $1\spr_op__insn_type$2$next[6:0]$8874
+ assign $0\spr_op__is_32bit$5$next[0:0]$8871 $1\spr_op__is_32bit$5$next[0:0]$8875
+ attribute \src "libresoc.v:165094.5-165094.29"
switch \initial
- attribute \src "libresoc.v:165430.9-165430.17"
+ attribute \src "libresoc.v:165094.9-165094.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\spr_op__is_32bit$5$next[0:0]$8927 $1\spr_op__insn$4$next[31:0]$8925 $1\spr_op__fn_unit$3$next[13:0]$8924 $1\spr_op__insn_type$2$next[6:0]$8926 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
+ assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\spr_op__is_32bit$5$next[0:0]$8927 $1\spr_op__insn$4$next[31:0]$8925 $1\spr_op__fn_unit$3$next[13:0]$8924 $1\spr_op__insn_type$2$next[6:0]$8926 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
+ assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
case
- assign $1\spr_op__fn_unit$3$next[13:0]$8924 \spr_op__fn_unit$3
- assign $1\spr_op__insn$4$next[31:0]$8925 \spr_op__insn$4
- assign $1\spr_op__insn_type$2$next[6:0]$8926 \spr_op__insn_type$2
- assign $1\spr_op__is_32bit$5$next[0:0]$8927 \spr_op__is_32bit$5
+ assign $1\spr_op__fn_unit$3$next[13:0]$8872 \spr_op__fn_unit$3
+ assign $1\spr_op__insn$4$next[31:0]$8873 \spr_op__insn$4
+ assign $1\spr_op__insn_type$2$next[6:0]$8874 \spr_op__insn_type$2
+ assign $1\spr_op__is_32bit$5$next[0:0]$8875 \spr_op__is_32bit$5
end
sync always
- update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8920
- update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8921
- update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8922
- update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8923
+ update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8868
+ update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8869
+ update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8870
+ update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8871
end
- attribute \src "libresoc.v:165445.3-165463.6"
- process $proc$libresoc.v:165445$8928
+ attribute \src "libresoc.v:165109.3-165127.6"
+ process $proc$libresoc.v:165109$8876
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$8929 $1\o$next[63:0]$8931
+ assign $0\o$next[63:0]$8877 $1\o$next[63:0]$8879
assign { } { }
- assign $0\o_ok$next[0:0]$8930 $2\o_ok$next[0:0]$8933
- attribute \src "libresoc.v:165446.5-165446.29"
+ assign $0\o_ok$next[0:0]$8878 $2\o_ok$next[0:0]$8881
+ attribute \src "libresoc.v:165110.5-165110.29"
switch \initial
- attribute \src "libresoc.v:165446.9-165446.17"
+ attribute \src "libresoc.v:165110.9-165110.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8932 $1\o$next[63:0]$8931 } { \o_ok$30 \o$29 }
+ assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8932 $1\o$next[63:0]$8931 } { \o_ok$30 \o$29 }
+ assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 }
case
- assign $1\o$next[63:0]$8931 \o
- assign $1\o_ok$next[0:0]$8932 \o_ok
+ assign $1\o$next[63:0]$8879 \o
+ assign $1\o_ok$next[0:0]$8880 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8933 1'0
+ assign $2\o_ok$next[0:0]$8881 1'0
case
- assign $2\o_ok$next[0:0]$8933 $1\o_ok$next[0:0]$8932
+ assign $2\o_ok$next[0:0]$8881 $1\o_ok$next[0:0]$8880
end
sync always
- update \o$next $0\o$next[63:0]$8929
- update \o_ok$next $0\o_ok$next[0:0]$8930
+ update \o$next $0\o$next[63:0]$8877
+ update \o_ok$next $0\o_ok$next[0:0]$8878
end
- attribute \src "libresoc.v:165464.3-165482.6"
- process $proc$libresoc.v:165464$8934
+ attribute \src "libresoc.v:165128.3-165146.6"
+ process $proc$libresoc.v:165128$8882
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\spr1$6$next[63:0]$8935 $1\spr1$6$next[63:0]$8937
+ assign $0\spr1$6$next[63:0]$8883 $1\spr1$6$next[63:0]$8885
assign { } { }
- assign $0\spr1_ok$next[0:0]$8936 $2\spr1_ok$next[0:0]$8939
- attribute \src "libresoc.v:165465.5-165465.29"
+ assign $0\spr1_ok$next[0:0]$8884 $2\spr1_ok$next[0:0]$8887
+ attribute \src "libresoc.v:165129.5-165129.29"
switch \initial
- attribute \src "libresoc.v:165465.9-165465.17"
+ attribute \src "libresoc.v:165129.9-165129.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\spr1_ok$next[0:0]$8938 $1\spr1$6$next[63:0]$8937 } { \spr1_ok$32 \spr1$31 }
+ assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\spr1_ok$next[0:0]$8938 $1\spr1$6$next[63:0]$8937 } { \spr1_ok$32 \spr1$31 }
+ assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 }
case
- assign $1\spr1$6$next[63:0]$8937 \spr1$6
- assign $1\spr1_ok$next[0:0]$8938 \spr1_ok
+ assign $1\spr1$6$next[63:0]$8885 \spr1$6
+ assign $1\spr1_ok$next[0:0]$8886 \spr1_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\spr1_ok$next[0:0]$8939 1'0
+ assign $2\spr1_ok$next[0:0]$8887 1'0
case
- assign $2\spr1_ok$next[0:0]$8939 $1\spr1_ok$next[0:0]$8938
+ assign $2\spr1_ok$next[0:0]$8887 $1\spr1_ok$next[0:0]$8886
end
sync always
- update \spr1$6$next $0\spr1$6$next[63:0]$8935
- update \spr1_ok$next $0\spr1_ok$next[0:0]$8936
+ update \spr1$6$next $0\spr1$6$next[63:0]$8883
+ update \spr1_ok$next $0\spr1_ok$next[0:0]$8884
end
- attribute \src "libresoc.v:165483.3-165501.6"
- process $proc$libresoc.v:165483$8940
+ attribute \src "libresoc.v:165147.3-165165.6"
+ process $proc$libresoc.v:165147$8888
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$7$next[63:0]$8942 $1\fast1$7$next[63:0]$8944
- assign $0\fast1_ok$next[0:0]$8941 $2\fast1_ok$next[0:0]$8945
- attribute \src "libresoc.v:165484.5-165484.29"
+ assign $0\fast1$7$next[63:0]$8890 $1\fast1$7$next[63:0]$8892
+ assign $0\fast1_ok$next[0:0]$8889 $2\fast1_ok$next[0:0]$8893
+ attribute \src "libresoc.v:165148.5-165148.29"
switch \initial
- attribute \src "libresoc.v:165484.9-165484.17"
+ attribute \src "libresoc.v:165148.9-165148.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8943 $1\fast1$7$next[63:0]$8944 } { \fast1_ok$34 \fast1$33 }
+ assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8943 $1\fast1$7$next[63:0]$8944 } { \fast1_ok$34 \fast1$33 }
+ assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 }
case
- assign $1\fast1_ok$next[0:0]$8943 \fast1_ok
- assign $1\fast1$7$next[63:0]$8944 \fast1$7
+ assign $1\fast1_ok$next[0:0]$8891 \fast1_ok
+ assign $1\fast1$7$next[63:0]$8892 \fast1$7
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$8945 1'0
+ assign $2\fast1_ok$next[0:0]$8893 1'0
case
- assign $2\fast1_ok$next[0:0]$8945 $1\fast1_ok$next[0:0]$8943
+ assign $2\fast1_ok$next[0:0]$8893 $1\fast1_ok$next[0:0]$8891
end
sync always
- update \fast1_ok$next $0\fast1_ok$next[0:0]$8941
- update \fast1$7$next $0\fast1$7$next[63:0]$8942
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$8889
+ update \fast1$7$next $0\fast1$7$next[63:0]$8890
end
- attribute \src "libresoc.v:165502.3-165520.6"
- process $proc$libresoc.v:165502$8946
+ attribute \src "libresoc.v:165166.3-165184.6"
+ process $proc$libresoc.v:165166$8894
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$8$next[0:0]$8948 $1\xer_so$8$next[0:0]$8950
- assign $0\xer_so_ok$next[0:0]$8947 $2\xer_so_ok$next[0:0]$8951
- attribute \src "libresoc.v:165503.5-165503.29"
+ assign $0\xer_so$8$next[0:0]$8896 $1\xer_so$8$next[0:0]$8898
+ assign $0\xer_so_ok$next[0:0]$8895 $2\xer_so_ok$next[0:0]$8899
+ attribute \src "libresoc.v:165167.5-165167.29"
switch \initial
- attribute \src "libresoc.v:165503.9-165503.17"
+ attribute \src "libresoc.v:165167.9-165167.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8949 $1\xer_so$8$next[0:0]$8950 } { \xer_so_ok$36 \xer_so$35 }
+ assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8949 $1\xer_so$8$next[0:0]$8950 } { \xer_so_ok$36 \xer_so$35 }
+ assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 }
case
- assign $1\xer_so_ok$next[0:0]$8949 \xer_so_ok
- assign $1\xer_so$8$next[0:0]$8950 \xer_so$8
+ assign $1\xer_so_ok$next[0:0]$8897 \xer_so_ok
+ assign $1\xer_so$8$next[0:0]$8898 \xer_so$8
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$8951 1'0
+ assign $2\xer_so_ok$next[0:0]$8899 1'0
case
- assign $2\xer_so_ok$next[0:0]$8951 $1\xer_so_ok$next[0:0]$8949
+ assign $2\xer_so_ok$next[0:0]$8899 $1\xer_so_ok$next[0:0]$8897
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8947
- update \xer_so$8$next $0\xer_so$8$next[0:0]$8948
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8895
+ update \xer_so$8$next $0\xer_so$8$next[0:0]$8896
end
- attribute \src "libresoc.v:165521.3-165539.6"
- process $proc$libresoc.v:165521$8952
+ attribute \src "libresoc.v:165185.3-165203.6"
+ process $proc$libresoc.v:165185$8900
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$9$next[1:0]$8954 $1\xer_ov$9$next[1:0]$8956
- assign $0\xer_ov_ok$next[0:0]$8953 $2\xer_ov_ok$next[0:0]$8957
- attribute \src "libresoc.v:165522.5-165522.29"
+ assign $0\xer_ov$9$next[1:0]$8902 $1\xer_ov$9$next[1:0]$8904
+ assign $0\xer_ov_ok$next[0:0]$8901 $2\xer_ov_ok$next[0:0]$8905
+ attribute \src "libresoc.v:165186.5-165186.29"
switch \initial
- attribute \src "libresoc.v:165522.9-165522.17"
+ attribute \src "libresoc.v:165186.9-165186.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8955 $1\xer_ov$9$next[1:0]$8956 } { \xer_ov_ok$38 \xer_ov$37 }
+ assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8955 $1\xer_ov$9$next[1:0]$8956 } { \xer_ov_ok$38 \xer_ov$37 }
+ assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 }
case
- assign $1\xer_ov_ok$next[0:0]$8955 \xer_ov_ok
- assign $1\xer_ov$9$next[1:0]$8956 \xer_ov$9
+ assign $1\xer_ov_ok$next[0:0]$8903 \xer_ov_ok
+ assign $1\xer_ov$9$next[1:0]$8904 \xer_ov$9
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$8957 1'0
+ assign $2\xer_ov_ok$next[0:0]$8905 1'0
case
- assign $2\xer_ov_ok$next[0:0]$8957 $1\xer_ov_ok$next[0:0]$8955
+ assign $2\xer_ov_ok$next[0:0]$8905 $1\xer_ov_ok$next[0:0]$8903
end
sync always
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8953
- update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8954
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8901
+ update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8902
end
- attribute \src "libresoc.v:165540.3-165558.6"
- process $proc$libresoc.v:165540$8958
+ attribute \src "libresoc.v:165204.3-165222.6"
+ process $proc$libresoc.v:165204$8906
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$10$next[1:0]$8959 $1\xer_ca$10$next[1:0]$8961
+ assign $0\xer_ca$10$next[1:0]$8907 $1\xer_ca$10$next[1:0]$8909
assign { } { }
- assign $0\xer_ca_ok$next[0:0]$8960 $2\xer_ca_ok$next[0:0]$8963
- attribute \src "libresoc.v:165541.5-165541.29"
+ assign $0\xer_ca_ok$next[0:0]$8908 $2\xer_ca_ok$next[0:0]$8911
+ attribute \src "libresoc.v:165205.5-165205.29"
switch \initial
- attribute \src "libresoc.v:165541.9-165541.17"
+ attribute \src "libresoc.v:165205.9-165205.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$8962 $1\xer_ca$10$next[1:0]$8961 } { \xer_ca_ok$40 \xer_ca$39 }
+ assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$8962 $1\xer_ca$10$next[1:0]$8961 } { \xer_ca_ok$40 \xer_ca$39 }
+ assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 }
case
- assign $1\xer_ca$10$next[1:0]$8961 \xer_ca$10
- assign $1\xer_ca_ok$next[0:0]$8962 \xer_ca_ok
+ assign $1\xer_ca$10$next[1:0]$8909 \xer_ca$10
+ assign $1\xer_ca_ok$next[0:0]$8910 \xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$8963 1'0
+ assign $2\xer_ca_ok$next[0:0]$8911 1'0
case
- assign $2\xer_ca_ok$next[0:0]$8963 $1\xer_ca_ok$next[0:0]$8962
+ assign $2\xer_ca_ok$next[0:0]$8911 $1\xer_ca_ok$next[0:0]$8910
end
sync always
- update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8959
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8960
+ update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8907
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8908
end
- connect \$22 $and$libresoc.v:165323$8883_Y
+ connect \$22 $and$libresoc.v:164987$8831_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 }
connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
connect \spr_main_muxid \muxid
end
-attribute \src "libresoc.v:165584.1-167076.10"
+attribute \src "libresoc.v:165248.1-166740.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1"
attribute \generator "nMigen"
module \pipe1
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 4 $0\alu_op__data_len$next[3:0]$9056
- attribute \src "libresoc.v:166766.3-166767.49"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 4 $0\alu_op__data_len$next[3:0]$9004
+ attribute \src "libresoc.v:166430.3-166431.49"
wire width 4 $0\alu_op__data_len[3:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 14 $0\alu_op__fn_unit$next[13:0]$9057
- attribute \src "libresoc.v:166736.3-166737.47"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 14 $0\alu_op__fn_unit$next[13:0]$9005
+ attribute \src "libresoc.v:166400.3-166401.47"
wire width 14 $0\alu_op__fn_unit[13:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 64 $0\alu_op__imm_data__data$next[63:0]$9058
- attribute \src "libresoc.v:166738.3-166739.61"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 64 $0\alu_op__imm_data__data$next[63:0]$9006
+ attribute \src "libresoc.v:166402.3-166403.61"
wire width 64 $0\alu_op__imm_data__data[63:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__imm_data__ok$next[0:0]$9059
- attribute \src "libresoc.v:166740.3-166741.57"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__imm_data__ok$next[0:0]$9007
+ attribute \src "libresoc.v:166404.3-166405.57"
wire $0\alu_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 2 $0\alu_op__input_carry$next[1:0]$9060
- attribute \src "libresoc.v:166758.3-166759.55"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 2 $0\alu_op__input_carry$next[1:0]$9008
+ attribute \src "libresoc.v:166422.3-166423.55"
wire width 2 $0\alu_op__input_carry[1:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 32 $0\alu_op__insn$next[31:0]$9061
- attribute \src "libresoc.v:166768.3-166769.41"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 32 $0\alu_op__insn$next[31:0]$9009
+ attribute \src "libresoc.v:166432.3-166433.41"
wire width 32 $0\alu_op__insn[31:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 7 $0\alu_op__insn_type$next[6:0]$9062
- attribute \src "libresoc.v:166734.3-166735.51"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 7 $0\alu_op__insn_type$next[6:0]$9010
+ attribute \src "libresoc.v:166398.3-166399.51"
wire width 7 $0\alu_op__insn_type[6:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__invert_in$next[0:0]$9063
- attribute \src "libresoc.v:166750.3-166751.51"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__invert_in$next[0:0]$9011
+ attribute \src "libresoc.v:166414.3-166415.51"
wire $0\alu_op__invert_in[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__invert_out$next[0:0]$9064
- attribute \src "libresoc.v:166754.3-166755.53"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__invert_out$next[0:0]$9012
+ attribute \src "libresoc.v:166418.3-166419.53"
wire $0\alu_op__invert_out[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__is_32bit$next[0:0]$9065
- attribute \src "libresoc.v:166762.3-166763.49"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__is_32bit$next[0:0]$9013
+ attribute \src "libresoc.v:166426.3-166427.49"
wire $0\alu_op__is_32bit[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__is_signed$next[0:0]$9066
- attribute \src "libresoc.v:166764.3-166765.51"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__is_signed$next[0:0]$9014
+ attribute \src "libresoc.v:166428.3-166429.51"
wire $0\alu_op__is_signed[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__oe__oe$next[0:0]$9067
- attribute \src "libresoc.v:166746.3-166747.45"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__oe__oe$next[0:0]$9015
+ attribute \src "libresoc.v:166410.3-166411.45"
wire $0\alu_op__oe__oe[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__oe__ok$next[0:0]$9068
- attribute \src "libresoc.v:166748.3-166749.45"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__oe__ok$next[0:0]$9016
+ attribute \src "libresoc.v:166412.3-166413.45"
wire $0\alu_op__oe__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__output_carry$next[0:0]$9069
- attribute \src "libresoc.v:166760.3-166761.57"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__output_carry$next[0:0]$9017
+ attribute \src "libresoc.v:166424.3-166425.57"
wire $0\alu_op__output_carry[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__rc__ok$next[0:0]$9070
- attribute \src "libresoc.v:166744.3-166745.45"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__rc__ok$next[0:0]$9018
+ attribute \src "libresoc.v:166408.3-166409.45"
wire $0\alu_op__rc__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__rc__rc$next[0:0]$9071
- attribute \src "libresoc.v:166742.3-166743.45"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__rc__rc$next[0:0]$9019
+ attribute \src "libresoc.v:166406.3-166407.45"
wire $0\alu_op__rc__rc[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__write_cr0$next[0:0]$9072
- attribute \src "libresoc.v:166756.3-166757.51"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__write_cr0$next[0:0]$9020
+ attribute \src "libresoc.v:166420.3-166421.51"
wire $0\alu_op__write_cr0[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $0\alu_op__zero_a$next[0:0]$9073
- attribute \src "libresoc.v:166752.3-166753.45"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $0\alu_op__zero_a$next[0:0]$9021
+ attribute \src "libresoc.v:166416.3-166417.45"
wire $0\alu_op__zero_a[0:0]
- attribute \src "libresoc.v:166883.3-166901.6"
- wire width 4 $0\cr_a$next[3:0]$9025
- attribute \src "libresoc.v:166726.3-166727.25"
+ attribute \src "libresoc.v:166547.3-166565.6"
+ wire width 4 $0\cr_a$next[3:0]$8973
+ attribute \src "libresoc.v:166390.3-166391.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:166883.3-166901.6"
- wire $0\cr_a_ok$next[0:0]$9026
- attribute \src "libresoc.v:166728.3-166729.31"
+ attribute \src "libresoc.v:166547.3-166565.6"
+ wire $0\cr_a_ok$next[0:0]$8974
+ attribute \src "libresoc.v:166392.3-166393.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:165585.7-165585.20"
+ attribute \src "libresoc.v:165249.7-165249.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:166977.3-166989.6"
- wire width 2 $0\muxid$next[1:0]$9053
- attribute \src "libresoc.v:166770.3-166771.27"
+ attribute \src "libresoc.v:166641.3-166653.6"
+ wire width 2 $0\muxid$next[1:0]$9001
+ attribute \src "libresoc.v:166434.3-166435.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:167032.3-167050.6"
- wire width 64 $0\o$next[63:0]$9099
- attribute \src "libresoc.v:166730.3-166731.19"
+ attribute \src "libresoc.v:166696.3-166714.6"
+ wire width 64 $0\o$next[63:0]$9047
+ attribute \src "libresoc.v:166394.3-166395.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:167032.3-167050.6"
- wire $0\o_ok$next[0:0]$9100
- attribute \src "libresoc.v:166732.3-166733.25"
+ attribute \src "libresoc.v:166696.3-166714.6"
+ wire $0\o_ok$next[0:0]$9048
+ attribute \src "libresoc.v:166396.3-166397.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:166959.3-166976.6"
- wire $0\r_busy$next[0:0]$9049
- attribute \src "libresoc.v:166772.3-166773.29"
+ attribute \src "libresoc.v:166623.3-166640.6"
+ wire $0\r_busy$next[0:0]$8997
+ attribute \src "libresoc.v:166436.3-166437.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:166902.3-166920.6"
- wire width 2 $0\xer_ca$next[1:0]$9032
- attribute \src "libresoc.v:166722.3-166723.29"
+ attribute \src "libresoc.v:166566.3-166584.6"
+ wire width 2 $0\xer_ca$next[1:0]$8980
+ attribute \src "libresoc.v:166386.3-166387.29"
wire width 2 $0\xer_ca[1:0]
- attribute \src "libresoc.v:166902.3-166920.6"
- wire $0\xer_ca_ok$next[0:0]$9031
- attribute \src "libresoc.v:166724.3-166725.35"
+ attribute \src "libresoc.v:166566.3-166584.6"
+ wire $0\xer_ca_ok$next[0:0]$8979
+ attribute \src "libresoc.v:166388.3-166389.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:166921.3-166939.6"
- wire width 2 $0\xer_ov$next[1:0]$9037
- attribute \src "libresoc.v:166718.3-166719.29"
+ attribute \src "libresoc.v:166585.3-166603.6"
+ wire width 2 $0\xer_ov$next[1:0]$8985
+ attribute \src "libresoc.v:166382.3-166383.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:166921.3-166939.6"
- wire $0\xer_ov_ok$next[0:0]$9038
- attribute \src "libresoc.v:166720.3-166721.35"
+ attribute \src "libresoc.v:166585.3-166603.6"
+ wire $0\xer_ov_ok$next[0:0]$8986
+ attribute \src "libresoc.v:166384.3-166385.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:166940.3-166958.6"
- wire $0\xer_so$next[0:0]$9043
- attribute \src "libresoc.v:166714.3-166715.29"
+ attribute \src "libresoc.v:166604.3-166622.6"
+ wire $0\xer_so$next[0:0]$8991
+ attribute \src "libresoc.v:166378.3-166379.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:166940.3-166958.6"
- wire $0\xer_so_ok$next[0:0]$9044
- attribute \src "libresoc.v:166716.3-166717.35"
+ attribute \src "libresoc.v:166604.3-166622.6"
+ wire $0\xer_so_ok$next[0:0]$8992
+ attribute \src "libresoc.v:166380.3-166381.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 4 $1\alu_op__data_len$next[3:0]$9074
- attribute \src "libresoc.v:165590.13-165590.36"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 4 $1\alu_op__data_len$next[3:0]$9022
+ attribute \src "libresoc.v:165254.13-165254.36"
wire width 4 $1\alu_op__data_len[3:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 14 $1\alu_op__fn_unit$next[13:0]$9075
- attribute \src "libresoc.v:165614.14-165614.40"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 14 $1\alu_op__fn_unit$next[13:0]$9023
+ attribute \src "libresoc.v:165278.14-165278.40"
wire width 14 $1\alu_op__fn_unit[13:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 64 $1\alu_op__imm_data__data$next[63:0]$9076
- attribute \src "libresoc.v:165653.14-165653.59"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 64 $1\alu_op__imm_data__data$next[63:0]$9024
+ attribute \src "libresoc.v:165317.14-165317.59"
wire width 64 $1\alu_op__imm_data__data[63:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__imm_data__ok$next[0:0]$9077
- attribute \src "libresoc.v:165662.7-165662.34"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__imm_data__ok$next[0:0]$9025
+ attribute \src "libresoc.v:165326.7-165326.34"
wire $1\alu_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 2 $1\alu_op__input_carry$next[1:0]$9078
- attribute \src "libresoc.v:165675.13-165675.39"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 2 $1\alu_op__input_carry$next[1:0]$9026
+ attribute \src "libresoc.v:165339.13-165339.39"
wire width 2 $1\alu_op__input_carry[1:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 32 $1\alu_op__insn$next[31:0]$9079
- attribute \src "libresoc.v:165692.14-165692.34"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 32 $1\alu_op__insn$next[31:0]$9027
+ attribute \src "libresoc.v:165356.14-165356.34"
wire width 32 $1\alu_op__insn[31:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 7 $1\alu_op__insn_type$next[6:0]$9080
- attribute \src "libresoc.v:165776.13-165776.38"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 7 $1\alu_op__insn_type$next[6:0]$9028
+ attribute \src "libresoc.v:165440.13-165440.38"
wire width 7 $1\alu_op__insn_type[6:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__invert_in$next[0:0]$9081
- attribute \src "libresoc.v:165935.7-165935.31"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__invert_in$next[0:0]$9029
+ attribute \src "libresoc.v:165599.7-165599.31"
wire $1\alu_op__invert_in[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__invert_out$next[0:0]$9082
- attribute \src "libresoc.v:165944.7-165944.32"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__invert_out$next[0:0]$9030
+ attribute \src "libresoc.v:165608.7-165608.32"
wire $1\alu_op__invert_out[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__is_32bit$next[0:0]$9083
- attribute \src "libresoc.v:165953.7-165953.30"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__is_32bit$next[0:0]$9031
+ attribute \src "libresoc.v:165617.7-165617.30"
wire $1\alu_op__is_32bit[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__is_signed$next[0:0]$9084
- attribute \src "libresoc.v:165962.7-165962.31"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__is_signed$next[0:0]$9032
+ attribute \src "libresoc.v:165626.7-165626.31"
wire $1\alu_op__is_signed[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__oe__oe$next[0:0]$9085
- attribute \src "libresoc.v:165971.7-165971.28"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__oe__oe$next[0:0]$9033
+ attribute \src "libresoc.v:165635.7-165635.28"
wire $1\alu_op__oe__oe[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__oe__ok$next[0:0]$9086
- attribute \src "libresoc.v:165980.7-165980.28"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__oe__ok$next[0:0]$9034
+ attribute \src "libresoc.v:165644.7-165644.28"
wire $1\alu_op__oe__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__output_carry$next[0:0]$9087
- attribute \src "libresoc.v:165989.7-165989.34"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__output_carry$next[0:0]$9035
+ attribute \src "libresoc.v:165653.7-165653.34"
wire $1\alu_op__output_carry[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__rc__ok$next[0:0]$9088
- attribute \src "libresoc.v:165998.7-165998.28"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__rc__ok$next[0:0]$9036
+ attribute \src "libresoc.v:165662.7-165662.28"
wire $1\alu_op__rc__ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__rc__rc$next[0:0]$9089
- attribute \src "libresoc.v:166007.7-166007.28"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__rc__rc$next[0:0]$9037
+ attribute \src "libresoc.v:165671.7-165671.28"
wire $1\alu_op__rc__rc[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__write_cr0$next[0:0]$9090
- attribute \src "libresoc.v:166016.7-166016.31"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__write_cr0$next[0:0]$9038
+ attribute \src "libresoc.v:165680.7-165680.31"
wire $1\alu_op__write_cr0[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $1\alu_op__zero_a$next[0:0]$9091
- attribute \src "libresoc.v:166025.7-166025.28"
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $1\alu_op__zero_a$next[0:0]$9039
+ attribute \src "libresoc.v:165689.7-165689.28"
wire $1\alu_op__zero_a[0:0]
- attribute \src "libresoc.v:166883.3-166901.6"
- wire width 4 $1\cr_a$next[3:0]$9027
- attribute \src "libresoc.v:166038.13-166038.24"
+ attribute \src "libresoc.v:166547.3-166565.6"
+ wire width 4 $1\cr_a$next[3:0]$8975
+ attribute \src "libresoc.v:165702.13-165702.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:166883.3-166901.6"
- wire $1\cr_a_ok$next[0:0]$9028
- attribute \src "libresoc.v:166045.7-166045.21"
+ attribute \src "libresoc.v:166547.3-166565.6"
+ wire $1\cr_a_ok$next[0:0]$8976
+ attribute \src "libresoc.v:165709.7-165709.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:166977.3-166989.6"
- wire width 2 $1\muxid$next[1:0]$9054
- attribute \src "libresoc.v:166622.13-166622.25"
+ attribute \src "libresoc.v:166641.3-166653.6"
+ wire width 2 $1\muxid$next[1:0]$9002
+ attribute \src "libresoc.v:166286.13-166286.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:167032.3-167050.6"
- wire width 64 $1\o$next[63:0]$9101
- attribute \src "libresoc.v:166637.14-166637.38"
+ attribute \src "libresoc.v:166696.3-166714.6"
+ wire width 64 $1\o$next[63:0]$9049
+ attribute \src "libresoc.v:166301.14-166301.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:167032.3-167050.6"
- wire $1\o_ok$next[0:0]$9102
- attribute \src "libresoc.v:166644.7-166644.18"
+ attribute \src "libresoc.v:166696.3-166714.6"
+ wire $1\o_ok$next[0:0]$9050
+ attribute \src "libresoc.v:166308.7-166308.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:166959.3-166976.6"
- wire $1\r_busy$next[0:0]$9050
- attribute \src "libresoc.v:166658.7-166658.20"
+ attribute \src "libresoc.v:166623.3-166640.6"
+ wire $1\r_busy$next[0:0]$8998
+ attribute \src "libresoc.v:166322.7-166322.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:166902.3-166920.6"
- wire width 2 $1\xer_ca$next[1:0]$9034
- attribute \src "libresoc.v:166667.13-166667.26"
+ attribute \src "libresoc.v:166566.3-166584.6"
+ wire width 2 $1\xer_ca$next[1:0]$8982
+ attribute \src "libresoc.v:166331.13-166331.26"
wire width 2 $1\xer_ca[1:0]
- attribute \src "libresoc.v:166902.3-166920.6"
- wire $1\xer_ca_ok$next[0:0]$9033
- attribute \src "libresoc.v:166676.7-166676.23"
+ attribute \src "libresoc.v:166566.3-166584.6"
+ wire $1\xer_ca_ok$next[0:0]$8981
+ attribute \src "libresoc.v:166340.7-166340.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:166921.3-166939.6"
- wire width 2 $1\xer_ov$next[1:0]$9039
- attribute \src "libresoc.v:166683.13-166683.26"
+ attribute \src "libresoc.v:166585.3-166603.6"
+ wire width 2 $1\xer_ov$next[1:0]$8987
+ attribute \src "libresoc.v:166347.13-166347.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:166921.3-166939.6"
- wire $1\xer_ov_ok$next[0:0]$9040
- attribute \src "libresoc.v:166690.7-166690.23"
+ attribute \src "libresoc.v:166585.3-166603.6"
+ wire $1\xer_ov_ok$next[0:0]$8988
+ attribute \src "libresoc.v:166354.7-166354.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:166940.3-166958.6"
- wire $1\xer_so$next[0:0]$9045
- attribute \src "libresoc.v:166697.7-166697.20"
+ attribute \src "libresoc.v:166604.3-166622.6"
+ wire $1\xer_so$next[0:0]$8993
+ attribute \src "libresoc.v:166361.7-166361.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:166940.3-166958.6"
- wire $1\xer_so_ok$next[0:0]$9046
- attribute \src "libresoc.v:166706.7-166706.23"
+ attribute \src "libresoc.v:166604.3-166622.6"
+ wire $1\xer_so_ok$next[0:0]$8994
+ attribute \src "libresoc.v:166370.7-166370.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:166990.3-167031.6"
- wire width 64 $2\alu_op__imm_data__data$next[63:0]$9092
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $2\alu_op__imm_data__ok$next[0:0]$9093
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $2\alu_op__oe__oe$next[0:0]$9094
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $2\alu_op__oe__ok$next[0:0]$9095
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $2\alu_op__rc__ok$next[0:0]$9096
- attribute \src "libresoc.v:166990.3-167031.6"
- wire $2\alu_op__rc__rc$next[0:0]$9097
- attribute \src "libresoc.v:166883.3-166901.6"
- wire $2\cr_a_ok$next[0:0]$9029
- attribute \src "libresoc.v:167032.3-167050.6"
- wire $2\o_ok$next[0:0]$9103
- attribute \src "libresoc.v:166959.3-166976.6"
- wire $2\r_busy$next[0:0]$9051
- attribute \src "libresoc.v:166902.3-166920.6"
- wire $2\xer_ca_ok$next[0:0]$9035
- attribute \src "libresoc.v:166921.3-166939.6"
- wire $2\xer_ov_ok$next[0:0]$9041
- attribute \src "libresoc.v:166940.3-166958.6"
- wire $2\xer_so_ok$next[0:0]$9047
- attribute \src "libresoc.v:166713.18-166713.118"
- wire $and$libresoc.v:166713$8993_Y
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire width 64 $2\alu_op__imm_data__data$next[63:0]$9040
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $2\alu_op__imm_data__ok$next[0:0]$9041
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $2\alu_op__oe__oe$next[0:0]$9042
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $2\alu_op__oe__ok$next[0:0]$9043
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $2\alu_op__rc__ok$next[0:0]$9044
+ attribute \src "libresoc.v:166654.3-166695.6"
+ wire $2\alu_op__rc__rc$next[0:0]$9045
+ attribute \src "libresoc.v:166547.3-166565.6"
+ wire $2\cr_a_ok$next[0:0]$8977
+ attribute \src "libresoc.v:166696.3-166714.6"
+ wire $2\o_ok$next[0:0]$9051
+ attribute \src "libresoc.v:166623.3-166640.6"
+ wire $2\r_busy$next[0:0]$8999
+ attribute \src "libresoc.v:166566.3-166584.6"
+ wire $2\xer_ca_ok$next[0:0]$8983
+ attribute \src "libresoc.v:166585.3-166603.6"
+ wire $2\xer_ov_ok$next[0:0]$8989
+ attribute \src "libresoc.v:166604.3-166622.6"
+ wire $2\xer_so_ok$next[0:0]$8995
+ attribute \src "libresoc.v:166377.18-166377.118"
+ wire $and$libresoc.v:166377$8941_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
wire \cr_a_ok$91
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:165585.7-165585.15"
+ attribute \src "libresoc.v:165249.7-165249.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_alu_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:166713$8993
+ cell $and $and$libresoc.v:166377$8941
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$66
connect \B \p_ready_o
- connect \Y $and$libresoc.v:166713$8993_Y
+ connect \Y $and$libresoc.v:166377$8941_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166774.11-166821.4"
+ attribute \src "libresoc.v:166438.11-166485.4"
cell \input \input
connect \alu_op__data_len \input_alu_op__data_len
connect \alu_op__data_len$18 \input_alu_op__data_len$39
connect \xer_so$22 \input_xer_so$43
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166822.8-166874.4"
+ attribute \src "libresoc.v:166486.8-166538.4"
cell \main \main
connect \alu_op__data_len \main_alu_op__data_len
connect \alu_op__data_len$18 \main_alu_op__data_len$62
connect \xer_so$21 \main_xer_so$65
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166875.9-166878.4"
+ attribute \src "libresoc.v:166539.9-166542.4"
cell \n$2 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166879.9-166882.4"
+ attribute \src "libresoc.v:166543.9-166546.4"
cell \p$1 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:165585.7-165585.20"
- process $proc$libresoc.v:165585$9104
+ attribute \src "libresoc.v:165249.7-165249.20"
+ process $proc$libresoc.v:165249$9052
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:165590.13-165590.36"
- process $proc$libresoc.v:165590$9105
+ attribute \src "libresoc.v:165254.13-165254.36"
+ process $proc$libresoc.v:165254$9053
assign { } { }
assign $1\alu_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_op__data_len $1\alu_op__data_len[3:0]
end
- attribute \src "libresoc.v:165614.14-165614.40"
- process $proc$libresoc.v:165614$9106
+ attribute \src "libresoc.v:165278.14-165278.40"
+ process $proc$libresoc.v:165278$9054
assign { } { }
assign $1\alu_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_op__fn_unit $1\alu_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:165653.14-165653.59"
- process $proc$libresoc.v:165653$9107
+ attribute \src "libresoc.v:165317.14-165317.59"
+ process $proc$libresoc.v:165317$9055
assign { } { }
assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:165662.7-165662.34"
- process $proc$libresoc.v:165662$9108
+ attribute \src "libresoc.v:165326.7-165326.34"
+ process $proc$libresoc.v:165326$9056
assign { } { }
assign $1\alu_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:165675.13-165675.39"
- process $proc$libresoc.v:165675$9109
+ attribute \src "libresoc.v:165339.13-165339.39"
+ process $proc$libresoc.v:165339$9057
assign { } { }
assign $1\alu_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_op__input_carry $1\alu_op__input_carry[1:0]
end
- attribute \src "libresoc.v:165692.14-165692.34"
- process $proc$libresoc.v:165692$9110
+ attribute \src "libresoc.v:165356.14-165356.34"
+ process $proc$libresoc.v:165356$9058
assign { } { }
assign $1\alu_op__insn[31:0] 0
sync always
sync init
update \alu_op__insn $1\alu_op__insn[31:0]
end
- attribute \src "libresoc.v:165776.13-165776.38"
- process $proc$libresoc.v:165776$9111
+ attribute \src "libresoc.v:165440.13-165440.38"
+ process $proc$libresoc.v:165440$9059
assign { } { }
assign $1\alu_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_op__insn_type $1\alu_op__insn_type[6:0]
end
- attribute \src "libresoc.v:165935.7-165935.31"
- process $proc$libresoc.v:165935$9112
+ attribute \src "libresoc.v:165599.7-165599.31"
+ process $proc$libresoc.v:165599$9060
assign { } { }
assign $1\alu_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_op__invert_in $1\alu_op__invert_in[0:0]
end
- attribute \src "libresoc.v:165944.7-165944.32"
- process $proc$libresoc.v:165944$9113
+ attribute \src "libresoc.v:165608.7-165608.32"
+ process $proc$libresoc.v:165608$9061
assign { } { }
assign $1\alu_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_op__invert_out $1\alu_op__invert_out[0:0]
end
- attribute \src "libresoc.v:165953.7-165953.30"
- process $proc$libresoc.v:165953$9114
+ attribute \src "libresoc.v:165617.7-165617.30"
+ process $proc$libresoc.v:165617$9062
assign { } { }
assign $1\alu_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_op__is_32bit $1\alu_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:165962.7-165962.31"
- process $proc$libresoc.v:165962$9115
+ attribute \src "libresoc.v:165626.7-165626.31"
+ process $proc$libresoc.v:165626$9063
assign { } { }
assign $1\alu_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_op__is_signed $1\alu_op__is_signed[0:0]
end
- attribute \src "libresoc.v:165971.7-165971.28"
- process $proc$libresoc.v:165971$9116
+ attribute \src "libresoc.v:165635.7-165635.28"
+ process $proc$libresoc.v:165635$9064
assign { } { }
assign $1\alu_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_op__oe__oe $1\alu_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:165980.7-165980.28"
- process $proc$libresoc.v:165980$9117
+ attribute \src "libresoc.v:165644.7-165644.28"
+ process $proc$libresoc.v:165644$9065
assign { } { }
assign $1\alu_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_op__oe__ok $1\alu_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:165989.7-165989.34"
- process $proc$libresoc.v:165989$9118
+ attribute \src "libresoc.v:165653.7-165653.34"
+ process $proc$libresoc.v:165653$9066
assign { } { }
assign $1\alu_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_op__output_carry $1\alu_op__output_carry[0:0]
end
- attribute \src "libresoc.v:165998.7-165998.28"
- process $proc$libresoc.v:165998$9119
+ attribute \src "libresoc.v:165662.7-165662.28"
+ process $proc$libresoc.v:165662$9067
assign { } { }
assign $1\alu_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_op__rc__ok $1\alu_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:166007.7-166007.28"
- process $proc$libresoc.v:166007$9120
+ attribute \src "libresoc.v:165671.7-165671.28"
+ process $proc$libresoc.v:165671$9068
assign { } { }
assign $1\alu_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_op__rc__rc $1\alu_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:166016.7-166016.31"
- process $proc$libresoc.v:166016$9121
+ attribute \src "libresoc.v:165680.7-165680.31"
+ process $proc$libresoc.v:165680$9069
assign { } { }
assign $1\alu_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:166025.7-166025.28"
- process $proc$libresoc.v:166025$9122
+ attribute \src "libresoc.v:165689.7-165689.28"
+ process $proc$libresoc.v:165689$9070
assign { } { }
assign $1\alu_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_op__zero_a $1\alu_op__zero_a[0:0]
end
- attribute \src "libresoc.v:166038.13-166038.24"
- process $proc$libresoc.v:166038$9123
+ attribute \src "libresoc.v:165702.13-165702.24"
+ process $proc$libresoc.v:165702$9071
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:166045.7-166045.21"
- process $proc$libresoc.v:166045$9124
+ attribute \src "libresoc.v:165709.7-165709.21"
+ process $proc$libresoc.v:165709$9072
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:166622.13-166622.25"
- process $proc$libresoc.v:166622$9125
+ attribute \src "libresoc.v:166286.13-166286.25"
+ process $proc$libresoc.v:166286$9073
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:166637.14-166637.38"
- process $proc$libresoc.v:166637$9126
+ attribute \src "libresoc.v:166301.14-166301.38"
+ process $proc$libresoc.v:166301$9074
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:166644.7-166644.18"
- process $proc$libresoc.v:166644$9127
+ attribute \src "libresoc.v:166308.7-166308.18"
+ process $proc$libresoc.v:166308$9075
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:166658.7-166658.20"
- process $proc$libresoc.v:166658$9128
+ attribute \src "libresoc.v:166322.7-166322.20"
+ process $proc$libresoc.v:166322$9076
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:166667.13-166667.26"
- process $proc$libresoc.v:166667$9129
+ attribute \src "libresoc.v:166331.13-166331.26"
+ process $proc$libresoc.v:166331$9077
assign { } { }
assign $1\xer_ca[1:0] 2'00
sync always
sync init
update \xer_ca $1\xer_ca[1:0]
end
- attribute \src "libresoc.v:166676.7-166676.23"
- process $proc$libresoc.v:166676$9130
+ attribute \src "libresoc.v:166340.7-166340.23"
+ process $proc$libresoc.v:166340$9078
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:166683.13-166683.26"
- process $proc$libresoc.v:166683$9131
+ attribute \src "libresoc.v:166347.13-166347.26"
+ process $proc$libresoc.v:166347$9079
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:166690.7-166690.23"
- process $proc$libresoc.v:166690$9132
+ attribute \src "libresoc.v:166354.7-166354.23"
+ process $proc$libresoc.v:166354$9080
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:166697.7-166697.20"
- process $proc$libresoc.v:166697$9133
+ attribute \src "libresoc.v:166361.7-166361.20"
+ process $proc$libresoc.v:166361$9081
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:166706.7-166706.23"
- process $proc$libresoc.v:166706$9134
+ attribute \src "libresoc.v:166370.7-166370.23"
+ process $proc$libresoc.v:166370$9082
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:166714.3-166715.29"
- process $proc$libresoc.v:166714$8994
+ attribute \src "libresoc.v:166378.3-166379.29"
+ process $proc$libresoc.v:166378$8942
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:166716.3-166717.35"
- process $proc$libresoc.v:166716$8995
+ attribute \src "libresoc.v:166380.3-166381.35"
+ process $proc$libresoc.v:166380$8943
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:166718.3-166719.29"
- process $proc$libresoc.v:166718$8996
+ attribute \src "libresoc.v:166382.3-166383.29"
+ process $proc$libresoc.v:166382$8944
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:166720.3-166721.35"
- process $proc$libresoc.v:166720$8997
+ attribute \src "libresoc.v:166384.3-166385.35"
+ process $proc$libresoc.v:166384$8945
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:166722.3-166723.29"
- process $proc$libresoc.v:166722$8998
+ attribute \src "libresoc.v:166386.3-166387.29"
+ process $proc$libresoc.v:166386$8946
assign { } { }
assign $0\xer_ca[1:0] \xer_ca$next
sync posedge \coresync_clk
update \xer_ca $0\xer_ca[1:0]
end
- attribute \src "libresoc.v:166724.3-166725.35"
- process $proc$libresoc.v:166724$8999
+ attribute \src "libresoc.v:166388.3-166389.35"
+ process $proc$libresoc.v:166388$8947
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:166726.3-166727.25"
- process $proc$libresoc.v:166726$9000
+ attribute \src "libresoc.v:166390.3-166391.25"
+ process $proc$libresoc.v:166390$8948
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:166728.3-166729.31"
- process $proc$libresoc.v:166728$9001
+ attribute \src "libresoc.v:166392.3-166393.31"
+ process $proc$libresoc.v:166392$8949
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:166730.3-166731.19"
- process $proc$libresoc.v:166730$9002
+ attribute \src "libresoc.v:166394.3-166395.19"
+ process $proc$libresoc.v:166394$8950
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:166732.3-166733.25"
- process $proc$libresoc.v:166732$9003
+ attribute \src "libresoc.v:166396.3-166397.25"
+ process $proc$libresoc.v:166396$8951
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:166734.3-166735.51"
- process $proc$libresoc.v:166734$9004
+ attribute \src "libresoc.v:166398.3-166399.51"
+ process $proc$libresoc.v:166398$8952
assign { } { }
assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next
sync posedge \coresync_clk
update \alu_op__insn_type $0\alu_op__insn_type[6:0]
end
- attribute \src "libresoc.v:166736.3-166737.47"
- process $proc$libresoc.v:166736$9005
+ attribute \src "libresoc.v:166400.3-166401.47"
+ process $proc$libresoc.v:166400$8953
assign { } { }
assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next
sync posedge \coresync_clk
update \alu_op__fn_unit $0\alu_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:166738.3-166739.61"
- process $proc$libresoc.v:166738$9006
+ attribute \src "libresoc.v:166402.3-166403.61"
+ process $proc$libresoc.v:166402$8954
assign { } { }
assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:166740.3-166741.57"
- process $proc$libresoc.v:166740$9007
+ attribute \src "libresoc.v:166404.3-166405.57"
+ process $proc$libresoc.v:166404$8955
assign { } { }
assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:166742.3-166743.45"
- process $proc$libresoc.v:166742$9008
+ attribute \src "libresoc.v:166406.3-166407.45"
+ process $proc$libresoc.v:166406$8956
assign { } { }
assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next
sync posedge \coresync_clk
update \alu_op__rc__rc $0\alu_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:166744.3-166745.45"
- process $proc$libresoc.v:166744$9009
+ attribute \src "libresoc.v:166408.3-166409.45"
+ process $proc$libresoc.v:166408$8957
assign { } { }
assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next
sync posedge \coresync_clk
update \alu_op__rc__ok $0\alu_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:166746.3-166747.45"
- process $proc$libresoc.v:166746$9010
+ attribute \src "libresoc.v:166410.3-166411.45"
+ process $proc$libresoc.v:166410$8958
assign { } { }
assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next
sync posedge \coresync_clk
update \alu_op__oe__oe $0\alu_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:166748.3-166749.45"
- process $proc$libresoc.v:166748$9011
+ attribute \src "libresoc.v:166412.3-166413.45"
+ process $proc$libresoc.v:166412$8959
assign { } { }
assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next
sync posedge \coresync_clk
update \alu_op__oe__ok $0\alu_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:166750.3-166751.51"
- process $proc$libresoc.v:166750$9012
+ attribute \src "libresoc.v:166414.3-166415.51"
+ process $proc$libresoc.v:166414$8960
assign { } { }
assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next
sync posedge \coresync_clk
update \alu_op__invert_in $0\alu_op__invert_in[0:0]
end
- attribute \src "libresoc.v:166752.3-166753.45"
- process $proc$libresoc.v:166752$9013
+ attribute \src "libresoc.v:166416.3-166417.45"
+ process $proc$libresoc.v:166416$8961
assign { } { }
assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next
sync posedge \coresync_clk
update \alu_op__zero_a $0\alu_op__zero_a[0:0]
end
- attribute \src "libresoc.v:166754.3-166755.53"
- process $proc$libresoc.v:166754$9014
+ attribute \src "libresoc.v:166418.3-166419.53"
+ process $proc$libresoc.v:166418$8962
assign { } { }
assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next
sync posedge \coresync_clk
update \alu_op__invert_out $0\alu_op__invert_out[0:0]
end
- attribute \src "libresoc.v:166756.3-166757.51"
- process $proc$libresoc.v:166756$9015
+ attribute \src "libresoc.v:166420.3-166421.51"
+ process $proc$libresoc.v:166420$8963
assign { } { }
assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next
sync posedge \coresync_clk
update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:166758.3-166759.55"
- process $proc$libresoc.v:166758$9016
+ attribute \src "libresoc.v:166422.3-166423.55"
+ process $proc$libresoc.v:166422$8964
assign { } { }
assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next
sync posedge \coresync_clk
update \alu_op__input_carry $0\alu_op__input_carry[1:0]
end
- attribute \src "libresoc.v:166760.3-166761.57"
- process $proc$libresoc.v:166760$9017
+ attribute \src "libresoc.v:166424.3-166425.57"
+ process $proc$libresoc.v:166424$8965
assign { } { }
assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next
sync posedge \coresync_clk
update \alu_op__output_carry $0\alu_op__output_carry[0:0]
end
- attribute \src "libresoc.v:166762.3-166763.49"
- process $proc$libresoc.v:166762$9018
+ attribute \src "libresoc.v:166426.3-166427.49"
+ process $proc$libresoc.v:166426$8966
assign { } { }
assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next
sync posedge \coresync_clk
update \alu_op__is_32bit $0\alu_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:166764.3-166765.51"
- process $proc$libresoc.v:166764$9019
+ attribute \src "libresoc.v:166428.3-166429.51"
+ process $proc$libresoc.v:166428$8967
assign { } { }
assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next
sync posedge \coresync_clk
update \alu_op__is_signed $0\alu_op__is_signed[0:0]
end
- attribute \src "libresoc.v:166766.3-166767.49"
- process $proc$libresoc.v:166766$9020
+ attribute \src "libresoc.v:166430.3-166431.49"
+ process $proc$libresoc.v:166430$8968
assign { } { }
assign $0\alu_op__data_len[3:0] \alu_op__data_len$next
sync posedge \coresync_clk
update \alu_op__data_len $0\alu_op__data_len[3:0]
end
- attribute \src "libresoc.v:166768.3-166769.41"
- process $proc$libresoc.v:166768$9021
+ attribute \src "libresoc.v:166432.3-166433.41"
+ process $proc$libresoc.v:166432$8969
assign { } { }
assign $0\alu_op__insn[31:0] \alu_op__insn$next
sync posedge \coresync_clk
update \alu_op__insn $0\alu_op__insn[31:0]
end
- attribute \src "libresoc.v:166770.3-166771.27"
- process $proc$libresoc.v:166770$9022
+ attribute \src "libresoc.v:166434.3-166435.27"
+ process $proc$libresoc.v:166434$8970
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:166772.3-166773.29"
- process $proc$libresoc.v:166772$9023
+ attribute \src "libresoc.v:166436.3-166437.29"
+ process $proc$libresoc.v:166436$8971
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:166883.3-166901.6"
- process $proc$libresoc.v:166883$9024
+ attribute \src "libresoc.v:166547.3-166565.6"
+ process $proc$libresoc.v:166547$8972
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9025 $1\cr_a$next[3:0]$9027
+ assign $0\cr_a$next[3:0]$8973 $1\cr_a$next[3:0]$8975
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9026 $2\cr_a_ok$next[0:0]$9029
- attribute \src "libresoc.v:166884.5-166884.29"
+ assign $0\cr_a_ok$next[0:0]$8974 $2\cr_a_ok$next[0:0]$8977
+ attribute \src "libresoc.v:166548.5-166548.29"
switch \initial
- attribute \src "libresoc.v:166884.9-166884.17"
+ attribute \src "libresoc.v:166548.9-166548.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9028 $1\cr_a$next[3:0]$9027 } { \cr_a_ok$91 \cr_a$90 }
+ assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9028 $1\cr_a$next[3:0]$9027 } { \cr_a_ok$91 \cr_a$90 }
+ assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 }
case
- assign $1\cr_a$next[3:0]$9027 \cr_a
- assign $1\cr_a_ok$next[0:0]$9028 \cr_a_ok
+ assign $1\cr_a$next[3:0]$8975 \cr_a
+ assign $1\cr_a_ok$next[0:0]$8976 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9029 1'0
+ assign $2\cr_a_ok$next[0:0]$8977 1'0
case
- assign $2\cr_a_ok$next[0:0]$9029 $1\cr_a_ok$next[0:0]$9028
+ assign $2\cr_a_ok$next[0:0]$8977 $1\cr_a_ok$next[0:0]$8976
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9025
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9026
+ update \cr_a$next $0\cr_a$next[3:0]$8973
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8974
end
- attribute \src "libresoc.v:166902.3-166920.6"
- process $proc$libresoc.v:166902$9030
+ attribute \src "libresoc.v:166566.3-166584.6"
+ process $proc$libresoc.v:166566$8978
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$next[1:0]$9032 $1\xer_ca$next[1:0]$9034
- assign $0\xer_ca_ok$next[0:0]$9031 $2\xer_ca_ok$next[0:0]$9035
- attribute \src "libresoc.v:166903.5-166903.29"
+ assign $0\xer_ca$next[1:0]$8980 $1\xer_ca$next[1:0]$8982
+ assign $0\xer_ca_ok$next[0:0]$8979 $2\xer_ca_ok$next[0:0]$8983
+ attribute \src "libresoc.v:166567.5-166567.29"
switch \initial
- attribute \src "libresoc.v:166903.9-166903.17"
+ attribute \src "libresoc.v:166567.9-166567.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9033 $1\xer_ca$next[1:0]$9034 } { \xer_ca_ok$93 \xer_ca$92 }
+ assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9033 $1\xer_ca$next[1:0]$9034 } { \xer_ca_ok$93 \xer_ca$92 }
+ assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 }
case
- assign $1\xer_ca_ok$next[0:0]$9033 \xer_ca_ok
- assign $1\xer_ca$next[1:0]$9034 \xer_ca
+ assign $1\xer_ca_ok$next[0:0]$8981 \xer_ca_ok
+ assign $1\xer_ca$next[1:0]$8982 \xer_ca
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$9035 1'0
+ assign $2\xer_ca_ok$next[0:0]$8983 1'0
case
- assign $2\xer_ca_ok$next[0:0]$9035 $1\xer_ca_ok$next[0:0]$9033
+ assign $2\xer_ca_ok$next[0:0]$8983 $1\xer_ca_ok$next[0:0]$8981
end
sync always
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9031
- update \xer_ca$next $0\xer_ca$next[1:0]$9032
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8979
+ update \xer_ca$next $0\xer_ca$next[1:0]$8980
end
- attribute \src "libresoc.v:166921.3-166939.6"
- process $proc$libresoc.v:166921$9036
+ attribute \src "libresoc.v:166585.3-166603.6"
+ process $proc$libresoc.v:166585$8984
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$9037 $1\xer_ov$next[1:0]$9039
+ assign $0\xer_ov$next[1:0]$8985 $1\xer_ov$next[1:0]$8987
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$9038 $2\xer_ov_ok$next[0:0]$9041
- attribute \src "libresoc.v:166922.5-166922.29"
+ assign $0\xer_ov_ok$next[0:0]$8986 $2\xer_ov_ok$next[0:0]$8989
+ attribute \src "libresoc.v:166586.5-166586.29"
switch \initial
- attribute \src "libresoc.v:166922.9-166922.17"
+ attribute \src "libresoc.v:166586.9-166586.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9040 $1\xer_ov$next[1:0]$9039 } { \xer_ov_ok$95 \xer_ov$94 }
+ assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9040 $1\xer_ov$next[1:0]$9039 } { \xer_ov_ok$95 \xer_ov$94 }
+ assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 }
case
- assign $1\xer_ov$next[1:0]$9039 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$9040 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$8987 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$8988 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$9041 1'0
+ assign $2\xer_ov_ok$next[0:0]$8989 1'0
case
- assign $2\xer_ov_ok$next[0:0]$9041 $1\xer_ov_ok$next[0:0]$9040
+ assign $2\xer_ov_ok$next[0:0]$8989 $1\xer_ov_ok$next[0:0]$8988
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$9037
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9038
+ update \xer_ov$next $0\xer_ov$next[1:0]$8985
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8986
end
- attribute \src "libresoc.v:166940.3-166958.6"
- process $proc$libresoc.v:166940$9042
+ attribute \src "libresoc.v:166604.3-166622.6"
+ process $proc$libresoc.v:166604$8990
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$9043 $1\xer_so$next[0:0]$9045
+ assign $0\xer_so$next[0:0]$8991 $1\xer_so$next[0:0]$8993
assign { } { }
- assign $0\xer_so_ok$next[0:0]$9044 $2\xer_so_ok$next[0:0]$9047
- attribute \src "libresoc.v:166941.5-166941.29"
+ assign $0\xer_so_ok$next[0:0]$8992 $2\xer_so_ok$next[0:0]$8995
+ attribute \src "libresoc.v:166605.5-166605.29"
switch \initial
- attribute \src "libresoc.v:166941.9-166941.17"
+ attribute \src "libresoc.v:166605.9-166605.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9046 $1\xer_so$next[0:0]$9045 } { \xer_so_ok$97 \xer_so$96 }
+ assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9046 $1\xer_so$next[0:0]$9045 } { \xer_so_ok$97 \xer_so$96 }
+ assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 }
case
- assign $1\xer_so$next[0:0]$9045 \xer_so
- assign $1\xer_so_ok$next[0:0]$9046 \xer_so_ok
+ assign $1\xer_so$next[0:0]$8993 \xer_so
+ assign $1\xer_so_ok$next[0:0]$8994 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9047 1'0
+ assign $2\xer_so_ok$next[0:0]$8995 1'0
case
- assign $2\xer_so_ok$next[0:0]$9047 $1\xer_so_ok$next[0:0]$9046
+ assign $2\xer_so_ok$next[0:0]$8995 $1\xer_so_ok$next[0:0]$8994
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$9043
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9044
+ update \xer_so$next $0\xer_so$next[0:0]$8991
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8992
end
- attribute \src "libresoc.v:166959.3-166976.6"
- process $proc$libresoc.v:166959$9048
+ attribute \src "libresoc.v:166623.3-166640.6"
+ process $proc$libresoc.v:166623$8996
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9049 $2\r_busy$next[0:0]$9051
- attribute \src "libresoc.v:166960.5-166960.29"
+ assign $0\r_busy$next[0:0]$8997 $2\r_busy$next[0:0]$8999
+ attribute \src "libresoc.v:166624.5-166624.29"
switch \initial
- attribute \src "libresoc.v:166960.9-166960.17"
+ attribute \src "libresoc.v:166624.9-166624.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9050 1'1
+ assign $1\r_busy$next[0:0]$8998 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9050 1'0
+ assign $1\r_busy$next[0:0]$8998 1'0
case
- assign $1\r_busy$next[0:0]$9050 \r_busy
+ assign $1\r_busy$next[0:0]$8998 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9051 1'0
+ assign $2\r_busy$next[0:0]$8999 1'0
case
- assign $2\r_busy$next[0:0]$9051 $1\r_busy$next[0:0]$9050
+ assign $2\r_busy$next[0:0]$8999 $1\r_busy$next[0:0]$8998
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9049
+ update \r_busy$next $0\r_busy$next[0:0]$8997
end
- attribute \src "libresoc.v:166977.3-166989.6"
- process $proc$libresoc.v:166977$9052
+ attribute \src "libresoc.v:166641.3-166653.6"
+ process $proc$libresoc.v:166641$9000
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9053 $1\muxid$next[1:0]$9054
- attribute \src "libresoc.v:166978.5-166978.29"
+ assign $0\muxid$next[1:0]$9001 $1\muxid$next[1:0]$9002
+ attribute \src "libresoc.v:166642.5-166642.29"
switch \initial
- attribute \src "libresoc.v:166978.9-166978.17"
+ attribute \src "libresoc.v:166642.9-166642.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9054 \muxid$69
+ assign $1\muxid$next[1:0]$9002 \muxid$69
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9054 \muxid$69
+ assign $1\muxid$next[1:0]$9002 \muxid$69
case
- assign $1\muxid$next[1:0]$9054 \muxid
+ assign $1\muxid$next[1:0]$9002 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9053
+ update \muxid$next $0\muxid$next[1:0]$9001
end
- attribute \src "libresoc.v:166990.3-167031.6"
- process $proc$libresoc.v:166990$9055
+ attribute \src "libresoc.v:166654.3-166695.6"
+ process $proc$libresoc.v:166654$9003
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_op__data_len$next[3:0]$9056 $1\alu_op__data_len$next[3:0]$9074
- assign $0\alu_op__fn_unit$next[13:0]$9057 $1\alu_op__fn_unit$next[13:0]$9075
+ assign $0\alu_op__data_len$next[3:0]$9004 $1\alu_op__data_len$next[3:0]$9022
+ assign $0\alu_op__fn_unit$next[13:0]$9005 $1\alu_op__fn_unit$next[13:0]$9023
assign { } { }
assign { } { }
- assign $0\alu_op__input_carry$next[1:0]$9060 $1\alu_op__input_carry$next[1:0]$9078
- assign $0\alu_op__insn$next[31:0]$9061 $1\alu_op__insn$next[31:0]$9079
- assign $0\alu_op__insn_type$next[6:0]$9062 $1\alu_op__insn_type$next[6:0]$9080
- assign $0\alu_op__invert_in$next[0:0]$9063 $1\alu_op__invert_in$next[0:0]$9081
- assign $0\alu_op__invert_out$next[0:0]$9064 $1\alu_op__invert_out$next[0:0]$9082
- assign $0\alu_op__is_32bit$next[0:0]$9065 $1\alu_op__is_32bit$next[0:0]$9083
- assign $0\alu_op__is_signed$next[0:0]$9066 $1\alu_op__is_signed$next[0:0]$9084
+ assign $0\alu_op__input_carry$next[1:0]$9008 $1\alu_op__input_carry$next[1:0]$9026
+ assign $0\alu_op__insn$next[31:0]$9009 $1\alu_op__insn$next[31:0]$9027
+ assign $0\alu_op__insn_type$next[6:0]$9010 $1\alu_op__insn_type$next[6:0]$9028
+ assign $0\alu_op__invert_in$next[0:0]$9011 $1\alu_op__invert_in$next[0:0]$9029
+ assign $0\alu_op__invert_out$next[0:0]$9012 $1\alu_op__invert_out$next[0:0]$9030
+ assign $0\alu_op__is_32bit$next[0:0]$9013 $1\alu_op__is_32bit$next[0:0]$9031
+ assign $0\alu_op__is_signed$next[0:0]$9014 $1\alu_op__is_signed$next[0:0]$9032
assign { } { }
assign { } { }
- assign $0\alu_op__output_carry$next[0:0]$9069 $1\alu_op__output_carry$next[0:0]$9087
+ assign $0\alu_op__output_carry$next[0:0]$9017 $1\alu_op__output_carry$next[0:0]$9035
assign { } { }
assign { } { }
- assign $0\alu_op__write_cr0$next[0:0]$9072 $1\alu_op__write_cr0$next[0:0]$9090
- assign $0\alu_op__zero_a$next[0:0]$9073 $1\alu_op__zero_a$next[0:0]$9091
- assign $0\alu_op__imm_data__data$next[63:0]$9058 $2\alu_op__imm_data__data$next[63:0]$9092
- assign $0\alu_op__imm_data__ok$next[0:0]$9059 $2\alu_op__imm_data__ok$next[0:0]$9093
- assign $0\alu_op__oe__oe$next[0:0]$9067 $2\alu_op__oe__oe$next[0:0]$9094
- assign $0\alu_op__oe__ok$next[0:0]$9068 $2\alu_op__oe__ok$next[0:0]$9095
- assign $0\alu_op__rc__ok$next[0:0]$9070 $2\alu_op__rc__ok$next[0:0]$9096
- assign $0\alu_op__rc__rc$next[0:0]$9071 $2\alu_op__rc__rc$next[0:0]$9097
- attribute \src "libresoc.v:166991.5-166991.29"
+ assign $0\alu_op__write_cr0$next[0:0]$9020 $1\alu_op__write_cr0$next[0:0]$9038
+ assign $0\alu_op__zero_a$next[0:0]$9021 $1\alu_op__zero_a$next[0:0]$9039
+ assign $0\alu_op__imm_data__data$next[63:0]$9006 $2\alu_op__imm_data__data$next[63:0]$9040
+ assign $0\alu_op__imm_data__ok$next[0:0]$9007 $2\alu_op__imm_data__ok$next[0:0]$9041
+ assign $0\alu_op__oe__oe$next[0:0]$9015 $2\alu_op__oe__oe$next[0:0]$9042
+ assign $0\alu_op__oe__ok$next[0:0]$9016 $2\alu_op__oe__ok$next[0:0]$9043
+ assign $0\alu_op__rc__ok$next[0:0]$9018 $2\alu_op__rc__ok$next[0:0]$9044
+ assign $0\alu_op__rc__rc$next[0:0]$9019 $2\alu_op__rc__rc$next[0:0]$9045
+ attribute \src "libresoc.v:166655.5-166655.29"
switch \initial
- attribute \src "libresoc.v:166991.9-166991.17"
+ attribute \src "libresoc.v:166655.9-166655.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$next[31:0]$9079 $1\alu_op__data_len$next[3:0]$9074 $1\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__output_carry$next[0:0]$9087 $1\alu_op__input_carry$next[1:0]$9078 $1\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__invert_out$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9091 $1\alu_op__invert_in$next[0:0]$9081 $1\alu_op__oe__ok$next[0:0]$9086 $1\alu_op__oe__oe$next[0:0]$9085 $1\alu_op__rc__ok$next[0:0]$9088 $1\alu_op__rc__rc$next[0:0]$9089 $1\alu_op__imm_data__ok$next[0:0]$9077 $1\alu_op__imm_data__data$next[63:0]$9076 $1\alu_op__fn_unit$next[13:0]$9075 $1\alu_op__insn_type$next[6:0]$9080 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
+ assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$next[31:0]$9079 $1\alu_op__data_len$next[3:0]$9074 $1\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__output_carry$next[0:0]$9087 $1\alu_op__input_carry$next[1:0]$9078 $1\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__invert_out$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9091 $1\alu_op__invert_in$next[0:0]$9081 $1\alu_op__oe__ok$next[0:0]$9086 $1\alu_op__oe__oe$next[0:0]$9085 $1\alu_op__rc__ok$next[0:0]$9088 $1\alu_op__rc__rc$next[0:0]$9089 $1\alu_op__imm_data__ok$next[0:0]$9077 $1\alu_op__imm_data__data$next[63:0]$9076 $1\alu_op__fn_unit$next[13:0]$9075 $1\alu_op__insn_type$next[6:0]$9080 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
+ assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
case
- assign $1\alu_op__data_len$next[3:0]$9074 \alu_op__data_len
- assign $1\alu_op__fn_unit$next[13:0]$9075 \alu_op__fn_unit
- assign $1\alu_op__imm_data__data$next[63:0]$9076 \alu_op__imm_data__data
- assign $1\alu_op__imm_data__ok$next[0:0]$9077 \alu_op__imm_data__ok
- assign $1\alu_op__input_carry$next[1:0]$9078 \alu_op__input_carry
- assign $1\alu_op__insn$next[31:0]$9079 \alu_op__insn
- assign $1\alu_op__insn_type$next[6:0]$9080 \alu_op__insn_type
- assign $1\alu_op__invert_in$next[0:0]$9081 \alu_op__invert_in
- assign $1\alu_op__invert_out$next[0:0]$9082 \alu_op__invert_out
- assign $1\alu_op__is_32bit$next[0:0]$9083 \alu_op__is_32bit
- assign $1\alu_op__is_signed$next[0:0]$9084 \alu_op__is_signed
- assign $1\alu_op__oe__oe$next[0:0]$9085 \alu_op__oe__oe
- assign $1\alu_op__oe__ok$next[0:0]$9086 \alu_op__oe__ok
- assign $1\alu_op__output_carry$next[0:0]$9087 \alu_op__output_carry
- assign $1\alu_op__rc__ok$next[0:0]$9088 \alu_op__rc__ok
- assign $1\alu_op__rc__rc$next[0:0]$9089 \alu_op__rc__rc
- assign $1\alu_op__write_cr0$next[0:0]$9090 \alu_op__write_cr0
- assign $1\alu_op__zero_a$next[0:0]$9091 \alu_op__zero_a
+ assign $1\alu_op__data_len$next[3:0]$9022 \alu_op__data_len
+ assign $1\alu_op__fn_unit$next[13:0]$9023 \alu_op__fn_unit
+ assign $1\alu_op__imm_data__data$next[63:0]$9024 \alu_op__imm_data__data
+ assign $1\alu_op__imm_data__ok$next[0:0]$9025 \alu_op__imm_data__ok
+ assign $1\alu_op__input_carry$next[1:0]$9026 \alu_op__input_carry
+ assign $1\alu_op__insn$next[31:0]$9027 \alu_op__insn
+ assign $1\alu_op__insn_type$next[6:0]$9028 \alu_op__insn_type
+ assign $1\alu_op__invert_in$next[0:0]$9029 \alu_op__invert_in
+ assign $1\alu_op__invert_out$next[0:0]$9030 \alu_op__invert_out
+ assign $1\alu_op__is_32bit$next[0:0]$9031 \alu_op__is_32bit
+ assign $1\alu_op__is_signed$next[0:0]$9032 \alu_op__is_signed
+ assign $1\alu_op__oe__oe$next[0:0]$9033 \alu_op__oe__oe
+ assign $1\alu_op__oe__ok$next[0:0]$9034 \alu_op__oe__ok
+ assign $1\alu_op__output_carry$next[0:0]$9035 \alu_op__output_carry
+ assign $1\alu_op__rc__ok$next[0:0]$9036 \alu_op__rc__ok
+ assign $1\alu_op__rc__rc$next[0:0]$9037 \alu_op__rc__rc
+ assign $1\alu_op__write_cr0$next[0:0]$9038 \alu_op__write_cr0
+ assign $1\alu_op__zero_a$next[0:0]$9039 \alu_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_op__imm_data__data$next[63:0]$9092 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_op__imm_data__ok$next[0:0]$9093 1'0
- assign $2\alu_op__rc__rc$next[0:0]$9097 1'0
- assign $2\alu_op__rc__ok$next[0:0]$9096 1'0
- assign $2\alu_op__oe__oe$next[0:0]$9094 1'0
- assign $2\alu_op__oe__ok$next[0:0]$9095 1'0
+ assign $2\alu_op__imm_data__data$next[63:0]$9040 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_op__imm_data__ok$next[0:0]$9041 1'0
+ assign $2\alu_op__rc__rc$next[0:0]$9045 1'0
+ assign $2\alu_op__rc__ok$next[0:0]$9044 1'0
+ assign $2\alu_op__oe__oe$next[0:0]$9042 1'0
+ assign $2\alu_op__oe__ok$next[0:0]$9043 1'0
case
- assign $2\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__imm_data__data$next[63:0]$9076
- assign $2\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__ok$next[0:0]$9077
- assign $2\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__oe__oe$next[0:0]$9085
- assign $2\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__ok$next[0:0]$9086
- assign $2\alu_op__rc__ok$next[0:0]$9096 $1\alu_op__rc__ok$next[0:0]$9088
- assign $2\alu_op__rc__rc$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9089
+ assign $2\alu_op__imm_data__data$next[63:0]$9040 $1\alu_op__imm_data__data$next[63:0]$9024
+ assign $2\alu_op__imm_data__ok$next[0:0]$9041 $1\alu_op__imm_data__ok$next[0:0]$9025
+ assign $2\alu_op__oe__oe$next[0:0]$9042 $1\alu_op__oe__oe$next[0:0]$9033
+ assign $2\alu_op__oe__ok$next[0:0]$9043 $1\alu_op__oe__ok$next[0:0]$9034
+ assign $2\alu_op__rc__ok$next[0:0]$9044 $1\alu_op__rc__ok$next[0:0]$9036
+ assign $2\alu_op__rc__rc$next[0:0]$9045 $1\alu_op__rc__rc$next[0:0]$9037
end
sync always
- update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9056
- update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9057
- update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9058
- update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9059
- update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9060
- update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9061
- update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9062
- update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9063
- update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9064
- update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9065
- update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9066
- update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9067
- update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9068
- update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9069
- update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9070
- update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9071
- update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9072
- update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9073
+ update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9004
+ update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9005
+ update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9006
+ update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9007
+ update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9008
+ update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9009
+ update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9010
+ update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9011
+ update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9012
+ update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9013
+ update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9014
+ update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9015
+ update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9016
+ update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9017
+ update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9018
+ update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9019
+ update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9020
+ update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9021
end
- attribute \src "libresoc.v:167032.3-167050.6"
- process $proc$libresoc.v:167032$9098
+ attribute \src "libresoc.v:166696.3-166714.6"
+ process $proc$libresoc.v:166696$9046
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9099 $1\o$next[63:0]$9101
+ assign $0\o$next[63:0]$9047 $1\o$next[63:0]$9049
assign { } { }
- assign $0\o_ok$next[0:0]$9100 $2\o_ok$next[0:0]$9103
- attribute \src "libresoc.v:167033.5-167033.29"
+ assign $0\o_ok$next[0:0]$9048 $2\o_ok$next[0:0]$9051
+ attribute \src "libresoc.v:166697.5-166697.29"
switch \initial
- attribute \src "libresoc.v:167033.9-167033.17"
+ attribute \src "libresoc.v:166697.9-166697.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9102 $1\o$next[63:0]$9101 } { \o_ok$89 \o$88 }
+ assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9102 $1\o$next[63:0]$9101 } { \o_ok$89 \o$88 }
+ assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 }
case
- assign $1\o$next[63:0]$9101 \o
- assign $1\o_ok$next[0:0]$9102 \o_ok
+ assign $1\o$next[63:0]$9049 \o
+ assign $1\o_ok$next[0:0]$9050 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9103 1'0
+ assign $2\o_ok$next[0:0]$9051 1'0
case
- assign $2\o_ok$next[0:0]$9103 $1\o_ok$next[0:0]$9102
+ assign $2\o_ok$next[0:0]$9051 $1\o_ok$next[0:0]$9050
end
sync always
- update \o$next $0\o$next[63:0]$9099
- update \o_ok$next $0\o_ok$next[0:0]$9100
+ update \o$next $0\o$next[63:0]$9047
+ update \o_ok$next $0\o_ok$next[0:0]$9048
end
- connect \$67 $and$libresoc.v:166713$8993_Y
+ connect \$67 $and$libresoc.v:166377$8941_Y
connect \xer_so_ok$98 1'0
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:167080.1-168516.10"
+attribute \src "libresoc.v:166744.1-168180.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1"
attribute \generator "nMigen"
module \pipe1$110
- attribute \src "libresoc.v:168449.3-168467.6"
- wire width 4 $0\cr_a$next[3:0]$9224
- attribute \src "libresoc.v:168191.3-168192.25"
+ attribute \src "libresoc.v:168113.3-168131.6"
+ wire width 4 $0\cr_a$next[3:0]$9172
+ attribute \src "libresoc.v:167855.3-167856.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:168449.3-168467.6"
- wire $0\cr_a_ok$next[0:0]$9225
- attribute \src "libresoc.v:168193.3-168194.31"
+ attribute \src "libresoc.v:168113.3-168131.6"
+ wire $0\cr_a_ok$next[0:0]$9173
+ attribute \src "libresoc.v:167857.3-167858.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:167081.7-167081.20"
+ attribute \src "libresoc.v:166745.7-166745.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:168376.3-168388.6"
- wire width 2 $0\muxid$next[1:0]$9174
- attribute \src "libresoc.v:168233.3-168234.27"
+ attribute \src "libresoc.v:168040.3-168052.6"
+ wire width 2 $0\muxid$next[1:0]$9122
+ attribute \src "libresoc.v:167897.3-167898.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:168430.3-168448.6"
- wire width 64 $0\o$next[63:0]$9218
- attribute \src "libresoc.v:168195.3-168196.19"
+ attribute \src "libresoc.v:168094.3-168112.6"
+ wire width 64 $0\o$next[63:0]$9166
+ attribute \src "libresoc.v:167859.3-167860.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:168430.3-168448.6"
- wire $0\o_ok$next[0:0]$9219
- attribute \src "libresoc.v:168197.3-168198.25"
+ attribute \src "libresoc.v:168094.3-168112.6"
+ wire $0\o_ok$next[0:0]$9167
+ attribute \src "libresoc.v:167861.3-167862.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:168358.3-168375.6"
- wire $0\r_busy$next[0:0]$9170
- attribute \src "libresoc.v:168235.3-168236.29"
+ attribute \src "libresoc.v:168022.3-168039.6"
+ wire $0\r_busy$next[0:0]$9118
+ attribute \src "libresoc.v:167899.3-167900.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 14 $0\sr_op__fn_unit$next[13:0]$9177
- attribute \src "libresoc.v:168201.3-168202.45"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 14 $0\sr_op__fn_unit$next[13:0]$9125
+ attribute \src "libresoc.v:167865.3-167866.45"
wire width 14 $0\sr_op__fn_unit[13:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 64 $0\sr_op__imm_data__data$next[63:0]$9178
- attribute \src "libresoc.v:168203.3-168204.59"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 64 $0\sr_op__imm_data__data$next[63:0]$9126
+ attribute \src "libresoc.v:167867.3-167868.59"
wire width 64 $0\sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__imm_data__ok$next[0:0]$9179
- attribute \src "libresoc.v:168205.3-168206.55"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__imm_data__ok$next[0:0]$9127
+ attribute \src "libresoc.v:167869.3-167870.55"
wire $0\sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 2 $0\sr_op__input_carry$next[1:0]$9180
- attribute \src "libresoc.v:168219.3-168220.53"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 2 $0\sr_op__input_carry$next[1:0]$9128
+ attribute \src "libresoc.v:167883.3-167884.53"
wire width 2 $0\sr_op__input_carry[1:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__input_cr$next[0:0]$9181
- attribute \src "libresoc.v:168223.3-168224.47"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__input_cr$next[0:0]$9129
+ attribute \src "libresoc.v:167887.3-167888.47"
wire $0\sr_op__input_cr[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 32 $0\sr_op__insn$next[31:0]$9182
- attribute \src "libresoc.v:168231.3-168232.39"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 32 $0\sr_op__insn$next[31:0]$9130
+ attribute \src "libresoc.v:167895.3-167896.39"
wire width 32 $0\sr_op__insn[31:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 7 $0\sr_op__insn_type$next[6:0]$9183
- attribute \src "libresoc.v:168199.3-168200.49"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 7 $0\sr_op__insn_type$next[6:0]$9131
+ attribute \src "libresoc.v:167863.3-167864.49"
wire width 7 $0\sr_op__insn_type[6:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__invert_in$next[0:0]$9184
- attribute \src "libresoc.v:168217.3-168218.49"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__invert_in$next[0:0]$9132
+ attribute \src "libresoc.v:167881.3-167882.49"
wire $0\sr_op__invert_in[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__is_32bit$next[0:0]$9185
- attribute \src "libresoc.v:168227.3-168228.47"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__is_32bit$next[0:0]$9133
+ attribute \src "libresoc.v:167891.3-167892.47"
wire $0\sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__is_signed$next[0:0]$9186
- attribute \src "libresoc.v:168229.3-168230.49"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__is_signed$next[0:0]$9134
+ attribute \src "libresoc.v:167893.3-167894.49"
wire $0\sr_op__is_signed[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__oe__oe$next[0:0]$9187
- attribute \src "libresoc.v:168211.3-168212.43"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__oe__oe$next[0:0]$9135
+ attribute \src "libresoc.v:167875.3-167876.43"
wire $0\sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__oe__ok$next[0:0]$9188
- attribute \src "libresoc.v:168213.3-168214.43"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__oe__ok$next[0:0]$9136
+ attribute \src "libresoc.v:167877.3-167878.43"
wire $0\sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__output_carry$next[0:0]$9189
- attribute \src "libresoc.v:168221.3-168222.55"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__output_carry$next[0:0]$9137
+ attribute \src "libresoc.v:167885.3-167886.55"
wire $0\sr_op__output_carry[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__output_cr$next[0:0]$9190
- attribute \src "libresoc.v:168225.3-168226.49"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__output_cr$next[0:0]$9138
+ attribute \src "libresoc.v:167889.3-167890.49"
wire $0\sr_op__output_cr[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__rc__ok$next[0:0]$9191
- attribute \src "libresoc.v:168209.3-168210.43"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__rc__ok$next[0:0]$9139
+ attribute \src "libresoc.v:167873.3-167874.43"
wire $0\sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__rc__rc$next[0:0]$9192
- attribute \src "libresoc.v:168207.3-168208.43"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__rc__rc$next[0:0]$9140
+ attribute \src "libresoc.v:167871.3-167872.43"
wire $0\sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $0\sr_op__write_cr0$next[0:0]$9193
- attribute \src "libresoc.v:168215.3-168216.49"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $0\sr_op__write_cr0$next[0:0]$9141
+ attribute \src "libresoc.v:167879.3-167880.49"
wire $0\sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:168339.3-168357.6"
- wire width 2 $0\xer_ca$next[1:0]$9165
- attribute \src "libresoc.v:168183.3-168184.29"
+ attribute \src "libresoc.v:168003.3-168021.6"
+ wire width 2 $0\xer_ca$next[1:0]$9113
+ attribute \src "libresoc.v:167847.3-167848.29"
wire width 2 $0\xer_ca[1:0]
- attribute \src "libresoc.v:168339.3-168357.6"
- wire $0\xer_ca_ok$next[0:0]$9164
- attribute \src "libresoc.v:168185.3-168186.35"
+ attribute \src "libresoc.v:168003.3-168021.6"
+ wire $0\xer_ca_ok$next[0:0]$9112
+ attribute \src "libresoc.v:167849.3-167850.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:168468.3-168486.6"
- wire $0\xer_so$next[0:0]$9230
- attribute \src "libresoc.v:168187.3-168188.29"
+ attribute \src "libresoc.v:168132.3-168150.6"
+ wire $0\xer_so$next[0:0]$9178
+ attribute \src "libresoc.v:167851.3-167852.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:168468.3-168486.6"
- wire $0\xer_so_ok$next[0:0]$9231
- attribute \src "libresoc.v:168189.3-168190.35"
+ attribute \src "libresoc.v:168132.3-168150.6"
+ wire $0\xer_so_ok$next[0:0]$9179
+ attribute \src "libresoc.v:167853.3-167854.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:168449.3-168467.6"
- wire width 4 $1\cr_a$next[3:0]$9226
- attribute \src "libresoc.v:167090.13-167090.24"
+ attribute \src "libresoc.v:168113.3-168131.6"
+ wire width 4 $1\cr_a$next[3:0]$9174
+ attribute \src "libresoc.v:166754.13-166754.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:168449.3-168467.6"
- wire $1\cr_a_ok$next[0:0]$9227
- attribute \src "libresoc.v:167099.7-167099.21"
+ attribute \src "libresoc.v:168113.3-168131.6"
+ wire $1\cr_a_ok$next[0:0]$9175
+ attribute \src "libresoc.v:166763.7-166763.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:168376.3-168388.6"
- wire width 2 $1\muxid$next[1:0]$9175
- attribute \src "libresoc.v:167664.13-167664.25"
+ attribute \src "libresoc.v:168040.3-168052.6"
+ wire width 2 $1\muxid$next[1:0]$9123
+ attribute \src "libresoc.v:167328.13-167328.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:168430.3-168448.6"
- wire width 64 $1\o$next[63:0]$9220
- attribute \src "libresoc.v:167679.14-167679.38"
+ attribute \src "libresoc.v:168094.3-168112.6"
+ wire width 64 $1\o$next[63:0]$9168
+ attribute \src "libresoc.v:167343.14-167343.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:168430.3-168448.6"
- wire $1\o_ok$next[0:0]$9221
- attribute \src "libresoc.v:167686.7-167686.18"
+ attribute \src "libresoc.v:168094.3-168112.6"
+ wire $1\o_ok$next[0:0]$9169
+ attribute \src "libresoc.v:167350.7-167350.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:168358.3-168375.6"
- wire $1\r_busy$next[0:0]$9171
- attribute \src "libresoc.v:167700.7-167700.20"
+ attribute \src "libresoc.v:168022.3-168039.6"
+ wire $1\r_busy$next[0:0]$9119
+ attribute \src "libresoc.v:167364.7-167364.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 14 $1\sr_op__fn_unit$next[13:0]$9194
- attribute \src "libresoc.v:167726.14-167726.39"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 14 $1\sr_op__fn_unit$next[13:0]$9142
+ attribute \src "libresoc.v:167390.14-167390.39"
wire width 14 $1\sr_op__fn_unit[13:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 64 $1\sr_op__imm_data__data$next[63:0]$9195
- attribute \src "libresoc.v:167765.14-167765.58"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 64 $1\sr_op__imm_data__data$next[63:0]$9143
+ attribute \src "libresoc.v:167429.14-167429.58"
wire width 64 $1\sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__imm_data__ok$next[0:0]$9196
- attribute \src "libresoc.v:167774.7-167774.33"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__imm_data__ok$next[0:0]$9144
+ attribute \src "libresoc.v:167438.7-167438.33"
wire $1\sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 2 $1\sr_op__input_carry$next[1:0]$9197
- attribute \src "libresoc.v:167787.13-167787.38"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 2 $1\sr_op__input_carry$next[1:0]$9145
+ attribute \src "libresoc.v:167451.13-167451.38"
wire width 2 $1\sr_op__input_carry[1:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__input_cr$next[0:0]$9198
- attribute \src "libresoc.v:167804.7-167804.29"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__input_cr$next[0:0]$9146
+ attribute \src "libresoc.v:167468.7-167468.29"
wire $1\sr_op__input_cr[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 32 $1\sr_op__insn$next[31:0]$9199
- attribute \src "libresoc.v:167813.14-167813.33"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 32 $1\sr_op__insn$next[31:0]$9147
+ attribute \src "libresoc.v:167477.14-167477.33"
wire width 32 $1\sr_op__insn[31:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 7 $1\sr_op__insn_type$next[6:0]$9200
- attribute \src "libresoc.v:167897.13-167897.37"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 7 $1\sr_op__insn_type$next[6:0]$9148
+ attribute \src "libresoc.v:167561.13-167561.37"
wire width 7 $1\sr_op__insn_type[6:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__invert_in$next[0:0]$9201
- attribute \src "libresoc.v:168056.7-168056.30"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__invert_in$next[0:0]$9149
+ attribute \src "libresoc.v:167720.7-167720.30"
wire $1\sr_op__invert_in[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__is_32bit$next[0:0]$9202
- attribute \src "libresoc.v:168065.7-168065.29"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__is_32bit$next[0:0]$9150
+ attribute \src "libresoc.v:167729.7-167729.29"
wire $1\sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__is_signed$next[0:0]$9203
- attribute \src "libresoc.v:168074.7-168074.30"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__is_signed$next[0:0]$9151
+ attribute \src "libresoc.v:167738.7-167738.30"
wire $1\sr_op__is_signed[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__oe__oe$next[0:0]$9204
- attribute \src "libresoc.v:168083.7-168083.27"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__oe__oe$next[0:0]$9152
+ attribute \src "libresoc.v:167747.7-167747.27"
wire $1\sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__oe__ok$next[0:0]$9205
- attribute \src "libresoc.v:168092.7-168092.27"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__oe__ok$next[0:0]$9153
+ attribute \src "libresoc.v:167756.7-167756.27"
wire $1\sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__output_carry$next[0:0]$9206
- attribute \src "libresoc.v:168101.7-168101.33"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__output_carry$next[0:0]$9154
+ attribute \src "libresoc.v:167765.7-167765.33"
wire $1\sr_op__output_carry[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__output_cr$next[0:0]$9207
- attribute \src "libresoc.v:168110.7-168110.30"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__output_cr$next[0:0]$9155
+ attribute \src "libresoc.v:167774.7-167774.30"
wire $1\sr_op__output_cr[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__rc__ok$next[0:0]$9208
- attribute \src "libresoc.v:168119.7-168119.27"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__rc__ok$next[0:0]$9156
+ attribute \src "libresoc.v:167783.7-167783.27"
wire $1\sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__rc__rc$next[0:0]$9209
- attribute \src "libresoc.v:168128.7-168128.27"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__rc__rc$next[0:0]$9157
+ attribute \src "libresoc.v:167792.7-167792.27"
wire $1\sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $1\sr_op__write_cr0$next[0:0]$9210
- attribute \src "libresoc.v:168137.7-168137.30"
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $1\sr_op__write_cr0$next[0:0]$9158
+ attribute \src "libresoc.v:167801.7-167801.30"
wire $1\sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:168339.3-168357.6"
- wire width 2 $1\xer_ca$next[1:0]$9167
- attribute \src "libresoc.v:168146.13-168146.26"
+ attribute \src "libresoc.v:168003.3-168021.6"
+ wire width 2 $1\xer_ca$next[1:0]$9115
+ attribute \src "libresoc.v:167810.13-167810.26"
wire width 2 $1\xer_ca[1:0]
- attribute \src "libresoc.v:168339.3-168357.6"
- wire $1\xer_ca_ok$next[0:0]$9166
- attribute \src "libresoc.v:168157.7-168157.23"
+ attribute \src "libresoc.v:168003.3-168021.6"
+ wire $1\xer_ca_ok$next[0:0]$9114
+ attribute \src "libresoc.v:167821.7-167821.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:168468.3-168486.6"
- wire $1\xer_so$next[0:0]$9232
- attribute \src "libresoc.v:168166.7-168166.20"
+ attribute \src "libresoc.v:168132.3-168150.6"
+ wire $1\xer_so$next[0:0]$9180
+ attribute \src "libresoc.v:167830.7-167830.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:168468.3-168486.6"
- wire $1\xer_so_ok$next[0:0]$9233
- attribute \src "libresoc.v:168175.7-168175.23"
+ attribute \src "libresoc.v:168132.3-168150.6"
+ wire $1\xer_so_ok$next[0:0]$9181
+ attribute \src "libresoc.v:167839.7-167839.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:168449.3-168467.6"
- wire $2\cr_a_ok$next[0:0]$9228
- attribute \src "libresoc.v:168430.3-168448.6"
- wire $2\o_ok$next[0:0]$9222
- attribute \src "libresoc.v:168358.3-168375.6"
- wire $2\r_busy$next[0:0]$9172
- attribute \src "libresoc.v:168389.3-168429.6"
- wire width 64 $2\sr_op__imm_data__data$next[63:0]$9211
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $2\sr_op__imm_data__ok$next[0:0]$9212
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $2\sr_op__oe__oe$next[0:0]$9213
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $2\sr_op__oe__ok$next[0:0]$9214
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $2\sr_op__rc__ok$next[0:0]$9215
- attribute \src "libresoc.v:168389.3-168429.6"
- wire $2\sr_op__rc__rc$next[0:0]$9216
- attribute \src "libresoc.v:168339.3-168357.6"
- wire $2\xer_ca_ok$next[0:0]$9168
- attribute \src "libresoc.v:168468.3-168486.6"
- wire $2\xer_so_ok$next[0:0]$9234
- attribute \src "libresoc.v:168182.18-168182.118"
- wire $and$libresoc.v:168182$9135_Y
+ attribute \src "libresoc.v:168113.3-168131.6"
+ wire $2\cr_a_ok$next[0:0]$9176
+ attribute \src "libresoc.v:168094.3-168112.6"
+ wire $2\o_ok$next[0:0]$9170
+ attribute \src "libresoc.v:168022.3-168039.6"
+ wire $2\r_busy$next[0:0]$9120
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire width 64 $2\sr_op__imm_data__data$next[63:0]$9159
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $2\sr_op__imm_data__ok$next[0:0]$9160
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $2\sr_op__oe__oe$next[0:0]$9161
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $2\sr_op__oe__ok$next[0:0]$9162
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $2\sr_op__rc__ok$next[0:0]$9163
+ attribute \src "libresoc.v:168053.3-168093.6"
+ wire $2\sr_op__rc__rc$next[0:0]$9164
+ attribute \src "libresoc.v:168003.3-168021.6"
+ wire $2\xer_ca_ok$next[0:0]$9116
+ attribute \src "libresoc.v:168132.3-168150.6"
+ wire $2\xer_so_ok$next[0:0]$9182
+ attribute \src "libresoc.v:167846.18-167846.118"
+ wire $and$libresoc.v:167846$9083_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 55 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 24 \cr_a
wire \cr_a_ok$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:167081.7-167081.15"
+ attribute \src "libresoc.v:166745.7-166745.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \input_muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:168182$9135
+ cell $and $and$libresoc.v:167846$9083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$64
connect \B \p_ready_o
- connect \Y $and$libresoc.v:168182$9135_Y
+ connect \Y $and$libresoc.v:167846$9083_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168237.15-168284.4"
+ attribute \src "libresoc.v:167901.15-167948.4"
cell \input$113 \input
connect \muxid \input_muxid
connect \muxid$1 \input_muxid$21
connect \xer_so$22 \input_xer_so$42
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168285.14-168330.4"
+ attribute \src "libresoc.v:167949.14-167994.4"
cell \main$114 \main
connect \muxid \main_muxid
connect \muxid$1 \main_muxid$44
connect \xer_so$19 \main_xer_so$62
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168331.11-168334.4"
+ attribute \src "libresoc.v:167995.11-167998.4"
cell \n$112 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168335.11-168338.4"
+ attribute \src "libresoc.v:167999.11-168002.4"
cell \p$111 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:167081.7-167081.20"
- process $proc$libresoc.v:167081$9235
+ attribute \src "libresoc.v:166745.7-166745.20"
+ process $proc$libresoc.v:166745$9183
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:167090.13-167090.24"
- process $proc$libresoc.v:167090$9236
+ attribute \src "libresoc.v:166754.13-166754.24"
+ process $proc$libresoc.v:166754$9184
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:167099.7-167099.21"
- process $proc$libresoc.v:167099$9237
+ attribute \src "libresoc.v:166763.7-166763.21"
+ process $proc$libresoc.v:166763$9185
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:167664.13-167664.25"
- process $proc$libresoc.v:167664$9238
+ attribute \src "libresoc.v:167328.13-167328.25"
+ process $proc$libresoc.v:167328$9186
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:167679.14-167679.38"
- process $proc$libresoc.v:167679$9239
+ attribute \src "libresoc.v:167343.14-167343.38"
+ process $proc$libresoc.v:167343$9187
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:167686.7-167686.18"
- process $proc$libresoc.v:167686$9240
+ attribute \src "libresoc.v:167350.7-167350.18"
+ process $proc$libresoc.v:167350$9188
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:167700.7-167700.20"
- process $proc$libresoc.v:167700$9241
+ attribute \src "libresoc.v:167364.7-167364.20"
+ process $proc$libresoc.v:167364$9189
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:167726.14-167726.39"
- process $proc$libresoc.v:167726$9242
+ attribute \src "libresoc.v:167390.14-167390.39"
+ process $proc$libresoc.v:167390$9190
assign { } { }
assign $1\sr_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \sr_op__fn_unit $1\sr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:167765.14-167765.58"
- process $proc$libresoc.v:167765$9243
+ attribute \src "libresoc.v:167429.14-167429.58"
+ process $proc$libresoc.v:167429$9191
assign { } { }
assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:167774.7-167774.33"
- process $proc$libresoc.v:167774$9244
+ attribute \src "libresoc.v:167438.7-167438.33"
+ process $proc$libresoc.v:167438$9192
assign { } { }
assign $1\sr_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:167787.13-167787.38"
- process $proc$libresoc.v:167787$9245
+ attribute \src "libresoc.v:167451.13-167451.38"
+ process $proc$libresoc.v:167451$9193
assign { } { }
assign $1\sr_op__input_carry[1:0] 2'00
sync always
sync init
update \sr_op__input_carry $1\sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:167804.7-167804.29"
- process $proc$libresoc.v:167804$9246
+ attribute \src "libresoc.v:167468.7-167468.29"
+ process $proc$libresoc.v:167468$9194
assign { } { }
assign $1\sr_op__input_cr[0:0] 1'0
sync always
sync init
update \sr_op__input_cr $1\sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:167813.14-167813.33"
- process $proc$libresoc.v:167813$9247
+ attribute \src "libresoc.v:167477.14-167477.33"
+ process $proc$libresoc.v:167477$9195
assign { } { }
assign $1\sr_op__insn[31:0] 0
sync always
sync init
update \sr_op__insn $1\sr_op__insn[31:0]
end
- attribute \src "libresoc.v:167897.13-167897.37"
- process $proc$libresoc.v:167897$9248
+ attribute \src "libresoc.v:167561.13-167561.37"
+ process $proc$libresoc.v:167561$9196
assign { } { }
assign $1\sr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \sr_op__insn_type $1\sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:168056.7-168056.30"
- process $proc$libresoc.v:168056$9249
+ attribute \src "libresoc.v:167720.7-167720.30"
+ process $proc$libresoc.v:167720$9197
assign { } { }
assign $1\sr_op__invert_in[0:0] 1'0
sync always
sync init
update \sr_op__invert_in $1\sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:168065.7-168065.29"
- process $proc$libresoc.v:168065$9250
+ attribute \src "libresoc.v:167729.7-167729.29"
+ process $proc$libresoc.v:167729$9198
assign { } { }
assign $1\sr_op__is_32bit[0:0] 1'0
sync always
sync init
update \sr_op__is_32bit $1\sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:168074.7-168074.30"
- process $proc$libresoc.v:168074$9251
+ attribute \src "libresoc.v:167738.7-167738.30"
+ process $proc$libresoc.v:167738$9199
assign { } { }
assign $1\sr_op__is_signed[0:0] 1'0
sync always
sync init
update \sr_op__is_signed $1\sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:168083.7-168083.27"
- process $proc$libresoc.v:168083$9252
+ attribute \src "libresoc.v:167747.7-167747.27"
+ process $proc$libresoc.v:167747$9200
assign { } { }
assign $1\sr_op__oe__oe[0:0] 1'0
sync always
sync init
update \sr_op__oe__oe $1\sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:168092.7-168092.27"
- process $proc$libresoc.v:168092$9253
+ attribute \src "libresoc.v:167756.7-167756.27"
+ process $proc$libresoc.v:167756$9201
assign { } { }
assign $1\sr_op__oe__ok[0:0] 1'0
sync always
sync init
update \sr_op__oe__ok $1\sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:168101.7-168101.33"
- process $proc$libresoc.v:168101$9254
+ attribute \src "libresoc.v:167765.7-167765.33"
+ process $proc$libresoc.v:167765$9202
assign { } { }
assign $1\sr_op__output_carry[0:0] 1'0
sync always
sync init
update \sr_op__output_carry $1\sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:168110.7-168110.30"
- process $proc$libresoc.v:168110$9255
+ attribute \src "libresoc.v:167774.7-167774.30"
+ process $proc$libresoc.v:167774$9203
assign { } { }
assign $1\sr_op__output_cr[0:0] 1'0
sync always
sync init
update \sr_op__output_cr $1\sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:168119.7-168119.27"
- process $proc$libresoc.v:168119$9256
+ attribute \src "libresoc.v:167783.7-167783.27"
+ process $proc$libresoc.v:167783$9204
assign { } { }
assign $1\sr_op__rc__ok[0:0] 1'0
sync always
sync init
update \sr_op__rc__ok $1\sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:168128.7-168128.27"
- process $proc$libresoc.v:168128$9257
+ attribute \src "libresoc.v:167792.7-167792.27"
+ process $proc$libresoc.v:167792$9205
assign { } { }
assign $1\sr_op__rc__rc[0:0] 1'0
sync always
sync init
update \sr_op__rc__rc $1\sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:168137.7-168137.30"
- process $proc$libresoc.v:168137$9258
+ attribute \src "libresoc.v:167801.7-167801.30"
+ process $proc$libresoc.v:167801$9206
assign { } { }
assign $1\sr_op__write_cr0[0:0] 1'0
sync always
sync init
update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:168146.13-168146.26"
- process $proc$libresoc.v:168146$9259
+ attribute \src "libresoc.v:167810.13-167810.26"
+ process $proc$libresoc.v:167810$9207
assign { } { }
assign $1\xer_ca[1:0] 2'00
sync always
sync init
update \xer_ca $1\xer_ca[1:0]
end
- attribute \src "libresoc.v:168157.7-168157.23"
- process $proc$libresoc.v:168157$9260
+ attribute \src "libresoc.v:167821.7-167821.23"
+ process $proc$libresoc.v:167821$9208
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:168166.7-168166.20"
- process $proc$libresoc.v:168166$9261
+ attribute \src "libresoc.v:167830.7-167830.20"
+ process $proc$libresoc.v:167830$9209
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:168175.7-168175.23"
- process $proc$libresoc.v:168175$9262
+ attribute \src "libresoc.v:167839.7-167839.23"
+ process $proc$libresoc.v:167839$9210
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:168183.3-168184.29"
- process $proc$libresoc.v:168183$9136
+ attribute \src "libresoc.v:167847.3-167848.29"
+ process $proc$libresoc.v:167847$9084
assign { } { }
assign $0\xer_ca[1:0] \xer_ca$next
sync posedge \coresync_clk
update \xer_ca $0\xer_ca[1:0]
end
- attribute \src "libresoc.v:168185.3-168186.35"
- process $proc$libresoc.v:168185$9137
+ attribute \src "libresoc.v:167849.3-167850.35"
+ process $proc$libresoc.v:167849$9085
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:168187.3-168188.29"
- process $proc$libresoc.v:168187$9138
+ attribute \src "libresoc.v:167851.3-167852.29"
+ process $proc$libresoc.v:167851$9086
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:168189.3-168190.35"
- process $proc$libresoc.v:168189$9139
+ attribute \src "libresoc.v:167853.3-167854.35"
+ process $proc$libresoc.v:167853$9087
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:168191.3-168192.25"
- process $proc$libresoc.v:168191$9140
+ attribute \src "libresoc.v:167855.3-167856.25"
+ process $proc$libresoc.v:167855$9088
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:168193.3-168194.31"
- process $proc$libresoc.v:168193$9141
+ attribute \src "libresoc.v:167857.3-167858.31"
+ process $proc$libresoc.v:167857$9089
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:168195.3-168196.19"
- process $proc$libresoc.v:168195$9142
+ attribute \src "libresoc.v:167859.3-167860.19"
+ process $proc$libresoc.v:167859$9090
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:168197.3-168198.25"
- process $proc$libresoc.v:168197$9143
+ attribute \src "libresoc.v:167861.3-167862.25"
+ process $proc$libresoc.v:167861$9091
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:168199.3-168200.49"
- process $proc$libresoc.v:168199$9144
+ attribute \src "libresoc.v:167863.3-167864.49"
+ process $proc$libresoc.v:167863$9092
assign { } { }
assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next
sync posedge \coresync_clk
update \sr_op__insn_type $0\sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:168201.3-168202.45"
- process $proc$libresoc.v:168201$9145
+ attribute \src "libresoc.v:167865.3-167866.45"
+ process $proc$libresoc.v:167865$9093
assign { } { }
assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next
sync posedge \coresync_clk
update \sr_op__fn_unit $0\sr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:168203.3-168204.59"
- process $proc$libresoc.v:168203$9146
+ attribute \src "libresoc.v:167867.3-167868.59"
+ process $proc$libresoc.v:167867$9094
assign { } { }
assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next
sync posedge \coresync_clk
update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:168205.3-168206.55"
- process $proc$libresoc.v:168205$9147
+ attribute \src "libresoc.v:167869.3-167870.55"
+ process $proc$libresoc.v:167869$9095
assign { } { }
assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next
sync posedge \coresync_clk
update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:168207.3-168208.43"
- process $proc$libresoc.v:168207$9148
+ attribute \src "libresoc.v:167871.3-167872.43"
+ process $proc$libresoc.v:167871$9096
assign { } { }
assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next
sync posedge \coresync_clk
update \sr_op__rc__rc $0\sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:168209.3-168210.43"
- process $proc$libresoc.v:168209$9149
+ attribute \src "libresoc.v:167873.3-167874.43"
+ process $proc$libresoc.v:167873$9097
assign { } { }
assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next
sync posedge \coresync_clk
update \sr_op__rc__ok $0\sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:168211.3-168212.43"
- process $proc$libresoc.v:168211$9150
+ attribute \src "libresoc.v:167875.3-167876.43"
+ process $proc$libresoc.v:167875$9098
assign { } { }
assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next
sync posedge \coresync_clk
update \sr_op__oe__oe $0\sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:168213.3-168214.43"
- process $proc$libresoc.v:168213$9151
+ attribute \src "libresoc.v:167877.3-167878.43"
+ process $proc$libresoc.v:167877$9099
assign { } { }
assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next
sync posedge \coresync_clk
update \sr_op__oe__ok $0\sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:168215.3-168216.49"
- process $proc$libresoc.v:168215$9152
+ attribute \src "libresoc.v:167879.3-167880.49"
+ process $proc$libresoc.v:167879$9100
assign { } { }
assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next
sync posedge \coresync_clk
update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:168217.3-168218.49"
- process $proc$libresoc.v:168217$9153
+ attribute \src "libresoc.v:167881.3-167882.49"
+ process $proc$libresoc.v:167881$9101
assign { } { }
assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next
sync posedge \coresync_clk
update \sr_op__invert_in $0\sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:168219.3-168220.53"
- process $proc$libresoc.v:168219$9154
+ attribute \src "libresoc.v:167883.3-167884.53"
+ process $proc$libresoc.v:167883$9102
assign { } { }
assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next
sync posedge \coresync_clk
update \sr_op__input_carry $0\sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:168221.3-168222.55"
- process $proc$libresoc.v:168221$9155
+ attribute \src "libresoc.v:167885.3-167886.55"
+ process $proc$libresoc.v:167885$9103
assign { } { }
assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next
sync posedge \coresync_clk
update \sr_op__output_carry $0\sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:168223.3-168224.47"
- process $proc$libresoc.v:168223$9156
+ attribute \src "libresoc.v:167887.3-167888.47"
+ process $proc$libresoc.v:167887$9104
assign { } { }
assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next
sync posedge \coresync_clk
update \sr_op__input_cr $0\sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:168225.3-168226.49"
- process $proc$libresoc.v:168225$9157
+ attribute \src "libresoc.v:167889.3-167890.49"
+ process $proc$libresoc.v:167889$9105
assign { } { }
assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next
sync posedge \coresync_clk
update \sr_op__output_cr $0\sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:168227.3-168228.47"
- process $proc$libresoc.v:168227$9158
+ attribute \src "libresoc.v:167891.3-167892.47"
+ process $proc$libresoc.v:167891$9106
assign { } { }
assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next
sync posedge \coresync_clk
update \sr_op__is_32bit $0\sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:168229.3-168230.49"
- process $proc$libresoc.v:168229$9159
+ attribute \src "libresoc.v:167893.3-167894.49"
+ process $proc$libresoc.v:167893$9107
assign { } { }
assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next
sync posedge \coresync_clk
update \sr_op__is_signed $0\sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:168231.3-168232.39"
- process $proc$libresoc.v:168231$9160
+ attribute \src "libresoc.v:167895.3-167896.39"
+ process $proc$libresoc.v:167895$9108
assign { } { }
assign $0\sr_op__insn[31:0] \sr_op__insn$next
sync posedge \coresync_clk
update \sr_op__insn $0\sr_op__insn[31:0]
end
- attribute \src "libresoc.v:168233.3-168234.27"
- process $proc$libresoc.v:168233$9161
+ attribute \src "libresoc.v:167897.3-167898.27"
+ process $proc$libresoc.v:167897$9109
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:168235.3-168236.29"
- process $proc$libresoc.v:168235$9162
+ attribute \src "libresoc.v:167899.3-167900.29"
+ process $proc$libresoc.v:167899$9110
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:168339.3-168357.6"
- process $proc$libresoc.v:168339$9163
+ attribute \src "libresoc.v:168003.3-168021.6"
+ process $proc$libresoc.v:168003$9111
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$next[1:0]$9165 $1\xer_ca$next[1:0]$9167
- assign $0\xer_ca_ok$next[0:0]$9164 $2\xer_ca_ok$next[0:0]$9168
- attribute \src "libresoc.v:168340.5-168340.29"
+ assign $0\xer_ca$next[1:0]$9113 $1\xer_ca$next[1:0]$9115
+ assign $0\xer_ca_ok$next[0:0]$9112 $2\xer_ca_ok$next[0:0]$9116
+ attribute \src "libresoc.v:168004.5-168004.29"
switch \initial
- attribute \src "libresoc.v:168340.9-168340.17"
+ attribute \src "libresoc.v:168004.9-168004.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9166 $1\xer_ca$next[1:0]$9167 } { \xer_ca_ok$95 \xer_ca$94 }
+ assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9166 $1\xer_ca$next[1:0]$9167 } { \xer_ca_ok$95 \xer_ca$94 }
+ assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 }
case
- assign $1\xer_ca_ok$next[0:0]$9166 \xer_ca_ok
- assign $1\xer_ca$next[1:0]$9167 \xer_ca
+ assign $1\xer_ca_ok$next[0:0]$9114 \xer_ca_ok
+ assign $1\xer_ca$next[1:0]$9115 \xer_ca
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$9168 1'0
+ assign $2\xer_ca_ok$next[0:0]$9116 1'0
case
- assign $2\xer_ca_ok$next[0:0]$9168 $1\xer_ca_ok$next[0:0]$9166
+ assign $2\xer_ca_ok$next[0:0]$9116 $1\xer_ca_ok$next[0:0]$9114
end
sync always
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9164
- update \xer_ca$next $0\xer_ca$next[1:0]$9165
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9112
+ update \xer_ca$next $0\xer_ca$next[1:0]$9113
end
- attribute \src "libresoc.v:168358.3-168375.6"
- process $proc$libresoc.v:168358$9169
+ attribute \src "libresoc.v:168022.3-168039.6"
+ process $proc$libresoc.v:168022$9117
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9170 $2\r_busy$next[0:0]$9172
- attribute \src "libresoc.v:168359.5-168359.29"
+ assign $0\r_busy$next[0:0]$9118 $2\r_busy$next[0:0]$9120
+ attribute \src "libresoc.v:168023.5-168023.29"
switch \initial
- attribute \src "libresoc.v:168359.9-168359.17"
+ attribute \src "libresoc.v:168023.9-168023.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9171 1'1
+ assign $1\r_busy$next[0:0]$9119 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9171 1'0
+ assign $1\r_busy$next[0:0]$9119 1'0
case
- assign $1\r_busy$next[0:0]$9171 \r_busy
+ assign $1\r_busy$next[0:0]$9119 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9172 1'0
+ assign $2\r_busy$next[0:0]$9120 1'0
case
- assign $2\r_busy$next[0:0]$9172 $1\r_busy$next[0:0]$9171
+ assign $2\r_busy$next[0:0]$9120 $1\r_busy$next[0:0]$9119
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9170
+ update \r_busy$next $0\r_busy$next[0:0]$9118
end
- attribute \src "libresoc.v:168376.3-168388.6"
- process $proc$libresoc.v:168376$9173
+ attribute \src "libresoc.v:168040.3-168052.6"
+ process $proc$libresoc.v:168040$9121
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9174 $1\muxid$next[1:0]$9175
- attribute \src "libresoc.v:168377.5-168377.29"
+ assign $0\muxid$next[1:0]$9122 $1\muxid$next[1:0]$9123
+ attribute \src "libresoc.v:168041.5-168041.29"
switch \initial
- attribute \src "libresoc.v:168377.9-168377.17"
+ attribute \src "libresoc.v:168041.9-168041.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9175 \muxid$67
+ assign $1\muxid$next[1:0]$9123 \muxid$67
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9175 \muxid$67
+ assign $1\muxid$next[1:0]$9123 \muxid$67
case
- assign $1\muxid$next[1:0]$9175 \muxid
+ assign $1\muxid$next[1:0]$9123 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9174
+ update \muxid$next $0\muxid$next[1:0]$9122
end
- attribute \src "libresoc.v:168389.3-168429.6"
- process $proc$libresoc.v:168389$9176
+ attribute \src "libresoc.v:168053.3-168093.6"
+ process $proc$libresoc.v:168053$9124
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr_op__fn_unit$next[13:0]$9177 $1\sr_op__fn_unit$next[13:0]$9194
+ assign $0\sr_op__fn_unit$next[13:0]$9125 $1\sr_op__fn_unit$next[13:0]$9142
assign { } { }
assign { } { }
- assign $0\sr_op__input_carry$next[1:0]$9180 $1\sr_op__input_carry$next[1:0]$9197
- assign $0\sr_op__input_cr$next[0:0]$9181 $1\sr_op__input_cr$next[0:0]$9198
- assign $0\sr_op__insn$next[31:0]$9182 $1\sr_op__insn$next[31:0]$9199
- assign $0\sr_op__insn_type$next[6:0]$9183 $1\sr_op__insn_type$next[6:0]$9200
- assign $0\sr_op__invert_in$next[0:0]$9184 $1\sr_op__invert_in$next[0:0]$9201
- assign $0\sr_op__is_32bit$next[0:0]$9185 $1\sr_op__is_32bit$next[0:0]$9202
- assign $0\sr_op__is_signed$next[0:0]$9186 $1\sr_op__is_signed$next[0:0]$9203
+ assign $0\sr_op__input_carry$next[1:0]$9128 $1\sr_op__input_carry$next[1:0]$9145
+ assign $0\sr_op__input_cr$next[0:0]$9129 $1\sr_op__input_cr$next[0:0]$9146
+ assign $0\sr_op__insn$next[31:0]$9130 $1\sr_op__insn$next[31:0]$9147
+ assign $0\sr_op__insn_type$next[6:0]$9131 $1\sr_op__insn_type$next[6:0]$9148
+ assign $0\sr_op__invert_in$next[0:0]$9132 $1\sr_op__invert_in$next[0:0]$9149
+ assign $0\sr_op__is_32bit$next[0:0]$9133 $1\sr_op__is_32bit$next[0:0]$9150
+ assign $0\sr_op__is_signed$next[0:0]$9134 $1\sr_op__is_signed$next[0:0]$9151
assign { } { }
assign { } { }
- assign $0\sr_op__output_carry$next[0:0]$9189 $1\sr_op__output_carry$next[0:0]$9206
- assign $0\sr_op__output_cr$next[0:0]$9190 $1\sr_op__output_cr$next[0:0]$9207
+ assign $0\sr_op__output_carry$next[0:0]$9137 $1\sr_op__output_carry$next[0:0]$9154
+ assign $0\sr_op__output_cr$next[0:0]$9138 $1\sr_op__output_cr$next[0:0]$9155
assign { } { }
assign { } { }
- assign $0\sr_op__write_cr0$next[0:0]$9193 $1\sr_op__write_cr0$next[0:0]$9210
- assign $0\sr_op__imm_data__data$next[63:0]$9178 $2\sr_op__imm_data__data$next[63:0]$9211
- assign $0\sr_op__imm_data__ok$next[0:0]$9179 $2\sr_op__imm_data__ok$next[0:0]$9212
- assign $0\sr_op__oe__oe$next[0:0]$9187 $2\sr_op__oe__oe$next[0:0]$9213
- assign $0\sr_op__oe__ok$next[0:0]$9188 $2\sr_op__oe__ok$next[0:0]$9214
- assign $0\sr_op__rc__ok$next[0:0]$9191 $2\sr_op__rc__ok$next[0:0]$9215
- assign $0\sr_op__rc__rc$next[0:0]$9192 $2\sr_op__rc__rc$next[0:0]$9216
- attribute \src "libresoc.v:168390.5-168390.29"
+ assign $0\sr_op__write_cr0$next[0:0]$9141 $1\sr_op__write_cr0$next[0:0]$9158
+ assign $0\sr_op__imm_data__data$next[63:0]$9126 $2\sr_op__imm_data__data$next[63:0]$9159
+ assign $0\sr_op__imm_data__ok$next[0:0]$9127 $2\sr_op__imm_data__ok$next[0:0]$9160
+ assign $0\sr_op__oe__oe$next[0:0]$9135 $2\sr_op__oe__oe$next[0:0]$9161
+ assign $0\sr_op__oe__ok$next[0:0]$9136 $2\sr_op__oe__ok$next[0:0]$9162
+ assign $0\sr_op__rc__ok$next[0:0]$9139 $2\sr_op__rc__ok$next[0:0]$9163
+ assign $0\sr_op__rc__rc$next[0:0]$9140 $2\sr_op__rc__rc$next[0:0]$9164
+ attribute \src "libresoc.v:168054.5-168054.29"
switch \initial
- attribute \src "libresoc.v:168390.9-168390.17"
+ attribute \src "libresoc.v:168054.9-168054.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$next[31:0]$9199 $1\sr_op__is_signed$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9202 $1\sr_op__output_cr$next[0:0]$9207 $1\sr_op__input_cr$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9206 $1\sr_op__input_carry$next[1:0]$9197 $1\sr_op__invert_in$next[0:0]$9201 $1\sr_op__write_cr0$next[0:0]$9210 $1\sr_op__oe__ok$next[0:0]$9205 $1\sr_op__oe__oe$next[0:0]$9204 $1\sr_op__rc__ok$next[0:0]$9208 $1\sr_op__rc__rc$next[0:0]$9209 $1\sr_op__imm_data__ok$next[0:0]$9196 $1\sr_op__imm_data__data$next[63:0]$9195 $1\sr_op__fn_unit$next[13:0]$9194 $1\sr_op__insn_type$next[6:0]$9200 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
+ assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$next[31:0]$9199 $1\sr_op__is_signed$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9202 $1\sr_op__output_cr$next[0:0]$9207 $1\sr_op__input_cr$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9206 $1\sr_op__input_carry$next[1:0]$9197 $1\sr_op__invert_in$next[0:0]$9201 $1\sr_op__write_cr0$next[0:0]$9210 $1\sr_op__oe__ok$next[0:0]$9205 $1\sr_op__oe__oe$next[0:0]$9204 $1\sr_op__rc__ok$next[0:0]$9208 $1\sr_op__rc__rc$next[0:0]$9209 $1\sr_op__imm_data__ok$next[0:0]$9196 $1\sr_op__imm_data__data$next[63:0]$9195 $1\sr_op__fn_unit$next[13:0]$9194 $1\sr_op__insn_type$next[6:0]$9200 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
+ assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
case
- assign $1\sr_op__fn_unit$next[13:0]$9194 \sr_op__fn_unit
- assign $1\sr_op__imm_data__data$next[63:0]$9195 \sr_op__imm_data__data
- assign $1\sr_op__imm_data__ok$next[0:0]$9196 \sr_op__imm_data__ok
- assign $1\sr_op__input_carry$next[1:0]$9197 \sr_op__input_carry
- assign $1\sr_op__input_cr$next[0:0]$9198 \sr_op__input_cr
- assign $1\sr_op__insn$next[31:0]$9199 \sr_op__insn
- assign $1\sr_op__insn_type$next[6:0]$9200 \sr_op__insn_type
- assign $1\sr_op__invert_in$next[0:0]$9201 \sr_op__invert_in
- assign $1\sr_op__is_32bit$next[0:0]$9202 \sr_op__is_32bit
- assign $1\sr_op__is_signed$next[0:0]$9203 \sr_op__is_signed
- assign $1\sr_op__oe__oe$next[0:0]$9204 \sr_op__oe__oe
- assign $1\sr_op__oe__ok$next[0:0]$9205 \sr_op__oe__ok
- assign $1\sr_op__output_carry$next[0:0]$9206 \sr_op__output_carry
- assign $1\sr_op__output_cr$next[0:0]$9207 \sr_op__output_cr
- assign $1\sr_op__rc__ok$next[0:0]$9208 \sr_op__rc__ok
- assign $1\sr_op__rc__rc$next[0:0]$9209 \sr_op__rc__rc
- assign $1\sr_op__write_cr0$next[0:0]$9210 \sr_op__write_cr0
+ assign $1\sr_op__fn_unit$next[13:0]$9142 \sr_op__fn_unit
+ assign $1\sr_op__imm_data__data$next[63:0]$9143 \sr_op__imm_data__data
+ assign $1\sr_op__imm_data__ok$next[0:0]$9144 \sr_op__imm_data__ok
+ assign $1\sr_op__input_carry$next[1:0]$9145 \sr_op__input_carry
+ assign $1\sr_op__input_cr$next[0:0]$9146 \sr_op__input_cr
+ assign $1\sr_op__insn$next[31:0]$9147 \sr_op__insn
+ assign $1\sr_op__insn_type$next[6:0]$9148 \sr_op__insn_type
+ assign $1\sr_op__invert_in$next[0:0]$9149 \sr_op__invert_in
+ assign $1\sr_op__is_32bit$next[0:0]$9150 \sr_op__is_32bit
+ assign $1\sr_op__is_signed$next[0:0]$9151 \sr_op__is_signed
+ assign $1\sr_op__oe__oe$next[0:0]$9152 \sr_op__oe__oe
+ assign $1\sr_op__oe__ok$next[0:0]$9153 \sr_op__oe__ok
+ assign $1\sr_op__output_carry$next[0:0]$9154 \sr_op__output_carry
+ assign $1\sr_op__output_cr$next[0:0]$9155 \sr_op__output_cr
+ assign $1\sr_op__rc__ok$next[0:0]$9156 \sr_op__rc__ok
+ assign $1\sr_op__rc__rc$next[0:0]$9157 \sr_op__rc__rc
+ assign $1\sr_op__write_cr0$next[0:0]$9158 \sr_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\sr_op__imm_data__data$next[63:0]$9211 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\sr_op__imm_data__ok$next[0:0]$9212 1'0
- assign $2\sr_op__rc__rc$next[0:0]$9216 1'0
- assign $2\sr_op__rc__ok$next[0:0]$9215 1'0
- assign $2\sr_op__oe__oe$next[0:0]$9213 1'0
- assign $2\sr_op__oe__ok$next[0:0]$9214 1'0
+ assign $2\sr_op__imm_data__data$next[63:0]$9159 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sr_op__imm_data__ok$next[0:0]$9160 1'0
+ assign $2\sr_op__rc__rc$next[0:0]$9164 1'0
+ assign $2\sr_op__rc__ok$next[0:0]$9163 1'0
+ assign $2\sr_op__oe__oe$next[0:0]$9161 1'0
+ assign $2\sr_op__oe__ok$next[0:0]$9162 1'0
case
- assign $2\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__imm_data__data$next[63:0]$9195
- assign $2\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__ok$next[0:0]$9196
- assign $2\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__oe__oe$next[0:0]$9204
- assign $2\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__ok$next[0:0]$9205
- assign $2\sr_op__rc__ok$next[0:0]$9215 $1\sr_op__rc__ok$next[0:0]$9208
- assign $2\sr_op__rc__rc$next[0:0]$9216 $1\sr_op__rc__rc$next[0:0]$9209
+ assign $2\sr_op__imm_data__data$next[63:0]$9159 $1\sr_op__imm_data__data$next[63:0]$9143
+ assign $2\sr_op__imm_data__ok$next[0:0]$9160 $1\sr_op__imm_data__ok$next[0:0]$9144
+ assign $2\sr_op__oe__oe$next[0:0]$9161 $1\sr_op__oe__oe$next[0:0]$9152
+ assign $2\sr_op__oe__ok$next[0:0]$9162 $1\sr_op__oe__ok$next[0:0]$9153
+ assign $2\sr_op__rc__ok$next[0:0]$9163 $1\sr_op__rc__ok$next[0:0]$9156
+ assign $2\sr_op__rc__rc$next[0:0]$9164 $1\sr_op__rc__rc$next[0:0]$9157
end
sync always
- update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9177
- update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9178
- update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9179
- update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9180
- update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9181
- update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9182
- update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9183
- update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9184
- update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9185
- update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9186
- update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9187
- update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9188
- update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9189
- update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9190
- update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9191
- update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9192
- update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9193
+ update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9125
+ update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9126
+ update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9127
+ update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9128
+ update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9129
+ update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9130
+ update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9131
+ update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9132
+ update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9133
+ update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9134
+ update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9135
+ update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9136
+ update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9137
+ update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9138
+ update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9139
+ update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9140
+ update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9141
end
- attribute \src "libresoc.v:168430.3-168448.6"
- process $proc$libresoc.v:168430$9217
+ attribute \src "libresoc.v:168094.3-168112.6"
+ process $proc$libresoc.v:168094$9165
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9218 $1\o$next[63:0]$9220
+ assign $0\o$next[63:0]$9166 $1\o$next[63:0]$9168
assign { } { }
- assign $0\o_ok$next[0:0]$9219 $2\o_ok$next[0:0]$9222
- attribute \src "libresoc.v:168431.5-168431.29"
+ assign $0\o_ok$next[0:0]$9167 $2\o_ok$next[0:0]$9170
+ attribute \src "libresoc.v:168095.5-168095.29"
switch \initial
- attribute \src "libresoc.v:168431.9-168431.17"
+ attribute \src "libresoc.v:168095.9-168095.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9221 $1\o$next[63:0]$9220 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9221 $1\o$next[63:0]$9220 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 }
case
- assign $1\o$next[63:0]$9220 \o
- assign $1\o_ok$next[0:0]$9221 \o_ok
+ assign $1\o$next[63:0]$9168 \o
+ assign $1\o_ok$next[0:0]$9169 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9222 1'0
+ assign $2\o_ok$next[0:0]$9170 1'0
case
- assign $2\o_ok$next[0:0]$9222 $1\o_ok$next[0:0]$9221
+ assign $2\o_ok$next[0:0]$9170 $1\o_ok$next[0:0]$9169
end
sync always
- update \o$next $0\o$next[63:0]$9218
- update \o_ok$next $0\o_ok$next[0:0]$9219
+ update \o$next $0\o$next[63:0]$9166
+ update \o_ok$next $0\o_ok$next[0:0]$9167
end
- attribute \src "libresoc.v:168449.3-168467.6"
- process $proc$libresoc.v:168449$9223
+ attribute \src "libresoc.v:168113.3-168131.6"
+ process $proc$libresoc.v:168113$9171
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9224 $1\cr_a$next[3:0]$9226
+ assign $0\cr_a$next[3:0]$9172 $1\cr_a$next[3:0]$9174
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9225 $2\cr_a_ok$next[0:0]$9228
- attribute \src "libresoc.v:168450.5-168450.29"
+ assign $0\cr_a_ok$next[0:0]$9173 $2\cr_a_ok$next[0:0]$9176
+ attribute \src "libresoc.v:168114.5-168114.29"
switch \initial
- attribute \src "libresoc.v:168450.9-168450.17"
+ attribute \src "libresoc.v:168114.9-168114.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9227 $1\cr_a$next[3:0]$9226 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9227 $1\cr_a$next[3:0]$9226 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 }
case
- assign $1\cr_a$next[3:0]$9226 \cr_a
- assign $1\cr_a_ok$next[0:0]$9227 \cr_a_ok
+ assign $1\cr_a$next[3:0]$9174 \cr_a
+ assign $1\cr_a_ok$next[0:0]$9175 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9228 1'0
+ assign $2\cr_a_ok$next[0:0]$9176 1'0
case
- assign $2\cr_a_ok$next[0:0]$9228 $1\cr_a_ok$next[0:0]$9227
+ assign $2\cr_a_ok$next[0:0]$9176 $1\cr_a_ok$next[0:0]$9175
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9224
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9225
+ update \cr_a$next $0\cr_a$next[3:0]$9172
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9173
end
- attribute \src "libresoc.v:168468.3-168486.6"
- process $proc$libresoc.v:168468$9229
+ attribute \src "libresoc.v:168132.3-168150.6"
+ process $proc$libresoc.v:168132$9177
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$9230 $1\xer_so$next[0:0]$9232
+ assign $0\xer_so$next[0:0]$9178 $1\xer_so$next[0:0]$9180
assign { } { }
- assign $0\xer_so_ok$next[0:0]$9231 $2\xer_so_ok$next[0:0]$9234
- attribute \src "libresoc.v:168469.5-168469.29"
+ assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9182
+ attribute \src "libresoc.v:168133.5-168133.29"
switch \initial
- attribute \src "libresoc.v:168469.9-168469.17"
+ attribute \src "libresoc.v:168133.9-168133.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9233 $1\xer_so$next[0:0]$9232 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9233 $1\xer_so$next[0:0]$9232 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 }
case
- assign $1\xer_so$next[0:0]$9232 \xer_so
- assign $1\xer_so_ok$next[0:0]$9233 \xer_so_ok
+ assign $1\xer_so$next[0:0]$9180 \xer_so
+ assign $1\xer_so_ok$next[0:0]$9181 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9234 1'0
+ assign $2\xer_so_ok$next[0:0]$9182 1'0
case
- assign $2\xer_so_ok$next[0:0]$9234 $1\xer_so_ok$next[0:0]$9233
+ assign $2\xer_so_ok$next[0:0]$9182 $1\xer_so_ok$next[0:0]$9181
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$9230
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9231
+ update \xer_so$next $0\xer_so$next[0:0]$9178
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179
end
- connect \$65 $and$libresoc.v:168182$9135_Y
+ connect \$65 $and$libresoc.v:167846$9083_Y
connect \cr_a$89 4'0000
connect \cr_a_ok$90 1'0
connect \xer_so_ok$93 1'0
connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:168520.1-169368.10"
+attribute \src "libresoc.v:168184.1-169032.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1"
attribute \generator "nMigen"
module \pipe1$32
- attribute \src "libresoc.v:169325.3-169337.6"
- wire width 64 $0\fast1$next[63:0]$9312
- attribute \src "libresoc.v:169181.3-169182.27"
+ attribute \src "libresoc.v:168989.3-169001.6"
+ wire width 64 $0\fast1$next[63:0]$9260
+ attribute \src "libresoc.v:168845.3-168846.27"
wire width 64 $0\fast1[63:0]
- attribute \src "libresoc.v:169338.3-169350.6"
- wire width 64 $0\fast2$next[63:0]$9315
- attribute \src "libresoc.v:169179.3-169180.27"
+ attribute \src "libresoc.v:169002.3-169014.6"
+ wire width 64 $0\fast2$next[63:0]$9263
+ attribute \src "libresoc.v:168843.3-168844.27"
wire width 64 $0\fast2[63:0]
- attribute \src "libresoc.v:168521.7-168521.20"
+ attribute \src "libresoc.v:168185.7-168185.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:169265.3-169277.6"
- wire width 2 $0\muxid$next[1:0]$9284
- attribute \src "libresoc.v:169205.3-169206.27"
+ attribute \src "libresoc.v:168929.3-168941.6"
+ wire width 2 $0\muxid$next[1:0]$9232
+ attribute \src "libresoc.v:168869.3-168870.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:169247.3-169264.6"
- wire $0\r_busy$next[0:0]$9280
- attribute \src "libresoc.v:169207.3-169208.29"
+ attribute \src "libresoc.v:168911.3-168928.6"
+ wire $0\r_busy$next[0:0]$9228
+ attribute \src "libresoc.v:168871.3-168872.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:169299.3-169311.6"
- wire width 64 $0\ra$next[63:0]$9306
- attribute \src "libresoc.v:169185.3-169186.21"
+ attribute \src "libresoc.v:168963.3-168975.6"
+ wire width 64 $0\ra$next[63:0]$9254
+ attribute \src "libresoc.v:168849.3-168850.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:169312.3-169324.6"
- wire width 64 $0\rb$next[63:0]$9309
- attribute \src "libresoc.v:169183.3-169184.21"
+ attribute \src "libresoc.v:168976.3-168988.6"
+ wire width 64 $0\rb$next[63:0]$9257
+ attribute \src "libresoc.v:168847.3-168848.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 64 $0\trap_op__cia$next[63:0]$9287
- attribute \src "libresoc.v:169195.3-169196.41"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 64 $0\trap_op__cia$next[63:0]$9235
+ attribute \src "libresoc.v:168859.3-168860.41"
wire width 64 $0\trap_op__cia[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 14 $0\trap_op__fn_unit$next[13:0]$9288
- attribute \src "libresoc.v:169189.3-169190.49"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 14 $0\trap_op__fn_unit$next[13:0]$9236
+ attribute \src "libresoc.v:168853.3-168854.49"
wire width 14 $0\trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 32 $0\trap_op__insn$next[31:0]$9289
- attribute \src "libresoc.v:169191.3-169192.43"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 32 $0\trap_op__insn$next[31:0]$9237
+ attribute \src "libresoc.v:168855.3-168856.43"
wire width 32 $0\trap_op__insn[31:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 7 $0\trap_op__insn_type$next[6:0]$9290
- attribute \src "libresoc.v:169187.3-169188.53"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 7 $0\trap_op__insn_type$next[6:0]$9238
+ attribute \src "libresoc.v:168851.3-168852.53"
wire width 7 $0\trap_op__insn_type[6:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire $0\trap_op__is_32bit$next[0:0]$9291
- attribute \src "libresoc.v:169197.3-169198.51"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire $0\trap_op__is_32bit$next[0:0]$9239
+ attribute \src "libresoc.v:168861.3-168862.51"
wire $0\trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 8 $0\trap_op__ldst_exc$next[7:0]$9292
- attribute \src "libresoc.v:169203.3-169204.51"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 8 $0\trap_op__ldst_exc$next[7:0]$9240
+ attribute \src "libresoc.v:168867.3-168868.51"
wire width 8 $0\trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 64 $0\trap_op__msr$next[63:0]$9293
- attribute \src "libresoc.v:169193.3-169194.41"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 64 $0\trap_op__msr$next[63:0]$9241
+ attribute \src "libresoc.v:168857.3-168858.41"
wire width 64 $0\trap_op__msr[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 13 $0\trap_op__trapaddr$next[12:0]$9294
- attribute \src "libresoc.v:169201.3-169202.51"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 13 $0\trap_op__trapaddr$next[12:0]$9242
+ attribute \src "libresoc.v:168865.3-168866.51"
wire width 13 $0\trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 8 $0\trap_op__traptype$next[7:0]$9295
- attribute \src "libresoc.v:169199.3-169200.51"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 8 $0\trap_op__traptype$next[7:0]$9243
+ attribute \src "libresoc.v:168863.3-168864.51"
wire width 8 $0\trap_op__traptype[7:0]
- attribute \src "libresoc.v:169325.3-169337.6"
- wire width 64 $1\fast1$next[63:0]$9313
- attribute \src "libresoc.v:168766.14-168766.42"
+ attribute \src "libresoc.v:168989.3-169001.6"
+ wire width 64 $1\fast1$next[63:0]$9261
+ attribute \src "libresoc.v:168430.14-168430.42"
wire width 64 $1\fast1[63:0]
- attribute \src "libresoc.v:169338.3-169350.6"
- wire width 64 $1\fast2$next[63:0]$9316
- attribute \src "libresoc.v:168775.14-168775.42"
+ attribute \src "libresoc.v:169002.3-169014.6"
+ wire width 64 $1\fast2$next[63:0]$9264
+ attribute \src "libresoc.v:168439.14-168439.42"
wire width 64 $1\fast2[63:0]
- attribute \src "libresoc.v:169265.3-169277.6"
- wire width 2 $1\muxid$next[1:0]$9285
- attribute \src "libresoc.v:168784.13-168784.25"
+ attribute \src "libresoc.v:168929.3-168941.6"
+ wire width 2 $1\muxid$next[1:0]$9233
+ attribute \src "libresoc.v:168448.13-168448.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:169247.3-169264.6"
- wire $1\r_busy$next[0:0]$9281
- attribute \src "libresoc.v:168806.7-168806.20"
+ attribute \src "libresoc.v:168911.3-168928.6"
+ wire $1\r_busy$next[0:0]$9229
+ attribute \src "libresoc.v:168470.7-168470.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:169299.3-169311.6"
- wire width 64 $1\ra$next[63:0]$9307
- attribute \src "libresoc.v:168811.14-168811.39"
+ attribute \src "libresoc.v:168963.3-168975.6"
+ wire width 64 $1\ra$next[63:0]$9255
+ attribute \src "libresoc.v:168475.14-168475.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:169312.3-169324.6"
- wire width 64 $1\rb$next[63:0]$9310
- attribute \src "libresoc.v:168820.14-168820.39"
+ attribute \src "libresoc.v:168976.3-168988.6"
+ wire width 64 $1\rb$next[63:0]$9258
+ attribute \src "libresoc.v:168484.14-168484.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 64 $1\trap_op__cia$next[63:0]$9296
- attribute \src "libresoc.v:168829.14-168829.49"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 64 $1\trap_op__cia$next[63:0]$9244
+ attribute \src "libresoc.v:168493.14-168493.49"
wire width 64 $1\trap_op__cia[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 14 $1\trap_op__fn_unit$next[13:0]$9297
- attribute \src "libresoc.v:168853.14-168853.41"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 14 $1\trap_op__fn_unit$next[13:0]$9245
+ attribute \src "libresoc.v:168517.14-168517.41"
wire width 14 $1\trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 32 $1\trap_op__insn$next[31:0]$9298
- attribute \src "libresoc.v:168892.14-168892.35"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 32 $1\trap_op__insn$next[31:0]$9246
+ attribute \src "libresoc.v:168556.14-168556.35"
wire width 32 $1\trap_op__insn[31:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 7 $1\trap_op__insn_type$next[6:0]$9299
- attribute \src "libresoc.v:168976.13-168976.39"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 7 $1\trap_op__insn_type$next[6:0]$9247
+ attribute \src "libresoc.v:168640.13-168640.39"
wire width 7 $1\trap_op__insn_type[6:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire $1\trap_op__is_32bit$next[0:0]$9300
- attribute \src "libresoc.v:169135.7-169135.31"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire $1\trap_op__is_32bit$next[0:0]$9248
+ attribute \src "libresoc.v:168799.7-168799.31"
wire $1\trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 8 $1\trap_op__ldst_exc$next[7:0]$9301
- attribute \src "libresoc.v:169144.13-169144.38"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 8 $1\trap_op__ldst_exc$next[7:0]$9249
+ attribute \src "libresoc.v:168808.13-168808.38"
wire width 8 $1\trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 64 $1\trap_op__msr$next[63:0]$9302
- attribute \src "libresoc.v:169153.14-169153.49"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 64 $1\trap_op__msr$next[63:0]$9250
+ attribute \src "libresoc.v:168817.14-168817.49"
wire width 64 $1\trap_op__msr[63:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 13 $1\trap_op__trapaddr$next[12:0]$9303
- attribute \src "libresoc.v:169162.14-169162.42"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 13 $1\trap_op__trapaddr$next[12:0]$9251
+ attribute \src "libresoc.v:168826.14-168826.42"
wire width 13 $1\trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:169278.3-169298.6"
- wire width 8 $1\trap_op__traptype$next[7:0]$9304
- attribute \src "libresoc.v:169171.13-169171.38"
+ attribute \src "libresoc.v:168942.3-168962.6"
+ wire width 8 $1\trap_op__traptype$next[7:0]$9252
+ attribute \src "libresoc.v:168835.13-168835.38"
wire width 8 $1\trap_op__traptype[7:0]
- attribute \src "libresoc.v:169247.3-169264.6"
- wire $2\r_busy$next[0:0]$9282
- attribute \src "libresoc.v:169178.18-169178.118"
- wire $and$libresoc.v:169178$9263_Y
+ attribute \src "libresoc.v:168911.3-168928.6"
+ wire $2\r_busy$next[0:0]$9230
+ attribute \src "libresoc.v:168842.18-168842.118"
+ wire $and$libresoc.v:168842$9211_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \dummy_fast1
wire width 64 \fast2$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \fast2$next
- attribute \src "libresoc.v:168521.7-168521.15"
+ attribute \src "libresoc.v:168185.7-168185.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 8 \trap_op__traptype$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:169178$9263
+ cell $and $and$libresoc.v:168842$9211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$29
connect \B \p_ready_o
- connect \Y $and$libresoc.v:169178$9263_Y
+ connect \Y $and$libresoc.v:168842$9211_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169209.9-169238.4"
+ attribute \src "libresoc.v:168873.9-168902.4"
cell \dummy \dummy
connect \fast1 \dummy_fast1
connect \fast1$13 \dummy_fast1$27
connect \trap_op__traptype$8 \dummy_trap_op__traptype$22
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169239.10-169242.4"
+ attribute \src "libresoc.v:168903.10-168906.4"
cell \n$34 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169243.10-169246.4"
+ attribute \src "libresoc.v:168907.10-168910.4"
cell \p$33 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:168521.7-168521.20"
- process $proc$libresoc.v:168521$9317
+ attribute \src "libresoc.v:168185.7-168185.20"
+ process $proc$libresoc.v:168185$9265
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:168766.14-168766.42"
- process $proc$libresoc.v:168766$9318
+ attribute \src "libresoc.v:168430.14-168430.42"
+ process $proc$libresoc.v:168430$9266
assign { } { }
assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \fast1 $1\fast1[63:0]
end
- attribute \src "libresoc.v:168775.14-168775.42"
- process $proc$libresoc.v:168775$9319
+ attribute \src "libresoc.v:168439.14-168439.42"
+ process $proc$libresoc.v:168439$9267
assign { } { }
assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \fast2 $1\fast2[63:0]
end
- attribute \src "libresoc.v:168784.13-168784.25"
- process $proc$libresoc.v:168784$9320
+ attribute \src "libresoc.v:168448.13-168448.25"
+ process $proc$libresoc.v:168448$9268
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:168806.7-168806.20"
- process $proc$libresoc.v:168806$9321
+ attribute \src "libresoc.v:168470.7-168470.20"
+ process $proc$libresoc.v:168470$9269
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:168811.14-168811.39"
- process $proc$libresoc.v:168811$9322
+ attribute \src "libresoc.v:168475.14-168475.39"
+ process $proc$libresoc.v:168475$9270
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:168820.14-168820.39"
- process $proc$libresoc.v:168820$9323
+ attribute \src "libresoc.v:168484.14-168484.39"
+ process $proc$libresoc.v:168484$9271
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:168829.14-168829.49"
- process $proc$libresoc.v:168829$9324
+ attribute \src "libresoc.v:168493.14-168493.49"
+ process $proc$libresoc.v:168493$9272
assign { } { }
assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \trap_op__cia $1\trap_op__cia[63:0]
end
- attribute \src "libresoc.v:168853.14-168853.41"
- process $proc$libresoc.v:168853$9325
+ attribute \src "libresoc.v:168517.14-168517.41"
+ process $proc$libresoc.v:168517$9273
assign { } { }
assign $1\trap_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \trap_op__fn_unit $1\trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:168892.14-168892.35"
- process $proc$libresoc.v:168892$9326
+ attribute \src "libresoc.v:168556.14-168556.35"
+ process $proc$libresoc.v:168556$9274
assign { } { }
assign $1\trap_op__insn[31:0] 0
sync always
sync init
update \trap_op__insn $1\trap_op__insn[31:0]
end
- attribute \src "libresoc.v:168976.13-168976.39"
- process $proc$libresoc.v:168976$9327
+ attribute \src "libresoc.v:168640.13-168640.39"
+ process $proc$libresoc.v:168640$9275
assign { } { }
assign $1\trap_op__insn_type[6:0] 7'0000000
sync always
sync init
update \trap_op__insn_type $1\trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:169135.7-169135.31"
- process $proc$libresoc.v:169135$9328
+ attribute \src "libresoc.v:168799.7-168799.31"
+ process $proc$libresoc.v:168799$9276
assign { } { }
assign $1\trap_op__is_32bit[0:0] 1'0
sync always
sync init
update \trap_op__is_32bit $1\trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:169144.13-169144.38"
- process $proc$libresoc.v:169144$9329
+ attribute \src "libresoc.v:168808.13-168808.38"
+ process $proc$libresoc.v:168808$9277
assign { } { }
assign $1\trap_op__ldst_exc[7:0] 8'00000000
sync always
sync init
update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:169153.14-169153.49"
- process $proc$libresoc.v:169153$9330
+ attribute \src "libresoc.v:168817.14-168817.49"
+ process $proc$libresoc.v:168817$9278
assign { } { }
assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \trap_op__msr $1\trap_op__msr[63:0]
end
- attribute \src "libresoc.v:169162.14-169162.42"
- process $proc$libresoc.v:169162$9331
+ attribute \src "libresoc.v:168826.14-168826.42"
+ process $proc$libresoc.v:168826$9279
assign { } { }
assign $1\trap_op__trapaddr[12:0] 13'0000000000000
sync always
sync init
update \trap_op__trapaddr $1\trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:169171.13-169171.38"
- process $proc$libresoc.v:169171$9332
+ attribute \src "libresoc.v:168835.13-168835.38"
+ process $proc$libresoc.v:168835$9280
assign { } { }
assign $1\trap_op__traptype[7:0] 8'00000000
sync always
sync init
update \trap_op__traptype $1\trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:169179.3-169180.27"
- process $proc$libresoc.v:169179$9264
+ attribute \src "libresoc.v:168843.3-168844.27"
+ process $proc$libresoc.v:168843$9212
assign { } { }
assign $0\fast2[63:0] \fast2$next
sync posedge \coresync_clk
update \fast2 $0\fast2[63:0]
end
- attribute \src "libresoc.v:169181.3-169182.27"
- process $proc$libresoc.v:169181$9265
+ attribute \src "libresoc.v:168845.3-168846.27"
+ process $proc$libresoc.v:168845$9213
assign { } { }
assign $0\fast1[63:0] \fast1$next
sync posedge \coresync_clk
update \fast1 $0\fast1[63:0]
end
- attribute \src "libresoc.v:169183.3-169184.21"
- process $proc$libresoc.v:169183$9266
+ attribute \src "libresoc.v:168847.3-168848.21"
+ process $proc$libresoc.v:168847$9214
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:169185.3-169186.21"
- process $proc$libresoc.v:169185$9267
+ attribute \src "libresoc.v:168849.3-168850.21"
+ process $proc$libresoc.v:168849$9215
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:169187.3-169188.53"
- process $proc$libresoc.v:169187$9268
+ attribute \src "libresoc.v:168851.3-168852.53"
+ process $proc$libresoc.v:168851$9216
assign { } { }
assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next
sync posedge \coresync_clk
update \trap_op__insn_type $0\trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:169189.3-169190.49"
- process $proc$libresoc.v:169189$9269
+ attribute \src "libresoc.v:168853.3-168854.49"
+ process $proc$libresoc.v:168853$9217
assign { } { }
assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next
sync posedge \coresync_clk
update \trap_op__fn_unit $0\trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:169191.3-169192.43"
- process $proc$libresoc.v:169191$9270
+ attribute \src "libresoc.v:168855.3-168856.43"
+ process $proc$libresoc.v:168855$9218
assign { } { }
assign $0\trap_op__insn[31:0] \trap_op__insn$next
sync posedge \coresync_clk
update \trap_op__insn $0\trap_op__insn[31:0]
end
- attribute \src "libresoc.v:169193.3-169194.41"
- process $proc$libresoc.v:169193$9271
+ attribute \src "libresoc.v:168857.3-168858.41"
+ process $proc$libresoc.v:168857$9219
assign { } { }
assign $0\trap_op__msr[63:0] \trap_op__msr$next
sync posedge \coresync_clk
update \trap_op__msr $0\trap_op__msr[63:0]
end
- attribute \src "libresoc.v:169195.3-169196.41"
- process $proc$libresoc.v:169195$9272
+ attribute \src "libresoc.v:168859.3-168860.41"
+ process $proc$libresoc.v:168859$9220
assign { } { }
assign $0\trap_op__cia[63:0] \trap_op__cia$next
sync posedge \coresync_clk
update \trap_op__cia $0\trap_op__cia[63:0]
end
- attribute \src "libresoc.v:169197.3-169198.51"
- process $proc$libresoc.v:169197$9273
+ attribute \src "libresoc.v:168861.3-168862.51"
+ process $proc$libresoc.v:168861$9221
assign { } { }
assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next
sync posedge \coresync_clk
update \trap_op__is_32bit $0\trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:169199.3-169200.51"
- process $proc$libresoc.v:169199$9274
+ attribute \src "libresoc.v:168863.3-168864.51"
+ process $proc$libresoc.v:168863$9222
assign { } { }
assign $0\trap_op__traptype[7:0] \trap_op__traptype$next
sync posedge \coresync_clk
update \trap_op__traptype $0\trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:169201.3-169202.51"
- process $proc$libresoc.v:169201$9275
+ attribute \src "libresoc.v:168865.3-168866.51"
+ process $proc$libresoc.v:168865$9223
assign { } { }
assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next
sync posedge \coresync_clk
update \trap_op__trapaddr $0\trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:169203.3-169204.51"
- process $proc$libresoc.v:169203$9276
+ attribute \src "libresoc.v:168867.3-168868.51"
+ process $proc$libresoc.v:168867$9224
assign { } { }
assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next
sync posedge \coresync_clk
update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:169205.3-169206.27"
- process $proc$libresoc.v:169205$9277
+ attribute \src "libresoc.v:168869.3-168870.27"
+ process $proc$libresoc.v:168869$9225
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:169207.3-169208.29"
- process $proc$libresoc.v:169207$9278
+ attribute \src "libresoc.v:168871.3-168872.29"
+ process $proc$libresoc.v:168871$9226
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:169247.3-169264.6"
- process $proc$libresoc.v:169247$9279
+ attribute \src "libresoc.v:168911.3-168928.6"
+ process $proc$libresoc.v:168911$9227
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9280 $2\r_busy$next[0:0]$9282
- attribute \src "libresoc.v:169248.5-169248.29"
+ assign $0\r_busy$next[0:0]$9228 $2\r_busy$next[0:0]$9230
+ attribute \src "libresoc.v:168912.5-168912.29"
switch \initial
- attribute \src "libresoc.v:169248.9-169248.17"
+ attribute \src "libresoc.v:168912.9-168912.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9281 1'1
+ assign $1\r_busy$next[0:0]$9229 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9281 1'0
+ assign $1\r_busy$next[0:0]$9229 1'0
case
- assign $1\r_busy$next[0:0]$9281 \r_busy
+ assign $1\r_busy$next[0:0]$9229 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9282 1'0
+ assign $2\r_busy$next[0:0]$9230 1'0
case
- assign $2\r_busy$next[0:0]$9282 $1\r_busy$next[0:0]$9281
+ assign $2\r_busy$next[0:0]$9230 $1\r_busy$next[0:0]$9229
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9280
+ update \r_busy$next $0\r_busy$next[0:0]$9228
end
- attribute \src "libresoc.v:169265.3-169277.6"
- process $proc$libresoc.v:169265$9283
+ attribute \src "libresoc.v:168929.3-168941.6"
+ process $proc$libresoc.v:168929$9231
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9284 $1\muxid$next[1:0]$9285
- attribute \src "libresoc.v:169266.5-169266.29"
+ assign $0\muxid$next[1:0]$9232 $1\muxid$next[1:0]$9233
+ attribute \src "libresoc.v:168930.5-168930.29"
switch \initial
- attribute \src "libresoc.v:169266.9-169266.17"
+ attribute \src "libresoc.v:168930.9-168930.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9285 \muxid$32
+ assign $1\muxid$next[1:0]$9233 \muxid$32
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9285 \muxid$32
+ assign $1\muxid$next[1:0]$9233 \muxid$32
case
- assign $1\muxid$next[1:0]$9285 \muxid
+ assign $1\muxid$next[1:0]$9233 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9284
+ update \muxid$next $0\muxid$next[1:0]$9232
end
- attribute \src "libresoc.v:169278.3-169298.6"
- process $proc$libresoc.v:169278$9286
+ attribute \src "libresoc.v:168942.3-168962.6"
+ process $proc$libresoc.v:168942$9234
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trap_op__cia$next[63:0]$9287 $1\trap_op__cia$next[63:0]$9296
- assign $0\trap_op__fn_unit$next[13:0]$9288 $1\trap_op__fn_unit$next[13:0]$9297
- assign $0\trap_op__insn$next[31:0]$9289 $1\trap_op__insn$next[31:0]$9298
- assign $0\trap_op__insn_type$next[6:0]$9290 $1\trap_op__insn_type$next[6:0]$9299
- assign $0\trap_op__is_32bit$next[0:0]$9291 $1\trap_op__is_32bit$next[0:0]$9300
- assign $0\trap_op__ldst_exc$next[7:0]$9292 $1\trap_op__ldst_exc$next[7:0]$9301
- assign $0\trap_op__msr$next[63:0]$9293 $1\trap_op__msr$next[63:0]$9302
- assign $0\trap_op__trapaddr$next[12:0]$9294 $1\trap_op__trapaddr$next[12:0]$9303
- assign $0\trap_op__traptype$next[7:0]$9295 $1\trap_op__traptype$next[7:0]$9304
- attribute \src "libresoc.v:169279.5-169279.29"
+ assign $0\trap_op__cia$next[63:0]$9235 $1\trap_op__cia$next[63:0]$9244
+ assign $0\trap_op__fn_unit$next[13:0]$9236 $1\trap_op__fn_unit$next[13:0]$9245
+ assign $0\trap_op__insn$next[31:0]$9237 $1\trap_op__insn$next[31:0]$9246
+ assign $0\trap_op__insn_type$next[6:0]$9238 $1\trap_op__insn_type$next[6:0]$9247
+ assign $0\trap_op__is_32bit$next[0:0]$9239 $1\trap_op__is_32bit$next[0:0]$9248
+ assign $0\trap_op__ldst_exc$next[7:0]$9240 $1\trap_op__ldst_exc$next[7:0]$9249
+ assign $0\trap_op__msr$next[63:0]$9241 $1\trap_op__msr$next[63:0]$9250
+ assign $0\trap_op__trapaddr$next[12:0]$9242 $1\trap_op__trapaddr$next[12:0]$9251
+ assign $0\trap_op__traptype$next[7:0]$9243 $1\trap_op__traptype$next[7:0]$9252
+ attribute \src "libresoc.v:168943.5-168943.29"
switch \initial
- attribute \src "libresoc.v:169279.9-169279.17"
+ attribute \src "libresoc.v:168943.9-168943.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__traptype$next[7:0]$9304 $1\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__cia$next[63:0]$9296 $1\trap_op__msr$next[63:0]$9302 $1\trap_op__insn$next[31:0]$9298 $1\trap_op__fn_unit$next[13:0]$9297 $1\trap_op__insn_type$next[6:0]$9299 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
+ assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__traptype$next[7:0]$9304 $1\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__cia$next[63:0]$9296 $1\trap_op__msr$next[63:0]$9302 $1\trap_op__insn$next[31:0]$9298 $1\trap_op__fn_unit$next[13:0]$9297 $1\trap_op__insn_type$next[6:0]$9299 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
+ assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
case
- assign $1\trap_op__cia$next[63:0]$9296 \trap_op__cia
- assign $1\trap_op__fn_unit$next[13:0]$9297 \trap_op__fn_unit
- assign $1\trap_op__insn$next[31:0]$9298 \trap_op__insn
- assign $1\trap_op__insn_type$next[6:0]$9299 \trap_op__insn_type
- assign $1\trap_op__is_32bit$next[0:0]$9300 \trap_op__is_32bit
- assign $1\trap_op__ldst_exc$next[7:0]$9301 \trap_op__ldst_exc
- assign $1\trap_op__msr$next[63:0]$9302 \trap_op__msr
- assign $1\trap_op__trapaddr$next[12:0]$9303 \trap_op__trapaddr
- assign $1\trap_op__traptype$next[7:0]$9304 \trap_op__traptype
+ assign $1\trap_op__cia$next[63:0]$9244 \trap_op__cia
+ assign $1\trap_op__fn_unit$next[13:0]$9245 \trap_op__fn_unit
+ assign $1\trap_op__insn$next[31:0]$9246 \trap_op__insn
+ assign $1\trap_op__insn_type$next[6:0]$9247 \trap_op__insn_type
+ assign $1\trap_op__is_32bit$next[0:0]$9248 \trap_op__is_32bit
+ assign $1\trap_op__ldst_exc$next[7:0]$9249 \trap_op__ldst_exc
+ assign $1\trap_op__msr$next[63:0]$9250 \trap_op__msr
+ assign $1\trap_op__trapaddr$next[12:0]$9251 \trap_op__trapaddr
+ assign $1\trap_op__traptype$next[7:0]$9252 \trap_op__traptype
end
sync always
- update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9287
- update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9288
- update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9289
- update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9290
- update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9291
- update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9292
- update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9293
- update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9294
- update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9295
+ update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9235
+ update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9236
+ update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9237
+ update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9238
+ update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9239
+ update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9240
+ update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9241
+ update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9242
+ update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9243
end
- attribute \src "libresoc.v:169299.3-169311.6"
- process $proc$libresoc.v:169299$9305
+ attribute \src "libresoc.v:168963.3-168975.6"
+ process $proc$libresoc.v:168963$9253
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$9306 $1\ra$next[63:0]$9307
- attribute \src "libresoc.v:169300.5-169300.29"
+ assign $0\ra$next[63:0]$9254 $1\ra$next[63:0]$9255
+ attribute \src "libresoc.v:168964.5-168964.29"
switch \initial
- attribute \src "libresoc.v:169300.9-169300.17"
+ attribute \src "libresoc.v:168964.9-168964.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$9307 \ra$42
+ assign $1\ra$next[63:0]$9255 \ra$42
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$9307 \ra$42
+ assign $1\ra$next[63:0]$9255 \ra$42
case
- assign $1\ra$next[63:0]$9307 \ra
+ assign $1\ra$next[63:0]$9255 \ra
end
sync always
- update \ra$next $0\ra$next[63:0]$9306
+ update \ra$next $0\ra$next[63:0]$9254
end
- attribute \src "libresoc.v:169312.3-169324.6"
- process $proc$libresoc.v:169312$9308
+ attribute \src "libresoc.v:168976.3-168988.6"
+ process $proc$libresoc.v:168976$9256
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$9309 $1\rb$next[63:0]$9310
- attribute \src "libresoc.v:169313.5-169313.29"
+ assign $0\rb$next[63:0]$9257 $1\rb$next[63:0]$9258
+ attribute \src "libresoc.v:168977.5-168977.29"
switch \initial
- attribute \src "libresoc.v:169313.9-169313.17"
+ attribute \src "libresoc.v:168977.9-168977.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$9310 \rb$43
+ assign $1\rb$next[63:0]$9258 \rb$43
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$9310 \rb$43
+ assign $1\rb$next[63:0]$9258 \rb$43
case
- assign $1\rb$next[63:0]$9310 \rb
+ assign $1\rb$next[63:0]$9258 \rb
end
sync always
- update \rb$next $0\rb$next[63:0]$9309
+ update \rb$next $0\rb$next[63:0]$9257
end
- attribute \src "libresoc.v:169325.3-169337.6"
- process $proc$libresoc.v:169325$9311
+ attribute \src "libresoc.v:168989.3-169001.6"
+ process $proc$libresoc.v:168989$9259
assign { } { }
assign { } { }
- assign $0\fast1$next[63:0]$9312 $1\fast1$next[63:0]$9313
- attribute \src "libresoc.v:169326.5-169326.29"
+ assign $0\fast1$next[63:0]$9260 $1\fast1$next[63:0]$9261
+ attribute \src "libresoc.v:168990.5-168990.29"
switch \initial
- attribute \src "libresoc.v:169326.9-169326.17"
+ attribute \src "libresoc.v:168990.9-168990.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\fast1$next[63:0]$9313 \fast1$44
+ assign $1\fast1$next[63:0]$9261 \fast1$44
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\fast1$next[63:0]$9313 \fast1$44
+ assign $1\fast1$next[63:0]$9261 \fast1$44
case
- assign $1\fast1$next[63:0]$9313 \fast1
+ assign $1\fast1$next[63:0]$9261 \fast1
end
sync always
- update \fast1$next $0\fast1$next[63:0]$9312
+ update \fast1$next $0\fast1$next[63:0]$9260
end
- attribute \src "libresoc.v:169338.3-169350.6"
- process $proc$libresoc.v:169338$9314
+ attribute \src "libresoc.v:169002.3-169014.6"
+ process $proc$libresoc.v:169002$9262
assign { } { }
assign { } { }
- assign $0\fast2$next[63:0]$9315 $1\fast2$next[63:0]$9316
- attribute \src "libresoc.v:169339.5-169339.29"
+ assign $0\fast2$next[63:0]$9263 $1\fast2$next[63:0]$9264
+ attribute \src "libresoc.v:169003.5-169003.29"
switch \initial
- attribute \src "libresoc.v:169339.9-169339.17"
+ attribute \src "libresoc.v:169003.9-169003.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\fast2$next[63:0]$9316 \fast2$45
+ assign $1\fast2$next[63:0]$9264 \fast2$45
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\fast2$next[63:0]$9316 \fast2$45
+ assign $1\fast2$next[63:0]$9264 \fast2$45
case
- assign $1\fast2$next[63:0]$9316 \fast2
+ assign $1\fast2$next[63:0]$9264 \fast2
end
sync always
- update \fast2$next $0\fast2$next[63:0]$9315
+ update \fast2$next $0\fast2$next[63:0]$9263
end
- connect \$30 $and$libresoc.v:169178$9263_Y
+ connect \$30 $and$libresoc.v:168842$9211_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \fast2$45 \dummy_fast2$28
connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 }
connect \dummy_muxid \muxid$1
end
-attribute \src "libresoc.v:169372.1-170557.10"
+attribute \src "libresoc.v:169036.1-170221.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2"
attribute \generator "nMigen"
module \pipe2
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 4 $0\alu_op__data_len$18$next[3:0]$9401
- attribute \src "libresoc.v:170298.3-170299.57"
- wire width 4 $0\alu_op__data_len$18[3:0]$9387
- attribute \src "libresoc.v:169380.13-169380.41"
- wire width 4 $0\alu_op__data_len$18[3:0]$9475
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9402
- attribute \src "libresoc.v:170268.3-170269.53"
- wire width 14 $0\alu_op__fn_unit$3[13:0]$9357
- attribute \src "libresoc.v:169419.14-169419.44"
- wire width 14 $0\alu_op__fn_unit$3[13:0]$9477
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9403
- attribute \src "libresoc.v:170270.3-170271.67"
- wire width 64 $0\alu_op__imm_data__data$4[63:0]$9359
- attribute \src "libresoc.v:169443.14-169443.63"
- wire width 64 $0\alu_op__imm_data__data$4[63:0]$9479
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__imm_data__ok$5$next[0:0]$9404
- attribute \src "libresoc.v:170272.3-170273.63"
- wire $0\alu_op__imm_data__ok$5[0:0]$9361
- attribute \src "libresoc.v:169452.7-169452.38"
- wire $0\alu_op__imm_data__ok$5[0:0]$9481
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 2 $0\alu_op__input_carry$14$next[1:0]$9405
- attribute \src "libresoc.v:170290.3-170291.63"
- wire width 2 $0\alu_op__input_carry$14[1:0]$9379
- attribute \src "libresoc.v:169469.13-169469.44"
- wire width 2 $0\alu_op__input_carry$14[1:0]$9483
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 32 $0\alu_op__insn$19$next[31:0]$9406
- attribute \src "libresoc.v:170300.3-170301.49"
- wire width 32 $0\alu_op__insn$19[31:0]$9389
- attribute \src "libresoc.v:169482.14-169482.39"
- wire width 32 $0\alu_op__insn$19[31:0]$9485
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 7 $0\alu_op__insn_type$2$next[6:0]$9407
- attribute \src "libresoc.v:170266.3-170267.57"
- wire width 7 $0\alu_op__insn_type$2[6:0]$9355
- attribute \src "libresoc.v:169641.13-169641.42"
- wire width 7 $0\alu_op__insn_type$2[6:0]$9487
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__invert_in$10$next[0:0]$9408
- attribute \src "libresoc.v:170282.3-170283.59"
- wire $0\alu_op__invert_in$10[0:0]$9371
- attribute \src "libresoc.v:169725.7-169725.36"
- wire $0\alu_op__invert_in$10[0:0]$9489
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__invert_out$12$next[0:0]$9409
- attribute \src "libresoc.v:170286.3-170287.61"
- wire $0\alu_op__invert_out$12[0:0]$9375
- attribute \src "libresoc.v:169734.7-169734.37"
- wire $0\alu_op__invert_out$12[0:0]$9491
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__is_32bit$16$next[0:0]$9410
- attribute \src "libresoc.v:170294.3-170295.57"
- wire $0\alu_op__is_32bit$16[0:0]$9383
- attribute \src "libresoc.v:169743.7-169743.35"
- wire $0\alu_op__is_32bit$16[0:0]$9493
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__is_signed$17$next[0:0]$9411
- attribute \src "libresoc.v:170296.3-170297.59"
- wire $0\alu_op__is_signed$17[0:0]$9385
- attribute \src "libresoc.v:169752.7-169752.36"
- wire $0\alu_op__is_signed$17[0:0]$9495
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__oe__oe$8$next[0:0]$9412
- attribute \src "libresoc.v:170278.3-170279.51"
- wire $0\alu_op__oe__oe$8[0:0]$9367
- attribute \src "libresoc.v:169763.7-169763.32"
- wire $0\alu_op__oe__oe$8[0:0]$9497
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__oe__ok$9$next[0:0]$9413
- attribute \src "libresoc.v:170280.3-170281.51"
- wire $0\alu_op__oe__ok$9[0:0]$9369
- attribute \src "libresoc.v:169772.7-169772.32"
- wire $0\alu_op__oe__ok$9[0:0]$9499
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__output_carry$15$next[0:0]$9414
- attribute \src "libresoc.v:170292.3-170293.65"
- wire $0\alu_op__output_carry$15[0:0]$9381
- attribute \src "libresoc.v:169779.7-169779.39"
- wire $0\alu_op__output_carry$15[0:0]$9501
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__rc__ok$7$next[0:0]$9415
- attribute \src "libresoc.v:170276.3-170277.51"
- wire $0\alu_op__rc__ok$7[0:0]$9365
- attribute \src "libresoc.v:169790.7-169790.32"
- wire $0\alu_op__rc__ok$7[0:0]$9503
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__rc__rc$6$next[0:0]$9416
- attribute \src "libresoc.v:170274.3-170275.51"
- wire $0\alu_op__rc__rc$6[0:0]$9363
- attribute \src "libresoc.v:169797.7-169797.32"
- wire $0\alu_op__rc__rc$6[0:0]$9505
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__write_cr0$13$next[0:0]$9417
- attribute \src "libresoc.v:170288.3-170289.59"
- wire $0\alu_op__write_cr0$13[0:0]$9377
- attribute \src "libresoc.v:169806.7-169806.36"
- wire $0\alu_op__write_cr0$13[0:0]$9507
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $0\alu_op__zero_a$11$next[0:0]$9418
- attribute \src "libresoc.v:170284.3-170285.53"
- wire $0\alu_op__zero_a$11[0:0]$9373
- attribute \src "libresoc.v:169815.7-169815.33"
- wire $0\alu_op__zero_a$11[0:0]$9509
- attribute \src "libresoc.v:170462.3-170480.6"
- wire width 4 $0\cr_a$22$next[3:0]$9450
- attribute \src "libresoc.v:170258.3-170259.33"
- wire width 4 $0\cr_a$22[3:0]$9347
- attribute \src "libresoc.v:169828.13-169828.29"
- wire width 4 $0\cr_a$22[3:0]$9511
- attribute \src "libresoc.v:170462.3-170480.6"
- wire $0\cr_a_ok$23$next[0:0]$9451
- attribute \src "libresoc.v:170260.3-170261.39"
- wire $0\cr_a_ok$23[0:0]$9349
- attribute \src "libresoc.v:169837.7-169837.26"
- wire $0\cr_a_ok$23[0:0]$9513
- attribute \src "libresoc.v:169373.7-169373.20"
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 4 $0\alu_op__data_len$18$next[3:0]$9349
+ attribute \src "libresoc.v:169962.3-169963.57"
+ wire width 4 $0\alu_op__data_len$18[3:0]$9335
+ attribute \src "libresoc.v:169044.13-169044.41"
+ wire width 4 $0\alu_op__data_len$18[3:0]$9423
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9350
+ attribute \src "libresoc.v:169932.3-169933.53"
+ wire width 14 $0\alu_op__fn_unit$3[13:0]$9305
+ attribute \src "libresoc.v:169083.14-169083.44"
+ wire width 14 $0\alu_op__fn_unit$3[13:0]$9425
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9351
+ attribute \src "libresoc.v:169934.3-169935.67"
+ wire width 64 $0\alu_op__imm_data__data$4[63:0]$9307
+ attribute \src "libresoc.v:169107.14-169107.63"
+ wire width 64 $0\alu_op__imm_data__data$4[63:0]$9427
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__imm_data__ok$5$next[0:0]$9352
+ attribute \src "libresoc.v:169936.3-169937.63"
+ wire $0\alu_op__imm_data__ok$5[0:0]$9309
+ attribute \src "libresoc.v:169116.7-169116.38"
+ wire $0\alu_op__imm_data__ok$5[0:0]$9429
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 2 $0\alu_op__input_carry$14$next[1:0]$9353
+ attribute \src "libresoc.v:169954.3-169955.63"
+ wire width 2 $0\alu_op__input_carry$14[1:0]$9327
+ attribute \src "libresoc.v:169133.13-169133.44"
+ wire width 2 $0\alu_op__input_carry$14[1:0]$9431
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 32 $0\alu_op__insn$19$next[31:0]$9354
+ attribute \src "libresoc.v:169964.3-169965.49"
+ wire width 32 $0\alu_op__insn$19[31:0]$9337
+ attribute \src "libresoc.v:169146.14-169146.39"
+ wire width 32 $0\alu_op__insn$19[31:0]$9433
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 7 $0\alu_op__insn_type$2$next[6:0]$9355
+ attribute \src "libresoc.v:169930.3-169931.57"
+ wire width 7 $0\alu_op__insn_type$2[6:0]$9303
+ attribute \src "libresoc.v:169305.13-169305.42"
+ wire width 7 $0\alu_op__insn_type$2[6:0]$9435
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__invert_in$10$next[0:0]$9356
+ attribute \src "libresoc.v:169946.3-169947.59"
+ wire $0\alu_op__invert_in$10[0:0]$9319
+ attribute \src "libresoc.v:169389.7-169389.36"
+ wire $0\alu_op__invert_in$10[0:0]$9437
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__invert_out$12$next[0:0]$9357
+ attribute \src "libresoc.v:169950.3-169951.61"
+ wire $0\alu_op__invert_out$12[0:0]$9323
+ attribute \src "libresoc.v:169398.7-169398.37"
+ wire $0\alu_op__invert_out$12[0:0]$9439
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__is_32bit$16$next[0:0]$9358
+ attribute \src "libresoc.v:169958.3-169959.57"
+ wire $0\alu_op__is_32bit$16[0:0]$9331
+ attribute \src "libresoc.v:169407.7-169407.35"
+ wire $0\alu_op__is_32bit$16[0:0]$9441
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__is_signed$17$next[0:0]$9359
+ attribute \src "libresoc.v:169960.3-169961.59"
+ wire $0\alu_op__is_signed$17[0:0]$9333
+ attribute \src "libresoc.v:169416.7-169416.36"
+ wire $0\alu_op__is_signed$17[0:0]$9443
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__oe__oe$8$next[0:0]$9360
+ attribute \src "libresoc.v:169942.3-169943.51"
+ wire $0\alu_op__oe__oe$8[0:0]$9315
+ attribute \src "libresoc.v:169427.7-169427.32"
+ wire $0\alu_op__oe__oe$8[0:0]$9445
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__oe__ok$9$next[0:0]$9361
+ attribute \src "libresoc.v:169944.3-169945.51"
+ wire $0\alu_op__oe__ok$9[0:0]$9317
+ attribute \src "libresoc.v:169436.7-169436.32"
+ wire $0\alu_op__oe__ok$9[0:0]$9447
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__output_carry$15$next[0:0]$9362
+ attribute \src "libresoc.v:169956.3-169957.65"
+ wire $0\alu_op__output_carry$15[0:0]$9329
+ attribute \src "libresoc.v:169443.7-169443.39"
+ wire $0\alu_op__output_carry$15[0:0]$9449
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__rc__ok$7$next[0:0]$9363
+ attribute \src "libresoc.v:169940.3-169941.51"
+ wire $0\alu_op__rc__ok$7[0:0]$9313
+ attribute \src "libresoc.v:169454.7-169454.32"
+ wire $0\alu_op__rc__ok$7[0:0]$9451
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__rc__rc$6$next[0:0]$9364
+ attribute \src "libresoc.v:169938.3-169939.51"
+ wire $0\alu_op__rc__rc$6[0:0]$9311
+ attribute \src "libresoc.v:169461.7-169461.32"
+ wire $0\alu_op__rc__rc$6[0:0]$9453
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__write_cr0$13$next[0:0]$9365
+ attribute \src "libresoc.v:169952.3-169953.59"
+ wire $0\alu_op__write_cr0$13[0:0]$9325
+ attribute \src "libresoc.v:169470.7-169470.36"
+ wire $0\alu_op__write_cr0$13[0:0]$9455
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $0\alu_op__zero_a$11$next[0:0]$9366
+ attribute \src "libresoc.v:169948.3-169949.53"
+ wire $0\alu_op__zero_a$11[0:0]$9321
+ attribute \src "libresoc.v:169479.7-169479.33"
+ wire $0\alu_op__zero_a$11[0:0]$9457
+ attribute \src "libresoc.v:170126.3-170144.6"
+ wire width 4 $0\cr_a$22$next[3:0]$9398
+ attribute \src "libresoc.v:169922.3-169923.33"
+ wire width 4 $0\cr_a$22[3:0]$9295
+ attribute \src "libresoc.v:169492.13-169492.29"
+ wire width 4 $0\cr_a$22[3:0]$9459
+ attribute \src "libresoc.v:170126.3-170144.6"
+ wire $0\cr_a_ok$23$next[0:0]$9399
+ attribute \src "libresoc.v:169924.3-169925.39"
+ wire $0\cr_a_ok$23[0:0]$9297
+ attribute \src "libresoc.v:169501.7-169501.26"
+ wire $0\cr_a_ok$23[0:0]$9461
+ attribute \src "libresoc.v:169037.7-169037.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:170388.3-170400.6"
- wire width 2 $0\muxid$1$next[1:0]$9398
- attribute \src "libresoc.v:170302.3-170303.33"
- wire width 2 $0\muxid$1[1:0]$9391
- attribute \src "libresoc.v:169848.13-169848.29"
- wire width 2 $0\muxid$1[1:0]$9515
- attribute \src "libresoc.v:170443.3-170461.6"
- wire width 64 $0\o$20$next[63:0]$9444
- attribute \src "libresoc.v:170262.3-170263.27"
- wire width 64 $0\o$20[63:0]$9351
- attribute \src "libresoc.v:169863.14-169863.43"
- wire width 64 $0\o$20[63:0]$9517
- attribute \src "libresoc.v:170443.3-170461.6"
- wire $0\o_ok$21$next[0:0]$9445
- attribute \src "libresoc.v:170264.3-170265.33"
- wire $0\o_ok$21[0:0]$9353
- attribute \src "libresoc.v:169872.7-169872.23"
- wire $0\o_ok$21[0:0]$9519
- attribute \src "libresoc.v:170370.3-170387.6"
- wire $0\r_busy$next[0:0]$9394
- attribute \src "libresoc.v:170304.3-170305.29"
+ attribute \src "libresoc.v:170052.3-170064.6"
+ wire width 2 $0\muxid$1$next[1:0]$9346
+ attribute \src "libresoc.v:169966.3-169967.33"
+ wire width 2 $0\muxid$1[1:0]$9339
+ attribute \src "libresoc.v:169512.13-169512.29"
+ wire width 2 $0\muxid$1[1:0]$9463
+ attribute \src "libresoc.v:170107.3-170125.6"
+ wire width 64 $0\o$20$next[63:0]$9392
+ attribute \src "libresoc.v:169926.3-169927.27"
+ wire width 64 $0\o$20[63:0]$9299
+ attribute \src "libresoc.v:169527.14-169527.43"
+ wire width 64 $0\o$20[63:0]$9465
+ attribute \src "libresoc.v:170107.3-170125.6"
+ wire $0\o_ok$21$next[0:0]$9393
+ attribute \src "libresoc.v:169928.3-169929.33"
+ wire $0\o_ok$21[0:0]$9301
+ attribute \src "libresoc.v:169536.7-169536.23"
+ wire $0\o_ok$21[0:0]$9467
+ attribute \src "libresoc.v:170034.3-170051.6"
+ wire $0\r_busy$next[0:0]$9342
+ attribute \src "libresoc.v:169968.3-169969.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:170481.3-170499.6"
- wire width 2 $0\xer_ca$24$next[1:0]$9456
- attribute \src "libresoc.v:170254.3-170255.37"
- wire width 2 $0\xer_ca$24[1:0]$9343
- attribute \src "libresoc.v:170189.13-170189.31"
- wire width 2 $0\xer_ca$24[1:0]$9522
- attribute \src "libresoc.v:170481.3-170499.6"
- wire $0\xer_ca_ok$25$next[0:0]$9457
- attribute \src "libresoc.v:170256.3-170257.43"
- wire $0\xer_ca_ok$25[0:0]$9345
- attribute \src "libresoc.v:170198.7-170198.28"
- wire $0\xer_ca_ok$25[0:0]$9524
- attribute \src "libresoc.v:170500.3-170518.6"
- wire width 2 $0\xer_ov$26$next[1:0]$9462
- attribute \src "libresoc.v:170250.3-170251.37"
- wire width 2 $0\xer_ov$26[1:0]$9339
- attribute \src "libresoc.v:170209.13-170209.31"
- wire width 2 $0\xer_ov$26[1:0]$9526
- attribute \src "libresoc.v:170500.3-170518.6"
- wire $0\xer_ov_ok$27$next[0:0]$9463
- attribute \src "libresoc.v:170252.3-170253.43"
- wire $0\xer_ov_ok$27[0:0]$9341
- attribute \src "libresoc.v:170218.7-170218.28"
- wire $0\xer_ov_ok$27[0:0]$9528
- attribute \src "libresoc.v:170519.3-170537.6"
- wire $0\xer_so$28$next[0:0]$9468
- attribute \src "libresoc.v:170246.3-170247.37"
- wire $0\xer_so$28[0:0]$9335
- attribute \src "libresoc.v:170229.7-170229.25"
- wire $0\xer_so$28[0:0]$9530
- attribute \src "libresoc.v:170519.3-170537.6"
- wire $0\xer_so_ok$29$next[0:0]$9469
- attribute \src "libresoc.v:170248.3-170249.43"
- wire $0\xer_so_ok$29[0:0]$9337
- attribute \src "libresoc.v:170238.7-170238.28"
- wire $0\xer_so_ok$29[0:0]$9532
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 4 $1\alu_op__data_len$18$next[3:0]$9419
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9420
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9421
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__imm_data__ok$5$next[0:0]$9422
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 2 $1\alu_op__input_carry$14$next[1:0]$9423
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 32 $1\alu_op__insn$19$next[31:0]$9424
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 7 $1\alu_op__insn_type$2$next[6:0]$9425
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__invert_in$10$next[0:0]$9426
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__invert_out$12$next[0:0]$9427
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__is_32bit$16$next[0:0]$9428
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__is_signed$17$next[0:0]$9429
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__oe__oe$8$next[0:0]$9430
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__oe__ok$9$next[0:0]$9431
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__output_carry$15$next[0:0]$9432
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__rc__ok$7$next[0:0]$9433
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__rc__rc$6$next[0:0]$9434
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__write_cr0$13$next[0:0]$9435
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $1\alu_op__zero_a$11$next[0:0]$9436
- attribute \src "libresoc.v:170462.3-170480.6"
- wire width 4 $1\cr_a$22$next[3:0]$9452
- attribute \src "libresoc.v:170462.3-170480.6"
- wire $1\cr_a_ok$23$next[0:0]$9453
- attribute \src "libresoc.v:170388.3-170400.6"
- wire width 2 $1\muxid$1$next[1:0]$9399
- attribute \src "libresoc.v:170443.3-170461.6"
- wire width 64 $1\o$20$next[63:0]$9446
- attribute \src "libresoc.v:170443.3-170461.6"
- wire $1\o_ok$21$next[0:0]$9447
- attribute \src "libresoc.v:170370.3-170387.6"
- wire $1\r_busy$next[0:0]$9395
- attribute \src "libresoc.v:170182.7-170182.20"
+ attribute \src "libresoc.v:170145.3-170163.6"
+ wire width 2 $0\xer_ca$24$next[1:0]$9404
+ attribute \src "libresoc.v:169918.3-169919.37"
+ wire width 2 $0\xer_ca$24[1:0]$9291
+ attribute \src "libresoc.v:169853.13-169853.31"
+ wire width 2 $0\xer_ca$24[1:0]$9470
+ attribute \src "libresoc.v:170145.3-170163.6"
+ wire $0\xer_ca_ok$25$next[0:0]$9405
+ attribute \src "libresoc.v:169920.3-169921.43"
+ wire $0\xer_ca_ok$25[0:0]$9293
+ attribute \src "libresoc.v:169862.7-169862.28"
+ wire $0\xer_ca_ok$25[0:0]$9472
+ attribute \src "libresoc.v:170164.3-170182.6"
+ wire width 2 $0\xer_ov$26$next[1:0]$9410
+ attribute \src "libresoc.v:169914.3-169915.37"
+ wire width 2 $0\xer_ov$26[1:0]$9287
+ attribute \src "libresoc.v:169873.13-169873.31"
+ wire width 2 $0\xer_ov$26[1:0]$9474
+ attribute \src "libresoc.v:170164.3-170182.6"
+ wire $0\xer_ov_ok$27$next[0:0]$9411
+ attribute \src "libresoc.v:169916.3-169917.43"
+ wire $0\xer_ov_ok$27[0:0]$9289
+ attribute \src "libresoc.v:169882.7-169882.28"
+ wire $0\xer_ov_ok$27[0:0]$9476
+ attribute \src "libresoc.v:170183.3-170201.6"
+ wire $0\xer_so$28$next[0:0]$9416
+ attribute \src "libresoc.v:169910.3-169911.37"
+ wire $0\xer_so$28[0:0]$9283
+ attribute \src "libresoc.v:169893.7-169893.25"
+ wire $0\xer_so$28[0:0]$9478
+ attribute \src "libresoc.v:170183.3-170201.6"
+ wire $0\xer_so_ok$29$next[0:0]$9417
+ attribute \src "libresoc.v:169912.3-169913.43"
+ wire $0\xer_so_ok$29[0:0]$9285
+ attribute \src "libresoc.v:169902.7-169902.28"
+ wire $0\xer_so_ok$29[0:0]$9480
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 4 $1\alu_op__data_len$18$next[3:0]$9367
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9368
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9369
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__imm_data__ok$5$next[0:0]$9370
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 2 $1\alu_op__input_carry$14$next[1:0]$9371
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 32 $1\alu_op__insn$19$next[31:0]$9372
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 7 $1\alu_op__insn_type$2$next[6:0]$9373
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__invert_in$10$next[0:0]$9374
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__invert_out$12$next[0:0]$9375
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__is_32bit$16$next[0:0]$9376
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__is_signed$17$next[0:0]$9377
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__oe__oe$8$next[0:0]$9378
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__oe__ok$9$next[0:0]$9379
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__output_carry$15$next[0:0]$9380
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__rc__ok$7$next[0:0]$9381
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__rc__rc$6$next[0:0]$9382
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__write_cr0$13$next[0:0]$9383
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $1\alu_op__zero_a$11$next[0:0]$9384
+ attribute \src "libresoc.v:170126.3-170144.6"
+ wire width 4 $1\cr_a$22$next[3:0]$9400
+ attribute \src "libresoc.v:170126.3-170144.6"
+ wire $1\cr_a_ok$23$next[0:0]$9401
+ attribute \src "libresoc.v:170052.3-170064.6"
+ wire width 2 $1\muxid$1$next[1:0]$9347
+ attribute \src "libresoc.v:170107.3-170125.6"
+ wire width 64 $1\o$20$next[63:0]$9394
+ attribute \src "libresoc.v:170107.3-170125.6"
+ wire $1\o_ok$21$next[0:0]$9395
+ attribute \src "libresoc.v:170034.3-170051.6"
+ wire $1\r_busy$next[0:0]$9343
+ attribute \src "libresoc.v:169846.7-169846.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:170481.3-170499.6"
- wire width 2 $1\xer_ca$24$next[1:0]$9458
- attribute \src "libresoc.v:170481.3-170499.6"
- wire $1\xer_ca_ok$25$next[0:0]$9459
- attribute \src "libresoc.v:170500.3-170518.6"
- wire width 2 $1\xer_ov$26$next[1:0]$9464
- attribute \src "libresoc.v:170500.3-170518.6"
- wire $1\xer_ov_ok$27$next[0:0]$9465
- attribute \src "libresoc.v:170519.3-170537.6"
- wire $1\xer_so$28$next[0:0]$9470
- attribute \src "libresoc.v:170519.3-170537.6"
- wire $1\xer_so_ok$29$next[0:0]$9471
- attribute \src "libresoc.v:170401.3-170442.6"
- wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9437
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $2\alu_op__imm_data__ok$5$next[0:0]$9438
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $2\alu_op__oe__oe$8$next[0:0]$9439
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $2\alu_op__oe__ok$9$next[0:0]$9440
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $2\alu_op__rc__ok$7$next[0:0]$9441
- attribute \src "libresoc.v:170401.3-170442.6"
- wire $2\alu_op__rc__rc$6$next[0:0]$9442
- attribute \src "libresoc.v:170462.3-170480.6"
- wire $2\cr_a_ok$23$next[0:0]$9454
- attribute \src "libresoc.v:170443.3-170461.6"
- wire $2\o_ok$21$next[0:0]$9448
- attribute \src "libresoc.v:170370.3-170387.6"
- wire $2\r_busy$next[0:0]$9396
- attribute \src "libresoc.v:170481.3-170499.6"
- wire $2\xer_ca_ok$25$next[0:0]$9460
- attribute \src "libresoc.v:170500.3-170518.6"
- wire $2\xer_ov_ok$27$next[0:0]$9466
- attribute \src "libresoc.v:170519.3-170537.6"
- wire $2\xer_so_ok$29$next[0:0]$9472
- attribute \src "libresoc.v:170245.18-170245.118"
- wire $and$libresoc.v:170245$9333_Y
+ attribute \src "libresoc.v:170145.3-170163.6"
+ wire width 2 $1\xer_ca$24$next[1:0]$9406
+ attribute \src "libresoc.v:170145.3-170163.6"
+ wire $1\xer_ca_ok$25$next[0:0]$9407
+ attribute \src "libresoc.v:170164.3-170182.6"
+ wire width 2 $1\xer_ov$26$next[1:0]$9412
+ attribute \src "libresoc.v:170164.3-170182.6"
+ wire $1\xer_ov_ok$27$next[0:0]$9413
+ attribute \src "libresoc.v:170183.3-170201.6"
+ wire $1\xer_so$28$next[0:0]$9418
+ attribute \src "libresoc.v:170183.3-170201.6"
+ wire $1\xer_so_ok$29$next[0:0]$9419
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9385
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $2\alu_op__imm_data__ok$5$next[0:0]$9386
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $2\alu_op__oe__oe$8$next[0:0]$9387
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $2\alu_op__oe__ok$9$next[0:0]$9388
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $2\alu_op__rc__ok$7$next[0:0]$9389
+ attribute \src "libresoc.v:170065.3-170106.6"
+ wire $2\alu_op__rc__rc$6$next[0:0]$9390
+ attribute \src "libresoc.v:170126.3-170144.6"
+ wire $2\cr_a_ok$23$next[0:0]$9402
+ attribute \src "libresoc.v:170107.3-170125.6"
+ wire $2\o_ok$21$next[0:0]$9396
+ attribute \src "libresoc.v:170034.3-170051.6"
+ wire $2\r_busy$next[0:0]$9344
+ attribute \src "libresoc.v:170145.3-170163.6"
+ wire $2\xer_ca_ok$25$next[0:0]$9408
+ attribute \src "libresoc.v:170164.3-170182.6"
+ wire $2\xer_ov_ok$27$next[0:0]$9414
+ attribute \src "libresoc.v:170183.3-170201.6"
+ wire $2\xer_so_ok$29$next[0:0]$9420
+ attribute \src "libresoc.v:169909.18-169909.118"
+ wire $and$libresoc.v:169909$9281_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$11$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 64 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 25 \cr_a
wire \cr_a_ok$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$84
- attribute \src "libresoc.v:169373.7-169373.15"
+ attribute \src "libresoc.v:169037.7-169037.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$90
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:170245$9333
+ cell $and $and$libresoc.v:169909$9281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$59
connect \B \p_ready_o
- connect \Y $and$libresoc.v:170245$9333_Y
+ connect \Y $and$libresoc.v:169909$9281_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:170306.9-170309.4"
+ attribute \src "libresoc.v:169970.9-169973.4"
cell \n$4 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:170310.12-170365.4"
+ attribute \src "libresoc.v:169974.12-170029.4"
cell \output \output
connect \alu_op__data_len \output_alu_op__data_len
connect \alu_op__data_len$18 \output_alu_op__data_len$47
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:170366.9-170369.4"
+ attribute \src "libresoc.v:170030.9-170033.4"
cell \p$3 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:169373.7-169373.20"
- process $proc$libresoc.v:169373$9473
+ attribute \src "libresoc.v:169037.7-169037.20"
+ process $proc$libresoc.v:169037$9421
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:169380.13-169380.41"
- process $proc$libresoc.v:169380$9474
+ attribute \src "libresoc.v:169044.13-169044.41"
+ process $proc$libresoc.v:169044$9422
assign { } { }
- assign $0\alu_op__data_len$18[3:0]$9475 4'0000
+ assign $0\alu_op__data_len$18[3:0]$9423 4'0000
sync always
sync init
- update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9475
+ update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9423
end
- attribute \src "libresoc.v:169419.14-169419.44"
- process $proc$libresoc.v:169419$9476
+ attribute \src "libresoc.v:169083.14-169083.44"
+ process $proc$libresoc.v:169083$9424
assign { } { }
- assign $0\alu_op__fn_unit$3[13:0]$9477 14'00000000000000
+ assign $0\alu_op__fn_unit$3[13:0]$9425 14'00000000000000
sync always
sync init
- update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9477
+ update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9425
end
- attribute \src "libresoc.v:169443.14-169443.63"
- process $proc$libresoc.v:169443$9478
+ attribute \src "libresoc.v:169107.14-169107.63"
+ process $proc$libresoc.v:169107$9426
assign { } { }
- assign $0\alu_op__imm_data__data$4[63:0]$9479 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\alu_op__imm_data__data$4[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9479
+ update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9427
end
- attribute \src "libresoc.v:169452.7-169452.38"
- process $proc$libresoc.v:169452$9480
+ attribute \src "libresoc.v:169116.7-169116.38"
+ process $proc$libresoc.v:169116$9428
assign { } { }
- assign $0\alu_op__imm_data__ok$5[0:0]$9481 1'0
+ assign $0\alu_op__imm_data__ok$5[0:0]$9429 1'0
sync always
sync init
- update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9481
+ update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9429
end
- attribute \src "libresoc.v:169469.13-169469.44"
- process $proc$libresoc.v:169469$9482
+ attribute \src "libresoc.v:169133.13-169133.44"
+ process $proc$libresoc.v:169133$9430
assign { } { }
- assign $0\alu_op__input_carry$14[1:0]$9483 2'00
+ assign $0\alu_op__input_carry$14[1:0]$9431 2'00
sync always
sync init
- update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9483
+ update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9431
end
- attribute \src "libresoc.v:169482.14-169482.39"
- process $proc$libresoc.v:169482$9484
+ attribute \src "libresoc.v:169146.14-169146.39"
+ process $proc$libresoc.v:169146$9432
assign { } { }
- assign $0\alu_op__insn$19[31:0]$9485 0
+ assign $0\alu_op__insn$19[31:0]$9433 0
sync always
sync init
- update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9485
+ update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9433
end
- attribute \src "libresoc.v:169641.13-169641.42"
- process $proc$libresoc.v:169641$9486
+ attribute \src "libresoc.v:169305.13-169305.42"
+ process $proc$libresoc.v:169305$9434
assign { } { }
- assign $0\alu_op__insn_type$2[6:0]$9487 7'0000000
+ assign $0\alu_op__insn_type$2[6:0]$9435 7'0000000
sync always
sync init
- update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9487
+ update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9435
end
- attribute \src "libresoc.v:169725.7-169725.36"
- process $proc$libresoc.v:169725$9488
+ attribute \src "libresoc.v:169389.7-169389.36"
+ process $proc$libresoc.v:169389$9436
assign { } { }
- assign $0\alu_op__invert_in$10[0:0]$9489 1'0
+ assign $0\alu_op__invert_in$10[0:0]$9437 1'0
sync always
sync init
- update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9489
+ update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9437
end
- attribute \src "libresoc.v:169734.7-169734.37"
- process $proc$libresoc.v:169734$9490
+ attribute \src "libresoc.v:169398.7-169398.37"
+ process $proc$libresoc.v:169398$9438
assign { } { }
- assign $0\alu_op__invert_out$12[0:0]$9491 1'0
+ assign $0\alu_op__invert_out$12[0:0]$9439 1'0
sync always
sync init
- update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9491
+ update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9439
end
- attribute \src "libresoc.v:169743.7-169743.35"
- process $proc$libresoc.v:169743$9492
+ attribute \src "libresoc.v:169407.7-169407.35"
+ process $proc$libresoc.v:169407$9440
assign { } { }
- assign $0\alu_op__is_32bit$16[0:0]$9493 1'0
+ assign $0\alu_op__is_32bit$16[0:0]$9441 1'0
sync always
sync init
- update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9493
+ update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9441
end
- attribute \src "libresoc.v:169752.7-169752.36"
- process $proc$libresoc.v:169752$9494
+ attribute \src "libresoc.v:169416.7-169416.36"
+ process $proc$libresoc.v:169416$9442
assign { } { }
- assign $0\alu_op__is_signed$17[0:0]$9495 1'0
+ assign $0\alu_op__is_signed$17[0:0]$9443 1'0
sync always
sync init
- update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9495
+ update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9443
end
- attribute \src "libresoc.v:169763.7-169763.32"
- process $proc$libresoc.v:169763$9496
+ attribute \src "libresoc.v:169427.7-169427.32"
+ process $proc$libresoc.v:169427$9444
assign { } { }
- assign $0\alu_op__oe__oe$8[0:0]$9497 1'0
+ assign $0\alu_op__oe__oe$8[0:0]$9445 1'0
sync always
sync init
- update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9497
+ update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9445
end
- attribute \src "libresoc.v:169772.7-169772.32"
- process $proc$libresoc.v:169772$9498
+ attribute \src "libresoc.v:169436.7-169436.32"
+ process $proc$libresoc.v:169436$9446
assign { } { }
- assign $0\alu_op__oe__ok$9[0:0]$9499 1'0
+ assign $0\alu_op__oe__ok$9[0:0]$9447 1'0
sync always
sync init
- update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9499
+ update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9447
end
- attribute \src "libresoc.v:169779.7-169779.39"
- process $proc$libresoc.v:169779$9500
+ attribute \src "libresoc.v:169443.7-169443.39"
+ process $proc$libresoc.v:169443$9448
assign { } { }
- assign $0\alu_op__output_carry$15[0:0]$9501 1'0
+ assign $0\alu_op__output_carry$15[0:0]$9449 1'0
sync always
sync init
- update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9501
+ update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9449
end
- attribute \src "libresoc.v:169790.7-169790.32"
- process $proc$libresoc.v:169790$9502
+ attribute \src "libresoc.v:169454.7-169454.32"
+ process $proc$libresoc.v:169454$9450
assign { } { }
- assign $0\alu_op__rc__ok$7[0:0]$9503 1'0
+ assign $0\alu_op__rc__ok$7[0:0]$9451 1'0
sync always
sync init
- update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9503
+ update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9451
end
- attribute \src "libresoc.v:169797.7-169797.32"
- process $proc$libresoc.v:169797$9504
+ attribute \src "libresoc.v:169461.7-169461.32"
+ process $proc$libresoc.v:169461$9452
assign { } { }
- assign $0\alu_op__rc__rc$6[0:0]$9505 1'0
+ assign $0\alu_op__rc__rc$6[0:0]$9453 1'0
sync always
sync init
- update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9505
+ update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9453
end
- attribute \src "libresoc.v:169806.7-169806.36"
- process $proc$libresoc.v:169806$9506
+ attribute \src "libresoc.v:169470.7-169470.36"
+ process $proc$libresoc.v:169470$9454
assign { } { }
- assign $0\alu_op__write_cr0$13[0:0]$9507 1'0
+ assign $0\alu_op__write_cr0$13[0:0]$9455 1'0
sync always
sync init
- update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9507
+ update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9455
end
- attribute \src "libresoc.v:169815.7-169815.33"
- process $proc$libresoc.v:169815$9508
+ attribute \src "libresoc.v:169479.7-169479.33"
+ process $proc$libresoc.v:169479$9456
assign { } { }
- assign $0\alu_op__zero_a$11[0:0]$9509 1'0
+ assign $0\alu_op__zero_a$11[0:0]$9457 1'0
sync always
sync init
- update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9509
+ update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9457
end
- attribute \src "libresoc.v:169828.13-169828.29"
- process $proc$libresoc.v:169828$9510
+ attribute \src "libresoc.v:169492.13-169492.29"
+ process $proc$libresoc.v:169492$9458
assign { } { }
- assign $0\cr_a$22[3:0]$9511 4'0000
+ assign $0\cr_a$22[3:0]$9459 4'0000
sync always
sync init
- update \cr_a$22 $0\cr_a$22[3:0]$9511
+ update \cr_a$22 $0\cr_a$22[3:0]$9459
end
- attribute \src "libresoc.v:169837.7-169837.26"
- process $proc$libresoc.v:169837$9512
+ attribute \src "libresoc.v:169501.7-169501.26"
+ process $proc$libresoc.v:169501$9460
assign { } { }
- assign $0\cr_a_ok$23[0:0]$9513 1'0
+ assign $0\cr_a_ok$23[0:0]$9461 1'0
sync always
sync init
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9513
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9461
end
- attribute \src "libresoc.v:169848.13-169848.29"
- process $proc$libresoc.v:169848$9514
+ attribute \src "libresoc.v:169512.13-169512.29"
+ process $proc$libresoc.v:169512$9462
assign { } { }
- assign $0\muxid$1[1:0]$9515 2'00
+ assign $0\muxid$1[1:0]$9463 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9515
+ update \muxid$1 $0\muxid$1[1:0]$9463
end
- attribute \src "libresoc.v:169863.14-169863.43"
- process $proc$libresoc.v:169863$9516
+ attribute \src "libresoc.v:169527.14-169527.43"
+ process $proc$libresoc.v:169527$9464
assign { } { }
- assign $0\o$20[63:0]$9517 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$20[63:0]$9465 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$20 $0\o$20[63:0]$9517
+ update \o$20 $0\o$20[63:0]$9465
end
- attribute \src "libresoc.v:169872.7-169872.23"
- process $proc$libresoc.v:169872$9518
+ attribute \src "libresoc.v:169536.7-169536.23"
+ process $proc$libresoc.v:169536$9466
assign { } { }
- assign $0\o_ok$21[0:0]$9519 1'0
+ assign $0\o_ok$21[0:0]$9467 1'0
sync always
sync init
- update \o_ok$21 $0\o_ok$21[0:0]$9519
+ update \o_ok$21 $0\o_ok$21[0:0]$9467
end
- attribute \src "libresoc.v:170182.7-170182.20"
- process $proc$libresoc.v:170182$9520
+ attribute \src "libresoc.v:169846.7-169846.20"
+ process $proc$libresoc.v:169846$9468
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:170189.13-170189.31"
- process $proc$libresoc.v:170189$9521
+ attribute \src "libresoc.v:169853.13-169853.31"
+ process $proc$libresoc.v:169853$9469
assign { } { }
- assign $0\xer_ca$24[1:0]$9522 2'00
+ assign $0\xer_ca$24[1:0]$9470 2'00
sync always
sync init
- update \xer_ca$24 $0\xer_ca$24[1:0]$9522
+ update \xer_ca$24 $0\xer_ca$24[1:0]$9470
end
- attribute \src "libresoc.v:170198.7-170198.28"
- process $proc$libresoc.v:170198$9523
+ attribute \src "libresoc.v:169862.7-169862.28"
+ process $proc$libresoc.v:169862$9471
assign { } { }
- assign $0\xer_ca_ok$25[0:0]$9524 1'0
+ assign $0\xer_ca_ok$25[0:0]$9472 1'0
sync always
sync init
- update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9524
+ update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9472
end
- attribute \src "libresoc.v:170209.13-170209.31"
- process $proc$libresoc.v:170209$9525
+ attribute \src "libresoc.v:169873.13-169873.31"
+ process $proc$libresoc.v:169873$9473
assign { } { }
- assign $0\xer_ov$26[1:0]$9526 2'00
+ assign $0\xer_ov$26[1:0]$9474 2'00
sync always
sync init
- update \xer_ov$26 $0\xer_ov$26[1:0]$9526
+ update \xer_ov$26 $0\xer_ov$26[1:0]$9474
end
- attribute \src "libresoc.v:170218.7-170218.28"
- process $proc$libresoc.v:170218$9527
+ attribute \src "libresoc.v:169882.7-169882.28"
+ process $proc$libresoc.v:169882$9475
assign { } { }
- assign $0\xer_ov_ok$27[0:0]$9528 1'0
+ assign $0\xer_ov_ok$27[0:0]$9476 1'0
sync always
sync init
- update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9528
+ update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9476
end
- attribute \src "libresoc.v:170229.7-170229.25"
- process $proc$libresoc.v:170229$9529
+ attribute \src "libresoc.v:169893.7-169893.25"
+ process $proc$libresoc.v:169893$9477
assign { } { }
- assign $0\xer_so$28[0:0]$9530 1'0
+ assign $0\xer_so$28[0:0]$9478 1'0
sync always
sync init
- update \xer_so$28 $0\xer_so$28[0:0]$9530
+ update \xer_so$28 $0\xer_so$28[0:0]$9478
end
- attribute \src "libresoc.v:170238.7-170238.28"
- process $proc$libresoc.v:170238$9531
+ attribute \src "libresoc.v:169902.7-169902.28"
+ process $proc$libresoc.v:169902$9479
assign { } { }
- assign $0\xer_so_ok$29[0:0]$9532 1'0
+ assign $0\xer_so_ok$29[0:0]$9480 1'0
sync always
sync init
- update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9532
+ update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9480
end
- attribute \src "libresoc.v:170246.3-170247.37"
- process $proc$libresoc.v:170246$9334
+ attribute \src "libresoc.v:169910.3-169911.37"
+ process $proc$libresoc.v:169910$9282
assign { } { }
- assign $0\xer_so$28[0:0]$9335 \xer_so$28$next
+ assign $0\xer_so$28[0:0]$9283 \xer_so$28$next
sync posedge \coresync_clk
- update \xer_so$28 $0\xer_so$28[0:0]$9335
+ update \xer_so$28 $0\xer_so$28[0:0]$9283
end
- attribute \src "libresoc.v:170248.3-170249.43"
- process $proc$libresoc.v:170248$9336
+ attribute \src "libresoc.v:169912.3-169913.43"
+ process $proc$libresoc.v:169912$9284
assign { } { }
- assign $0\xer_so_ok$29[0:0]$9337 \xer_so_ok$29$next
+ assign $0\xer_so_ok$29[0:0]$9285 \xer_so_ok$29$next
sync posedge \coresync_clk
- update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9337
+ update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9285
end
- attribute \src "libresoc.v:170250.3-170251.37"
- process $proc$libresoc.v:170250$9338
+ attribute \src "libresoc.v:169914.3-169915.37"
+ process $proc$libresoc.v:169914$9286
assign { } { }
- assign $0\xer_ov$26[1:0]$9339 \xer_ov$26$next
+ assign $0\xer_ov$26[1:0]$9287 \xer_ov$26$next
sync posedge \coresync_clk
- update \xer_ov$26 $0\xer_ov$26[1:0]$9339
+ update \xer_ov$26 $0\xer_ov$26[1:0]$9287
end
- attribute \src "libresoc.v:170252.3-170253.43"
- process $proc$libresoc.v:170252$9340
+ attribute \src "libresoc.v:169916.3-169917.43"
+ process $proc$libresoc.v:169916$9288
assign { } { }
- assign $0\xer_ov_ok$27[0:0]$9341 \xer_ov_ok$27$next
+ assign $0\xer_ov_ok$27[0:0]$9289 \xer_ov_ok$27$next
sync posedge \coresync_clk
- update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9341
+ update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9289
end
- attribute \src "libresoc.v:170254.3-170255.37"
- process $proc$libresoc.v:170254$9342
+ attribute \src "libresoc.v:169918.3-169919.37"
+ process $proc$libresoc.v:169918$9290
assign { } { }
- assign $0\xer_ca$24[1:0]$9343 \xer_ca$24$next
+ assign $0\xer_ca$24[1:0]$9291 \xer_ca$24$next
sync posedge \coresync_clk
- update \xer_ca$24 $0\xer_ca$24[1:0]$9343
+ update \xer_ca$24 $0\xer_ca$24[1:0]$9291
end
- attribute \src "libresoc.v:170256.3-170257.43"
- process $proc$libresoc.v:170256$9344
+ attribute \src "libresoc.v:169920.3-169921.43"
+ process $proc$libresoc.v:169920$9292
assign { } { }
- assign $0\xer_ca_ok$25[0:0]$9345 \xer_ca_ok$25$next
+ assign $0\xer_ca_ok$25[0:0]$9293 \xer_ca_ok$25$next
sync posedge \coresync_clk
- update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9345
+ update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9293
end
- attribute \src "libresoc.v:170258.3-170259.33"
- process $proc$libresoc.v:170258$9346
+ attribute \src "libresoc.v:169922.3-169923.33"
+ process $proc$libresoc.v:169922$9294
assign { } { }
- assign $0\cr_a$22[3:0]$9347 \cr_a$22$next
+ assign $0\cr_a$22[3:0]$9295 \cr_a$22$next
sync posedge \coresync_clk
- update \cr_a$22 $0\cr_a$22[3:0]$9347
+ update \cr_a$22 $0\cr_a$22[3:0]$9295
end
- attribute \src "libresoc.v:170260.3-170261.39"
- process $proc$libresoc.v:170260$9348
+ attribute \src "libresoc.v:169924.3-169925.39"
+ process $proc$libresoc.v:169924$9296
assign { } { }
- assign $0\cr_a_ok$23[0:0]$9349 \cr_a_ok$23$next
+ assign $0\cr_a_ok$23[0:0]$9297 \cr_a_ok$23$next
sync posedge \coresync_clk
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9349
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9297
end
- attribute \src "libresoc.v:170262.3-170263.27"
- process $proc$libresoc.v:170262$9350
+ attribute \src "libresoc.v:169926.3-169927.27"
+ process $proc$libresoc.v:169926$9298
assign { } { }
- assign $0\o$20[63:0]$9351 \o$20$next
+ assign $0\o$20[63:0]$9299 \o$20$next
sync posedge \coresync_clk
- update \o$20 $0\o$20[63:0]$9351
+ update \o$20 $0\o$20[63:0]$9299
end
- attribute \src "libresoc.v:170264.3-170265.33"
- process $proc$libresoc.v:170264$9352
+ attribute \src "libresoc.v:169928.3-169929.33"
+ process $proc$libresoc.v:169928$9300
assign { } { }
- assign $0\o_ok$21[0:0]$9353 \o_ok$21$next
+ assign $0\o_ok$21[0:0]$9301 \o_ok$21$next
sync posedge \coresync_clk
- update \o_ok$21 $0\o_ok$21[0:0]$9353
+ update \o_ok$21 $0\o_ok$21[0:0]$9301
end
- attribute \src "libresoc.v:170266.3-170267.57"
- process $proc$libresoc.v:170266$9354
+ attribute \src "libresoc.v:169930.3-169931.57"
+ process $proc$libresoc.v:169930$9302
assign { } { }
- assign $0\alu_op__insn_type$2[6:0]$9355 \alu_op__insn_type$2$next
+ assign $0\alu_op__insn_type$2[6:0]$9303 \alu_op__insn_type$2$next
sync posedge \coresync_clk
- update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9355
+ update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9303
end
- attribute \src "libresoc.v:170268.3-170269.53"
- process $proc$libresoc.v:170268$9356
+ attribute \src "libresoc.v:169932.3-169933.53"
+ process $proc$libresoc.v:169932$9304
assign { } { }
- assign $0\alu_op__fn_unit$3[13:0]$9357 \alu_op__fn_unit$3$next
+ assign $0\alu_op__fn_unit$3[13:0]$9305 \alu_op__fn_unit$3$next
sync posedge \coresync_clk
- update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9357
+ update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9305
end
- attribute \src "libresoc.v:170270.3-170271.67"
- process $proc$libresoc.v:170270$9358
+ attribute \src "libresoc.v:169934.3-169935.67"
+ process $proc$libresoc.v:169934$9306
assign { } { }
- assign $0\alu_op__imm_data__data$4[63:0]$9359 \alu_op__imm_data__data$4$next
+ assign $0\alu_op__imm_data__data$4[63:0]$9307 \alu_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9359
+ update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9307
end
- attribute \src "libresoc.v:170272.3-170273.63"
- process $proc$libresoc.v:170272$9360
+ attribute \src "libresoc.v:169936.3-169937.63"
+ process $proc$libresoc.v:169936$9308
assign { } { }
- assign $0\alu_op__imm_data__ok$5[0:0]$9361 \alu_op__imm_data__ok$5$next
+ assign $0\alu_op__imm_data__ok$5[0:0]$9309 \alu_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9361
+ update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9309
end
- attribute \src "libresoc.v:170274.3-170275.51"
- process $proc$libresoc.v:170274$9362
+ attribute \src "libresoc.v:169938.3-169939.51"
+ process $proc$libresoc.v:169938$9310
assign { } { }
- assign $0\alu_op__rc__rc$6[0:0]$9363 \alu_op__rc__rc$6$next
+ assign $0\alu_op__rc__rc$6[0:0]$9311 \alu_op__rc__rc$6$next
sync posedge \coresync_clk
- update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9363
+ update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9311
end
- attribute \src "libresoc.v:170276.3-170277.51"
- process $proc$libresoc.v:170276$9364
+ attribute \src "libresoc.v:169940.3-169941.51"
+ process $proc$libresoc.v:169940$9312
assign { } { }
- assign $0\alu_op__rc__ok$7[0:0]$9365 \alu_op__rc__ok$7$next
+ assign $0\alu_op__rc__ok$7[0:0]$9313 \alu_op__rc__ok$7$next
sync posedge \coresync_clk
- update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9365
+ update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9313
end
- attribute \src "libresoc.v:170278.3-170279.51"
- process $proc$libresoc.v:170278$9366
+ attribute \src "libresoc.v:169942.3-169943.51"
+ process $proc$libresoc.v:169942$9314
assign { } { }
- assign $0\alu_op__oe__oe$8[0:0]$9367 \alu_op__oe__oe$8$next
+ assign $0\alu_op__oe__oe$8[0:0]$9315 \alu_op__oe__oe$8$next
sync posedge \coresync_clk
- update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9367
+ update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9315
end
- attribute \src "libresoc.v:170280.3-170281.51"
- process $proc$libresoc.v:170280$9368
+ attribute \src "libresoc.v:169944.3-169945.51"
+ process $proc$libresoc.v:169944$9316
assign { } { }
- assign $0\alu_op__oe__ok$9[0:0]$9369 \alu_op__oe__ok$9$next
+ assign $0\alu_op__oe__ok$9[0:0]$9317 \alu_op__oe__ok$9$next
sync posedge \coresync_clk
- update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9369
+ update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9317
end
- attribute \src "libresoc.v:170282.3-170283.59"
- process $proc$libresoc.v:170282$9370
+ attribute \src "libresoc.v:169946.3-169947.59"
+ process $proc$libresoc.v:169946$9318
assign { } { }
- assign $0\alu_op__invert_in$10[0:0]$9371 \alu_op__invert_in$10$next
+ assign $0\alu_op__invert_in$10[0:0]$9319 \alu_op__invert_in$10$next
sync posedge \coresync_clk
- update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9371
+ update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9319
end
- attribute \src "libresoc.v:170284.3-170285.53"
- process $proc$libresoc.v:170284$9372
+ attribute \src "libresoc.v:169948.3-169949.53"
+ process $proc$libresoc.v:169948$9320
assign { } { }
- assign $0\alu_op__zero_a$11[0:0]$9373 \alu_op__zero_a$11$next
+ assign $0\alu_op__zero_a$11[0:0]$9321 \alu_op__zero_a$11$next
sync posedge \coresync_clk
- update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9373
+ update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9321
end
- attribute \src "libresoc.v:170286.3-170287.61"
- process $proc$libresoc.v:170286$9374
+ attribute \src "libresoc.v:169950.3-169951.61"
+ process $proc$libresoc.v:169950$9322
assign { } { }
- assign $0\alu_op__invert_out$12[0:0]$9375 \alu_op__invert_out$12$next
+ assign $0\alu_op__invert_out$12[0:0]$9323 \alu_op__invert_out$12$next
sync posedge \coresync_clk
- update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9375
+ update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9323
end
- attribute \src "libresoc.v:170288.3-170289.59"
- process $proc$libresoc.v:170288$9376
+ attribute \src "libresoc.v:169952.3-169953.59"
+ process $proc$libresoc.v:169952$9324
assign { } { }
- assign $0\alu_op__write_cr0$13[0:0]$9377 \alu_op__write_cr0$13$next
+ assign $0\alu_op__write_cr0$13[0:0]$9325 \alu_op__write_cr0$13$next
sync posedge \coresync_clk
- update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9377
+ update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9325
end
- attribute \src "libresoc.v:170290.3-170291.63"
- process $proc$libresoc.v:170290$9378
+ attribute \src "libresoc.v:169954.3-169955.63"
+ process $proc$libresoc.v:169954$9326
assign { } { }
- assign $0\alu_op__input_carry$14[1:0]$9379 \alu_op__input_carry$14$next
+ assign $0\alu_op__input_carry$14[1:0]$9327 \alu_op__input_carry$14$next
sync posedge \coresync_clk
- update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9379
+ update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9327
end
- attribute \src "libresoc.v:170292.3-170293.65"
- process $proc$libresoc.v:170292$9380
+ attribute \src "libresoc.v:169956.3-169957.65"
+ process $proc$libresoc.v:169956$9328
assign { } { }
- assign $0\alu_op__output_carry$15[0:0]$9381 \alu_op__output_carry$15$next
+ assign $0\alu_op__output_carry$15[0:0]$9329 \alu_op__output_carry$15$next
sync posedge \coresync_clk
- update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9381
+ update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9329
end
- attribute \src "libresoc.v:170294.3-170295.57"
- process $proc$libresoc.v:170294$9382
+ attribute \src "libresoc.v:169958.3-169959.57"
+ process $proc$libresoc.v:169958$9330
assign { } { }
- assign $0\alu_op__is_32bit$16[0:0]$9383 \alu_op__is_32bit$16$next
+ assign $0\alu_op__is_32bit$16[0:0]$9331 \alu_op__is_32bit$16$next
sync posedge \coresync_clk
- update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9383
+ update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9331
end
- attribute \src "libresoc.v:170296.3-170297.59"
- process $proc$libresoc.v:170296$9384
+ attribute \src "libresoc.v:169960.3-169961.59"
+ process $proc$libresoc.v:169960$9332
assign { } { }
- assign $0\alu_op__is_signed$17[0:0]$9385 \alu_op__is_signed$17$next
+ assign $0\alu_op__is_signed$17[0:0]$9333 \alu_op__is_signed$17$next
sync posedge \coresync_clk
- update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9385
+ update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9333
end
- attribute \src "libresoc.v:170298.3-170299.57"
- process $proc$libresoc.v:170298$9386
+ attribute \src "libresoc.v:169962.3-169963.57"
+ process $proc$libresoc.v:169962$9334
assign { } { }
- assign $0\alu_op__data_len$18[3:0]$9387 \alu_op__data_len$18$next
+ assign $0\alu_op__data_len$18[3:0]$9335 \alu_op__data_len$18$next
sync posedge \coresync_clk
- update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9387
+ update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9335
end
- attribute \src "libresoc.v:170300.3-170301.49"
- process $proc$libresoc.v:170300$9388
+ attribute \src "libresoc.v:169964.3-169965.49"
+ process $proc$libresoc.v:169964$9336
assign { } { }
- assign $0\alu_op__insn$19[31:0]$9389 \alu_op__insn$19$next
+ assign $0\alu_op__insn$19[31:0]$9337 \alu_op__insn$19$next
sync posedge \coresync_clk
- update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9389
+ update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9337
end
- attribute \src "libresoc.v:170302.3-170303.33"
- process $proc$libresoc.v:170302$9390
+ attribute \src "libresoc.v:169966.3-169967.33"
+ process $proc$libresoc.v:169966$9338
assign { } { }
- assign $0\muxid$1[1:0]$9391 \muxid$1$next
+ assign $0\muxid$1[1:0]$9339 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9391
+ update \muxid$1 $0\muxid$1[1:0]$9339
end
- attribute \src "libresoc.v:170304.3-170305.29"
- process $proc$libresoc.v:170304$9392
+ attribute \src "libresoc.v:169968.3-169969.29"
+ process $proc$libresoc.v:169968$9340
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:170370.3-170387.6"
- process $proc$libresoc.v:170370$9393
+ attribute \src "libresoc.v:170034.3-170051.6"
+ process $proc$libresoc.v:170034$9341
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9394 $2\r_busy$next[0:0]$9396
- attribute \src "libresoc.v:170371.5-170371.29"
+ assign $0\r_busy$next[0:0]$9342 $2\r_busy$next[0:0]$9344
+ attribute \src "libresoc.v:170035.5-170035.29"
switch \initial
- attribute \src "libresoc.v:170371.9-170371.17"
+ attribute \src "libresoc.v:170035.9-170035.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9395 1'1
+ assign $1\r_busy$next[0:0]$9343 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9395 1'0
+ assign $1\r_busy$next[0:0]$9343 1'0
case
- assign $1\r_busy$next[0:0]$9395 \r_busy
+ assign $1\r_busy$next[0:0]$9343 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9396 1'0
+ assign $2\r_busy$next[0:0]$9344 1'0
case
- assign $2\r_busy$next[0:0]$9396 $1\r_busy$next[0:0]$9395
+ assign $2\r_busy$next[0:0]$9344 $1\r_busy$next[0:0]$9343
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9394
+ update \r_busy$next $0\r_busy$next[0:0]$9342
end
- attribute \src "libresoc.v:170388.3-170400.6"
- process $proc$libresoc.v:170388$9397
+ attribute \src "libresoc.v:170052.3-170064.6"
+ process $proc$libresoc.v:170052$9345
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9398 $1\muxid$1$next[1:0]$9399
- attribute \src "libresoc.v:170389.5-170389.29"
+ assign $0\muxid$1$next[1:0]$9346 $1\muxid$1$next[1:0]$9347
+ attribute \src "libresoc.v:170053.5-170053.29"
switch \initial
- attribute \src "libresoc.v:170389.9-170389.17"
+ attribute \src "libresoc.v:170053.9-170053.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9399 \muxid$62
+ assign $1\muxid$1$next[1:0]$9347 \muxid$62
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9399 \muxid$62
+ assign $1\muxid$1$next[1:0]$9347 \muxid$62
case
- assign $1\muxid$1$next[1:0]$9399 \muxid$1
+ assign $1\muxid$1$next[1:0]$9347 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9398
+ update \muxid$1$next $0\muxid$1$next[1:0]$9346
end
- attribute \src "libresoc.v:170401.3-170442.6"
- process $proc$libresoc.v:170401$9400
+ attribute \src "libresoc.v:170065.3-170106.6"
+ process $proc$libresoc.v:170065$9348
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_op__data_len$18$next[3:0]$9401 $1\alu_op__data_len$18$next[3:0]$9419
- assign $0\alu_op__fn_unit$3$next[13:0]$9402 $1\alu_op__fn_unit$3$next[13:0]$9420
+ assign $0\alu_op__data_len$18$next[3:0]$9349 $1\alu_op__data_len$18$next[3:0]$9367
+ assign $0\alu_op__fn_unit$3$next[13:0]$9350 $1\alu_op__fn_unit$3$next[13:0]$9368
assign { } { }
assign { } { }
- assign $0\alu_op__input_carry$14$next[1:0]$9405 $1\alu_op__input_carry$14$next[1:0]$9423
- assign $0\alu_op__insn$19$next[31:0]$9406 $1\alu_op__insn$19$next[31:0]$9424
- assign $0\alu_op__insn_type$2$next[6:0]$9407 $1\alu_op__insn_type$2$next[6:0]$9425
- assign $0\alu_op__invert_in$10$next[0:0]$9408 $1\alu_op__invert_in$10$next[0:0]$9426
- assign $0\alu_op__invert_out$12$next[0:0]$9409 $1\alu_op__invert_out$12$next[0:0]$9427
- assign $0\alu_op__is_32bit$16$next[0:0]$9410 $1\alu_op__is_32bit$16$next[0:0]$9428
- assign $0\alu_op__is_signed$17$next[0:0]$9411 $1\alu_op__is_signed$17$next[0:0]$9429
+ assign $0\alu_op__input_carry$14$next[1:0]$9353 $1\alu_op__input_carry$14$next[1:0]$9371
+ assign $0\alu_op__insn$19$next[31:0]$9354 $1\alu_op__insn$19$next[31:0]$9372
+ assign $0\alu_op__insn_type$2$next[6:0]$9355 $1\alu_op__insn_type$2$next[6:0]$9373
+ assign $0\alu_op__invert_in$10$next[0:0]$9356 $1\alu_op__invert_in$10$next[0:0]$9374
+ assign $0\alu_op__invert_out$12$next[0:0]$9357 $1\alu_op__invert_out$12$next[0:0]$9375
+ assign $0\alu_op__is_32bit$16$next[0:0]$9358 $1\alu_op__is_32bit$16$next[0:0]$9376
+ assign $0\alu_op__is_signed$17$next[0:0]$9359 $1\alu_op__is_signed$17$next[0:0]$9377
assign { } { }
assign { } { }
- assign $0\alu_op__output_carry$15$next[0:0]$9414 $1\alu_op__output_carry$15$next[0:0]$9432
+ assign $0\alu_op__output_carry$15$next[0:0]$9362 $1\alu_op__output_carry$15$next[0:0]$9380
assign { } { }
assign { } { }
- assign $0\alu_op__write_cr0$13$next[0:0]$9417 $1\alu_op__write_cr0$13$next[0:0]$9435
- assign $0\alu_op__zero_a$11$next[0:0]$9418 $1\alu_op__zero_a$11$next[0:0]$9436
- assign $0\alu_op__imm_data__data$4$next[63:0]$9403 $2\alu_op__imm_data__data$4$next[63:0]$9437
- assign $0\alu_op__imm_data__ok$5$next[0:0]$9404 $2\alu_op__imm_data__ok$5$next[0:0]$9438
- assign $0\alu_op__oe__oe$8$next[0:0]$9412 $2\alu_op__oe__oe$8$next[0:0]$9439
- assign $0\alu_op__oe__ok$9$next[0:0]$9413 $2\alu_op__oe__ok$9$next[0:0]$9440
- assign $0\alu_op__rc__ok$7$next[0:0]$9415 $2\alu_op__rc__ok$7$next[0:0]$9441
- assign $0\alu_op__rc__rc$6$next[0:0]$9416 $2\alu_op__rc__rc$6$next[0:0]$9442
- attribute \src "libresoc.v:170402.5-170402.29"
+ assign $0\alu_op__write_cr0$13$next[0:0]$9365 $1\alu_op__write_cr0$13$next[0:0]$9383
+ assign $0\alu_op__zero_a$11$next[0:0]$9366 $1\alu_op__zero_a$11$next[0:0]$9384
+ assign $0\alu_op__imm_data__data$4$next[63:0]$9351 $2\alu_op__imm_data__data$4$next[63:0]$9385
+ assign $0\alu_op__imm_data__ok$5$next[0:0]$9352 $2\alu_op__imm_data__ok$5$next[0:0]$9386
+ assign $0\alu_op__oe__oe$8$next[0:0]$9360 $2\alu_op__oe__oe$8$next[0:0]$9387
+ assign $0\alu_op__oe__ok$9$next[0:0]$9361 $2\alu_op__oe__ok$9$next[0:0]$9388
+ assign $0\alu_op__rc__ok$7$next[0:0]$9363 $2\alu_op__rc__ok$7$next[0:0]$9389
+ assign $0\alu_op__rc__rc$6$next[0:0]$9364 $2\alu_op__rc__rc$6$next[0:0]$9390
+ attribute \src "libresoc.v:170066.5-170066.29"
switch \initial
- attribute \src "libresoc.v:170402.9-170402.17"
+ attribute \src "libresoc.v:170066.9-170066.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$19$next[31:0]$9424 $1\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__oe__ok$9$next[0:0]$9431 $1\alu_op__oe__oe$8$next[0:0]$9430 $1\alu_op__rc__ok$7$next[0:0]$9433 $1\alu_op__rc__rc$6$next[0:0]$9434 $1\alu_op__imm_data__ok$5$next[0:0]$9422 $1\alu_op__imm_data__data$4$next[63:0]$9421 $1\alu_op__fn_unit$3$next[13:0]$9420 $1\alu_op__insn_type$2$next[6:0]$9425 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
+ assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$19$next[31:0]$9424 $1\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__oe__ok$9$next[0:0]$9431 $1\alu_op__oe__oe$8$next[0:0]$9430 $1\alu_op__rc__ok$7$next[0:0]$9433 $1\alu_op__rc__rc$6$next[0:0]$9434 $1\alu_op__imm_data__ok$5$next[0:0]$9422 $1\alu_op__imm_data__data$4$next[63:0]$9421 $1\alu_op__fn_unit$3$next[13:0]$9420 $1\alu_op__insn_type$2$next[6:0]$9425 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
+ assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
case
- assign $1\alu_op__data_len$18$next[3:0]$9419 \alu_op__data_len$18
- assign $1\alu_op__fn_unit$3$next[13:0]$9420 \alu_op__fn_unit$3
- assign $1\alu_op__imm_data__data$4$next[63:0]$9421 \alu_op__imm_data__data$4
- assign $1\alu_op__imm_data__ok$5$next[0:0]$9422 \alu_op__imm_data__ok$5
- assign $1\alu_op__input_carry$14$next[1:0]$9423 \alu_op__input_carry$14
- assign $1\alu_op__insn$19$next[31:0]$9424 \alu_op__insn$19
- assign $1\alu_op__insn_type$2$next[6:0]$9425 \alu_op__insn_type$2
- assign $1\alu_op__invert_in$10$next[0:0]$9426 \alu_op__invert_in$10
- assign $1\alu_op__invert_out$12$next[0:0]$9427 \alu_op__invert_out$12
- assign $1\alu_op__is_32bit$16$next[0:0]$9428 \alu_op__is_32bit$16
- assign $1\alu_op__is_signed$17$next[0:0]$9429 \alu_op__is_signed$17
- assign $1\alu_op__oe__oe$8$next[0:0]$9430 \alu_op__oe__oe$8
- assign $1\alu_op__oe__ok$9$next[0:0]$9431 \alu_op__oe__ok$9
- assign $1\alu_op__output_carry$15$next[0:0]$9432 \alu_op__output_carry$15
- assign $1\alu_op__rc__ok$7$next[0:0]$9433 \alu_op__rc__ok$7
- assign $1\alu_op__rc__rc$6$next[0:0]$9434 \alu_op__rc__rc$6
- assign $1\alu_op__write_cr0$13$next[0:0]$9435 \alu_op__write_cr0$13
- assign $1\alu_op__zero_a$11$next[0:0]$9436 \alu_op__zero_a$11
+ assign $1\alu_op__data_len$18$next[3:0]$9367 \alu_op__data_len$18
+ assign $1\alu_op__fn_unit$3$next[13:0]$9368 \alu_op__fn_unit$3
+ assign $1\alu_op__imm_data__data$4$next[63:0]$9369 \alu_op__imm_data__data$4
+ assign $1\alu_op__imm_data__ok$5$next[0:0]$9370 \alu_op__imm_data__ok$5
+ assign $1\alu_op__input_carry$14$next[1:0]$9371 \alu_op__input_carry$14
+ assign $1\alu_op__insn$19$next[31:0]$9372 \alu_op__insn$19
+ assign $1\alu_op__insn_type$2$next[6:0]$9373 \alu_op__insn_type$2
+ assign $1\alu_op__invert_in$10$next[0:0]$9374 \alu_op__invert_in$10
+ assign $1\alu_op__invert_out$12$next[0:0]$9375 \alu_op__invert_out$12
+ assign $1\alu_op__is_32bit$16$next[0:0]$9376 \alu_op__is_32bit$16
+ assign $1\alu_op__is_signed$17$next[0:0]$9377 \alu_op__is_signed$17
+ assign $1\alu_op__oe__oe$8$next[0:0]$9378 \alu_op__oe__oe$8
+ assign $1\alu_op__oe__ok$9$next[0:0]$9379 \alu_op__oe__ok$9
+ assign $1\alu_op__output_carry$15$next[0:0]$9380 \alu_op__output_carry$15
+ assign $1\alu_op__rc__ok$7$next[0:0]$9381 \alu_op__rc__ok$7
+ assign $1\alu_op__rc__rc$6$next[0:0]$9382 \alu_op__rc__rc$6
+ assign $1\alu_op__write_cr0$13$next[0:0]$9383 \alu_op__write_cr0$13
+ assign $1\alu_op__zero_a$11$next[0:0]$9384 \alu_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_op__imm_data__data$4$next[63:0]$9437 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_op__imm_data__ok$5$next[0:0]$9438 1'0
- assign $2\alu_op__rc__rc$6$next[0:0]$9442 1'0
- assign $2\alu_op__rc__ok$7$next[0:0]$9441 1'0
- assign $2\alu_op__oe__oe$8$next[0:0]$9439 1'0
- assign $2\alu_op__oe__ok$9$next[0:0]$9440 1'0
+ assign $2\alu_op__imm_data__data$4$next[63:0]$9385 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 1'0
+ assign $2\alu_op__rc__rc$6$next[0:0]$9390 1'0
+ assign $2\alu_op__rc__ok$7$next[0:0]$9389 1'0
+ assign $2\alu_op__oe__oe$8$next[0:0]$9387 1'0
+ assign $2\alu_op__oe__ok$9$next[0:0]$9388 1'0
case
- assign $2\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__imm_data__data$4$next[63:0]$9421
- assign $2\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__ok$5$next[0:0]$9422
- assign $2\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__oe__oe$8$next[0:0]$9430
- assign $2\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__ok$9$next[0:0]$9431
- assign $2\alu_op__rc__ok$7$next[0:0]$9441 $1\alu_op__rc__ok$7$next[0:0]$9433
- assign $2\alu_op__rc__rc$6$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9434
+ assign $2\alu_op__imm_data__data$4$next[63:0]$9385 $1\alu_op__imm_data__data$4$next[63:0]$9369
+ assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 $1\alu_op__imm_data__ok$5$next[0:0]$9370
+ assign $2\alu_op__oe__oe$8$next[0:0]$9387 $1\alu_op__oe__oe$8$next[0:0]$9378
+ assign $2\alu_op__oe__ok$9$next[0:0]$9388 $1\alu_op__oe__ok$9$next[0:0]$9379
+ assign $2\alu_op__rc__ok$7$next[0:0]$9389 $1\alu_op__rc__ok$7$next[0:0]$9381
+ assign $2\alu_op__rc__rc$6$next[0:0]$9390 $1\alu_op__rc__rc$6$next[0:0]$9382
end
sync always
- update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9401
- update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9402
- update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9403
- update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9404
- update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9405
- update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9406
- update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9407
- update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9408
- update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9409
- update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9410
- update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9411
- update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9412
- update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9413
- update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9414
- update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9415
- update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9416
- update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9417
- update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9418
+ update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9349
+ update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9350
+ update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9351
+ update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9352
+ update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9353
+ update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9354
+ update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9355
+ update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9356
+ update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9357
+ update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9358
+ update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9359
+ update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9360
+ update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9361
+ update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9362
+ update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9363
+ update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9364
+ update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9365
+ update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9366
end
- attribute \src "libresoc.v:170443.3-170461.6"
- process $proc$libresoc.v:170443$9443
+ attribute \src "libresoc.v:170107.3-170125.6"
+ process $proc$libresoc.v:170107$9391
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$20$next[63:0]$9444 $1\o$20$next[63:0]$9446
+ assign $0\o$20$next[63:0]$9392 $1\o$20$next[63:0]$9394
assign { } { }
- assign $0\o_ok$21$next[0:0]$9445 $2\o_ok$21$next[0:0]$9448
- attribute \src "libresoc.v:170444.5-170444.29"
+ assign $0\o_ok$21$next[0:0]$9393 $2\o_ok$21$next[0:0]$9396
+ attribute \src "libresoc.v:170108.5-170108.29"
switch \initial
- attribute \src "libresoc.v:170444.9-170444.17"
+ attribute \src "libresoc.v:170108.9-170108.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$9447 $1\o$20$next[63:0]$9446 } { \o_ok$82 \o$81 }
+ assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$9447 $1\o$20$next[63:0]$9446 } { \o_ok$82 \o$81 }
+ assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 }
case
- assign $1\o$20$next[63:0]$9446 \o$20
- assign $1\o_ok$21$next[0:0]$9447 \o_ok$21
+ assign $1\o$20$next[63:0]$9394 \o$20
+ assign $1\o_ok$21$next[0:0]$9395 \o_ok$21
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$21$next[0:0]$9448 1'0
+ assign $2\o_ok$21$next[0:0]$9396 1'0
case
- assign $2\o_ok$21$next[0:0]$9448 $1\o_ok$21$next[0:0]$9447
+ assign $2\o_ok$21$next[0:0]$9396 $1\o_ok$21$next[0:0]$9395
end
sync always
- update \o$20$next $0\o$20$next[63:0]$9444
- update \o_ok$21$next $0\o_ok$21$next[0:0]$9445
+ update \o$20$next $0\o$20$next[63:0]$9392
+ update \o_ok$21$next $0\o_ok$21$next[0:0]$9393
end
- attribute \src "libresoc.v:170462.3-170480.6"
- process $proc$libresoc.v:170462$9449
+ attribute \src "libresoc.v:170126.3-170144.6"
+ process $proc$libresoc.v:170126$9397
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$22$next[3:0]$9450 $1\cr_a$22$next[3:0]$9452
+ assign $0\cr_a$22$next[3:0]$9398 $1\cr_a$22$next[3:0]$9400
assign { } { }
- assign $0\cr_a_ok$23$next[0:0]$9451 $2\cr_a_ok$23$next[0:0]$9454
- attribute \src "libresoc.v:170463.5-170463.29"
+ assign $0\cr_a_ok$23$next[0:0]$9399 $2\cr_a_ok$23$next[0:0]$9402
+ attribute \src "libresoc.v:170127.5-170127.29"
switch \initial
- attribute \src "libresoc.v:170463.9-170463.17"
+ attribute \src "libresoc.v:170127.9-170127.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$9453 $1\cr_a$22$next[3:0]$9452 } { \cr_a_ok$84 \cr_a$83 }
+ assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$9453 $1\cr_a$22$next[3:0]$9452 } { \cr_a_ok$84 \cr_a$83 }
+ assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 }
case
- assign $1\cr_a$22$next[3:0]$9452 \cr_a$22
- assign $1\cr_a_ok$23$next[0:0]$9453 \cr_a_ok$23
+ assign $1\cr_a$22$next[3:0]$9400 \cr_a$22
+ assign $1\cr_a_ok$23$next[0:0]$9401 \cr_a_ok$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$23$next[0:0]$9454 1'0
+ assign $2\cr_a_ok$23$next[0:0]$9402 1'0
case
- assign $2\cr_a_ok$23$next[0:0]$9454 $1\cr_a_ok$23$next[0:0]$9453
+ assign $2\cr_a_ok$23$next[0:0]$9402 $1\cr_a_ok$23$next[0:0]$9401
end
sync always
- update \cr_a$22$next $0\cr_a$22$next[3:0]$9450
- update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9451
+ update \cr_a$22$next $0\cr_a$22$next[3:0]$9398
+ update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9399
end
- attribute \src "libresoc.v:170481.3-170499.6"
- process $proc$libresoc.v:170481$9455
+ attribute \src "libresoc.v:170145.3-170163.6"
+ process $proc$libresoc.v:170145$9403
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$24$next[1:0]$9456 $1\xer_ca$24$next[1:0]$9458
+ assign $0\xer_ca$24$next[1:0]$9404 $1\xer_ca$24$next[1:0]$9406
assign { } { }
- assign $0\xer_ca_ok$25$next[0:0]$9457 $2\xer_ca_ok$25$next[0:0]$9460
- attribute \src "libresoc.v:170482.5-170482.29"
+ assign $0\xer_ca_ok$25$next[0:0]$9405 $2\xer_ca_ok$25$next[0:0]$9408
+ attribute \src "libresoc.v:170146.5-170146.29"
switch \initial
- attribute \src "libresoc.v:170482.9-170482.17"
+ attribute \src "libresoc.v:170146.9-170146.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$25$next[0:0]$9459 $1\xer_ca$24$next[1:0]$9458 } { \xer_ca_ok$86 \xer_ca$85 }
+ assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$25$next[0:0]$9459 $1\xer_ca$24$next[1:0]$9458 } { \xer_ca_ok$86 \xer_ca$85 }
+ assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 }
case
- assign $1\xer_ca$24$next[1:0]$9458 \xer_ca$24
- assign $1\xer_ca_ok$25$next[0:0]$9459 \xer_ca_ok$25
+ assign $1\xer_ca$24$next[1:0]$9406 \xer_ca$24
+ assign $1\xer_ca_ok$25$next[0:0]$9407 \xer_ca_ok$25
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$25$next[0:0]$9460 1'0
+ assign $2\xer_ca_ok$25$next[0:0]$9408 1'0
case
- assign $2\xer_ca_ok$25$next[0:0]$9460 $1\xer_ca_ok$25$next[0:0]$9459
+ assign $2\xer_ca_ok$25$next[0:0]$9408 $1\xer_ca_ok$25$next[0:0]$9407
end
sync always
- update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9456
- update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9457
+ update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9404
+ update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9405
end
- attribute \src "libresoc.v:170500.3-170518.6"
- process $proc$libresoc.v:170500$9461
+ attribute \src "libresoc.v:170164.3-170182.6"
+ process $proc$libresoc.v:170164$9409
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$26$next[1:0]$9462 $1\xer_ov$26$next[1:0]$9464
+ assign $0\xer_ov$26$next[1:0]$9410 $1\xer_ov$26$next[1:0]$9412
assign { } { }
- assign $0\xer_ov_ok$27$next[0:0]$9463 $2\xer_ov_ok$27$next[0:0]$9466
- attribute \src "libresoc.v:170501.5-170501.29"
+ assign $0\xer_ov_ok$27$next[0:0]$9411 $2\xer_ov_ok$27$next[0:0]$9414
+ attribute \src "libresoc.v:170165.5-170165.29"
switch \initial
- attribute \src "libresoc.v:170501.9-170501.17"
+ attribute \src "libresoc.v:170165.9-170165.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$27$next[0:0]$9465 $1\xer_ov$26$next[1:0]$9464 } { \xer_ov_ok$88 \xer_ov$87 }
+ assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$27$next[0:0]$9465 $1\xer_ov$26$next[1:0]$9464 } { \xer_ov_ok$88 \xer_ov$87 }
+ assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 }
case
- assign $1\xer_ov$26$next[1:0]$9464 \xer_ov$26
- assign $1\xer_ov_ok$27$next[0:0]$9465 \xer_ov_ok$27
+ assign $1\xer_ov$26$next[1:0]$9412 \xer_ov$26
+ assign $1\xer_ov_ok$27$next[0:0]$9413 \xer_ov_ok$27
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$27$next[0:0]$9466 1'0
+ assign $2\xer_ov_ok$27$next[0:0]$9414 1'0
case
- assign $2\xer_ov_ok$27$next[0:0]$9466 $1\xer_ov_ok$27$next[0:0]$9465
+ assign $2\xer_ov_ok$27$next[0:0]$9414 $1\xer_ov_ok$27$next[0:0]$9413
end
sync always
- update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9462
- update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9463
+ update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9410
+ update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9411
end
- attribute \src "libresoc.v:170519.3-170537.6"
- process $proc$libresoc.v:170519$9467
+ attribute \src "libresoc.v:170183.3-170201.6"
+ process $proc$libresoc.v:170183$9415
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$28$next[0:0]$9468 $1\xer_so$28$next[0:0]$9470
+ assign $0\xer_so$28$next[0:0]$9416 $1\xer_so$28$next[0:0]$9418
assign { } { }
- assign $0\xer_so_ok$29$next[0:0]$9469 $2\xer_so_ok$29$next[0:0]$9472
- attribute \src "libresoc.v:170520.5-170520.29"
+ assign $0\xer_so_ok$29$next[0:0]$9417 $2\xer_so_ok$29$next[0:0]$9420
+ attribute \src "libresoc.v:170184.5-170184.29"
switch \initial
- attribute \src "libresoc.v:170520.9-170520.17"
+ attribute \src "libresoc.v:170184.9-170184.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$29$next[0:0]$9471 $1\xer_so$28$next[0:0]$9470 } { \xer_so_ok$90 \xer_so$89 }
+ assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$29$next[0:0]$9471 $1\xer_so$28$next[0:0]$9470 } { \xer_so_ok$90 \xer_so$89 }
+ assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 }
case
- assign $1\xer_so$28$next[0:0]$9470 \xer_so$28
- assign $1\xer_so_ok$29$next[0:0]$9471 \xer_so_ok$29
+ assign $1\xer_so$28$next[0:0]$9418 \xer_so$28
+ assign $1\xer_so_ok$29$next[0:0]$9419 \xer_so_ok$29
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$29$next[0:0]$9472 1'0
+ assign $2\xer_so_ok$29$next[0:0]$9420 1'0
case
- assign $2\xer_so_ok$29$next[0:0]$9472 $1\xer_so_ok$29$next[0:0]$9471
+ assign $2\xer_so_ok$29$next[0:0]$9420 $1\xer_so_ok$29$next[0:0]$9419
end
sync always
- update \xer_so$28$next $0\xer_so$28$next[0:0]$9468
- update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9469
+ update \xer_so$28$next $0\xer_so$28$next[0:0]$9416
+ update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9417
end
- connect \$60 $and$libresoc.v:170245$9333_Y
+ connect \$60 $and$libresoc.v:169909$9281_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 }
connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \output_muxid \muxid
end
-attribute \src "libresoc.v:170561.1-171630.10"
+attribute \src "libresoc.v:170225.1-171294.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2"
attribute \generator "nMigen"
module \pipe2$115
- attribute \src "libresoc.v:171576.3-171594.6"
- wire width 4 $0\cr_a$21$next[3:0]$9638
- attribute \src "libresoc.v:171382.3-171383.33"
- wire width 4 $0\cr_a$21[3:0]$9539
- attribute \src "libresoc.v:170573.13-170573.29"
- wire width 4 $0\cr_a$21[3:0]$9651
- attribute \src "libresoc.v:171576.3-171594.6"
- wire $0\cr_a_ok$22$next[0:0]$9639
- attribute \src "libresoc.v:171384.3-171385.39"
- wire $0\cr_a_ok$22[0:0]$9541
- attribute \src "libresoc.v:170582.7-170582.26"
- wire $0\cr_a_ok$22[0:0]$9653
- attribute \src "libresoc.v:170562.7-170562.20"
+ attribute \src "libresoc.v:171240.3-171258.6"
+ wire width 4 $0\cr_a$21$next[3:0]$9586
+ attribute \src "libresoc.v:171046.3-171047.33"
+ wire width 4 $0\cr_a$21[3:0]$9487
+ attribute \src "libresoc.v:170237.13-170237.29"
+ wire width 4 $0\cr_a$21[3:0]$9599
+ attribute \src "libresoc.v:171240.3-171258.6"
+ wire $0\cr_a_ok$22$next[0:0]$9587
+ attribute \src "libresoc.v:171048.3-171049.39"
+ wire $0\cr_a_ok$22[0:0]$9489
+ attribute \src "libresoc.v:170246.7-170246.26"
+ wire $0\cr_a_ok$22[0:0]$9601
+ attribute \src "libresoc.v:170226.7-170226.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:171503.3-171515.6"
- wire width 2 $0\muxid$1$next[1:0]$9588
- attribute \src "libresoc.v:171424.3-171425.33"
- wire width 2 $0\muxid$1[1:0]$9581
- attribute \src "libresoc.v:170593.13-170593.29"
- wire width 2 $0\muxid$1[1:0]$9655
- attribute \src "libresoc.v:171557.3-171575.6"
- wire width 64 $0\o$19$next[63:0]$9632
- attribute \src "libresoc.v:171386.3-171387.27"
- wire width 64 $0\o$19[63:0]$9543
- attribute \src "libresoc.v:170608.14-170608.43"
- wire width 64 $0\o$19[63:0]$9657
- attribute \src "libresoc.v:171557.3-171575.6"
- wire $0\o_ok$20$next[0:0]$9633
- attribute \src "libresoc.v:171388.3-171389.33"
- wire $0\o_ok$20[0:0]$9545
- attribute \src "libresoc.v:170617.7-170617.23"
- wire $0\o_ok$20[0:0]$9659
- attribute \src "libresoc.v:171485.3-171502.6"
- wire $0\r_busy$next[0:0]$9584
- attribute \src "libresoc.v:171426.3-171427.29"
+ attribute \src "libresoc.v:171167.3-171179.6"
+ wire width 2 $0\muxid$1$next[1:0]$9536
+ attribute \src "libresoc.v:171088.3-171089.33"
+ wire width 2 $0\muxid$1[1:0]$9529
+ attribute \src "libresoc.v:170257.13-170257.29"
+ wire width 2 $0\muxid$1[1:0]$9603
+ attribute \src "libresoc.v:171221.3-171239.6"
+ wire width 64 $0\o$19$next[63:0]$9580
+ attribute \src "libresoc.v:171050.3-171051.27"
+ wire width 64 $0\o$19[63:0]$9491
+ attribute \src "libresoc.v:170272.14-170272.43"
+ wire width 64 $0\o$19[63:0]$9605
+ attribute \src "libresoc.v:171221.3-171239.6"
+ wire $0\o_ok$20$next[0:0]$9581
+ attribute \src "libresoc.v:171052.3-171053.33"
+ wire $0\o_ok$20[0:0]$9493
+ attribute \src "libresoc.v:170281.7-170281.23"
+ wire $0\o_ok$20[0:0]$9607
+ attribute \src "libresoc.v:171149.3-171166.6"
+ wire $0\r_busy$next[0:0]$9532
+ attribute \src "libresoc.v:171090.3-171091.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9591
- attribute \src "libresoc.v:171392.3-171393.51"
- wire width 14 $0\sr_op__fn_unit$3[13:0]$9549
- attribute \src "libresoc.v:170950.14-170950.43"
- wire width 14 $0\sr_op__fn_unit$3[13:0]$9662
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9592
- attribute \src "libresoc.v:171394.3-171395.65"
- wire width 64 $0\sr_op__imm_data__data$4[63:0]$9551
- attribute \src "libresoc.v:170974.14-170974.62"
- wire width 64 $0\sr_op__imm_data__data$4[63:0]$9664
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__imm_data__ok$5$next[0:0]$9593
- attribute \src "libresoc.v:171396.3-171397.61"
- wire $0\sr_op__imm_data__ok$5[0:0]$9553
- attribute \src "libresoc.v:170983.7-170983.37"
- wire $0\sr_op__imm_data__ok$5[0:0]$9666
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 2 $0\sr_op__input_carry$12$next[1:0]$9594
- attribute \src "libresoc.v:171410.3-171411.61"
- wire width 2 $0\sr_op__input_carry$12[1:0]$9567
- attribute \src "libresoc.v:171000.13-171000.43"
- wire width 2 $0\sr_op__input_carry$12[1:0]$9668
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__input_cr$14$next[0:0]$9595
- attribute \src "libresoc.v:171414.3-171415.55"
- wire $0\sr_op__input_cr$14[0:0]$9571
- attribute \src "libresoc.v:171013.7-171013.34"
- wire $0\sr_op__input_cr$14[0:0]$9670
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 32 $0\sr_op__insn$18$next[31:0]$9596
- attribute \src "libresoc.v:171422.3-171423.47"
- wire width 32 $0\sr_op__insn$18[31:0]$9579
- attribute \src "libresoc.v:171022.14-171022.38"
- wire width 32 $0\sr_op__insn$18[31:0]$9672
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 7 $0\sr_op__insn_type$2$next[6:0]$9597
- attribute \src "libresoc.v:171390.3-171391.55"
- wire width 7 $0\sr_op__insn_type$2[6:0]$9547
- attribute \src "libresoc.v:171181.13-171181.41"
- wire width 7 $0\sr_op__insn_type$2[6:0]$9674
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__invert_in$11$next[0:0]$9598
- attribute \src "libresoc.v:171408.3-171409.57"
- wire $0\sr_op__invert_in$11[0:0]$9565
- attribute \src "libresoc.v:171265.7-171265.35"
- wire $0\sr_op__invert_in$11[0:0]$9676
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__is_32bit$16$next[0:0]$9599
- attribute \src "libresoc.v:171418.3-171419.55"
- wire $0\sr_op__is_32bit$16[0:0]$9575
- attribute \src "libresoc.v:171274.7-171274.34"
- wire $0\sr_op__is_32bit$16[0:0]$9678
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__is_signed$17$next[0:0]$9600
- attribute \src "libresoc.v:171420.3-171421.57"
- wire $0\sr_op__is_signed$17[0:0]$9577
- attribute \src "libresoc.v:171283.7-171283.35"
- wire $0\sr_op__is_signed$17[0:0]$9680
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__oe__oe$8$next[0:0]$9601
- attribute \src "libresoc.v:171402.3-171403.49"
- wire $0\sr_op__oe__oe$8[0:0]$9559
- attribute \src "libresoc.v:171294.7-171294.31"
- wire $0\sr_op__oe__oe$8[0:0]$9682
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__oe__ok$9$next[0:0]$9602
- attribute \src "libresoc.v:171404.3-171405.49"
- wire $0\sr_op__oe__ok$9[0:0]$9561
- attribute \src "libresoc.v:171303.7-171303.31"
- wire $0\sr_op__oe__ok$9[0:0]$9684
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__output_carry$13$next[0:0]$9603
- attribute \src "libresoc.v:171412.3-171413.63"
- wire $0\sr_op__output_carry$13[0:0]$9569
- attribute \src "libresoc.v:171310.7-171310.38"
- wire $0\sr_op__output_carry$13[0:0]$9686
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__output_cr$15$next[0:0]$9604
- attribute \src "libresoc.v:171416.3-171417.57"
- wire $0\sr_op__output_cr$15[0:0]$9573
- attribute \src "libresoc.v:171319.7-171319.35"
- wire $0\sr_op__output_cr$15[0:0]$9688
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__rc__ok$7$next[0:0]$9605
- attribute \src "libresoc.v:171400.3-171401.49"
- wire $0\sr_op__rc__ok$7[0:0]$9557
- attribute \src "libresoc.v:171330.7-171330.31"
- wire $0\sr_op__rc__ok$7[0:0]$9690
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__rc__rc$6$next[0:0]$9606
- attribute \src "libresoc.v:171398.3-171399.49"
- wire $0\sr_op__rc__rc$6[0:0]$9555
- attribute \src "libresoc.v:171339.7-171339.31"
- wire $0\sr_op__rc__rc$6[0:0]$9692
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $0\sr_op__write_cr0$10$next[0:0]$9607
- attribute \src "libresoc.v:171406.3-171407.57"
- wire $0\sr_op__write_cr0$10[0:0]$9563
- attribute \src "libresoc.v:171346.7-171346.35"
- wire $0\sr_op__write_cr0$10[0:0]$9694
- attribute \src "libresoc.v:171595.3-171613.6"
- wire width 2 $0\xer_ca$23$next[1:0]$9644
- attribute \src "libresoc.v:171378.3-171379.37"
- wire width 2 $0\xer_ca$23[1:0]$9535
- attribute \src "libresoc.v:171355.13-171355.31"
- wire width 2 $0\xer_ca$23[1:0]$9696
- attribute \src "libresoc.v:171595.3-171613.6"
- wire $0\xer_ca_ok$24$next[0:0]$9645
- attribute \src "libresoc.v:171380.3-171381.43"
- wire $0\xer_ca_ok$24[0:0]$9537
- attribute \src "libresoc.v:171364.7-171364.28"
- wire $0\xer_ca_ok$24[0:0]$9698
- attribute \src "libresoc.v:171576.3-171594.6"
- wire width 4 $1\cr_a$21$next[3:0]$9640
- attribute \src "libresoc.v:171576.3-171594.6"
- wire $1\cr_a_ok$22$next[0:0]$9641
- attribute \src "libresoc.v:171503.3-171515.6"
- wire width 2 $1\muxid$1$next[1:0]$9589
- attribute \src "libresoc.v:171557.3-171575.6"
- wire width 64 $1\o$19$next[63:0]$9634
- attribute \src "libresoc.v:171557.3-171575.6"
- wire $1\o_ok$20$next[0:0]$9635
- attribute \src "libresoc.v:171485.3-171502.6"
- wire $1\r_busy$next[0:0]$9585
- attribute \src "libresoc.v:170913.7-170913.20"
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9539
+ attribute \src "libresoc.v:171056.3-171057.51"
+ wire width 14 $0\sr_op__fn_unit$3[13:0]$9497
+ attribute \src "libresoc.v:170614.14-170614.43"
+ wire width 14 $0\sr_op__fn_unit$3[13:0]$9610
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9540
+ attribute \src "libresoc.v:171058.3-171059.65"
+ wire width 64 $0\sr_op__imm_data__data$4[63:0]$9499
+ attribute \src "libresoc.v:170638.14-170638.62"
+ wire width 64 $0\sr_op__imm_data__data$4[63:0]$9612
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__imm_data__ok$5$next[0:0]$9541
+ attribute \src "libresoc.v:171060.3-171061.61"
+ wire $0\sr_op__imm_data__ok$5[0:0]$9501
+ attribute \src "libresoc.v:170647.7-170647.37"
+ wire $0\sr_op__imm_data__ok$5[0:0]$9614
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 2 $0\sr_op__input_carry$12$next[1:0]$9542
+ attribute \src "libresoc.v:171074.3-171075.61"
+ wire width 2 $0\sr_op__input_carry$12[1:0]$9515
+ attribute \src "libresoc.v:170664.13-170664.43"
+ wire width 2 $0\sr_op__input_carry$12[1:0]$9616
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__input_cr$14$next[0:0]$9543
+ attribute \src "libresoc.v:171078.3-171079.55"
+ wire $0\sr_op__input_cr$14[0:0]$9519
+ attribute \src "libresoc.v:170677.7-170677.34"
+ wire $0\sr_op__input_cr$14[0:0]$9618
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 32 $0\sr_op__insn$18$next[31:0]$9544
+ attribute \src "libresoc.v:171086.3-171087.47"
+ wire width 32 $0\sr_op__insn$18[31:0]$9527
+ attribute \src "libresoc.v:170686.14-170686.38"
+ wire width 32 $0\sr_op__insn$18[31:0]$9620
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 7 $0\sr_op__insn_type$2$next[6:0]$9545
+ attribute \src "libresoc.v:171054.3-171055.55"
+ wire width 7 $0\sr_op__insn_type$2[6:0]$9495
+ attribute \src "libresoc.v:170845.13-170845.41"
+ wire width 7 $0\sr_op__insn_type$2[6:0]$9622
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__invert_in$11$next[0:0]$9546
+ attribute \src "libresoc.v:171072.3-171073.57"
+ wire $0\sr_op__invert_in$11[0:0]$9513
+ attribute \src "libresoc.v:170929.7-170929.35"
+ wire $0\sr_op__invert_in$11[0:0]$9624
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__is_32bit$16$next[0:0]$9547
+ attribute \src "libresoc.v:171082.3-171083.55"
+ wire $0\sr_op__is_32bit$16[0:0]$9523
+ attribute \src "libresoc.v:170938.7-170938.34"
+ wire $0\sr_op__is_32bit$16[0:0]$9626
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__is_signed$17$next[0:0]$9548
+ attribute \src "libresoc.v:171084.3-171085.57"
+ wire $0\sr_op__is_signed$17[0:0]$9525
+ attribute \src "libresoc.v:170947.7-170947.35"
+ wire $0\sr_op__is_signed$17[0:0]$9628
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__oe__oe$8$next[0:0]$9549
+ attribute \src "libresoc.v:171066.3-171067.49"
+ wire $0\sr_op__oe__oe$8[0:0]$9507
+ attribute \src "libresoc.v:170958.7-170958.31"
+ wire $0\sr_op__oe__oe$8[0:0]$9630
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__oe__ok$9$next[0:0]$9550
+ attribute \src "libresoc.v:171068.3-171069.49"
+ wire $0\sr_op__oe__ok$9[0:0]$9509
+ attribute \src "libresoc.v:170967.7-170967.31"
+ wire $0\sr_op__oe__ok$9[0:0]$9632
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__output_carry$13$next[0:0]$9551
+ attribute \src "libresoc.v:171076.3-171077.63"
+ wire $0\sr_op__output_carry$13[0:0]$9517
+ attribute \src "libresoc.v:170974.7-170974.38"
+ wire $0\sr_op__output_carry$13[0:0]$9634
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__output_cr$15$next[0:0]$9552
+ attribute \src "libresoc.v:171080.3-171081.57"
+ wire $0\sr_op__output_cr$15[0:0]$9521
+ attribute \src "libresoc.v:170983.7-170983.35"
+ wire $0\sr_op__output_cr$15[0:0]$9636
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__rc__ok$7$next[0:0]$9553
+ attribute \src "libresoc.v:171064.3-171065.49"
+ wire $0\sr_op__rc__ok$7[0:0]$9505
+ attribute \src "libresoc.v:170994.7-170994.31"
+ wire $0\sr_op__rc__ok$7[0:0]$9638
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__rc__rc$6$next[0:0]$9554
+ attribute \src "libresoc.v:171062.3-171063.49"
+ wire $0\sr_op__rc__rc$6[0:0]$9503
+ attribute \src "libresoc.v:171003.7-171003.31"
+ wire $0\sr_op__rc__rc$6[0:0]$9640
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $0\sr_op__write_cr0$10$next[0:0]$9555
+ attribute \src "libresoc.v:171070.3-171071.57"
+ wire $0\sr_op__write_cr0$10[0:0]$9511
+ attribute \src "libresoc.v:171010.7-171010.35"
+ wire $0\sr_op__write_cr0$10[0:0]$9642
+ attribute \src "libresoc.v:171259.3-171277.6"
+ wire width 2 $0\xer_ca$23$next[1:0]$9592
+ attribute \src "libresoc.v:171042.3-171043.37"
+ wire width 2 $0\xer_ca$23[1:0]$9483
+ attribute \src "libresoc.v:171019.13-171019.31"
+ wire width 2 $0\xer_ca$23[1:0]$9644
+ attribute \src "libresoc.v:171259.3-171277.6"
+ wire $0\xer_ca_ok$24$next[0:0]$9593
+ attribute \src "libresoc.v:171044.3-171045.43"
+ wire $0\xer_ca_ok$24[0:0]$9485
+ attribute \src "libresoc.v:171028.7-171028.28"
+ wire $0\xer_ca_ok$24[0:0]$9646
+ attribute \src "libresoc.v:171240.3-171258.6"
+ wire width 4 $1\cr_a$21$next[3:0]$9588
+ attribute \src "libresoc.v:171240.3-171258.6"
+ wire $1\cr_a_ok$22$next[0:0]$9589
+ attribute \src "libresoc.v:171167.3-171179.6"
+ wire width 2 $1\muxid$1$next[1:0]$9537
+ attribute \src "libresoc.v:171221.3-171239.6"
+ wire width 64 $1\o$19$next[63:0]$9582
+ attribute \src "libresoc.v:171221.3-171239.6"
+ wire $1\o_ok$20$next[0:0]$9583
+ attribute \src "libresoc.v:171149.3-171166.6"
+ wire $1\r_busy$next[0:0]$9533
+ attribute \src "libresoc.v:170577.7-170577.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9608
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9609
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__imm_data__ok$5$next[0:0]$9610
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 2 $1\sr_op__input_carry$12$next[1:0]$9611
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__input_cr$14$next[0:0]$9612
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 32 $1\sr_op__insn$18$next[31:0]$9613
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 7 $1\sr_op__insn_type$2$next[6:0]$9614
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__invert_in$11$next[0:0]$9615
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__is_32bit$16$next[0:0]$9616
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__is_signed$17$next[0:0]$9617
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__oe__oe$8$next[0:0]$9618
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__oe__ok$9$next[0:0]$9619
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__output_carry$13$next[0:0]$9620
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__output_cr$15$next[0:0]$9621
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__rc__ok$7$next[0:0]$9622
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__rc__rc$6$next[0:0]$9623
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $1\sr_op__write_cr0$10$next[0:0]$9624
- attribute \src "libresoc.v:171595.3-171613.6"
- wire width 2 $1\xer_ca$23$next[1:0]$9646
- attribute \src "libresoc.v:171595.3-171613.6"
- wire $1\xer_ca_ok$24$next[0:0]$9647
- attribute \src "libresoc.v:171576.3-171594.6"
- wire $2\cr_a_ok$22$next[0:0]$9642
- attribute \src "libresoc.v:171557.3-171575.6"
- wire $2\o_ok$20$next[0:0]$9636
- attribute \src "libresoc.v:171485.3-171502.6"
- wire $2\r_busy$next[0:0]$9586
- attribute \src "libresoc.v:171516.3-171556.6"
- wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9625
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $2\sr_op__imm_data__ok$5$next[0:0]$9626
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $2\sr_op__oe__oe$8$next[0:0]$9627
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $2\sr_op__oe__ok$9$next[0:0]$9628
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $2\sr_op__rc__ok$7$next[0:0]$9629
- attribute \src "libresoc.v:171516.3-171556.6"
- wire $2\sr_op__rc__rc$6$next[0:0]$9630
- attribute \src "libresoc.v:171595.3-171613.6"
- wire $2\xer_ca_ok$24$next[0:0]$9648
- attribute \src "libresoc.v:171377.18-171377.118"
- wire $and$libresoc.v:171377$9533_Y
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9556
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9557
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__imm_data__ok$5$next[0:0]$9558
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 2 $1\sr_op__input_carry$12$next[1:0]$9559
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__input_cr$14$next[0:0]$9560
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 32 $1\sr_op__insn$18$next[31:0]$9561
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 7 $1\sr_op__insn_type$2$next[6:0]$9562
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__invert_in$11$next[0:0]$9563
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__is_32bit$16$next[0:0]$9564
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__is_signed$17$next[0:0]$9565
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__oe__oe$8$next[0:0]$9566
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__oe__ok$9$next[0:0]$9567
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__output_carry$13$next[0:0]$9568
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__output_cr$15$next[0:0]$9569
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__rc__ok$7$next[0:0]$9570
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__rc__rc$6$next[0:0]$9571
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $1\sr_op__write_cr0$10$next[0:0]$9572
+ attribute \src "libresoc.v:171259.3-171277.6"
+ wire width 2 $1\xer_ca$23$next[1:0]$9594
+ attribute \src "libresoc.v:171259.3-171277.6"
+ wire $1\xer_ca_ok$24$next[0:0]$9595
+ attribute \src "libresoc.v:171240.3-171258.6"
+ wire $2\cr_a_ok$22$next[0:0]$9590
+ attribute \src "libresoc.v:171221.3-171239.6"
+ wire $2\o_ok$20$next[0:0]$9584
+ attribute \src "libresoc.v:171149.3-171166.6"
+ wire $2\r_busy$next[0:0]$9534
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9573
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $2\sr_op__imm_data__ok$5$next[0:0]$9574
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $2\sr_op__oe__oe$8$next[0:0]$9575
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $2\sr_op__oe__ok$9$next[0:0]$9576
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $2\sr_op__rc__ok$7$next[0:0]$9577
+ attribute \src "libresoc.v:171180.3-171220.6"
+ wire $2\sr_op__rc__rc$6$next[0:0]$9578
+ attribute \src "libresoc.v:171259.3-171277.6"
+ wire $2\xer_ca_ok$24$next[0:0]$9596
+ attribute \src "libresoc.v:171041.18-171041.118"
+ wire $and$libresoc.v:171041$9481_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 56 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 24 \cr_a
wire \cr_a_ok$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$74
- attribute \src "libresoc.v:170562.7-170562.15"
+ attribute \src "libresoc.v:170226.7-170226.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$48
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:171377$9533
+ cell $and $and$libresoc.v:171041$9481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$50
connect \B \p_ready_o
- connect \Y $and$libresoc.v:171377$9533_Y
+ connect \Y $and$libresoc.v:171041$9481_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171428.11-171431.4"
+ attribute \src "libresoc.v:171092.11-171095.4"
cell \n$117 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171432.16-171480.4"
+ attribute \src "libresoc.v:171096.16-171144.4"
cell \output$118 \output
connect \cr_a \output_cr_a
connect \cr_a$21 \output_cr_a$45
connect \xer_so \output_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171481.11-171484.4"
+ attribute \src "libresoc.v:171145.11-171148.4"
cell \p$116 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:170562.7-170562.20"
- process $proc$libresoc.v:170562$9649
+ attribute \src "libresoc.v:170226.7-170226.20"
+ process $proc$libresoc.v:170226$9597
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:170573.13-170573.29"
- process $proc$libresoc.v:170573$9650
+ attribute \src "libresoc.v:170237.13-170237.29"
+ process $proc$libresoc.v:170237$9598
assign { } { }
- assign $0\cr_a$21[3:0]$9651 4'0000
+ assign $0\cr_a$21[3:0]$9599 4'0000
sync always
sync init
- update \cr_a$21 $0\cr_a$21[3:0]$9651
+ update \cr_a$21 $0\cr_a$21[3:0]$9599
end
- attribute \src "libresoc.v:170582.7-170582.26"
- process $proc$libresoc.v:170582$9652
+ attribute \src "libresoc.v:170246.7-170246.26"
+ process $proc$libresoc.v:170246$9600
assign { } { }
- assign $0\cr_a_ok$22[0:0]$9653 1'0
+ assign $0\cr_a_ok$22[0:0]$9601 1'0
sync always
sync init
- update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9653
+ update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9601
end
- attribute \src "libresoc.v:170593.13-170593.29"
- process $proc$libresoc.v:170593$9654
+ attribute \src "libresoc.v:170257.13-170257.29"
+ process $proc$libresoc.v:170257$9602
assign { } { }
- assign $0\muxid$1[1:0]$9655 2'00
+ assign $0\muxid$1[1:0]$9603 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9655
+ update \muxid$1 $0\muxid$1[1:0]$9603
end
- attribute \src "libresoc.v:170608.14-170608.43"
- process $proc$libresoc.v:170608$9656
+ attribute \src "libresoc.v:170272.14-170272.43"
+ process $proc$libresoc.v:170272$9604
assign { } { }
- assign $0\o$19[63:0]$9657 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$19[63:0]$9605 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$19 $0\o$19[63:0]$9657
+ update \o$19 $0\o$19[63:0]$9605
end
- attribute \src "libresoc.v:170617.7-170617.23"
- process $proc$libresoc.v:170617$9658
+ attribute \src "libresoc.v:170281.7-170281.23"
+ process $proc$libresoc.v:170281$9606
assign { } { }
- assign $0\o_ok$20[0:0]$9659 1'0
+ assign $0\o_ok$20[0:0]$9607 1'0
sync always
sync init
- update \o_ok$20 $0\o_ok$20[0:0]$9659
+ update \o_ok$20 $0\o_ok$20[0:0]$9607
end
- attribute \src "libresoc.v:170913.7-170913.20"
- process $proc$libresoc.v:170913$9660
+ attribute \src "libresoc.v:170577.7-170577.20"
+ process $proc$libresoc.v:170577$9608
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:170950.14-170950.43"
- process $proc$libresoc.v:170950$9661
+ attribute \src "libresoc.v:170614.14-170614.43"
+ process $proc$libresoc.v:170614$9609
assign { } { }
- assign $0\sr_op__fn_unit$3[13:0]$9662 14'00000000000000
+ assign $0\sr_op__fn_unit$3[13:0]$9610 14'00000000000000
sync always
sync init
- update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9662
+ update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9610
end
- attribute \src "libresoc.v:170974.14-170974.62"
- process $proc$libresoc.v:170974$9663
+ attribute \src "libresoc.v:170638.14-170638.62"
+ process $proc$libresoc.v:170638$9611
assign { } { }
- assign $0\sr_op__imm_data__data$4[63:0]$9664 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\sr_op__imm_data__data$4[63:0]$9612 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9664
+ update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9612
end
- attribute \src "libresoc.v:170983.7-170983.37"
- process $proc$libresoc.v:170983$9665
+ attribute \src "libresoc.v:170647.7-170647.37"
+ process $proc$libresoc.v:170647$9613
assign { } { }
- assign $0\sr_op__imm_data__ok$5[0:0]$9666 1'0
+ assign $0\sr_op__imm_data__ok$5[0:0]$9614 1'0
sync always
sync init
- update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9666
+ update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9614
end
- attribute \src "libresoc.v:171000.13-171000.43"
- process $proc$libresoc.v:171000$9667
+ attribute \src "libresoc.v:170664.13-170664.43"
+ process $proc$libresoc.v:170664$9615
assign { } { }
- assign $0\sr_op__input_carry$12[1:0]$9668 2'00
+ assign $0\sr_op__input_carry$12[1:0]$9616 2'00
sync always
sync init
- update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9668
+ update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9616
end
- attribute \src "libresoc.v:171013.7-171013.34"
- process $proc$libresoc.v:171013$9669
+ attribute \src "libresoc.v:170677.7-170677.34"
+ process $proc$libresoc.v:170677$9617
assign { } { }
- assign $0\sr_op__input_cr$14[0:0]$9670 1'0
+ assign $0\sr_op__input_cr$14[0:0]$9618 1'0
sync always
sync init
- update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9670
+ update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9618
end
- attribute \src "libresoc.v:171022.14-171022.38"
- process $proc$libresoc.v:171022$9671
+ attribute \src "libresoc.v:170686.14-170686.38"
+ process $proc$libresoc.v:170686$9619
assign { } { }
- assign $0\sr_op__insn$18[31:0]$9672 0
+ assign $0\sr_op__insn$18[31:0]$9620 0
sync always
sync init
- update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9672
+ update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9620
end
- attribute \src "libresoc.v:171181.13-171181.41"
- process $proc$libresoc.v:171181$9673
+ attribute \src "libresoc.v:170845.13-170845.41"
+ process $proc$libresoc.v:170845$9621
assign { } { }
- assign $0\sr_op__insn_type$2[6:0]$9674 7'0000000
+ assign $0\sr_op__insn_type$2[6:0]$9622 7'0000000
sync always
sync init
- update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9674
+ update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9622
end
- attribute \src "libresoc.v:171265.7-171265.35"
- process $proc$libresoc.v:171265$9675
+ attribute \src "libresoc.v:170929.7-170929.35"
+ process $proc$libresoc.v:170929$9623
assign { } { }
- assign $0\sr_op__invert_in$11[0:0]$9676 1'0
+ assign $0\sr_op__invert_in$11[0:0]$9624 1'0
sync always
sync init
- update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9676
+ update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9624
end
- attribute \src "libresoc.v:171274.7-171274.34"
- process $proc$libresoc.v:171274$9677
+ attribute \src "libresoc.v:170938.7-170938.34"
+ process $proc$libresoc.v:170938$9625
assign { } { }
- assign $0\sr_op__is_32bit$16[0:0]$9678 1'0
+ assign $0\sr_op__is_32bit$16[0:0]$9626 1'0
sync always
sync init
- update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9678
+ update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9626
end
- attribute \src "libresoc.v:171283.7-171283.35"
- process $proc$libresoc.v:171283$9679
+ attribute \src "libresoc.v:170947.7-170947.35"
+ process $proc$libresoc.v:170947$9627
assign { } { }
- assign $0\sr_op__is_signed$17[0:0]$9680 1'0
+ assign $0\sr_op__is_signed$17[0:0]$9628 1'0
sync always
sync init
- update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9680
+ update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9628
end
- attribute \src "libresoc.v:171294.7-171294.31"
- process $proc$libresoc.v:171294$9681
+ attribute \src "libresoc.v:170958.7-170958.31"
+ process $proc$libresoc.v:170958$9629
assign { } { }
- assign $0\sr_op__oe__oe$8[0:0]$9682 1'0
+ assign $0\sr_op__oe__oe$8[0:0]$9630 1'0
sync always
sync init
- update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9682
+ update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9630
end
- attribute \src "libresoc.v:171303.7-171303.31"
- process $proc$libresoc.v:171303$9683
+ attribute \src "libresoc.v:170967.7-170967.31"
+ process $proc$libresoc.v:170967$9631
assign { } { }
- assign $0\sr_op__oe__ok$9[0:0]$9684 1'0
+ assign $0\sr_op__oe__ok$9[0:0]$9632 1'0
sync always
sync init
- update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9684
+ update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9632
end
- attribute \src "libresoc.v:171310.7-171310.38"
- process $proc$libresoc.v:171310$9685
+ attribute \src "libresoc.v:170974.7-170974.38"
+ process $proc$libresoc.v:170974$9633
assign { } { }
- assign $0\sr_op__output_carry$13[0:0]$9686 1'0
+ assign $0\sr_op__output_carry$13[0:0]$9634 1'0
sync always
sync init
- update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9686
+ update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9634
end
- attribute \src "libresoc.v:171319.7-171319.35"
- process $proc$libresoc.v:171319$9687
+ attribute \src "libresoc.v:170983.7-170983.35"
+ process $proc$libresoc.v:170983$9635
assign { } { }
- assign $0\sr_op__output_cr$15[0:0]$9688 1'0
+ assign $0\sr_op__output_cr$15[0:0]$9636 1'0
sync always
sync init
- update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9688
+ update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9636
end
- attribute \src "libresoc.v:171330.7-171330.31"
- process $proc$libresoc.v:171330$9689
+ attribute \src "libresoc.v:170994.7-170994.31"
+ process $proc$libresoc.v:170994$9637
assign { } { }
- assign $0\sr_op__rc__ok$7[0:0]$9690 1'0
+ assign $0\sr_op__rc__ok$7[0:0]$9638 1'0
sync always
sync init
- update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9690
+ update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9638
end
- attribute \src "libresoc.v:171339.7-171339.31"
- process $proc$libresoc.v:171339$9691
+ attribute \src "libresoc.v:171003.7-171003.31"
+ process $proc$libresoc.v:171003$9639
assign { } { }
- assign $0\sr_op__rc__rc$6[0:0]$9692 1'0
+ assign $0\sr_op__rc__rc$6[0:0]$9640 1'0
sync always
sync init
- update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9692
+ update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9640
end
- attribute \src "libresoc.v:171346.7-171346.35"
- process $proc$libresoc.v:171346$9693
+ attribute \src "libresoc.v:171010.7-171010.35"
+ process $proc$libresoc.v:171010$9641
assign { } { }
- assign $0\sr_op__write_cr0$10[0:0]$9694 1'0
+ assign $0\sr_op__write_cr0$10[0:0]$9642 1'0
sync always
sync init
- update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9694
+ update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9642
end
- attribute \src "libresoc.v:171355.13-171355.31"
- process $proc$libresoc.v:171355$9695
+ attribute \src "libresoc.v:171019.13-171019.31"
+ process $proc$libresoc.v:171019$9643
assign { } { }
- assign $0\xer_ca$23[1:0]$9696 2'00
+ assign $0\xer_ca$23[1:0]$9644 2'00
sync always
sync init
- update \xer_ca$23 $0\xer_ca$23[1:0]$9696
+ update \xer_ca$23 $0\xer_ca$23[1:0]$9644
end
- attribute \src "libresoc.v:171364.7-171364.28"
- process $proc$libresoc.v:171364$9697
+ attribute \src "libresoc.v:171028.7-171028.28"
+ process $proc$libresoc.v:171028$9645
assign { } { }
- assign $0\xer_ca_ok$24[0:0]$9698 1'0
+ assign $0\xer_ca_ok$24[0:0]$9646 1'0
sync always
sync init
- update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9698
+ update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9646
end
- attribute \src "libresoc.v:171378.3-171379.37"
- process $proc$libresoc.v:171378$9534
+ attribute \src "libresoc.v:171042.3-171043.37"
+ process $proc$libresoc.v:171042$9482
assign { } { }
- assign $0\xer_ca$23[1:0]$9535 \xer_ca$23$next
+ assign $0\xer_ca$23[1:0]$9483 \xer_ca$23$next
sync posedge \coresync_clk
- update \xer_ca$23 $0\xer_ca$23[1:0]$9535
+ update \xer_ca$23 $0\xer_ca$23[1:0]$9483
end
- attribute \src "libresoc.v:171380.3-171381.43"
- process $proc$libresoc.v:171380$9536
+ attribute \src "libresoc.v:171044.3-171045.43"
+ process $proc$libresoc.v:171044$9484
assign { } { }
- assign $0\xer_ca_ok$24[0:0]$9537 \xer_ca_ok$24$next
+ assign $0\xer_ca_ok$24[0:0]$9485 \xer_ca_ok$24$next
sync posedge \coresync_clk
- update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9537
+ update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9485
end
- attribute \src "libresoc.v:171382.3-171383.33"
- process $proc$libresoc.v:171382$9538
+ attribute \src "libresoc.v:171046.3-171047.33"
+ process $proc$libresoc.v:171046$9486
assign { } { }
- assign $0\cr_a$21[3:0]$9539 \cr_a$21$next
+ assign $0\cr_a$21[3:0]$9487 \cr_a$21$next
sync posedge \coresync_clk
- update \cr_a$21 $0\cr_a$21[3:0]$9539
+ update \cr_a$21 $0\cr_a$21[3:0]$9487
end
- attribute \src "libresoc.v:171384.3-171385.39"
- process $proc$libresoc.v:171384$9540
+ attribute \src "libresoc.v:171048.3-171049.39"
+ process $proc$libresoc.v:171048$9488
assign { } { }
- assign $0\cr_a_ok$22[0:0]$9541 \cr_a_ok$22$next
+ assign $0\cr_a_ok$22[0:0]$9489 \cr_a_ok$22$next
sync posedge \coresync_clk
- update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9541
+ update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9489
end
- attribute \src "libresoc.v:171386.3-171387.27"
- process $proc$libresoc.v:171386$9542
+ attribute \src "libresoc.v:171050.3-171051.27"
+ process $proc$libresoc.v:171050$9490
assign { } { }
- assign $0\o$19[63:0]$9543 \o$19$next
+ assign $0\o$19[63:0]$9491 \o$19$next
sync posedge \coresync_clk
- update \o$19 $0\o$19[63:0]$9543
+ update \o$19 $0\o$19[63:0]$9491
end
- attribute \src "libresoc.v:171388.3-171389.33"
- process $proc$libresoc.v:171388$9544
+ attribute \src "libresoc.v:171052.3-171053.33"
+ process $proc$libresoc.v:171052$9492
assign { } { }
- assign $0\o_ok$20[0:0]$9545 \o_ok$20$next
+ assign $0\o_ok$20[0:0]$9493 \o_ok$20$next
sync posedge \coresync_clk
- update \o_ok$20 $0\o_ok$20[0:0]$9545
+ update \o_ok$20 $0\o_ok$20[0:0]$9493
end
- attribute \src "libresoc.v:171390.3-171391.55"
- process $proc$libresoc.v:171390$9546
+ attribute \src "libresoc.v:171054.3-171055.55"
+ process $proc$libresoc.v:171054$9494
assign { } { }
- assign $0\sr_op__insn_type$2[6:0]$9547 \sr_op__insn_type$2$next
+ assign $0\sr_op__insn_type$2[6:0]$9495 \sr_op__insn_type$2$next
sync posedge \coresync_clk
- update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9547
+ update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9495
end
- attribute \src "libresoc.v:171392.3-171393.51"
- process $proc$libresoc.v:171392$9548
+ attribute \src "libresoc.v:171056.3-171057.51"
+ process $proc$libresoc.v:171056$9496
assign { } { }
- assign $0\sr_op__fn_unit$3[13:0]$9549 \sr_op__fn_unit$3$next
+ assign $0\sr_op__fn_unit$3[13:0]$9497 \sr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9549
+ update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9497
end
- attribute \src "libresoc.v:171394.3-171395.65"
- process $proc$libresoc.v:171394$9550
+ attribute \src "libresoc.v:171058.3-171059.65"
+ process $proc$libresoc.v:171058$9498
assign { } { }
- assign $0\sr_op__imm_data__data$4[63:0]$9551 \sr_op__imm_data__data$4$next
+ assign $0\sr_op__imm_data__data$4[63:0]$9499 \sr_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9551
+ update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9499
end
- attribute \src "libresoc.v:171396.3-171397.61"
- process $proc$libresoc.v:171396$9552
+ attribute \src "libresoc.v:171060.3-171061.61"
+ process $proc$libresoc.v:171060$9500
assign { } { }
- assign $0\sr_op__imm_data__ok$5[0:0]$9553 \sr_op__imm_data__ok$5$next
+ assign $0\sr_op__imm_data__ok$5[0:0]$9501 \sr_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9553
+ update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9501
end
- attribute \src "libresoc.v:171398.3-171399.49"
- process $proc$libresoc.v:171398$9554
+ attribute \src "libresoc.v:171062.3-171063.49"
+ process $proc$libresoc.v:171062$9502
assign { } { }
- assign $0\sr_op__rc__rc$6[0:0]$9555 \sr_op__rc__rc$6$next
+ assign $0\sr_op__rc__rc$6[0:0]$9503 \sr_op__rc__rc$6$next
sync posedge \coresync_clk
- update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9555
+ update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9503
end
- attribute \src "libresoc.v:171400.3-171401.49"
- process $proc$libresoc.v:171400$9556
+ attribute \src "libresoc.v:171064.3-171065.49"
+ process $proc$libresoc.v:171064$9504
assign { } { }
- assign $0\sr_op__rc__ok$7[0:0]$9557 \sr_op__rc__ok$7$next
+ assign $0\sr_op__rc__ok$7[0:0]$9505 \sr_op__rc__ok$7$next
sync posedge \coresync_clk
- update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9557
+ update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9505
end
- attribute \src "libresoc.v:171402.3-171403.49"
- process $proc$libresoc.v:171402$9558
+ attribute \src "libresoc.v:171066.3-171067.49"
+ process $proc$libresoc.v:171066$9506
assign { } { }
- assign $0\sr_op__oe__oe$8[0:0]$9559 \sr_op__oe__oe$8$next
+ assign $0\sr_op__oe__oe$8[0:0]$9507 \sr_op__oe__oe$8$next
sync posedge \coresync_clk
- update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9559
+ update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9507
end
- attribute \src "libresoc.v:171404.3-171405.49"
- process $proc$libresoc.v:171404$9560
+ attribute \src "libresoc.v:171068.3-171069.49"
+ process $proc$libresoc.v:171068$9508
assign { } { }
- assign $0\sr_op__oe__ok$9[0:0]$9561 \sr_op__oe__ok$9$next
+ assign $0\sr_op__oe__ok$9[0:0]$9509 \sr_op__oe__ok$9$next
sync posedge \coresync_clk
- update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9561
+ update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9509
end
- attribute \src "libresoc.v:171406.3-171407.57"
- process $proc$libresoc.v:171406$9562
+ attribute \src "libresoc.v:171070.3-171071.57"
+ process $proc$libresoc.v:171070$9510
assign { } { }
- assign $0\sr_op__write_cr0$10[0:0]$9563 \sr_op__write_cr0$10$next
+ assign $0\sr_op__write_cr0$10[0:0]$9511 \sr_op__write_cr0$10$next
sync posedge \coresync_clk
- update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9563
+ update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9511
end
- attribute \src "libresoc.v:171408.3-171409.57"
- process $proc$libresoc.v:171408$9564
+ attribute \src "libresoc.v:171072.3-171073.57"
+ process $proc$libresoc.v:171072$9512
assign { } { }
- assign $0\sr_op__invert_in$11[0:0]$9565 \sr_op__invert_in$11$next
+ assign $0\sr_op__invert_in$11[0:0]$9513 \sr_op__invert_in$11$next
sync posedge \coresync_clk
- update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9565
+ update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9513
end
- attribute \src "libresoc.v:171410.3-171411.61"
- process $proc$libresoc.v:171410$9566
+ attribute \src "libresoc.v:171074.3-171075.61"
+ process $proc$libresoc.v:171074$9514
assign { } { }
- assign $0\sr_op__input_carry$12[1:0]$9567 \sr_op__input_carry$12$next
+ assign $0\sr_op__input_carry$12[1:0]$9515 \sr_op__input_carry$12$next
sync posedge \coresync_clk
- update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9567
+ update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9515
end
- attribute \src "libresoc.v:171412.3-171413.63"
- process $proc$libresoc.v:171412$9568
+ attribute \src "libresoc.v:171076.3-171077.63"
+ process $proc$libresoc.v:171076$9516
assign { } { }
- assign $0\sr_op__output_carry$13[0:0]$9569 \sr_op__output_carry$13$next
+ assign $0\sr_op__output_carry$13[0:0]$9517 \sr_op__output_carry$13$next
sync posedge \coresync_clk
- update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9569
+ update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9517
end
- attribute \src "libresoc.v:171414.3-171415.55"
- process $proc$libresoc.v:171414$9570
+ attribute \src "libresoc.v:171078.3-171079.55"
+ process $proc$libresoc.v:171078$9518
assign { } { }
- assign $0\sr_op__input_cr$14[0:0]$9571 \sr_op__input_cr$14$next
+ assign $0\sr_op__input_cr$14[0:0]$9519 \sr_op__input_cr$14$next
sync posedge \coresync_clk
- update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9571
+ update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9519
end
- attribute \src "libresoc.v:171416.3-171417.57"
- process $proc$libresoc.v:171416$9572
+ attribute \src "libresoc.v:171080.3-171081.57"
+ process $proc$libresoc.v:171080$9520
assign { } { }
- assign $0\sr_op__output_cr$15[0:0]$9573 \sr_op__output_cr$15$next
+ assign $0\sr_op__output_cr$15[0:0]$9521 \sr_op__output_cr$15$next
sync posedge \coresync_clk
- update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9573
+ update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9521
end
- attribute \src "libresoc.v:171418.3-171419.55"
- process $proc$libresoc.v:171418$9574
+ attribute \src "libresoc.v:171082.3-171083.55"
+ process $proc$libresoc.v:171082$9522
assign { } { }
- assign $0\sr_op__is_32bit$16[0:0]$9575 \sr_op__is_32bit$16$next
+ assign $0\sr_op__is_32bit$16[0:0]$9523 \sr_op__is_32bit$16$next
sync posedge \coresync_clk
- update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9575
+ update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9523
end
- attribute \src "libresoc.v:171420.3-171421.57"
- process $proc$libresoc.v:171420$9576
+ attribute \src "libresoc.v:171084.3-171085.57"
+ process $proc$libresoc.v:171084$9524
assign { } { }
- assign $0\sr_op__is_signed$17[0:0]$9577 \sr_op__is_signed$17$next
+ assign $0\sr_op__is_signed$17[0:0]$9525 \sr_op__is_signed$17$next
sync posedge \coresync_clk
- update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9577
+ update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9525
end
- attribute \src "libresoc.v:171422.3-171423.47"
- process $proc$libresoc.v:171422$9578
+ attribute \src "libresoc.v:171086.3-171087.47"
+ process $proc$libresoc.v:171086$9526
assign { } { }
- assign $0\sr_op__insn$18[31:0]$9579 \sr_op__insn$18$next
+ assign $0\sr_op__insn$18[31:0]$9527 \sr_op__insn$18$next
sync posedge \coresync_clk
- update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9579
+ update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9527
end
- attribute \src "libresoc.v:171424.3-171425.33"
- process $proc$libresoc.v:171424$9580
+ attribute \src "libresoc.v:171088.3-171089.33"
+ process $proc$libresoc.v:171088$9528
assign { } { }
- assign $0\muxid$1[1:0]$9581 \muxid$1$next
+ assign $0\muxid$1[1:0]$9529 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9581
+ update \muxid$1 $0\muxid$1[1:0]$9529
end
- attribute \src "libresoc.v:171426.3-171427.29"
- process $proc$libresoc.v:171426$9582
+ attribute \src "libresoc.v:171090.3-171091.29"
+ process $proc$libresoc.v:171090$9530
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:171485.3-171502.6"
- process $proc$libresoc.v:171485$9583
+ attribute \src "libresoc.v:171149.3-171166.6"
+ process $proc$libresoc.v:171149$9531
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9584 $2\r_busy$next[0:0]$9586
- attribute \src "libresoc.v:171486.5-171486.29"
+ assign $0\r_busy$next[0:0]$9532 $2\r_busy$next[0:0]$9534
+ attribute \src "libresoc.v:171150.5-171150.29"
switch \initial
- attribute \src "libresoc.v:171486.9-171486.17"
+ attribute \src "libresoc.v:171150.9-171150.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9585 1'1
+ assign $1\r_busy$next[0:0]$9533 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9585 1'0
+ assign $1\r_busy$next[0:0]$9533 1'0
case
- assign $1\r_busy$next[0:0]$9585 \r_busy
+ assign $1\r_busy$next[0:0]$9533 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9586 1'0
+ assign $2\r_busy$next[0:0]$9534 1'0
case
- assign $2\r_busy$next[0:0]$9586 $1\r_busy$next[0:0]$9585
+ assign $2\r_busy$next[0:0]$9534 $1\r_busy$next[0:0]$9533
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9584
+ update \r_busy$next $0\r_busy$next[0:0]$9532
end
- attribute \src "libresoc.v:171503.3-171515.6"
- process $proc$libresoc.v:171503$9587
+ attribute \src "libresoc.v:171167.3-171179.6"
+ process $proc$libresoc.v:171167$9535
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9588 $1\muxid$1$next[1:0]$9589
- attribute \src "libresoc.v:171504.5-171504.29"
+ assign $0\muxid$1$next[1:0]$9536 $1\muxid$1$next[1:0]$9537
+ attribute \src "libresoc.v:171168.5-171168.29"
switch \initial
- attribute \src "libresoc.v:171504.9-171504.17"
+ attribute \src "libresoc.v:171168.9-171168.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9589 \muxid$53
+ assign $1\muxid$1$next[1:0]$9537 \muxid$53
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9589 \muxid$53
+ assign $1\muxid$1$next[1:0]$9537 \muxid$53
case
- assign $1\muxid$1$next[1:0]$9589 \muxid$1
+ assign $1\muxid$1$next[1:0]$9537 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9588
+ update \muxid$1$next $0\muxid$1$next[1:0]$9536
end
- attribute \src "libresoc.v:171516.3-171556.6"
- process $proc$libresoc.v:171516$9590
+ attribute \src "libresoc.v:171180.3-171220.6"
+ process $proc$libresoc.v:171180$9538
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr_op__fn_unit$3$next[13:0]$9591 $1\sr_op__fn_unit$3$next[13:0]$9608
+ assign $0\sr_op__fn_unit$3$next[13:0]$9539 $1\sr_op__fn_unit$3$next[13:0]$9556
assign { } { }
assign { } { }
- assign $0\sr_op__input_carry$12$next[1:0]$9594 $1\sr_op__input_carry$12$next[1:0]$9611
- assign $0\sr_op__input_cr$14$next[0:0]$9595 $1\sr_op__input_cr$14$next[0:0]$9612
- assign $0\sr_op__insn$18$next[31:0]$9596 $1\sr_op__insn$18$next[31:0]$9613
- assign $0\sr_op__insn_type$2$next[6:0]$9597 $1\sr_op__insn_type$2$next[6:0]$9614
- assign $0\sr_op__invert_in$11$next[0:0]$9598 $1\sr_op__invert_in$11$next[0:0]$9615
- assign $0\sr_op__is_32bit$16$next[0:0]$9599 $1\sr_op__is_32bit$16$next[0:0]$9616
- assign $0\sr_op__is_signed$17$next[0:0]$9600 $1\sr_op__is_signed$17$next[0:0]$9617
+ assign $0\sr_op__input_carry$12$next[1:0]$9542 $1\sr_op__input_carry$12$next[1:0]$9559
+ assign $0\sr_op__input_cr$14$next[0:0]$9543 $1\sr_op__input_cr$14$next[0:0]$9560
+ assign $0\sr_op__insn$18$next[31:0]$9544 $1\sr_op__insn$18$next[31:0]$9561
+ assign $0\sr_op__insn_type$2$next[6:0]$9545 $1\sr_op__insn_type$2$next[6:0]$9562
+ assign $0\sr_op__invert_in$11$next[0:0]$9546 $1\sr_op__invert_in$11$next[0:0]$9563
+ assign $0\sr_op__is_32bit$16$next[0:0]$9547 $1\sr_op__is_32bit$16$next[0:0]$9564
+ assign $0\sr_op__is_signed$17$next[0:0]$9548 $1\sr_op__is_signed$17$next[0:0]$9565
assign { } { }
assign { } { }
- assign $0\sr_op__output_carry$13$next[0:0]$9603 $1\sr_op__output_carry$13$next[0:0]$9620
- assign $0\sr_op__output_cr$15$next[0:0]$9604 $1\sr_op__output_cr$15$next[0:0]$9621
+ assign $0\sr_op__output_carry$13$next[0:0]$9551 $1\sr_op__output_carry$13$next[0:0]$9568
+ assign $0\sr_op__output_cr$15$next[0:0]$9552 $1\sr_op__output_cr$15$next[0:0]$9569
assign { } { }
assign { } { }
- assign $0\sr_op__write_cr0$10$next[0:0]$9607 $1\sr_op__write_cr0$10$next[0:0]$9624
- assign $0\sr_op__imm_data__data$4$next[63:0]$9592 $2\sr_op__imm_data__data$4$next[63:0]$9625
- assign $0\sr_op__imm_data__ok$5$next[0:0]$9593 $2\sr_op__imm_data__ok$5$next[0:0]$9626
- assign $0\sr_op__oe__oe$8$next[0:0]$9601 $2\sr_op__oe__oe$8$next[0:0]$9627
- assign $0\sr_op__oe__ok$9$next[0:0]$9602 $2\sr_op__oe__ok$9$next[0:0]$9628
- assign $0\sr_op__rc__ok$7$next[0:0]$9605 $2\sr_op__rc__ok$7$next[0:0]$9629
- assign $0\sr_op__rc__rc$6$next[0:0]$9606 $2\sr_op__rc__rc$6$next[0:0]$9630
- attribute \src "libresoc.v:171517.5-171517.29"
+ assign $0\sr_op__write_cr0$10$next[0:0]$9555 $1\sr_op__write_cr0$10$next[0:0]$9572
+ assign $0\sr_op__imm_data__data$4$next[63:0]$9540 $2\sr_op__imm_data__data$4$next[63:0]$9573
+ assign $0\sr_op__imm_data__ok$5$next[0:0]$9541 $2\sr_op__imm_data__ok$5$next[0:0]$9574
+ assign $0\sr_op__oe__oe$8$next[0:0]$9549 $2\sr_op__oe__oe$8$next[0:0]$9575
+ assign $0\sr_op__oe__ok$9$next[0:0]$9550 $2\sr_op__oe__ok$9$next[0:0]$9576
+ assign $0\sr_op__rc__ok$7$next[0:0]$9553 $2\sr_op__rc__ok$7$next[0:0]$9577
+ assign $0\sr_op__rc__rc$6$next[0:0]$9554 $2\sr_op__rc__rc$6$next[0:0]$9578
+ attribute \src "libresoc.v:171181.5-171181.29"
switch \initial
- attribute \src "libresoc.v:171517.9-171517.17"
+ attribute \src "libresoc.v:171181.9-171181.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$18$next[31:0]$9613 $1\sr_op__is_signed$17$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9616 $1\sr_op__output_cr$15$next[0:0]$9621 $1\sr_op__input_cr$14$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9620 $1\sr_op__input_carry$12$next[1:0]$9611 $1\sr_op__invert_in$11$next[0:0]$9615 $1\sr_op__write_cr0$10$next[0:0]$9624 $1\sr_op__oe__ok$9$next[0:0]$9619 $1\sr_op__oe__oe$8$next[0:0]$9618 $1\sr_op__rc__ok$7$next[0:0]$9622 $1\sr_op__rc__rc$6$next[0:0]$9623 $1\sr_op__imm_data__ok$5$next[0:0]$9610 $1\sr_op__imm_data__data$4$next[63:0]$9609 $1\sr_op__fn_unit$3$next[13:0]$9608 $1\sr_op__insn_type$2$next[6:0]$9614 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
+ assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$18$next[31:0]$9613 $1\sr_op__is_signed$17$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9616 $1\sr_op__output_cr$15$next[0:0]$9621 $1\sr_op__input_cr$14$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9620 $1\sr_op__input_carry$12$next[1:0]$9611 $1\sr_op__invert_in$11$next[0:0]$9615 $1\sr_op__write_cr0$10$next[0:0]$9624 $1\sr_op__oe__ok$9$next[0:0]$9619 $1\sr_op__oe__oe$8$next[0:0]$9618 $1\sr_op__rc__ok$7$next[0:0]$9622 $1\sr_op__rc__rc$6$next[0:0]$9623 $1\sr_op__imm_data__ok$5$next[0:0]$9610 $1\sr_op__imm_data__data$4$next[63:0]$9609 $1\sr_op__fn_unit$3$next[13:0]$9608 $1\sr_op__insn_type$2$next[6:0]$9614 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
+ assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
case
- assign $1\sr_op__fn_unit$3$next[13:0]$9608 \sr_op__fn_unit$3
- assign $1\sr_op__imm_data__data$4$next[63:0]$9609 \sr_op__imm_data__data$4
- assign $1\sr_op__imm_data__ok$5$next[0:0]$9610 \sr_op__imm_data__ok$5
- assign $1\sr_op__input_carry$12$next[1:0]$9611 \sr_op__input_carry$12
- assign $1\sr_op__input_cr$14$next[0:0]$9612 \sr_op__input_cr$14
- assign $1\sr_op__insn$18$next[31:0]$9613 \sr_op__insn$18
- assign $1\sr_op__insn_type$2$next[6:0]$9614 \sr_op__insn_type$2
- assign $1\sr_op__invert_in$11$next[0:0]$9615 \sr_op__invert_in$11
- assign $1\sr_op__is_32bit$16$next[0:0]$9616 \sr_op__is_32bit$16
- assign $1\sr_op__is_signed$17$next[0:0]$9617 \sr_op__is_signed$17
- assign $1\sr_op__oe__oe$8$next[0:0]$9618 \sr_op__oe__oe$8
- assign $1\sr_op__oe__ok$9$next[0:0]$9619 \sr_op__oe__ok$9
- assign $1\sr_op__output_carry$13$next[0:0]$9620 \sr_op__output_carry$13
- assign $1\sr_op__output_cr$15$next[0:0]$9621 \sr_op__output_cr$15
- assign $1\sr_op__rc__ok$7$next[0:0]$9622 \sr_op__rc__ok$7
- assign $1\sr_op__rc__rc$6$next[0:0]$9623 \sr_op__rc__rc$6
- assign $1\sr_op__write_cr0$10$next[0:0]$9624 \sr_op__write_cr0$10
+ assign $1\sr_op__fn_unit$3$next[13:0]$9556 \sr_op__fn_unit$3
+ assign $1\sr_op__imm_data__data$4$next[63:0]$9557 \sr_op__imm_data__data$4
+ assign $1\sr_op__imm_data__ok$5$next[0:0]$9558 \sr_op__imm_data__ok$5
+ assign $1\sr_op__input_carry$12$next[1:0]$9559 \sr_op__input_carry$12
+ assign $1\sr_op__input_cr$14$next[0:0]$9560 \sr_op__input_cr$14
+ assign $1\sr_op__insn$18$next[31:0]$9561 \sr_op__insn$18
+ assign $1\sr_op__insn_type$2$next[6:0]$9562 \sr_op__insn_type$2
+ assign $1\sr_op__invert_in$11$next[0:0]$9563 \sr_op__invert_in$11
+ assign $1\sr_op__is_32bit$16$next[0:0]$9564 \sr_op__is_32bit$16
+ assign $1\sr_op__is_signed$17$next[0:0]$9565 \sr_op__is_signed$17
+ assign $1\sr_op__oe__oe$8$next[0:0]$9566 \sr_op__oe__oe$8
+ assign $1\sr_op__oe__ok$9$next[0:0]$9567 \sr_op__oe__ok$9
+ assign $1\sr_op__output_carry$13$next[0:0]$9568 \sr_op__output_carry$13
+ assign $1\sr_op__output_cr$15$next[0:0]$9569 \sr_op__output_cr$15
+ assign $1\sr_op__rc__ok$7$next[0:0]$9570 \sr_op__rc__ok$7
+ assign $1\sr_op__rc__rc$6$next[0:0]$9571 \sr_op__rc__rc$6
+ assign $1\sr_op__write_cr0$10$next[0:0]$9572 \sr_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\sr_op__imm_data__data$4$next[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\sr_op__imm_data__ok$5$next[0:0]$9626 1'0
- assign $2\sr_op__rc__rc$6$next[0:0]$9630 1'0
- assign $2\sr_op__rc__ok$7$next[0:0]$9629 1'0
- assign $2\sr_op__oe__oe$8$next[0:0]$9627 1'0
- assign $2\sr_op__oe__ok$9$next[0:0]$9628 1'0
+ assign $2\sr_op__imm_data__data$4$next[63:0]$9573 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 1'0
+ assign $2\sr_op__rc__rc$6$next[0:0]$9578 1'0
+ assign $2\sr_op__rc__ok$7$next[0:0]$9577 1'0
+ assign $2\sr_op__oe__oe$8$next[0:0]$9575 1'0
+ assign $2\sr_op__oe__ok$9$next[0:0]$9576 1'0
case
- assign $2\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__imm_data__data$4$next[63:0]$9609
- assign $2\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__ok$5$next[0:0]$9610
- assign $2\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__oe__oe$8$next[0:0]$9618
- assign $2\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__ok$9$next[0:0]$9619
- assign $2\sr_op__rc__ok$7$next[0:0]$9629 $1\sr_op__rc__ok$7$next[0:0]$9622
- assign $2\sr_op__rc__rc$6$next[0:0]$9630 $1\sr_op__rc__rc$6$next[0:0]$9623
+ assign $2\sr_op__imm_data__data$4$next[63:0]$9573 $1\sr_op__imm_data__data$4$next[63:0]$9557
+ assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 $1\sr_op__imm_data__ok$5$next[0:0]$9558
+ assign $2\sr_op__oe__oe$8$next[0:0]$9575 $1\sr_op__oe__oe$8$next[0:0]$9566
+ assign $2\sr_op__oe__ok$9$next[0:0]$9576 $1\sr_op__oe__ok$9$next[0:0]$9567
+ assign $2\sr_op__rc__ok$7$next[0:0]$9577 $1\sr_op__rc__ok$7$next[0:0]$9570
+ assign $2\sr_op__rc__rc$6$next[0:0]$9578 $1\sr_op__rc__rc$6$next[0:0]$9571
end
sync always
- update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9591
- update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9592
- update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9593
- update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9594
- update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9595
- update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9596
- update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9597
- update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9598
- update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9599
- update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9600
- update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9601
- update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9602
- update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9603
- update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9604
- update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9605
- update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9606
- update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9607
+ update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9539
+ update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9540
+ update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9541
+ update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9542
+ update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9543
+ update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9544
+ update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9545
+ update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9546
+ update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9547
+ update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9548
+ update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9549
+ update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9550
+ update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9551
+ update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9552
+ update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9553
+ update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9554
+ update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9555
end
- attribute \src "libresoc.v:171557.3-171575.6"
- process $proc$libresoc.v:171557$9631
+ attribute \src "libresoc.v:171221.3-171239.6"
+ process $proc$libresoc.v:171221$9579
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$19$next[63:0]$9632 $1\o$19$next[63:0]$9634
+ assign $0\o$19$next[63:0]$9580 $1\o$19$next[63:0]$9582
assign { } { }
- assign $0\o_ok$20$next[0:0]$9633 $2\o_ok$20$next[0:0]$9636
- attribute \src "libresoc.v:171558.5-171558.29"
+ assign $0\o_ok$20$next[0:0]$9581 $2\o_ok$20$next[0:0]$9584
+ attribute \src "libresoc.v:171222.5-171222.29"
switch \initial
- attribute \src "libresoc.v:171558.9-171558.17"
+ attribute \src "libresoc.v:171222.9-171222.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$20$next[0:0]$9635 $1\o$19$next[63:0]$9634 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$20$next[0:0]$9635 $1\o$19$next[63:0]$9634 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 }
case
- assign $1\o$19$next[63:0]$9634 \o$19
- assign $1\o_ok$20$next[0:0]$9635 \o_ok$20
+ assign $1\o$19$next[63:0]$9582 \o$19
+ assign $1\o_ok$20$next[0:0]$9583 \o_ok$20
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$20$next[0:0]$9636 1'0
+ assign $2\o_ok$20$next[0:0]$9584 1'0
case
- assign $2\o_ok$20$next[0:0]$9636 $1\o_ok$20$next[0:0]$9635
+ assign $2\o_ok$20$next[0:0]$9584 $1\o_ok$20$next[0:0]$9583
end
sync always
- update \o$19$next $0\o$19$next[63:0]$9632
- update \o_ok$20$next $0\o_ok$20$next[0:0]$9633
+ update \o$19$next $0\o$19$next[63:0]$9580
+ update \o_ok$20$next $0\o_ok$20$next[0:0]$9581
end
- attribute \src "libresoc.v:171576.3-171594.6"
- process $proc$libresoc.v:171576$9637
+ attribute \src "libresoc.v:171240.3-171258.6"
+ process $proc$libresoc.v:171240$9585
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$21$next[3:0]$9638 $1\cr_a$21$next[3:0]$9640
+ assign $0\cr_a$21$next[3:0]$9586 $1\cr_a$21$next[3:0]$9588
assign { } { }
- assign $0\cr_a_ok$22$next[0:0]$9639 $2\cr_a_ok$22$next[0:0]$9642
- attribute \src "libresoc.v:171577.5-171577.29"
+ assign $0\cr_a_ok$22$next[0:0]$9587 $2\cr_a_ok$22$next[0:0]$9590
+ attribute \src "libresoc.v:171241.5-171241.29"
switch \initial
- attribute \src "libresoc.v:171577.9-171577.17"
+ attribute \src "libresoc.v:171241.9-171241.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$22$next[0:0]$9641 $1\cr_a$21$next[3:0]$9640 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$22$next[0:0]$9641 $1\cr_a$21$next[3:0]$9640 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 }
case
- assign $1\cr_a$21$next[3:0]$9640 \cr_a$21
- assign $1\cr_a_ok$22$next[0:0]$9641 \cr_a_ok$22
+ assign $1\cr_a$21$next[3:0]$9588 \cr_a$21
+ assign $1\cr_a_ok$22$next[0:0]$9589 \cr_a_ok$22
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$22$next[0:0]$9642 1'0
+ assign $2\cr_a_ok$22$next[0:0]$9590 1'0
case
- assign $2\cr_a_ok$22$next[0:0]$9642 $1\cr_a_ok$22$next[0:0]$9641
+ assign $2\cr_a_ok$22$next[0:0]$9590 $1\cr_a_ok$22$next[0:0]$9589
end
sync always
- update \cr_a$21$next $0\cr_a$21$next[3:0]$9638
- update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9639
+ update \cr_a$21$next $0\cr_a$21$next[3:0]$9586
+ update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9587
end
- attribute \src "libresoc.v:171595.3-171613.6"
- process $proc$libresoc.v:171595$9643
+ attribute \src "libresoc.v:171259.3-171277.6"
+ process $proc$libresoc.v:171259$9591
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$23$next[1:0]$9644 $1\xer_ca$23$next[1:0]$9646
+ assign $0\xer_ca$23$next[1:0]$9592 $1\xer_ca$23$next[1:0]$9594
assign { } { }
- assign $0\xer_ca_ok$24$next[0:0]$9645 $2\xer_ca_ok$24$next[0:0]$9648
- attribute \src "libresoc.v:171596.5-171596.29"
+ assign $0\xer_ca_ok$24$next[0:0]$9593 $2\xer_ca_ok$24$next[0:0]$9596
+ attribute \src "libresoc.v:171260.5-171260.29"
switch \initial
- attribute \src "libresoc.v:171596.9-171596.17"
+ attribute \src "libresoc.v:171260.9-171260.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$24$next[0:0]$9647 $1\xer_ca$23$next[1:0]$9646 } { \xer_ca_ok$76 \xer_ca$75 }
+ assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$24$next[0:0]$9647 $1\xer_ca$23$next[1:0]$9646 } { \xer_ca_ok$76 \xer_ca$75 }
+ assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 }
case
- assign $1\xer_ca$23$next[1:0]$9646 \xer_ca$23
- assign $1\xer_ca_ok$24$next[0:0]$9647 \xer_ca_ok$24
+ assign $1\xer_ca$23$next[1:0]$9594 \xer_ca$23
+ assign $1\xer_ca_ok$24$next[0:0]$9595 \xer_ca_ok$24
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$24$next[0:0]$9648 1'0
+ assign $2\xer_ca_ok$24$next[0:0]$9596 1'0
case
- assign $2\xer_ca_ok$24$next[0:0]$9648 $1\xer_ca_ok$24$next[0:0]$9647
+ assign $2\xer_ca_ok$24$next[0:0]$9596 $1\xer_ca_ok$24$next[0:0]$9595
end
sync always
- update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9644
- update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9645
+ update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9592
+ update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9593
end
- connect \$51 $and$libresoc.v:171377$9533_Y
+ connect \$51 $and$libresoc.v:171041$9481_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 }
connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \output_muxid \muxid
end
-attribute \src "libresoc.v:171634.1-172598.10"
+attribute \src "libresoc.v:171298.1-172262.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2"
attribute \generator "nMigen"
module \pipe2$35
- attribute \src "libresoc.v:172504.3-172522.6"
- wire width 64 $0\fast1$11$next[63:0]$9767
- attribute \src "libresoc.v:172359.3-172360.35"
- wire width 64 $0\fast1$11[63:0]$9708
- attribute \src "libresoc.v:171646.14-171646.47"
- wire width 64 $0\fast1$11[63:0]$9791
- attribute \src "libresoc.v:172504.3-172522.6"
- wire $0\fast1_ok$next[0:0]$9766
- attribute \src "libresoc.v:172361.3-172362.33"
+ attribute \src "libresoc.v:172168.3-172186.6"
+ wire width 64 $0\fast1$11$next[63:0]$9715
+ attribute \src "libresoc.v:172045.3-172046.35"
+ wire width 64 $0\fast1$11[63:0]$9677
+ attribute \src "libresoc.v:171310.14-171310.47"
+ wire width 64 $0\fast1$11[63:0]$9739
+ attribute \src "libresoc.v:172168.3-172186.6"
+ wire $0\fast1_ok$next[0:0]$9714
+ attribute \src "libresoc.v:172047.3-172048.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:172523.3-172541.6"
- wire width 64 $0\fast2$12$next[63:0]$9773
- attribute \src "libresoc.v:172355.3-172356.35"
- wire width 64 $0\fast2$12[63:0]$9705
- attribute \src "libresoc.v:171662.14-171662.47"
- wire width 64 $0\fast2$12[63:0]$9794
- attribute \src "libresoc.v:172523.3-172541.6"
- wire $0\fast2_ok$next[0:0]$9772
- attribute \src "libresoc.v:172357.3-172358.33"
+ attribute \src "libresoc.v:172187.3-172205.6"
+ wire width 64 $0\fast2$12$next[63:0]$9721
+ attribute \src "libresoc.v:172041.3-172042.35"
+ wire width 64 $0\fast2$12[63:0]$9674
+ attribute \src "libresoc.v:171326.14-171326.47"
+ wire width 64 $0\fast2$12[63:0]$9742
+ attribute \src "libresoc.v:172187.3-172205.6"
+ wire $0\fast2_ok$next[0:0]$9720
+ attribute \src "libresoc.v:172043.3-172044.33"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:171635.7-171635.20"
+ attribute \src "libresoc.v:171299.7-171299.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:172561.3-172579.6"
- wire width 64 $0\msr$next[63:0]$9784
- attribute \src "libresoc.v:172347.3-172348.23"
+ attribute \src "libresoc.v:172225.3-172243.6"
+ wire width 64 $0\msr$next[63:0]$9732
+ attribute \src "libresoc.v:172033.3-172034.23"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:172561.3-172579.6"
- wire $0\msr_ok$next[0:0]$9785
- attribute \src "libresoc.v:172349.3-172350.29"
+ attribute \src "libresoc.v:172225.3-172243.6"
+ wire $0\msr_ok$next[0:0]$9733
+ attribute \src "libresoc.v:172035.3-172036.29"
wire $0\msr_ok[0:0]
- attribute \src "libresoc.v:172451.3-172463.6"
- wire width 2 $0\muxid$1$next[1:0]$9738
- attribute \src "libresoc.v:172385.3-172386.33"
- wire width 2 $0\muxid$1[1:0]$9731
- attribute \src "libresoc.v:171940.13-171940.29"
- wire width 2 $0\muxid$1[1:0]$9799
- attribute \src "libresoc.v:172542.3-172560.6"
- wire width 64 $0\nia$next[63:0]$9778
- attribute \src "libresoc.v:172351.3-172352.23"
+ attribute \src "libresoc.v:172115.3-172127.6"
+ wire width 2 $0\muxid$1$next[1:0]$9686
+ attribute \src "libresoc.v:172029.3-172030.33"
+ wire width 2 $0\muxid$1[1:0]$9667
+ attribute \src "libresoc.v:171604.13-171604.29"
+ wire width 2 $0\muxid$1[1:0]$9747
+ attribute \src "libresoc.v:172206.3-172224.6"
+ wire width 64 $0\nia$next[63:0]$9726
+ attribute \src "libresoc.v:172037.3-172038.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:172542.3-172560.6"
- wire $0\nia_ok$next[0:0]$9779
- attribute \src "libresoc.v:172353.3-172354.29"
+ attribute \src "libresoc.v:172206.3-172224.6"
+ wire $0\nia_ok$next[0:0]$9727
+ attribute \src "libresoc.v:172039.3-172040.29"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:172485.3-172503.6"
- wire width 64 $0\o$next[63:0]$9760
- attribute \src "libresoc.v:172363.3-172364.19"
+ attribute \src "libresoc.v:172149.3-172167.6"
+ wire width 64 $0\o$next[63:0]$9708
+ attribute \src "libresoc.v:172049.3-172050.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:172485.3-172503.6"
- wire $0\o_ok$next[0:0]$9761
- attribute \src "libresoc.v:172365.3-172366.25"
+ attribute \src "libresoc.v:172149.3-172167.6"
+ wire $0\o_ok$next[0:0]$9709
+ attribute \src "libresoc.v:172051.3-172052.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:172433.3-172450.6"
- wire $0\r_busy$next[0:0]$9734
- attribute \src "libresoc.v:172387.3-172388.29"
+ attribute \src "libresoc.v:172097.3-172114.6"
+ wire $0\r_busy$next[0:0]$9682
+ attribute \src "libresoc.v:172031.3-172032.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 64 $0\trap_op__cia$6$next[63:0]$9741
- attribute \src "libresoc.v:172375.3-172376.47"
- wire width 64 $0\trap_op__cia$6[63:0]$9721
- attribute \src "libresoc.v:172001.14-172001.53"
- wire width 64 $0\trap_op__cia$6[63:0]$9806
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9742
- attribute \src "libresoc.v:172369.3-172370.55"
- wire width 14 $0\trap_op__fn_unit$3[13:0]$9715
- attribute \src "libresoc.v:172038.14-172038.45"
- wire width 14 $0\trap_op__fn_unit$3[13:0]$9808
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 32 $0\trap_op__insn$4$next[31:0]$9743
- attribute \src "libresoc.v:172371.3-172372.49"
- wire width 32 $0\trap_op__insn$4[31:0]$9717
- attribute \src "libresoc.v:172064.14-172064.39"
- wire width 32 $0\trap_op__insn$4[31:0]$9810
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 7 $0\trap_op__insn_type$2$next[6:0]$9744
- attribute \src "libresoc.v:172367.3-172368.59"
- wire width 7 $0\trap_op__insn_type$2[6:0]$9713
- attribute \src "libresoc.v:172221.13-172221.43"
- wire width 7 $0\trap_op__insn_type$2[6:0]$9812
- attribute \src "libresoc.v:172464.3-172484.6"
- wire $0\trap_op__is_32bit$7$next[0:0]$9745
- attribute \src "libresoc.v:172377.3-172378.57"
- wire $0\trap_op__is_32bit$7[0:0]$9723
- attribute \src "libresoc.v:172307.7-172307.35"
- wire $0\trap_op__is_32bit$7[0:0]$9814
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9746
- attribute \src "libresoc.v:172383.3-172384.59"
- wire width 8 $0\trap_op__ldst_exc$10[7:0]$9729
- attribute \src "libresoc.v:172314.13-172314.43"
- wire width 8 $0\trap_op__ldst_exc$10[7:0]$9816
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 64 $0\trap_op__msr$5$next[63:0]$9747
- attribute \src "libresoc.v:172373.3-172374.47"
- wire width 64 $0\trap_op__msr$5[63:0]$9719
- attribute \src "libresoc.v:172325.14-172325.53"
- wire width 64 $0\trap_op__msr$5[63:0]$9818
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9748
- attribute \src "libresoc.v:172381.3-172382.57"
- wire width 13 $0\trap_op__trapaddr$9[12:0]$9727
- attribute \src "libresoc.v:172334.14-172334.46"
- wire width 13 $0\trap_op__trapaddr$9[12:0]$9820
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 8 $0\trap_op__traptype$8$next[7:0]$9749
- attribute \src "libresoc.v:172379.3-172380.57"
- wire width 8 $0\trap_op__traptype$8[7:0]$9725
- attribute \src "libresoc.v:172343.13-172343.42"
- wire width 8 $0\trap_op__traptype$8[7:0]$9822
- attribute \src "libresoc.v:172504.3-172522.6"
- wire width 64 $1\fast1$11$next[63:0]$9769
- attribute \src "libresoc.v:172504.3-172522.6"
- wire $1\fast1_ok$next[0:0]$9768
- attribute \src "libresoc.v:171653.7-171653.22"
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 64 $0\trap_op__cia$6$next[63:0]$9689
+ attribute \src "libresoc.v:172019.3-172020.47"
+ wire width 64 $0\trap_op__cia$6[63:0]$9657
+ attribute \src "libresoc.v:171665.14-171665.53"
+ wire width 64 $0\trap_op__cia$6[63:0]$9754
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9690
+ attribute \src "libresoc.v:172013.3-172014.55"
+ wire width 14 $0\trap_op__fn_unit$3[13:0]$9651
+ attribute \src "libresoc.v:171702.14-171702.45"
+ wire width 14 $0\trap_op__fn_unit$3[13:0]$9756
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 32 $0\trap_op__insn$4$next[31:0]$9691
+ attribute \src "libresoc.v:172015.3-172016.49"
+ wire width 32 $0\trap_op__insn$4[31:0]$9653
+ attribute \src "libresoc.v:171728.14-171728.39"
+ wire width 32 $0\trap_op__insn$4[31:0]$9758
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 7 $0\trap_op__insn_type$2$next[6:0]$9692
+ attribute \src "libresoc.v:172011.3-172012.59"
+ wire width 7 $0\trap_op__insn_type$2[6:0]$9649
+ attribute \src "libresoc.v:171885.13-171885.43"
+ wire width 7 $0\trap_op__insn_type$2[6:0]$9760
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire $0\trap_op__is_32bit$7$next[0:0]$9693
+ attribute \src "libresoc.v:172021.3-172022.57"
+ wire $0\trap_op__is_32bit$7[0:0]$9659
+ attribute \src "libresoc.v:171971.7-171971.35"
+ wire $0\trap_op__is_32bit$7[0:0]$9762
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9694
+ attribute \src "libresoc.v:172027.3-172028.59"
+ wire width 8 $0\trap_op__ldst_exc$10[7:0]$9665
+ attribute \src "libresoc.v:171978.13-171978.43"
+ wire width 8 $0\trap_op__ldst_exc$10[7:0]$9764
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 64 $0\trap_op__msr$5$next[63:0]$9695
+ attribute \src "libresoc.v:172017.3-172018.47"
+ wire width 64 $0\trap_op__msr$5[63:0]$9655
+ attribute \src "libresoc.v:171989.14-171989.53"
+ wire width 64 $0\trap_op__msr$5[63:0]$9766
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9696
+ attribute \src "libresoc.v:172025.3-172026.57"
+ wire width 13 $0\trap_op__trapaddr$9[12:0]$9663
+ attribute \src "libresoc.v:171998.14-171998.46"
+ wire width 13 $0\trap_op__trapaddr$9[12:0]$9768
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 8 $0\trap_op__traptype$8$next[7:0]$9697
+ attribute \src "libresoc.v:172023.3-172024.57"
+ wire width 8 $0\trap_op__traptype$8[7:0]$9661
+ attribute \src "libresoc.v:172007.13-172007.42"
+ wire width 8 $0\trap_op__traptype$8[7:0]$9770
+ attribute \src "libresoc.v:172168.3-172186.6"
+ wire width 64 $1\fast1$11$next[63:0]$9717
+ attribute \src "libresoc.v:172168.3-172186.6"
+ wire $1\fast1_ok$next[0:0]$9716
+ attribute \src "libresoc.v:171317.7-171317.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:172523.3-172541.6"
- wire width 64 $1\fast2$12$next[63:0]$9775
- attribute \src "libresoc.v:172523.3-172541.6"
- wire $1\fast2_ok$next[0:0]$9774
- attribute \src "libresoc.v:171669.7-171669.22"
+ attribute \src "libresoc.v:172187.3-172205.6"
+ wire width 64 $1\fast2$12$next[63:0]$9723
+ attribute \src "libresoc.v:172187.3-172205.6"
+ wire $1\fast2_ok$next[0:0]$9722
+ attribute \src "libresoc.v:171333.7-171333.22"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:172561.3-172579.6"
- wire width 64 $1\msr$next[63:0]$9786
- attribute \src "libresoc.v:171924.14-171924.40"
+ attribute \src "libresoc.v:172225.3-172243.6"
+ wire width 64 $1\msr$next[63:0]$9734
+ attribute \src "libresoc.v:171588.14-171588.40"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:172561.3-172579.6"
- wire $1\msr_ok$next[0:0]$9787
- attribute \src "libresoc.v:171931.7-171931.20"
+ attribute \src "libresoc.v:172225.3-172243.6"
+ wire $1\msr_ok$next[0:0]$9735
+ attribute \src "libresoc.v:171595.7-171595.20"
wire $1\msr_ok[0:0]
- attribute \src "libresoc.v:172451.3-172463.6"
- wire width 2 $1\muxid$1$next[1:0]$9739
- attribute \src "libresoc.v:172542.3-172560.6"
- wire width 64 $1\nia$next[63:0]$9780
- attribute \src "libresoc.v:171953.14-171953.40"
+ attribute \src "libresoc.v:172115.3-172127.6"
+ wire width 2 $1\muxid$1$next[1:0]$9687
+ attribute \src "libresoc.v:172206.3-172224.6"
+ wire width 64 $1\nia$next[63:0]$9728
+ attribute \src "libresoc.v:171617.14-171617.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:172542.3-172560.6"
- wire $1\nia_ok$next[0:0]$9781
- attribute \src "libresoc.v:171960.7-171960.20"
+ attribute \src "libresoc.v:172206.3-172224.6"
+ wire $1\nia_ok$next[0:0]$9729
+ attribute \src "libresoc.v:171624.7-171624.20"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:172485.3-172503.6"
- wire width 64 $1\o$next[63:0]$9762
- attribute \src "libresoc.v:171967.14-171967.38"
+ attribute \src "libresoc.v:172149.3-172167.6"
+ wire width 64 $1\o$next[63:0]$9710
+ attribute \src "libresoc.v:171631.14-171631.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:172485.3-172503.6"
- wire $1\o_ok$next[0:0]$9763
- attribute \src "libresoc.v:171974.7-171974.18"
+ attribute \src "libresoc.v:172149.3-172167.6"
+ wire $1\o_ok$next[0:0]$9711
+ attribute \src "libresoc.v:171638.7-171638.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:172433.3-172450.6"
- wire $1\r_busy$next[0:0]$9735
- attribute \src "libresoc.v:171988.7-171988.20"
+ attribute \src "libresoc.v:172097.3-172114.6"
+ wire $1\r_busy$next[0:0]$9683
+ attribute \src "libresoc.v:171652.7-171652.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 64 $1\trap_op__cia$6$next[63:0]$9750
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9751
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 32 $1\trap_op__insn$4$next[31:0]$9752
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 7 $1\trap_op__insn_type$2$next[6:0]$9753
- attribute \src "libresoc.v:172464.3-172484.6"
- wire $1\trap_op__is_32bit$7$next[0:0]$9754
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9755
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 64 $1\trap_op__msr$5$next[63:0]$9756
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9757
- attribute \src "libresoc.v:172464.3-172484.6"
- wire width 8 $1\trap_op__traptype$8$next[7:0]$9758
- attribute \src "libresoc.v:172504.3-172522.6"
- wire $2\fast1_ok$next[0:0]$9770
- attribute \src "libresoc.v:172523.3-172541.6"
- wire $2\fast2_ok$next[0:0]$9776
- attribute \src "libresoc.v:172561.3-172579.6"
- wire $2\msr_ok$next[0:0]$9788
- attribute \src "libresoc.v:172542.3-172560.6"
- wire $2\nia_ok$next[0:0]$9782
- attribute \src "libresoc.v:172485.3-172503.6"
- wire $2\o_ok$next[0:0]$9764
- attribute \src "libresoc.v:172433.3-172450.6"
- wire $2\r_busy$next[0:0]$9736
- attribute \src "libresoc.v:172346.18-172346.118"
- wire $and$libresoc.v:172346$9699_Y
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 64 $1\trap_op__cia$6$next[63:0]$9698
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9699
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 32 $1\trap_op__insn$4$next[31:0]$9700
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 7 $1\trap_op__insn_type$2$next[6:0]$9701
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire $1\trap_op__is_32bit$7$next[0:0]$9702
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9703
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 64 $1\trap_op__msr$5$next[63:0]$9704
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9705
+ attribute \src "libresoc.v:172128.3-172148.6"
+ wire width 8 $1\trap_op__traptype$8$next[7:0]$9706
+ attribute \src "libresoc.v:172168.3-172186.6"
+ wire $2\fast1_ok$next[0:0]$9718
+ attribute \src "libresoc.v:172187.3-172205.6"
+ wire $2\fast2_ok$next[0:0]$9724
+ attribute \src "libresoc.v:172225.3-172243.6"
+ wire $2\msr_ok$next[0:0]$9736
+ attribute \src "libresoc.v:172206.3-172224.6"
+ wire $2\nia_ok$next[0:0]$9730
+ attribute \src "libresoc.v:172149.3-172167.6"
+ wire $2\o_ok$next[0:0]$9712
+ attribute \src "libresoc.v:172097.3-172114.6"
+ wire $2\r_busy$next[0:0]$9684
+ attribute \src "libresoc.v:172010.18-172010.118"
+ wire $and$libresoc.v:172010$9647_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 16 \fast1
wire \fast2_ok$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast2_ok$next
- attribute \src "libresoc.v:171635.7-171635.15"
+ attribute \src "libresoc.v:171299.7-171299.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 8 \trap_op__traptype$8$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:172346$9699
+ cell $and $and$libresoc.v:172010$9647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$25
connect \B \p_ready_o
- connect \Y $and$libresoc.v:172346$9699_Y
+ connect \Y $and$libresoc.v:172010$9647_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:172389.13-172424.4"
+ attribute \src "libresoc.v:172053.13-172088.4"
cell \main$38 \main
connect \fast1 \main_fast1
connect \fast1$11 \main_fast1$23
connect \trap_op__traptype$8 \main_trap_op__traptype$20
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:172425.10-172428.4"
+ attribute \src "libresoc.v:172089.10-172092.4"
cell \n$37 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:172429.10-172432.4"
+ attribute \src "libresoc.v:172093.10-172096.4"
cell \p$36 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:171635.7-171635.20"
- process $proc$libresoc.v:171635$9789
+ attribute \src "libresoc.v:171299.7-171299.20"
+ process $proc$libresoc.v:171299$9737
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:171646.14-171646.47"
- process $proc$libresoc.v:171646$9790
+ attribute \src "libresoc.v:171310.14-171310.47"
+ process $proc$libresoc.v:171310$9738
assign { } { }
- assign $0\fast1$11[63:0]$9791 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$11[63:0]$9739 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$11 $0\fast1$11[63:0]$9791
+ update \fast1$11 $0\fast1$11[63:0]$9739
end
- attribute \src "libresoc.v:171653.7-171653.22"
- process $proc$libresoc.v:171653$9792
+ attribute \src "libresoc.v:171317.7-171317.22"
+ process $proc$libresoc.v:171317$9740
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:171662.14-171662.47"
- process $proc$libresoc.v:171662$9793
+ attribute \src "libresoc.v:171326.14-171326.47"
+ process $proc$libresoc.v:171326$9741
assign { } { }
- assign $0\fast2$12[63:0]$9794 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast2$12[63:0]$9742 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast2$12 $0\fast2$12[63:0]$9794
+ update \fast2$12 $0\fast2$12[63:0]$9742
end
- attribute \src "libresoc.v:171669.7-171669.22"
- process $proc$libresoc.v:171669$9795
+ attribute \src "libresoc.v:171333.7-171333.22"
+ process $proc$libresoc.v:171333$9743
assign { } { }
assign $1\fast2_ok[0:0] 1'0
sync always
sync init
update \fast2_ok $1\fast2_ok[0:0]
end
- attribute \src "libresoc.v:171924.14-171924.40"
- process $proc$libresoc.v:171924$9796
+ attribute \src "libresoc.v:171588.14-171588.40"
+ process $proc$libresoc.v:171588$9744
assign { } { }
assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr $1\msr[63:0]
end
- attribute \src "libresoc.v:171931.7-171931.20"
- process $proc$libresoc.v:171931$9797
+ attribute \src "libresoc.v:171595.7-171595.20"
+ process $proc$libresoc.v:171595$9745
assign { } { }
assign $1\msr_ok[0:0] 1'0
sync always
sync init
update \msr_ok $1\msr_ok[0:0]
end
- attribute \src "libresoc.v:171940.13-171940.29"
- process $proc$libresoc.v:171940$9798
+ attribute \src "libresoc.v:171604.13-171604.29"
+ process $proc$libresoc.v:171604$9746
assign { } { }
- assign $0\muxid$1[1:0]$9799 2'00
+ assign $0\muxid$1[1:0]$9747 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9799
+ update \muxid$1 $0\muxid$1[1:0]$9747
end
- attribute \src "libresoc.v:171953.14-171953.40"
- process $proc$libresoc.v:171953$9800
+ attribute \src "libresoc.v:171617.14-171617.40"
+ process $proc$libresoc.v:171617$9748
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:171960.7-171960.20"
- process $proc$libresoc.v:171960$9801
+ attribute \src "libresoc.v:171624.7-171624.20"
+ process $proc$libresoc.v:171624$9749
assign { } { }
assign $1\nia_ok[0:0] 1'0
sync always
sync init
update \nia_ok $1\nia_ok[0:0]
end
- attribute \src "libresoc.v:171967.14-171967.38"
- process $proc$libresoc.v:171967$9802
+ attribute \src "libresoc.v:171631.14-171631.38"
+ process $proc$libresoc.v:171631$9750
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:171974.7-171974.18"
- process $proc$libresoc.v:171974$9803
+ attribute \src "libresoc.v:171638.7-171638.18"
+ process $proc$libresoc.v:171638$9751
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:171988.7-171988.20"
- process $proc$libresoc.v:171988$9804
+ attribute \src "libresoc.v:171652.7-171652.20"
+ process $proc$libresoc.v:171652$9752
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:172001.14-172001.53"
- process $proc$libresoc.v:172001$9805
+ attribute \src "libresoc.v:171665.14-171665.53"
+ process $proc$libresoc.v:171665$9753
assign { } { }
- assign $0\trap_op__cia$6[63:0]$9806 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\trap_op__cia$6[63:0]$9754 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9806
+ update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9754
end
- attribute \src "libresoc.v:172038.14-172038.45"
- process $proc$libresoc.v:172038$9807
+ attribute \src "libresoc.v:171702.14-171702.45"
+ process $proc$libresoc.v:171702$9755
assign { } { }
- assign $0\trap_op__fn_unit$3[13:0]$9808 14'00000000000000
+ assign $0\trap_op__fn_unit$3[13:0]$9756 14'00000000000000
sync always
sync init
- update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9808
+ update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9756
end
- attribute \src "libresoc.v:172064.14-172064.39"
- process $proc$libresoc.v:172064$9809
+ attribute \src "libresoc.v:171728.14-171728.39"
+ process $proc$libresoc.v:171728$9757
assign { } { }
- assign $0\trap_op__insn$4[31:0]$9810 0
+ assign $0\trap_op__insn$4[31:0]$9758 0
sync always
sync init
- update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9810
+ update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9758
end
- attribute \src "libresoc.v:172221.13-172221.43"
- process $proc$libresoc.v:172221$9811
+ attribute \src "libresoc.v:171885.13-171885.43"
+ process $proc$libresoc.v:171885$9759
assign { } { }
- assign $0\trap_op__insn_type$2[6:0]$9812 7'0000000
+ assign $0\trap_op__insn_type$2[6:0]$9760 7'0000000
sync always
sync init
- update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9812
+ update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9760
end
- attribute \src "libresoc.v:172307.7-172307.35"
- process $proc$libresoc.v:172307$9813
+ attribute \src "libresoc.v:171971.7-171971.35"
+ process $proc$libresoc.v:171971$9761
assign { } { }
- assign $0\trap_op__is_32bit$7[0:0]$9814 1'0
+ assign $0\trap_op__is_32bit$7[0:0]$9762 1'0
sync always
sync init
- update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9814
+ update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9762
end
- attribute \src "libresoc.v:172314.13-172314.43"
- process $proc$libresoc.v:172314$9815
+ attribute \src "libresoc.v:171978.13-171978.43"
+ process $proc$libresoc.v:171978$9763
assign { } { }
- assign $0\trap_op__ldst_exc$10[7:0]$9816 8'00000000
+ assign $0\trap_op__ldst_exc$10[7:0]$9764 8'00000000
sync always
sync init
- update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9816
+ update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9764
end
- attribute \src "libresoc.v:172325.14-172325.53"
- process $proc$libresoc.v:172325$9817
+ attribute \src "libresoc.v:171989.14-171989.53"
+ process $proc$libresoc.v:171989$9765
assign { } { }
- assign $0\trap_op__msr$5[63:0]$9818 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\trap_op__msr$5[63:0]$9766 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9818
+ update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9766
end
- attribute \src "libresoc.v:172334.14-172334.46"
- process $proc$libresoc.v:172334$9819
+ attribute \src "libresoc.v:171998.14-171998.46"
+ process $proc$libresoc.v:171998$9767
assign { } { }
- assign $0\trap_op__trapaddr$9[12:0]$9820 13'0000000000000
+ assign $0\trap_op__trapaddr$9[12:0]$9768 13'0000000000000
sync always
sync init
- update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9820
+ update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9768
end
- attribute \src "libresoc.v:172343.13-172343.42"
- process $proc$libresoc.v:172343$9821
+ attribute \src "libresoc.v:172007.13-172007.42"
+ process $proc$libresoc.v:172007$9769
assign { } { }
- assign $0\trap_op__traptype$8[7:0]$9822 8'00000000
+ assign $0\trap_op__traptype$8[7:0]$9770 8'00000000
sync always
sync init
- update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9822
+ update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9770
end
- attribute \src "libresoc.v:172347.3-172348.23"
- process $proc$libresoc.v:172347$9700
+ attribute \src "libresoc.v:172011.3-172012.59"
+ process $proc$libresoc.v:172011$9648
assign { } { }
- assign $0\msr[63:0] \msr$next
+ assign $0\trap_op__insn_type$2[6:0]$9649 \trap_op__insn_type$2$next
sync posedge \coresync_clk
- update \msr $0\msr[63:0]
+ update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9649
end
- attribute \src "libresoc.v:172349.3-172350.29"
- process $proc$libresoc.v:172349$9701
+ attribute \src "libresoc.v:172013.3-172014.55"
+ process $proc$libresoc.v:172013$9650
assign { } { }
- assign $0\msr_ok[0:0] \msr_ok$next
+ assign $0\trap_op__fn_unit$3[13:0]$9651 \trap_op__fn_unit$3$next
sync posedge \coresync_clk
- update \msr_ok $0\msr_ok[0:0]
+ update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9651
end
- attribute \src "libresoc.v:172351.3-172352.23"
- process $proc$libresoc.v:172351$9702
+ attribute \src "libresoc.v:172015.3-172016.49"
+ process $proc$libresoc.v:172015$9652
assign { } { }
- assign $0\nia[63:0] \nia$next
+ assign $0\trap_op__insn$4[31:0]$9653 \trap_op__insn$4$next
sync posedge \coresync_clk
- update \nia $0\nia[63:0]
+ update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9653
end
- attribute \src "libresoc.v:172353.3-172354.29"
- process $proc$libresoc.v:172353$9703
+ attribute \src "libresoc.v:172017.3-172018.47"
+ process $proc$libresoc.v:172017$9654
assign { } { }
- assign $0\nia_ok[0:0] \nia_ok$next
+ assign $0\trap_op__msr$5[63:0]$9655 \trap_op__msr$5$next
sync posedge \coresync_clk
- update \nia_ok $0\nia_ok[0:0]
+ update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9655
end
- attribute \src "libresoc.v:172355.3-172356.35"
- process $proc$libresoc.v:172355$9704
+ attribute \src "libresoc.v:172019.3-172020.47"
+ process $proc$libresoc.v:172019$9656
assign { } { }
- assign $0\fast2$12[63:0]$9705 \fast2$12$next
+ assign $0\trap_op__cia$6[63:0]$9657 \trap_op__cia$6$next
sync posedge \coresync_clk
- update \fast2$12 $0\fast2$12[63:0]$9705
+ update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9657
end
- attribute \src "libresoc.v:172357.3-172358.33"
- process $proc$libresoc.v:172357$9706
+ attribute \src "libresoc.v:172021.3-172022.57"
+ process $proc$libresoc.v:172021$9658
assign { } { }
- assign $0\fast2_ok[0:0] \fast2_ok$next
+ assign $0\trap_op__is_32bit$7[0:0]$9659 \trap_op__is_32bit$7$next
sync posedge \coresync_clk
- update \fast2_ok $0\fast2_ok[0:0]
+ update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9659
end
- attribute \src "libresoc.v:172359.3-172360.35"
- process $proc$libresoc.v:172359$9707
+ attribute \src "libresoc.v:172023.3-172024.57"
+ process $proc$libresoc.v:172023$9660
assign { } { }
- assign $0\fast1$11[63:0]$9708 \fast1$11$next
+ assign $0\trap_op__traptype$8[7:0]$9661 \trap_op__traptype$8$next
sync posedge \coresync_clk
- update \fast1$11 $0\fast1$11[63:0]$9708
+ update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9661
end
- attribute \src "libresoc.v:172361.3-172362.33"
- process $proc$libresoc.v:172361$9709
+ attribute \src "libresoc.v:172025.3-172026.57"
+ process $proc$libresoc.v:172025$9662
assign { } { }
- assign $0\fast1_ok[0:0] \fast1_ok$next
+ assign $0\trap_op__trapaddr$9[12:0]$9663 \trap_op__trapaddr$9$next
sync posedge \coresync_clk
- update \fast1_ok $0\fast1_ok[0:0]
+ update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9663
end
- attribute \src "libresoc.v:172363.3-172364.19"
- process $proc$libresoc.v:172363$9710
+ attribute \src "libresoc.v:172027.3-172028.59"
+ process $proc$libresoc.v:172027$9664
assign { } { }
- assign $0\o[63:0] \o$next
+ assign $0\trap_op__ldst_exc$10[7:0]$9665 \trap_op__ldst_exc$10$next
sync posedge \coresync_clk
- update \o $0\o[63:0]
+ update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9665
end
- attribute \src "libresoc.v:172365.3-172366.25"
- process $proc$libresoc.v:172365$9711
+ attribute \src "libresoc.v:172029.3-172030.33"
+ process $proc$libresoc.v:172029$9666
assign { } { }
- assign $0\o_ok[0:0] \o_ok$next
+ assign $0\muxid$1[1:0]$9667 \muxid$1$next
sync posedge \coresync_clk
- update \o_ok $0\o_ok[0:0]
+ update \muxid$1 $0\muxid$1[1:0]$9667
end
- attribute \src "libresoc.v:172367.3-172368.59"
- process $proc$libresoc.v:172367$9712
+ attribute \src "libresoc.v:172031.3-172032.29"
+ process $proc$libresoc.v:172031$9668
assign { } { }
- assign $0\trap_op__insn_type$2[6:0]$9713 \trap_op__insn_type$2$next
+ assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
- update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9713
+ update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:172369.3-172370.55"
- process $proc$libresoc.v:172369$9714
+ attribute \src "libresoc.v:172033.3-172034.23"
+ process $proc$libresoc.v:172033$9669
assign { } { }
- assign $0\trap_op__fn_unit$3[13:0]$9715 \trap_op__fn_unit$3$next
+ assign $0\msr[63:0] \msr$next
sync posedge \coresync_clk
- update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9715
+ update \msr $0\msr[63:0]
end
- attribute \src "libresoc.v:172371.3-172372.49"
- process $proc$libresoc.v:172371$9716
+ attribute \src "libresoc.v:172035.3-172036.29"
+ process $proc$libresoc.v:172035$9670
assign { } { }
- assign $0\trap_op__insn$4[31:0]$9717 \trap_op__insn$4$next
+ assign $0\msr_ok[0:0] \msr_ok$next
sync posedge \coresync_clk
- update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9717
+ update \msr_ok $0\msr_ok[0:0]
end
- attribute \src "libresoc.v:172373.3-172374.47"
- process $proc$libresoc.v:172373$9718
+ attribute \src "libresoc.v:172037.3-172038.23"
+ process $proc$libresoc.v:172037$9671
assign { } { }
- assign $0\trap_op__msr$5[63:0]$9719 \trap_op__msr$5$next
+ assign $0\nia[63:0] \nia$next
sync posedge \coresync_clk
- update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9719
+ update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:172375.3-172376.47"
- process $proc$libresoc.v:172375$9720
+ attribute \src "libresoc.v:172039.3-172040.29"
+ process $proc$libresoc.v:172039$9672
assign { } { }
- assign $0\trap_op__cia$6[63:0]$9721 \trap_op__cia$6$next
+ assign $0\nia_ok[0:0] \nia_ok$next
sync posedge \coresync_clk
- update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9721
+ update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:172377.3-172378.57"
- process $proc$libresoc.v:172377$9722
+ attribute \src "libresoc.v:172041.3-172042.35"
+ process $proc$libresoc.v:172041$9673
assign { } { }
- assign $0\trap_op__is_32bit$7[0:0]$9723 \trap_op__is_32bit$7$next
+ assign $0\fast2$12[63:0]$9674 \fast2$12$next
sync posedge \coresync_clk
- update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9723
+ update \fast2$12 $0\fast2$12[63:0]$9674
end
- attribute \src "libresoc.v:172379.3-172380.57"
- process $proc$libresoc.v:172379$9724
+ attribute \src "libresoc.v:172043.3-172044.33"
+ process $proc$libresoc.v:172043$9675
assign { } { }
- assign $0\trap_op__traptype$8[7:0]$9725 \trap_op__traptype$8$next
+ assign $0\fast2_ok[0:0] \fast2_ok$next
sync posedge \coresync_clk
- update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9725
+ update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:172381.3-172382.57"
- process $proc$libresoc.v:172381$9726
+ attribute \src "libresoc.v:172045.3-172046.35"
+ process $proc$libresoc.v:172045$9676
assign { } { }
- assign $0\trap_op__trapaddr$9[12:0]$9727 \trap_op__trapaddr$9$next
+ assign $0\fast1$11[63:0]$9677 \fast1$11$next
sync posedge \coresync_clk
- update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9727
+ update \fast1$11 $0\fast1$11[63:0]$9677
end
- attribute \src "libresoc.v:172383.3-172384.59"
- process $proc$libresoc.v:172383$9728
+ attribute \src "libresoc.v:172047.3-172048.33"
+ process $proc$libresoc.v:172047$9678
assign { } { }
- assign $0\trap_op__ldst_exc$10[7:0]$9729 \trap_op__ldst_exc$10$next
+ assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
- update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9729
+ update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:172385.3-172386.33"
- process $proc$libresoc.v:172385$9730
+ attribute \src "libresoc.v:172049.3-172050.19"
+ process $proc$libresoc.v:172049$9679
assign { } { }
- assign $0\muxid$1[1:0]$9731 \muxid$1$next
+ assign $0\o[63:0] \o$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9731
+ update \o $0\o[63:0]
end
- attribute \src "libresoc.v:172387.3-172388.29"
- process $proc$libresoc.v:172387$9732
+ attribute \src "libresoc.v:172051.3-172052.25"
+ process $proc$libresoc.v:172051$9680
assign { } { }
- assign $0\r_busy[0:0] \r_busy$next
+ assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
- update \r_busy $0\r_busy[0:0]
+ update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:172433.3-172450.6"
- process $proc$libresoc.v:172433$9733
+ attribute \src "libresoc.v:172097.3-172114.6"
+ process $proc$libresoc.v:172097$9681
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9734 $2\r_busy$next[0:0]$9736
- attribute \src "libresoc.v:172434.5-172434.29"
+ assign $0\r_busy$next[0:0]$9682 $2\r_busy$next[0:0]$9684
+ attribute \src "libresoc.v:172098.5-172098.29"
switch \initial
- attribute \src "libresoc.v:172434.9-172434.17"
+ attribute \src "libresoc.v:172098.9-172098.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9735 1'1
+ assign $1\r_busy$next[0:0]$9683 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9735 1'0
+ assign $1\r_busy$next[0:0]$9683 1'0
case
- assign $1\r_busy$next[0:0]$9735 \r_busy
+ assign $1\r_busy$next[0:0]$9683 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9736 1'0
+ assign $2\r_busy$next[0:0]$9684 1'0
case
- assign $2\r_busy$next[0:0]$9736 $1\r_busy$next[0:0]$9735
+ assign $2\r_busy$next[0:0]$9684 $1\r_busy$next[0:0]$9683
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9734
+ update \r_busy$next $0\r_busy$next[0:0]$9682
end
- attribute \src "libresoc.v:172451.3-172463.6"
- process $proc$libresoc.v:172451$9737
+ attribute \src "libresoc.v:172115.3-172127.6"
+ process $proc$libresoc.v:172115$9685
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9738 $1\muxid$1$next[1:0]$9739
- attribute \src "libresoc.v:172452.5-172452.29"
+ assign $0\muxid$1$next[1:0]$9686 $1\muxid$1$next[1:0]$9687
+ attribute \src "libresoc.v:172116.5-172116.29"
switch \initial
- attribute \src "libresoc.v:172452.9-172452.17"
+ attribute \src "libresoc.v:172116.9-172116.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9739 \muxid$28
+ assign $1\muxid$1$next[1:0]$9687 \muxid$28
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9739 \muxid$28
+ assign $1\muxid$1$next[1:0]$9687 \muxid$28
case
- assign $1\muxid$1$next[1:0]$9739 \muxid$1
+ assign $1\muxid$1$next[1:0]$9687 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9738
+ update \muxid$1$next $0\muxid$1$next[1:0]$9686
end
- attribute \src "libresoc.v:172464.3-172484.6"
- process $proc$libresoc.v:172464$9740
+ attribute \src "libresoc.v:172128.3-172148.6"
+ process $proc$libresoc.v:172128$9688
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trap_op__cia$6$next[63:0]$9741 $1\trap_op__cia$6$next[63:0]$9750
- assign $0\trap_op__fn_unit$3$next[13:0]$9742 $1\trap_op__fn_unit$3$next[13:0]$9751
- assign $0\trap_op__insn$4$next[31:0]$9743 $1\trap_op__insn$4$next[31:0]$9752
- assign $0\trap_op__insn_type$2$next[6:0]$9744 $1\trap_op__insn_type$2$next[6:0]$9753
- assign $0\trap_op__is_32bit$7$next[0:0]$9745 $1\trap_op__is_32bit$7$next[0:0]$9754
- assign $0\trap_op__ldst_exc$10$next[7:0]$9746 $1\trap_op__ldst_exc$10$next[7:0]$9755
- assign $0\trap_op__msr$5$next[63:0]$9747 $1\trap_op__msr$5$next[63:0]$9756
- assign $0\trap_op__trapaddr$9$next[12:0]$9748 $1\trap_op__trapaddr$9$next[12:0]$9757
- assign $0\trap_op__traptype$8$next[7:0]$9749 $1\trap_op__traptype$8$next[7:0]$9758
- attribute \src "libresoc.v:172465.5-172465.29"
+ assign $0\trap_op__cia$6$next[63:0]$9689 $1\trap_op__cia$6$next[63:0]$9698
+ assign $0\trap_op__fn_unit$3$next[13:0]$9690 $1\trap_op__fn_unit$3$next[13:0]$9699
+ assign $0\trap_op__insn$4$next[31:0]$9691 $1\trap_op__insn$4$next[31:0]$9700
+ assign $0\trap_op__insn_type$2$next[6:0]$9692 $1\trap_op__insn_type$2$next[6:0]$9701
+ assign $0\trap_op__is_32bit$7$next[0:0]$9693 $1\trap_op__is_32bit$7$next[0:0]$9702
+ assign $0\trap_op__ldst_exc$10$next[7:0]$9694 $1\trap_op__ldst_exc$10$next[7:0]$9703
+ assign $0\trap_op__msr$5$next[63:0]$9695 $1\trap_op__msr$5$next[63:0]$9704
+ assign $0\trap_op__trapaddr$9$next[12:0]$9696 $1\trap_op__trapaddr$9$next[12:0]$9705
+ assign $0\trap_op__traptype$8$next[7:0]$9697 $1\trap_op__traptype$8$next[7:0]$9706
+ attribute \src "libresoc.v:172129.5-172129.29"
switch \initial
- attribute \src "libresoc.v:172465.9-172465.17"
+ attribute \src "libresoc.v:172129.9-172129.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__cia$6$next[63:0]$9750 $1\trap_op__msr$5$next[63:0]$9756 $1\trap_op__insn$4$next[31:0]$9752 $1\trap_op__fn_unit$3$next[13:0]$9751 $1\trap_op__insn_type$2$next[6:0]$9753 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
+ assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__cia$6$next[63:0]$9750 $1\trap_op__msr$5$next[63:0]$9756 $1\trap_op__insn$4$next[31:0]$9752 $1\trap_op__fn_unit$3$next[13:0]$9751 $1\trap_op__insn_type$2$next[6:0]$9753 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
+ assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
case
- assign $1\trap_op__cia$6$next[63:0]$9750 \trap_op__cia$6
- assign $1\trap_op__fn_unit$3$next[13:0]$9751 \trap_op__fn_unit$3
- assign $1\trap_op__insn$4$next[31:0]$9752 \trap_op__insn$4
- assign $1\trap_op__insn_type$2$next[6:0]$9753 \trap_op__insn_type$2
- assign $1\trap_op__is_32bit$7$next[0:0]$9754 \trap_op__is_32bit$7
- assign $1\trap_op__ldst_exc$10$next[7:0]$9755 \trap_op__ldst_exc$10
- assign $1\trap_op__msr$5$next[63:0]$9756 \trap_op__msr$5
- assign $1\trap_op__trapaddr$9$next[12:0]$9757 \trap_op__trapaddr$9
- assign $1\trap_op__traptype$8$next[7:0]$9758 \trap_op__traptype$8
+ assign $1\trap_op__cia$6$next[63:0]$9698 \trap_op__cia$6
+ assign $1\trap_op__fn_unit$3$next[13:0]$9699 \trap_op__fn_unit$3
+ assign $1\trap_op__insn$4$next[31:0]$9700 \trap_op__insn$4
+ assign $1\trap_op__insn_type$2$next[6:0]$9701 \trap_op__insn_type$2
+ assign $1\trap_op__is_32bit$7$next[0:0]$9702 \trap_op__is_32bit$7
+ assign $1\trap_op__ldst_exc$10$next[7:0]$9703 \trap_op__ldst_exc$10
+ assign $1\trap_op__msr$5$next[63:0]$9704 \trap_op__msr$5
+ assign $1\trap_op__trapaddr$9$next[12:0]$9705 \trap_op__trapaddr$9
+ assign $1\trap_op__traptype$8$next[7:0]$9706 \trap_op__traptype$8
end
sync always
- update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9741
- update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9742
- update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9743
- update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9744
- update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9745
- update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9746
- update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9747
- update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9748
- update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9749
+ update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9689
+ update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9690
+ update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9691
+ update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9692
+ update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9693
+ update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9694
+ update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9695
+ update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9696
+ update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9697
end
- attribute \src "libresoc.v:172485.3-172503.6"
- process $proc$libresoc.v:172485$9759
+ attribute \src "libresoc.v:172149.3-172167.6"
+ process $proc$libresoc.v:172149$9707
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9760 $1\o$next[63:0]$9762
+ assign $0\o$next[63:0]$9708 $1\o$next[63:0]$9710
assign { } { }
- assign $0\o_ok$next[0:0]$9761 $2\o_ok$next[0:0]$9764
- attribute \src "libresoc.v:172486.5-172486.29"
+ assign $0\o_ok$next[0:0]$9709 $2\o_ok$next[0:0]$9712
+ attribute \src "libresoc.v:172150.5-172150.29"
switch \initial
- attribute \src "libresoc.v:172486.9-172486.17"
+ attribute \src "libresoc.v:172150.9-172150.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9763 $1\o$next[63:0]$9762 } { \o_ok$39 \o$38 }
+ assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9763 $1\o$next[63:0]$9762 } { \o_ok$39 \o$38 }
+ assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 }
case
- assign $1\o$next[63:0]$9762 \o
- assign $1\o_ok$next[0:0]$9763 \o_ok
+ assign $1\o$next[63:0]$9710 \o
+ assign $1\o_ok$next[0:0]$9711 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9764 1'0
+ assign $2\o_ok$next[0:0]$9712 1'0
case
- assign $2\o_ok$next[0:0]$9764 $1\o_ok$next[0:0]$9763
+ assign $2\o_ok$next[0:0]$9712 $1\o_ok$next[0:0]$9711
end
sync always
- update \o$next $0\o$next[63:0]$9760
- update \o_ok$next $0\o_ok$next[0:0]$9761
+ update \o$next $0\o$next[63:0]$9708
+ update \o_ok$next $0\o_ok$next[0:0]$9709
end
- attribute \src "libresoc.v:172504.3-172522.6"
- process $proc$libresoc.v:172504$9765
+ attribute \src "libresoc.v:172168.3-172186.6"
+ process $proc$libresoc.v:172168$9713
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$11$next[63:0]$9767 $1\fast1$11$next[63:0]$9769
- assign $0\fast1_ok$next[0:0]$9766 $2\fast1_ok$next[0:0]$9770
- attribute \src "libresoc.v:172505.5-172505.29"
+ assign $0\fast1$11$next[63:0]$9715 $1\fast1$11$next[63:0]$9717
+ assign $0\fast1_ok$next[0:0]$9714 $2\fast1_ok$next[0:0]$9718
+ attribute \src "libresoc.v:172169.5-172169.29"
switch \initial
- attribute \src "libresoc.v:172505.9-172505.17"
+ attribute \src "libresoc.v:172169.9-172169.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$9768 $1\fast1$11$next[63:0]$9769 } { \fast1_ok$41 \fast1$40 }
+ assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$9768 $1\fast1$11$next[63:0]$9769 } { \fast1_ok$41 \fast1$40 }
+ assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 }
case
- assign $1\fast1_ok$next[0:0]$9768 \fast1_ok
- assign $1\fast1$11$next[63:0]$9769 \fast1$11
+ assign $1\fast1_ok$next[0:0]$9716 \fast1_ok
+ assign $1\fast1$11$next[63:0]$9717 \fast1$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$9770 1'0
+ assign $2\fast1_ok$next[0:0]$9718 1'0
case
- assign $2\fast1_ok$next[0:0]$9770 $1\fast1_ok$next[0:0]$9768
+ assign $2\fast1_ok$next[0:0]$9718 $1\fast1_ok$next[0:0]$9716
end
sync always
- update \fast1_ok$next $0\fast1_ok$next[0:0]$9766
- update \fast1$11$next $0\fast1$11$next[63:0]$9767
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$9714
+ update \fast1$11$next $0\fast1$11$next[63:0]$9715
end
- attribute \src "libresoc.v:172523.3-172541.6"
- process $proc$libresoc.v:172523$9771
+ attribute \src "libresoc.v:172187.3-172205.6"
+ process $proc$libresoc.v:172187$9719
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast2$12$next[63:0]$9773 $1\fast2$12$next[63:0]$9775
- assign $0\fast2_ok$next[0:0]$9772 $2\fast2_ok$next[0:0]$9776
- attribute \src "libresoc.v:172524.5-172524.29"
+ assign $0\fast2$12$next[63:0]$9721 $1\fast2$12$next[63:0]$9723
+ assign $0\fast2_ok$next[0:0]$9720 $2\fast2_ok$next[0:0]$9724
+ attribute \src "libresoc.v:172188.5-172188.29"
switch \initial
- attribute \src "libresoc.v:172524.9-172524.17"
+ attribute \src "libresoc.v:172188.9-172188.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$9774 $1\fast2$12$next[63:0]$9775 } { \fast2_ok$43 \fast2$42 }
+ assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$9774 $1\fast2$12$next[63:0]$9775 } { \fast2_ok$43 \fast2$42 }
+ assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 }
case
- assign $1\fast2_ok$next[0:0]$9774 \fast2_ok
- assign $1\fast2$12$next[63:0]$9775 \fast2$12
+ assign $1\fast2_ok$next[0:0]$9722 \fast2_ok
+ assign $1\fast2$12$next[63:0]$9723 \fast2$12
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast2_ok$next[0:0]$9776 1'0
+ assign $2\fast2_ok$next[0:0]$9724 1'0
case
- assign $2\fast2_ok$next[0:0]$9776 $1\fast2_ok$next[0:0]$9774
+ assign $2\fast2_ok$next[0:0]$9724 $1\fast2_ok$next[0:0]$9722
end
sync always
- update \fast2_ok$next $0\fast2_ok$next[0:0]$9772
- update \fast2$12$next $0\fast2$12$next[63:0]$9773
+ update \fast2_ok$next $0\fast2_ok$next[0:0]$9720
+ update \fast2$12$next $0\fast2$12$next[63:0]$9721
end
- attribute \src "libresoc.v:172542.3-172560.6"
- process $proc$libresoc.v:172542$9777
+ attribute \src "libresoc.v:172206.3-172224.6"
+ process $proc$libresoc.v:172206$9725
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$9778 $1\nia$next[63:0]$9780
+ assign $0\nia$next[63:0]$9726 $1\nia$next[63:0]$9728
assign { } { }
- assign $0\nia_ok$next[0:0]$9779 $2\nia_ok$next[0:0]$9782
- attribute \src "libresoc.v:172543.5-172543.29"
+ assign $0\nia_ok$next[0:0]$9727 $2\nia_ok$next[0:0]$9730
+ attribute \src "libresoc.v:172207.5-172207.29"
switch \initial
- attribute \src "libresoc.v:172543.9-172543.17"
+ attribute \src "libresoc.v:172207.9-172207.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$9781 $1\nia$next[63:0]$9780 } { \nia_ok$45 \nia$44 }
+ assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$9781 $1\nia$next[63:0]$9780 } { \nia_ok$45 \nia$44 }
+ assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 }
case
- assign $1\nia$next[63:0]$9780 \nia
- assign $1\nia_ok$next[0:0]$9781 \nia_ok
+ assign $1\nia$next[63:0]$9728 \nia
+ assign $1\nia_ok$next[0:0]$9729 \nia_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\nia_ok$next[0:0]$9782 1'0
+ assign $2\nia_ok$next[0:0]$9730 1'0
case
- assign $2\nia_ok$next[0:0]$9782 $1\nia_ok$next[0:0]$9781
+ assign $2\nia_ok$next[0:0]$9730 $1\nia_ok$next[0:0]$9729
end
sync always
- update \nia$next $0\nia$next[63:0]$9778
- update \nia_ok$next $0\nia_ok$next[0:0]$9779
+ update \nia$next $0\nia$next[63:0]$9726
+ update \nia_ok$next $0\nia_ok$next[0:0]$9727
end
- attribute \src "libresoc.v:172561.3-172579.6"
- process $proc$libresoc.v:172561$9783
+ attribute \src "libresoc.v:172225.3-172243.6"
+ process $proc$libresoc.v:172225$9731
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr$next[63:0]$9784 $1\msr$next[63:0]$9786
+ assign $0\msr$next[63:0]$9732 $1\msr$next[63:0]$9734
assign { } { }
- assign $0\msr_ok$next[0:0]$9785 $2\msr_ok$next[0:0]$9788
- attribute \src "libresoc.v:172562.5-172562.29"
+ assign $0\msr_ok$next[0:0]$9733 $2\msr_ok$next[0:0]$9736
+ attribute \src "libresoc.v:172226.5-172226.29"
switch \initial
- attribute \src "libresoc.v:172562.9-172562.17"
+ attribute \src "libresoc.v:172226.9-172226.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\msr_ok$next[0:0]$9787 $1\msr$next[63:0]$9786 } { \msr_ok$47 \msr$46 }
+ assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\msr_ok$next[0:0]$9787 $1\msr$next[63:0]$9786 } { \msr_ok$47 \msr$46 }
+ assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 }
case
- assign $1\msr$next[63:0]$9786 \msr
- assign $1\msr_ok$next[0:0]$9787 \msr_ok
+ assign $1\msr$next[63:0]$9734 \msr
+ assign $1\msr_ok$next[0:0]$9735 \msr_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_ok$next[0:0]$9788 1'0
+ assign $2\msr_ok$next[0:0]$9736 1'0
case
- assign $2\msr_ok$next[0:0]$9788 $1\msr_ok$next[0:0]$9787
+ assign $2\msr_ok$next[0:0]$9736 $1\msr_ok$next[0:0]$9735
end
sync always
- update \msr$next $0\msr$next[63:0]$9784
- update \msr_ok$next $0\msr_ok$next[0:0]$9785
+ update \msr$next $0\msr$next[63:0]$9732
+ update \msr_ok$next $0\msr_ok$next[0:0]$9733
end
- connect \$26 $and$libresoc.v:172346$9699_Y
+ connect \$26 $and$libresoc.v:172010$9647_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr }
connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:172602.1-174105.10"
+attribute \src "libresoc.v:172266.1-173769.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end"
attribute \generator "nMigen"
module \pipe_end
- attribute \src "libresoc.v:173943.3-173961.6"
- wire width 4 $0\cr_a$next[3:0]$9879
- attribute \src "libresoc.v:173762.3-173763.25"
+ attribute \src "libresoc.v:173607.3-173625.6"
+ wire width 4 $0\cr_a$next[3:0]$9827
+ attribute \src "libresoc.v:173426.3-173427.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:173943.3-173961.6"
- wire $0\cr_a_ok$next[0:0]$9880
- attribute \src "libresoc.v:173764.3-173765.31"
+ attribute \src "libresoc.v:173607.3-173625.6"
+ wire $0\cr_a_ok$next[0:0]$9828
+ attribute \src "libresoc.v:173428.3-173429.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:172603.7-172603.20"
+ attribute \src "libresoc.v:172267.7-172267.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 4 $0\logical_op__data_len$18$next[3:0]$9904
- attribute \src "libresoc.v:173802.3-173803.65"
- wire width 4 $0\logical_op__data_len$18[3:0]$9866
- attribute \src "libresoc.v:172644.13-172644.45"
- wire width 4 $0\logical_op__data_len$18[3:0]$9950
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9905
- attribute \src "libresoc.v:173772.3-173773.61"
- wire width 14 $0\logical_op__fn_unit$3[13:0]$9836
- attribute \src "libresoc.v:172683.14-172683.48"
- wire width 14 $0\logical_op__fn_unit$3[13:0]$9952
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9906
- attribute \src "libresoc.v:173774.3-173775.75"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$9838
- attribute \src "libresoc.v:172707.14-172707.67"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$9954
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__imm_data__ok$5$next[0:0]$9907
- attribute \src "libresoc.v:173776.3-173777.71"
- wire $0\logical_op__imm_data__ok$5[0:0]$9840
- attribute \src "libresoc.v:172716.7-172716.42"
- wire $0\logical_op__imm_data__ok$5[0:0]$9956
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 2 $0\logical_op__input_carry$12$next[1:0]$9908
- attribute \src "libresoc.v:173790.3-173791.71"
- wire width 2 $0\logical_op__input_carry$12[1:0]$9854
- attribute \src "libresoc.v:172733.13-172733.48"
- wire width 2 $0\logical_op__input_carry$12[1:0]$9958
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 32 $0\logical_op__insn$19$next[31:0]$9909
- attribute \src "libresoc.v:173804.3-173805.57"
- wire width 32 $0\logical_op__insn$19[31:0]$9868
- attribute \src "libresoc.v:172746.14-172746.43"
- wire width 32 $0\logical_op__insn$19[31:0]$9960
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 7 $0\logical_op__insn_type$2$next[6:0]$9910
- attribute \src "libresoc.v:173770.3-173771.65"
- wire width 7 $0\logical_op__insn_type$2[6:0]$9834
- attribute \src "libresoc.v:172905.13-172905.46"
- wire width 7 $0\logical_op__insn_type$2[6:0]$9962
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__invert_in$10$next[0:0]$9911
- attribute \src "libresoc.v:173786.3-173787.67"
- wire $0\logical_op__invert_in$10[0:0]$9850
- attribute \src "libresoc.v:172989.7-172989.40"
- wire $0\logical_op__invert_in$10[0:0]$9964
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__invert_out$13$next[0:0]$9912
- attribute \src "libresoc.v:173792.3-173793.69"
- wire $0\logical_op__invert_out$13[0:0]$9856
- attribute \src "libresoc.v:172998.7-172998.41"
- wire $0\logical_op__invert_out$13[0:0]$9966
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__is_32bit$16$next[0:0]$9913
- attribute \src "libresoc.v:173798.3-173799.65"
- wire $0\logical_op__is_32bit$16[0:0]$9862
- attribute \src "libresoc.v:173007.7-173007.39"
- wire $0\logical_op__is_32bit$16[0:0]$9968
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__is_signed$17$next[0:0]$9914
- attribute \src "libresoc.v:173800.3-173801.67"
- wire $0\logical_op__is_signed$17[0:0]$9864
- attribute \src "libresoc.v:173016.7-173016.40"
- wire $0\logical_op__is_signed$17[0:0]$9970
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__oe__oe$8$next[0:0]$9915
- attribute \src "libresoc.v:173782.3-173783.59"
- wire $0\logical_op__oe__oe$8[0:0]$9846
- attribute \src "libresoc.v:173025.7-173025.36"
- wire $0\logical_op__oe__oe$8[0:0]$9972
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__oe__ok$9$next[0:0]$9916
- attribute \src "libresoc.v:173784.3-173785.59"
- wire $0\logical_op__oe__ok$9[0:0]$9848
- attribute \src "libresoc.v:173036.7-173036.36"
- wire $0\logical_op__oe__ok$9[0:0]$9974
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__output_carry$15$next[0:0]$9917
- attribute \src "libresoc.v:173796.3-173797.73"
- wire $0\logical_op__output_carry$15[0:0]$9860
- attribute \src "libresoc.v:173043.7-173043.43"
- wire $0\logical_op__output_carry$15[0:0]$9976
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__rc__ok$7$next[0:0]$9918
- attribute \src "libresoc.v:173780.3-173781.59"
- wire $0\logical_op__rc__ok$7[0:0]$9844
- attribute \src "libresoc.v:173052.7-173052.36"
- wire $0\logical_op__rc__ok$7[0:0]$9978
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__rc__rc$6$next[0:0]$9919
- attribute \src "libresoc.v:173778.3-173779.59"
- wire $0\logical_op__rc__rc$6[0:0]$9842
- attribute \src "libresoc.v:173061.7-173061.36"
- wire $0\logical_op__rc__rc$6[0:0]$9980
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__write_cr0$14$next[0:0]$9920
- attribute \src "libresoc.v:173794.3-173795.67"
- wire $0\logical_op__write_cr0$14[0:0]$9858
- attribute \src "libresoc.v:173070.7-173070.40"
- wire $0\logical_op__write_cr0$14[0:0]$9982
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $0\logical_op__zero_a$11$next[0:0]$9921
- attribute \src "libresoc.v:173788.3-173789.61"
- wire $0\logical_op__zero_a$11[0:0]$9852
- attribute \src "libresoc.v:173079.7-173079.37"
- wire $0\logical_op__zero_a$11[0:0]$9984
- attribute \src "libresoc.v:174018.3-174030.6"
- wire width 2 $0\muxid$1$next[1:0]$9901
- attribute \src "libresoc.v:173806.3-173807.33"
- wire width 2 $0\muxid$1[1:0]$9870
- attribute \src "libresoc.v:173088.13-173088.29"
- wire width 2 $0\muxid$1[1:0]$9986
- attribute \src "libresoc.v:173924.3-173942.6"
- wire width 64 $0\o$next[63:0]$9873
- attribute \src "libresoc.v:173766.3-173767.19"
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 4 $0\logical_op__data_len$18$next[3:0]$9852
+ attribute \src "libresoc.v:173466.3-173467.65"
+ wire width 4 $0\logical_op__data_len$18[3:0]$9814
+ attribute \src "libresoc.v:172308.13-172308.45"
+ wire width 4 $0\logical_op__data_len$18[3:0]$9898
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9853
+ attribute \src "libresoc.v:173436.3-173437.61"
+ wire width 14 $0\logical_op__fn_unit$3[13:0]$9784
+ attribute \src "libresoc.v:172347.14-172347.48"
+ wire width 14 $0\logical_op__fn_unit$3[13:0]$9900
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9854
+ attribute \src "libresoc.v:173438.3-173439.75"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$9786
+ attribute \src "libresoc.v:172371.14-172371.67"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$9902
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__imm_data__ok$5$next[0:0]$9855
+ attribute \src "libresoc.v:173440.3-173441.71"
+ wire $0\logical_op__imm_data__ok$5[0:0]$9788
+ attribute \src "libresoc.v:172380.7-172380.42"
+ wire $0\logical_op__imm_data__ok$5[0:0]$9904
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 2 $0\logical_op__input_carry$12$next[1:0]$9856
+ attribute \src "libresoc.v:173454.3-173455.71"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$9802
+ attribute \src "libresoc.v:172397.13-172397.48"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$9906
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 32 $0\logical_op__insn$19$next[31:0]$9857
+ attribute \src "libresoc.v:173468.3-173469.57"
+ wire width 32 $0\logical_op__insn$19[31:0]$9816
+ attribute \src "libresoc.v:172410.14-172410.43"
+ wire width 32 $0\logical_op__insn$19[31:0]$9908
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 7 $0\logical_op__insn_type$2$next[6:0]$9858
+ attribute \src "libresoc.v:173434.3-173435.65"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$9782
+ attribute \src "libresoc.v:172569.13-172569.46"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$9910
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__invert_in$10$next[0:0]$9859
+ attribute \src "libresoc.v:173450.3-173451.67"
+ wire $0\logical_op__invert_in$10[0:0]$9798
+ attribute \src "libresoc.v:172653.7-172653.40"
+ wire $0\logical_op__invert_in$10[0:0]$9912
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__invert_out$13$next[0:0]$9860
+ attribute \src "libresoc.v:173456.3-173457.69"
+ wire $0\logical_op__invert_out$13[0:0]$9804
+ attribute \src "libresoc.v:172662.7-172662.41"
+ wire $0\logical_op__invert_out$13[0:0]$9914
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__is_32bit$16$next[0:0]$9861
+ attribute \src "libresoc.v:173462.3-173463.65"
+ wire $0\logical_op__is_32bit$16[0:0]$9810
+ attribute \src "libresoc.v:172671.7-172671.39"
+ wire $0\logical_op__is_32bit$16[0:0]$9916
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__is_signed$17$next[0:0]$9862
+ attribute \src "libresoc.v:173464.3-173465.67"
+ wire $0\logical_op__is_signed$17[0:0]$9812
+ attribute \src "libresoc.v:172680.7-172680.40"
+ wire $0\logical_op__is_signed$17[0:0]$9918
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__oe__oe$8$next[0:0]$9863
+ attribute \src "libresoc.v:173446.3-173447.59"
+ wire $0\logical_op__oe__oe$8[0:0]$9794
+ attribute \src "libresoc.v:172689.7-172689.36"
+ wire $0\logical_op__oe__oe$8[0:0]$9920
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__oe__ok$9$next[0:0]$9864
+ attribute \src "libresoc.v:173448.3-173449.59"
+ wire $0\logical_op__oe__ok$9[0:0]$9796
+ attribute \src "libresoc.v:172700.7-172700.36"
+ wire $0\logical_op__oe__ok$9[0:0]$9922
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__output_carry$15$next[0:0]$9865
+ attribute \src "libresoc.v:173460.3-173461.73"
+ wire $0\logical_op__output_carry$15[0:0]$9808
+ attribute \src "libresoc.v:172707.7-172707.43"
+ wire $0\logical_op__output_carry$15[0:0]$9924
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__rc__ok$7$next[0:0]$9866
+ attribute \src "libresoc.v:173444.3-173445.59"
+ wire $0\logical_op__rc__ok$7[0:0]$9792
+ attribute \src "libresoc.v:172716.7-172716.36"
+ wire $0\logical_op__rc__ok$7[0:0]$9926
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__rc__rc$6$next[0:0]$9867
+ attribute \src "libresoc.v:173442.3-173443.59"
+ wire $0\logical_op__rc__rc$6[0:0]$9790
+ attribute \src "libresoc.v:172725.7-172725.36"
+ wire $0\logical_op__rc__rc$6[0:0]$9928
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__write_cr0$14$next[0:0]$9868
+ attribute \src "libresoc.v:173458.3-173459.67"
+ wire $0\logical_op__write_cr0$14[0:0]$9806
+ attribute \src "libresoc.v:172734.7-172734.40"
+ wire $0\logical_op__write_cr0$14[0:0]$9930
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $0\logical_op__zero_a$11$next[0:0]$9869
+ attribute \src "libresoc.v:173452.3-173453.61"
+ wire $0\logical_op__zero_a$11[0:0]$9800
+ attribute \src "libresoc.v:172743.7-172743.37"
+ wire $0\logical_op__zero_a$11[0:0]$9932
+ attribute \src "libresoc.v:173682.3-173694.6"
+ wire width 2 $0\muxid$1$next[1:0]$9849
+ attribute \src "libresoc.v:173470.3-173471.33"
+ wire width 2 $0\muxid$1[1:0]$9818
+ attribute \src "libresoc.v:172752.13-172752.29"
+ wire width 2 $0\muxid$1[1:0]$9934
+ attribute \src "libresoc.v:173588.3-173606.6"
+ wire width 64 $0\o$next[63:0]$9821
+ attribute \src "libresoc.v:173430.3-173431.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:173924.3-173942.6"
- wire $0\o_ok$next[0:0]$9874
- attribute \src "libresoc.v:173768.3-173769.25"
+ attribute \src "libresoc.v:173588.3-173606.6"
+ wire $0\o_ok$next[0:0]$9822
+ attribute \src "libresoc.v:173432.3-173433.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:174000.3-174017.6"
- wire $0\r_busy$next[0:0]$9897
- attribute \src "libresoc.v:173808.3-173809.29"
+ attribute \src "libresoc.v:173664.3-173681.6"
+ wire $0\r_busy$next[0:0]$9845
+ attribute \src "libresoc.v:173472.3-173473.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:173962.3-173980.6"
- wire width 2 $0\xer_ov$next[1:0]$9885
- attribute \src "libresoc.v:173758.3-173759.29"
+ attribute \src "libresoc.v:173626.3-173644.6"
+ wire width 2 $0\xer_ov$next[1:0]$9833
+ attribute \src "libresoc.v:173422.3-173423.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:173962.3-173980.6"
- wire $0\xer_ov_ok$next[0:0]$9886
- attribute \src "libresoc.v:173760.3-173761.35"
+ attribute \src "libresoc.v:173626.3-173644.6"
+ wire $0\xer_ov_ok$next[0:0]$9834
+ attribute \src "libresoc.v:173424.3-173425.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:173981.3-173999.6"
- wire $0\xer_so$20$next[0:0]$9892
- attribute \src "libresoc.v:173754.3-173755.37"
- wire $0\xer_so$20[0:0]$9825
- attribute \src "libresoc.v:173739.7-173739.25"
- wire $0\xer_so$20[0:0]$9993
- attribute \src "libresoc.v:173981.3-173999.6"
- wire $0\xer_so_ok$next[0:0]$9891
- attribute \src "libresoc.v:173756.3-173757.35"
+ attribute \src "libresoc.v:173645.3-173663.6"
+ wire $0\xer_so$20$next[0:0]$9840
+ attribute \src "libresoc.v:173418.3-173419.37"
+ wire $0\xer_so$20[0:0]$9773
+ attribute \src "libresoc.v:173403.7-173403.25"
+ wire $0\xer_so$20[0:0]$9941
+ attribute \src "libresoc.v:173645.3-173663.6"
+ wire $0\xer_so_ok$next[0:0]$9839
+ attribute \src "libresoc.v:173420.3-173421.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:173943.3-173961.6"
- wire width 4 $1\cr_a$next[3:0]$9881
- attribute \src "libresoc.v:172612.13-172612.24"
+ attribute \src "libresoc.v:173607.3-173625.6"
+ wire width 4 $1\cr_a$next[3:0]$9829
+ attribute \src "libresoc.v:172276.13-172276.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:173943.3-173961.6"
- wire $1\cr_a_ok$next[0:0]$9882
- attribute \src "libresoc.v:172621.7-172621.21"
+ attribute \src "libresoc.v:173607.3-173625.6"
+ wire $1\cr_a_ok$next[0:0]$9830
+ attribute \src "libresoc.v:172285.7-172285.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 4 $1\logical_op__data_len$18$next[3:0]$9922
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9923
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9924
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__imm_data__ok$5$next[0:0]$9925
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 2 $1\logical_op__input_carry$12$next[1:0]$9926
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 32 $1\logical_op__insn$19$next[31:0]$9927
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 7 $1\logical_op__insn_type$2$next[6:0]$9928
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__invert_in$10$next[0:0]$9929
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__invert_out$13$next[0:0]$9930
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__is_32bit$16$next[0:0]$9931
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__is_signed$17$next[0:0]$9932
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__oe__oe$8$next[0:0]$9933
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__oe__ok$9$next[0:0]$9934
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__output_carry$15$next[0:0]$9935
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__rc__ok$7$next[0:0]$9936
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__rc__rc$6$next[0:0]$9937
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__write_cr0$14$next[0:0]$9938
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $1\logical_op__zero_a$11$next[0:0]$9939
- attribute \src "libresoc.v:174018.3-174030.6"
- wire width 2 $1\muxid$1$next[1:0]$9902
- attribute \src "libresoc.v:173924.3-173942.6"
- wire width 64 $1\o$next[63:0]$9875
- attribute \src "libresoc.v:173101.14-173101.38"
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 4 $1\logical_op__data_len$18$next[3:0]$9870
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9871
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9872
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__imm_data__ok$5$next[0:0]$9873
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 2 $1\logical_op__input_carry$12$next[1:0]$9874
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 32 $1\logical_op__insn$19$next[31:0]$9875
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 7 $1\logical_op__insn_type$2$next[6:0]$9876
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__invert_in$10$next[0:0]$9877
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__invert_out$13$next[0:0]$9878
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__is_32bit$16$next[0:0]$9879
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__is_signed$17$next[0:0]$9880
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__oe__oe$8$next[0:0]$9881
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__oe__ok$9$next[0:0]$9882
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__output_carry$15$next[0:0]$9883
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__rc__ok$7$next[0:0]$9884
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__rc__rc$6$next[0:0]$9885
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__write_cr0$14$next[0:0]$9886
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $1\logical_op__zero_a$11$next[0:0]$9887
+ attribute \src "libresoc.v:173682.3-173694.6"
+ wire width 2 $1\muxid$1$next[1:0]$9850
+ attribute \src "libresoc.v:173588.3-173606.6"
+ wire width 64 $1\o$next[63:0]$9823
+ attribute \src "libresoc.v:172765.14-172765.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:173924.3-173942.6"
- wire $1\o_ok$next[0:0]$9876
- attribute \src "libresoc.v:173108.7-173108.18"
+ attribute \src "libresoc.v:173588.3-173606.6"
+ wire $1\o_ok$next[0:0]$9824
+ attribute \src "libresoc.v:172772.7-172772.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:174000.3-174017.6"
- wire $1\r_busy$next[0:0]$9898
- attribute \src "libresoc.v:173704.7-173704.20"
+ attribute \src "libresoc.v:173664.3-173681.6"
+ wire $1\r_busy$next[0:0]$9846
+ attribute \src "libresoc.v:173368.7-173368.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:173962.3-173980.6"
- wire width 2 $1\xer_ov$next[1:0]$9887
- attribute \src "libresoc.v:173719.13-173719.26"
+ attribute \src "libresoc.v:173626.3-173644.6"
+ wire width 2 $1\xer_ov$next[1:0]$9835
+ attribute \src "libresoc.v:173383.13-173383.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:173962.3-173980.6"
- wire $1\xer_ov_ok$next[0:0]$9888
- attribute \src "libresoc.v:173726.7-173726.23"
+ attribute \src "libresoc.v:173626.3-173644.6"
+ wire $1\xer_ov_ok$next[0:0]$9836
+ attribute \src "libresoc.v:173390.7-173390.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:173981.3-173999.6"
- wire $1\xer_so$20$next[0:0]$9894
- attribute \src "libresoc.v:173981.3-173999.6"
- wire $1\xer_so_ok$next[0:0]$9893
- attribute \src "libresoc.v:173744.7-173744.23"
+ attribute \src "libresoc.v:173645.3-173663.6"
+ wire $1\xer_so$20$next[0:0]$9842
+ attribute \src "libresoc.v:173645.3-173663.6"
+ wire $1\xer_so_ok$next[0:0]$9841
+ attribute \src "libresoc.v:173408.7-173408.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:173943.3-173961.6"
- wire $2\cr_a_ok$next[0:0]$9883
- attribute \src "libresoc.v:174031.3-174072.6"
- wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9940
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $2\logical_op__imm_data__ok$5$next[0:0]$9941
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $2\logical_op__oe__oe$8$next[0:0]$9942
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $2\logical_op__oe__ok$9$next[0:0]$9943
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $2\logical_op__rc__ok$7$next[0:0]$9944
- attribute \src "libresoc.v:174031.3-174072.6"
- wire $2\logical_op__rc__rc$6$next[0:0]$9945
- attribute \src "libresoc.v:173924.3-173942.6"
- wire $2\o_ok$next[0:0]$9877
- attribute \src "libresoc.v:174000.3-174017.6"
- wire $2\r_busy$next[0:0]$9899
- attribute \src "libresoc.v:173962.3-173980.6"
- wire $2\xer_ov_ok$next[0:0]$9889
- attribute \src "libresoc.v:173981.3-173999.6"
- wire $2\xer_so_ok$next[0:0]$9895
- attribute \src "libresoc.v:173753.18-173753.118"
- wire $and$libresoc.v:173753$9823_Y
+ attribute \src "libresoc.v:173607.3-173625.6"
+ wire $2\cr_a_ok$next[0:0]$9831
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9888
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $2\logical_op__imm_data__ok$5$next[0:0]$9889
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $2\logical_op__oe__oe$8$next[0:0]$9890
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $2\logical_op__oe__ok$9$next[0:0]$9891
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $2\logical_op__rc__ok$7$next[0:0]$9892
+ attribute \src "libresoc.v:173695.3-173736.6"
+ wire $2\logical_op__rc__rc$6$next[0:0]$9893
+ attribute \src "libresoc.v:173588.3-173606.6"
+ wire $2\o_ok$next[0:0]$9825
+ attribute \src "libresoc.v:173664.3-173681.6"
+ wire $2\r_busy$next[0:0]$9847
+ attribute \src "libresoc.v:173626.3-173644.6"
+ wire $2\xer_ov_ok$next[0:0]$9837
+ attribute \src "libresoc.v:173645.3-173663.6"
+ wire $2\xer_so_ok$next[0:0]$9843
+ attribute \src "libresoc.v:173417.18-173417.118"
+ wire $and$libresoc.v:173417$9771_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 62 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 56 \cr_a
wire input 27 \dividend_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
wire input 26 \divisor_neg
- attribute \src "libresoc.v:172603.7-172603.15"
+ attribute \src "libresoc.v:172267.7-172267.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:173753$9823
+ cell $and $and$libresoc.v:173417$9771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$73
connect \B \p_ready_o
- connect \Y $and$libresoc.v:173753$9823_Y
+ connect \Y $and$libresoc.v:173417$9771_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173810.10-173813.4"
+ attribute \src "libresoc.v:173474.10-173477.4"
cell \n$82 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173814.15-173866.4"
+ attribute \src "libresoc.v:173478.15-173530.4"
cell \output$83 \output
connect \cr_a \output_cr_a
connect \cr_a$22 \output_cr_a$62
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173867.16-173919.4"
+ attribute \src "libresoc.v:173531.16-173583.4"
cell \output_stage \output_stage
connect \div_by_zero \output_stage_div_by_zero
connect \dive_abs_ov32 \output_stage_dive_abs_ov32
connect \xer_so$20 \output_stage_xer_so$40
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173920.10-173923.4"
+ attribute \src "libresoc.v:173584.10-173587.4"
cell \p$81 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:172603.7-172603.20"
- process $proc$libresoc.v:172603$9946
+ attribute \src "libresoc.v:172267.7-172267.20"
+ process $proc$libresoc.v:172267$9894
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:172612.13-172612.24"
- process $proc$libresoc.v:172612$9947
+ attribute \src "libresoc.v:172276.13-172276.24"
+ process $proc$libresoc.v:172276$9895
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:172621.7-172621.21"
- process $proc$libresoc.v:172621$9948
+ attribute \src "libresoc.v:172285.7-172285.21"
+ process $proc$libresoc.v:172285$9896
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:172644.13-172644.45"
- process $proc$libresoc.v:172644$9949
+ attribute \src "libresoc.v:172308.13-172308.45"
+ process $proc$libresoc.v:172308$9897
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$9950 4'0000
+ assign $0\logical_op__data_len$18[3:0]$9898 4'0000
sync always
sync init
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9950
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9898
end
- attribute \src "libresoc.v:172683.14-172683.48"
- process $proc$libresoc.v:172683$9951
+ attribute \src "libresoc.v:172347.14-172347.48"
+ process $proc$libresoc.v:172347$9899
assign { } { }
- assign $0\logical_op__fn_unit$3[13:0]$9952 14'00000000000000
+ assign $0\logical_op__fn_unit$3[13:0]$9900 14'00000000000000
sync always
sync init
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9952
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9900
end
- attribute \src "libresoc.v:172707.14-172707.67"
- process $proc$libresoc.v:172707$9953
+ attribute \src "libresoc.v:172371.14-172371.67"
+ process $proc$libresoc.v:172371$9901
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$9954 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$4[63:0]$9902 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9954
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9902
end
- attribute \src "libresoc.v:172716.7-172716.42"
- process $proc$libresoc.v:172716$9955
+ attribute \src "libresoc.v:172380.7-172380.42"
+ process $proc$libresoc.v:172380$9903
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$9956 1'0
+ assign $0\logical_op__imm_data__ok$5[0:0]$9904 1'0
sync always
sync init
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9956
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9904
end
- attribute \src "libresoc.v:172733.13-172733.48"
- process $proc$libresoc.v:172733$9957
+ attribute \src "libresoc.v:172397.13-172397.48"
+ process $proc$libresoc.v:172397$9905
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$9958 2'00
+ assign $0\logical_op__input_carry$12[1:0]$9906 2'00
sync always
sync init
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9958
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9906
end
- attribute \src "libresoc.v:172746.14-172746.43"
- process $proc$libresoc.v:172746$9959
+ attribute \src "libresoc.v:172410.14-172410.43"
+ process $proc$libresoc.v:172410$9907
assign { } { }
- assign $0\logical_op__insn$19[31:0]$9960 0
+ assign $0\logical_op__insn$19[31:0]$9908 0
sync always
sync init
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9960
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9908
end
- attribute \src "libresoc.v:172905.13-172905.46"
- process $proc$libresoc.v:172905$9961
+ attribute \src "libresoc.v:172569.13-172569.46"
+ process $proc$libresoc.v:172569$9909
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$9962 7'0000000
+ assign $0\logical_op__insn_type$2[6:0]$9910 7'0000000
sync always
sync init
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9962
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9910
end
- attribute \src "libresoc.v:172989.7-172989.40"
- process $proc$libresoc.v:172989$9963
+ attribute \src "libresoc.v:172653.7-172653.40"
+ process $proc$libresoc.v:172653$9911
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$9964 1'0
+ assign $0\logical_op__invert_in$10[0:0]$9912 1'0
sync always
sync init
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9964
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9912
end
- attribute \src "libresoc.v:172998.7-172998.41"
- process $proc$libresoc.v:172998$9965
+ attribute \src "libresoc.v:172662.7-172662.41"
+ process $proc$libresoc.v:172662$9913
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$9966 1'0
+ assign $0\logical_op__invert_out$13[0:0]$9914 1'0
sync always
sync init
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9966
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9914
end
- attribute \src "libresoc.v:173007.7-173007.39"
- process $proc$libresoc.v:173007$9967
+ attribute \src "libresoc.v:172671.7-172671.39"
+ process $proc$libresoc.v:172671$9915
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$9968 1'0
+ assign $0\logical_op__is_32bit$16[0:0]$9916 1'0
sync always
sync init
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9968
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9916
end
- attribute \src "libresoc.v:173016.7-173016.40"
- process $proc$libresoc.v:173016$9969
+ attribute \src "libresoc.v:172680.7-172680.40"
+ process $proc$libresoc.v:172680$9917
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$9970 1'0
+ assign $0\logical_op__is_signed$17[0:0]$9918 1'0
sync always
sync init
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9970
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9918
end
- attribute \src "libresoc.v:173025.7-173025.36"
- process $proc$libresoc.v:173025$9971
+ attribute \src "libresoc.v:172689.7-172689.36"
+ process $proc$libresoc.v:172689$9919
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$9972 1'0
+ assign $0\logical_op__oe__oe$8[0:0]$9920 1'0
sync always
sync init
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9972
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9920
end
- attribute \src "libresoc.v:173036.7-173036.36"
- process $proc$libresoc.v:173036$9973
+ attribute \src "libresoc.v:172700.7-172700.36"
+ process $proc$libresoc.v:172700$9921
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$9974 1'0
+ assign $0\logical_op__oe__ok$9[0:0]$9922 1'0
sync always
sync init
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9974
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9922
end
- attribute \src "libresoc.v:173043.7-173043.43"
- process $proc$libresoc.v:173043$9975
+ attribute \src "libresoc.v:172707.7-172707.43"
+ process $proc$libresoc.v:172707$9923
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$9976 1'0
+ assign $0\logical_op__output_carry$15[0:0]$9924 1'0
sync always
sync init
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9976
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9924
end
- attribute \src "libresoc.v:173052.7-173052.36"
- process $proc$libresoc.v:173052$9977
+ attribute \src "libresoc.v:172716.7-172716.36"
+ process $proc$libresoc.v:172716$9925
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$9978 1'0
+ assign $0\logical_op__rc__ok$7[0:0]$9926 1'0
sync always
sync init
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9978
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9926
end
- attribute \src "libresoc.v:173061.7-173061.36"
- process $proc$libresoc.v:173061$9979
+ attribute \src "libresoc.v:172725.7-172725.36"
+ process $proc$libresoc.v:172725$9927
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$9980 1'0
+ assign $0\logical_op__rc__rc$6[0:0]$9928 1'0
sync always
sync init
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9980
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9928
end
- attribute \src "libresoc.v:173070.7-173070.40"
- process $proc$libresoc.v:173070$9981
+ attribute \src "libresoc.v:172734.7-172734.40"
+ process $proc$libresoc.v:172734$9929
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$9982 1'0
+ assign $0\logical_op__write_cr0$14[0:0]$9930 1'0
sync always
sync init
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9982
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9930
end
- attribute \src "libresoc.v:173079.7-173079.37"
- process $proc$libresoc.v:173079$9983
+ attribute \src "libresoc.v:172743.7-172743.37"
+ process $proc$libresoc.v:172743$9931
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$9984 1'0
+ assign $0\logical_op__zero_a$11[0:0]$9932 1'0
sync always
sync init
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9984
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9932
end
- attribute \src "libresoc.v:173088.13-173088.29"
- process $proc$libresoc.v:173088$9985
+ attribute \src "libresoc.v:172752.13-172752.29"
+ process $proc$libresoc.v:172752$9933
assign { } { }
- assign $0\muxid$1[1:0]$9986 2'00
+ assign $0\muxid$1[1:0]$9934 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9986
+ update \muxid$1 $0\muxid$1[1:0]$9934
end
- attribute \src "libresoc.v:173101.14-173101.38"
- process $proc$libresoc.v:173101$9987
+ attribute \src "libresoc.v:172765.14-172765.38"
+ process $proc$libresoc.v:172765$9935
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:173108.7-173108.18"
- process $proc$libresoc.v:173108$9988
+ attribute \src "libresoc.v:172772.7-172772.18"
+ process $proc$libresoc.v:172772$9936
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:173704.7-173704.20"
- process $proc$libresoc.v:173704$9989
+ attribute \src "libresoc.v:173368.7-173368.20"
+ process $proc$libresoc.v:173368$9937
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:173719.13-173719.26"
- process $proc$libresoc.v:173719$9990
+ attribute \src "libresoc.v:173383.13-173383.26"
+ process $proc$libresoc.v:173383$9938
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:173726.7-173726.23"
- process $proc$libresoc.v:173726$9991
+ attribute \src "libresoc.v:173390.7-173390.23"
+ process $proc$libresoc.v:173390$9939
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:173739.7-173739.25"
- process $proc$libresoc.v:173739$9992
+ attribute \src "libresoc.v:173403.7-173403.25"
+ process $proc$libresoc.v:173403$9940
assign { } { }
- assign $0\xer_so$20[0:0]$9993 1'0
+ assign $0\xer_so$20[0:0]$9941 1'0
sync always
sync init
- update \xer_so$20 $0\xer_so$20[0:0]$9993
+ update \xer_so$20 $0\xer_so$20[0:0]$9941
end
- attribute \src "libresoc.v:173744.7-173744.23"
- process $proc$libresoc.v:173744$9994
+ attribute \src "libresoc.v:173408.7-173408.23"
+ process $proc$libresoc.v:173408$9942
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:173754.3-173755.37"
- process $proc$libresoc.v:173754$9824
+ attribute \src "libresoc.v:173418.3-173419.37"
+ process $proc$libresoc.v:173418$9772
assign { } { }
- assign $0\xer_so$20[0:0]$9825 \xer_so$20$next
+ assign $0\xer_so$20[0:0]$9773 \xer_so$20$next
sync posedge \coresync_clk
- update \xer_so$20 $0\xer_so$20[0:0]$9825
+ update \xer_so$20 $0\xer_so$20[0:0]$9773
end
- attribute \src "libresoc.v:173756.3-173757.35"
- process $proc$libresoc.v:173756$9826
+ attribute \src "libresoc.v:173420.3-173421.35"
+ process $proc$libresoc.v:173420$9774
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:173758.3-173759.29"
- process $proc$libresoc.v:173758$9827
+ attribute \src "libresoc.v:173422.3-173423.29"
+ process $proc$libresoc.v:173422$9775
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:173760.3-173761.35"
- process $proc$libresoc.v:173760$9828
+ attribute \src "libresoc.v:173424.3-173425.35"
+ process $proc$libresoc.v:173424$9776
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:173762.3-173763.25"
- process $proc$libresoc.v:173762$9829
+ attribute \src "libresoc.v:173426.3-173427.25"
+ process $proc$libresoc.v:173426$9777
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:173764.3-173765.31"
- process $proc$libresoc.v:173764$9830
+ attribute \src "libresoc.v:173428.3-173429.31"
+ process $proc$libresoc.v:173428$9778
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:173766.3-173767.19"
- process $proc$libresoc.v:173766$9831
+ attribute \src "libresoc.v:173430.3-173431.19"
+ process $proc$libresoc.v:173430$9779
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:173768.3-173769.25"
- process $proc$libresoc.v:173768$9832
+ attribute \src "libresoc.v:173432.3-173433.25"
+ process $proc$libresoc.v:173432$9780
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:173770.3-173771.65"
- process $proc$libresoc.v:173770$9833
+ attribute \src "libresoc.v:173434.3-173435.65"
+ process $proc$libresoc.v:173434$9781
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$9834 \logical_op__insn_type$2$next
+ assign $0\logical_op__insn_type$2[6:0]$9782 \logical_op__insn_type$2$next
sync posedge \coresync_clk
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9834
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9782
end
- attribute \src "libresoc.v:173772.3-173773.61"
- process $proc$libresoc.v:173772$9835
+ attribute \src "libresoc.v:173436.3-173437.61"
+ process $proc$libresoc.v:173436$9783
assign { } { }
- assign $0\logical_op__fn_unit$3[13:0]$9836 \logical_op__fn_unit$3$next
+ assign $0\logical_op__fn_unit$3[13:0]$9784 \logical_op__fn_unit$3$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9836
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9784
end
- attribute \src "libresoc.v:173774.3-173775.75"
- process $proc$libresoc.v:173774$9837
+ attribute \src "libresoc.v:173438.3-173439.75"
+ process $proc$libresoc.v:173438$9785
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$9838 \logical_op__imm_data__data$4$next
+ assign $0\logical_op__imm_data__data$4[63:0]$9786 \logical_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9838
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9786
end
- attribute \src "libresoc.v:173776.3-173777.71"
- process $proc$libresoc.v:173776$9839
+ attribute \src "libresoc.v:173440.3-173441.71"
+ process $proc$libresoc.v:173440$9787
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$9840 \logical_op__imm_data__ok$5$next
+ assign $0\logical_op__imm_data__ok$5[0:0]$9788 \logical_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9840
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9788
end
- attribute \src "libresoc.v:173778.3-173779.59"
- process $proc$libresoc.v:173778$9841
+ attribute \src "libresoc.v:173442.3-173443.59"
+ process $proc$libresoc.v:173442$9789
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$9842 \logical_op__rc__rc$6$next
+ assign $0\logical_op__rc__rc$6[0:0]$9790 \logical_op__rc__rc$6$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9842
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9790
end
- attribute \src "libresoc.v:173780.3-173781.59"
- process $proc$libresoc.v:173780$9843
+ attribute \src "libresoc.v:173444.3-173445.59"
+ process $proc$libresoc.v:173444$9791
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$9844 \logical_op__rc__ok$7$next
+ assign $0\logical_op__rc__ok$7[0:0]$9792 \logical_op__rc__ok$7$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9844
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9792
end
- attribute \src "libresoc.v:173782.3-173783.59"
- process $proc$libresoc.v:173782$9845
+ attribute \src "libresoc.v:173446.3-173447.59"
+ process $proc$libresoc.v:173446$9793
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$9846 \logical_op__oe__oe$8$next
+ assign $0\logical_op__oe__oe$8[0:0]$9794 \logical_op__oe__oe$8$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9846
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9794
end
- attribute \src "libresoc.v:173784.3-173785.59"
- process $proc$libresoc.v:173784$9847
+ attribute \src "libresoc.v:173448.3-173449.59"
+ process $proc$libresoc.v:173448$9795
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$9848 \logical_op__oe__ok$9$next
+ assign $0\logical_op__oe__ok$9[0:0]$9796 \logical_op__oe__ok$9$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9848
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9796
end
- attribute \src "libresoc.v:173786.3-173787.67"
- process $proc$libresoc.v:173786$9849
+ attribute \src "libresoc.v:173450.3-173451.67"
+ process $proc$libresoc.v:173450$9797
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$9850 \logical_op__invert_in$10$next
+ assign $0\logical_op__invert_in$10[0:0]$9798 \logical_op__invert_in$10$next
sync posedge \coresync_clk
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9850
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9798
end
- attribute \src "libresoc.v:173788.3-173789.61"
- process $proc$libresoc.v:173788$9851
+ attribute \src "libresoc.v:173452.3-173453.61"
+ process $proc$libresoc.v:173452$9799
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$9852 \logical_op__zero_a$11$next
+ assign $0\logical_op__zero_a$11[0:0]$9800 \logical_op__zero_a$11$next
sync posedge \coresync_clk
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9852
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9800
end
- attribute \src "libresoc.v:173790.3-173791.71"
- process $proc$libresoc.v:173790$9853
+ attribute \src "libresoc.v:173454.3-173455.71"
+ process $proc$libresoc.v:173454$9801
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$9854 \logical_op__input_carry$12$next
+ assign $0\logical_op__input_carry$12[1:0]$9802 \logical_op__input_carry$12$next
sync posedge \coresync_clk
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9854
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9802
end
- attribute \src "libresoc.v:173792.3-173793.69"
- process $proc$libresoc.v:173792$9855
+ attribute \src "libresoc.v:173456.3-173457.69"
+ process $proc$libresoc.v:173456$9803
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$9856 \logical_op__invert_out$13$next
+ assign $0\logical_op__invert_out$13[0:0]$9804 \logical_op__invert_out$13$next
sync posedge \coresync_clk
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9856
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9804
end
- attribute \src "libresoc.v:173794.3-173795.67"
- process $proc$libresoc.v:173794$9857
+ attribute \src "libresoc.v:173458.3-173459.67"
+ process $proc$libresoc.v:173458$9805
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$9858 \logical_op__write_cr0$14$next
+ assign $0\logical_op__write_cr0$14[0:0]$9806 \logical_op__write_cr0$14$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9858
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9806
end
- attribute \src "libresoc.v:173796.3-173797.73"
- process $proc$libresoc.v:173796$9859
+ attribute \src "libresoc.v:173460.3-173461.73"
+ process $proc$libresoc.v:173460$9807
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$9860 \logical_op__output_carry$15$next
+ assign $0\logical_op__output_carry$15[0:0]$9808 \logical_op__output_carry$15$next
sync posedge \coresync_clk
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9860
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9808
end
- attribute \src "libresoc.v:173798.3-173799.65"
- process $proc$libresoc.v:173798$9861
+ attribute \src "libresoc.v:173462.3-173463.65"
+ process $proc$libresoc.v:173462$9809
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$9862 \logical_op__is_32bit$16$next
+ assign $0\logical_op__is_32bit$16[0:0]$9810 \logical_op__is_32bit$16$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9862
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9810
end
- attribute \src "libresoc.v:173800.3-173801.67"
- process $proc$libresoc.v:173800$9863
+ attribute \src "libresoc.v:173464.3-173465.67"
+ process $proc$libresoc.v:173464$9811
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$9864 \logical_op__is_signed$17$next
+ assign $0\logical_op__is_signed$17[0:0]$9812 \logical_op__is_signed$17$next
sync posedge \coresync_clk
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9864
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9812
end
- attribute \src "libresoc.v:173802.3-173803.65"
- process $proc$libresoc.v:173802$9865
+ attribute \src "libresoc.v:173466.3-173467.65"
+ process $proc$libresoc.v:173466$9813
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$9866 \logical_op__data_len$18$next
+ assign $0\logical_op__data_len$18[3:0]$9814 \logical_op__data_len$18$next
sync posedge \coresync_clk
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9866
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9814
end
- attribute \src "libresoc.v:173804.3-173805.57"
- process $proc$libresoc.v:173804$9867
+ attribute \src "libresoc.v:173468.3-173469.57"
+ process $proc$libresoc.v:173468$9815
assign { } { }
- assign $0\logical_op__insn$19[31:0]$9868 \logical_op__insn$19$next
+ assign $0\logical_op__insn$19[31:0]$9816 \logical_op__insn$19$next
sync posedge \coresync_clk
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9868
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9816
end
- attribute \src "libresoc.v:173806.3-173807.33"
- process $proc$libresoc.v:173806$9869
+ attribute \src "libresoc.v:173470.3-173471.33"
+ process $proc$libresoc.v:173470$9817
assign { } { }
- assign $0\muxid$1[1:0]$9870 \muxid$1$next
+ assign $0\muxid$1[1:0]$9818 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9870
+ update \muxid$1 $0\muxid$1[1:0]$9818
end
- attribute \src "libresoc.v:173808.3-173809.29"
- process $proc$libresoc.v:173808$9871
+ attribute \src "libresoc.v:173472.3-173473.29"
+ process $proc$libresoc.v:173472$9819
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:173924.3-173942.6"
- process $proc$libresoc.v:173924$9872
+ attribute \src "libresoc.v:173588.3-173606.6"
+ process $proc$libresoc.v:173588$9820
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9873 $1\o$next[63:0]$9875
+ assign $0\o$next[63:0]$9821 $1\o$next[63:0]$9823
assign { } { }
- assign $0\o_ok$next[0:0]$9874 $2\o_ok$next[0:0]$9877
- attribute \src "libresoc.v:173925.5-173925.29"
+ assign $0\o_ok$next[0:0]$9822 $2\o_ok$next[0:0]$9825
+ attribute \src "libresoc.v:173589.5-173589.29"
switch \initial
- attribute \src "libresoc.v:173925.9-173925.17"
+ attribute \src "libresoc.v:173589.9-173589.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9876 $1\o$next[63:0]$9875 } { \o_ok$96 \o$95 }
+ assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9876 $1\o$next[63:0]$9875 } { \o_ok$96 \o$95 }
+ assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 }
case
- assign $1\o$next[63:0]$9875 \o
- assign $1\o_ok$next[0:0]$9876 \o_ok
+ assign $1\o$next[63:0]$9823 \o
+ assign $1\o_ok$next[0:0]$9824 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9877 1'0
+ assign $2\o_ok$next[0:0]$9825 1'0
case
- assign $2\o_ok$next[0:0]$9877 $1\o_ok$next[0:0]$9876
+ assign $2\o_ok$next[0:0]$9825 $1\o_ok$next[0:0]$9824
end
sync always
- update \o$next $0\o$next[63:0]$9873
- update \o_ok$next $0\o_ok$next[0:0]$9874
+ update \o$next $0\o$next[63:0]$9821
+ update \o_ok$next $0\o_ok$next[0:0]$9822
end
- attribute \src "libresoc.v:173943.3-173961.6"
- process $proc$libresoc.v:173943$9878
+ attribute \src "libresoc.v:173607.3-173625.6"
+ process $proc$libresoc.v:173607$9826
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9879 $1\cr_a$next[3:0]$9881
+ assign $0\cr_a$next[3:0]$9827 $1\cr_a$next[3:0]$9829
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9880 $2\cr_a_ok$next[0:0]$9883
- attribute \src "libresoc.v:173944.5-173944.29"
+ assign $0\cr_a_ok$next[0:0]$9828 $2\cr_a_ok$next[0:0]$9831
+ attribute \src "libresoc.v:173608.5-173608.29"
switch \initial
- attribute \src "libresoc.v:173944.9-173944.17"
+ attribute \src "libresoc.v:173608.9-173608.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9882 $1\cr_a$next[3:0]$9881 } { \cr_a_ok$98 \cr_a$97 }
+ assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9882 $1\cr_a$next[3:0]$9881 } { \cr_a_ok$98 \cr_a$97 }
+ assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 }
case
- assign $1\cr_a$next[3:0]$9881 \cr_a
- assign $1\cr_a_ok$next[0:0]$9882 \cr_a_ok
+ assign $1\cr_a$next[3:0]$9829 \cr_a
+ assign $1\cr_a_ok$next[0:0]$9830 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9883 1'0
+ assign $2\cr_a_ok$next[0:0]$9831 1'0
case
- assign $2\cr_a_ok$next[0:0]$9883 $1\cr_a_ok$next[0:0]$9882
+ assign $2\cr_a_ok$next[0:0]$9831 $1\cr_a_ok$next[0:0]$9830
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9879
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9880
+ update \cr_a$next $0\cr_a$next[3:0]$9827
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9828
end
- attribute \src "libresoc.v:173962.3-173980.6"
- process $proc$libresoc.v:173962$9884
+ attribute \src "libresoc.v:173626.3-173644.6"
+ process $proc$libresoc.v:173626$9832
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$9885 $1\xer_ov$next[1:0]$9887
+ assign $0\xer_ov$next[1:0]$9833 $1\xer_ov$next[1:0]$9835
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$9886 $2\xer_ov_ok$next[0:0]$9889
- attribute \src "libresoc.v:173963.5-173963.29"
+ assign $0\xer_ov_ok$next[0:0]$9834 $2\xer_ov_ok$next[0:0]$9837
+ attribute \src "libresoc.v:173627.5-173627.29"
switch \initial
- attribute \src "libresoc.v:173963.9-173963.17"
+ attribute \src "libresoc.v:173627.9-173627.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9888 $1\xer_ov$next[1:0]$9887 } { \xer_ov_ok$100 \xer_ov$99 }
+ assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9888 $1\xer_ov$next[1:0]$9887 } { \xer_ov_ok$100 \xer_ov$99 }
+ assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 }
case
- assign $1\xer_ov$next[1:0]$9887 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$9888 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$9835 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$9836 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$9889 1'0
+ assign $2\xer_ov_ok$next[0:0]$9837 1'0
case
- assign $2\xer_ov_ok$next[0:0]$9889 $1\xer_ov_ok$next[0:0]$9888
+ assign $2\xer_ov_ok$next[0:0]$9837 $1\xer_ov_ok$next[0:0]$9836
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$9885
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9886
+ update \xer_ov$next $0\xer_ov$next[1:0]$9833
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9834
end
- attribute \src "libresoc.v:173981.3-173999.6"
- process $proc$libresoc.v:173981$9890
+ attribute \src "libresoc.v:173645.3-173663.6"
+ process $proc$libresoc.v:173645$9838
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$20$next[0:0]$9892 $1\xer_so$20$next[0:0]$9894
- assign $0\xer_so_ok$next[0:0]$9891 $2\xer_so_ok$next[0:0]$9895
- attribute \src "libresoc.v:173982.5-173982.29"
+ assign $0\xer_so$20$next[0:0]$9840 $1\xer_so$20$next[0:0]$9842
+ assign $0\xer_so_ok$next[0:0]$9839 $2\xer_so_ok$next[0:0]$9843
+ attribute \src "libresoc.v:173646.5-173646.29"
switch \initial
- attribute \src "libresoc.v:173982.9-173982.17"
+ attribute \src "libresoc.v:173646.9-173646.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9893 $1\xer_so$20$next[0:0]$9894 } { \xer_so_ok$102 \xer_so$101 }
+ assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9893 $1\xer_so$20$next[0:0]$9894 } { \xer_so_ok$102 \xer_so$101 }
+ assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 }
case
- assign $1\xer_so_ok$next[0:0]$9893 \xer_so_ok
- assign $1\xer_so$20$next[0:0]$9894 \xer_so$20
+ assign $1\xer_so_ok$next[0:0]$9841 \xer_so_ok
+ assign $1\xer_so$20$next[0:0]$9842 \xer_so$20
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9895 1'0
+ assign $2\xer_so_ok$next[0:0]$9843 1'0
case
- assign $2\xer_so_ok$next[0:0]$9895 $1\xer_so_ok$next[0:0]$9893
+ assign $2\xer_so_ok$next[0:0]$9843 $1\xer_so_ok$next[0:0]$9841
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9891
- update \xer_so$20$next $0\xer_so$20$next[0:0]$9892
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9839
+ update \xer_so$20$next $0\xer_so$20$next[0:0]$9840
end
- attribute \src "libresoc.v:174000.3-174017.6"
- process $proc$libresoc.v:174000$9896
+ attribute \src "libresoc.v:173664.3-173681.6"
+ process $proc$libresoc.v:173664$9844
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9897 $2\r_busy$next[0:0]$9899
- attribute \src "libresoc.v:174001.5-174001.29"
+ assign $0\r_busy$next[0:0]$9845 $2\r_busy$next[0:0]$9847
+ attribute \src "libresoc.v:173665.5-173665.29"
switch \initial
- attribute \src "libresoc.v:174001.9-174001.17"
+ attribute \src "libresoc.v:173665.9-173665.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9898 1'1
+ assign $1\r_busy$next[0:0]$9846 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9898 1'0
+ assign $1\r_busy$next[0:0]$9846 1'0
case
- assign $1\r_busy$next[0:0]$9898 \r_busy
+ assign $1\r_busy$next[0:0]$9846 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9899 1'0
+ assign $2\r_busy$next[0:0]$9847 1'0
case
- assign $2\r_busy$next[0:0]$9899 $1\r_busy$next[0:0]$9898
+ assign $2\r_busy$next[0:0]$9847 $1\r_busy$next[0:0]$9846
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9897
+ update \r_busy$next $0\r_busy$next[0:0]$9845
end
- attribute \src "libresoc.v:174018.3-174030.6"
- process $proc$libresoc.v:174018$9900
+ attribute \src "libresoc.v:173682.3-173694.6"
+ process $proc$libresoc.v:173682$9848
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9901 $1\muxid$1$next[1:0]$9902
- attribute \src "libresoc.v:174019.5-174019.29"
+ assign $0\muxid$1$next[1:0]$9849 $1\muxid$1$next[1:0]$9850
+ attribute \src "libresoc.v:173683.5-173683.29"
switch \initial
- attribute \src "libresoc.v:174019.9-174019.17"
+ attribute \src "libresoc.v:173683.9-173683.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9902 \muxid$76
+ assign $1\muxid$1$next[1:0]$9850 \muxid$76
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9902 \muxid$76
+ assign $1\muxid$1$next[1:0]$9850 \muxid$76
case
- assign $1\muxid$1$next[1:0]$9902 \muxid$1
+ assign $1\muxid$1$next[1:0]$9850 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9901
+ update \muxid$1$next $0\muxid$1$next[1:0]$9849
end
- attribute \src "libresoc.v:174031.3-174072.6"
- process $proc$libresoc.v:174031$9903
+ attribute \src "libresoc.v:173695.3-173736.6"
+ process $proc$libresoc.v:173695$9851
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$18$next[3:0]$9904 $1\logical_op__data_len$18$next[3:0]$9922
- assign $0\logical_op__fn_unit$3$next[13:0]$9905 $1\logical_op__fn_unit$3$next[13:0]$9923
+ assign $0\logical_op__data_len$18$next[3:0]$9852 $1\logical_op__data_len$18$next[3:0]$9870
+ assign $0\logical_op__fn_unit$3$next[13:0]$9853 $1\logical_op__fn_unit$3$next[13:0]$9871
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$12$next[1:0]$9908 $1\logical_op__input_carry$12$next[1:0]$9926
- assign $0\logical_op__insn$19$next[31:0]$9909 $1\logical_op__insn$19$next[31:0]$9927
- assign $0\logical_op__insn_type$2$next[6:0]$9910 $1\logical_op__insn_type$2$next[6:0]$9928
- assign $0\logical_op__invert_in$10$next[0:0]$9911 $1\logical_op__invert_in$10$next[0:0]$9929
- assign $0\logical_op__invert_out$13$next[0:0]$9912 $1\logical_op__invert_out$13$next[0:0]$9930
- assign $0\logical_op__is_32bit$16$next[0:0]$9913 $1\logical_op__is_32bit$16$next[0:0]$9931
- assign $0\logical_op__is_signed$17$next[0:0]$9914 $1\logical_op__is_signed$17$next[0:0]$9932
+ assign $0\logical_op__input_carry$12$next[1:0]$9856 $1\logical_op__input_carry$12$next[1:0]$9874
+ assign $0\logical_op__insn$19$next[31:0]$9857 $1\logical_op__insn$19$next[31:0]$9875
+ assign $0\logical_op__insn_type$2$next[6:0]$9858 $1\logical_op__insn_type$2$next[6:0]$9876
+ assign $0\logical_op__invert_in$10$next[0:0]$9859 $1\logical_op__invert_in$10$next[0:0]$9877
+ assign $0\logical_op__invert_out$13$next[0:0]$9860 $1\logical_op__invert_out$13$next[0:0]$9878
+ assign $0\logical_op__is_32bit$16$next[0:0]$9861 $1\logical_op__is_32bit$16$next[0:0]$9879
+ assign $0\logical_op__is_signed$17$next[0:0]$9862 $1\logical_op__is_signed$17$next[0:0]$9880
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$15$next[0:0]$9917 $1\logical_op__output_carry$15$next[0:0]$9935
+ assign $0\logical_op__output_carry$15$next[0:0]$9865 $1\logical_op__output_carry$15$next[0:0]$9883
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$14$next[0:0]$9920 $1\logical_op__write_cr0$14$next[0:0]$9938
- assign $0\logical_op__zero_a$11$next[0:0]$9921 $1\logical_op__zero_a$11$next[0:0]$9939
- assign $0\logical_op__imm_data__data$4$next[63:0]$9906 $2\logical_op__imm_data__data$4$next[63:0]$9940
- assign $0\logical_op__imm_data__ok$5$next[0:0]$9907 $2\logical_op__imm_data__ok$5$next[0:0]$9941
- assign $0\logical_op__oe__oe$8$next[0:0]$9915 $2\logical_op__oe__oe$8$next[0:0]$9942
- assign $0\logical_op__oe__ok$9$next[0:0]$9916 $2\logical_op__oe__ok$9$next[0:0]$9943
- assign $0\logical_op__rc__ok$7$next[0:0]$9918 $2\logical_op__rc__ok$7$next[0:0]$9944
- assign $0\logical_op__rc__rc$6$next[0:0]$9919 $2\logical_op__rc__rc$6$next[0:0]$9945
- attribute \src "libresoc.v:174032.5-174032.29"
+ assign $0\logical_op__write_cr0$14$next[0:0]$9868 $1\logical_op__write_cr0$14$next[0:0]$9886
+ assign $0\logical_op__zero_a$11$next[0:0]$9869 $1\logical_op__zero_a$11$next[0:0]$9887
+ assign $0\logical_op__imm_data__data$4$next[63:0]$9854 $2\logical_op__imm_data__data$4$next[63:0]$9888
+ assign $0\logical_op__imm_data__ok$5$next[0:0]$9855 $2\logical_op__imm_data__ok$5$next[0:0]$9889
+ assign $0\logical_op__oe__oe$8$next[0:0]$9863 $2\logical_op__oe__oe$8$next[0:0]$9890
+ assign $0\logical_op__oe__ok$9$next[0:0]$9864 $2\logical_op__oe__ok$9$next[0:0]$9891
+ assign $0\logical_op__rc__ok$7$next[0:0]$9866 $2\logical_op__rc__ok$7$next[0:0]$9892
+ assign $0\logical_op__rc__rc$6$next[0:0]$9867 $2\logical_op__rc__rc$6$next[0:0]$9893
+ attribute \src "libresoc.v:173696.5-173696.29"
switch \initial
- attribute \src "libresoc.v:174032.9-174032.17"
+ attribute \src "libresoc.v:173696.9-173696.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$9927 $1\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__oe__ok$9$next[0:0]$9934 $1\logical_op__oe__oe$8$next[0:0]$9933 $1\logical_op__rc__ok$7$next[0:0]$9936 $1\logical_op__rc__rc$6$next[0:0]$9937 $1\logical_op__imm_data__ok$5$next[0:0]$9925 $1\logical_op__imm_data__data$4$next[63:0]$9924 $1\logical_op__fn_unit$3$next[13:0]$9923 $1\logical_op__insn_type$2$next[6:0]$9928 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+ assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$9927 $1\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__oe__ok$9$next[0:0]$9934 $1\logical_op__oe__oe$8$next[0:0]$9933 $1\logical_op__rc__ok$7$next[0:0]$9936 $1\logical_op__rc__rc$6$next[0:0]$9937 $1\logical_op__imm_data__ok$5$next[0:0]$9925 $1\logical_op__imm_data__data$4$next[63:0]$9924 $1\logical_op__fn_unit$3$next[13:0]$9923 $1\logical_op__insn_type$2$next[6:0]$9928 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+ assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
case
- assign $1\logical_op__data_len$18$next[3:0]$9922 \logical_op__data_len$18
- assign $1\logical_op__fn_unit$3$next[13:0]$9923 \logical_op__fn_unit$3
- assign $1\logical_op__imm_data__data$4$next[63:0]$9924 \logical_op__imm_data__data$4
- assign $1\logical_op__imm_data__ok$5$next[0:0]$9925 \logical_op__imm_data__ok$5
- assign $1\logical_op__input_carry$12$next[1:0]$9926 \logical_op__input_carry$12
- assign $1\logical_op__insn$19$next[31:0]$9927 \logical_op__insn$19
- assign $1\logical_op__insn_type$2$next[6:0]$9928 \logical_op__insn_type$2
- assign $1\logical_op__invert_in$10$next[0:0]$9929 \logical_op__invert_in$10
- assign $1\logical_op__invert_out$13$next[0:0]$9930 \logical_op__invert_out$13
- assign $1\logical_op__is_32bit$16$next[0:0]$9931 \logical_op__is_32bit$16
- assign $1\logical_op__is_signed$17$next[0:0]$9932 \logical_op__is_signed$17
- assign $1\logical_op__oe__oe$8$next[0:0]$9933 \logical_op__oe__oe$8
- assign $1\logical_op__oe__ok$9$next[0:0]$9934 \logical_op__oe__ok$9
- assign $1\logical_op__output_carry$15$next[0:0]$9935 \logical_op__output_carry$15
- assign $1\logical_op__rc__ok$7$next[0:0]$9936 \logical_op__rc__ok$7
- assign $1\logical_op__rc__rc$6$next[0:0]$9937 \logical_op__rc__rc$6
- assign $1\logical_op__write_cr0$14$next[0:0]$9938 \logical_op__write_cr0$14
- assign $1\logical_op__zero_a$11$next[0:0]$9939 \logical_op__zero_a$11
+ assign $1\logical_op__data_len$18$next[3:0]$9870 \logical_op__data_len$18
+ assign $1\logical_op__fn_unit$3$next[13:0]$9871 \logical_op__fn_unit$3
+ assign $1\logical_op__imm_data__data$4$next[63:0]$9872 \logical_op__imm_data__data$4
+ assign $1\logical_op__imm_data__ok$5$next[0:0]$9873 \logical_op__imm_data__ok$5
+ assign $1\logical_op__input_carry$12$next[1:0]$9874 \logical_op__input_carry$12
+ assign $1\logical_op__insn$19$next[31:0]$9875 \logical_op__insn$19
+ assign $1\logical_op__insn_type$2$next[6:0]$9876 \logical_op__insn_type$2
+ assign $1\logical_op__invert_in$10$next[0:0]$9877 \logical_op__invert_in$10
+ assign $1\logical_op__invert_out$13$next[0:0]$9878 \logical_op__invert_out$13
+ assign $1\logical_op__is_32bit$16$next[0:0]$9879 \logical_op__is_32bit$16
+ assign $1\logical_op__is_signed$17$next[0:0]$9880 \logical_op__is_signed$17
+ assign $1\logical_op__oe__oe$8$next[0:0]$9881 \logical_op__oe__oe$8
+ assign $1\logical_op__oe__ok$9$next[0:0]$9882 \logical_op__oe__ok$9
+ assign $1\logical_op__output_carry$15$next[0:0]$9883 \logical_op__output_carry$15
+ assign $1\logical_op__rc__ok$7$next[0:0]$9884 \logical_op__rc__ok$7
+ assign $1\logical_op__rc__rc$6$next[0:0]$9885 \logical_op__rc__rc$6
+ assign $1\logical_op__write_cr0$14$next[0:0]$9886 \logical_op__write_cr0$14
+ assign $1\logical_op__zero_a$11$next[0:0]$9887 \logical_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$4$next[63:0]$9940 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$5$next[0:0]$9941 1'0
- assign $2\logical_op__rc__rc$6$next[0:0]$9945 1'0
- assign $2\logical_op__rc__ok$7$next[0:0]$9944 1'0
- assign $2\logical_op__oe__oe$8$next[0:0]$9942 1'0
- assign $2\logical_op__oe__ok$9$next[0:0]$9943 1'0
+ assign $2\logical_op__imm_data__data$4$next[63:0]$9888 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 1'0
+ assign $2\logical_op__rc__rc$6$next[0:0]$9893 1'0
+ assign $2\logical_op__rc__ok$7$next[0:0]$9892 1'0
+ assign $2\logical_op__oe__oe$8$next[0:0]$9890 1'0
+ assign $2\logical_op__oe__ok$9$next[0:0]$9891 1'0
case
- assign $2\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__imm_data__data$4$next[63:0]$9924
- assign $2\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__ok$5$next[0:0]$9925
- assign $2\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__oe__oe$8$next[0:0]$9933
- assign $2\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__ok$9$next[0:0]$9934
- assign $2\logical_op__rc__ok$7$next[0:0]$9944 $1\logical_op__rc__ok$7$next[0:0]$9936
- assign $2\logical_op__rc__rc$6$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9937
+ assign $2\logical_op__imm_data__data$4$next[63:0]$9888 $1\logical_op__imm_data__data$4$next[63:0]$9872
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 $1\logical_op__imm_data__ok$5$next[0:0]$9873
+ assign $2\logical_op__oe__oe$8$next[0:0]$9890 $1\logical_op__oe__oe$8$next[0:0]$9881
+ assign $2\logical_op__oe__ok$9$next[0:0]$9891 $1\logical_op__oe__ok$9$next[0:0]$9882
+ assign $2\logical_op__rc__ok$7$next[0:0]$9892 $1\logical_op__rc__ok$7$next[0:0]$9884
+ assign $2\logical_op__rc__rc$6$next[0:0]$9893 $1\logical_op__rc__rc$6$next[0:0]$9885
end
sync always
- update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9904
- update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9905
- update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9906
- update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9907
- update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9908
- update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9909
- update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9910
- update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9911
- update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9912
- update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9913
- update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9914
- update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9915
- update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9916
- update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9917
- update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9918
- update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9919
- update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9920
- update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9921
+ update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9852
+ update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9853
+ update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9854
+ update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9855
+ update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9856
+ update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9857
+ update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9858
+ update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9859
+ update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9860
+ update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9861
+ update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9862
+ update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9863
+ update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9864
+ update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9865
+ update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9866
+ update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9867
+ update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9868
+ update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9869
end
- connect \$74 $and$libresoc.v:173753$9823_Y
+ connect \$74 $and$libresoc.v:173417$9771_Y
connect \cr_a$68 4'0000
connect \cr_a_ok$69 1'0
connect \xer_so_ok$72 1'0
connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \output_stage_muxid \muxid
end
-attribute \src "libresoc.v:174109.1-175096.10"
+attribute \src "libresoc.v:173773.1-174760.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0"
attribute \generator "nMigen"
module \pipe_middle_0
- attribute \src "libresoc.v:175021.3-175035.6"
- wire $0\div_by_zero$54$next[0:0]$10174
- attribute \src "libresoc.v:174695.3-174696.47"
- wire $0\div_by_zero$54[0:0]$10009
- attribute \src "libresoc.v:174132.7-174132.30"
- wire $0\div_by_zero$54[0:0]$10191
- attribute \src "libresoc.v:174817.3-174828.6"
+ attribute \src "libresoc.v:174685.3-174699.6"
+ wire $0\div_by_zero$54$next[0:0]$10122
+ attribute \src "libresoc.v:173796.7-173796.30"
+ wire $0\div_by_zero$54[0:0]$10139
+ attribute \src "libresoc.v:174359.3-174360.47"
+ wire $0\div_by_zero$54[0:0]$9957
+ attribute \src "libresoc.v:174481.3-174492.6"
wire width 64 $0\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:174805.3-174816.6"
+ attribute \src "libresoc.v:174469.3-174480.6"
wire width 128 $0\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:174793.3-174804.6"
+ attribute \src "libresoc.v:174457.3-174468.6"
wire width 7 $0\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:174991.3-175005.6"
- wire $0\dive_abs_ov32$52$next[0:0]$10166
- attribute \src "libresoc.v:174699.3-174700.51"
- wire $0\dive_abs_ov32$52[0:0]$10013
- attribute \src "libresoc.v:174156.7-174156.32"
- wire $0\dive_abs_ov32$52[0:0]$10193
- attribute \src "libresoc.v:175006.3-175020.6"
- wire $0\dive_abs_ov64$53$next[0:0]$10170
- attribute \src "libresoc.v:174697.3-174698.51"
- wire $0\dive_abs_ov64$53[0:0]$10011
- attribute \src "libresoc.v:174164.7-174164.32"
- wire $0\dive_abs_ov64$53[0:0]$10195
- attribute \src "libresoc.v:175036.3-175050.6"
- wire width 128 $0\dividend$68$next[127:0]$10178
- attribute \src "libresoc.v:174693.3-174694.41"
- wire width 128 $0\dividend$68[127:0]$10007
- attribute \src "libresoc.v:174170.15-174170.68"
- wire width 128 $0\dividend$68[127:0]$10197
- attribute \src "libresoc.v:174976.3-174990.6"
- wire $0\dividend_neg$51$next[0:0]$10162
- attribute \src "libresoc.v:174701.3-174702.49"
- wire $0\dividend_neg$51[0:0]$10015
- attribute \src "libresoc.v:174178.7-174178.31"
- wire $0\dividend_neg$51[0:0]$10199
- attribute \src "libresoc.v:174961.3-174975.6"
- wire $0\divisor_neg$50$next[0:0]$10158
- attribute \src "libresoc.v:174703.3-174704.47"
- wire $0\divisor_neg$50[0:0]$10017
- attribute \src "libresoc.v:174186.7-174186.30"
- wire $0\divisor_neg$50[0:0]$10201
- attribute \src "libresoc.v:175051.3-175065.6"
- wire width 64 $0\divisor_radicand$65$next[63:0]$10182
- attribute \src "libresoc.v:174691.3-174692.57"
- wire width 64 $0\divisor_radicand$65[63:0]$10005
- attribute \src "libresoc.v:174192.14-174192.58"
- wire width 64 $0\divisor_radicand$65[63:0]$10203
- attribute \src "libresoc.v:174829.3-174856.6"
- wire $0\empty$next[0:0]$10075
- attribute \src "libresoc.v:174749.3-174750.27"
+ attribute \src "libresoc.v:174655.3-174669.6"
+ wire $0\dive_abs_ov32$52$next[0:0]$10114
+ attribute \src "libresoc.v:173820.7-173820.32"
+ wire $0\dive_abs_ov32$52[0:0]$10141
+ attribute \src "libresoc.v:174363.3-174364.51"
+ wire $0\dive_abs_ov32$52[0:0]$9961
+ attribute \src "libresoc.v:174670.3-174684.6"
+ wire $0\dive_abs_ov64$53$next[0:0]$10118
+ attribute \src "libresoc.v:173828.7-173828.32"
+ wire $0\dive_abs_ov64$53[0:0]$10143
+ attribute \src "libresoc.v:174361.3-174362.51"
+ wire $0\dive_abs_ov64$53[0:0]$9959
+ attribute \src "libresoc.v:174700.3-174714.6"
+ wire width 128 $0\dividend$68$next[127:0]$10126
+ attribute \src "libresoc.v:173834.15-173834.68"
+ wire width 128 $0\dividend$68[127:0]$10145
+ attribute \src "libresoc.v:174357.3-174358.41"
+ wire width 128 $0\dividend$68[127:0]$9955
+ attribute \src "libresoc.v:174640.3-174654.6"
+ wire $0\dividend_neg$51$next[0:0]$10110
+ attribute \src "libresoc.v:173842.7-173842.31"
+ wire $0\dividend_neg$51[0:0]$10147
+ attribute \src "libresoc.v:174365.3-174366.49"
+ wire $0\dividend_neg$51[0:0]$9963
+ attribute \src "libresoc.v:174625.3-174639.6"
+ wire $0\divisor_neg$50$next[0:0]$10106
+ attribute \src "libresoc.v:173850.7-173850.30"
+ wire $0\divisor_neg$50[0:0]$10149
+ attribute \src "libresoc.v:174367.3-174368.47"
+ wire $0\divisor_neg$50[0:0]$9965
+ attribute \src "libresoc.v:174715.3-174729.6"
+ wire width 64 $0\divisor_radicand$65$next[63:0]$10130
+ attribute \src "libresoc.v:173856.14-173856.58"
+ wire width 64 $0\divisor_radicand$65[63:0]$10151
+ attribute \src "libresoc.v:174355.3-174356.57"
+ wire width 64 $0\divisor_radicand$65[63:0]$9953
+ attribute \src "libresoc.v:174493.3-174520.6"
+ wire $0\empty$next[0:0]$10023
+ attribute \src "libresoc.v:174413.3-174414.27"
wire $0\empty[0:0]
- attribute \src "libresoc.v:174110.7-174110.20"
+ attribute \src "libresoc.v:173774.7-173774.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 4 $0\logical_op__data_len$45$next[3:0]$10085
- attribute \src "libresoc.v:174743.3-174744.65"
- wire width 4 $0\logical_op__data_len$45[3:0]$10057
- attribute \src "libresoc.v:174204.13-174204.45"
- wire width 4 $0\logical_op__data_len$45[3:0]$10206
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10086
- attribute \src "libresoc.v:174713.3-174714.63"
- wire width 14 $0\logical_op__fn_unit$30[13:0]$10027
- attribute \src "libresoc.v:174257.14-174257.49"
- wire width 14 $0\logical_op__fn_unit$30[13:0]$10208
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10087
- attribute \src "libresoc.v:174715.3-174716.77"
- wire width 64 $0\logical_op__imm_data__data$31[63:0]$10029
- attribute \src "libresoc.v:174263.14-174263.68"
- wire width 64 $0\logical_op__imm_data__data$31[63:0]$10210
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__imm_data__ok$32$next[0:0]$10088
- attribute \src "libresoc.v:174717.3-174718.73"
- wire $0\logical_op__imm_data__ok$32[0:0]$10031
- attribute \src "libresoc.v:174271.7-174271.43"
- wire $0\logical_op__imm_data__ok$32[0:0]$10212
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 2 $0\logical_op__input_carry$39$next[1:0]$10089
- attribute \src "libresoc.v:174731.3-174732.71"
- wire width 2 $0\logical_op__input_carry$39[1:0]$10045
- attribute \src "libresoc.v:174293.13-174293.48"
- wire width 2 $0\logical_op__input_carry$39[1:0]$10214
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 32 $0\logical_op__insn$46$next[31:0]$10090
- attribute \src "libresoc.v:174745.3-174746.57"
- wire width 32 $0\logical_op__insn$46[31:0]$10059
- attribute \src "libresoc.v:174301.14-174301.43"
- wire width 32 $0\logical_op__insn$46[31:0]$10216
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 7 $0\logical_op__insn_type$29$next[6:0]$10091
- attribute \src "libresoc.v:174711.3-174712.67"
- wire width 7 $0\logical_op__insn_type$29[6:0]$10025
- attribute \src "libresoc.v:174534.13-174534.47"
- wire width 7 $0\logical_op__insn_type$29[6:0]$10218
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__invert_in$37$next[0:0]$10092
- attribute \src "libresoc.v:174727.3-174728.67"
- wire $0\logical_op__invert_in$37[0:0]$10041
- attribute \src "libresoc.v:174542.7-174542.40"
- wire $0\logical_op__invert_in$37[0:0]$10220
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__invert_out$40$next[0:0]$10093
- attribute \src "libresoc.v:174733.3-174734.69"
- wire $0\logical_op__invert_out$40[0:0]$10047
- attribute \src "libresoc.v:174550.7-174550.41"
- wire $0\logical_op__invert_out$40[0:0]$10222
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__is_32bit$43$next[0:0]$10094
- attribute \src "libresoc.v:174739.3-174740.65"
- wire $0\logical_op__is_32bit$43[0:0]$10053
- attribute \src "libresoc.v:174558.7-174558.39"
- wire $0\logical_op__is_32bit$43[0:0]$10224
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__is_signed$44$next[0:0]$10095
- attribute \src "libresoc.v:174741.3-174742.67"
- wire $0\logical_op__is_signed$44[0:0]$10055
- attribute \src "libresoc.v:174566.7-174566.40"
- wire $0\logical_op__is_signed$44[0:0]$10226
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__oe__oe$35$next[0:0]$10096
- attribute \src "libresoc.v:174723.3-174724.61"
- wire $0\logical_op__oe__oe$35[0:0]$10037
- attribute \src "libresoc.v:174572.7-174572.37"
- wire $0\logical_op__oe__oe$35[0:0]$10228
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__oe__ok$36$next[0:0]$10097
- attribute \src "libresoc.v:174725.3-174726.61"
- wire $0\logical_op__oe__ok$36[0:0]$10039
- attribute \src "libresoc.v:174580.7-174580.37"
- wire $0\logical_op__oe__ok$36[0:0]$10230
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__output_carry$42$next[0:0]$10098
- attribute \src "libresoc.v:174737.3-174738.73"
- wire $0\logical_op__output_carry$42[0:0]$10051
- attribute \src "libresoc.v:174590.7-174590.43"
- wire $0\logical_op__output_carry$42[0:0]$10232
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__rc__ok$34$next[0:0]$10099
- attribute \src "libresoc.v:174721.3-174722.61"
- wire $0\logical_op__rc__ok$34[0:0]$10035
- attribute \src "libresoc.v:174596.7-174596.37"
- wire $0\logical_op__rc__ok$34[0:0]$10234
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__rc__rc$33$next[0:0]$10100
- attribute \src "libresoc.v:174719.3-174720.61"
- wire $0\logical_op__rc__rc$33[0:0]$10033
- attribute \src "libresoc.v:174604.7-174604.37"
- wire $0\logical_op__rc__rc$33[0:0]$10236
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__write_cr0$41$next[0:0]$10101
- attribute \src "libresoc.v:174735.3-174736.67"
- wire $0\logical_op__write_cr0$41[0:0]$10049
- attribute \src "libresoc.v:174614.7-174614.40"
- wire $0\logical_op__write_cr0$41[0:0]$10238
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $0\logical_op__zero_a$38$next[0:0]$10102
- attribute \src "libresoc.v:174729.3-174730.61"
- wire $0\logical_op__zero_a$38[0:0]$10043
- attribute \src "libresoc.v:174622.7-174622.37"
- wire $0\logical_op__zero_a$38[0:0]$10240
- attribute \src "libresoc.v:174857.3-174871.6"
- wire width 2 $0\muxid$28$next[1:0]$10081
- attribute \src "libresoc.v:174747.3-174748.35"
- wire width 2 $0\muxid$28[1:0]$10061
- attribute \src "libresoc.v:174630.13-174630.30"
- wire width 2 $0\muxid$28[1:0]$10242
- attribute \src "libresoc.v:175066.3-175080.6"
- wire width 2 $0\operation$69$next[1:0]$10186
- attribute \src "libresoc.v:174689.3-174690.43"
- wire width 2 $0\operation$69[1:0]$10003
- attribute \src "libresoc.v:174640.13-174640.34"
- wire width 2 $0\operation$69[1:0]$10244
- attribute \src "libresoc.v:174916.3-174930.6"
- wire width 64 $0\ra$47$next[63:0]$10146
- attribute \src "libresoc.v:174709.3-174710.29"
- wire width 64 $0\ra$47[63:0]$10023
- attribute \src "libresoc.v:174654.14-174654.44"
- wire width 64 $0\ra$47[63:0]$10246
- attribute \src "libresoc.v:174931.3-174945.6"
- wire width 64 $0\rb$48$next[63:0]$10150
- attribute \src "libresoc.v:174707.3-174708.29"
- wire width 64 $0\rb$48[63:0]$10021
- attribute \src "libresoc.v:174662.14-174662.44"
- wire width 64 $0\rb$48[63:0]$10248
- attribute \src "libresoc.v:174784.3-174792.6"
- wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10069
- attribute \src "libresoc.v:174751.3-174752.75"
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 4 $0\logical_op__data_len$45$next[3:0]$10033
+ attribute \src "libresoc.v:174407.3-174408.65"
+ wire width 4 $0\logical_op__data_len$45[3:0]$10005
+ attribute \src "libresoc.v:173868.13-173868.45"
+ wire width 4 $0\logical_op__data_len$45[3:0]$10154
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10034
+ attribute \src "libresoc.v:173921.14-173921.49"
+ wire width 14 $0\logical_op__fn_unit$30[13:0]$10156
+ attribute \src "libresoc.v:174377.3-174378.63"
+ wire width 14 $0\logical_op__fn_unit$30[13:0]$9975
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10035
+ attribute \src "libresoc.v:173927.14-173927.68"
+ wire width 64 $0\logical_op__imm_data__data$31[63:0]$10158
+ attribute \src "libresoc.v:174379.3-174380.77"
+ wire width 64 $0\logical_op__imm_data__data$31[63:0]$9977
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__imm_data__ok$32$next[0:0]$10036
+ attribute \src "libresoc.v:173935.7-173935.43"
+ wire $0\logical_op__imm_data__ok$32[0:0]$10160
+ attribute \src "libresoc.v:174381.3-174382.73"
+ wire $0\logical_op__imm_data__ok$32[0:0]$9979
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 2 $0\logical_op__input_carry$39$next[1:0]$10037
+ attribute \src "libresoc.v:173957.13-173957.48"
+ wire width 2 $0\logical_op__input_carry$39[1:0]$10162
+ attribute \src "libresoc.v:174395.3-174396.71"
+ wire width 2 $0\logical_op__input_carry$39[1:0]$9993
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 32 $0\logical_op__insn$46$next[31:0]$10038
+ attribute \src "libresoc.v:174409.3-174410.57"
+ wire width 32 $0\logical_op__insn$46[31:0]$10007
+ attribute \src "libresoc.v:173965.14-173965.43"
+ wire width 32 $0\logical_op__insn$46[31:0]$10164
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 7 $0\logical_op__insn_type$29$next[6:0]$10039
+ attribute \src "libresoc.v:174198.13-174198.47"
+ wire width 7 $0\logical_op__insn_type$29[6:0]$10166
+ attribute \src "libresoc.v:174375.3-174376.67"
+ wire width 7 $0\logical_op__insn_type$29[6:0]$9973
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__invert_in$37$next[0:0]$10040
+ attribute \src "libresoc.v:174206.7-174206.40"
+ wire $0\logical_op__invert_in$37[0:0]$10168
+ attribute \src "libresoc.v:174391.3-174392.67"
+ wire $0\logical_op__invert_in$37[0:0]$9989
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__invert_out$40$next[0:0]$10041
+ attribute \src "libresoc.v:174214.7-174214.41"
+ wire $0\logical_op__invert_out$40[0:0]$10170
+ attribute \src "libresoc.v:174397.3-174398.69"
+ wire $0\logical_op__invert_out$40[0:0]$9995
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__is_32bit$43$next[0:0]$10042
+ attribute \src "libresoc.v:174403.3-174404.65"
+ wire $0\logical_op__is_32bit$43[0:0]$10001
+ attribute \src "libresoc.v:174222.7-174222.39"
+ wire $0\logical_op__is_32bit$43[0:0]$10172
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__is_signed$44$next[0:0]$10043
+ attribute \src "libresoc.v:174405.3-174406.67"
+ wire $0\logical_op__is_signed$44[0:0]$10003
+ attribute \src "libresoc.v:174230.7-174230.40"
+ wire $0\logical_op__is_signed$44[0:0]$10174
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__oe__oe$35$next[0:0]$10044
+ attribute \src "libresoc.v:174236.7-174236.37"
+ wire $0\logical_op__oe__oe$35[0:0]$10176
+ attribute \src "libresoc.v:174387.3-174388.61"
+ wire $0\logical_op__oe__oe$35[0:0]$9985
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__oe__ok$36$next[0:0]$10045
+ attribute \src "libresoc.v:174244.7-174244.37"
+ wire $0\logical_op__oe__ok$36[0:0]$10178
+ attribute \src "libresoc.v:174389.3-174390.61"
+ wire $0\logical_op__oe__ok$36[0:0]$9987
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__output_carry$42$next[0:0]$10046
+ attribute \src "libresoc.v:174254.7-174254.43"
+ wire $0\logical_op__output_carry$42[0:0]$10180
+ attribute \src "libresoc.v:174401.3-174402.73"
+ wire $0\logical_op__output_carry$42[0:0]$9999
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__rc__ok$34$next[0:0]$10047
+ attribute \src "libresoc.v:174260.7-174260.37"
+ wire $0\logical_op__rc__ok$34[0:0]$10182
+ attribute \src "libresoc.v:174385.3-174386.61"
+ wire $0\logical_op__rc__ok$34[0:0]$9983
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__rc__rc$33$next[0:0]$10048
+ attribute \src "libresoc.v:174268.7-174268.37"
+ wire $0\logical_op__rc__rc$33[0:0]$10184
+ attribute \src "libresoc.v:174383.3-174384.61"
+ wire $0\logical_op__rc__rc$33[0:0]$9981
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__write_cr0$41$next[0:0]$10049
+ attribute \src "libresoc.v:174278.7-174278.40"
+ wire $0\logical_op__write_cr0$41[0:0]$10186
+ attribute \src "libresoc.v:174399.3-174400.67"
+ wire $0\logical_op__write_cr0$41[0:0]$9997
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $0\logical_op__zero_a$38$next[0:0]$10050
+ attribute \src "libresoc.v:174286.7-174286.37"
+ wire $0\logical_op__zero_a$38[0:0]$10188
+ attribute \src "libresoc.v:174393.3-174394.61"
+ wire $0\logical_op__zero_a$38[0:0]$9991
+ attribute \src "libresoc.v:174521.3-174535.6"
+ wire width 2 $0\muxid$28$next[1:0]$10029
+ attribute \src "libresoc.v:174411.3-174412.35"
+ wire width 2 $0\muxid$28[1:0]$10009
+ attribute \src "libresoc.v:174294.13-174294.30"
+ wire width 2 $0\muxid$28[1:0]$10190
+ attribute \src "libresoc.v:174730.3-174744.6"
+ wire width 2 $0\operation$69$next[1:0]$10134
+ attribute \src "libresoc.v:174304.13-174304.34"
+ wire width 2 $0\operation$69[1:0]$10192
+ attribute \src "libresoc.v:174353.3-174354.43"
+ wire width 2 $0\operation$69[1:0]$9951
+ attribute \src "libresoc.v:174580.3-174594.6"
+ wire width 64 $0\ra$47$next[63:0]$10094
+ attribute \src "libresoc.v:174318.14-174318.44"
+ wire width 64 $0\ra$47[63:0]$10194
+ attribute \src "libresoc.v:174373.3-174374.29"
+ wire width 64 $0\ra$47[63:0]$9971
+ attribute \src "libresoc.v:174595.3-174609.6"
+ wire width 64 $0\rb$48$next[63:0]$10098
+ attribute \src "libresoc.v:174326.14-174326.44"
+ wire width 64 $0\rb$48[63:0]$10196
+ attribute \src "libresoc.v:174371.3-174372.29"
+ wire width 64 $0\rb$48[63:0]$9969
+ attribute \src "libresoc.v:174448.3-174456.6"
+ wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10017
+ attribute \src "libresoc.v:174415.3-174416.75"
wire width 128 $0\saved_state_dividend_quotient[127:0]
- attribute \src "libresoc.v:174775.3-174783.6"
- wire width 7 $0\saved_state_q_bits_known$next[6:0]$10066
- attribute \src "libresoc.v:174753.3-174754.65"
+ attribute \src "libresoc.v:174439.3-174447.6"
+ wire width 7 $0\saved_state_q_bits_known$next[6:0]$10014
+ attribute \src "libresoc.v:174417.3-174418.65"
wire width 7 $0\saved_state_q_bits_known[6:0]
- attribute \src "libresoc.v:174946.3-174960.6"
- wire $0\xer_so$49$next[0:0]$10154
- attribute \src "libresoc.v:174705.3-174706.37"
- wire $0\xer_so$49[0:0]$10019
- attribute \src "libresoc.v:174680.7-174680.25"
- wire $0\xer_so$49[0:0]$10252
- attribute \src "libresoc.v:175021.3-175035.6"
- wire $1\div_by_zero$54$next[0:0]$10175
- attribute \src "libresoc.v:174817.3-174828.6"
+ attribute \src "libresoc.v:174610.3-174624.6"
+ wire $0\xer_so$49$next[0:0]$10102
+ attribute \src "libresoc.v:174344.7-174344.25"
+ wire $0\xer_so$49[0:0]$10200
+ attribute \src "libresoc.v:174369.3-174370.37"
+ wire $0\xer_so$49[0:0]$9967
+ attribute \src "libresoc.v:174685.3-174699.6"
+ wire $1\div_by_zero$54$next[0:0]$10123
+ attribute \src "libresoc.v:174481.3-174492.6"
wire width 64 $1\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:174805.3-174816.6"
+ attribute \src "libresoc.v:174469.3-174480.6"
wire width 128 $1\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:174793.3-174804.6"
+ attribute \src "libresoc.v:174457.3-174468.6"
wire width 7 $1\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:174991.3-175005.6"
- wire $1\dive_abs_ov32$52$next[0:0]$10167
- attribute \src "libresoc.v:175006.3-175020.6"
- wire $1\dive_abs_ov64$53$next[0:0]$10171
- attribute \src "libresoc.v:175036.3-175050.6"
- wire width 128 $1\dividend$68$next[127:0]$10179
- attribute \src "libresoc.v:174976.3-174990.6"
- wire $1\dividend_neg$51$next[0:0]$10163
- attribute \src "libresoc.v:174961.3-174975.6"
- wire $1\divisor_neg$50$next[0:0]$10159
- attribute \src "libresoc.v:175051.3-175065.6"
- wire width 64 $1\divisor_radicand$65$next[63:0]$10183
- attribute \src "libresoc.v:174829.3-174856.6"
- wire $1\empty$next[0:0]$10076
- attribute \src "libresoc.v:174196.7-174196.19"
+ attribute \src "libresoc.v:174655.3-174669.6"
+ wire $1\dive_abs_ov32$52$next[0:0]$10115
+ attribute \src "libresoc.v:174670.3-174684.6"
+ wire $1\dive_abs_ov64$53$next[0:0]$10119
+ attribute \src "libresoc.v:174700.3-174714.6"
+ wire width 128 $1\dividend$68$next[127:0]$10127
+ attribute \src "libresoc.v:174640.3-174654.6"
+ wire $1\dividend_neg$51$next[0:0]$10111
+ attribute \src "libresoc.v:174625.3-174639.6"
+ wire $1\divisor_neg$50$next[0:0]$10107
+ attribute \src "libresoc.v:174715.3-174729.6"
+ wire width 64 $1\divisor_radicand$65$next[63:0]$10131
+ attribute \src "libresoc.v:174493.3-174520.6"
+ wire $1\empty$next[0:0]$10024
+ attribute \src "libresoc.v:173860.7-173860.19"
wire $1\empty[0:0]
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 4 $1\logical_op__data_len$45$next[3:0]$10103
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10104
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10105
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__imm_data__ok$32$next[0:0]$10106
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 2 $1\logical_op__input_carry$39$next[1:0]$10107
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 32 $1\logical_op__insn$46$next[31:0]$10108
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 7 $1\logical_op__insn_type$29$next[6:0]$10109
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__invert_in$37$next[0:0]$10110
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__invert_out$40$next[0:0]$10111
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__is_32bit$43$next[0:0]$10112
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__is_signed$44$next[0:0]$10113
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__oe__oe$35$next[0:0]$10114
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__oe__ok$36$next[0:0]$10115
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__output_carry$42$next[0:0]$10116
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__rc__ok$34$next[0:0]$10117
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__rc__rc$33$next[0:0]$10118
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__write_cr0$41$next[0:0]$10119
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $1\logical_op__zero_a$38$next[0:0]$10120
- attribute \src "libresoc.v:174857.3-174871.6"
- wire width 2 $1\muxid$28$next[1:0]$10082
- attribute \src "libresoc.v:175066.3-175080.6"
- wire width 2 $1\operation$69$next[1:0]$10187
- attribute \src "libresoc.v:174916.3-174930.6"
- wire width 64 $1\ra$47$next[63:0]$10147
- attribute \src "libresoc.v:174931.3-174945.6"
- wire width 64 $1\rb$48$next[63:0]$10151
- attribute \src "libresoc.v:174784.3-174792.6"
- wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10070
- attribute \src "libresoc.v:174668.15-174668.84"
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 4 $1\logical_op__data_len$45$next[3:0]$10051
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10052
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10053
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__imm_data__ok$32$next[0:0]$10054
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 2 $1\logical_op__input_carry$39$next[1:0]$10055
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 32 $1\logical_op__insn$46$next[31:0]$10056
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 7 $1\logical_op__insn_type$29$next[6:0]$10057
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__invert_in$37$next[0:0]$10058
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__invert_out$40$next[0:0]$10059
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__is_32bit$43$next[0:0]$10060
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__is_signed$44$next[0:0]$10061
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__oe__oe$35$next[0:0]$10062
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__oe__ok$36$next[0:0]$10063
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__output_carry$42$next[0:0]$10064
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__rc__ok$34$next[0:0]$10065
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__rc__rc$33$next[0:0]$10066
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__write_cr0$41$next[0:0]$10067
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $1\logical_op__zero_a$38$next[0:0]$10068
+ attribute \src "libresoc.v:174521.3-174535.6"
+ wire width 2 $1\muxid$28$next[1:0]$10030
+ attribute \src "libresoc.v:174730.3-174744.6"
+ wire width 2 $1\operation$69$next[1:0]$10135
+ attribute \src "libresoc.v:174580.3-174594.6"
+ wire width 64 $1\ra$47$next[63:0]$10095
+ attribute \src "libresoc.v:174595.3-174609.6"
+ wire width 64 $1\rb$48$next[63:0]$10099
+ attribute \src "libresoc.v:174448.3-174456.6"
+ wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10018
+ attribute \src "libresoc.v:174332.15-174332.84"
wire width 128 $1\saved_state_dividend_quotient[127:0]
- attribute \src "libresoc.v:174775.3-174783.6"
- wire width 7 $1\saved_state_q_bits_known$next[6:0]$10067
- attribute \src "libresoc.v:174672.13-174672.45"
+ attribute \src "libresoc.v:174439.3-174447.6"
+ wire width 7 $1\saved_state_q_bits_known$next[6:0]$10015
+ attribute \src "libresoc.v:174336.13-174336.45"
wire width 7 $1\saved_state_q_bits_known[6:0]
- attribute \src "libresoc.v:174946.3-174960.6"
- wire $1\xer_so$49$next[0:0]$10155
- attribute \src "libresoc.v:175021.3-175035.6"
- wire $2\div_by_zero$54$next[0:0]$10176
- attribute \src "libresoc.v:174991.3-175005.6"
- wire $2\dive_abs_ov32$52$next[0:0]$10168
- attribute \src "libresoc.v:175006.3-175020.6"
- wire $2\dive_abs_ov64$53$next[0:0]$10172
- attribute \src "libresoc.v:175036.3-175050.6"
- wire width 128 $2\dividend$68$next[127:0]$10180
- attribute \src "libresoc.v:174976.3-174990.6"
- wire $2\dividend_neg$51$next[0:0]$10164
- attribute \src "libresoc.v:174961.3-174975.6"
- wire $2\divisor_neg$50$next[0:0]$10160
- attribute \src "libresoc.v:175051.3-175065.6"
- wire width 64 $2\divisor_radicand$65$next[63:0]$10184
- attribute \src "libresoc.v:174829.3-174856.6"
- wire $2\empty$next[0:0]$10077
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 4 $2\logical_op__data_len$45$next[3:0]$10121
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10122
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10123
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__imm_data__ok$32$next[0:0]$10124
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 2 $2\logical_op__input_carry$39$next[1:0]$10125
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 32 $2\logical_op__insn$46$next[31:0]$10126
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 7 $2\logical_op__insn_type$29$next[6:0]$10127
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__invert_in$37$next[0:0]$10128
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__invert_out$40$next[0:0]$10129
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__is_32bit$43$next[0:0]$10130
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__is_signed$44$next[0:0]$10131
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__oe__oe$35$next[0:0]$10132
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__oe__ok$36$next[0:0]$10133
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__output_carry$42$next[0:0]$10134
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__rc__ok$34$next[0:0]$10135
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__rc__rc$33$next[0:0]$10136
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__write_cr0$41$next[0:0]$10137
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $2\logical_op__zero_a$38$next[0:0]$10138
- attribute \src "libresoc.v:174857.3-174871.6"
- wire width 2 $2\muxid$28$next[1:0]$10083
- attribute \src "libresoc.v:175066.3-175080.6"
- wire width 2 $2\operation$69$next[1:0]$10188
- attribute \src "libresoc.v:174916.3-174930.6"
- wire width 64 $2\ra$47$next[63:0]$10148
- attribute \src "libresoc.v:174931.3-174945.6"
- wire width 64 $2\rb$48$next[63:0]$10152
- attribute \src "libresoc.v:174946.3-174960.6"
- wire $2\xer_so$49$next[0:0]$10156
- attribute \src "libresoc.v:174829.3-174856.6"
- wire $3\empty$next[0:0]$10078
- attribute \src "libresoc.v:174872.3-174915.6"
- wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10139
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $3\logical_op__imm_data__ok$32$next[0:0]$10140
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $3\logical_op__oe__oe$35$next[0:0]$10141
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $3\logical_op__oe__ok$36$next[0:0]$10142
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $3\logical_op__rc__ok$34$next[0:0]$10143
- attribute \src "libresoc.v:174872.3-174915.6"
- wire $3\logical_op__rc__rc$33$next[0:0]$10144
- attribute \src "libresoc.v:174829.3-174856.6"
- wire $4\empty$next[0:0]$10079
- attribute \src "libresoc.v:174687.18-174687.98"
- wire $and$libresoc.v:174687$10000_Y
- attribute \src "libresoc.v:174688.18-174688.107"
- wire $and$libresoc.v:174688$10001_Y
- attribute \src "libresoc.v:174684.18-174684.92"
- wire width 192 $extend$libresoc.v:174684$9996_Y
- attribute \src "libresoc.v:174686.18-174686.119"
- wire $ge$libresoc.v:174686$9999_Y
- attribute \src "libresoc.v:174685.18-174685.93"
- wire $not$libresoc.v:174685$9998_Y
- attribute \src "libresoc.v:174684.18-174684.92"
- wire width 192 $pos$libresoc.v:174684$9997_Y
- attribute \src "libresoc.v:174683.18-174683.138"
- wire width 191 $sshl$libresoc.v:174683$9995_Y
+ attribute \src "libresoc.v:174610.3-174624.6"
+ wire $1\xer_so$49$next[0:0]$10103
+ attribute \src "libresoc.v:174685.3-174699.6"
+ wire $2\div_by_zero$54$next[0:0]$10124
+ attribute \src "libresoc.v:174655.3-174669.6"
+ wire $2\dive_abs_ov32$52$next[0:0]$10116
+ attribute \src "libresoc.v:174670.3-174684.6"
+ wire $2\dive_abs_ov64$53$next[0:0]$10120
+ attribute \src "libresoc.v:174700.3-174714.6"
+ wire width 128 $2\dividend$68$next[127:0]$10128
+ attribute \src "libresoc.v:174640.3-174654.6"
+ wire $2\dividend_neg$51$next[0:0]$10112
+ attribute \src "libresoc.v:174625.3-174639.6"
+ wire $2\divisor_neg$50$next[0:0]$10108
+ attribute \src "libresoc.v:174715.3-174729.6"
+ wire width 64 $2\divisor_radicand$65$next[63:0]$10132
+ attribute \src "libresoc.v:174493.3-174520.6"
+ wire $2\empty$next[0:0]$10025
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 4 $2\logical_op__data_len$45$next[3:0]$10069
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10070
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10071
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__imm_data__ok$32$next[0:0]$10072
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 2 $2\logical_op__input_carry$39$next[1:0]$10073
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 32 $2\logical_op__insn$46$next[31:0]$10074
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 7 $2\logical_op__insn_type$29$next[6:0]$10075
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__invert_in$37$next[0:0]$10076
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__invert_out$40$next[0:0]$10077
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__is_32bit$43$next[0:0]$10078
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__is_signed$44$next[0:0]$10079
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__oe__oe$35$next[0:0]$10080
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__oe__ok$36$next[0:0]$10081
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__output_carry$42$next[0:0]$10082
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__rc__ok$34$next[0:0]$10083
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__rc__rc$33$next[0:0]$10084
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__write_cr0$41$next[0:0]$10085
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $2\logical_op__zero_a$38$next[0:0]$10086
+ attribute \src "libresoc.v:174521.3-174535.6"
+ wire width 2 $2\muxid$28$next[1:0]$10031
+ attribute \src "libresoc.v:174730.3-174744.6"
+ wire width 2 $2\operation$69$next[1:0]$10136
+ attribute \src "libresoc.v:174580.3-174594.6"
+ wire width 64 $2\ra$47$next[63:0]$10096
+ attribute \src "libresoc.v:174595.3-174609.6"
+ wire width 64 $2\rb$48$next[63:0]$10100
+ attribute \src "libresoc.v:174610.3-174624.6"
+ wire $2\xer_so$49$next[0:0]$10104
+ attribute \src "libresoc.v:174493.3-174520.6"
+ wire $3\empty$next[0:0]$10026
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10087
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $3\logical_op__imm_data__ok$32$next[0:0]$10088
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $3\logical_op__oe__oe$35$next[0:0]$10089
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $3\logical_op__oe__ok$36$next[0:0]$10090
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $3\logical_op__rc__ok$34$next[0:0]$10091
+ attribute \src "libresoc.v:174536.3-174579.6"
+ wire $3\logical_op__rc__rc$33$next[0:0]$10092
+ attribute \src "libresoc.v:174493.3-174520.6"
+ wire $4\empty$next[0:0]$10027
+ attribute \src "libresoc.v:174351.18-174351.98"
+ wire $and$libresoc.v:174351$9948_Y
+ attribute \src "libresoc.v:174352.18-174352.107"
+ wire $and$libresoc.v:174352$9949_Y
+ attribute \src "libresoc.v:174348.18-174348.92"
+ wire width 192 $extend$libresoc.v:174348$9944_Y
+ attribute \src "libresoc.v:174350.18-174350.119"
+ wire $ge$libresoc.v:174350$9947_Y
+ attribute \src "libresoc.v:174349.18-174349.93"
+ wire $not$libresoc.v:174349$9946_Y
+ attribute \src "libresoc.v:174348.18-174348.92"
+ wire width 192 $pos$libresoc.v:174348$9945_Y
+ attribute \src "libresoc.v:174347.18-174347.138"
+ wire width 191 $sshl$libresoc.v:174347$9943_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
wire width 192 \$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
wire \$63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 65 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire input 30 \div_by_zero
wire \empty
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140"
wire \empty$next
- attribute \src "libresoc.v:174110.7-174110.15"
+ attribute \src "libresoc.v:173774.7-173774.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$49$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171"
- cell $and $and$libresoc.v:174687$10000
+ cell $and $and$libresoc.v:174351$9948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$59
connect \B \$61
- connect \Y $and$libresoc.v:174687$10000_Y
+ connect \Y $and$libresoc.v:174351$9948_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
- cell $and $and$libresoc.v:174688$10001
+ cell $and $and$libresoc.v:174352$9949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:174688$10001_Y
+ connect \Y $and$libresoc.v:174352$9949_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $pos $extend$libresoc.v:174684$9996
+ cell $pos $extend$libresoc.v:174348$9944
parameter \A_SIGNED 0
parameter \A_WIDTH 191
parameter \Y_WIDTH 192
connect \A \$56
- connect \Y $extend$libresoc.v:174684$9996_Y
+ connect \Y $extend$libresoc.v:174348$9944_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:174686$9999
+ cell $ge $ge$libresoc.v:174350$9947
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \saved_state_q_bits_known
connect \B 6'111111
- connect \Y $ge$libresoc.v:174686$9999_Y
+ connect \Y $ge$libresoc.v:174350$9947_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171"
- cell $not $not$libresoc.v:174685$9998
+ cell $not $not$libresoc.v:174349$9946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \empty
- connect \Y $not$libresoc.v:174685$9998_Y
+ connect \Y $not$libresoc.v:174349$9946_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $pos $pos$libresoc.v:174684$9997
+ cell $pos $pos$libresoc.v:174348$9945
parameter \A_SIGNED 0
parameter \A_WIDTH 192
parameter \Y_WIDTH 192
- connect \A $extend$libresoc.v:174684$9996_Y
- connect \Y $pos$libresoc.v:174684$9997_Y
+ connect \A $extend$libresoc.v:174348$9944_Y
+ connect \Y $pos$libresoc.v:174348$9945_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $sshl $sshl$libresoc.v:174683$9995
+ cell $sshl $sshl$libresoc.v:174347$9943
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 191
connect \A \div_state_next_o_dividend_quotient [127:64]
connect \B 7'1000000
- connect \Y $sshl$libresoc.v:174683$9995_Y
+ connect \Y $sshl$libresoc.v:174347$9943_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:174755.18-174759.4"
+ attribute \src "libresoc.v:174419.18-174423.4"
cell \div_state_init \div_state_init
connect \dividend \div_state_init_dividend
connect \o_dividend_quotient \div_state_init_o_dividend_quotient
connect \o_q_bits_known \div_state_init_o_q_bits_known
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:174760.18-174766.4"
+ attribute \src "libresoc.v:174424.18-174430.4"
cell \div_state_next \div_state_next
connect \divisor \div_state_next_divisor
connect \i_dividend_quotient \div_state_next_i_dividend_quotient
connect \o_q_bits_known \div_state_next_o_q_bits_known
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:174767.10-174770.4"
+ attribute \src "libresoc.v:174431.10-174434.4"
cell \n$80 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:174771.10-174774.4"
+ attribute \src "libresoc.v:174435.10-174438.4"
cell \p$79 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:174110.7-174110.20"
- process $proc$libresoc.v:174110$10189
+ attribute \src "libresoc.v:173774.7-173774.20"
+ process $proc$libresoc.v:173774$10137
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:174132.7-174132.30"
- process $proc$libresoc.v:174132$10190
+ attribute \src "libresoc.v:173796.7-173796.30"
+ process $proc$libresoc.v:173796$10138
assign { } { }
- assign $0\div_by_zero$54[0:0]$10191 1'0
+ assign $0\div_by_zero$54[0:0]$10139 1'0
sync always
sync init
- update \div_by_zero$54 $0\div_by_zero$54[0:0]$10191
+ update \div_by_zero$54 $0\div_by_zero$54[0:0]$10139
end
- attribute \src "libresoc.v:174156.7-174156.32"
- process $proc$libresoc.v:174156$10192
+ attribute \src "libresoc.v:173820.7-173820.32"
+ process $proc$libresoc.v:173820$10140
assign { } { }
- assign $0\dive_abs_ov32$52[0:0]$10193 1'0
+ assign $0\dive_abs_ov32$52[0:0]$10141 1'0
sync always
sync init
- update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10193
+ update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10141
end
- attribute \src "libresoc.v:174164.7-174164.32"
- process $proc$libresoc.v:174164$10194
+ attribute \src "libresoc.v:173828.7-173828.32"
+ process $proc$libresoc.v:173828$10142
assign { } { }
- assign $0\dive_abs_ov64$53[0:0]$10195 1'0
+ assign $0\dive_abs_ov64$53[0:0]$10143 1'0
sync always
sync init
- update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10195
+ update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10143
end
- attribute \src "libresoc.v:174170.15-174170.68"
- process $proc$libresoc.v:174170$10196
+ attribute \src "libresoc.v:173834.15-173834.68"
+ process $proc$libresoc.v:173834$10144
assign { } { }
- assign $0\dividend$68[127:0]$10197 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $0\dividend$68[127:0]$10145 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \dividend$68 $0\dividend$68[127:0]$10197
+ update \dividend$68 $0\dividend$68[127:0]$10145
end
- attribute \src "libresoc.v:174178.7-174178.31"
- process $proc$libresoc.v:174178$10198
+ attribute \src "libresoc.v:173842.7-173842.31"
+ process $proc$libresoc.v:173842$10146
assign { } { }
- assign $0\dividend_neg$51[0:0]$10199 1'0
+ assign $0\dividend_neg$51[0:0]$10147 1'0
sync always
sync init
- update \dividend_neg$51 $0\dividend_neg$51[0:0]$10199
+ update \dividend_neg$51 $0\dividend_neg$51[0:0]$10147
end
- attribute \src "libresoc.v:174186.7-174186.30"
- process $proc$libresoc.v:174186$10200
+ attribute \src "libresoc.v:173850.7-173850.30"
+ process $proc$libresoc.v:173850$10148
assign { } { }
- assign $0\divisor_neg$50[0:0]$10201 1'0
+ assign $0\divisor_neg$50[0:0]$10149 1'0
sync always
sync init
- update \divisor_neg$50 $0\divisor_neg$50[0:0]$10201
+ update \divisor_neg$50 $0\divisor_neg$50[0:0]$10149
end
- attribute \src "libresoc.v:174192.14-174192.58"
- process $proc$libresoc.v:174192$10202
+ attribute \src "libresoc.v:173856.14-173856.58"
+ process $proc$libresoc.v:173856$10150
assign { } { }
- assign $0\divisor_radicand$65[63:0]$10203 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\divisor_radicand$65[63:0]$10151 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10203
+ update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10151
end
- attribute \src "libresoc.v:174196.7-174196.19"
- process $proc$libresoc.v:174196$10204
+ attribute \src "libresoc.v:173860.7-173860.19"
+ process $proc$libresoc.v:173860$10152
assign { } { }
assign $1\empty[0:0] 1'1
sync always
sync init
update \empty $1\empty[0:0]
end
- attribute \src "libresoc.v:174204.13-174204.45"
- process $proc$libresoc.v:174204$10205
+ attribute \src "libresoc.v:173868.13-173868.45"
+ process $proc$libresoc.v:173868$10153
assign { } { }
- assign $0\logical_op__data_len$45[3:0]$10206 4'0000
+ assign $0\logical_op__data_len$45[3:0]$10154 4'0000
sync always
sync init
- update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10206
+ update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10154
end
- attribute \src "libresoc.v:174257.14-174257.49"
- process $proc$libresoc.v:174257$10207
+ attribute \src "libresoc.v:173921.14-173921.49"
+ process $proc$libresoc.v:173921$10155
assign { } { }
- assign $0\logical_op__fn_unit$30[13:0]$10208 14'00000000000000
+ assign $0\logical_op__fn_unit$30[13:0]$10156 14'00000000000000
sync always
sync init
- update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10208
+ update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10156
end
- attribute \src "libresoc.v:174263.14-174263.68"
- process $proc$libresoc.v:174263$10209
+ attribute \src "libresoc.v:173927.14-173927.68"
+ process $proc$libresoc.v:173927$10157
assign { } { }
- assign $0\logical_op__imm_data__data$31[63:0]$10210 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$31[63:0]$10158 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10210
+ update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10158
end
- attribute \src "libresoc.v:174271.7-174271.43"
- process $proc$libresoc.v:174271$10211
+ attribute \src "libresoc.v:173935.7-173935.43"
+ process $proc$libresoc.v:173935$10159
assign { } { }
- assign $0\logical_op__imm_data__ok$32[0:0]$10212 1'0
+ assign $0\logical_op__imm_data__ok$32[0:0]$10160 1'0
sync always
sync init
- update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10212
+ update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10160
end
- attribute \src "libresoc.v:174293.13-174293.48"
- process $proc$libresoc.v:174293$10213
+ attribute \src "libresoc.v:173957.13-173957.48"
+ process $proc$libresoc.v:173957$10161
assign { } { }
- assign $0\logical_op__input_carry$39[1:0]$10214 2'00
+ assign $0\logical_op__input_carry$39[1:0]$10162 2'00
sync always
sync init
- update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10214
+ update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10162
end
- attribute \src "libresoc.v:174301.14-174301.43"
- process $proc$libresoc.v:174301$10215
+ attribute \src "libresoc.v:173965.14-173965.43"
+ process $proc$libresoc.v:173965$10163
assign { } { }
- assign $0\logical_op__insn$46[31:0]$10216 0
+ assign $0\logical_op__insn$46[31:0]$10164 0
sync always
sync init
- update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10216
+ update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10164
end
- attribute \src "libresoc.v:174534.13-174534.47"
- process $proc$libresoc.v:174534$10217
+ attribute \src "libresoc.v:174198.13-174198.47"
+ process $proc$libresoc.v:174198$10165
assign { } { }
- assign $0\logical_op__insn_type$29[6:0]$10218 7'0000000
+ assign $0\logical_op__insn_type$29[6:0]$10166 7'0000000
sync always
sync init
- update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10218
+ update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10166
end
- attribute \src "libresoc.v:174542.7-174542.40"
- process $proc$libresoc.v:174542$10219
+ attribute \src "libresoc.v:174206.7-174206.40"
+ process $proc$libresoc.v:174206$10167
assign { } { }
- assign $0\logical_op__invert_in$37[0:0]$10220 1'0
+ assign $0\logical_op__invert_in$37[0:0]$10168 1'0
sync always
sync init
- update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10220
+ update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10168
end
- attribute \src "libresoc.v:174550.7-174550.41"
- process $proc$libresoc.v:174550$10221
+ attribute \src "libresoc.v:174214.7-174214.41"
+ process $proc$libresoc.v:174214$10169
assign { } { }
- assign $0\logical_op__invert_out$40[0:0]$10222 1'0
+ assign $0\logical_op__invert_out$40[0:0]$10170 1'0
sync always
sync init
- update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10222
+ update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10170
end
- attribute \src "libresoc.v:174558.7-174558.39"
- process $proc$libresoc.v:174558$10223
+ attribute \src "libresoc.v:174222.7-174222.39"
+ process $proc$libresoc.v:174222$10171
assign { } { }
- assign $0\logical_op__is_32bit$43[0:0]$10224 1'0
+ assign $0\logical_op__is_32bit$43[0:0]$10172 1'0
sync always
sync init
- update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10224
+ update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10172
end
- attribute \src "libresoc.v:174566.7-174566.40"
- process $proc$libresoc.v:174566$10225
+ attribute \src "libresoc.v:174230.7-174230.40"
+ process $proc$libresoc.v:174230$10173
assign { } { }
- assign $0\logical_op__is_signed$44[0:0]$10226 1'0
+ assign $0\logical_op__is_signed$44[0:0]$10174 1'0
sync always
sync init
- update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10226
+ update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10174
end
- attribute \src "libresoc.v:174572.7-174572.37"
- process $proc$libresoc.v:174572$10227
+ attribute \src "libresoc.v:174236.7-174236.37"
+ process $proc$libresoc.v:174236$10175
assign { } { }
- assign $0\logical_op__oe__oe$35[0:0]$10228 1'0
+ assign $0\logical_op__oe__oe$35[0:0]$10176 1'0
sync always
sync init
- update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10228
+ update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10176
end
- attribute \src "libresoc.v:174580.7-174580.37"
- process $proc$libresoc.v:174580$10229
+ attribute \src "libresoc.v:174244.7-174244.37"
+ process $proc$libresoc.v:174244$10177
assign { } { }
- assign $0\logical_op__oe__ok$36[0:0]$10230 1'0
+ assign $0\logical_op__oe__ok$36[0:0]$10178 1'0
sync always
sync init
- update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10230
+ update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10178
end
- attribute \src "libresoc.v:174590.7-174590.43"
- process $proc$libresoc.v:174590$10231
+ attribute \src "libresoc.v:174254.7-174254.43"
+ process $proc$libresoc.v:174254$10179
assign { } { }
- assign $0\logical_op__output_carry$42[0:0]$10232 1'0
+ assign $0\logical_op__output_carry$42[0:0]$10180 1'0
sync always
sync init
- update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10232
+ update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10180
end
- attribute \src "libresoc.v:174596.7-174596.37"
- process $proc$libresoc.v:174596$10233
+ attribute \src "libresoc.v:174260.7-174260.37"
+ process $proc$libresoc.v:174260$10181
assign { } { }
- assign $0\logical_op__rc__ok$34[0:0]$10234 1'0
+ assign $0\logical_op__rc__ok$34[0:0]$10182 1'0
sync always
sync init
- update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10234
+ update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10182
end
- attribute \src "libresoc.v:174604.7-174604.37"
- process $proc$libresoc.v:174604$10235
+ attribute \src "libresoc.v:174268.7-174268.37"
+ process $proc$libresoc.v:174268$10183
assign { } { }
- assign $0\logical_op__rc__rc$33[0:0]$10236 1'0
+ assign $0\logical_op__rc__rc$33[0:0]$10184 1'0
sync always
sync init
- update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10236
+ update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10184
end
- attribute \src "libresoc.v:174614.7-174614.40"
- process $proc$libresoc.v:174614$10237
+ attribute \src "libresoc.v:174278.7-174278.40"
+ process $proc$libresoc.v:174278$10185
assign { } { }
- assign $0\logical_op__write_cr0$41[0:0]$10238 1'0
+ assign $0\logical_op__write_cr0$41[0:0]$10186 1'0
sync always
sync init
- update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10238
+ update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10186
end
- attribute \src "libresoc.v:174622.7-174622.37"
- process $proc$libresoc.v:174622$10239
+ attribute \src "libresoc.v:174286.7-174286.37"
+ process $proc$libresoc.v:174286$10187
assign { } { }
- assign $0\logical_op__zero_a$38[0:0]$10240 1'0
+ assign $0\logical_op__zero_a$38[0:0]$10188 1'0
sync always
sync init
- update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10240
+ update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10188
end
- attribute \src "libresoc.v:174630.13-174630.30"
- process $proc$libresoc.v:174630$10241
+ attribute \src "libresoc.v:174294.13-174294.30"
+ process $proc$libresoc.v:174294$10189
assign { } { }
- assign $0\muxid$28[1:0]$10242 2'00
+ assign $0\muxid$28[1:0]$10190 2'00
sync always
sync init
- update \muxid$28 $0\muxid$28[1:0]$10242
+ update \muxid$28 $0\muxid$28[1:0]$10190
end
- attribute \src "libresoc.v:174640.13-174640.34"
- process $proc$libresoc.v:174640$10243
+ attribute \src "libresoc.v:174304.13-174304.34"
+ process $proc$libresoc.v:174304$10191
assign { } { }
- assign $0\operation$69[1:0]$10244 2'00
+ assign $0\operation$69[1:0]$10192 2'00
sync always
sync init
- update \operation$69 $0\operation$69[1:0]$10244
+ update \operation$69 $0\operation$69[1:0]$10192
end
- attribute \src "libresoc.v:174654.14-174654.44"
- process $proc$libresoc.v:174654$10245
+ attribute \src "libresoc.v:174318.14-174318.44"
+ process $proc$libresoc.v:174318$10193
assign { } { }
- assign $0\ra$47[63:0]$10246 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\ra$47[63:0]$10194 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \ra$47 $0\ra$47[63:0]$10246
+ update \ra$47 $0\ra$47[63:0]$10194
end
- attribute \src "libresoc.v:174662.14-174662.44"
- process $proc$libresoc.v:174662$10247
+ attribute \src "libresoc.v:174326.14-174326.44"
+ process $proc$libresoc.v:174326$10195
assign { } { }
- assign $0\rb$48[63:0]$10248 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\rb$48[63:0]$10196 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \rb$48 $0\rb$48[63:0]$10248
+ update \rb$48 $0\rb$48[63:0]$10196
end
- attribute \src "libresoc.v:174668.15-174668.84"
- process $proc$libresoc.v:174668$10249
+ attribute \src "libresoc.v:174332.15-174332.84"
+ process $proc$libresoc.v:174332$10197
assign { } { }
assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:174672.13-174672.45"
- process $proc$libresoc.v:174672$10250
+ attribute \src "libresoc.v:174336.13-174336.45"
+ process $proc$libresoc.v:174336$10198
assign { } { }
assign $1\saved_state_q_bits_known[6:0] 7'0000000
sync always
sync init
update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0]
end
- attribute \src "libresoc.v:174680.7-174680.25"
- process $proc$libresoc.v:174680$10251
+ attribute \src "libresoc.v:174344.7-174344.25"
+ process $proc$libresoc.v:174344$10199
assign { } { }
- assign $0\xer_so$49[0:0]$10252 1'0
+ assign $0\xer_so$49[0:0]$10200 1'0
sync always
sync init
- update \xer_so$49 $0\xer_so$49[0:0]$10252
+ update \xer_so$49 $0\xer_so$49[0:0]$10200
end
- attribute \src "libresoc.v:174689.3-174690.43"
- process $proc$libresoc.v:174689$10002
+ attribute \src "libresoc.v:174353.3-174354.43"
+ process $proc$libresoc.v:174353$9950
assign { } { }
- assign $0\operation$69[1:0]$10003 \operation$69$next
+ assign $0\operation$69[1:0]$9951 \operation$69$next
sync posedge \coresync_clk
- update \operation$69 $0\operation$69[1:0]$10003
+ update \operation$69 $0\operation$69[1:0]$9951
end
- attribute \src "libresoc.v:174691.3-174692.57"
- process $proc$libresoc.v:174691$10004
+ attribute \src "libresoc.v:174355.3-174356.57"
+ process $proc$libresoc.v:174355$9952
assign { } { }
- assign $0\divisor_radicand$65[63:0]$10005 \divisor_radicand$65$next
+ assign $0\divisor_radicand$65[63:0]$9953 \divisor_radicand$65$next
sync posedge \coresync_clk
- update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10005
+ update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9953
end
- attribute \src "libresoc.v:174693.3-174694.41"
- process $proc$libresoc.v:174693$10006
+ attribute \src "libresoc.v:174357.3-174358.41"
+ process $proc$libresoc.v:174357$9954
assign { } { }
- assign $0\dividend$68[127:0]$10007 \dividend$68$next
+ assign $0\dividend$68[127:0]$9955 \dividend$68$next
sync posedge \coresync_clk
- update \dividend$68 $0\dividend$68[127:0]$10007
+ update \dividend$68 $0\dividend$68[127:0]$9955
end
- attribute \src "libresoc.v:174695.3-174696.47"
- process $proc$libresoc.v:174695$10008
+ attribute \src "libresoc.v:174359.3-174360.47"
+ process $proc$libresoc.v:174359$9956
assign { } { }
- assign $0\div_by_zero$54[0:0]$10009 \div_by_zero$54$next
+ assign $0\div_by_zero$54[0:0]$9957 \div_by_zero$54$next
sync posedge \coresync_clk
- update \div_by_zero$54 $0\div_by_zero$54[0:0]$10009
+ update \div_by_zero$54 $0\div_by_zero$54[0:0]$9957
end
- attribute \src "libresoc.v:174697.3-174698.51"
- process $proc$libresoc.v:174697$10010
+ attribute \src "libresoc.v:174361.3-174362.51"
+ process $proc$libresoc.v:174361$9958
assign { } { }
- assign $0\dive_abs_ov64$53[0:0]$10011 \dive_abs_ov64$53$next
+ assign $0\dive_abs_ov64$53[0:0]$9959 \dive_abs_ov64$53$next
sync posedge \coresync_clk
- update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10011
+ update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9959
end
- attribute \src "libresoc.v:174699.3-174700.51"
- process $proc$libresoc.v:174699$10012
+ attribute \src "libresoc.v:174363.3-174364.51"
+ process $proc$libresoc.v:174363$9960
assign { } { }
- assign $0\dive_abs_ov32$52[0:0]$10013 \dive_abs_ov32$52$next
+ assign $0\dive_abs_ov32$52[0:0]$9961 \dive_abs_ov32$52$next
sync posedge \coresync_clk
- update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10013
+ update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9961
end
- attribute \src "libresoc.v:174701.3-174702.49"
- process $proc$libresoc.v:174701$10014
+ attribute \src "libresoc.v:174365.3-174366.49"
+ process $proc$libresoc.v:174365$9962
assign { } { }
- assign $0\dividend_neg$51[0:0]$10015 \dividend_neg$51$next
+ assign $0\dividend_neg$51[0:0]$9963 \dividend_neg$51$next
sync posedge \coresync_clk
- update \dividend_neg$51 $0\dividend_neg$51[0:0]$10015
+ update \dividend_neg$51 $0\dividend_neg$51[0:0]$9963
end
- attribute \src "libresoc.v:174703.3-174704.47"
- process $proc$libresoc.v:174703$10016
+ attribute \src "libresoc.v:174367.3-174368.47"
+ process $proc$libresoc.v:174367$9964
assign { } { }
- assign $0\divisor_neg$50[0:0]$10017 \divisor_neg$50$next
+ assign $0\divisor_neg$50[0:0]$9965 \divisor_neg$50$next
sync posedge \coresync_clk
- update \divisor_neg$50 $0\divisor_neg$50[0:0]$10017
+ update \divisor_neg$50 $0\divisor_neg$50[0:0]$9965
end
- attribute \src "libresoc.v:174705.3-174706.37"
- process $proc$libresoc.v:174705$10018
+ attribute \src "libresoc.v:174369.3-174370.37"
+ process $proc$libresoc.v:174369$9966
assign { } { }
- assign $0\xer_so$49[0:0]$10019 \xer_so$49$next
+ assign $0\xer_so$49[0:0]$9967 \xer_so$49$next
sync posedge \coresync_clk
- update \xer_so$49 $0\xer_so$49[0:0]$10019
+ update \xer_so$49 $0\xer_so$49[0:0]$9967
end
- attribute \src "libresoc.v:174707.3-174708.29"
- process $proc$libresoc.v:174707$10020
+ attribute \src "libresoc.v:174371.3-174372.29"
+ process $proc$libresoc.v:174371$9968
assign { } { }
- assign $0\rb$48[63:0]$10021 \rb$48$next
+ assign $0\rb$48[63:0]$9969 \rb$48$next
sync posedge \coresync_clk
- update \rb$48 $0\rb$48[63:0]$10021
+ update \rb$48 $0\rb$48[63:0]$9969
end
- attribute \src "libresoc.v:174709.3-174710.29"
- process $proc$libresoc.v:174709$10022
+ attribute \src "libresoc.v:174373.3-174374.29"
+ process $proc$libresoc.v:174373$9970
assign { } { }
- assign $0\ra$47[63:0]$10023 \ra$47$next
+ assign $0\ra$47[63:0]$9971 \ra$47$next
sync posedge \coresync_clk
- update \ra$47 $0\ra$47[63:0]$10023
+ update \ra$47 $0\ra$47[63:0]$9971
end
- attribute \src "libresoc.v:174711.3-174712.67"
- process $proc$libresoc.v:174711$10024
+ attribute \src "libresoc.v:174375.3-174376.67"
+ process $proc$libresoc.v:174375$9972
assign { } { }
- assign $0\logical_op__insn_type$29[6:0]$10025 \logical_op__insn_type$29$next
+ assign $0\logical_op__insn_type$29[6:0]$9973 \logical_op__insn_type$29$next
sync posedge \coresync_clk
- update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10025
+ update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9973
end
- attribute \src "libresoc.v:174713.3-174714.63"
- process $proc$libresoc.v:174713$10026
+ attribute \src "libresoc.v:174377.3-174378.63"
+ process $proc$libresoc.v:174377$9974
assign { } { }
- assign $0\logical_op__fn_unit$30[13:0]$10027 \logical_op__fn_unit$30$next
+ assign $0\logical_op__fn_unit$30[13:0]$9975 \logical_op__fn_unit$30$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10027
+ update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9975
end
- attribute \src "libresoc.v:174715.3-174716.77"
- process $proc$libresoc.v:174715$10028
+ attribute \src "libresoc.v:174379.3-174380.77"
+ process $proc$libresoc.v:174379$9976
assign { } { }
- assign $0\logical_op__imm_data__data$31[63:0]$10029 \logical_op__imm_data__data$31$next
+ assign $0\logical_op__imm_data__data$31[63:0]$9977 \logical_op__imm_data__data$31$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10029
+ update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9977
end
- attribute \src "libresoc.v:174717.3-174718.73"
- process $proc$libresoc.v:174717$10030
+ attribute \src "libresoc.v:174381.3-174382.73"
+ process $proc$libresoc.v:174381$9978
assign { } { }
- assign $0\logical_op__imm_data__ok$32[0:0]$10031 \logical_op__imm_data__ok$32$next
+ assign $0\logical_op__imm_data__ok$32[0:0]$9979 \logical_op__imm_data__ok$32$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10031
+ update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9979
end
- attribute \src "libresoc.v:174719.3-174720.61"
- process $proc$libresoc.v:174719$10032
+ attribute \src "libresoc.v:174383.3-174384.61"
+ process $proc$libresoc.v:174383$9980
assign { } { }
- assign $0\logical_op__rc__rc$33[0:0]$10033 \logical_op__rc__rc$33$next
+ assign $0\logical_op__rc__rc$33[0:0]$9981 \logical_op__rc__rc$33$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10033
+ update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9981
end
- attribute \src "libresoc.v:174721.3-174722.61"
- process $proc$libresoc.v:174721$10034
+ attribute \src "libresoc.v:174385.3-174386.61"
+ process $proc$libresoc.v:174385$9982
assign { } { }
- assign $0\logical_op__rc__ok$34[0:0]$10035 \logical_op__rc__ok$34$next
+ assign $0\logical_op__rc__ok$34[0:0]$9983 \logical_op__rc__ok$34$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10035
+ update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9983
end
- attribute \src "libresoc.v:174723.3-174724.61"
- process $proc$libresoc.v:174723$10036
+ attribute \src "libresoc.v:174387.3-174388.61"
+ process $proc$libresoc.v:174387$9984
assign { } { }
- assign $0\logical_op__oe__oe$35[0:0]$10037 \logical_op__oe__oe$35$next
+ assign $0\logical_op__oe__oe$35[0:0]$9985 \logical_op__oe__oe$35$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10037
+ update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9985
end
- attribute \src "libresoc.v:174725.3-174726.61"
- process $proc$libresoc.v:174725$10038
+ attribute \src "libresoc.v:174389.3-174390.61"
+ process $proc$libresoc.v:174389$9986
assign { } { }
- assign $0\logical_op__oe__ok$36[0:0]$10039 \logical_op__oe__ok$36$next
+ assign $0\logical_op__oe__ok$36[0:0]$9987 \logical_op__oe__ok$36$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10039
+ update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9987
end
- attribute \src "libresoc.v:174727.3-174728.67"
- process $proc$libresoc.v:174727$10040
+ attribute \src "libresoc.v:174391.3-174392.67"
+ process $proc$libresoc.v:174391$9988
assign { } { }
- assign $0\logical_op__invert_in$37[0:0]$10041 \logical_op__invert_in$37$next
+ assign $0\logical_op__invert_in$37[0:0]$9989 \logical_op__invert_in$37$next
sync posedge \coresync_clk
- update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10041
+ update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9989
end
- attribute \src "libresoc.v:174729.3-174730.61"
- process $proc$libresoc.v:174729$10042
+ attribute \src "libresoc.v:174393.3-174394.61"
+ process $proc$libresoc.v:174393$9990
assign { } { }
- assign $0\logical_op__zero_a$38[0:0]$10043 \logical_op__zero_a$38$next
+ assign $0\logical_op__zero_a$38[0:0]$9991 \logical_op__zero_a$38$next
sync posedge \coresync_clk
- update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10043
+ update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9991
end
- attribute \src "libresoc.v:174731.3-174732.71"
- process $proc$libresoc.v:174731$10044
+ attribute \src "libresoc.v:174395.3-174396.71"
+ process $proc$libresoc.v:174395$9992
assign { } { }
- assign $0\logical_op__input_carry$39[1:0]$10045 \logical_op__input_carry$39$next
+ assign $0\logical_op__input_carry$39[1:0]$9993 \logical_op__input_carry$39$next
sync posedge \coresync_clk
- update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10045
+ update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9993
end
- attribute \src "libresoc.v:174733.3-174734.69"
- process $proc$libresoc.v:174733$10046
+ attribute \src "libresoc.v:174397.3-174398.69"
+ process $proc$libresoc.v:174397$9994
assign { } { }
- assign $0\logical_op__invert_out$40[0:0]$10047 \logical_op__invert_out$40$next
+ assign $0\logical_op__invert_out$40[0:0]$9995 \logical_op__invert_out$40$next
sync posedge \coresync_clk
- update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10047
+ update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9995
end
- attribute \src "libresoc.v:174735.3-174736.67"
- process $proc$libresoc.v:174735$10048
+ attribute \src "libresoc.v:174399.3-174400.67"
+ process $proc$libresoc.v:174399$9996
assign { } { }
- assign $0\logical_op__write_cr0$41[0:0]$10049 \logical_op__write_cr0$41$next
+ assign $0\logical_op__write_cr0$41[0:0]$9997 \logical_op__write_cr0$41$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10049
+ update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9997
end
- attribute \src "libresoc.v:174737.3-174738.73"
- process $proc$libresoc.v:174737$10050
+ attribute \src "libresoc.v:174401.3-174402.73"
+ process $proc$libresoc.v:174401$9998
assign { } { }
- assign $0\logical_op__output_carry$42[0:0]$10051 \logical_op__output_carry$42$next
+ assign $0\logical_op__output_carry$42[0:0]$9999 \logical_op__output_carry$42$next
sync posedge \coresync_clk
- update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10051
+ update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9999
end
- attribute \src "libresoc.v:174739.3-174740.65"
- process $proc$libresoc.v:174739$10052
+ attribute \src "libresoc.v:174403.3-174404.65"
+ process $proc$libresoc.v:174403$10000
assign { } { }
- assign $0\logical_op__is_32bit$43[0:0]$10053 \logical_op__is_32bit$43$next
+ assign $0\logical_op__is_32bit$43[0:0]$10001 \logical_op__is_32bit$43$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10053
+ update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10001
end
- attribute \src "libresoc.v:174741.3-174742.67"
- process $proc$libresoc.v:174741$10054
+ attribute \src "libresoc.v:174405.3-174406.67"
+ process $proc$libresoc.v:174405$10002
assign { } { }
- assign $0\logical_op__is_signed$44[0:0]$10055 \logical_op__is_signed$44$next
+ assign $0\logical_op__is_signed$44[0:0]$10003 \logical_op__is_signed$44$next
sync posedge \coresync_clk
- update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10055
+ update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10003
end
- attribute \src "libresoc.v:174743.3-174744.65"
- process $proc$libresoc.v:174743$10056
+ attribute \src "libresoc.v:174407.3-174408.65"
+ process $proc$libresoc.v:174407$10004
assign { } { }
- assign $0\logical_op__data_len$45[3:0]$10057 \logical_op__data_len$45$next
+ assign $0\logical_op__data_len$45[3:0]$10005 \logical_op__data_len$45$next
sync posedge \coresync_clk
- update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10057
+ update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10005
end
- attribute \src "libresoc.v:174745.3-174746.57"
- process $proc$libresoc.v:174745$10058
+ attribute \src "libresoc.v:174409.3-174410.57"
+ process $proc$libresoc.v:174409$10006
assign { } { }
- assign $0\logical_op__insn$46[31:0]$10059 \logical_op__insn$46$next
+ assign $0\logical_op__insn$46[31:0]$10007 \logical_op__insn$46$next
sync posedge \coresync_clk
- update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10059
+ update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10007
end
- attribute \src "libresoc.v:174747.3-174748.35"
- process $proc$libresoc.v:174747$10060
+ attribute \src "libresoc.v:174411.3-174412.35"
+ process $proc$libresoc.v:174411$10008
assign { } { }
- assign $0\muxid$28[1:0]$10061 \muxid$28$next
+ assign $0\muxid$28[1:0]$10009 \muxid$28$next
sync posedge \coresync_clk
- update \muxid$28 $0\muxid$28[1:0]$10061
+ update \muxid$28 $0\muxid$28[1:0]$10009
end
- attribute \src "libresoc.v:174749.3-174750.27"
- process $proc$libresoc.v:174749$10062
+ attribute \src "libresoc.v:174413.3-174414.27"
+ process $proc$libresoc.v:174413$10010
assign { } { }
assign $0\empty[0:0] \empty$next
sync posedge \coresync_clk
update \empty $0\empty[0:0]
end
- attribute \src "libresoc.v:174751.3-174752.75"
- process $proc$libresoc.v:174751$10063
+ attribute \src "libresoc.v:174415.3-174416.75"
+ process $proc$libresoc.v:174415$10011
assign { } { }
assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next
sync posedge \coresync_clk
update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:174753.3-174754.65"
- process $proc$libresoc.v:174753$10064
+ attribute \src "libresoc.v:174417.3-174418.65"
+ process $proc$libresoc.v:174417$10012
assign { } { }
assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next
sync posedge \coresync_clk
update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0]
end
- attribute \src "libresoc.v:174775.3-174783.6"
- process $proc$libresoc.v:174775$10065
+ attribute \src "libresoc.v:174439.3-174447.6"
+ process $proc$libresoc.v:174439$10013
assign { } { }
assign { } { }
- assign $0\saved_state_q_bits_known$next[6:0]$10066 $1\saved_state_q_bits_known$next[6:0]$10067
- attribute \src "libresoc.v:174776.5-174776.29"
+ assign $0\saved_state_q_bits_known$next[6:0]$10014 $1\saved_state_q_bits_known$next[6:0]$10015
+ attribute \src "libresoc.v:174440.5-174440.29"
switch \initial
- attribute \src "libresoc.v:174776.9-174776.17"
+ attribute \src "libresoc.v:174440.9-174440.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\saved_state_q_bits_known$next[6:0]$10067 7'0000000
+ assign $1\saved_state_q_bits_known$next[6:0]$10015 7'0000000
case
- assign $1\saved_state_q_bits_known$next[6:0]$10067 \div_state_next_o_q_bits_known
+ assign $1\saved_state_q_bits_known$next[6:0]$10015 \div_state_next_o_q_bits_known
end
sync always
- update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10066
+ update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10014
end
- attribute \src "libresoc.v:174784.3-174792.6"
- process $proc$libresoc.v:174784$10068
+ attribute \src "libresoc.v:174448.3-174456.6"
+ process $proc$libresoc.v:174448$10016
assign { } { }
assign { } { }
- assign $0\saved_state_dividend_quotient$next[127:0]$10069 $1\saved_state_dividend_quotient$next[127:0]$10070
- attribute \src "libresoc.v:174785.5-174785.29"
+ assign $0\saved_state_dividend_quotient$next[127:0]$10017 $1\saved_state_dividend_quotient$next[127:0]$10018
+ attribute \src "libresoc.v:174449.5-174449.29"
switch \initial
- attribute \src "libresoc.v:174785.9-174785.17"
+ attribute \src "libresoc.v:174449.9-174449.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\saved_state_dividend_quotient$next[127:0]$10070 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $1\saved_state_dividend_quotient$next[127:0]$10018 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\saved_state_dividend_quotient$next[127:0]$10070 \div_state_next_o_dividend_quotient
+ assign $1\saved_state_dividend_quotient$next[127:0]$10018 \div_state_next_o_dividend_quotient
end
sync always
- update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10069
+ update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10017
end
- attribute \src "libresoc.v:174793.3-174804.6"
- process $proc$libresoc.v:174793$10071
+ attribute \src "libresoc.v:174457.3-174468.6"
+ process $proc$libresoc.v:174457$10019
assign { } { }
assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:174794.5-174794.29"
+ attribute \src "libresoc.v:174458.5-174458.29"
switch \initial
- attribute \src "libresoc.v:174794.9-174794.17"
+ attribute \src "libresoc.v:174458.9-174458.17"
case 1'1
case
end
sync always
update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0]
end
- attribute \src "libresoc.v:174805.3-174816.6"
- process $proc$libresoc.v:174805$10072
+ attribute \src "libresoc.v:174469.3-174480.6"
+ process $proc$libresoc.v:174469$10020
assign { } { }
assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:174806.5-174806.29"
+ attribute \src "libresoc.v:174470.5-174470.29"
switch \initial
- attribute \src "libresoc.v:174806.9-174806.17"
+ attribute \src "libresoc.v:174470.9-174470.17"
case 1'1
case
end
sync always
update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:174817.3-174828.6"
- process $proc$libresoc.v:174817$10073
+ attribute \src "libresoc.v:174481.3-174492.6"
+ process $proc$libresoc.v:174481$10021
assign { } { }
assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:174818.5-174818.29"
+ attribute \src "libresoc.v:174482.5-174482.29"
switch \initial
- attribute \src "libresoc.v:174818.9-174818.17"
+ attribute \src "libresoc.v:174482.9-174482.17"
case 1'1
case
end
sync always
update \div_state_next_divisor $0\div_state_next_divisor[63:0]
end
- attribute \src "libresoc.v:174829.3-174856.6"
- process $proc$libresoc.v:174829$10074
+ attribute \src "libresoc.v:174493.3-174520.6"
+ process $proc$libresoc.v:174493$10022
assign { } { }
assign { } { }
assign { } { }
- assign $0\empty$next[0:0]$10075 $4\empty$next[0:0]$10079
- attribute \src "libresoc.v:174830.5-174830.29"
+ assign $0\empty$next[0:0]$10023 $4\empty$next[0:0]$10027
+ attribute \src "libresoc.v:174494.5-174494.29"
switch \initial
- attribute \src "libresoc.v:174830.9-174830.17"
+ attribute \src "libresoc.v:174494.9-174494.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\empty$next[0:0]$10076 $2\empty$next[0:0]$10077
+ assign $1\empty$next[0:0]$10024 $2\empty$next[0:0]$10025
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\empty$next[0:0]$10077 1'0
+ assign $2\empty$next[0:0]$10025 1'0
case
- assign $2\empty$next[0:0]$10077 \empty
+ assign $2\empty$next[0:0]$10025 \empty
end
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\empty$next[0:0]$10076 $3\empty$next[0:0]$10078
+ assign $1\empty$next[0:0]$10024 $3\empty$next[0:0]$10026
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
switch \$66
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\empty$next[0:0]$10078 1'1
+ assign $3\empty$next[0:0]$10026 1'1
case
- assign $3\empty$next[0:0]$10078 \empty
+ assign $3\empty$next[0:0]$10026 \empty
end
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\empty$next[0:0]$10079 1'1
+ assign $4\empty$next[0:0]$10027 1'1
case
- assign $4\empty$next[0:0]$10079 $1\empty$next[0:0]$10076
+ assign $4\empty$next[0:0]$10027 $1\empty$next[0:0]$10024
end
sync always
- update \empty$next $0\empty$next[0:0]$10075
+ update \empty$next $0\empty$next[0:0]$10023
end
- attribute \src "libresoc.v:174857.3-174871.6"
- process $proc$libresoc.v:174857$10080
+ attribute \src "libresoc.v:174521.3-174535.6"
+ process $proc$libresoc.v:174521$10028
assign { } { }
assign { } { }
- assign $0\muxid$28$next[1:0]$10081 $1\muxid$28$next[1:0]$10082
- attribute \src "libresoc.v:174858.5-174858.29"
+ assign $0\muxid$28$next[1:0]$10029 $1\muxid$28$next[1:0]$10030
+ attribute \src "libresoc.v:174522.5-174522.29"
switch \initial
- attribute \src "libresoc.v:174858.9-174858.17"
+ attribute \src "libresoc.v:174522.9-174522.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\muxid$28$next[1:0]$10082 $2\muxid$28$next[1:0]$10083
+ assign $1\muxid$28$next[1:0]$10030 $2\muxid$28$next[1:0]$10031
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\muxid$28$next[1:0]$10083 \muxid
+ assign $2\muxid$28$next[1:0]$10031 \muxid
case
- assign $2\muxid$28$next[1:0]$10083 \muxid$28
+ assign $2\muxid$28$next[1:0]$10031 \muxid$28
end
case
- assign $1\muxid$28$next[1:0]$10082 \muxid$28
+ assign $1\muxid$28$next[1:0]$10030 \muxid$28
end
sync always
- update \muxid$28$next $0\muxid$28$next[1:0]$10081
+ update \muxid$28$next $0\muxid$28$next[1:0]$10029
end
- attribute \src "libresoc.v:174872.3-174915.6"
- process $proc$libresoc.v:174872$10084
+ attribute \src "libresoc.v:174536.3-174579.6"
+ process $proc$libresoc.v:174536$10032
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$45$next[3:0]$10085 $1\logical_op__data_len$45$next[3:0]$10103
- assign $0\logical_op__fn_unit$30$next[13:0]$10086 $1\logical_op__fn_unit$30$next[13:0]$10104
+ assign $0\logical_op__data_len$45$next[3:0]$10033 $1\logical_op__data_len$45$next[3:0]$10051
+ assign $0\logical_op__fn_unit$30$next[13:0]$10034 $1\logical_op__fn_unit$30$next[13:0]$10052
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$39$next[1:0]$10089 $1\logical_op__input_carry$39$next[1:0]$10107
- assign $0\logical_op__insn$46$next[31:0]$10090 $1\logical_op__insn$46$next[31:0]$10108
- assign $0\logical_op__insn_type$29$next[6:0]$10091 $1\logical_op__insn_type$29$next[6:0]$10109
- assign $0\logical_op__invert_in$37$next[0:0]$10092 $1\logical_op__invert_in$37$next[0:0]$10110
- assign $0\logical_op__invert_out$40$next[0:0]$10093 $1\logical_op__invert_out$40$next[0:0]$10111
- assign $0\logical_op__is_32bit$43$next[0:0]$10094 $1\logical_op__is_32bit$43$next[0:0]$10112
- assign $0\logical_op__is_signed$44$next[0:0]$10095 $1\logical_op__is_signed$44$next[0:0]$10113
+ assign $0\logical_op__input_carry$39$next[1:0]$10037 $1\logical_op__input_carry$39$next[1:0]$10055
+ assign $0\logical_op__insn$46$next[31:0]$10038 $1\logical_op__insn$46$next[31:0]$10056
+ assign $0\logical_op__insn_type$29$next[6:0]$10039 $1\logical_op__insn_type$29$next[6:0]$10057
+ assign $0\logical_op__invert_in$37$next[0:0]$10040 $1\logical_op__invert_in$37$next[0:0]$10058
+ assign $0\logical_op__invert_out$40$next[0:0]$10041 $1\logical_op__invert_out$40$next[0:0]$10059
+ assign $0\logical_op__is_32bit$43$next[0:0]$10042 $1\logical_op__is_32bit$43$next[0:0]$10060
+ assign $0\logical_op__is_signed$44$next[0:0]$10043 $1\logical_op__is_signed$44$next[0:0]$10061
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$42$next[0:0]$10098 $1\logical_op__output_carry$42$next[0:0]$10116
+ assign $0\logical_op__output_carry$42$next[0:0]$10046 $1\logical_op__output_carry$42$next[0:0]$10064
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$41$next[0:0]$10101 $1\logical_op__write_cr0$41$next[0:0]$10119
- assign $0\logical_op__zero_a$38$next[0:0]$10102 $1\logical_op__zero_a$38$next[0:0]$10120
- assign $0\logical_op__imm_data__data$31$next[63:0]$10087 $3\logical_op__imm_data__data$31$next[63:0]$10139
- assign $0\logical_op__imm_data__ok$32$next[0:0]$10088 $3\logical_op__imm_data__ok$32$next[0:0]$10140
- assign $0\logical_op__oe__oe$35$next[0:0]$10096 $3\logical_op__oe__oe$35$next[0:0]$10141
- assign $0\logical_op__oe__ok$36$next[0:0]$10097 $3\logical_op__oe__ok$36$next[0:0]$10142
- assign $0\logical_op__rc__ok$34$next[0:0]$10099 $3\logical_op__rc__ok$34$next[0:0]$10143
- assign $0\logical_op__rc__rc$33$next[0:0]$10100 $3\logical_op__rc__rc$33$next[0:0]$10144
- attribute \src "libresoc.v:174873.5-174873.29"
+ assign $0\logical_op__write_cr0$41$next[0:0]$10049 $1\logical_op__write_cr0$41$next[0:0]$10067
+ assign $0\logical_op__zero_a$38$next[0:0]$10050 $1\logical_op__zero_a$38$next[0:0]$10068
+ assign $0\logical_op__imm_data__data$31$next[63:0]$10035 $3\logical_op__imm_data__data$31$next[63:0]$10087
+ assign $0\logical_op__imm_data__ok$32$next[0:0]$10036 $3\logical_op__imm_data__ok$32$next[0:0]$10088
+ assign $0\logical_op__oe__oe$35$next[0:0]$10044 $3\logical_op__oe__oe$35$next[0:0]$10089
+ assign $0\logical_op__oe__ok$36$next[0:0]$10045 $3\logical_op__oe__ok$36$next[0:0]$10090
+ assign $0\logical_op__rc__ok$34$next[0:0]$10047 $3\logical_op__rc__ok$34$next[0:0]$10091
+ assign $0\logical_op__rc__rc$33$next[0:0]$10048 $3\logical_op__rc__rc$33$next[0:0]$10092
+ attribute \src "libresoc.v:174537.5-174537.29"
switch \initial
- attribute \src "libresoc.v:174873.9-174873.17"
+ attribute \src "libresoc.v:174537.9-174537.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\logical_op__data_len$45$next[3:0]$10103 $2\logical_op__data_len$45$next[3:0]$10121
- assign $1\logical_op__fn_unit$30$next[13:0]$10104 $2\logical_op__fn_unit$30$next[13:0]$10122
- assign $1\logical_op__imm_data__data$31$next[63:0]$10105 $2\logical_op__imm_data__data$31$next[63:0]$10123
- assign $1\logical_op__imm_data__ok$32$next[0:0]$10106 $2\logical_op__imm_data__ok$32$next[0:0]$10124
- assign $1\logical_op__input_carry$39$next[1:0]$10107 $2\logical_op__input_carry$39$next[1:0]$10125
- assign $1\logical_op__insn$46$next[31:0]$10108 $2\logical_op__insn$46$next[31:0]$10126
- assign $1\logical_op__insn_type$29$next[6:0]$10109 $2\logical_op__insn_type$29$next[6:0]$10127
- assign $1\logical_op__invert_in$37$next[0:0]$10110 $2\logical_op__invert_in$37$next[0:0]$10128
- assign $1\logical_op__invert_out$40$next[0:0]$10111 $2\logical_op__invert_out$40$next[0:0]$10129
- assign $1\logical_op__is_32bit$43$next[0:0]$10112 $2\logical_op__is_32bit$43$next[0:0]$10130
- assign $1\logical_op__is_signed$44$next[0:0]$10113 $2\logical_op__is_signed$44$next[0:0]$10131
- assign $1\logical_op__oe__oe$35$next[0:0]$10114 $2\logical_op__oe__oe$35$next[0:0]$10132
- assign $1\logical_op__oe__ok$36$next[0:0]$10115 $2\logical_op__oe__ok$36$next[0:0]$10133
- assign $1\logical_op__output_carry$42$next[0:0]$10116 $2\logical_op__output_carry$42$next[0:0]$10134
- assign $1\logical_op__rc__ok$34$next[0:0]$10117 $2\logical_op__rc__ok$34$next[0:0]$10135
- assign $1\logical_op__rc__rc$33$next[0:0]$10118 $2\logical_op__rc__rc$33$next[0:0]$10136
- assign $1\logical_op__write_cr0$41$next[0:0]$10119 $2\logical_op__write_cr0$41$next[0:0]$10137
- assign $1\logical_op__zero_a$38$next[0:0]$10120 $2\logical_op__zero_a$38$next[0:0]$10138
+ assign $1\logical_op__data_len$45$next[3:0]$10051 $2\logical_op__data_len$45$next[3:0]$10069
+ assign $1\logical_op__fn_unit$30$next[13:0]$10052 $2\logical_op__fn_unit$30$next[13:0]$10070
+ assign $1\logical_op__imm_data__data$31$next[63:0]$10053 $2\logical_op__imm_data__data$31$next[63:0]$10071
+ assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 $2\logical_op__imm_data__ok$32$next[0:0]$10072
+ assign $1\logical_op__input_carry$39$next[1:0]$10055 $2\logical_op__input_carry$39$next[1:0]$10073
+ assign $1\logical_op__insn$46$next[31:0]$10056 $2\logical_op__insn$46$next[31:0]$10074
+ assign $1\logical_op__insn_type$29$next[6:0]$10057 $2\logical_op__insn_type$29$next[6:0]$10075
+ assign $1\logical_op__invert_in$37$next[0:0]$10058 $2\logical_op__invert_in$37$next[0:0]$10076
+ assign $1\logical_op__invert_out$40$next[0:0]$10059 $2\logical_op__invert_out$40$next[0:0]$10077
+ assign $1\logical_op__is_32bit$43$next[0:0]$10060 $2\logical_op__is_32bit$43$next[0:0]$10078
+ assign $1\logical_op__is_signed$44$next[0:0]$10061 $2\logical_op__is_signed$44$next[0:0]$10079
+ assign $1\logical_op__oe__oe$35$next[0:0]$10062 $2\logical_op__oe__oe$35$next[0:0]$10080
+ assign $1\logical_op__oe__ok$36$next[0:0]$10063 $2\logical_op__oe__ok$36$next[0:0]$10081
+ assign $1\logical_op__output_carry$42$next[0:0]$10064 $2\logical_op__output_carry$42$next[0:0]$10082
+ assign $1\logical_op__rc__ok$34$next[0:0]$10065 $2\logical_op__rc__ok$34$next[0:0]$10083
+ assign $1\logical_op__rc__rc$33$next[0:0]$10066 $2\logical_op__rc__rc$33$next[0:0]$10084
+ assign $1\logical_op__write_cr0$41$next[0:0]$10067 $2\logical_op__write_cr0$41$next[0:0]$10085
+ assign $1\logical_op__zero_a$38$next[0:0]$10068 $2\logical_op__zero_a$38$next[0:0]$10086
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $2\logical_op__insn$46$next[31:0]$10126 $2\logical_op__data_len$45$next[3:0]$10121 $2\logical_op__is_signed$44$next[0:0]$10131 $2\logical_op__is_32bit$43$next[0:0]$10130 $2\logical_op__output_carry$42$next[0:0]$10134 $2\logical_op__write_cr0$41$next[0:0]$10137 $2\logical_op__invert_out$40$next[0:0]$10129 $2\logical_op__input_carry$39$next[1:0]$10125 $2\logical_op__zero_a$38$next[0:0]$10138 $2\logical_op__invert_in$37$next[0:0]$10128 $2\logical_op__oe__ok$36$next[0:0]$10133 $2\logical_op__oe__oe$35$next[0:0]$10132 $2\logical_op__rc__ok$34$next[0:0]$10135 $2\logical_op__rc__rc$33$next[0:0]$10136 $2\logical_op__imm_data__ok$32$next[0:0]$10124 $2\logical_op__imm_data__data$31$next[63:0]$10123 $2\logical_op__fn_unit$30$next[13:0]$10122 $2\logical_op__insn_type$29$next[6:0]$10127 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
+ assign { $2\logical_op__insn$46$next[31:0]$10074 $2\logical_op__data_len$45$next[3:0]$10069 $2\logical_op__is_signed$44$next[0:0]$10079 $2\logical_op__is_32bit$43$next[0:0]$10078 $2\logical_op__output_carry$42$next[0:0]$10082 $2\logical_op__write_cr0$41$next[0:0]$10085 $2\logical_op__invert_out$40$next[0:0]$10077 $2\logical_op__input_carry$39$next[1:0]$10073 $2\logical_op__zero_a$38$next[0:0]$10086 $2\logical_op__invert_in$37$next[0:0]$10076 $2\logical_op__oe__ok$36$next[0:0]$10081 $2\logical_op__oe__oe$35$next[0:0]$10080 $2\logical_op__rc__ok$34$next[0:0]$10083 $2\logical_op__rc__rc$33$next[0:0]$10084 $2\logical_op__imm_data__ok$32$next[0:0]$10072 $2\logical_op__imm_data__data$31$next[63:0]$10071 $2\logical_op__fn_unit$30$next[13:0]$10070 $2\logical_op__insn_type$29$next[6:0]$10075 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
case
- assign $2\logical_op__data_len$45$next[3:0]$10121 \logical_op__data_len$45
- assign $2\logical_op__fn_unit$30$next[13:0]$10122 \logical_op__fn_unit$30
- assign $2\logical_op__imm_data__data$31$next[63:0]$10123 \logical_op__imm_data__data$31
- assign $2\logical_op__imm_data__ok$32$next[0:0]$10124 \logical_op__imm_data__ok$32
- assign $2\logical_op__input_carry$39$next[1:0]$10125 \logical_op__input_carry$39
- assign $2\logical_op__insn$46$next[31:0]$10126 \logical_op__insn$46
- assign $2\logical_op__insn_type$29$next[6:0]$10127 \logical_op__insn_type$29
- assign $2\logical_op__invert_in$37$next[0:0]$10128 \logical_op__invert_in$37
- assign $2\logical_op__invert_out$40$next[0:0]$10129 \logical_op__invert_out$40
- assign $2\logical_op__is_32bit$43$next[0:0]$10130 \logical_op__is_32bit$43
- assign $2\logical_op__is_signed$44$next[0:0]$10131 \logical_op__is_signed$44
- assign $2\logical_op__oe__oe$35$next[0:0]$10132 \logical_op__oe__oe$35
- assign $2\logical_op__oe__ok$36$next[0:0]$10133 \logical_op__oe__ok$36
- assign $2\logical_op__output_carry$42$next[0:0]$10134 \logical_op__output_carry$42
- assign $2\logical_op__rc__ok$34$next[0:0]$10135 \logical_op__rc__ok$34
- assign $2\logical_op__rc__rc$33$next[0:0]$10136 \logical_op__rc__rc$33
- assign $2\logical_op__write_cr0$41$next[0:0]$10137 \logical_op__write_cr0$41
- assign $2\logical_op__zero_a$38$next[0:0]$10138 \logical_op__zero_a$38
+ assign $2\logical_op__data_len$45$next[3:0]$10069 \logical_op__data_len$45
+ assign $2\logical_op__fn_unit$30$next[13:0]$10070 \logical_op__fn_unit$30
+ assign $2\logical_op__imm_data__data$31$next[63:0]$10071 \logical_op__imm_data__data$31
+ assign $2\logical_op__imm_data__ok$32$next[0:0]$10072 \logical_op__imm_data__ok$32
+ assign $2\logical_op__input_carry$39$next[1:0]$10073 \logical_op__input_carry$39
+ assign $2\logical_op__insn$46$next[31:0]$10074 \logical_op__insn$46
+ assign $2\logical_op__insn_type$29$next[6:0]$10075 \logical_op__insn_type$29
+ assign $2\logical_op__invert_in$37$next[0:0]$10076 \logical_op__invert_in$37
+ assign $2\logical_op__invert_out$40$next[0:0]$10077 \logical_op__invert_out$40
+ assign $2\logical_op__is_32bit$43$next[0:0]$10078 \logical_op__is_32bit$43
+ assign $2\logical_op__is_signed$44$next[0:0]$10079 \logical_op__is_signed$44
+ assign $2\logical_op__oe__oe$35$next[0:0]$10080 \logical_op__oe__oe$35
+ assign $2\logical_op__oe__ok$36$next[0:0]$10081 \logical_op__oe__ok$36
+ assign $2\logical_op__output_carry$42$next[0:0]$10082 \logical_op__output_carry$42
+ assign $2\logical_op__rc__ok$34$next[0:0]$10083 \logical_op__rc__ok$34
+ assign $2\logical_op__rc__rc$33$next[0:0]$10084 \logical_op__rc__rc$33
+ assign $2\logical_op__write_cr0$41$next[0:0]$10085 \logical_op__write_cr0$41
+ assign $2\logical_op__zero_a$38$next[0:0]$10086 \logical_op__zero_a$38
end
case
- assign $1\logical_op__data_len$45$next[3:0]$10103 \logical_op__data_len$45
- assign $1\logical_op__fn_unit$30$next[13:0]$10104 \logical_op__fn_unit$30
- assign $1\logical_op__imm_data__data$31$next[63:0]$10105 \logical_op__imm_data__data$31
- assign $1\logical_op__imm_data__ok$32$next[0:0]$10106 \logical_op__imm_data__ok$32
- assign $1\logical_op__input_carry$39$next[1:0]$10107 \logical_op__input_carry$39
- assign $1\logical_op__insn$46$next[31:0]$10108 \logical_op__insn$46
- assign $1\logical_op__insn_type$29$next[6:0]$10109 \logical_op__insn_type$29
- assign $1\logical_op__invert_in$37$next[0:0]$10110 \logical_op__invert_in$37
- assign $1\logical_op__invert_out$40$next[0:0]$10111 \logical_op__invert_out$40
- assign $1\logical_op__is_32bit$43$next[0:0]$10112 \logical_op__is_32bit$43
- assign $1\logical_op__is_signed$44$next[0:0]$10113 \logical_op__is_signed$44
- assign $1\logical_op__oe__oe$35$next[0:0]$10114 \logical_op__oe__oe$35
- assign $1\logical_op__oe__ok$36$next[0:0]$10115 \logical_op__oe__ok$36
- assign $1\logical_op__output_carry$42$next[0:0]$10116 \logical_op__output_carry$42
- assign $1\logical_op__rc__ok$34$next[0:0]$10117 \logical_op__rc__ok$34
- assign $1\logical_op__rc__rc$33$next[0:0]$10118 \logical_op__rc__rc$33
- assign $1\logical_op__write_cr0$41$next[0:0]$10119 \logical_op__write_cr0$41
- assign $1\logical_op__zero_a$38$next[0:0]$10120 \logical_op__zero_a$38
+ assign $1\logical_op__data_len$45$next[3:0]$10051 \logical_op__data_len$45
+ assign $1\logical_op__fn_unit$30$next[13:0]$10052 \logical_op__fn_unit$30
+ assign $1\logical_op__imm_data__data$31$next[63:0]$10053 \logical_op__imm_data__data$31
+ assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 \logical_op__imm_data__ok$32
+ assign $1\logical_op__input_carry$39$next[1:0]$10055 \logical_op__input_carry$39
+ assign $1\logical_op__insn$46$next[31:0]$10056 \logical_op__insn$46
+ assign $1\logical_op__insn_type$29$next[6:0]$10057 \logical_op__insn_type$29
+ assign $1\logical_op__invert_in$37$next[0:0]$10058 \logical_op__invert_in$37
+ assign $1\logical_op__invert_out$40$next[0:0]$10059 \logical_op__invert_out$40
+ assign $1\logical_op__is_32bit$43$next[0:0]$10060 \logical_op__is_32bit$43
+ assign $1\logical_op__is_signed$44$next[0:0]$10061 \logical_op__is_signed$44
+ assign $1\logical_op__oe__oe$35$next[0:0]$10062 \logical_op__oe__oe$35
+ assign $1\logical_op__oe__ok$36$next[0:0]$10063 \logical_op__oe__ok$36
+ assign $1\logical_op__output_carry$42$next[0:0]$10064 \logical_op__output_carry$42
+ assign $1\logical_op__rc__ok$34$next[0:0]$10065 \logical_op__rc__ok$34
+ assign $1\logical_op__rc__rc$33$next[0:0]$10066 \logical_op__rc__rc$33
+ assign $1\logical_op__write_cr0$41$next[0:0]$10067 \logical_op__write_cr0$41
+ assign $1\logical_op__zero_a$38$next[0:0]$10068 \logical_op__zero_a$38
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\logical_op__imm_data__data$31$next[63:0]$10139 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\logical_op__imm_data__ok$32$next[0:0]$10140 1'0
- assign $3\logical_op__rc__rc$33$next[0:0]$10144 1'0
- assign $3\logical_op__rc__ok$34$next[0:0]$10143 1'0
- assign $3\logical_op__oe__oe$35$next[0:0]$10141 1'0
- assign $3\logical_op__oe__ok$36$next[0:0]$10142 1'0
+ assign $3\logical_op__imm_data__data$31$next[63:0]$10087 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 1'0
+ assign $3\logical_op__rc__rc$33$next[0:0]$10092 1'0
+ assign $3\logical_op__rc__ok$34$next[0:0]$10091 1'0
+ assign $3\logical_op__oe__oe$35$next[0:0]$10089 1'0
+ assign $3\logical_op__oe__ok$36$next[0:0]$10090 1'0
case
- assign $3\logical_op__imm_data__data$31$next[63:0]$10139 $1\logical_op__imm_data__data$31$next[63:0]$10105
- assign $3\logical_op__imm_data__ok$32$next[0:0]$10140 $1\logical_op__imm_data__ok$32$next[0:0]$10106
- assign $3\logical_op__oe__oe$35$next[0:0]$10141 $1\logical_op__oe__oe$35$next[0:0]$10114
- assign $3\logical_op__oe__ok$36$next[0:0]$10142 $1\logical_op__oe__ok$36$next[0:0]$10115
- assign $3\logical_op__rc__ok$34$next[0:0]$10143 $1\logical_op__rc__ok$34$next[0:0]$10117
- assign $3\logical_op__rc__rc$33$next[0:0]$10144 $1\logical_op__rc__rc$33$next[0:0]$10118
+ assign $3\logical_op__imm_data__data$31$next[63:0]$10087 $1\logical_op__imm_data__data$31$next[63:0]$10053
+ assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 $1\logical_op__imm_data__ok$32$next[0:0]$10054
+ assign $3\logical_op__oe__oe$35$next[0:0]$10089 $1\logical_op__oe__oe$35$next[0:0]$10062
+ assign $3\logical_op__oe__ok$36$next[0:0]$10090 $1\logical_op__oe__ok$36$next[0:0]$10063
+ assign $3\logical_op__rc__ok$34$next[0:0]$10091 $1\logical_op__rc__ok$34$next[0:0]$10065
+ assign $3\logical_op__rc__rc$33$next[0:0]$10092 $1\logical_op__rc__rc$33$next[0:0]$10066
end
sync always
- update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10085
- update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10086
- update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10087
- update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10088
- update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10089
- update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10090
- update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10091
- update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10092
- update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10093
- update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10094
- update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10095
- update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10096
- update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10097
- update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10098
- update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10099
- update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10100
- update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10101
- update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10102
+ update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10033
+ update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10034
+ update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10035
+ update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10036
+ update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10037
+ update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10038
+ update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10039
+ update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10040
+ update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10041
+ update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10042
+ update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10043
+ update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10044
+ update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10045
+ update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10046
+ update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10047
+ update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10048
+ update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10049
+ update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10050
end
- attribute \src "libresoc.v:174916.3-174930.6"
- process $proc$libresoc.v:174916$10145
+ attribute \src "libresoc.v:174580.3-174594.6"
+ process $proc$libresoc.v:174580$10093
assign { } { }
assign { } { }
- assign $0\ra$47$next[63:0]$10146 $1\ra$47$next[63:0]$10147
- attribute \src "libresoc.v:174917.5-174917.29"
+ assign $0\ra$47$next[63:0]$10094 $1\ra$47$next[63:0]$10095
+ attribute \src "libresoc.v:174581.5-174581.29"
switch \initial
- attribute \src "libresoc.v:174917.9-174917.17"
+ attribute \src "libresoc.v:174581.9-174581.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ra$47$next[63:0]$10147 $2\ra$47$next[63:0]$10148
+ assign $1\ra$47$next[63:0]$10095 $2\ra$47$next[63:0]$10096
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ra$47$next[63:0]$10148 \ra
+ assign $2\ra$47$next[63:0]$10096 \ra
case
- assign $2\ra$47$next[63:0]$10148 \ra$47
+ assign $2\ra$47$next[63:0]$10096 \ra$47
end
case
- assign $1\ra$47$next[63:0]$10147 \ra$47
+ assign $1\ra$47$next[63:0]$10095 \ra$47
end
sync always
- update \ra$47$next $0\ra$47$next[63:0]$10146
+ update \ra$47$next $0\ra$47$next[63:0]$10094
end
- attribute \src "libresoc.v:174931.3-174945.6"
- process $proc$libresoc.v:174931$10149
+ attribute \src "libresoc.v:174595.3-174609.6"
+ process $proc$libresoc.v:174595$10097
assign { } { }
assign { } { }
- assign $0\rb$48$next[63:0]$10150 $1\rb$48$next[63:0]$10151
- attribute \src "libresoc.v:174932.5-174932.29"
+ assign $0\rb$48$next[63:0]$10098 $1\rb$48$next[63:0]$10099
+ attribute \src "libresoc.v:174596.5-174596.29"
switch \initial
- attribute \src "libresoc.v:174932.9-174932.17"
+ attribute \src "libresoc.v:174596.9-174596.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rb$48$next[63:0]$10151 $2\rb$48$next[63:0]$10152
+ assign $1\rb$48$next[63:0]$10099 $2\rb$48$next[63:0]$10100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\rb$48$next[63:0]$10152 \rb
+ assign $2\rb$48$next[63:0]$10100 \rb
case
- assign $2\rb$48$next[63:0]$10152 \rb$48
+ assign $2\rb$48$next[63:0]$10100 \rb$48
end
case
- assign $1\rb$48$next[63:0]$10151 \rb$48
+ assign $1\rb$48$next[63:0]$10099 \rb$48
end
sync always
- update \rb$48$next $0\rb$48$next[63:0]$10150
+ update \rb$48$next $0\rb$48$next[63:0]$10098
end
- attribute \src "libresoc.v:174946.3-174960.6"
- process $proc$libresoc.v:174946$10153
+ attribute \src "libresoc.v:174610.3-174624.6"
+ process $proc$libresoc.v:174610$10101
assign { } { }
assign { } { }
- assign $0\xer_so$49$next[0:0]$10154 $1\xer_so$49$next[0:0]$10155
- attribute \src "libresoc.v:174947.5-174947.29"
+ assign $0\xer_so$49$next[0:0]$10102 $1\xer_so$49$next[0:0]$10103
+ attribute \src "libresoc.v:174611.5-174611.29"
switch \initial
- attribute \src "libresoc.v:174947.9-174947.17"
+ attribute \src "libresoc.v:174611.9-174611.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$49$next[0:0]$10155 $2\xer_so$49$next[0:0]$10156
+ assign $1\xer_so$49$next[0:0]$10103 $2\xer_so$49$next[0:0]$10104
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so$49$next[0:0]$10156 \xer_so
+ assign $2\xer_so$49$next[0:0]$10104 \xer_so
case
- assign $2\xer_so$49$next[0:0]$10156 \xer_so$49
+ assign $2\xer_so$49$next[0:0]$10104 \xer_so$49
end
case
- assign $1\xer_so$49$next[0:0]$10155 \xer_so$49
+ assign $1\xer_so$49$next[0:0]$10103 \xer_so$49
end
sync always
- update \xer_so$49$next $0\xer_so$49$next[0:0]$10154
+ update \xer_so$49$next $0\xer_so$49$next[0:0]$10102
end
- attribute \src "libresoc.v:174961.3-174975.6"
- process $proc$libresoc.v:174961$10157
+ attribute \src "libresoc.v:174625.3-174639.6"
+ process $proc$libresoc.v:174625$10105
assign { } { }
assign { } { }
- assign $0\divisor_neg$50$next[0:0]$10158 $1\divisor_neg$50$next[0:0]$10159
- attribute \src "libresoc.v:174962.5-174962.29"
+ assign $0\divisor_neg$50$next[0:0]$10106 $1\divisor_neg$50$next[0:0]$10107
+ attribute \src "libresoc.v:174626.5-174626.29"
switch \initial
- attribute \src "libresoc.v:174962.9-174962.17"
+ attribute \src "libresoc.v:174626.9-174626.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\divisor_neg$50$next[0:0]$10159 $2\divisor_neg$50$next[0:0]$10160
+ assign $1\divisor_neg$50$next[0:0]$10107 $2\divisor_neg$50$next[0:0]$10108
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\divisor_neg$50$next[0:0]$10160 \divisor_neg
+ assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg
case
- assign $2\divisor_neg$50$next[0:0]$10160 \divisor_neg$50
+ assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg$50
end
case
- assign $1\divisor_neg$50$next[0:0]$10159 \divisor_neg$50
+ assign $1\divisor_neg$50$next[0:0]$10107 \divisor_neg$50
end
sync always
- update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10158
+ update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10106
end
- attribute \src "libresoc.v:174976.3-174990.6"
- process $proc$libresoc.v:174976$10161
+ attribute \src "libresoc.v:174640.3-174654.6"
+ process $proc$libresoc.v:174640$10109
assign { } { }
assign { } { }
- assign $0\dividend_neg$51$next[0:0]$10162 $1\dividend_neg$51$next[0:0]$10163
- attribute \src "libresoc.v:174977.5-174977.29"
+ assign $0\dividend_neg$51$next[0:0]$10110 $1\dividend_neg$51$next[0:0]$10111
+ attribute \src "libresoc.v:174641.5-174641.29"
switch \initial
- attribute \src "libresoc.v:174977.9-174977.17"
+ attribute \src "libresoc.v:174641.9-174641.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dividend_neg$51$next[0:0]$10163 $2\dividend_neg$51$next[0:0]$10164
+ assign $1\dividend_neg$51$next[0:0]$10111 $2\dividend_neg$51$next[0:0]$10112
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dividend_neg$51$next[0:0]$10164 \dividend_neg
+ assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg
case
- assign $2\dividend_neg$51$next[0:0]$10164 \dividend_neg$51
+ assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg$51
end
case
- assign $1\dividend_neg$51$next[0:0]$10163 \dividend_neg$51
+ assign $1\dividend_neg$51$next[0:0]$10111 \dividend_neg$51
end
sync always
- update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10162
+ update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10110
end
- attribute \src "libresoc.v:174991.3-175005.6"
- process $proc$libresoc.v:174991$10165
+ attribute \src "libresoc.v:174655.3-174669.6"
+ process $proc$libresoc.v:174655$10113
assign { } { }
assign { } { }
- assign $0\dive_abs_ov32$52$next[0:0]$10166 $1\dive_abs_ov32$52$next[0:0]$10167
- attribute \src "libresoc.v:174992.5-174992.29"
+ assign $0\dive_abs_ov32$52$next[0:0]$10114 $1\dive_abs_ov32$52$next[0:0]$10115
+ attribute \src "libresoc.v:174656.5-174656.29"
switch \initial
- attribute \src "libresoc.v:174992.9-174992.17"
+ attribute \src "libresoc.v:174656.9-174656.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dive_abs_ov32$52$next[0:0]$10167 $2\dive_abs_ov32$52$next[0:0]$10168
+ assign $1\dive_abs_ov32$52$next[0:0]$10115 $2\dive_abs_ov32$52$next[0:0]$10116
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dive_abs_ov32$52$next[0:0]$10168 \dive_abs_ov32
+ assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32
case
- assign $2\dive_abs_ov32$52$next[0:0]$10168 \dive_abs_ov32$52
+ assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32$52
end
case
- assign $1\dive_abs_ov32$52$next[0:0]$10167 \dive_abs_ov32$52
+ assign $1\dive_abs_ov32$52$next[0:0]$10115 \dive_abs_ov32$52
end
sync always
- update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10166
+ update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10114
end
- attribute \src "libresoc.v:175006.3-175020.6"
- process $proc$libresoc.v:175006$10169
+ attribute \src "libresoc.v:174670.3-174684.6"
+ process $proc$libresoc.v:174670$10117
assign { } { }
assign { } { }
- assign $0\dive_abs_ov64$53$next[0:0]$10170 $1\dive_abs_ov64$53$next[0:0]$10171
- attribute \src "libresoc.v:175007.5-175007.29"
+ assign $0\dive_abs_ov64$53$next[0:0]$10118 $1\dive_abs_ov64$53$next[0:0]$10119
+ attribute \src "libresoc.v:174671.5-174671.29"
switch \initial
- attribute \src "libresoc.v:175007.9-175007.17"
+ attribute \src "libresoc.v:174671.9-174671.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dive_abs_ov64$53$next[0:0]$10171 $2\dive_abs_ov64$53$next[0:0]$10172
+ assign $1\dive_abs_ov64$53$next[0:0]$10119 $2\dive_abs_ov64$53$next[0:0]$10120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dive_abs_ov64$53$next[0:0]$10172 \dive_abs_ov64
+ assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64
case
- assign $2\dive_abs_ov64$53$next[0:0]$10172 \dive_abs_ov64$53
+ assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64$53
end
case
- assign $1\dive_abs_ov64$53$next[0:0]$10171 \dive_abs_ov64$53
+ assign $1\dive_abs_ov64$53$next[0:0]$10119 \dive_abs_ov64$53
end
sync always
- update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10170
+ update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10118
end
- attribute \src "libresoc.v:175021.3-175035.6"
- process $proc$libresoc.v:175021$10173
+ attribute \src "libresoc.v:174685.3-174699.6"
+ process $proc$libresoc.v:174685$10121
assign { } { }
assign { } { }
- assign $0\div_by_zero$54$next[0:0]$10174 $1\div_by_zero$54$next[0:0]$10175
- attribute \src "libresoc.v:175022.5-175022.29"
+ assign $0\div_by_zero$54$next[0:0]$10122 $1\div_by_zero$54$next[0:0]$10123
+ attribute \src "libresoc.v:174686.5-174686.29"
switch \initial
- attribute \src "libresoc.v:175022.9-175022.17"
+ attribute \src "libresoc.v:174686.9-174686.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\div_by_zero$54$next[0:0]$10175 $2\div_by_zero$54$next[0:0]$10176
+ assign $1\div_by_zero$54$next[0:0]$10123 $2\div_by_zero$54$next[0:0]$10124
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\div_by_zero$54$next[0:0]$10176 \div_by_zero
+ assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero
case
- assign $2\div_by_zero$54$next[0:0]$10176 \div_by_zero$54
+ assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero$54
end
case
- assign $1\div_by_zero$54$next[0:0]$10175 \div_by_zero$54
+ assign $1\div_by_zero$54$next[0:0]$10123 \div_by_zero$54
end
sync always
- update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10174
+ update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10122
end
- attribute \src "libresoc.v:175036.3-175050.6"
- process $proc$libresoc.v:175036$10177
+ attribute \src "libresoc.v:174700.3-174714.6"
+ process $proc$libresoc.v:174700$10125
assign { } { }
assign { } { }
- assign $0\dividend$68$next[127:0]$10178 $1\dividend$68$next[127:0]$10179
- attribute \src "libresoc.v:175037.5-175037.29"
+ assign $0\dividend$68$next[127:0]$10126 $1\dividend$68$next[127:0]$10127
+ attribute \src "libresoc.v:174701.5-174701.29"
switch \initial
- attribute \src "libresoc.v:175037.9-175037.17"
+ attribute \src "libresoc.v:174701.9-174701.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dividend$68$next[127:0]$10179 $2\dividend$68$next[127:0]$10180
+ assign $1\dividend$68$next[127:0]$10127 $2\dividend$68$next[127:0]$10128
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dividend$68$next[127:0]$10180 \dividend
+ assign $2\dividend$68$next[127:0]$10128 \dividend
case
- assign $2\dividend$68$next[127:0]$10180 \dividend$68
+ assign $2\dividend$68$next[127:0]$10128 \dividend$68
end
case
- assign $1\dividend$68$next[127:0]$10179 \dividend$68
+ assign $1\dividend$68$next[127:0]$10127 \dividend$68
end
sync always
- update \dividend$68$next $0\dividend$68$next[127:0]$10178
+ update \dividend$68$next $0\dividend$68$next[127:0]$10126
end
- attribute \src "libresoc.v:175051.3-175065.6"
- process $proc$libresoc.v:175051$10181
+ attribute \src "libresoc.v:174715.3-174729.6"
+ process $proc$libresoc.v:174715$10129
assign { } { }
assign { } { }
- assign $0\divisor_radicand$65$next[63:0]$10182 $1\divisor_radicand$65$next[63:0]$10183
- attribute \src "libresoc.v:175052.5-175052.29"
+ assign $0\divisor_radicand$65$next[63:0]$10130 $1\divisor_radicand$65$next[63:0]$10131
+ attribute \src "libresoc.v:174716.5-174716.29"
switch \initial
- attribute \src "libresoc.v:175052.9-175052.17"
+ attribute \src "libresoc.v:174716.9-174716.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\divisor_radicand$65$next[63:0]$10183 $2\divisor_radicand$65$next[63:0]$10184
+ assign $1\divisor_radicand$65$next[63:0]$10131 $2\divisor_radicand$65$next[63:0]$10132
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\divisor_radicand$65$next[63:0]$10184 \divisor_radicand
+ assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand
case
- assign $2\divisor_radicand$65$next[63:0]$10184 \divisor_radicand$65
+ assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand$65
end
case
- assign $1\divisor_radicand$65$next[63:0]$10183 \divisor_radicand$65
+ assign $1\divisor_radicand$65$next[63:0]$10131 \divisor_radicand$65
end
sync always
- update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10182
+ update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10130
end
- attribute \src "libresoc.v:175066.3-175080.6"
- process $proc$libresoc.v:175066$10185
+ attribute \src "libresoc.v:174730.3-174744.6"
+ process $proc$libresoc.v:174730$10133
assign { } { }
assign { } { }
- assign $0\operation$69$next[1:0]$10186 $1\operation$69$next[1:0]$10187
- attribute \src "libresoc.v:175067.5-175067.29"
+ assign $0\operation$69$next[1:0]$10134 $1\operation$69$next[1:0]$10135
+ attribute \src "libresoc.v:174731.5-174731.29"
switch \initial
- attribute \src "libresoc.v:175067.9-175067.17"
+ attribute \src "libresoc.v:174731.9-174731.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\operation$69$next[1:0]$10187 $2\operation$69$next[1:0]$10188
+ assign $1\operation$69$next[1:0]$10135 $2\operation$69$next[1:0]$10136
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\operation$69$next[1:0]$10188 \operation
+ assign $2\operation$69$next[1:0]$10136 \operation
case
- assign $2\operation$69$next[1:0]$10188 \operation$69
+ assign $2\operation$69$next[1:0]$10136 \operation$69
end
case
- assign $1\operation$69$next[1:0]$10187 \operation$69
+ assign $1\operation$69$next[1:0]$10135 \operation$69
end
sync always
- update \operation$69$next $0\operation$69$next[1:0]$10186
+ update \operation$69$next $0\operation$69$next[1:0]$10134
end
- connect \$56 $sshl$libresoc.v:174683$9995_Y
- connect \$55 $pos$libresoc.v:174684$9997_Y
- connect \$59 $not$libresoc.v:174685$9998_Y
- connect \$61 $ge$libresoc.v:174686$9999_Y
- connect \$63 $and$libresoc.v:174687$10000_Y
- connect \$66 $and$libresoc.v:174688$10001_Y
+ connect \$56 $sshl$libresoc.v:174347$9943_Y
+ connect \$55 $pos$libresoc.v:174348$9945_Y
+ connect \$59 $not$libresoc.v:174349$9946_Y
+ connect \$61 $ge$libresoc.v:174350$9947_Y
+ connect \$63 $and$libresoc.v:174351$9948_Y
+ connect \$66 $and$libresoc.v:174352$9949_Y
connect \p_ready_o \empty
connect \n_valid_o \$63
connect \remainder \$55
connect \muxid$1 \muxid$28
connect \div_state_init_dividend \dividend
end
-attribute \src "libresoc.v:175100.1-176645.10"
+attribute \src "libresoc.v:174764.1-176309.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start"
attribute \generator "nMigen"
module \pipe_start
- attribute \src "libresoc.v:176451.3-176463.6"
- wire $0\div_by_zero$next[0:0]$10298
- attribute \src "libresoc.v:176237.3-176238.39"
+ attribute \src "libresoc.v:176115.3-176127.6"
+ wire $0\div_by_zero$next[0:0]$10246
+ attribute \src "libresoc.v:175901.3-175902.39"
wire $0\div_by_zero[0:0]
- attribute \src "libresoc.v:176425.3-176437.6"
- wire $0\dive_abs_ov32$next[0:0]$10292
- attribute \src "libresoc.v:176241.3-176242.43"
+ attribute \src "libresoc.v:176089.3-176101.6"
+ wire $0\dive_abs_ov32$next[0:0]$10240
+ attribute \src "libresoc.v:175905.3-175906.43"
wire $0\dive_abs_ov32[0:0]
- attribute \src "libresoc.v:176438.3-176450.6"
- wire $0\dive_abs_ov64$next[0:0]$10295
- attribute \src "libresoc.v:176239.3-176240.43"
+ attribute \src "libresoc.v:176102.3-176114.6"
+ wire $0\dive_abs_ov64$next[0:0]$10243
+ attribute \src "libresoc.v:175903.3-175904.43"
wire $0\dive_abs_ov64[0:0]
- attribute \src "libresoc.v:176464.3-176476.6"
- wire width 128 $0\dividend$next[127:0]$10301
- attribute \src "libresoc.v:176235.3-176236.33"
+ attribute \src "libresoc.v:176128.3-176140.6"
+ wire width 128 $0\dividend$next[127:0]$10249
+ attribute \src "libresoc.v:175899.3-175900.33"
wire width 128 $0\dividend[127:0]
- attribute \src "libresoc.v:176412.3-176424.6"
- wire $0\dividend_neg$next[0:0]$10289
- attribute \src "libresoc.v:176243.3-176244.41"
+ attribute \src "libresoc.v:176076.3-176088.6"
+ wire $0\dividend_neg$next[0:0]$10237
+ attribute \src "libresoc.v:175907.3-175908.41"
wire $0\dividend_neg[0:0]
- attribute \src "libresoc.v:176399.3-176411.6"
- wire $0\divisor_neg$next[0:0]$10286
- attribute \src "libresoc.v:176245.3-176246.39"
+ attribute \src "libresoc.v:176063.3-176075.6"
+ wire $0\divisor_neg$next[0:0]$10234
+ attribute \src "libresoc.v:175909.3-175910.39"
wire $0\divisor_neg[0:0]
- attribute \src "libresoc.v:176477.3-176489.6"
- wire width 64 $0\divisor_radicand$next[63:0]$10304
- attribute \src "libresoc.v:176233.3-176234.49"
+ attribute \src "libresoc.v:176141.3-176153.6"
+ wire width 64 $0\divisor_radicand$next[63:0]$10252
+ attribute \src "libresoc.v:175897.3-175898.49"
wire width 64 $0\divisor_radicand[63:0]
- attribute \src "libresoc.v:175101.7-175101.20"
+ attribute \src "libresoc.v:174765.7-174765.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 4 $0\logical_op__data_len$next[3:0]$10317
- attribute \src "libresoc.v:176285.3-176286.57"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 4 $0\logical_op__data_len$next[3:0]$10265
+ attribute \src "libresoc.v:175949.3-175950.57"
wire width 4 $0\logical_op__data_len[3:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 14 $0\logical_op__fn_unit$next[13:0]$10318
- attribute \src "libresoc.v:176255.3-176256.55"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 14 $0\logical_op__fn_unit$next[13:0]$10266
+ attribute \src "libresoc.v:175919.3-175920.55"
wire width 14 $0\logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 64 $0\logical_op__imm_data__data$next[63:0]$10319
- attribute \src "libresoc.v:176257.3-176258.69"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 64 $0\logical_op__imm_data__data$next[63:0]$10267
+ attribute \src "libresoc.v:175921.3-175922.69"
wire width 64 $0\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__imm_data__ok$next[0:0]$10320
- attribute \src "libresoc.v:176259.3-176260.65"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__imm_data__ok$next[0:0]$10268
+ attribute \src "libresoc.v:175923.3-175924.65"
wire $0\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 2 $0\logical_op__input_carry$next[1:0]$10321
- attribute \src "libresoc.v:176273.3-176274.63"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 2 $0\logical_op__input_carry$next[1:0]$10269
+ attribute \src "libresoc.v:175937.3-175938.63"
wire width 2 $0\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 32 $0\logical_op__insn$next[31:0]$10322
- attribute \src "libresoc.v:176287.3-176288.49"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 32 $0\logical_op__insn$next[31:0]$10270
+ attribute \src "libresoc.v:175951.3-175952.49"
wire width 32 $0\logical_op__insn[31:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 7 $0\logical_op__insn_type$next[6:0]$10323
- attribute \src "libresoc.v:176253.3-176254.59"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 7 $0\logical_op__insn_type$next[6:0]$10271
+ attribute \src "libresoc.v:175917.3-175918.59"
wire width 7 $0\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__invert_in$next[0:0]$10324
- attribute \src "libresoc.v:176269.3-176270.59"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__invert_in$next[0:0]$10272
+ attribute \src "libresoc.v:175933.3-175934.59"
wire $0\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__invert_out$next[0:0]$10325
- attribute \src "libresoc.v:176275.3-176276.61"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__invert_out$next[0:0]$10273
+ attribute \src "libresoc.v:175939.3-175940.61"
wire $0\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__is_32bit$next[0:0]$10326
- attribute \src "libresoc.v:176281.3-176282.57"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__is_32bit$next[0:0]$10274
+ attribute \src "libresoc.v:175945.3-175946.57"
wire $0\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__is_signed$next[0:0]$10327
- attribute \src "libresoc.v:176283.3-176284.59"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__is_signed$next[0:0]$10275
+ attribute \src "libresoc.v:175947.3-175948.59"
wire $0\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__oe__oe$next[0:0]$10328
- attribute \src "libresoc.v:176265.3-176266.53"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__oe__oe$next[0:0]$10276
+ attribute \src "libresoc.v:175929.3-175930.53"
wire $0\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__oe__ok$next[0:0]$10329
- attribute \src "libresoc.v:176267.3-176268.53"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__oe__ok$next[0:0]$10277
+ attribute \src "libresoc.v:175931.3-175932.53"
wire $0\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__output_carry$next[0:0]$10330
- attribute \src "libresoc.v:176279.3-176280.65"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__output_carry$next[0:0]$10278
+ attribute \src "libresoc.v:175943.3-175944.65"
wire $0\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__rc__ok$next[0:0]$10331
- attribute \src "libresoc.v:176263.3-176264.53"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__rc__ok$next[0:0]$10279
+ attribute \src "libresoc.v:175927.3-175928.53"
wire $0\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__rc__rc$next[0:0]$10332
- attribute \src "libresoc.v:176261.3-176262.53"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__rc__rc$next[0:0]$10280
+ attribute \src "libresoc.v:175925.3-175926.53"
wire $0\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__write_cr0$next[0:0]$10333
- attribute \src "libresoc.v:176277.3-176278.59"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__write_cr0$next[0:0]$10281
+ attribute \src "libresoc.v:175941.3-175942.59"
wire $0\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $0\logical_op__zero_a$next[0:0]$10334
- attribute \src "libresoc.v:176271.3-176272.53"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $0\logical_op__zero_a$next[0:0]$10282
+ attribute \src "libresoc.v:175935.3-175936.53"
wire $0\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:176521.3-176533.6"
- wire width 2 $0\muxid$next[1:0]$10314
- attribute \src "libresoc.v:176289.3-176290.27"
+ attribute \src "libresoc.v:176185.3-176197.6"
+ wire width 2 $0\muxid$next[1:0]$10262
+ attribute \src "libresoc.v:175953.3-175954.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:176490.3-176502.6"
- wire width 2 $0\operation$next[1:0]$10307
- attribute \src "libresoc.v:176231.3-176232.35"
+ attribute \src "libresoc.v:176154.3-176166.6"
+ wire width 2 $0\operation$next[1:0]$10255
+ attribute \src "libresoc.v:175895.3-175896.35"
wire width 2 $0\operation[1:0]
- attribute \src "libresoc.v:176503.3-176520.6"
- wire $0\r_busy$next[0:0]$10310
- attribute \src "libresoc.v:176291.3-176292.29"
+ attribute \src "libresoc.v:176167.3-176184.6"
+ wire $0\r_busy$next[0:0]$10258
+ attribute \src "libresoc.v:175955.3-175956.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:176576.3-176588.6"
- wire width 64 $0\ra$next[63:0]$10360
- attribute \src "libresoc.v:176251.3-176252.21"
+ attribute \src "libresoc.v:176240.3-176252.6"
+ wire width 64 $0\ra$next[63:0]$10308
+ attribute \src "libresoc.v:175915.3-175916.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:176589.3-176601.6"
- wire width 64 $0\rb$next[63:0]$10363
- attribute \src "libresoc.v:176249.3-176250.21"
+ attribute \src "libresoc.v:176253.3-176265.6"
+ wire width 64 $0\rb$next[63:0]$10311
+ attribute \src "libresoc.v:175913.3-175914.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:176602.3-176614.6"
- wire $0\xer_so$next[0:0]$10366
- attribute \src "libresoc.v:176247.3-176248.29"
+ attribute \src "libresoc.v:176266.3-176278.6"
+ wire $0\xer_so$next[0:0]$10314
+ attribute \src "libresoc.v:175911.3-175912.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:176451.3-176463.6"
- wire $1\div_by_zero$next[0:0]$10299
- attribute \src "libresoc.v:175110.7-175110.25"
+ attribute \src "libresoc.v:176115.3-176127.6"
+ wire $1\div_by_zero$next[0:0]$10247
+ attribute \src "libresoc.v:174774.7-174774.25"
wire $1\div_by_zero[0:0]
- attribute \src "libresoc.v:176425.3-176437.6"
- wire $1\dive_abs_ov32$next[0:0]$10293
- attribute \src "libresoc.v:175117.7-175117.27"
+ attribute \src "libresoc.v:176089.3-176101.6"
+ wire $1\dive_abs_ov32$next[0:0]$10241
+ attribute \src "libresoc.v:174781.7-174781.27"
wire $1\dive_abs_ov32[0:0]
- attribute \src "libresoc.v:176438.3-176450.6"
- wire $1\dive_abs_ov64$next[0:0]$10296
- attribute \src "libresoc.v:175124.7-175124.27"
+ attribute \src "libresoc.v:176102.3-176114.6"
+ wire $1\dive_abs_ov64$next[0:0]$10244
+ attribute \src "libresoc.v:174788.7-174788.27"
wire $1\dive_abs_ov64[0:0]
- attribute \src "libresoc.v:176464.3-176476.6"
- wire width 128 $1\dividend$next[127:0]$10302
- attribute \src "libresoc.v:175131.15-175131.63"
+ attribute \src "libresoc.v:176128.3-176140.6"
+ wire width 128 $1\dividend$next[127:0]$10250
+ attribute \src "libresoc.v:174795.15-174795.63"
wire width 128 $1\dividend[127:0]
- attribute \src "libresoc.v:176412.3-176424.6"
- wire $1\dividend_neg$next[0:0]$10290
- attribute \src "libresoc.v:175138.7-175138.26"
+ attribute \src "libresoc.v:176076.3-176088.6"
+ wire $1\dividend_neg$next[0:0]$10238
+ attribute \src "libresoc.v:174802.7-174802.26"
wire $1\dividend_neg[0:0]
- attribute \src "libresoc.v:176399.3-176411.6"
- wire $1\divisor_neg$next[0:0]$10287
- attribute \src "libresoc.v:175145.7-175145.25"
+ attribute \src "libresoc.v:176063.3-176075.6"
+ wire $1\divisor_neg$next[0:0]$10235
+ attribute \src "libresoc.v:174809.7-174809.25"
wire $1\divisor_neg[0:0]
- attribute \src "libresoc.v:176477.3-176489.6"
- wire width 64 $1\divisor_radicand$next[63:0]$10305
- attribute \src "libresoc.v:175152.14-175152.53"
+ attribute \src "libresoc.v:176141.3-176153.6"
+ wire width 64 $1\divisor_radicand$next[63:0]$10253
+ attribute \src "libresoc.v:174816.14-174816.53"
wire width 64 $1\divisor_radicand[63:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 4 $1\logical_op__data_len$next[3:0]$10335
- attribute \src "libresoc.v:175435.13-175435.40"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 4 $1\logical_op__data_len$next[3:0]$10283
+ attribute \src "libresoc.v:175099.13-175099.40"
wire width 4 $1\logical_op__data_len[3:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 14 $1\logical_op__fn_unit$next[13:0]$10336
- attribute \src "libresoc.v:175459.14-175459.44"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 14 $1\logical_op__fn_unit$next[13:0]$10284
+ attribute \src "libresoc.v:175123.14-175123.44"
wire width 14 $1\logical_op__fn_unit[13:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 64 $1\logical_op__imm_data__data$next[63:0]$10337
- attribute \src "libresoc.v:175498.14-175498.63"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 64 $1\logical_op__imm_data__data$next[63:0]$10285
+ attribute \src "libresoc.v:175162.14-175162.63"
wire width 64 $1\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__imm_data__ok$next[0:0]$10338
- attribute \src "libresoc.v:175507.7-175507.38"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__imm_data__ok$next[0:0]$10286
+ attribute \src "libresoc.v:175171.7-175171.38"
wire $1\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 2 $1\logical_op__input_carry$next[1:0]$10339
- attribute \src "libresoc.v:175520.13-175520.43"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 2 $1\logical_op__input_carry$next[1:0]$10287
+ attribute \src "libresoc.v:175184.13-175184.43"
wire width 2 $1\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 32 $1\logical_op__insn$next[31:0]$10340
- attribute \src "libresoc.v:175537.14-175537.38"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 32 $1\logical_op__insn$next[31:0]$10288
+ attribute \src "libresoc.v:175201.14-175201.38"
wire width 32 $1\logical_op__insn[31:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 7 $1\logical_op__insn_type$next[6:0]$10341
- attribute \src "libresoc.v:175621.13-175621.42"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 7 $1\logical_op__insn_type$next[6:0]$10289
+ attribute \src "libresoc.v:175285.13-175285.42"
wire width 7 $1\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__invert_in$next[0:0]$10342
- attribute \src "libresoc.v:175780.7-175780.35"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__invert_in$next[0:0]$10290
+ attribute \src "libresoc.v:175444.7-175444.35"
wire $1\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__invert_out$next[0:0]$10343
- attribute \src "libresoc.v:175789.7-175789.36"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__invert_out$next[0:0]$10291
+ attribute \src "libresoc.v:175453.7-175453.36"
wire $1\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__is_32bit$next[0:0]$10344
- attribute \src "libresoc.v:175798.7-175798.34"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__is_32bit$next[0:0]$10292
+ attribute \src "libresoc.v:175462.7-175462.34"
wire $1\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__is_signed$next[0:0]$10345
- attribute \src "libresoc.v:175807.7-175807.35"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__is_signed$next[0:0]$10293
+ attribute \src "libresoc.v:175471.7-175471.35"
wire $1\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__oe__oe$next[0:0]$10346
- attribute \src "libresoc.v:175816.7-175816.32"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__oe__oe$next[0:0]$10294
+ attribute \src "libresoc.v:175480.7-175480.32"
wire $1\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__oe__ok$next[0:0]$10347
- attribute \src "libresoc.v:175825.7-175825.32"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__oe__ok$next[0:0]$10295
+ attribute \src "libresoc.v:175489.7-175489.32"
wire $1\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__output_carry$next[0:0]$10348
- attribute \src "libresoc.v:175834.7-175834.38"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__output_carry$next[0:0]$10296
+ attribute \src "libresoc.v:175498.7-175498.38"
wire $1\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__rc__ok$next[0:0]$10349
- attribute \src "libresoc.v:175843.7-175843.32"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__rc__ok$next[0:0]$10297
+ attribute \src "libresoc.v:175507.7-175507.32"
wire $1\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__rc__rc$next[0:0]$10350
- attribute \src "libresoc.v:175852.7-175852.32"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__rc__rc$next[0:0]$10298
+ attribute \src "libresoc.v:175516.7-175516.32"
wire $1\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__write_cr0$next[0:0]$10351
- attribute \src "libresoc.v:175861.7-175861.35"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__write_cr0$next[0:0]$10299
+ attribute \src "libresoc.v:175525.7-175525.35"
wire $1\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $1\logical_op__zero_a$next[0:0]$10352
- attribute \src "libresoc.v:175870.7-175870.32"
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $1\logical_op__zero_a$next[0:0]$10300
+ attribute \src "libresoc.v:175534.7-175534.32"
wire $1\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:176521.3-176533.6"
- wire width 2 $1\muxid$next[1:0]$10315
- attribute \src "libresoc.v:175879.13-175879.25"
+ attribute \src "libresoc.v:176185.3-176197.6"
+ wire width 2 $1\muxid$next[1:0]$10263
+ attribute \src "libresoc.v:175543.13-175543.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:176490.3-176502.6"
- wire width 2 $1\operation$next[1:0]$10308
- attribute \src "libresoc.v:175894.13-175894.29"
+ attribute \src "libresoc.v:176154.3-176166.6"
+ wire width 2 $1\operation$next[1:0]$10256
+ attribute \src "libresoc.v:175558.13-175558.29"
wire width 2 $1\operation[1:0]
- attribute \src "libresoc.v:176503.3-176520.6"
- wire $1\r_busy$next[0:0]$10311
- attribute \src "libresoc.v:175908.7-175908.20"
+ attribute \src "libresoc.v:176167.3-176184.6"
+ wire $1\r_busy$next[0:0]$10259
+ attribute \src "libresoc.v:175572.7-175572.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:176576.3-176588.6"
- wire width 64 $1\ra$next[63:0]$10361
- attribute \src "libresoc.v:175913.14-175913.39"
+ attribute \src "libresoc.v:176240.3-176252.6"
+ wire width 64 $1\ra$next[63:0]$10309
+ attribute \src "libresoc.v:175577.14-175577.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:176589.3-176601.6"
- wire width 64 $1\rb$next[63:0]$10364
- attribute \src "libresoc.v:175924.14-175924.39"
+ attribute \src "libresoc.v:176253.3-176265.6"
+ wire width 64 $1\rb$next[63:0]$10312
+ attribute \src "libresoc.v:175588.14-175588.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:176602.3-176614.6"
- wire $1\xer_so$next[0:0]$10367
- attribute \src "libresoc.v:176223.7-176223.20"
+ attribute \src "libresoc.v:176266.3-176278.6"
+ wire $1\xer_so$next[0:0]$10315
+ attribute \src "libresoc.v:175887.7-175887.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:176534.3-176575.6"
- wire width 64 $2\logical_op__imm_data__data$next[63:0]$10353
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $2\logical_op__imm_data__ok$next[0:0]$10354
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $2\logical_op__oe__oe$next[0:0]$10355
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $2\logical_op__oe__ok$next[0:0]$10356
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $2\logical_op__rc__ok$next[0:0]$10357
- attribute \src "libresoc.v:176534.3-176575.6"
- wire $2\logical_op__rc__rc$next[0:0]$10358
- attribute \src "libresoc.v:176503.3-176520.6"
- wire $2\r_busy$next[0:0]$10312
- attribute \src "libresoc.v:176230.18-176230.118"
- wire $and$libresoc.v:176230$10253_Y
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire width 64 $2\logical_op__imm_data__data$next[63:0]$10301
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $2\logical_op__imm_data__ok$next[0:0]$10302
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $2\logical_op__oe__oe$next[0:0]$10303
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $2\logical_op__oe__ok$next[0:0]$10304
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $2\logical_op__rc__ok$next[0:0]$10305
+ attribute \src "libresoc.v:176198.3-176239.6"
+ wire $2\logical_op__rc__rc$next[0:0]$10306
+ attribute \src "libresoc.v:176167.3-176184.6"
+ wire $2\r_busy$next[0:0]$10260
+ attribute \src "libresoc.v:175894.18-175894.118"
+ wire $and$libresoc.v:175894$10201_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire output 30 \div_by_zero
wire width 64 \divisor_radicand$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
wire width 64 \divisor_radicand$next
- attribute \src "libresoc.v:175101.7-175101.15"
+ attribute \src "libresoc.v:174765.7-174765.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:176230$10253
+ cell $and $and$libresoc.v:175894$10201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$65
connect \B \p_ready_o
- connect \Y $and$libresoc.v:176230$10253_Y
+ connect \Y $and$libresoc.v:175894$10201_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:176293.14-176338.4"
+ attribute \src "libresoc.v:175957.14-176002.4"
cell \input$78 \input
connect \logical_op__data_len \input_logical_op__data_len
connect \logical_op__data_len$18 \input_logical_op__data_len$40
connect \xer_so$22 \input_xer_so$44
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:176339.10-176342.4"
+ attribute \src "libresoc.v:176003.10-176006.4"
cell \n$77 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:176343.10-176346.4"
+ attribute \src "libresoc.v:176007.10-176010.4"
cell \p$76 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:176347.15-176398.4"
+ attribute \src "libresoc.v:176011.15-176062.4"
cell \setup_stage \setup_stage
connect \div_by_zero \setup_stage_div_by_zero
connect \dive_abs_ov32 \setup_stage_dive_abs_ov32
connect \xer_so \setup_stage_xer_so
connect \xer_so$20 \setup_stage_xer_so$64
end
- attribute \src "libresoc.v:175101.7-175101.20"
- process $proc$libresoc.v:175101$10368
+ attribute \src "libresoc.v:174765.7-174765.20"
+ process $proc$libresoc.v:174765$10316
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:175110.7-175110.25"
- process $proc$libresoc.v:175110$10369
+ attribute \src "libresoc.v:174774.7-174774.25"
+ process $proc$libresoc.v:174774$10317
assign { } { }
assign $1\div_by_zero[0:0] 1'0
sync always
sync init
update \div_by_zero $1\div_by_zero[0:0]
end
- attribute \src "libresoc.v:175117.7-175117.27"
- process $proc$libresoc.v:175117$10370
+ attribute \src "libresoc.v:174781.7-174781.27"
+ process $proc$libresoc.v:174781$10318
assign { } { }
assign $1\dive_abs_ov32[0:0] 1'0
sync always
sync init
update \dive_abs_ov32 $1\dive_abs_ov32[0:0]
end
- attribute \src "libresoc.v:175124.7-175124.27"
- process $proc$libresoc.v:175124$10371
+ attribute \src "libresoc.v:174788.7-174788.27"
+ process $proc$libresoc.v:174788$10319
assign { } { }
assign $1\dive_abs_ov64[0:0] 1'0
sync always
sync init
update \dive_abs_ov64 $1\dive_abs_ov64[0:0]
end
- attribute \src "libresoc.v:175131.15-175131.63"
- process $proc$libresoc.v:175131$10372
+ attribute \src "libresoc.v:174795.15-174795.63"
+ process $proc$libresoc.v:174795$10320
assign { } { }
assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dividend $1\dividend[127:0]
end
- attribute \src "libresoc.v:175138.7-175138.26"
- process $proc$libresoc.v:175138$10373
+ attribute \src "libresoc.v:174802.7-174802.26"
+ process $proc$libresoc.v:174802$10321
assign { } { }
assign $1\dividend_neg[0:0] 1'0
sync always
sync init
update \dividend_neg $1\dividend_neg[0:0]
end
- attribute \src "libresoc.v:175145.7-175145.25"
- process $proc$libresoc.v:175145$10374
+ attribute \src "libresoc.v:174809.7-174809.25"
+ process $proc$libresoc.v:174809$10322
assign { } { }
assign $1\divisor_neg[0:0] 1'0
sync always
sync init
update \divisor_neg $1\divisor_neg[0:0]
end
- attribute \src "libresoc.v:175152.14-175152.53"
- process $proc$libresoc.v:175152$10375
+ attribute \src "libresoc.v:174816.14-174816.53"
+ process $proc$libresoc.v:174816$10323
assign { } { }
assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \divisor_radicand $1\divisor_radicand[63:0]
end
- attribute \src "libresoc.v:175435.13-175435.40"
- process $proc$libresoc.v:175435$10376
+ attribute \src "libresoc.v:175099.13-175099.40"
+ process $proc$libresoc.v:175099$10324
assign { } { }
assign $1\logical_op__data_len[3:0] 4'0000
sync always
sync init
update \logical_op__data_len $1\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:175459.14-175459.44"
- process $proc$libresoc.v:175459$10377
+ attribute \src "libresoc.v:175123.14-175123.44"
+ process $proc$libresoc.v:175123$10325
assign { } { }
assign $1\logical_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \logical_op__fn_unit $1\logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:175498.14-175498.63"
- process $proc$libresoc.v:175498$10378
+ attribute \src "libresoc.v:175162.14-175162.63"
+ process $proc$libresoc.v:175162$10326
assign { } { }
assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:175507.7-175507.38"
- process $proc$libresoc.v:175507$10379
+ attribute \src "libresoc.v:175171.7-175171.38"
+ process $proc$libresoc.v:175171$10327
assign { } { }
assign $1\logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:175520.13-175520.43"
- process $proc$libresoc.v:175520$10380
+ attribute \src "libresoc.v:175184.13-175184.43"
+ process $proc$libresoc.v:175184$10328
assign { } { }
assign $1\logical_op__input_carry[1:0] 2'00
sync always
sync init
update \logical_op__input_carry $1\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:175537.14-175537.38"
- process $proc$libresoc.v:175537$10381
+ attribute \src "libresoc.v:175201.14-175201.38"
+ process $proc$libresoc.v:175201$10329
assign { } { }
assign $1\logical_op__insn[31:0] 0
sync always
sync init
update \logical_op__insn $1\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:175621.13-175621.42"
- process $proc$libresoc.v:175621$10382
+ attribute \src "libresoc.v:175285.13-175285.42"
+ process $proc$libresoc.v:175285$10330
assign { } { }
assign $1\logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \logical_op__insn_type $1\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:175780.7-175780.35"
- process $proc$libresoc.v:175780$10383
+ attribute \src "libresoc.v:175444.7-175444.35"
+ process $proc$libresoc.v:175444$10331
assign { } { }
assign $1\logical_op__invert_in[0:0] 1'0
sync always
sync init
update \logical_op__invert_in $1\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:175789.7-175789.36"
- process $proc$libresoc.v:175789$10384
+ attribute \src "libresoc.v:175453.7-175453.36"
+ process $proc$libresoc.v:175453$10332
assign { } { }
assign $1\logical_op__invert_out[0:0] 1'0
sync always
sync init
update \logical_op__invert_out $1\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:175798.7-175798.34"
- process $proc$libresoc.v:175798$10385
+ attribute \src "libresoc.v:175462.7-175462.34"
+ process $proc$libresoc.v:175462$10333
assign { } { }
assign $1\logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \logical_op__is_32bit $1\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:175807.7-175807.35"
- process $proc$libresoc.v:175807$10386
+ attribute \src "libresoc.v:175471.7-175471.35"
+ process $proc$libresoc.v:175471$10334
assign { } { }
assign $1\logical_op__is_signed[0:0] 1'0
sync always
sync init
update \logical_op__is_signed $1\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:175816.7-175816.32"
- process $proc$libresoc.v:175816$10387
+ attribute \src "libresoc.v:175480.7-175480.32"
+ process $proc$libresoc.v:175480$10335
assign { } { }
assign $1\logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \logical_op__oe__oe $1\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:175825.7-175825.32"
- process $proc$libresoc.v:175825$10388
+ attribute \src "libresoc.v:175489.7-175489.32"
+ process $proc$libresoc.v:175489$10336
assign { } { }
assign $1\logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \logical_op__oe__ok $1\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:175834.7-175834.38"
- process $proc$libresoc.v:175834$10389
+ attribute \src "libresoc.v:175498.7-175498.38"
+ process $proc$libresoc.v:175498$10337
assign { } { }
assign $1\logical_op__output_carry[0:0] 1'0
sync always
sync init
update \logical_op__output_carry $1\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:175843.7-175843.32"
- process $proc$libresoc.v:175843$10390
+ attribute \src "libresoc.v:175507.7-175507.32"
+ process $proc$libresoc.v:175507$10338
assign { } { }
assign $1\logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \logical_op__rc__ok $1\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:175852.7-175852.32"
- process $proc$libresoc.v:175852$10391
+ attribute \src "libresoc.v:175516.7-175516.32"
+ process $proc$libresoc.v:175516$10339
assign { } { }
assign $1\logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \logical_op__rc__rc $1\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:175861.7-175861.35"
- process $proc$libresoc.v:175861$10392
+ attribute \src "libresoc.v:175525.7-175525.35"
+ process $proc$libresoc.v:175525$10340
assign { } { }
assign $1\logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:175870.7-175870.32"
- process $proc$libresoc.v:175870$10393
+ attribute \src "libresoc.v:175534.7-175534.32"
+ process $proc$libresoc.v:175534$10341
assign { } { }
assign $1\logical_op__zero_a[0:0] 1'0
sync always
sync init
update \logical_op__zero_a $1\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:175879.13-175879.25"
- process $proc$libresoc.v:175879$10394
+ attribute \src "libresoc.v:175543.13-175543.25"
+ process $proc$libresoc.v:175543$10342
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:175894.13-175894.29"
- process $proc$libresoc.v:175894$10395
+ attribute \src "libresoc.v:175558.13-175558.29"
+ process $proc$libresoc.v:175558$10343
assign { } { }
assign $1\operation[1:0] 2'00
sync always
sync init
update \operation $1\operation[1:0]
end
- attribute \src "libresoc.v:175908.7-175908.20"
- process $proc$libresoc.v:175908$10396
+ attribute \src "libresoc.v:175572.7-175572.20"
+ process $proc$libresoc.v:175572$10344
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:175913.14-175913.39"
- process $proc$libresoc.v:175913$10397
+ attribute \src "libresoc.v:175577.14-175577.39"
+ process $proc$libresoc.v:175577$10345
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:175924.14-175924.39"
- process $proc$libresoc.v:175924$10398
+ attribute \src "libresoc.v:175588.14-175588.39"
+ process $proc$libresoc.v:175588$10346
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:176223.7-176223.20"
- process $proc$libresoc.v:176223$10399
+ attribute \src "libresoc.v:175887.7-175887.20"
+ process $proc$libresoc.v:175887$10347
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:176231.3-176232.35"
- process $proc$libresoc.v:176231$10254
+ attribute \src "libresoc.v:175895.3-175896.35"
+ process $proc$libresoc.v:175895$10202
assign { } { }
assign $0\operation[1:0] \operation$next
sync posedge \coresync_clk
update \operation $0\operation[1:0]
end
- attribute \src "libresoc.v:176233.3-176234.49"
- process $proc$libresoc.v:176233$10255
+ attribute \src "libresoc.v:175897.3-175898.49"
+ process $proc$libresoc.v:175897$10203
assign { } { }
assign $0\divisor_radicand[63:0] \divisor_radicand$next
sync posedge \coresync_clk
update \divisor_radicand $0\divisor_radicand[63:0]
end
- attribute \src "libresoc.v:176235.3-176236.33"
- process $proc$libresoc.v:176235$10256
+ attribute \src "libresoc.v:175899.3-175900.33"
+ process $proc$libresoc.v:175899$10204
assign { } { }
assign $0\dividend[127:0] \dividend$next
sync posedge \coresync_clk
update \dividend $0\dividend[127:0]
end
- attribute \src "libresoc.v:176237.3-176238.39"
- process $proc$libresoc.v:176237$10257
+ attribute \src "libresoc.v:175901.3-175902.39"
+ process $proc$libresoc.v:175901$10205
assign { } { }
assign $0\div_by_zero[0:0] \div_by_zero$next
sync posedge \coresync_clk
update \div_by_zero $0\div_by_zero[0:0]
end
- attribute \src "libresoc.v:176239.3-176240.43"
- process $proc$libresoc.v:176239$10258
+ attribute \src "libresoc.v:175903.3-175904.43"
+ process $proc$libresoc.v:175903$10206
assign { } { }
assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next
sync posedge \coresync_clk
update \dive_abs_ov64 $0\dive_abs_ov64[0:0]
end
- attribute \src "libresoc.v:176241.3-176242.43"
- process $proc$libresoc.v:176241$10259
+ attribute \src "libresoc.v:175905.3-175906.43"
+ process $proc$libresoc.v:175905$10207
assign { } { }
assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next
sync posedge \coresync_clk
update \dive_abs_ov32 $0\dive_abs_ov32[0:0]
end
- attribute \src "libresoc.v:176243.3-176244.41"
- process $proc$libresoc.v:176243$10260
+ attribute \src "libresoc.v:175907.3-175908.41"
+ process $proc$libresoc.v:175907$10208
assign { } { }
assign $0\dividend_neg[0:0] \dividend_neg$next
sync posedge \coresync_clk
update \dividend_neg $0\dividend_neg[0:0]
end
- attribute \src "libresoc.v:176245.3-176246.39"
- process $proc$libresoc.v:176245$10261
+ attribute \src "libresoc.v:175909.3-175910.39"
+ process $proc$libresoc.v:175909$10209
assign { } { }
assign $0\divisor_neg[0:0] \divisor_neg$next
sync posedge \coresync_clk
update \divisor_neg $0\divisor_neg[0:0]
end
- attribute \src "libresoc.v:176247.3-176248.29"
- process $proc$libresoc.v:176247$10262
+ attribute \src "libresoc.v:175911.3-175912.29"
+ process $proc$libresoc.v:175911$10210
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:176249.3-176250.21"
- process $proc$libresoc.v:176249$10263
+ attribute \src "libresoc.v:175913.3-175914.21"
+ process $proc$libresoc.v:175913$10211
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:176251.3-176252.21"
- process $proc$libresoc.v:176251$10264
+ attribute \src "libresoc.v:175915.3-175916.21"
+ process $proc$libresoc.v:175915$10212
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:176253.3-176254.59"
- process $proc$libresoc.v:176253$10265
+ attribute \src "libresoc.v:175917.3-175918.59"
+ process $proc$libresoc.v:175917$10213
assign { } { }
assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next
sync posedge \coresync_clk
update \logical_op__insn_type $0\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:176255.3-176256.55"
- process $proc$libresoc.v:176255$10266
+ attribute \src "libresoc.v:175919.3-175920.55"
+ process $proc$libresoc.v:175919$10214
assign { } { }
assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next
sync posedge \coresync_clk
update \logical_op__fn_unit $0\logical_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:176257.3-176258.69"
- process $proc$libresoc.v:176257$10267
+ attribute \src "libresoc.v:175921.3-175922.69"
+ process $proc$libresoc.v:175921$10215
assign { } { }
assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next
sync posedge \coresync_clk
update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:176259.3-176260.65"
- process $proc$libresoc.v:176259$10268
+ attribute \src "libresoc.v:175923.3-175924.65"
+ process $proc$libresoc.v:175923$10216
assign { } { }
assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:176261.3-176262.53"
- process $proc$libresoc.v:176261$10269
+ attribute \src "libresoc.v:175925.3-175926.53"
+ process $proc$libresoc.v:175925$10217
assign { } { }
assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next
sync posedge \coresync_clk
update \logical_op__rc__rc $0\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:176263.3-176264.53"
- process $proc$libresoc.v:176263$10270
+ attribute \src "libresoc.v:175927.3-175928.53"
+ process $proc$libresoc.v:175927$10218
assign { } { }
assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next
sync posedge \coresync_clk
update \logical_op__rc__ok $0\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:176265.3-176266.53"
- process $proc$libresoc.v:176265$10271
+ attribute \src "libresoc.v:175929.3-175930.53"
+ process $proc$libresoc.v:175929$10219
assign { } { }
assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next
sync posedge \coresync_clk
update \logical_op__oe__oe $0\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:176267.3-176268.53"
- process $proc$libresoc.v:176267$10272
+ attribute \src "libresoc.v:175931.3-175932.53"
+ process $proc$libresoc.v:175931$10220
assign { } { }
assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next
sync posedge \coresync_clk
update \logical_op__oe__ok $0\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:176269.3-176270.59"
- process $proc$libresoc.v:176269$10273
+ attribute \src "libresoc.v:175933.3-175934.59"
+ process $proc$libresoc.v:175933$10221
assign { } { }
assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next
sync posedge \coresync_clk
update \logical_op__invert_in $0\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:176271.3-176272.53"
- process $proc$libresoc.v:176271$10274
+ attribute \src "libresoc.v:175935.3-175936.53"
+ process $proc$libresoc.v:175935$10222
assign { } { }
assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next
sync posedge \coresync_clk
update \logical_op__zero_a $0\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:176273.3-176274.63"
- process $proc$libresoc.v:176273$10275
+ attribute \src "libresoc.v:175937.3-175938.63"
+ process $proc$libresoc.v:175937$10223
assign { } { }
assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next
sync posedge \coresync_clk
update \logical_op__input_carry $0\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:176275.3-176276.61"
- process $proc$libresoc.v:176275$10276
+ attribute \src "libresoc.v:175939.3-175940.61"
+ process $proc$libresoc.v:175939$10224
assign { } { }
assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next
sync posedge \coresync_clk
update \logical_op__invert_out $0\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:176277.3-176278.59"
- process $proc$libresoc.v:176277$10277
+ attribute \src "libresoc.v:175941.3-175942.59"
+ process $proc$libresoc.v:175941$10225
assign { } { }
assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next
sync posedge \coresync_clk
update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:176279.3-176280.65"
- process $proc$libresoc.v:176279$10278
+ attribute \src "libresoc.v:175943.3-175944.65"
+ process $proc$libresoc.v:175943$10226
assign { } { }
assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next
sync posedge \coresync_clk
update \logical_op__output_carry $0\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:176281.3-176282.57"
- process $proc$libresoc.v:176281$10279
+ attribute \src "libresoc.v:175945.3-175946.57"
+ process $proc$libresoc.v:175945$10227
assign { } { }
assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next
sync posedge \coresync_clk
update \logical_op__is_32bit $0\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:176283.3-176284.59"
- process $proc$libresoc.v:176283$10280
+ attribute \src "libresoc.v:175947.3-175948.59"
+ process $proc$libresoc.v:175947$10228
assign { } { }
assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next
sync posedge \coresync_clk
update \logical_op__is_signed $0\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:176285.3-176286.57"
- process $proc$libresoc.v:176285$10281
+ attribute \src "libresoc.v:175949.3-175950.57"
+ process $proc$libresoc.v:175949$10229
assign { } { }
assign $0\logical_op__data_len[3:0] \logical_op__data_len$next
sync posedge \coresync_clk
update \logical_op__data_len $0\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:176287.3-176288.49"
- process $proc$libresoc.v:176287$10282
+ attribute \src "libresoc.v:175951.3-175952.49"
+ process $proc$libresoc.v:175951$10230
assign { } { }
assign $0\logical_op__insn[31:0] \logical_op__insn$next
sync posedge \coresync_clk
update \logical_op__insn $0\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:176289.3-176290.27"
- process $proc$libresoc.v:176289$10283
+ attribute \src "libresoc.v:175953.3-175954.27"
+ process $proc$libresoc.v:175953$10231
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:176291.3-176292.29"
- process $proc$libresoc.v:176291$10284
+ attribute \src "libresoc.v:175955.3-175956.29"
+ process $proc$libresoc.v:175955$10232
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:176399.3-176411.6"
- process $proc$libresoc.v:176399$10285
+ attribute \src "libresoc.v:176063.3-176075.6"
+ process $proc$libresoc.v:176063$10233
assign { } { }
assign { } { }
- assign $0\divisor_neg$next[0:0]$10286 $1\divisor_neg$next[0:0]$10287
- attribute \src "libresoc.v:176400.5-176400.29"
+ assign $0\divisor_neg$next[0:0]$10234 $1\divisor_neg$next[0:0]$10235
+ attribute \src "libresoc.v:176064.5-176064.29"
switch \initial
- attribute \src "libresoc.v:176400.9-176400.17"
+ attribute \src "libresoc.v:176064.9-176064.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\divisor_neg$next[0:0]$10287 \divisor_neg$92
+ assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\divisor_neg$next[0:0]$10287 \divisor_neg$92
+ assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92
case
- assign $1\divisor_neg$next[0:0]$10287 \divisor_neg
+ assign $1\divisor_neg$next[0:0]$10235 \divisor_neg
end
sync always
- update \divisor_neg$next $0\divisor_neg$next[0:0]$10286
+ update \divisor_neg$next $0\divisor_neg$next[0:0]$10234
end
- attribute \src "libresoc.v:176412.3-176424.6"
- process $proc$libresoc.v:176412$10288
+ attribute \src "libresoc.v:176076.3-176088.6"
+ process $proc$libresoc.v:176076$10236
assign { } { }
assign { } { }
- assign $0\dividend_neg$next[0:0]$10289 $1\dividend_neg$next[0:0]$10290
- attribute \src "libresoc.v:176413.5-176413.29"
+ assign $0\dividend_neg$next[0:0]$10237 $1\dividend_neg$next[0:0]$10238
+ attribute \src "libresoc.v:176077.5-176077.29"
switch \initial
- attribute \src "libresoc.v:176413.9-176413.17"
+ attribute \src "libresoc.v:176077.9-176077.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\dividend_neg$next[0:0]$10290 \dividend_neg$93
+ assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\dividend_neg$next[0:0]$10290 \dividend_neg$93
+ assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93
case
- assign $1\dividend_neg$next[0:0]$10290 \dividend_neg
+ assign $1\dividend_neg$next[0:0]$10238 \dividend_neg
end
sync always
- update \dividend_neg$next $0\dividend_neg$next[0:0]$10289
+ update \dividend_neg$next $0\dividend_neg$next[0:0]$10237
end
- attribute \src "libresoc.v:176425.3-176437.6"
- process $proc$libresoc.v:176425$10291
+ attribute \src "libresoc.v:176089.3-176101.6"
+ process $proc$libresoc.v:176089$10239
assign { } { }
assign { } { }
- assign $0\dive_abs_ov32$next[0:0]$10292 $1\dive_abs_ov32$next[0:0]$10293
- attribute \src "libresoc.v:176426.5-176426.29"
+ assign $0\dive_abs_ov32$next[0:0]$10240 $1\dive_abs_ov32$next[0:0]$10241
+ attribute \src "libresoc.v:176090.5-176090.29"
switch \initial
- attribute \src "libresoc.v:176426.9-176426.17"
+ attribute \src "libresoc.v:176090.9-176090.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32$94
+ assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32$94
+ assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94
case
- assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32
+ assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32
end
sync always
- update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10292
+ update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10240
end
- attribute \src "libresoc.v:176438.3-176450.6"
- process $proc$libresoc.v:176438$10294
+ attribute \src "libresoc.v:176102.3-176114.6"
+ process $proc$libresoc.v:176102$10242
assign { } { }
assign { } { }
- assign $0\dive_abs_ov64$next[0:0]$10295 $1\dive_abs_ov64$next[0:0]$10296
- attribute \src "libresoc.v:176439.5-176439.29"
+ assign $0\dive_abs_ov64$next[0:0]$10243 $1\dive_abs_ov64$next[0:0]$10244
+ attribute \src "libresoc.v:176103.5-176103.29"
switch \initial
- attribute \src "libresoc.v:176439.9-176439.17"
+ attribute \src "libresoc.v:176103.9-176103.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64$95
+ assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64$95
+ assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95
case
- assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64
+ assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64
end
sync always
- update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10295
+ update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10243
end
- attribute \src "libresoc.v:176451.3-176463.6"
- process $proc$libresoc.v:176451$10297
+ attribute \src "libresoc.v:176115.3-176127.6"
+ process $proc$libresoc.v:176115$10245
assign { } { }
assign { } { }
- assign $0\div_by_zero$next[0:0]$10298 $1\div_by_zero$next[0:0]$10299
- attribute \src "libresoc.v:176452.5-176452.29"
+ assign $0\div_by_zero$next[0:0]$10246 $1\div_by_zero$next[0:0]$10247
+ attribute \src "libresoc.v:176116.5-176116.29"
switch \initial
- attribute \src "libresoc.v:176452.9-176452.17"
+ attribute \src "libresoc.v:176116.9-176116.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\div_by_zero$next[0:0]$10299 \div_by_zero$96
+ assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\div_by_zero$next[0:0]$10299 \div_by_zero$96
+ assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96
case
- assign $1\div_by_zero$next[0:0]$10299 \div_by_zero
+ assign $1\div_by_zero$next[0:0]$10247 \div_by_zero
end
sync always
- update \div_by_zero$next $0\div_by_zero$next[0:0]$10298
+ update \div_by_zero$next $0\div_by_zero$next[0:0]$10246
end
- attribute \src "libresoc.v:176464.3-176476.6"
- process $proc$libresoc.v:176464$10300
+ attribute \src "libresoc.v:176128.3-176140.6"
+ process $proc$libresoc.v:176128$10248
assign { } { }
assign { } { }
- assign $0\dividend$next[127:0]$10301 $1\dividend$next[127:0]$10302
- attribute \src "libresoc.v:176465.5-176465.29"
+ assign $0\dividend$next[127:0]$10249 $1\dividend$next[127:0]$10250
+ attribute \src "libresoc.v:176129.5-176129.29"
switch \initial
- attribute \src "libresoc.v:176465.9-176465.17"
+ attribute \src "libresoc.v:176129.9-176129.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\dividend$next[127:0]$10302 \dividend$97
+ assign $1\dividend$next[127:0]$10250 \dividend$97
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\dividend$next[127:0]$10302 \dividend$97
+ assign $1\dividend$next[127:0]$10250 \dividend$97
case
- assign $1\dividend$next[127:0]$10302 \dividend
+ assign $1\dividend$next[127:0]$10250 \dividend
end
sync always
- update \dividend$next $0\dividend$next[127:0]$10301
+ update \dividend$next $0\dividend$next[127:0]$10249
end
- attribute \src "libresoc.v:176477.3-176489.6"
- process $proc$libresoc.v:176477$10303
+ attribute \src "libresoc.v:176141.3-176153.6"
+ process $proc$libresoc.v:176141$10251
assign { } { }
assign { } { }
- assign $0\divisor_radicand$next[63:0]$10304 $1\divisor_radicand$next[63:0]$10305
- attribute \src "libresoc.v:176478.5-176478.29"
+ assign $0\divisor_radicand$next[63:0]$10252 $1\divisor_radicand$next[63:0]$10253
+ attribute \src "libresoc.v:176142.5-176142.29"
switch \initial
- attribute \src "libresoc.v:176478.9-176478.17"
+ attribute \src "libresoc.v:176142.9-176142.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand$98
+ assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand$98
+ assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98
case
- assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand
+ assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand
end
sync always
- update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10304
+ update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10252
end
- attribute \src "libresoc.v:176490.3-176502.6"
- process $proc$libresoc.v:176490$10306
+ attribute \src "libresoc.v:176154.3-176166.6"
+ process $proc$libresoc.v:176154$10254
assign { } { }
assign { } { }
- assign $0\operation$next[1:0]$10307 $1\operation$next[1:0]$10308
- attribute \src "libresoc.v:176491.5-176491.29"
+ assign $0\operation$next[1:0]$10255 $1\operation$next[1:0]$10256
+ attribute \src "libresoc.v:176155.5-176155.29"
switch \initial
- attribute \src "libresoc.v:176491.9-176491.17"
+ attribute \src "libresoc.v:176155.9-176155.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\operation$next[1:0]$10308 \operation$99
+ assign $1\operation$next[1:0]$10256 \operation$99
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\operation$next[1:0]$10308 \operation$99
+ assign $1\operation$next[1:0]$10256 \operation$99
case
- assign $1\operation$next[1:0]$10308 \operation
+ assign $1\operation$next[1:0]$10256 \operation
end
sync always
- update \operation$next $0\operation$next[1:0]$10307
+ update \operation$next $0\operation$next[1:0]$10255
end
- attribute \src "libresoc.v:176503.3-176520.6"
- process $proc$libresoc.v:176503$10309
+ attribute \src "libresoc.v:176167.3-176184.6"
+ process $proc$libresoc.v:176167$10257
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$10310 $2\r_busy$next[0:0]$10312
- attribute \src "libresoc.v:176504.5-176504.29"
+ assign $0\r_busy$next[0:0]$10258 $2\r_busy$next[0:0]$10260
+ attribute \src "libresoc.v:176168.5-176168.29"
switch \initial
- attribute \src "libresoc.v:176504.9-176504.17"
+ attribute \src "libresoc.v:176168.9-176168.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$10311 1'1
+ assign $1\r_busy$next[0:0]$10259 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$10311 1'0
+ assign $1\r_busy$next[0:0]$10259 1'0
case
- assign $1\r_busy$next[0:0]$10311 \r_busy
+ assign $1\r_busy$next[0:0]$10259 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$10312 1'0
+ assign $2\r_busy$next[0:0]$10260 1'0
case
- assign $2\r_busy$next[0:0]$10312 $1\r_busy$next[0:0]$10311
+ assign $2\r_busy$next[0:0]$10260 $1\r_busy$next[0:0]$10259
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$10310
+ update \r_busy$next $0\r_busy$next[0:0]$10258
end
- attribute \src "libresoc.v:176521.3-176533.6"
- process $proc$libresoc.v:176521$10313
+ attribute \src "libresoc.v:176185.3-176197.6"
+ process $proc$libresoc.v:176185$10261
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$10314 $1\muxid$next[1:0]$10315
- attribute \src "libresoc.v:176522.5-176522.29"
+ assign $0\muxid$next[1:0]$10262 $1\muxid$next[1:0]$10263
+ attribute \src "libresoc.v:176186.5-176186.29"
switch \initial
- attribute \src "libresoc.v:176522.9-176522.17"
+ attribute \src "libresoc.v:176186.9-176186.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$10315 \muxid$68
+ assign $1\muxid$next[1:0]$10263 \muxid$68
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$10315 \muxid$68
+ assign $1\muxid$next[1:0]$10263 \muxid$68
case
- assign $1\muxid$next[1:0]$10315 \muxid
+ assign $1\muxid$next[1:0]$10263 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$10314
+ update \muxid$next $0\muxid$next[1:0]$10262
end
- attribute \src "libresoc.v:176534.3-176575.6"
- process $proc$libresoc.v:176534$10316
+ attribute \src "libresoc.v:176198.3-176239.6"
+ process $proc$libresoc.v:176198$10264
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$next[3:0]$10317 $1\logical_op__data_len$next[3:0]$10335
- assign $0\logical_op__fn_unit$next[13:0]$10318 $1\logical_op__fn_unit$next[13:0]$10336
+ assign $0\logical_op__data_len$next[3:0]$10265 $1\logical_op__data_len$next[3:0]$10283
+ assign $0\logical_op__fn_unit$next[13:0]$10266 $1\logical_op__fn_unit$next[13:0]$10284
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$next[1:0]$10321 $1\logical_op__input_carry$next[1:0]$10339
- assign $0\logical_op__insn$next[31:0]$10322 $1\logical_op__insn$next[31:0]$10340
- assign $0\logical_op__insn_type$next[6:0]$10323 $1\logical_op__insn_type$next[6:0]$10341
- assign $0\logical_op__invert_in$next[0:0]$10324 $1\logical_op__invert_in$next[0:0]$10342
- assign $0\logical_op__invert_out$next[0:0]$10325 $1\logical_op__invert_out$next[0:0]$10343
- assign $0\logical_op__is_32bit$next[0:0]$10326 $1\logical_op__is_32bit$next[0:0]$10344
- assign $0\logical_op__is_signed$next[0:0]$10327 $1\logical_op__is_signed$next[0:0]$10345
+ assign $0\logical_op__input_carry$next[1:0]$10269 $1\logical_op__input_carry$next[1:0]$10287
+ assign $0\logical_op__insn$next[31:0]$10270 $1\logical_op__insn$next[31:0]$10288
+ assign $0\logical_op__insn_type$next[6:0]$10271 $1\logical_op__insn_type$next[6:0]$10289
+ assign $0\logical_op__invert_in$next[0:0]$10272 $1\logical_op__invert_in$next[0:0]$10290
+ assign $0\logical_op__invert_out$next[0:0]$10273 $1\logical_op__invert_out$next[0:0]$10291
+ assign $0\logical_op__is_32bit$next[0:0]$10274 $1\logical_op__is_32bit$next[0:0]$10292
+ assign $0\logical_op__is_signed$next[0:0]$10275 $1\logical_op__is_signed$next[0:0]$10293
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$next[0:0]$10330 $1\logical_op__output_carry$next[0:0]$10348
+ assign $0\logical_op__output_carry$next[0:0]$10278 $1\logical_op__output_carry$next[0:0]$10296
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$next[0:0]$10333 $1\logical_op__write_cr0$next[0:0]$10351
- assign $0\logical_op__zero_a$next[0:0]$10334 $1\logical_op__zero_a$next[0:0]$10352
- assign $0\logical_op__imm_data__data$next[63:0]$10319 $2\logical_op__imm_data__data$next[63:0]$10353
- assign $0\logical_op__imm_data__ok$next[0:0]$10320 $2\logical_op__imm_data__ok$next[0:0]$10354
- assign $0\logical_op__oe__oe$next[0:0]$10328 $2\logical_op__oe__oe$next[0:0]$10355
- assign $0\logical_op__oe__ok$next[0:0]$10329 $2\logical_op__oe__ok$next[0:0]$10356
- assign $0\logical_op__rc__ok$next[0:0]$10331 $2\logical_op__rc__ok$next[0:0]$10357
- assign $0\logical_op__rc__rc$next[0:0]$10332 $2\logical_op__rc__rc$next[0:0]$10358
- attribute \src "libresoc.v:176535.5-176535.29"
+ assign $0\logical_op__write_cr0$next[0:0]$10281 $1\logical_op__write_cr0$next[0:0]$10299
+ assign $0\logical_op__zero_a$next[0:0]$10282 $1\logical_op__zero_a$next[0:0]$10300
+ assign $0\logical_op__imm_data__data$next[63:0]$10267 $2\logical_op__imm_data__data$next[63:0]$10301
+ assign $0\logical_op__imm_data__ok$next[0:0]$10268 $2\logical_op__imm_data__ok$next[0:0]$10302
+ assign $0\logical_op__oe__oe$next[0:0]$10276 $2\logical_op__oe__oe$next[0:0]$10303
+ assign $0\logical_op__oe__ok$next[0:0]$10277 $2\logical_op__oe__ok$next[0:0]$10304
+ assign $0\logical_op__rc__ok$next[0:0]$10279 $2\logical_op__rc__ok$next[0:0]$10305
+ assign $0\logical_op__rc__rc$next[0:0]$10280 $2\logical_op__rc__rc$next[0:0]$10306
+ attribute \src "libresoc.v:176199.5-176199.29"
switch \initial
- attribute \src "libresoc.v:176535.9-176535.17"
+ attribute \src "libresoc.v:176199.9-176199.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$10340 $1\logical_op__data_len$next[3:0]$10335 $1\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__output_carry$next[0:0]$10348 $1\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__invert_out$next[0:0]$10343 $1\logical_op__input_carry$next[1:0]$10339 $1\logical_op__zero_a$next[0:0]$10352 $1\logical_op__invert_in$next[0:0]$10342 $1\logical_op__oe__ok$next[0:0]$10347 $1\logical_op__oe__oe$next[0:0]$10346 $1\logical_op__rc__ok$next[0:0]$10349 $1\logical_op__rc__rc$next[0:0]$10350 $1\logical_op__imm_data__ok$next[0:0]$10338 $1\logical_op__imm_data__data$next[63:0]$10337 $1\logical_op__fn_unit$next[13:0]$10336 $1\logical_op__insn_type$next[6:0]$10341 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
+ assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$10340 $1\logical_op__data_len$next[3:0]$10335 $1\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__output_carry$next[0:0]$10348 $1\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__invert_out$next[0:0]$10343 $1\logical_op__input_carry$next[1:0]$10339 $1\logical_op__zero_a$next[0:0]$10352 $1\logical_op__invert_in$next[0:0]$10342 $1\logical_op__oe__ok$next[0:0]$10347 $1\logical_op__oe__oe$next[0:0]$10346 $1\logical_op__rc__ok$next[0:0]$10349 $1\logical_op__rc__rc$next[0:0]$10350 $1\logical_op__imm_data__ok$next[0:0]$10338 $1\logical_op__imm_data__data$next[63:0]$10337 $1\logical_op__fn_unit$next[13:0]$10336 $1\logical_op__insn_type$next[6:0]$10341 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
+ assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
case
- assign $1\logical_op__data_len$next[3:0]$10335 \logical_op__data_len
- assign $1\logical_op__fn_unit$next[13:0]$10336 \logical_op__fn_unit
- assign $1\logical_op__imm_data__data$next[63:0]$10337 \logical_op__imm_data__data
- assign $1\logical_op__imm_data__ok$next[0:0]$10338 \logical_op__imm_data__ok
- assign $1\logical_op__input_carry$next[1:0]$10339 \logical_op__input_carry
- assign $1\logical_op__insn$next[31:0]$10340 \logical_op__insn
- assign $1\logical_op__insn_type$next[6:0]$10341 \logical_op__insn_type
- assign $1\logical_op__invert_in$next[0:0]$10342 \logical_op__invert_in
- assign $1\logical_op__invert_out$next[0:0]$10343 \logical_op__invert_out
- assign $1\logical_op__is_32bit$next[0:0]$10344 \logical_op__is_32bit
- assign $1\logical_op__is_signed$next[0:0]$10345 \logical_op__is_signed
- assign $1\logical_op__oe__oe$next[0:0]$10346 \logical_op__oe__oe
- assign $1\logical_op__oe__ok$next[0:0]$10347 \logical_op__oe__ok
- assign $1\logical_op__output_carry$next[0:0]$10348 \logical_op__output_carry
- assign $1\logical_op__rc__ok$next[0:0]$10349 \logical_op__rc__ok
- assign $1\logical_op__rc__rc$next[0:0]$10350 \logical_op__rc__rc
- assign $1\logical_op__write_cr0$next[0:0]$10351 \logical_op__write_cr0
- assign $1\logical_op__zero_a$next[0:0]$10352 \logical_op__zero_a
+ assign $1\logical_op__data_len$next[3:0]$10283 \logical_op__data_len
+ assign $1\logical_op__fn_unit$next[13:0]$10284 \logical_op__fn_unit
+ assign $1\logical_op__imm_data__data$next[63:0]$10285 \logical_op__imm_data__data
+ assign $1\logical_op__imm_data__ok$next[0:0]$10286 \logical_op__imm_data__ok
+ assign $1\logical_op__input_carry$next[1:0]$10287 \logical_op__input_carry
+ assign $1\logical_op__insn$next[31:0]$10288 \logical_op__insn
+ assign $1\logical_op__insn_type$next[6:0]$10289 \logical_op__insn_type
+ assign $1\logical_op__invert_in$next[0:0]$10290 \logical_op__invert_in
+ assign $1\logical_op__invert_out$next[0:0]$10291 \logical_op__invert_out
+ assign $1\logical_op__is_32bit$next[0:0]$10292 \logical_op__is_32bit
+ assign $1\logical_op__is_signed$next[0:0]$10293 \logical_op__is_signed
+ assign $1\logical_op__oe__oe$next[0:0]$10294 \logical_op__oe__oe
+ assign $1\logical_op__oe__ok$next[0:0]$10295 \logical_op__oe__ok
+ assign $1\logical_op__output_carry$next[0:0]$10296 \logical_op__output_carry
+ assign $1\logical_op__rc__ok$next[0:0]$10297 \logical_op__rc__ok
+ assign $1\logical_op__rc__rc$next[0:0]$10298 \logical_op__rc__rc
+ assign $1\logical_op__write_cr0$next[0:0]$10299 \logical_op__write_cr0
+ assign $1\logical_op__zero_a$next[0:0]$10300 \logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$next[63:0]$10353 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$next[0:0]$10354 1'0
- assign $2\logical_op__rc__rc$next[0:0]$10358 1'0
- assign $2\logical_op__rc__ok$next[0:0]$10357 1'0
- assign $2\logical_op__oe__oe$next[0:0]$10355 1'0
- assign $2\logical_op__oe__ok$next[0:0]$10356 1'0
+ assign $2\logical_op__imm_data__data$next[63:0]$10301 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$next[0:0]$10302 1'0
+ assign $2\logical_op__rc__rc$next[0:0]$10306 1'0
+ assign $2\logical_op__rc__ok$next[0:0]$10305 1'0
+ assign $2\logical_op__oe__oe$next[0:0]$10303 1'0
+ assign $2\logical_op__oe__ok$next[0:0]$10304 1'0
case
- assign $2\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__imm_data__data$next[63:0]$10337
- assign $2\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__ok$next[0:0]$10338
- assign $2\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__oe__oe$next[0:0]$10346
- assign $2\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__ok$next[0:0]$10347
- assign $2\logical_op__rc__ok$next[0:0]$10357 $1\logical_op__rc__ok$next[0:0]$10349
- assign $2\logical_op__rc__rc$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10350
+ assign $2\logical_op__imm_data__data$next[63:0]$10301 $1\logical_op__imm_data__data$next[63:0]$10285
+ assign $2\logical_op__imm_data__ok$next[0:0]$10302 $1\logical_op__imm_data__ok$next[0:0]$10286
+ assign $2\logical_op__oe__oe$next[0:0]$10303 $1\logical_op__oe__oe$next[0:0]$10294
+ assign $2\logical_op__oe__ok$next[0:0]$10304 $1\logical_op__oe__ok$next[0:0]$10295
+ assign $2\logical_op__rc__ok$next[0:0]$10305 $1\logical_op__rc__ok$next[0:0]$10297
+ assign $2\logical_op__rc__rc$next[0:0]$10306 $1\logical_op__rc__rc$next[0:0]$10298
end
sync always
- update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10317
- update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10318
- update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10319
- update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10320
- update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10321
- update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10322
- update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10323
- update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10324
- update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10325
- update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10326
- update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10327
- update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10328
- update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10329
- update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10330
- update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10331
- update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10332
- update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10333
- update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10334
+ update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10265
+ update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10266
+ update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10267
+ update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10268
+ update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10269
+ update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10270
+ update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10271
+ update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10272
+ update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10273
+ update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10274
+ update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10275
+ update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10276
+ update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10277
+ update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10278
+ update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10279
+ update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10280
+ update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10281
+ update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10282
end
- attribute \src "libresoc.v:176576.3-176588.6"
- process $proc$libresoc.v:176576$10359
+ attribute \src "libresoc.v:176240.3-176252.6"
+ process $proc$libresoc.v:176240$10307
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$10360 $1\ra$next[63:0]$10361
- attribute \src "libresoc.v:176577.5-176577.29"
+ assign $0\ra$next[63:0]$10308 $1\ra$next[63:0]$10309
+ attribute \src "libresoc.v:176241.5-176241.29"
switch \initial
- attribute \src "libresoc.v:176577.9-176577.17"
+ attribute \src "libresoc.v:176241.9-176241.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$10361 \ra$87
+ assign $1\ra$next[63:0]$10309 \ra$87
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$10361 \ra$87
+ assign $1\ra$next[63:0]$10309 \ra$87
case
- assign $1\ra$next[63:0]$10361 \ra
+ assign $1\ra$next[63:0]$10309 \ra
end
sync always
- update \ra$next $0\ra$next[63:0]$10360
+ update \ra$next $0\ra$next[63:0]$10308
end
- attribute \src "libresoc.v:176589.3-176601.6"
- process $proc$libresoc.v:176589$10362
+ attribute \src "libresoc.v:176253.3-176265.6"
+ process $proc$libresoc.v:176253$10310
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$10363 $1\rb$next[63:0]$10364
- attribute \src "libresoc.v:176590.5-176590.29"
+ assign $0\rb$next[63:0]$10311 $1\rb$next[63:0]$10312
+ attribute \src "libresoc.v:176254.5-176254.29"
switch \initial
- attribute \src "libresoc.v:176590.9-176590.17"
+ attribute \src "libresoc.v:176254.9-176254.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$10364 \rb$89
+ assign $1\rb$next[63:0]$10312 \rb$89
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$10364 \rb$89
+ assign $1\rb$next[63:0]$10312 \rb$89
case
- assign $1\rb$next[63:0]$10364 \rb
+ assign $1\rb$next[63:0]$10312 \rb
end
sync always
- update \rb$next $0\rb$next[63:0]$10363
+ update \rb$next $0\rb$next[63:0]$10311
end
- attribute \src "libresoc.v:176602.3-176614.6"
- process $proc$libresoc.v:176602$10365
+ attribute \src "libresoc.v:176266.3-176278.6"
+ process $proc$libresoc.v:176266$10313
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$10366 $1\xer_so$next[0:0]$10367
- attribute \src "libresoc.v:176603.5-176603.29"
+ assign $0\xer_so$next[0:0]$10314 $1\xer_so$next[0:0]$10315
+ attribute \src "libresoc.v:176267.5-176267.29"
switch \initial
- attribute \src "libresoc.v:176603.9-176603.17"
+ attribute \src "libresoc.v:176267.9-176267.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$next[0:0]$10367 \xer_so$91
+ assign $1\xer_so$next[0:0]$10315 \xer_so$91
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$next[0:0]$10367 \xer_so$91
+ assign $1\xer_so$next[0:0]$10315 \xer_so$91
case
- assign $1\xer_so$next[0:0]$10367 \xer_so
+ assign $1\xer_so$next[0:0]$10315 \xer_so
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$10366
+ update \xer_so$next $0\xer_so$next[0:0]$10314
end
- connect \$66 $and$libresoc.v:176230$10253_Y
+ connect \$66 $and$libresoc.v:175894$10201_Y
connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000
connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000
connect \p_ready_o \n_i_rdy_data
connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:176649.1-176693.10"
+attribute \src "libresoc.v:176313.1-176357.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.pll"
attribute \generator "nMigen"
module \pll
- attribute \src "libresoc.v:176650.7-176650.20"
+ attribute \src "libresoc.v:176314.7-176314.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:176682.3-176691.6"
+ attribute \src "libresoc.v:176346.3-176355.6"
wire $0\pll_18_o[0:0]
- attribute \src "libresoc.v:176672.3-176681.6"
+ attribute \src "libresoc.v:176336.3-176345.6"
wire $0\pll_lck_o[0:0]
- attribute \src "libresoc.v:176682.3-176691.6"
+ attribute \src "libresoc.v:176346.3-176355.6"
wire $1\pll_18_o[0:0]
- attribute \src "libresoc.v:176672.3-176681.6"
+ attribute \src "libresoc.v:176336.3-176345.6"
wire $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:176669.17-176669.105"
- wire $eq$libresoc.v:176669$10400_Y
- attribute \src "libresoc.v:176670.17-176670.105"
- wire $eq$libresoc.v:176670$10401_Y
- attribute \src "libresoc.v:176671.17-176671.98"
- wire $not$libresoc.v:176671$10402_Y
+ attribute \src "libresoc.v:176333.17-176333.105"
+ wire $eq$libresoc.v:176333$10348_Y
+ attribute \src "libresoc.v:176334.17-176334.105"
+ wire $eq$libresoc.v:176334$10349_Y
+ attribute \src "libresoc.v:176335.17-176335.98"
+ wire $not$libresoc.v:176335$10350_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
wire output 5 \clk_pll_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
wire width 2 input 3 \clk_sel_i
- attribute \src "libresoc.v:176650.7-176650.15"
+ attribute \src "libresoc.v:176314.7-176314.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
wire output 2 \pll_18_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
wire output 4 \pll_lck_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:176669$10400
+ cell $eq $eq$libresoc.v:176333$10348
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clk_sel_i
connect \B 2'00
- connect \Y $eq$libresoc.v:176669$10400_Y
+ connect \Y $eq$libresoc.v:176333$10348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:176670$10401
+ cell $eq $eq$libresoc.v:176334$10349
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clk_sel_i
connect \B 2'00
- connect \Y $eq$libresoc.v:176670$10401_Y
+ connect \Y $eq$libresoc.v:176334$10349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21"
- cell $not $not$libresoc.v:176671$10402
+ cell $not $not$libresoc.v:176335$10350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \clk_24_i
- connect \Y $not$libresoc.v:176671$10402_Y
+ connect \Y $not$libresoc.v:176335$10350_Y
end
- attribute \src "libresoc.v:176650.7-176650.20"
- process $proc$libresoc.v:176650$10405
+ attribute \src "libresoc.v:176314.7-176314.20"
+ process $proc$libresoc.v:176314$10353
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:176672.3-176681.6"
- process $proc$libresoc.v:176672$10403
+ attribute \src "libresoc.v:176336.3-176345.6"
+ process $proc$libresoc.v:176336$10351
assign { } { }
assign { } { }
assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:176673.5-176673.29"
+ attribute \src "libresoc.v:176337.5-176337.29"
switch \initial
- attribute \src "libresoc.v:176673.9-176673.17"
+ attribute \src "libresoc.v:176337.9-176337.17"
case 1'1
case
end
sync always
update \pll_lck_o $0\pll_lck_o[0:0]
end
- attribute \src "libresoc.v:176682.3-176691.6"
- process $proc$libresoc.v:176682$10404
+ attribute \src "libresoc.v:176346.3-176355.6"
+ process $proc$libresoc.v:176346$10352
assign { } { }
assign { } { }
assign $0\pll_18_o[0:0] $1\pll_18_o[0:0]
- attribute \src "libresoc.v:176683.5-176683.29"
+ attribute \src "libresoc.v:176347.5-176347.29"
switch \initial
- attribute \src "libresoc.v:176683.9-176683.17"
+ attribute \src "libresoc.v:176347.9-176347.17"
case 1'1
case
end
sync always
update \pll_18_o $0\pll_18_o[0:0]
end
- connect \$1 $eq$libresoc.v:176669$10400_Y
- connect \$3 $eq$libresoc.v:176670$10401_Y
- connect \$5 $not$libresoc.v:176671$10402_Y
+ connect \$1 $eq$libresoc.v:176333$10348_Y
+ connect \$3 $eq$libresoc.v:176334$10349_Y
+ connect \$5 $not$libresoc.v:176335$10350_Y
connect \clk_pll_o \clk_24_i
end
-attribute \src "libresoc.v:176697.1-177339.10"
+attribute \src "libresoc.v:176361.1-177003.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount"
attribute \generator "nMigen"
module \popcount
- attribute \src "libresoc.v:176698.7-176698.20"
+ attribute \src "libresoc.v:176362.7-176362.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:177186.3-177212.6"
+ attribute \src "libresoc.v:176850.3-176876.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:177186.3-177212.6"
+ attribute \src "libresoc.v:176850.3-176876.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:177110.19-177110.132"
- wire width 4 $add$libresoc.v:177110$10406_Y
- attribute \src "libresoc.v:177111.19-177111.132"
- wire width 4 $add$libresoc.v:177111$10407_Y
- attribute \src "libresoc.v:177112.19-177112.132"
- wire width 4 $add$libresoc.v:177112$10408_Y
- attribute \src "libresoc.v:177113.19-177113.132"
- wire width 4 $add$libresoc.v:177113$10409_Y
- attribute \src "libresoc.v:177114.19-177114.134"
- wire width 4 $add$libresoc.v:177114$10410_Y
- attribute \src "libresoc.v:177115.19-177115.134"
- wire width 4 $add$libresoc.v:177115$10411_Y
- attribute \src "libresoc.v:177116.18-177116.125"
- wire width 3 $add$libresoc.v:177116$10412_Y
- attribute \src "libresoc.v:177117.19-177117.134"
- wire width 4 $add$libresoc.v:177117$10413_Y
- attribute \src "libresoc.v:177118.19-177118.134"
- wire width 4 $add$libresoc.v:177118$10414_Y
- attribute \src "libresoc.v:177119.19-177119.134"
- wire width 4 $add$libresoc.v:177119$10415_Y
- attribute \src "libresoc.v:177120.19-177120.134"
- wire width 4 $add$libresoc.v:177120$10416_Y
- attribute \src "libresoc.v:177121.19-177121.134"
- wire width 4 $add$libresoc.v:177121$10417_Y
- attribute \src "libresoc.v:177122.19-177122.134"
- wire width 4 $add$libresoc.v:177122$10418_Y
- attribute \src "libresoc.v:177123.19-177123.134"
- wire width 4 $add$libresoc.v:177123$10419_Y
- attribute \src "libresoc.v:177124.19-177124.134"
- wire width 4 $add$libresoc.v:177124$10420_Y
- attribute \src "libresoc.v:177125.19-177125.134"
- wire width 4 $add$libresoc.v:177125$10421_Y
- attribute \src "libresoc.v:177126.19-177126.132"
- wire width 5 $add$libresoc.v:177126$10422_Y
- attribute \src "libresoc.v:177127.18-177127.125"
- wire width 3 $add$libresoc.v:177127$10423_Y
- attribute \src "libresoc.v:177128.19-177128.132"
- wire width 5 $add$libresoc.v:177128$10424_Y
- attribute \src "libresoc.v:177129.19-177129.132"
- wire width 5 $add$libresoc.v:177129$10425_Y
- attribute \src "libresoc.v:177130.19-177130.132"
- wire width 5 $add$libresoc.v:177130$10426_Y
- attribute \src "libresoc.v:177131.19-177131.132"
- wire width 5 $add$libresoc.v:177131$10427_Y
- attribute \src "libresoc.v:177132.19-177132.134"
- wire width 5 $add$libresoc.v:177132$10428_Y
- attribute \src "libresoc.v:177133.19-177133.134"
- wire width 5 $add$libresoc.v:177133$10429_Y
- attribute \src "libresoc.v:177134.19-177134.134"
- wire width 5 $add$libresoc.v:177134$10430_Y
- attribute \src "libresoc.v:177135.19-177135.132"
- wire width 6 $add$libresoc.v:177135$10431_Y
- attribute \src "libresoc.v:177136.19-177136.132"
- wire width 6 $add$libresoc.v:177136$10432_Y
- attribute \src "libresoc.v:177137.19-177137.132"
- wire width 6 $add$libresoc.v:177137$10433_Y
- attribute \src "libresoc.v:177138.18-177138.127"
- wire width 3 $add$libresoc.v:177138$10434_Y
- attribute \src "libresoc.v:177139.19-177139.132"
- wire width 6 $add$libresoc.v:177139$10435_Y
- attribute \src "libresoc.v:177140.19-177140.132"
- wire width 7 $add$libresoc.v:177140$10436_Y
- attribute \src "libresoc.v:177141.19-177141.132"
- wire width 7 $add$libresoc.v:177141$10437_Y
- attribute \src "libresoc.v:177142.19-177142.132"
- wire width 8 $add$libresoc.v:177142$10438_Y
- attribute \src "libresoc.v:177153.18-177153.127"
- wire width 3 $add$libresoc.v:177153$10457_Y
- attribute \src "libresoc.v:177157.18-177157.127"
- wire width 3 $add$libresoc.v:177157$10464_Y
- attribute \src "libresoc.v:177158.18-177158.127"
- wire width 3 $add$libresoc.v:177158$10465_Y
- attribute \src "libresoc.v:177159.17-177159.124"
- wire width 3 $add$libresoc.v:177159$10466_Y
- attribute \src "libresoc.v:177160.18-177160.127"
- wire width 3 $add$libresoc.v:177160$10467_Y
- attribute \src "libresoc.v:177161.18-177161.127"
- wire width 3 $add$libresoc.v:177161$10468_Y
- attribute \src "libresoc.v:177162.18-177162.127"
- wire width 3 $add$libresoc.v:177162$10469_Y
- attribute \src "libresoc.v:177163.18-177163.127"
- wire width 3 $add$libresoc.v:177163$10470_Y
- attribute \src "libresoc.v:177164.18-177164.127"
- wire width 3 $add$libresoc.v:177164$10471_Y
- attribute \src "libresoc.v:177165.18-177165.127"
- wire width 3 $add$libresoc.v:177165$10472_Y
- attribute \src "libresoc.v:177166.18-177166.127"
- wire width 3 $add$libresoc.v:177166$10473_Y
- attribute \src "libresoc.v:177167.18-177167.127"
- wire width 3 $add$libresoc.v:177167$10474_Y
- attribute \src "libresoc.v:177168.18-177168.127"
- wire width 3 $add$libresoc.v:177168$10475_Y
- attribute \src "libresoc.v:177169.18-177169.127"
- wire width 3 $add$libresoc.v:177169$10476_Y
- attribute \src "libresoc.v:177170.17-177170.124"
- wire width 3 $add$libresoc.v:177170$10477_Y
- attribute \src "libresoc.v:177171.18-177171.127"
- wire width 3 $add$libresoc.v:177171$10478_Y
- attribute \src "libresoc.v:177172.18-177172.127"
- wire width 3 $add$libresoc.v:177172$10479_Y
- attribute \src "libresoc.v:177173.18-177173.127"
- wire width 3 $add$libresoc.v:177173$10480_Y
- attribute \src "libresoc.v:177174.18-177174.127"
- wire width 3 $add$libresoc.v:177174$10481_Y
- attribute \src "libresoc.v:177175.18-177175.127"
- wire width 3 $add$libresoc.v:177175$10482_Y
- attribute \src "libresoc.v:177176.18-177176.127"
- wire width 3 $add$libresoc.v:177176$10483_Y
- attribute \src "libresoc.v:177177.18-177177.127"
- wire width 3 $add$libresoc.v:177177$10484_Y
- attribute \src "libresoc.v:177178.18-177178.127"
- wire width 3 $add$libresoc.v:177178$10485_Y
- attribute \src "libresoc.v:177179.18-177179.127"
- wire width 3 $add$libresoc.v:177179$10486_Y
- attribute \src "libresoc.v:177180.18-177180.127"
- wire width 3 $add$libresoc.v:177180$10487_Y
- attribute \src "libresoc.v:177181.17-177181.124"
- wire width 3 $add$libresoc.v:177181$10488_Y
- attribute \src "libresoc.v:177182.18-177182.127"
- wire width 3 $add$libresoc.v:177182$10489_Y
- attribute \src "libresoc.v:177183.18-177183.127"
- wire width 3 $add$libresoc.v:177183$10490_Y
- attribute \src "libresoc.v:177184.18-177184.127"
- wire width 3 $add$libresoc.v:177184$10491_Y
- attribute \src "libresoc.v:177185.18-177185.131"
- wire width 4 $add$libresoc.v:177185$10492_Y
- attribute \src "libresoc.v:177143.19-177143.111"
- wire $eq$libresoc.v:177143$10439_Y
- attribute \src "libresoc.v:177144.19-177144.111"
- wire $eq$libresoc.v:177144$10440_Y
- attribute \src "libresoc.v:177145.19-177145.104"
- wire width 8 $extend$libresoc.v:177145$10441_Y
- attribute \src "libresoc.v:177146.19-177146.104"
- wire width 8 $extend$libresoc.v:177146$10443_Y
- attribute \src "libresoc.v:177147.19-177147.104"
- wire width 8 $extend$libresoc.v:177147$10445_Y
- attribute \src "libresoc.v:177148.19-177148.104"
- wire width 8 $extend$libresoc.v:177148$10447_Y
- attribute \src "libresoc.v:177149.19-177149.104"
- wire width 8 $extend$libresoc.v:177149$10449_Y
- attribute \src "libresoc.v:177150.19-177150.104"
- wire width 8 $extend$libresoc.v:177150$10451_Y
- attribute \src "libresoc.v:177151.19-177151.104"
- wire width 8 $extend$libresoc.v:177151$10453_Y
- attribute \src "libresoc.v:177152.19-177152.104"
- wire width 8 $extend$libresoc.v:177152$10455_Y
- attribute \src "libresoc.v:177154.19-177154.104"
- wire width 32 $extend$libresoc.v:177154$10458_Y
- attribute \src "libresoc.v:177155.19-177155.104"
- wire width 32 $extend$libresoc.v:177155$10460_Y
- attribute \src "libresoc.v:177156.19-177156.104"
- wire width 64 $extend$libresoc.v:177156$10462_Y
- attribute \src "libresoc.v:177145.19-177145.104"
- wire width 8 $pos$libresoc.v:177145$10442_Y
- attribute \src "libresoc.v:177146.19-177146.104"
- wire width 8 $pos$libresoc.v:177146$10444_Y
- attribute \src "libresoc.v:177147.19-177147.104"
- wire width 8 $pos$libresoc.v:177147$10446_Y
- attribute \src "libresoc.v:177148.19-177148.104"
- wire width 8 $pos$libresoc.v:177148$10448_Y
- attribute \src "libresoc.v:177149.19-177149.104"
- wire width 8 $pos$libresoc.v:177149$10450_Y
- attribute \src "libresoc.v:177150.19-177150.104"
- wire width 8 $pos$libresoc.v:177150$10452_Y
- attribute \src "libresoc.v:177151.19-177151.104"
- wire width 8 $pos$libresoc.v:177151$10454_Y
- attribute \src "libresoc.v:177152.19-177152.104"
- wire width 8 $pos$libresoc.v:177152$10456_Y
- attribute \src "libresoc.v:177154.19-177154.104"
- wire width 32 $pos$libresoc.v:177154$10459_Y
- attribute \src "libresoc.v:177155.19-177155.104"
- wire width 32 $pos$libresoc.v:177155$10461_Y
- attribute \src "libresoc.v:177156.19-177156.104"
- wire width 64 $pos$libresoc.v:177156$10463_Y
+ attribute \src "libresoc.v:176774.19-176774.132"
+ wire width 4 $add$libresoc.v:176774$10354_Y
+ attribute \src "libresoc.v:176775.19-176775.132"
+ wire width 4 $add$libresoc.v:176775$10355_Y
+ attribute \src "libresoc.v:176776.19-176776.132"
+ wire width 4 $add$libresoc.v:176776$10356_Y
+ attribute \src "libresoc.v:176777.19-176777.132"
+ wire width 4 $add$libresoc.v:176777$10357_Y
+ attribute \src "libresoc.v:176778.19-176778.134"
+ wire width 4 $add$libresoc.v:176778$10358_Y
+ attribute \src "libresoc.v:176779.19-176779.134"
+ wire width 4 $add$libresoc.v:176779$10359_Y
+ attribute \src "libresoc.v:176780.18-176780.125"
+ wire width 3 $add$libresoc.v:176780$10360_Y
+ attribute \src "libresoc.v:176781.19-176781.134"
+ wire width 4 $add$libresoc.v:176781$10361_Y
+ attribute \src "libresoc.v:176782.19-176782.134"
+ wire width 4 $add$libresoc.v:176782$10362_Y
+ attribute \src "libresoc.v:176783.19-176783.134"
+ wire width 4 $add$libresoc.v:176783$10363_Y
+ attribute \src "libresoc.v:176784.19-176784.134"
+ wire width 4 $add$libresoc.v:176784$10364_Y
+ attribute \src "libresoc.v:176785.19-176785.134"
+ wire width 4 $add$libresoc.v:176785$10365_Y
+ attribute \src "libresoc.v:176786.19-176786.134"
+ wire width 4 $add$libresoc.v:176786$10366_Y
+ attribute \src "libresoc.v:176787.19-176787.134"
+ wire width 4 $add$libresoc.v:176787$10367_Y
+ attribute \src "libresoc.v:176788.19-176788.134"
+ wire width 4 $add$libresoc.v:176788$10368_Y
+ attribute \src "libresoc.v:176789.19-176789.134"
+ wire width 4 $add$libresoc.v:176789$10369_Y
+ attribute \src "libresoc.v:176790.19-176790.132"
+ wire width 5 $add$libresoc.v:176790$10370_Y
+ attribute \src "libresoc.v:176791.18-176791.125"
+ wire width 3 $add$libresoc.v:176791$10371_Y
+ attribute \src "libresoc.v:176792.19-176792.132"
+ wire width 5 $add$libresoc.v:176792$10372_Y
+ attribute \src "libresoc.v:176793.19-176793.132"
+ wire width 5 $add$libresoc.v:176793$10373_Y
+ attribute \src "libresoc.v:176794.19-176794.132"
+ wire width 5 $add$libresoc.v:176794$10374_Y
+ attribute \src "libresoc.v:176795.19-176795.132"
+ wire width 5 $add$libresoc.v:176795$10375_Y
+ attribute \src "libresoc.v:176796.19-176796.134"
+ wire width 5 $add$libresoc.v:176796$10376_Y
+ attribute \src "libresoc.v:176797.19-176797.134"
+ wire width 5 $add$libresoc.v:176797$10377_Y
+ attribute \src "libresoc.v:176798.19-176798.134"
+ wire width 5 $add$libresoc.v:176798$10378_Y
+ attribute \src "libresoc.v:176799.19-176799.132"
+ wire width 6 $add$libresoc.v:176799$10379_Y
+ attribute \src "libresoc.v:176800.19-176800.132"
+ wire width 6 $add$libresoc.v:176800$10380_Y
+ attribute \src "libresoc.v:176801.19-176801.132"
+ wire width 6 $add$libresoc.v:176801$10381_Y
+ attribute \src "libresoc.v:176802.18-176802.127"
+ wire width 3 $add$libresoc.v:176802$10382_Y
+ attribute \src "libresoc.v:176803.19-176803.132"
+ wire width 6 $add$libresoc.v:176803$10383_Y
+ attribute \src "libresoc.v:176804.19-176804.132"
+ wire width 7 $add$libresoc.v:176804$10384_Y
+ attribute \src "libresoc.v:176805.19-176805.132"
+ wire width 7 $add$libresoc.v:176805$10385_Y
+ attribute \src "libresoc.v:176806.19-176806.132"
+ wire width 8 $add$libresoc.v:176806$10386_Y
+ attribute \src "libresoc.v:176817.18-176817.127"
+ wire width 3 $add$libresoc.v:176817$10405_Y
+ attribute \src "libresoc.v:176821.18-176821.127"
+ wire width 3 $add$libresoc.v:176821$10412_Y
+ attribute \src "libresoc.v:176822.18-176822.127"
+ wire width 3 $add$libresoc.v:176822$10413_Y
+ attribute \src "libresoc.v:176823.17-176823.124"
+ wire width 3 $add$libresoc.v:176823$10414_Y
+ attribute \src "libresoc.v:176824.18-176824.127"
+ wire width 3 $add$libresoc.v:176824$10415_Y
+ attribute \src "libresoc.v:176825.18-176825.127"
+ wire width 3 $add$libresoc.v:176825$10416_Y
+ attribute \src "libresoc.v:176826.18-176826.127"
+ wire width 3 $add$libresoc.v:176826$10417_Y
+ attribute \src "libresoc.v:176827.18-176827.127"
+ wire width 3 $add$libresoc.v:176827$10418_Y
+ attribute \src "libresoc.v:176828.18-176828.127"
+ wire width 3 $add$libresoc.v:176828$10419_Y
+ attribute \src "libresoc.v:176829.18-176829.127"
+ wire width 3 $add$libresoc.v:176829$10420_Y
+ attribute \src "libresoc.v:176830.18-176830.127"
+ wire width 3 $add$libresoc.v:176830$10421_Y
+ attribute \src "libresoc.v:176831.18-176831.127"
+ wire width 3 $add$libresoc.v:176831$10422_Y
+ attribute \src "libresoc.v:176832.18-176832.127"
+ wire width 3 $add$libresoc.v:176832$10423_Y
+ attribute \src "libresoc.v:176833.18-176833.127"
+ wire width 3 $add$libresoc.v:176833$10424_Y
+ attribute \src "libresoc.v:176834.17-176834.124"
+ wire width 3 $add$libresoc.v:176834$10425_Y
+ attribute \src "libresoc.v:176835.18-176835.127"
+ wire width 3 $add$libresoc.v:176835$10426_Y
+ attribute \src "libresoc.v:176836.18-176836.127"
+ wire width 3 $add$libresoc.v:176836$10427_Y
+ attribute \src "libresoc.v:176837.18-176837.127"
+ wire width 3 $add$libresoc.v:176837$10428_Y
+ attribute \src "libresoc.v:176838.18-176838.127"
+ wire width 3 $add$libresoc.v:176838$10429_Y
+ attribute \src "libresoc.v:176839.18-176839.127"
+ wire width 3 $add$libresoc.v:176839$10430_Y
+ attribute \src "libresoc.v:176840.18-176840.127"
+ wire width 3 $add$libresoc.v:176840$10431_Y
+ attribute \src "libresoc.v:176841.18-176841.127"
+ wire width 3 $add$libresoc.v:176841$10432_Y
+ attribute \src "libresoc.v:176842.18-176842.127"
+ wire width 3 $add$libresoc.v:176842$10433_Y
+ attribute \src "libresoc.v:176843.18-176843.127"
+ wire width 3 $add$libresoc.v:176843$10434_Y
+ attribute \src "libresoc.v:176844.18-176844.127"
+ wire width 3 $add$libresoc.v:176844$10435_Y
+ attribute \src "libresoc.v:176845.17-176845.124"
+ wire width 3 $add$libresoc.v:176845$10436_Y
+ attribute \src "libresoc.v:176846.18-176846.127"
+ wire width 3 $add$libresoc.v:176846$10437_Y
+ attribute \src "libresoc.v:176847.18-176847.127"
+ wire width 3 $add$libresoc.v:176847$10438_Y
+ attribute \src "libresoc.v:176848.18-176848.127"
+ wire width 3 $add$libresoc.v:176848$10439_Y
+ attribute \src "libresoc.v:176849.18-176849.131"
+ wire width 4 $add$libresoc.v:176849$10440_Y
+ attribute \src "libresoc.v:176807.19-176807.111"
+ wire $eq$libresoc.v:176807$10387_Y
+ attribute \src "libresoc.v:176808.19-176808.111"
+ wire $eq$libresoc.v:176808$10388_Y
+ attribute \src "libresoc.v:176809.19-176809.104"
+ wire width 8 $extend$libresoc.v:176809$10389_Y
+ attribute \src "libresoc.v:176810.19-176810.104"
+ wire width 8 $extend$libresoc.v:176810$10391_Y
+ attribute \src "libresoc.v:176811.19-176811.104"
+ wire width 8 $extend$libresoc.v:176811$10393_Y
+ attribute \src "libresoc.v:176812.19-176812.104"
+ wire width 8 $extend$libresoc.v:176812$10395_Y
+ attribute \src "libresoc.v:176813.19-176813.104"
+ wire width 8 $extend$libresoc.v:176813$10397_Y
+ attribute \src "libresoc.v:176814.19-176814.104"
+ wire width 8 $extend$libresoc.v:176814$10399_Y
+ attribute \src "libresoc.v:176815.19-176815.104"
+ wire width 8 $extend$libresoc.v:176815$10401_Y
+ attribute \src "libresoc.v:176816.19-176816.104"
+ wire width 8 $extend$libresoc.v:176816$10403_Y
+ attribute \src "libresoc.v:176818.19-176818.104"
+ wire width 32 $extend$libresoc.v:176818$10406_Y
+ attribute \src "libresoc.v:176819.19-176819.104"
+ wire width 32 $extend$libresoc.v:176819$10408_Y
+ attribute \src "libresoc.v:176820.19-176820.104"
+ wire width 64 $extend$libresoc.v:176820$10410_Y
+ attribute \src "libresoc.v:176809.19-176809.104"
+ wire width 8 $pos$libresoc.v:176809$10390_Y
+ attribute \src "libresoc.v:176810.19-176810.104"
+ wire width 8 $pos$libresoc.v:176810$10392_Y
+ attribute \src "libresoc.v:176811.19-176811.104"
+ wire width 8 $pos$libresoc.v:176811$10394_Y
+ attribute \src "libresoc.v:176812.19-176812.104"
+ wire width 8 $pos$libresoc.v:176812$10396_Y
+ attribute \src "libresoc.v:176813.19-176813.104"
+ wire width 8 $pos$libresoc.v:176813$10398_Y
+ attribute \src "libresoc.v:176814.19-176814.104"
+ wire width 8 $pos$libresoc.v:176814$10400_Y
+ attribute \src "libresoc.v:176815.19-176815.104"
+ wire width 8 $pos$libresoc.v:176815$10402_Y
+ attribute \src "libresoc.v:176816.19-176816.104"
+ wire width 8 $pos$libresoc.v:176816$10404_Y
+ attribute \src "libresoc.v:176818.19-176818.104"
+ wire width 32 $pos$libresoc.v:176818$10407_Y
+ attribute \src "libresoc.v:176819.19-176819.104"
+ wire width 32 $pos$libresoc.v:176819$10409_Y
+ attribute \src "libresoc.v:176820.19-176820.104"
+ wire width 64 $pos$libresoc.v:176820$10411_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 64 input 3 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29"
wire width 64 input 1 \data_len
- attribute \src "libresoc.v:176698.7-176698.15"
+ attribute \src "libresoc.v:176362.7-176362.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30"
wire width 64 output 2 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 7 \pop_7_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177110$10406
+ cell $add $add$libresoc.v:176774$10354
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_2 }
connect \B { 2'00 \pop_2_3 }
- connect \Y $add$libresoc.v:177110$10406_Y
+ connect \Y $add$libresoc.v:176774$10354_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177111$10407
+ cell $add $add$libresoc.v:176775$10355
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_4 }
connect \B { 2'00 \pop_2_5 }
- connect \Y $add$libresoc.v:177111$10407_Y
+ connect \Y $add$libresoc.v:176775$10355_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177112$10408
+ cell $add $add$libresoc.v:176776$10356
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_6 }
connect \B { 2'00 \pop_2_7 }
- connect \Y $add$libresoc.v:177112$10408_Y
+ connect \Y $add$libresoc.v:176776$10356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177113$10409
+ cell $add $add$libresoc.v:176777$10357
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_8 }
connect \B { 2'00 \pop_2_9 }
- connect \Y $add$libresoc.v:177113$10409_Y
+ connect \Y $add$libresoc.v:176777$10357_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177114$10410
+ cell $add $add$libresoc.v:176778$10358
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_10 }
connect \B { 2'00 \pop_2_11 }
- connect \Y $add$libresoc.v:177114$10410_Y
+ connect \Y $add$libresoc.v:176778$10358_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177115$10411
+ cell $add $add$libresoc.v:176779$10359
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_12 }
connect \B { 2'00 \pop_2_13 }
- connect \Y $add$libresoc.v:177115$10411_Y
+ connect \Y $add$libresoc.v:176779$10359_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177116$10412
+ cell $add $add$libresoc.v:176780$10360
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [6] }
connect \B { 2'00 \a [7] }
- connect \Y $add$libresoc.v:177116$10412_Y
+ connect \Y $add$libresoc.v:176780$10360_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177117$10413
+ cell $add $add$libresoc.v:176781$10361
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_14 }
connect \B { 2'00 \pop_2_15 }
- connect \Y $add$libresoc.v:177117$10413_Y
+ connect \Y $add$libresoc.v:176781$10361_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177118$10414
+ cell $add $add$libresoc.v:176782$10362
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_16 }
connect \B { 2'00 \pop_2_17 }
- connect \Y $add$libresoc.v:177118$10414_Y
+ connect \Y $add$libresoc.v:176782$10362_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177119$10415
+ cell $add $add$libresoc.v:176783$10363
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_18 }
connect \B { 2'00 \pop_2_19 }
- connect \Y $add$libresoc.v:177119$10415_Y
+ connect \Y $add$libresoc.v:176783$10363_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177120$10416
+ cell $add $add$libresoc.v:176784$10364
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_20 }
connect \B { 2'00 \pop_2_21 }
- connect \Y $add$libresoc.v:177120$10416_Y
+ connect \Y $add$libresoc.v:176784$10364_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177121$10417
+ cell $add $add$libresoc.v:176785$10365
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_22 }
connect \B { 2'00 \pop_2_23 }
- connect \Y $add$libresoc.v:177121$10417_Y
+ connect \Y $add$libresoc.v:176785$10365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177122$10418
+ cell $add $add$libresoc.v:176786$10366
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_24 }
connect \B { 2'00 \pop_2_25 }
- connect \Y $add$libresoc.v:177122$10418_Y
+ connect \Y $add$libresoc.v:176786$10366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177123$10419
+ cell $add $add$libresoc.v:176787$10367
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_26 }
connect \B { 2'00 \pop_2_27 }
- connect \Y $add$libresoc.v:177123$10419_Y
+ connect \Y $add$libresoc.v:176787$10367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177124$10420
+ cell $add $add$libresoc.v:176788$10368
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_28 }
connect \B { 2'00 \pop_2_29 }
- connect \Y $add$libresoc.v:177124$10420_Y
+ connect \Y $add$libresoc.v:176788$10368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177125$10421
+ cell $add $add$libresoc.v:176789$10369
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_30 }
connect \B { 2'00 \pop_2_31 }
- connect \Y $add$libresoc.v:177125$10421_Y
+ connect \Y $add$libresoc.v:176789$10369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177126$10422
+ cell $add $add$libresoc.v:176790$10370
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_0 }
connect \B { 2'00 \pop_3_1 }
- connect \Y $add$libresoc.v:177126$10422_Y
+ connect \Y $add$libresoc.v:176790$10370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177127$10423
+ cell $add $add$libresoc.v:176791$10371
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [8] }
connect \B { 2'00 \a [9] }
- connect \Y $add$libresoc.v:177127$10423_Y
+ connect \Y $add$libresoc.v:176791$10371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177128$10424
+ cell $add $add$libresoc.v:176792$10372
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_2 }
connect \B { 2'00 \pop_3_3 }
- connect \Y $add$libresoc.v:177128$10424_Y
+ connect \Y $add$libresoc.v:176792$10372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177129$10425
+ cell $add $add$libresoc.v:176793$10373
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_4 }
connect \B { 2'00 \pop_3_5 }
- connect \Y $add$libresoc.v:177129$10425_Y
+ connect \Y $add$libresoc.v:176793$10373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177130$10426
+ cell $add $add$libresoc.v:176794$10374
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_6 }
connect \B { 2'00 \pop_3_7 }
- connect \Y $add$libresoc.v:177130$10426_Y
+ connect \Y $add$libresoc.v:176794$10374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177131$10427
+ cell $add $add$libresoc.v:176795$10375
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_8 }
connect \B { 2'00 \pop_3_9 }
- connect \Y $add$libresoc.v:177131$10427_Y
+ connect \Y $add$libresoc.v:176795$10375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177132$10428
+ cell $add $add$libresoc.v:176796$10376
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_10 }
connect \B { 2'00 \pop_3_11 }
- connect \Y $add$libresoc.v:177132$10428_Y
+ connect \Y $add$libresoc.v:176796$10376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177133$10429
+ cell $add $add$libresoc.v:176797$10377
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_12 }
connect \B { 2'00 \pop_3_13 }
- connect \Y $add$libresoc.v:177133$10429_Y
+ connect \Y $add$libresoc.v:176797$10377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177134$10430
+ cell $add $add$libresoc.v:176798$10378
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_14 }
connect \B { 2'00 \pop_3_15 }
- connect \Y $add$libresoc.v:177134$10430_Y
+ connect \Y $add$libresoc.v:176798$10378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177135$10431
+ cell $add $add$libresoc.v:176799$10379
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_0 }
connect \B { 2'00 \pop_4_1 }
- connect \Y $add$libresoc.v:177135$10431_Y
+ connect \Y $add$libresoc.v:176799$10379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177136$10432
+ cell $add $add$libresoc.v:176800$10380
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_2 }
connect \B { 2'00 \pop_4_3 }
- connect \Y $add$libresoc.v:177136$10432_Y
+ connect \Y $add$libresoc.v:176800$10380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177137$10433
+ cell $add $add$libresoc.v:176801$10381
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_4 }
connect \B { 2'00 \pop_4_5 }
- connect \Y $add$libresoc.v:177137$10433_Y
+ connect \Y $add$libresoc.v:176801$10381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177138$10434
+ cell $add $add$libresoc.v:176802$10382
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [10] }
connect \B { 2'00 \a [11] }
- connect \Y $add$libresoc.v:177138$10434_Y
+ connect \Y $add$libresoc.v:176802$10382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177139$10435
+ cell $add $add$libresoc.v:176803$10383
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_6 }
connect \B { 2'00 \pop_4_7 }
- connect \Y $add$libresoc.v:177139$10435_Y
+ connect \Y $add$libresoc.v:176803$10383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177140$10436
+ cell $add $add$libresoc.v:176804$10384
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A { 2'00 \pop_5_0 }
connect \B { 2'00 \pop_5_1 }
- connect \Y $add$libresoc.v:177140$10436_Y
+ connect \Y $add$libresoc.v:176804$10384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177141$10437
+ cell $add $add$libresoc.v:176805$10385
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A { 2'00 \pop_5_2 }
connect \B { 2'00 \pop_5_3 }
- connect \Y $add$libresoc.v:177141$10437_Y
+ connect \Y $add$libresoc.v:176805$10385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177142$10438
+ cell $add $add$libresoc.v:176806$10386
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A { 2'00 \pop_6_0 }
connect \B { 2'00 \pop_6_1 }
- connect \Y $add$libresoc.v:177142$10438_Y
+ connect \Y $add$libresoc.v:176806$10386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177153$10457
+ cell $add $add$libresoc.v:176817$10405
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [12] }
connect \B { 2'00 \a [13] }
- connect \Y $add$libresoc.v:177153$10457_Y
+ connect \Y $add$libresoc.v:176817$10405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177157$10464
+ cell $add $add$libresoc.v:176821$10412
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [14] }
connect \B { 2'00 \a [15] }
- connect \Y $add$libresoc.v:177157$10464_Y
+ connect \Y $add$libresoc.v:176821$10412_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177158$10465
+ cell $add $add$libresoc.v:176822$10413
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [16] }
connect \B { 2'00 \a [17] }
- connect \Y $add$libresoc.v:177158$10465_Y
+ connect \Y $add$libresoc.v:176822$10413_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177159$10466
+ cell $add $add$libresoc.v:176823$10414
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [0] }
connect \B { 2'00 \a [1] }
- connect \Y $add$libresoc.v:177159$10466_Y
+ connect \Y $add$libresoc.v:176823$10414_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177160$10467
+ cell $add $add$libresoc.v:176824$10415
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [18] }
connect \B { 2'00 \a [19] }
- connect \Y $add$libresoc.v:177160$10467_Y
+ connect \Y $add$libresoc.v:176824$10415_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177161$10468
+ cell $add $add$libresoc.v:176825$10416
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [20] }
connect \B { 2'00 \a [21] }
- connect \Y $add$libresoc.v:177161$10468_Y
+ connect \Y $add$libresoc.v:176825$10416_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177162$10469
+ cell $add $add$libresoc.v:176826$10417
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [22] }
connect \B { 2'00 \a [23] }
- connect \Y $add$libresoc.v:177162$10469_Y
+ connect \Y $add$libresoc.v:176826$10417_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177163$10470
+ cell $add $add$libresoc.v:176827$10418
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [24] }
connect \B { 2'00 \a [25] }
- connect \Y $add$libresoc.v:177163$10470_Y
+ connect \Y $add$libresoc.v:176827$10418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177164$10471
+ cell $add $add$libresoc.v:176828$10419
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [26] }
connect \B { 2'00 \a [27] }
- connect \Y $add$libresoc.v:177164$10471_Y
+ connect \Y $add$libresoc.v:176828$10419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177165$10472
+ cell $add $add$libresoc.v:176829$10420
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [28] }
connect \B { 2'00 \a [29] }
- connect \Y $add$libresoc.v:177165$10472_Y
+ connect \Y $add$libresoc.v:176829$10420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177166$10473
+ cell $add $add$libresoc.v:176830$10421
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [30] }
connect \B { 2'00 \a [31] }
- connect \Y $add$libresoc.v:177166$10473_Y
+ connect \Y $add$libresoc.v:176830$10421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177167$10474
+ cell $add $add$libresoc.v:176831$10422
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [32] }
connect \B { 2'00 \a [33] }
- connect \Y $add$libresoc.v:177167$10474_Y
+ connect \Y $add$libresoc.v:176831$10422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177168$10475
+ cell $add $add$libresoc.v:176832$10423
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [34] }
connect \B { 2'00 \a [35] }
- connect \Y $add$libresoc.v:177168$10475_Y
+ connect \Y $add$libresoc.v:176832$10423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177169$10476
+ cell $add $add$libresoc.v:176833$10424
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [36] }
connect \B { 2'00 \a [37] }
- connect \Y $add$libresoc.v:177169$10476_Y
+ connect \Y $add$libresoc.v:176833$10424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177170$10477
+ cell $add $add$libresoc.v:176834$10425
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [2] }
connect \B { 2'00 \a [3] }
- connect \Y $add$libresoc.v:177170$10477_Y
+ connect \Y $add$libresoc.v:176834$10425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177171$10478
+ cell $add $add$libresoc.v:176835$10426
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [38] }
connect \B { 2'00 \a [39] }
- connect \Y $add$libresoc.v:177171$10478_Y
+ connect \Y $add$libresoc.v:176835$10426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177172$10479
+ cell $add $add$libresoc.v:176836$10427
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [40] }
connect \B { 2'00 \a [41] }
- connect \Y $add$libresoc.v:177172$10479_Y
+ connect \Y $add$libresoc.v:176836$10427_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177173$10480
+ cell $add $add$libresoc.v:176837$10428
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [42] }
connect \B { 2'00 \a [43] }
- connect \Y $add$libresoc.v:177173$10480_Y
+ connect \Y $add$libresoc.v:176837$10428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177174$10481
+ cell $add $add$libresoc.v:176838$10429
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [44] }
connect \B { 2'00 \a [45] }
- connect \Y $add$libresoc.v:177174$10481_Y
+ connect \Y $add$libresoc.v:176838$10429_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177175$10482
+ cell $add $add$libresoc.v:176839$10430
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [46] }
connect \B { 2'00 \a [47] }
- connect \Y $add$libresoc.v:177175$10482_Y
+ connect \Y $add$libresoc.v:176839$10430_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177176$10483
+ cell $add $add$libresoc.v:176840$10431
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [48] }
connect \B { 2'00 \a [49] }
- connect \Y $add$libresoc.v:177176$10483_Y
+ connect \Y $add$libresoc.v:176840$10431_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177177$10484
+ cell $add $add$libresoc.v:176841$10432
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [50] }
connect \B { 2'00 \a [51] }
- connect \Y $add$libresoc.v:177177$10484_Y
+ connect \Y $add$libresoc.v:176841$10432_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177178$10485
+ cell $add $add$libresoc.v:176842$10433
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [52] }
connect \B { 2'00 \a [53] }
- connect \Y $add$libresoc.v:177178$10485_Y
+ connect \Y $add$libresoc.v:176842$10433_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177179$10486
+ cell $add $add$libresoc.v:176843$10434
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [54] }
connect \B { 2'00 \a [55] }
- connect \Y $add$libresoc.v:177179$10486_Y
+ connect \Y $add$libresoc.v:176843$10434_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177180$10487
+ cell $add $add$libresoc.v:176844$10435
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [56] }
connect \B { 2'00 \a [57] }
- connect \Y $add$libresoc.v:177180$10487_Y
+ connect \Y $add$libresoc.v:176844$10435_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177181$10488
+ cell $add $add$libresoc.v:176845$10436
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [4] }
connect \B { 2'00 \a [5] }
- connect \Y $add$libresoc.v:177181$10488_Y
+ connect \Y $add$libresoc.v:176845$10436_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177182$10489
+ cell $add $add$libresoc.v:176846$10437
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [58] }
connect \B { 2'00 \a [59] }
- connect \Y $add$libresoc.v:177182$10489_Y
+ connect \Y $add$libresoc.v:176846$10437_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177183$10490
+ cell $add $add$libresoc.v:176847$10438
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [60] }
connect \B { 2'00 \a [61] }
- connect \Y $add$libresoc.v:177183$10490_Y
+ connect \Y $add$libresoc.v:176847$10438_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177184$10491
+ cell $add $add$libresoc.v:176848$10439
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [62] }
connect \B { 2'00 \a [63] }
- connect \Y $add$libresoc.v:177184$10491_Y
+ connect \Y $add$libresoc.v:176848$10439_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:177185$10492
+ cell $add $add$libresoc.v:176849$10440
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_0 }
connect \B { 2'00 \pop_2_1 }
- connect \Y $add$libresoc.v:177185$10492_Y
+ connect \Y $add$libresoc.v:176849$10440_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55"
- cell $eq $eq$libresoc.v:177143$10439
+ cell $eq $eq$libresoc.v:176807$10387
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \data_len
connect \B 1'1
- connect \Y $eq$libresoc.v:177143$10439_Y
+ connect \Y $eq$libresoc.v:176807$10387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59"
- cell $eq $eq$libresoc.v:177144$10440
+ cell $eq $eq$libresoc.v:176808$10388
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \data_len
connect \B 3'100
- connect \Y $eq$libresoc.v:177144$10440_Y
+ connect \Y $eq$libresoc.v:176808$10388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177145$10441
+ cell $pos $extend$libresoc.v:176809$10389
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_0
- connect \Y $extend$libresoc.v:177145$10441_Y
+ connect \Y $extend$libresoc.v:176809$10389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177146$10443
+ cell $pos $extend$libresoc.v:176810$10391
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_1
- connect \Y $extend$libresoc.v:177146$10443_Y
+ connect \Y $extend$libresoc.v:176810$10391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177147$10445
+ cell $pos $extend$libresoc.v:176811$10393
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_2
- connect \Y $extend$libresoc.v:177147$10445_Y
+ connect \Y $extend$libresoc.v:176811$10393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177148$10447
+ cell $pos $extend$libresoc.v:176812$10395
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_3
- connect \Y $extend$libresoc.v:177148$10447_Y
+ connect \Y $extend$libresoc.v:176812$10395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177149$10449
+ cell $pos $extend$libresoc.v:176813$10397
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_4
- connect \Y $extend$libresoc.v:177149$10449_Y
+ connect \Y $extend$libresoc.v:176813$10397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177150$10451
+ cell $pos $extend$libresoc.v:176814$10399
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_5
- connect \Y $extend$libresoc.v:177150$10451_Y
+ connect \Y $extend$libresoc.v:176814$10399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177151$10453
+ cell $pos $extend$libresoc.v:176815$10401
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_6
- connect \Y $extend$libresoc.v:177151$10453_Y
+ connect \Y $extend$libresoc.v:176815$10401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177152$10455
+ cell $pos $extend$libresoc.v:176816$10403
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_7
- connect \Y $extend$libresoc.v:177152$10455_Y
+ connect \Y $extend$libresoc.v:176816$10403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177154$10458
+ cell $pos $extend$libresoc.v:176818$10406
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 32
connect \A \pop_6_0
- connect \Y $extend$libresoc.v:177154$10458_Y
+ connect \Y $extend$libresoc.v:176818$10406_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177155$10460
+ cell $pos $extend$libresoc.v:176819$10408
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 32
connect \A \pop_6_1
- connect \Y $extend$libresoc.v:177155$10460_Y
+ connect \Y $extend$libresoc.v:176819$10408_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:177156$10462
+ cell $pos $extend$libresoc.v:176820$10410
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 64
connect \A \pop_7_0
- connect \Y $extend$libresoc.v:177156$10462_Y
+ connect \Y $extend$libresoc.v:176820$10410_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177145$10442
+ cell $pos $pos$libresoc.v:176809$10390
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177145$10441_Y
- connect \Y $pos$libresoc.v:177145$10442_Y
+ connect \A $extend$libresoc.v:176809$10389_Y
+ connect \Y $pos$libresoc.v:176809$10390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177146$10444
+ cell $pos $pos$libresoc.v:176810$10392
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177146$10443_Y
- connect \Y $pos$libresoc.v:177146$10444_Y
+ connect \A $extend$libresoc.v:176810$10391_Y
+ connect \Y $pos$libresoc.v:176810$10392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177147$10446
+ cell $pos $pos$libresoc.v:176811$10394
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177147$10445_Y
- connect \Y $pos$libresoc.v:177147$10446_Y
+ connect \A $extend$libresoc.v:176811$10393_Y
+ connect \Y $pos$libresoc.v:176811$10394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177148$10448
+ cell $pos $pos$libresoc.v:176812$10396
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177148$10447_Y
- connect \Y $pos$libresoc.v:177148$10448_Y
+ connect \A $extend$libresoc.v:176812$10395_Y
+ connect \Y $pos$libresoc.v:176812$10396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177149$10450
+ cell $pos $pos$libresoc.v:176813$10398
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177149$10449_Y
- connect \Y $pos$libresoc.v:177149$10450_Y
+ connect \A $extend$libresoc.v:176813$10397_Y
+ connect \Y $pos$libresoc.v:176813$10398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177150$10452
+ cell $pos $pos$libresoc.v:176814$10400
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177150$10451_Y
- connect \Y $pos$libresoc.v:177150$10452_Y
+ connect \A $extend$libresoc.v:176814$10399_Y
+ connect \Y $pos$libresoc.v:176814$10400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177151$10454
+ cell $pos $pos$libresoc.v:176815$10402
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177151$10453_Y
- connect \Y $pos$libresoc.v:177151$10454_Y
+ connect \A $extend$libresoc.v:176815$10401_Y
+ connect \Y $pos$libresoc.v:176815$10402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177152$10456
+ cell $pos $pos$libresoc.v:176816$10404
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:177152$10455_Y
- connect \Y $pos$libresoc.v:177152$10456_Y
+ connect \A $extend$libresoc.v:176816$10403_Y
+ connect \Y $pos$libresoc.v:176816$10404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177154$10459
+ cell $pos $pos$libresoc.v:176818$10407
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $extend$libresoc.v:177154$10458_Y
- connect \Y $pos$libresoc.v:177154$10459_Y
+ connect \A $extend$libresoc.v:176818$10406_Y
+ connect \Y $pos$libresoc.v:176818$10407_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177155$10461
+ cell $pos $pos$libresoc.v:176819$10409
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $extend$libresoc.v:177155$10460_Y
- connect \Y $pos$libresoc.v:177155$10461_Y
+ connect \A $extend$libresoc.v:176819$10408_Y
+ connect \Y $pos$libresoc.v:176819$10409_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:177156$10463
+ cell $pos $pos$libresoc.v:176820$10411
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:177156$10462_Y
- connect \Y $pos$libresoc.v:177156$10463_Y
+ connect \A $extend$libresoc.v:176820$10410_Y
+ connect \Y $pos$libresoc.v:176820$10411_Y
end
- attribute \src "libresoc.v:176698.7-176698.20"
- process $proc$libresoc.v:176698$10494
+ attribute \src "libresoc.v:176362.7-176362.20"
+ process $proc$libresoc.v:176362$10442
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:177186.3-177212.6"
- process $proc$libresoc.v:177186$10493
+ attribute \src "libresoc.v:176850.3-176876.6"
+ process $proc$libresoc.v:176850$10441
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:177187.5-177187.29"
+ attribute \src "libresoc.v:176851.5-176851.29"
switch \initial
- attribute \src "libresoc.v:177187.9-177187.17"
+ attribute \src "libresoc.v:176851.9-176851.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- connect \$101 $add$libresoc.v:177110$10406_Y
- connect \$104 $add$libresoc.v:177111$10407_Y
- connect \$107 $add$libresoc.v:177112$10408_Y
- connect \$110 $add$libresoc.v:177113$10409_Y
- connect \$113 $add$libresoc.v:177114$10410_Y
- connect \$116 $add$libresoc.v:177115$10411_Y
- connect \$11 $add$libresoc.v:177116$10412_Y
- connect \$119 $add$libresoc.v:177117$10413_Y
- connect \$122 $add$libresoc.v:177118$10414_Y
- connect \$125 $add$libresoc.v:177119$10415_Y
- connect \$128 $add$libresoc.v:177120$10416_Y
- connect \$131 $add$libresoc.v:177121$10417_Y
- connect \$134 $add$libresoc.v:177122$10418_Y
- connect \$137 $add$libresoc.v:177123$10419_Y
- connect \$140 $add$libresoc.v:177124$10420_Y
- connect \$143 $add$libresoc.v:177125$10421_Y
- connect \$146 $add$libresoc.v:177126$10422_Y
- connect \$14 $add$libresoc.v:177127$10423_Y
- connect \$149 $add$libresoc.v:177128$10424_Y
- connect \$152 $add$libresoc.v:177129$10425_Y
- connect \$155 $add$libresoc.v:177130$10426_Y
- connect \$158 $add$libresoc.v:177131$10427_Y
- connect \$161 $add$libresoc.v:177132$10428_Y
- connect \$164 $add$libresoc.v:177133$10429_Y
- connect \$167 $add$libresoc.v:177134$10430_Y
- connect \$170 $add$libresoc.v:177135$10431_Y
- connect \$173 $add$libresoc.v:177136$10432_Y
- connect \$176 $add$libresoc.v:177137$10433_Y
- connect \$17 $add$libresoc.v:177138$10434_Y
- connect \$179 $add$libresoc.v:177139$10435_Y
- connect \$182 $add$libresoc.v:177140$10436_Y
- connect \$185 $add$libresoc.v:177141$10437_Y
- connect \$188 $add$libresoc.v:177142$10438_Y
- connect \$190 $eq$libresoc.v:177143$10439_Y
- connect \$192 $eq$libresoc.v:177144$10440_Y
- connect \$194 $pos$libresoc.v:177145$10442_Y
- connect \$196 $pos$libresoc.v:177146$10444_Y
- connect \$198 $pos$libresoc.v:177147$10446_Y
- connect \$200 $pos$libresoc.v:177148$10448_Y
- connect \$202 $pos$libresoc.v:177149$10450_Y
- connect \$204 $pos$libresoc.v:177150$10452_Y
- connect \$206 $pos$libresoc.v:177151$10454_Y
- connect \$208 $pos$libresoc.v:177152$10456_Y
- connect \$20 $add$libresoc.v:177153$10457_Y
- connect \$210 $pos$libresoc.v:177154$10459_Y
- connect \$212 $pos$libresoc.v:177155$10461_Y
- connect \$214 $pos$libresoc.v:177156$10463_Y
- connect \$23 $add$libresoc.v:177157$10464_Y
- connect \$26 $add$libresoc.v:177158$10465_Y
- connect \$2 $add$libresoc.v:177159$10466_Y
- connect \$29 $add$libresoc.v:177160$10467_Y
- connect \$32 $add$libresoc.v:177161$10468_Y
- connect \$35 $add$libresoc.v:177162$10469_Y
- connect \$38 $add$libresoc.v:177163$10470_Y
- connect \$41 $add$libresoc.v:177164$10471_Y
- connect \$44 $add$libresoc.v:177165$10472_Y
- connect \$47 $add$libresoc.v:177166$10473_Y
- connect \$50 $add$libresoc.v:177167$10474_Y
- connect \$53 $add$libresoc.v:177168$10475_Y
- connect \$56 $add$libresoc.v:177169$10476_Y
- connect \$5 $add$libresoc.v:177170$10477_Y
- connect \$59 $add$libresoc.v:177171$10478_Y
- connect \$62 $add$libresoc.v:177172$10479_Y
- connect \$65 $add$libresoc.v:177173$10480_Y
- connect \$68 $add$libresoc.v:177174$10481_Y
- connect \$71 $add$libresoc.v:177175$10482_Y
- connect \$74 $add$libresoc.v:177176$10483_Y
- connect \$77 $add$libresoc.v:177177$10484_Y
- connect \$80 $add$libresoc.v:177178$10485_Y
- connect \$83 $add$libresoc.v:177179$10486_Y
- connect \$86 $add$libresoc.v:177180$10487_Y
- connect \$8 $add$libresoc.v:177181$10488_Y
- connect \$89 $add$libresoc.v:177182$10489_Y
- connect \$92 $add$libresoc.v:177183$10490_Y
- connect \$95 $add$libresoc.v:177184$10491_Y
- connect \$98 $add$libresoc.v:177185$10492_Y
+ connect \$101 $add$libresoc.v:176774$10354_Y
+ connect \$104 $add$libresoc.v:176775$10355_Y
+ connect \$107 $add$libresoc.v:176776$10356_Y
+ connect \$110 $add$libresoc.v:176777$10357_Y
+ connect \$113 $add$libresoc.v:176778$10358_Y
+ connect \$116 $add$libresoc.v:176779$10359_Y
+ connect \$11 $add$libresoc.v:176780$10360_Y
+ connect \$119 $add$libresoc.v:176781$10361_Y
+ connect \$122 $add$libresoc.v:176782$10362_Y
+ connect \$125 $add$libresoc.v:176783$10363_Y
+ connect \$128 $add$libresoc.v:176784$10364_Y
+ connect \$131 $add$libresoc.v:176785$10365_Y
+ connect \$134 $add$libresoc.v:176786$10366_Y
+ connect \$137 $add$libresoc.v:176787$10367_Y
+ connect \$140 $add$libresoc.v:176788$10368_Y
+ connect \$143 $add$libresoc.v:176789$10369_Y
+ connect \$146 $add$libresoc.v:176790$10370_Y
+ connect \$14 $add$libresoc.v:176791$10371_Y
+ connect \$149 $add$libresoc.v:176792$10372_Y
+ connect \$152 $add$libresoc.v:176793$10373_Y
+ connect \$155 $add$libresoc.v:176794$10374_Y
+ connect \$158 $add$libresoc.v:176795$10375_Y
+ connect \$161 $add$libresoc.v:176796$10376_Y
+ connect \$164 $add$libresoc.v:176797$10377_Y
+ connect \$167 $add$libresoc.v:176798$10378_Y
+ connect \$170 $add$libresoc.v:176799$10379_Y
+ connect \$173 $add$libresoc.v:176800$10380_Y
+ connect \$176 $add$libresoc.v:176801$10381_Y
+ connect \$17 $add$libresoc.v:176802$10382_Y
+ connect \$179 $add$libresoc.v:176803$10383_Y
+ connect \$182 $add$libresoc.v:176804$10384_Y
+ connect \$185 $add$libresoc.v:176805$10385_Y
+ connect \$188 $add$libresoc.v:176806$10386_Y
+ connect \$190 $eq$libresoc.v:176807$10387_Y
+ connect \$192 $eq$libresoc.v:176808$10388_Y
+ connect \$194 $pos$libresoc.v:176809$10390_Y
+ connect \$196 $pos$libresoc.v:176810$10392_Y
+ connect \$198 $pos$libresoc.v:176811$10394_Y
+ connect \$200 $pos$libresoc.v:176812$10396_Y
+ connect \$202 $pos$libresoc.v:176813$10398_Y
+ connect \$204 $pos$libresoc.v:176814$10400_Y
+ connect \$206 $pos$libresoc.v:176815$10402_Y
+ connect \$208 $pos$libresoc.v:176816$10404_Y
+ connect \$20 $add$libresoc.v:176817$10405_Y
+ connect \$210 $pos$libresoc.v:176818$10407_Y
+ connect \$212 $pos$libresoc.v:176819$10409_Y
+ connect \$214 $pos$libresoc.v:176820$10411_Y
+ connect \$23 $add$libresoc.v:176821$10412_Y
+ connect \$26 $add$libresoc.v:176822$10413_Y
+ connect \$2 $add$libresoc.v:176823$10414_Y
+ connect \$29 $add$libresoc.v:176824$10415_Y
+ connect \$32 $add$libresoc.v:176825$10416_Y
+ connect \$35 $add$libresoc.v:176826$10417_Y
+ connect \$38 $add$libresoc.v:176827$10418_Y
+ connect \$41 $add$libresoc.v:176828$10419_Y
+ connect \$44 $add$libresoc.v:176829$10420_Y
+ connect \$47 $add$libresoc.v:176830$10421_Y
+ connect \$50 $add$libresoc.v:176831$10422_Y
+ connect \$53 $add$libresoc.v:176832$10423_Y
+ connect \$56 $add$libresoc.v:176833$10424_Y
+ connect \$5 $add$libresoc.v:176834$10425_Y
+ connect \$59 $add$libresoc.v:176835$10426_Y
+ connect \$62 $add$libresoc.v:176836$10427_Y
+ connect \$65 $add$libresoc.v:176837$10428_Y
+ connect \$68 $add$libresoc.v:176838$10429_Y
+ connect \$71 $add$libresoc.v:176839$10430_Y
+ connect \$74 $add$libresoc.v:176840$10431_Y
+ connect \$77 $add$libresoc.v:176841$10432_Y
+ connect \$80 $add$libresoc.v:176842$10433_Y
+ connect \$83 $add$libresoc.v:176843$10434_Y
+ connect \$86 $add$libresoc.v:176844$10435_Y
+ connect \$8 $add$libresoc.v:176845$10436_Y
+ connect \$89 $add$libresoc.v:176846$10437_Y
+ connect \$92 $add$libresoc.v:176847$10438_Y
+ connect \$95 $add$libresoc.v:176848$10439_Y
+ connect \$98 $add$libresoc.v:176849$10440_Y
connect \$1 \$2
connect \$4 \$5
connect \$7 \$8
connect \pop_2_1 \$5 [1:0]
connect \pop_2_0 \$2 [1:0]
end
-attribute \src "libresoc.v:177343.1-177427.10"
+attribute \src "libresoc.v:177007.1-177091.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick"
attribute \generator "nMigen"
module \ppick
- attribute \src "libresoc.v:177400.17-177400.91"
- wire $not$libresoc.v:177400$10495_Y
- attribute \src "libresoc.v:177402.18-177402.93"
- wire $not$libresoc.v:177402$10497_Y
- attribute \src "libresoc.v:177404.18-177404.93"
- wire $not$libresoc.v:177404$10499_Y
- attribute \src "libresoc.v:177405.17-177405.138"
- wire width 8 $not$libresoc.v:177405$10500_Y
- attribute \src "libresoc.v:177407.18-177407.93"
- wire $not$libresoc.v:177407$10502_Y
- attribute \src "libresoc.v:177409.18-177409.93"
- wire $not$libresoc.v:177409$10504_Y
- attribute \src "libresoc.v:177411.18-177411.93"
- wire $not$libresoc.v:177411$10506_Y
- attribute \src "libresoc.v:177414.17-177414.91"
- wire $not$libresoc.v:177414$10509_Y
- attribute \src "libresoc.v:177401.18-177401.116"
- wire $reduce_or$libresoc.v:177401$10496_Y
- attribute \src "libresoc.v:177403.18-177403.122"
- wire $reduce_or$libresoc.v:177403$10498_Y
- attribute \src "libresoc.v:177406.18-177406.128"
- wire $reduce_or$libresoc.v:177406$10501_Y
- attribute \src "libresoc.v:177408.18-177408.134"
- wire $reduce_or$libresoc.v:177408$10503_Y
- attribute \src "libresoc.v:177410.18-177410.140"
- wire $reduce_or$libresoc.v:177410$10505_Y
- attribute \src "libresoc.v:177412.18-177412.90"
- wire $reduce_or$libresoc.v:177412$10507_Y
- attribute \src "libresoc.v:177413.17-177413.103"
- wire $reduce_or$libresoc.v:177413$10508_Y
- attribute \src "libresoc.v:177415.17-177415.109"
- wire $reduce_or$libresoc.v:177415$10510_Y
+ attribute \src "libresoc.v:177064.17-177064.91"
+ wire $not$libresoc.v:177064$10443_Y
+ attribute \src "libresoc.v:177066.18-177066.93"
+ wire $not$libresoc.v:177066$10445_Y
+ attribute \src "libresoc.v:177068.18-177068.93"
+ wire $not$libresoc.v:177068$10447_Y
+ attribute \src "libresoc.v:177069.17-177069.138"
+ wire width 8 $not$libresoc.v:177069$10448_Y
+ attribute \src "libresoc.v:177071.18-177071.93"
+ wire $not$libresoc.v:177071$10450_Y
+ attribute \src "libresoc.v:177073.18-177073.93"
+ wire $not$libresoc.v:177073$10452_Y
+ attribute \src "libresoc.v:177075.18-177075.93"
+ wire $not$libresoc.v:177075$10454_Y
+ attribute \src "libresoc.v:177078.17-177078.91"
+ wire $not$libresoc.v:177078$10457_Y
+ attribute \src "libresoc.v:177065.18-177065.116"
+ wire $reduce_or$libresoc.v:177065$10444_Y
+ attribute \src "libresoc.v:177067.18-177067.122"
+ wire $reduce_or$libresoc.v:177067$10446_Y
+ attribute \src "libresoc.v:177070.18-177070.128"
+ wire $reduce_or$libresoc.v:177070$10449_Y
+ attribute \src "libresoc.v:177072.18-177072.134"
+ wire $reduce_or$libresoc.v:177072$10451_Y
+ attribute \src "libresoc.v:177074.18-177074.140"
+ wire $reduce_or$libresoc.v:177074$10453_Y
+ attribute \src "libresoc.v:177076.18-177076.90"
+ wire $reduce_or$libresoc.v:177076$10455_Y
+ attribute \src "libresoc.v:177077.17-177077.103"
+ wire $reduce_or$libresoc.v:177077$10456_Y
+ attribute \src "libresoc.v:177079.17-177079.109"
+ wire $reduce_or$libresoc.v:177079$10458_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177400$10495
+ cell $not $not$libresoc.v:177064$10443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:177400$10495_Y
+ connect \Y $not$libresoc.v:177064$10443_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177402$10497
+ cell $not $not$libresoc.v:177066$10445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:177402$10497_Y
+ connect \Y $not$libresoc.v:177066$10445_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177404$10499
+ cell $not $not$libresoc.v:177068$10447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:177404$10499_Y
+ connect \Y $not$libresoc.v:177068$10447_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177405$10500
+ cell $not $not$libresoc.v:177069$10448
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:177405$10500_Y
+ connect \Y $not$libresoc.v:177069$10448_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177407$10502
+ cell $not $not$libresoc.v:177071$10450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:177407$10502_Y
+ connect \Y $not$libresoc.v:177071$10450_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177409$10504
+ cell $not $not$libresoc.v:177073$10452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:177409$10504_Y
+ connect \Y $not$libresoc.v:177073$10452_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177411$10506
+ cell $not $not$libresoc.v:177075$10454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:177411$10506_Y
+ connect \Y $not$libresoc.v:177075$10454_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177414$10509
+ cell $not $not$libresoc.v:177078$10457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:177414$10509_Y
+ connect \Y $not$libresoc.v:177078$10457_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177401$10496
+ cell $reduce_or $reduce_or$libresoc.v:177065$10444
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:177401$10496_Y
+ connect \Y $reduce_or$libresoc.v:177065$10444_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177403$10498
+ cell $reduce_or $reduce_or$libresoc.v:177067$10446
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:177403$10498_Y
+ connect \Y $reduce_or$libresoc.v:177067$10446_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177406$10501
+ cell $reduce_or $reduce_or$libresoc.v:177070$10449
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:177406$10501_Y
+ connect \Y $reduce_or$libresoc.v:177070$10449_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177408$10503
+ cell $reduce_or $reduce_or$libresoc.v:177072$10451
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:177408$10503_Y
+ connect \Y $reduce_or$libresoc.v:177072$10451_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177410$10505
+ cell $reduce_or $reduce_or$libresoc.v:177074$10453
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:177410$10505_Y
+ connect \Y $reduce_or$libresoc.v:177074$10453_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177412$10507
+ cell $reduce_or $reduce_or$libresoc.v:177076$10455
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177412$10507_Y
+ connect \Y $reduce_or$libresoc.v:177076$10455_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177413$10508
+ cell $reduce_or $reduce_or$libresoc.v:177077$10456
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177413$10508_Y
+ connect \Y $reduce_or$libresoc.v:177077$10456_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177415$10510
+ cell $reduce_or $reduce_or$libresoc.v:177079$10458
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177415$10510_Y
- end
- connect \$7 $not$libresoc.v:177400$10495_Y
- connect \$12 $reduce_or$libresoc.v:177401$10496_Y
- connect \$11 $not$libresoc.v:177402$10497_Y
- connect \$16 $reduce_or$libresoc.v:177403$10498_Y
- connect \$15 $not$libresoc.v:177404$10499_Y
- connect \$1 $not$libresoc.v:177405$10500_Y
- connect \$20 $reduce_or$libresoc.v:177406$10501_Y
- connect \$19 $not$libresoc.v:177407$10502_Y
- connect \$24 $reduce_or$libresoc.v:177408$10503_Y
- connect \$23 $not$libresoc.v:177409$10504_Y
- connect \$28 $reduce_or$libresoc.v:177410$10505_Y
- connect \$27 $not$libresoc.v:177411$10506_Y
- connect \$31 $reduce_or$libresoc.v:177412$10507_Y
- connect \$4 $reduce_or$libresoc.v:177413$10508_Y
- connect \$3 $not$libresoc.v:177414$10509_Y
- connect \$8 $reduce_or$libresoc.v:177415$10510_Y
+ connect \Y $reduce_or$libresoc.v:177079$10458_Y
+ end
+ connect \$7 $not$libresoc.v:177064$10443_Y
+ connect \$12 $reduce_or$libresoc.v:177065$10444_Y
+ connect \$11 $not$libresoc.v:177066$10445_Y
+ connect \$16 $reduce_or$libresoc.v:177067$10446_Y
+ connect \$15 $not$libresoc.v:177068$10447_Y
+ connect \$1 $not$libresoc.v:177069$10448_Y
+ connect \$20 $reduce_or$libresoc.v:177070$10449_Y
+ connect \$19 $not$libresoc.v:177071$10450_Y
+ connect \$24 $reduce_or$libresoc.v:177072$10451_Y
+ connect \$23 $not$libresoc.v:177073$10452_Y
+ connect \$28 $reduce_or$libresoc.v:177074$10453_Y
+ connect \$27 $not$libresoc.v:177075$10454_Y
+ connect \$31 $reduce_or$libresoc.v:177076$10455_Y
+ connect \$4 $reduce_or$libresoc.v:177077$10456_Y
+ connect \$3 $not$libresoc.v:177078$10457_Y
+ connect \$8 $reduce_or$libresoc.v:177079$10458_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:177431.1-177515.10"
+attribute \src "libresoc.v:177095.1-177179.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick"
attribute \generator "nMigen"
module \ppick$175
- attribute \src "libresoc.v:177488.17-177488.91"
- wire $not$libresoc.v:177488$10511_Y
- attribute \src "libresoc.v:177490.18-177490.93"
- wire $not$libresoc.v:177490$10513_Y
- attribute \src "libresoc.v:177492.18-177492.93"
- wire $not$libresoc.v:177492$10515_Y
- attribute \src "libresoc.v:177493.17-177493.138"
- wire width 8 $not$libresoc.v:177493$10516_Y
- attribute \src "libresoc.v:177495.18-177495.93"
- wire $not$libresoc.v:177495$10518_Y
- attribute \src "libresoc.v:177497.18-177497.93"
- wire $not$libresoc.v:177497$10520_Y
- attribute \src "libresoc.v:177499.18-177499.93"
- wire $not$libresoc.v:177499$10522_Y
- attribute \src "libresoc.v:177502.17-177502.91"
- wire $not$libresoc.v:177502$10525_Y
- attribute \src "libresoc.v:177489.18-177489.116"
- wire $reduce_or$libresoc.v:177489$10512_Y
- attribute \src "libresoc.v:177491.18-177491.122"
- wire $reduce_or$libresoc.v:177491$10514_Y
- attribute \src "libresoc.v:177494.18-177494.128"
- wire $reduce_or$libresoc.v:177494$10517_Y
- attribute \src "libresoc.v:177496.18-177496.134"
- wire $reduce_or$libresoc.v:177496$10519_Y
- attribute \src "libresoc.v:177498.18-177498.140"
- wire $reduce_or$libresoc.v:177498$10521_Y
- attribute \src "libresoc.v:177500.18-177500.90"
- wire $reduce_or$libresoc.v:177500$10523_Y
- attribute \src "libresoc.v:177501.17-177501.103"
- wire $reduce_or$libresoc.v:177501$10524_Y
- attribute \src "libresoc.v:177503.17-177503.109"
- wire $reduce_or$libresoc.v:177503$10526_Y
+ attribute \src "libresoc.v:177152.17-177152.91"
+ wire $not$libresoc.v:177152$10459_Y
+ attribute \src "libresoc.v:177154.18-177154.93"
+ wire $not$libresoc.v:177154$10461_Y
+ attribute \src "libresoc.v:177156.18-177156.93"
+ wire $not$libresoc.v:177156$10463_Y
+ attribute \src "libresoc.v:177157.17-177157.138"
+ wire width 8 $not$libresoc.v:177157$10464_Y
+ attribute \src "libresoc.v:177159.18-177159.93"
+ wire $not$libresoc.v:177159$10466_Y
+ attribute \src "libresoc.v:177161.18-177161.93"
+ wire $not$libresoc.v:177161$10468_Y
+ attribute \src "libresoc.v:177163.18-177163.93"
+ wire $not$libresoc.v:177163$10470_Y
+ attribute \src "libresoc.v:177166.17-177166.91"
+ wire $not$libresoc.v:177166$10473_Y
+ attribute \src "libresoc.v:177153.18-177153.116"
+ wire $reduce_or$libresoc.v:177153$10460_Y
+ attribute \src "libresoc.v:177155.18-177155.122"
+ wire $reduce_or$libresoc.v:177155$10462_Y
+ attribute \src "libresoc.v:177158.18-177158.128"
+ wire $reduce_or$libresoc.v:177158$10465_Y
+ attribute \src "libresoc.v:177160.18-177160.134"
+ wire $reduce_or$libresoc.v:177160$10467_Y
+ attribute \src "libresoc.v:177162.18-177162.140"
+ wire $reduce_or$libresoc.v:177162$10469_Y
+ attribute \src "libresoc.v:177164.18-177164.90"
+ wire $reduce_or$libresoc.v:177164$10471_Y
+ attribute \src "libresoc.v:177165.17-177165.103"
+ wire $reduce_or$libresoc.v:177165$10472_Y
+ attribute \src "libresoc.v:177167.17-177167.109"
+ wire $reduce_or$libresoc.v:177167$10474_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177488$10511
+ cell $not $not$libresoc.v:177152$10459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:177488$10511_Y
+ connect \Y $not$libresoc.v:177152$10459_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177490$10513
+ cell $not $not$libresoc.v:177154$10461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:177490$10513_Y
+ connect \Y $not$libresoc.v:177154$10461_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177492$10515
+ cell $not $not$libresoc.v:177156$10463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:177492$10515_Y
+ connect \Y $not$libresoc.v:177156$10463_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177493$10516
+ cell $not $not$libresoc.v:177157$10464
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:177493$10516_Y
+ connect \Y $not$libresoc.v:177157$10464_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177495$10518
+ cell $not $not$libresoc.v:177159$10466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:177495$10518_Y
+ connect \Y $not$libresoc.v:177159$10466_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177497$10520
+ cell $not $not$libresoc.v:177161$10468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:177497$10520_Y
+ connect \Y $not$libresoc.v:177161$10468_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177499$10522
+ cell $not $not$libresoc.v:177163$10470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:177499$10522_Y
+ connect \Y $not$libresoc.v:177163$10470_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177502$10525
+ cell $not $not$libresoc.v:177166$10473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:177502$10525_Y
+ connect \Y $not$libresoc.v:177166$10473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177489$10512
+ cell $reduce_or $reduce_or$libresoc.v:177153$10460
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:177489$10512_Y
+ connect \Y $reduce_or$libresoc.v:177153$10460_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177491$10514
+ cell $reduce_or $reduce_or$libresoc.v:177155$10462
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:177491$10514_Y
+ connect \Y $reduce_or$libresoc.v:177155$10462_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177494$10517
+ cell $reduce_or $reduce_or$libresoc.v:177158$10465
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:177494$10517_Y
+ connect \Y $reduce_or$libresoc.v:177158$10465_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177496$10519
+ cell $reduce_or $reduce_or$libresoc.v:177160$10467
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:177496$10519_Y
+ connect \Y $reduce_or$libresoc.v:177160$10467_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177498$10521
+ cell $reduce_or $reduce_or$libresoc.v:177162$10469
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:177498$10521_Y
+ connect \Y $reduce_or$libresoc.v:177162$10469_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177500$10523
+ cell $reduce_or $reduce_or$libresoc.v:177164$10471
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177500$10523_Y
+ connect \Y $reduce_or$libresoc.v:177164$10471_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177501$10524
+ cell $reduce_or $reduce_or$libresoc.v:177165$10472
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177501$10524_Y
+ connect \Y $reduce_or$libresoc.v:177165$10472_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177503$10526
+ cell $reduce_or $reduce_or$libresoc.v:177167$10474
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177503$10526_Y
- end
- connect \$7 $not$libresoc.v:177488$10511_Y
- connect \$12 $reduce_or$libresoc.v:177489$10512_Y
- connect \$11 $not$libresoc.v:177490$10513_Y
- connect \$16 $reduce_or$libresoc.v:177491$10514_Y
- connect \$15 $not$libresoc.v:177492$10515_Y
- connect \$1 $not$libresoc.v:177493$10516_Y
- connect \$20 $reduce_or$libresoc.v:177494$10517_Y
- connect \$19 $not$libresoc.v:177495$10518_Y
- connect \$24 $reduce_or$libresoc.v:177496$10519_Y
- connect \$23 $not$libresoc.v:177497$10520_Y
- connect \$28 $reduce_or$libresoc.v:177498$10521_Y
- connect \$27 $not$libresoc.v:177499$10522_Y
- connect \$31 $reduce_or$libresoc.v:177500$10523_Y
- connect \$4 $reduce_or$libresoc.v:177501$10524_Y
- connect \$3 $not$libresoc.v:177502$10525_Y
- connect \$8 $reduce_or$libresoc.v:177503$10526_Y
+ connect \Y $reduce_or$libresoc.v:177167$10474_Y
+ end
+ connect \$7 $not$libresoc.v:177152$10459_Y
+ connect \$12 $reduce_or$libresoc.v:177153$10460_Y
+ connect \$11 $not$libresoc.v:177154$10461_Y
+ connect \$16 $reduce_or$libresoc.v:177155$10462_Y
+ connect \$15 $not$libresoc.v:177156$10463_Y
+ connect \$1 $not$libresoc.v:177157$10464_Y
+ connect \$20 $reduce_or$libresoc.v:177158$10465_Y
+ connect \$19 $not$libresoc.v:177159$10466_Y
+ connect \$24 $reduce_or$libresoc.v:177160$10467_Y
+ connect \$23 $not$libresoc.v:177161$10468_Y
+ connect \$28 $reduce_or$libresoc.v:177162$10469_Y
+ connect \$27 $not$libresoc.v:177163$10470_Y
+ connect \$31 $reduce_or$libresoc.v:177164$10471_Y
+ connect \$4 $reduce_or$libresoc.v:177165$10472_Y
+ connect \$3 $not$libresoc.v:177166$10473_Y
+ connect \$8 $reduce_or$libresoc.v:177167$10474_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:177519.1-177549.10"
+attribute \src "libresoc.v:177183.1-177213.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a"
attribute \generator "nMigen"
module \rdpick_CR_cr_a
- attribute \src "libresoc.v:177540.17-177540.89"
- wire width 2 $not$libresoc.v:177540$10527_Y
- attribute \src "libresoc.v:177542.17-177542.91"
- wire $not$libresoc.v:177542$10529_Y
- attribute \src "libresoc.v:177541.17-177541.103"
- wire $reduce_or$libresoc.v:177541$10528_Y
- attribute \src "libresoc.v:177543.17-177543.89"
- wire $reduce_or$libresoc.v:177543$10530_Y
+ attribute \src "libresoc.v:177204.17-177204.89"
+ wire width 2 $not$libresoc.v:177204$10475_Y
+ attribute \src "libresoc.v:177206.17-177206.91"
+ wire $not$libresoc.v:177206$10477_Y
+ attribute \src "libresoc.v:177205.17-177205.103"
+ wire $reduce_or$libresoc.v:177205$10476_Y
+ attribute \src "libresoc.v:177207.17-177207.89"
+ wire $reduce_or$libresoc.v:177207$10478_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177540$10527
+ cell $not $not$libresoc.v:177204$10475
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:177540$10527_Y
+ connect \Y $not$libresoc.v:177204$10475_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177542$10529
+ cell $not $not$libresoc.v:177206$10477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:177542$10529_Y
+ connect \Y $not$libresoc.v:177206$10477_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177541$10528
+ cell $reduce_or $reduce_or$libresoc.v:177205$10476
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177541$10528_Y
+ connect \Y $reduce_or$libresoc.v:177205$10476_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177543$10530
+ cell $reduce_or $reduce_or$libresoc.v:177207$10478
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177543$10530_Y
+ connect \Y $reduce_or$libresoc.v:177207$10478_Y
end
- connect \$1 $not$libresoc.v:177540$10527_Y
- connect \$4 $reduce_or$libresoc.v:177541$10528_Y
- connect \$3 $not$libresoc.v:177542$10529_Y
- connect \$7 $reduce_or$libresoc.v:177543$10530_Y
+ connect \$1 $not$libresoc.v:177204$10475_Y
+ connect \$4 $reduce_or$libresoc.v:177205$10476_Y
+ connect \$3 $not$libresoc.v:177206$10477_Y
+ connect \$7 $reduce_or$libresoc.v:177207$10478_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:177553.1-177574.10"
+attribute \src "libresoc.v:177217.1-177238.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b"
attribute \generator "nMigen"
module \rdpick_CR_cr_b
- attribute \src "libresoc.v:177568.17-177568.89"
- wire $not$libresoc.v:177568$10531_Y
- attribute \src "libresoc.v:177569.17-177569.89"
- wire $reduce_or$libresoc.v:177569$10532_Y
+ attribute \src "libresoc.v:177232.17-177232.89"
+ wire $not$libresoc.v:177232$10479_Y
+ attribute \src "libresoc.v:177233.17-177233.89"
+ wire $reduce_or$libresoc.v:177233$10480_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177568$10531
+ cell $not $not$libresoc.v:177232$10479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:177568$10531_Y
+ connect \Y $not$libresoc.v:177232$10479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177569$10532
+ cell $reduce_or $reduce_or$libresoc.v:177233$10480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177569$10532_Y
+ connect \Y $reduce_or$libresoc.v:177233$10480_Y
end
- connect \$1 $not$libresoc.v:177568$10531_Y
- connect \$3 $reduce_or$libresoc.v:177569$10532_Y
+ connect \$1 $not$libresoc.v:177232$10479_Y
+ connect \$3 $reduce_or$libresoc.v:177233$10480_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:177578.1-177599.10"
+attribute \src "libresoc.v:177242.1-177263.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c"
attribute \generator "nMigen"
module \rdpick_CR_cr_c
- attribute \src "libresoc.v:177593.17-177593.89"
- wire $not$libresoc.v:177593$10533_Y
- attribute \src "libresoc.v:177594.17-177594.89"
- wire $reduce_or$libresoc.v:177594$10534_Y
+ attribute \src "libresoc.v:177257.17-177257.89"
+ wire $not$libresoc.v:177257$10481_Y
+ attribute \src "libresoc.v:177258.17-177258.89"
+ wire $reduce_or$libresoc.v:177258$10482_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177593$10533
+ cell $not $not$libresoc.v:177257$10481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:177593$10533_Y
+ connect \Y $not$libresoc.v:177257$10481_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177594$10534
+ cell $reduce_or $reduce_or$libresoc.v:177258$10482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177594$10534_Y
+ connect \Y $reduce_or$libresoc.v:177258$10482_Y
end
- connect \$1 $not$libresoc.v:177593$10533_Y
- connect \$3 $reduce_or$libresoc.v:177594$10534_Y
+ connect \$1 $not$libresoc.v:177257$10481_Y
+ connect \$3 $reduce_or$libresoc.v:177258$10482_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:177603.1-177624.10"
+attribute \src "libresoc.v:177267.1-177288.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr"
attribute \generator "nMigen"
module \rdpick_CR_full_cr
- attribute \src "libresoc.v:177618.17-177618.89"
- wire $not$libresoc.v:177618$10535_Y
- attribute \src "libresoc.v:177619.17-177619.89"
- wire $reduce_or$libresoc.v:177619$10536_Y
+ attribute \src "libresoc.v:177282.17-177282.89"
+ wire $not$libresoc.v:177282$10483_Y
+ attribute \src "libresoc.v:177283.17-177283.89"
+ wire $reduce_or$libresoc.v:177283$10484_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177618$10535
+ cell $not $not$libresoc.v:177282$10483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:177618$10535_Y
+ connect \Y $not$libresoc.v:177282$10483_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177619$10536
+ cell $reduce_or $reduce_or$libresoc.v:177283$10484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177619$10536_Y
+ connect \Y $reduce_or$libresoc.v:177283$10484_Y
end
- connect \$1 $not$libresoc.v:177618$10535_Y
- connect \$3 $reduce_or$libresoc.v:177619$10536_Y
+ connect \$1 $not$libresoc.v:177282$10483_Y
+ connect \$3 $reduce_or$libresoc.v:177283$10484_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:177628.1-177667.10"
+attribute \src "libresoc.v:177292.1-177349.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1"
attribute \generator "nMigen"
module \rdpick_FAST_fast1
- attribute \src "libresoc.v:177655.17-177655.91"
- wire $not$libresoc.v:177655$10537_Y
- attribute \src "libresoc.v:177657.17-177657.89"
- wire width 3 $not$libresoc.v:177657$10539_Y
- attribute \src "libresoc.v:177659.17-177659.91"
- wire $not$libresoc.v:177659$10541_Y
- attribute \src "libresoc.v:177656.18-177656.90"
- wire $reduce_or$libresoc.v:177656$10538_Y
- attribute \src "libresoc.v:177658.17-177658.103"
- wire $reduce_or$libresoc.v:177658$10540_Y
- attribute \src "libresoc.v:177660.17-177660.105"
- wire $reduce_or$libresoc.v:177660$10542_Y
+ attribute \src "libresoc.v:177331.17-177331.91"
+ wire $not$libresoc.v:177331$10485_Y
+ attribute \src "libresoc.v:177333.18-177333.93"
+ wire $not$libresoc.v:177333$10487_Y
+ attribute \src "libresoc.v:177335.18-177335.93"
+ wire $not$libresoc.v:177335$10489_Y
+ attribute \src "libresoc.v:177336.17-177336.89"
+ wire width 5 $not$libresoc.v:177336$10490_Y
+ attribute \src "libresoc.v:177339.17-177339.91"
+ wire $not$libresoc.v:177339$10493_Y
+ attribute \src "libresoc.v:177332.18-177332.106"
+ wire $reduce_or$libresoc.v:177332$10486_Y
+ attribute \src "libresoc.v:177334.18-177334.106"
+ wire $reduce_or$libresoc.v:177334$10488_Y
+ attribute \src "libresoc.v:177337.18-177337.90"
+ wire $reduce_or$libresoc.v:177337$10491_Y
+ attribute \src "libresoc.v:177338.17-177338.103"
+ wire $reduce_or$libresoc.v:177338$10492_Y
+ attribute \src "libresoc.v:177340.17-177340.105"
+ wire $reduce_or$libresoc.v:177340$10494_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- wire width 3 \$1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
+ wire width 5 \$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$12
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
+ wire \$19
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire output 2 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 3 input 3 \i
+ wire width 5 input 3 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54"
- wire width 3 \ni
+ wire width 5 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 3 output 1 \o
+ wire width 5 output 1 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177655$10537
+ cell $not $not$libresoc.v:177331$10485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:177655$10537_Y
+ connect \Y $not$libresoc.v:177331$10485_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177657$10539
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $not $not$libresoc.v:177333$10487
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 3
- connect \A \i
- connect \Y $not$libresoc.v:177657$10539_Y
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$12
+ connect \Y $not$libresoc.v:177333$10487_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177659$10541
+ cell $not $not$libresoc.v:177335$10489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$4
- connect \Y $not$libresoc.v:177659$10541_Y
+ connect \A \$16
+ connect \Y $not$libresoc.v:177335$10489_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177656$10538
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
+ cell $not $not$libresoc.v:177336$10490
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $reduce_or$libresoc.v:177656$10538_Y
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \i
+ connect \Y $not$libresoc.v:177336$10490_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177658$10540
+ cell $not $not$libresoc.v:177339$10493
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177658$10540_Y
+ connect \A \$4
+ connect \Y $not$libresoc.v:177339$10493_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177660$10542
+ cell $reduce_or $reduce_or$libresoc.v:177332$10486
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
+ parameter \A_WIDTH 4
parameter \Y_WIDTH 1
- connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177660$10542_Y
- end
- connect \$7 $not$libresoc.v:177655$10537_Y
- connect \$11 $reduce_or$libresoc.v:177656$10538_Y
- connect \$1 $not$libresoc.v:177657$10539_Y
- connect \$4 $reduce_or$libresoc.v:177658$10540_Y
- connect \$3 $not$libresoc.v:177659$10541_Y
- connect \$8 $reduce_or$libresoc.v:177660$10542_Y
- connect \en_o \$11
- connect \o { \t2 \t1 \t0 }
- connect \t2 \$7
- connect \t1 \$3
- connect \t0 \i [0]
- connect \ni \$1
-end
-attribute \src "libresoc.v:177671.1-177701.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2"
-attribute \generator "nMigen"
-module \rdpick_FAST_fast2
- attribute \src "libresoc.v:177692.17-177692.89"
- wire width 2 $not$libresoc.v:177692$10543_Y
- attribute \src "libresoc.v:177694.17-177694.91"
- wire $not$libresoc.v:177694$10545_Y
- attribute \src "libresoc.v:177693.17-177693.103"
- wire $reduce_or$libresoc.v:177693$10544_Y
- attribute \src "libresoc.v:177695.17-177695.89"
- wire $reduce_or$libresoc.v:177695$10546_Y
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- wire width 2 \$1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$3
+ connect \A { \i [2:0] \ni [3] }
+ connect \Y $reduce_or$libresoc.v:177332$10486_Y
+ end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- wire \$7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire output 2 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 2 input 3 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54"
- wire width 2 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 2 output 1 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t0
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177692$10543
+ cell $reduce_or $reduce_or$libresoc.v:177334$10488
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
- connect \A \i
- connect \Y $not$libresoc.v:177692$10543_Y
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A { \i [3:0] \ni [4] }
+ connect \Y $reduce_or$libresoc.v:177334$10488_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177694$10545
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
+ cell $reduce_or $reduce_or$libresoc.v:177337$10491
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \$4
- connect \Y $not$libresoc.v:177694$10545_Y
+ connect \A \o
+ connect \Y $reduce_or$libresoc.v:177337$10491_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177693$10544
+ cell $reduce_or $reduce_or$libresoc.v:177338$10492
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177693$10544_Y
+ connect \Y $reduce_or$libresoc.v:177338$10492_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177695$10546
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177340$10494
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $reduce_or$libresoc.v:177695$10546_Y
- end
- connect \$1 $not$libresoc.v:177692$10543_Y
- connect \$4 $reduce_or$libresoc.v:177693$10544_Y
- connect \$3 $not$libresoc.v:177694$10545_Y
- connect \$7 $reduce_or$libresoc.v:177695$10546_Y
- connect \en_o \$7
- connect \o { \t1 \t0 }
+ connect \A { \i [1:0] \ni [2] }
+ connect \Y $reduce_or$libresoc.v:177340$10494_Y
+ end
+ connect \$7 $not$libresoc.v:177331$10485_Y
+ connect \$12 $reduce_or$libresoc.v:177332$10486_Y
+ connect \$11 $not$libresoc.v:177333$10487_Y
+ connect \$16 $reduce_or$libresoc.v:177334$10488_Y
+ connect \$15 $not$libresoc.v:177335$10489_Y
+ connect \$1 $not$libresoc.v:177336$10490_Y
+ connect \$19 $reduce_or$libresoc.v:177337$10491_Y
+ connect \$4 $reduce_or$libresoc.v:177338$10492_Y
+ connect \$3 $not$libresoc.v:177339$10493_Y
+ connect \$8 $reduce_or$libresoc.v:177340$10494_Y
+ connect \en_o \$19
+ connect \o { \t4 \t3 \t2 \t1 \t0 }
+ connect \t4 \$15
+ connect \t3 \$11
+ connect \t2 \$7
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:177705.1-177798.10"
+attribute \src "libresoc.v:177353.1-177536.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra"
+attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rabc"
attribute \generator "nMigen"
-module \rdpick_INT_ra
- attribute \src "libresoc.v:177768.17-177768.91"
- wire $not$libresoc.v:177768$10547_Y
- attribute \src "libresoc.v:177770.18-177770.93"
- wire $not$libresoc.v:177770$10549_Y
- attribute \src "libresoc.v:177772.18-177772.93"
- wire $not$libresoc.v:177772$10551_Y
- attribute \src "libresoc.v:177773.17-177773.89"
- wire width 9 $not$libresoc.v:177773$10552_Y
- attribute \src "libresoc.v:177775.18-177775.93"
- wire $not$libresoc.v:177775$10554_Y
- attribute \src "libresoc.v:177777.18-177777.93"
- wire $not$libresoc.v:177777$10556_Y
- attribute \src "libresoc.v:177779.18-177779.93"
- wire $not$libresoc.v:177779$10558_Y
- attribute \src "libresoc.v:177781.18-177781.93"
- wire $not$libresoc.v:177781$10560_Y
- attribute \src "libresoc.v:177784.17-177784.91"
- wire $not$libresoc.v:177784$10563_Y
- attribute \src "libresoc.v:177769.18-177769.106"
- wire $reduce_or$libresoc.v:177769$10548_Y
- attribute \src "libresoc.v:177771.18-177771.106"
- wire $reduce_or$libresoc.v:177771$10550_Y
- attribute \src "libresoc.v:177774.18-177774.106"
- wire $reduce_or$libresoc.v:177774$10553_Y
- attribute \src "libresoc.v:177776.18-177776.106"
- wire $reduce_or$libresoc.v:177776$10555_Y
- attribute \src "libresoc.v:177778.18-177778.106"
- wire $reduce_or$libresoc.v:177778$10557_Y
- attribute \src "libresoc.v:177780.18-177780.106"
- wire $reduce_or$libresoc.v:177780$10559_Y
- attribute \src "libresoc.v:177782.18-177782.90"
- wire $reduce_or$libresoc.v:177782$10561_Y
- attribute \src "libresoc.v:177783.17-177783.103"
- wire $reduce_or$libresoc.v:177783$10562_Y
- attribute \src "libresoc.v:177785.17-177785.105"
- wire $reduce_or$libresoc.v:177785$10564_Y
+module \rdpick_INT_rabc
+ attribute \src "libresoc.v:177476.17-177476.91"
+ wire $not$libresoc.v:177476$10495_Y
+ attribute \src "libresoc.v:177478.18-177478.93"
+ wire $not$libresoc.v:177478$10497_Y
+ attribute \src "libresoc.v:177480.18-177480.93"
+ wire $not$libresoc.v:177480$10499_Y
+ attribute \src "libresoc.v:177481.17-177481.89"
+ wire width 19 $not$libresoc.v:177481$10500_Y
+ attribute \src "libresoc.v:177483.18-177483.93"
+ wire $not$libresoc.v:177483$10502_Y
+ attribute \src "libresoc.v:177485.18-177485.93"
+ wire $not$libresoc.v:177485$10504_Y
+ attribute \src "libresoc.v:177487.18-177487.93"
+ wire $not$libresoc.v:177487$10506_Y
+ attribute \src "libresoc.v:177489.18-177489.93"
+ wire $not$libresoc.v:177489$10508_Y
+ attribute \src "libresoc.v:177491.18-177491.93"
+ wire $not$libresoc.v:177491$10510_Y
+ attribute \src "libresoc.v:177493.18-177493.93"
+ wire $not$libresoc.v:177493$10512_Y
+ attribute \src "libresoc.v:177495.18-177495.93"
+ wire $not$libresoc.v:177495$10514_Y
+ attribute \src "libresoc.v:177498.18-177498.93"
+ wire $not$libresoc.v:177498$10517_Y
+ attribute \src "libresoc.v:177500.18-177500.93"
+ wire $not$libresoc.v:177500$10519_Y
+ attribute \src "libresoc.v:177502.18-177502.93"
+ wire $not$libresoc.v:177502$10521_Y
+ attribute \src "libresoc.v:177503.17-177503.91"
+ wire $not$libresoc.v:177503$10522_Y
+ attribute \src "libresoc.v:177505.18-177505.93"
+ wire $not$libresoc.v:177505$10524_Y
+ attribute \src "libresoc.v:177507.18-177507.93"
+ wire $not$libresoc.v:177507$10526_Y
+ attribute \src "libresoc.v:177509.18-177509.93"
+ wire $not$libresoc.v:177509$10528_Y
+ attribute \src "libresoc.v:177511.18-177511.93"
+ wire $not$libresoc.v:177511$10530_Y
+ attribute \src "libresoc.v:177477.18-177477.106"
+ wire $reduce_or$libresoc.v:177477$10496_Y
+ attribute \src "libresoc.v:177479.18-177479.106"
+ wire $reduce_or$libresoc.v:177479$10498_Y
+ attribute \src "libresoc.v:177482.18-177482.106"
+ wire $reduce_or$libresoc.v:177482$10501_Y
+ attribute \src "libresoc.v:177484.18-177484.106"
+ wire $reduce_or$libresoc.v:177484$10503_Y
+ attribute \src "libresoc.v:177486.18-177486.106"
+ wire $reduce_or$libresoc.v:177486$10505_Y
+ attribute \src "libresoc.v:177488.18-177488.106"
+ wire $reduce_or$libresoc.v:177488$10507_Y
+ attribute \src "libresoc.v:177490.18-177490.106"
+ wire $reduce_or$libresoc.v:177490$10509_Y
+ attribute \src "libresoc.v:177492.18-177492.107"
+ wire $reduce_or$libresoc.v:177492$10511_Y
+ attribute \src "libresoc.v:177494.18-177494.108"
+ wire $reduce_or$libresoc.v:177494$10513_Y
+ attribute \src "libresoc.v:177496.18-177496.108"
+ wire $reduce_or$libresoc.v:177496$10515_Y
+ attribute \src "libresoc.v:177497.17-177497.103"
+ wire $reduce_or$libresoc.v:177497$10516_Y
+ attribute \src "libresoc.v:177499.18-177499.108"
+ wire $reduce_or$libresoc.v:177499$10518_Y
+ attribute \src "libresoc.v:177501.18-177501.108"
+ wire $reduce_or$libresoc.v:177501$10520_Y
+ attribute \src "libresoc.v:177504.18-177504.108"
+ wire $reduce_or$libresoc.v:177504$10523_Y
+ attribute \src "libresoc.v:177506.18-177506.108"
+ wire $reduce_or$libresoc.v:177506$10525_Y
+ attribute \src "libresoc.v:177508.18-177508.108"
+ wire $reduce_or$libresoc.v:177508$10527_Y
+ attribute \src "libresoc.v:177510.18-177510.108"
+ wire $reduce_or$libresoc.v:177510$10529_Y
+ attribute \src "libresoc.v:177512.18-177512.90"
+ wire $reduce_or$libresoc.v:177512$10531_Y
+ attribute \src "libresoc.v:177513.17-177513.105"
+ wire $reduce_or$libresoc.v:177513$10532_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- wire width 9 \$1
+ wire width 19 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$31
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$35
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$36
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$39
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$40
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$43
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$44
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$47
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$48
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$51
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$52
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$55
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$56
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$59
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$60
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$63
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$64
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$67
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$68
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$71
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ wire \$72
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
+ wire \$75
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
wire \$8
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire output 2 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 9 input 3 \i
+ wire width 19 input 3 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54"
- wire width 9 \ni
+ wire width 19 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 9 output 1 \o
+ wire width 19 output 1 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t10
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t12
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t14
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t17
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t18
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
+ wire \t9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177768$10547
+ cell $not $not$libresoc.v:177476$10495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:177768$10547_Y
+ connect \Y $not$libresoc.v:177476$10495_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177770$10549
+ cell $not $not$libresoc.v:177478$10497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:177770$10549_Y
+ connect \Y $not$libresoc.v:177478$10497_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177772$10551
+ cell $not $not$libresoc.v:177480$10499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:177772$10551_Y
+ connect \Y $not$libresoc.v:177480$10499_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177773$10552
+ cell $not $not$libresoc.v:177481$10500
parameter \A_SIGNED 0
- parameter \A_WIDTH 9
- parameter \Y_WIDTH 9
+ parameter \A_WIDTH 19
+ parameter \Y_WIDTH 19
connect \A \i
- connect \Y $not$libresoc.v:177773$10552_Y
+ connect \Y $not$libresoc.v:177481$10500_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177775$10554
+ cell $not $not$libresoc.v:177483$10502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:177775$10554_Y
+ connect \Y $not$libresoc.v:177483$10502_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177777$10556
+ cell $not $not$libresoc.v:177485$10504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:177777$10556_Y
+ connect \Y $not$libresoc.v:177485$10504_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177779$10558
+ cell $not $not$libresoc.v:177487$10506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:177779$10558_Y
+ connect \Y $not$libresoc.v:177487$10506_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177781$10560
+ cell $not $not$libresoc.v:177489$10508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$32
- connect \Y $not$libresoc.v:177781$10560_Y
+ connect \Y $not$libresoc.v:177489$10508_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177784$10563
+ cell $not $not$libresoc.v:177491$10510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$4
- connect \Y $not$libresoc.v:177784$10563_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177769$10548
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 1
- connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:177769$10548_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177771$10550
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 1
- connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:177771$10550_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177774$10553
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 1
- connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:177774$10553_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177776$10555
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:177776$10555_Y
+ connect \A \$36
+ connect \Y $not$libresoc.v:177491$10510_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177778$10557
+ cell $not $not$libresoc.v:177493$10512
parameter \A_SIGNED 0
- parameter \A_WIDTH 8
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:177778$10557_Y
+ connect \A \$40
+ connect \Y $not$libresoc.v:177493$10512_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177780$10559
- parameter \A_SIGNED 0
- parameter \A_WIDTH 9
- parameter \Y_WIDTH 1
- connect \A { \i [7:0] \ni [8] }
- connect \Y $reduce_or$libresoc.v:177780$10559_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177782$10561
+ cell $not $not$libresoc.v:177495$10514
parameter \A_SIGNED 0
- parameter \A_WIDTH 9
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $reduce_or$libresoc.v:177782$10561_Y
+ connect \A \$44
+ connect \Y $not$libresoc.v:177495$10514_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177783$10562
+ cell $not $not$libresoc.v:177498$10517
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177783$10562_Y
+ connect \A \$48
+ connect \Y $not$libresoc.v:177498$10517_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177785$10564
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 1
- connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177785$10564_Y
- end
- connect \$7 $not$libresoc.v:177768$10547_Y
- connect \$12 $reduce_or$libresoc.v:177769$10548_Y
- connect \$11 $not$libresoc.v:177770$10549_Y
- connect \$16 $reduce_or$libresoc.v:177771$10550_Y
- connect \$15 $not$libresoc.v:177772$10551_Y
- connect \$1 $not$libresoc.v:177773$10552_Y
- connect \$20 $reduce_or$libresoc.v:177774$10553_Y
- connect \$19 $not$libresoc.v:177775$10554_Y
- connect \$24 $reduce_or$libresoc.v:177776$10555_Y
- connect \$23 $not$libresoc.v:177777$10556_Y
- connect \$28 $reduce_or$libresoc.v:177778$10557_Y
- connect \$27 $not$libresoc.v:177779$10558_Y
- connect \$32 $reduce_or$libresoc.v:177780$10559_Y
- connect \$31 $not$libresoc.v:177781$10560_Y
- connect \$35 $reduce_or$libresoc.v:177782$10561_Y
- connect \$4 $reduce_or$libresoc.v:177783$10562_Y
- connect \$3 $not$libresoc.v:177784$10563_Y
- connect \$8 $reduce_or$libresoc.v:177785$10564_Y
- connect \en_o \$35
- connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
- connect \t8 \$31
- connect \t7 \$27
- connect \t6 \$23
- connect \t5 \$19
- connect \t4 \$15
- connect \t3 \$11
- connect \t2 \$7
- connect \t1 \$3
- connect \t0 \i [0]
- connect \ni \$1
-end
-attribute \src "libresoc.v:177802.1-177886.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb"
-attribute \generator "nMigen"
-module \rdpick_INT_rb
- attribute \src "libresoc.v:177859.17-177859.91"
- wire $not$libresoc.v:177859$10565_Y
- attribute \src "libresoc.v:177861.18-177861.93"
- wire $not$libresoc.v:177861$10567_Y
- attribute \src "libresoc.v:177863.18-177863.93"
- wire $not$libresoc.v:177863$10569_Y
- attribute \src "libresoc.v:177864.17-177864.89"
- wire width 8 $not$libresoc.v:177864$10570_Y
- attribute \src "libresoc.v:177866.18-177866.93"
- wire $not$libresoc.v:177866$10572_Y
- attribute \src "libresoc.v:177868.18-177868.93"
- wire $not$libresoc.v:177868$10574_Y
- attribute \src "libresoc.v:177870.18-177870.93"
- wire $not$libresoc.v:177870$10576_Y
- attribute \src "libresoc.v:177873.17-177873.91"
- wire $not$libresoc.v:177873$10579_Y
- attribute \src "libresoc.v:177860.18-177860.106"
- wire $reduce_or$libresoc.v:177860$10566_Y
- attribute \src "libresoc.v:177862.18-177862.106"
- wire $reduce_or$libresoc.v:177862$10568_Y
- attribute \src "libresoc.v:177865.18-177865.106"
- wire $reduce_or$libresoc.v:177865$10571_Y
- attribute \src "libresoc.v:177867.18-177867.106"
- wire $reduce_or$libresoc.v:177867$10573_Y
- attribute \src "libresoc.v:177869.18-177869.106"
- wire $reduce_or$libresoc.v:177869$10575_Y
- attribute \src "libresoc.v:177871.18-177871.90"
- wire $reduce_or$libresoc.v:177871$10577_Y
- attribute \src "libresoc.v:177872.17-177872.103"
- wire $reduce_or$libresoc.v:177872$10578_Y
- attribute \src "libresoc.v:177874.17-177874.105"
- wire $reduce_or$libresoc.v:177874$10580_Y
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- wire width 8 \$1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$12
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$16
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$19
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$20
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$23
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$24
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$27
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$28
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- wire \$31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire output 2 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 8 input 3 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54"
- wire width 8 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 8 output 1 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t0
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t6
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177859$10565
+ cell $not $not$libresoc.v:177500$10519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$8
- connect \Y $not$libresoc.v:177859$10565_Y
+ connect \A \$52
+ connect \Y $not$libresoc.v:177500$10519_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177861$10567
+ cell $not $not$libresoc.v:177502$10521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$12
- connect \Y $not$libresoc.v:177861$10567_Y
+ connect \A \$56
+ connect \Y $not$libresoc.v:177502$10521_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177863$10569
+ cell $not $not$libresoc.v:177503$10522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$16
- connect \Y $not$libresoc.v:177863$10569_Y
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177864$10570
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \Y_WIDTH 8
- connect \A \i
- connect \Y $not$libresoc.v:177864$10570_Y
+ connect \A \$4
+ connect \Y $not$libresoc.v:177503$10522_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177866$10572
+ cell $not $not$libresoc.v:177505$10524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$20
- connect \Y $not$libresoc.v:177866$10572_Y
+ connect \A \$60
+ connect \Y $not$libresoc.v:177505$10524_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177868$10574
+ cell $not $not$libresoc.v:177507$10526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$24
- connect \Y $not$libresoc.v:177868$10574_Y
+ connect \A \$64
+ connect \Y $not$libresoc.v:177507$10526_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177870$10576
+ cell $not $not$libresoc.v:177509$10528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$28
- connect \Y $not$libresoc.v:177870$10576_Y
+ connect \A \$68
+ connect \Y $not$libresoc.v:177509$10528_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177873$10579
+ cell $not $not$libresoc.v:177511$10530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$4
- connect \Y $not$libresoc.v:177873$10579_Y
+ connect \A \$72
+ connect \Y $not$libresoc.v:177511$10530_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177860$10566
+ cell $reduce_or $reduce_or$libresoc.v:177477$10496
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:177860$10566_Y
+ connect \Y $reduce_or$libresoc.v:177477$10496_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177862$10568
+ cell $reduce_or $reduce_or$libresoc.v:177479$10498
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:177862$10568_Y
+ connect \Y $reduce_or$libresoc.v:177479$10498_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177865$10571
+ cell $reduce_or $reduce_or$libresoc.v:177482$10501
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:177865$10571_Y
+ connect \Y $reduce_or$libresoc.v:177482$10501_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177867$10573
+ cell $reduce_or $reduce_or$libresoc.v:177484$10503
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:177867$10573_Y
+ connect \Y $reduce_or$libresoc.v:177484$10503_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177869$10575
+ cell $reduce_or $reduce_or$libresoc.v:177486$10505
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:177869$10575_Y
+ connect \Y $reduce_or$libresoc.v:177486$10505_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177871$10577
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177488$10507
parameter \A_SIGNED 0
- parameter \A_WIDTH 8
+ parameter \A_WIDTH 9
parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $reduce_or$libresoc.v:177871$10577_Y
+ connect \A { \i [7:0] \ni [8] }
+ connect \Y $reduce_or$libresoc.v:177488$10507_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177490$10509
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 10
+ parameter \Y_WIDTH 1
+ connect \A { \i [8:0] \ni [9] }
+ connect \Y $reduce_or$libresoc.v:177490$10509_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177492$10511
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A { \i [9:0] \ni [10] }
+ connect \Y $reduce_or$libresoc.v:177492$10511_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177494$10513
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 12
+ parameter \Y_WIDTH 1
+ connect \A { \i [10:0] \ni [11] }
+ connect \Y $reduce_or$libresoc.v:177494$10513_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177872$10578
+ cell $reduce_or $reduce_or$libresoc.v:177496$10515
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 13
+ parameter \Y_WIDTH 1
+ connect \A { \i [11:0] \ni [12] }
+ connect \Y $reduce_or$libresoc.v:177496$10515_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177497$10516
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177872$10578_Y
+ connect \Y $reduce_or$libresoc.v:177497$10516_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177874$10580
+ cell $reduce_or $reduce_or$libresoc.v:177499$10518
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
+ parameter \A_WIDTH 14
parameter \Y_WIDTH 1
- connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177874$10580_Y
- end
- connect \$7 $not$libresoc.v:177859$10565_Y
- connect \$12 $reduce_or$libresoc.v:177860$10566_Y
- connect \$11 $not$libresoc.v:177861$10567_Y
- connect \$16 $reduce_or$libresoc.v:177862$10568_Y
- connect \$15 $not$libresoc.v:177863$10569_Y
- connect \$1 $not$libresoc.v:177864$10570_Y
- connect \$20 $reduce_or$libresoc.v:177865$10571_Y
- connect \$19 $not$libresoc.v:177866$10572_Y
- connect \$24 $reduce_or$libresoc.v:177867$10573_Y
- connect \$23 $not$libresoc.v:177868$10574_Y
- connect \$28 $reduce_or$libresoc.v:177869$10575_Y
- connect \$27 $not$libresoc.v:177870$10576_Y
- connect \$31 $reduce_or$libresoc.v:177871$10577_Y
- connect \$4 $reduce_or$libresoc.v:177872$10578_Y
- connect \$3 $not$libresoc.v:177873$10579_Y
- connect \$8 $reduce_or$libresoc.v:177874$10580_Y
- connect \en_o \$31
- connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
- connect \t7 \$27
- connect \t6 \$23
- connect \t5 \$19
- connect \t4 \$15
- connect \t3 \$11
- connect \t2 \$7
- connect \t1 \$3
- connect \t0 \i [0]
- connect \ni \$1
-end
-attribute \src "libresoc.v:177890.1-177920.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc"
-attribute \generator "nMigen"
-module \rdpick_INT_rc
- attribute \src "libresoc.v:177911.17-177911.89"
- wire width 2 $not$libresoc.v:177911$10581_Y
- attribute \src "libresoc.v:177913.17-177913.91"
- wire $not$libresoc.v:177913$10583_Y
- attribute \src "libresoc.v:177912.17-177912.103"
- wire $reduce_or$libresoc.v:177912$10582_Y
- attribute \src "libresoc.v:177914.17-177914.89"
- wire $reduce_or$libresoc.v:177914$10584_Y
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- wire width 2 \$1
+ connect \A { \i [12:0] \ni [13] }
+ connect \Y $reduce_or$libresoc.v:177499$10518_Y
+ end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$3
+ cell $reduce_or $reduce_or$libresoc.v:177501$10520
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 15
+ parameter \Y_WIDTH 1
+ connect \A { \i [13:0] \ni [14] }
+ connect \Y $reduce_or$libresoc.v:177501$10520_Y
+ end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- wire \$4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- wire \$7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
- wire output 2 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 2 input 3 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54"
- wire width 2 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
- wire width 2 output 1 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t0
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- wire \t1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177911$10581
+ cell $reduce_or $reduce_or$libresoc.v:177504$10523
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
- connect \A \i
- connect \Y $not$libresoc.v:177911$10581_Y
+ parameter \A_WIDTH 16
+ parameter \Y_WIDTH 1
+ connect \A { \i [14:0] \ni [15] }
+ connect \Y $reduce_or$libresoc.v:177504$10523_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177913$10583
+ cell $reduce_or $reduce_or$libresoc.v:177506$10525
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 17
parameter \Y_WIDTH 1
- connect \A \$4
- connect \Y $not$libresoc.v:177913$10583_Y
+ connect \A { \i [15:0] \ni [16] }
+ connect \Y $reduce_or$libresoc.v:177506$10525_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177912$10582
+ cell $reduce_or $reduce_or$libresoc.v:177508$10527
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 18
parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177912$10582_Y
+ connect \A { \i [16:0] \ni [17] }
+ connect \Y $reduce_or$libresoc.v:177508$10527_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177510$10529
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 19
+ parameter \Y_WIDTH 1
+ connect \A { \i [17:0] \ni [18] }
+ connect \Y $reduce_or$libresoc.v:177510$10529_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177914$10584
+ cell $reduce_or $reduce_or$libresoc.v:177512$10531
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 19
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177914$10584_Y
+ connect \Y $reduce_or$libresoc.v:177512$10531_Y
end
- connect \$1 $not$libresoc.v:177911$10581_Y
- connect \$4 $reduce_or$libresoc.v:177912$10582_Y
- connect \$3 $not$libresoc.v:177913$10583_Y
- connect \$7 $reduce_or$libresoc.v:177914$10584_Y
- connect \en_o \$7
- connect \o { \t1 \t0 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
+ cell $reduce_or $reduce_or$libresoc.v:177513$10532
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] \ni [2] }
+ connect \Y $reduce_or$libresoc.v:177513$10532_Y
+ end
+ connect \$7 $not$libresoc.v:177476$10495_Y
+ connect \$12 $reduce_or$libresoc.v:177477$10496_Y
+ connect \$11 $not$libresoc.v:177478$10497_Y
+ connect \$16 $reduce_or$libresoc.v:177479$10498_Y
+ connect \$15 $not$libresoc.v:177480$10499_Y
+ connect \$1 $not$libresoc.v:177481$10500_Y
+ connect \$20 $reduce_or$libresoc.v:177482$10501_Y
+ connect \$19 $not$libresoc.v:177483$10502_Y
+ connect \$24 $reduce_or$libresoc.v:177484$10503_Y
+ connect \$23 $not$libresoc.v:177485$10504_Y
+ connect \$28 $reduce_or$libresoc.v:177486$10505_Y
+ connect \$27 $not$libresoc.v:177487$10506_Y
+ connect \$32 $reduce_or$libresoc.v:177488$10507_Y
+ connect \$31 $not$libresoc.v:177489$10508_Y
+ connect \$36 $reduce_or$libresoc.v:177490$10509_Y
+ connect \$35 $not$libresoc.v:177491$10510_Y
+ connect \$40 $reduce_or$libresoc.v:177492$10511_Y
+ connect \$39 $not$libresoc.v:177493$10512_Y
+ connect \$44 $reduce_or$libresoc.v:177494$10513_Y
+ connect \$43 $not$libresoc.v:177495$10514_Y
+ connect \$48 $reduce_or$libresoc.v:177496$10515_Y
+ connect \$4 $reduce_or$libresoc.v:177497$10516_Y
+ connect \$47 $not$libresoc.v:177498$10517_Y
+ connect \$52 $reduce_or$libresoc.v:177499$10518_Y
+ connect \$51 $not$libresoc.v:177500$10519_Y
+ connect \$56 $reduce_or$libresoc.v:177501$10520_Y
+ connect \$55 $not$libresoc.v:177502$10521_Y
+ connect \$3 $not$libresoc.v:177503$10522_Y
+ connect \$60 $reduce_or$libresoc.v:177504$10523_Y
+ connect \$59 $not$libresoc.v:177505$10524_Y
+ connect \$64 $reduce_or$libresoc.v:177506$10525_Y
+ connect \$63 $not$libresoc.v:177507$10526_Y
+ connect \$68 $reduce_or$libresoc.v:177508$10527_Y
+ connect \$67 $not$libresoc.v:177509$10528_Y
+ connect \$72 $reduce_or$libresoc.v:177510$10529_Y
+ connect \$71 $not$libresoc.v:177511$10530_Y
+ connect \$75 $reduce_or$libresoc.v:177512$10531_Y
+ connect \$8 $reduce_or$libresoc.v:177513$10532_Y
+ connect \en_o \$75
+ connect \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+ connect \t18 \$71
+ connect \t17 \$67
+ connect \t16 \$63
+ connect \t15 \$59
+ connect \t14 \$55
+ connect \t13 \$51
+ connect \t12 \$47
+ connect \t11 \$43
+ connect \t10 \$39
+ connect \t9 \$35
+ connect \t8 \$31
+ connect \t7 \$27
+ connect \t6 \$23
+ connect \t5 \$19
+ connect \t4 \$15
+ connect \t3 \$11
+ connect \t2 \$7
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:177924.1-177945.10"
+attribute \src "libresoc.v:177540.1-177561.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1"
attribute \generator "nMigen"
module \rdpick_SPR_spr1
- attribute \src "libresoc.v:177939.17-177939.89"
- wire $not$libresoc.v:177939$10585_Y
- attribute \src "libresoc.v:177940.17-177940.89"
- wire $reduce_or$libresoc.v:177940$10586_Y
+ attribute \src "libresoc.v:177555.17-177555.89"
+ wire $not$libresoc.v:177555$10533_Y
+ attribute \src "libresoc.v:177556.17-177556.89"
+ wire $reduce_or$libresoc.v:177556$10534_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177939$10585
+ cell $not $not$libresoc.v:177555$10533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:177939$10585_Y
+ connect \Y $not$libresoc.v:177555$10533_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177940$10586
+ cell $reduce_or $reduce_or$libresoc.v:177556$10534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177940$10586_Y
+ connect \Y $reduce_or$libresoc.v:177556$10534_Y
end
- connect \$1 $not$libresoc.v:177939$10585_Y
- connect \$3 $reduce_or$libresoc.v:177940$10586_Y
+ connect \$1 $not$libresoc.v:177555$10533_Y
+ connect \$3 $reduce_or$libresoc.v:177556$10534_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:177949.1-177988.10"
+attribute \src "libresoc.v:177565.1-177604.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca"
attribute \generator "nMigen"
module \rdpick_XER_xer_ca
- attribute \src "libresoc.v:177976.17-177976.91"
- wire $not$libresoc.v:177976$10587_Y
- attribute \src "libresoc.v:177978.17-177978.89"
- wire width 3 $not$libresoc.v:177978$10589_Y
- attribute \src "libresoc.v:177980.17-177980.91"
- wire $not$libresoc.v:177980$10591_Y
- attribute \src "libresoc.v:177977.18-177977.90"
- wire $reduce_or$libresoc.v:177977$10588_Y
- attribute \src "libresoc.v:177979.17-177979.103"
- wire $reduce_or$libresoc.v:177979$10590_Y
- attribute \src "libresoc.v:177981.17-177981.105"
- wire $reduce_or$libresoc.v:177981$10592_Y
+ attribute \src "libresoc.v:177592.17-177592.91"
+ wire $not$libresoc.v:177592$10535_Y
+ attribute \src "libresoc.v:177594.17-177594.89"
+ wire width 3 $not$libresoc.v:177594$10537_Y
+ attribute \src "libresoc.v:177596.17-177596.91"
+ wire $not$libresoc.v:177596$10539_Y
+ attribute \src "libresoc.v:177593.18-177593.90"
+ wire $reduce_or$libresoc.v:177593$10536_Y
+ attribute \src "libresoc.v:177595.17-177595.103"
+ wire $reduce_or$libresoc.v:177595$10538_Y
+ attribute \src "libresoc.v:177597.17-177597.105"
+ wire $reduce_or$libresoc.v:177597$10540_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177976$10587
+ cell $not $not$libresoc.v:177592$10535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:177976$10587_Y
+ connect \Y $not$libresoc.v:177592$10535_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:177978$10589
+ cell $not $not$libresoc.v:177594$10537
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:177978$10589_Y
+ connect \Y $not$libresoc.v:177594$10537_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:177980$10591
+ cell $not $not$libresoc.v:177596$10539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:177980$10591_Y
+ connect \Y $not$libresoc.v:177596$10539_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:177977$10588
+ cell $reduce_or $reduce_or$libresoc.v:177593$10536
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:177977$10588_Y
+ connect \Y $reduce_or$libresoc.v:177593$10536_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177979$10590
+ cell $reduce_or $reduce_or$libresoc.v:177595$10538
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:177979$10590_Y
+ connect \Y $reduce_or$libresoc.v:177595$10538_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:177981$10592
+ cell $reduce_or $reduce_or$libresoc.v:177597$10540
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:177981$10592_Y
- end
- connect \$7 $not$libresoc.v:177976$10587_Y
- connect \$11 $reduce_or$libresoc.v:177977$10588_Y
- connect \$1 $not$libresoc.v:177978$10589_Y
- connect \$4 $reduce_or$libresoc.v:177979$10590_Y
- connect \$3 $not$libresoc.v:177980$10591_Y
- connect \$8 $reduce_or$libresoc.v:177981$10592_Y
+ connect \Y $reduce_or$libresoc.v:177597$10540_Y
+ end
+ connect \$7 $not$libresoc.v:177592$10535_Y
+ connect \$11 $reduce_or$libresoc.v:177593$10536_Y
+ connect \$1 $not$libresoc.v:177594$10537_Y
+ connect \$4 $reduce_or$libresoc.v:177595$10538_Y
+ connect \$3 $not$libresoc.v:177596$10539_Y
+ connect \$8 $reduce_or$libresoc.v:177597$10540_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:177992.1-178013.10"
+attribute \src "libresoc.v:177608.1-177629.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov"
attribute \generator "nMigen"
module \rdpick_XER_xer_ov
- attribute \src "libresoc.v:178007.17-178007.89"
- wire $not$libresoc.v:178007$10593_Y
- attribute \src "libresoc.v:178008.17-178008.89"
- wire $reduce_or$libresoc.v:178008$10594_Y
+ attribute \src "libresoc.v:177623.17-177623.89"
+ wire $not$libresoc.v:177623$10541_Y
+ attribute \src "libresoc.v:177624.17-177624.89"
+ wire $reduce_or$libresoc.v:177624$10542_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:178007$10593
+ cell $not $not$libresoc.v:177623$10541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:178007$10593_Y
+ connect \Y $not$libresoc.v:177623$10541_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:178008$10594
+ cell $reduce_or $reduce_or$libresoc.v:177624$10542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:178008$10594_Y
+ connect \Y $reduce_or$libresoc.v:177624$10542_Y
end
- connect \$1 $not$libresoc.v:178007$10593_Y
- connect \$3 $reduce_or$libresoc.v:178008$10594_Y
+ connect \$1 $not$libresoc.v:177623$10541_Y
+ connect \$3 $reduce_or$libresoc.v:177624$10542_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:178017.1-178083.10"
+attribute \src "libresoc.v:177633.1-177699.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so"
attribute \generator "nMigen"
module \rdpick_XER_xer_so
- attribute \src "libresoc.v:178062.17-178062.91"
- wire $not$libresoc.v:178062$10595_Y
- attribute \src "libresoc.v:178064.18-178064.93"
- wire $not$libresoc.v:178064$10597_Y
- attribute \src "libresoc.v:178066.18-178066.93"
- wire $not$libresoc.v:178066$10599_Y
- attribute \src "libresoc.v:178067.17-178067.89"
- wire width 6 $not$libresoc.v:178067$10600_Y
- attribute \src "libresoc.v:178069.18-178069.93"
- wire $not$libresoc.v:178069$10602_Y
- attribute \src "libresoc.v:178072.17-178072.91"
- wire $not$libresoc.v:178072$10605_Y
- attribute \src "libresoc.v:178063.18-178063.106"
- wire $reduce_or$libresoc.v:178063$10596_Y
- attribute \src "libresoc.v:178065.18-178065.106"
- wire $reduce_or$libresoc.v:178065$10598_Y
- attribute \src "libresoc.v:178068.18-178068.106"
- wire $reduce_or$libresoc.v:178068$10601_Y
- attribute \src "libresoc.v:178070.18-178070.90"
- wire $reduce_or$libresoc.v:178070$10603_Y
- attribute \src "libresoc.v:178071.17-178071.103"
- wire $reduce_or$libresoc.v:178071$10604_Y
- attribute \src "libresoc.v:178073.17-178073.105"
- wire $reduce_or$libresoc.v:178073$10606_Y
+ attribute \src "libresoc.v:177678.17-177678.91"
+ wire $not$libresoc.v:177678$10543_Y
+ attribute \src "libresoc.v:177680.18-177680.93"
+ wire $not$libresoc.v:177680$10545_Y
+ attribute \src "libresoc.v:177682.18-177682.93"
+ wire $not$libresoc.v:177682$10547_Y
+ attribute \src "libresoc.v:177683.17-177683.89"
+ wire width 6 $not$libresoc.v:177683$10548_Y
+ attribute \src "libresoc.v:177685.18-177685.93"
+ wire $not$libresoc.v:177685$10550_Y
+ attribute \src "libresoc.v:177688.17-177688.91"
+ wire $not$libresoc.v:177688$10553_Y
+ attribute \src "libresoc.v:177679.18-177679.106"
+ wire $reduce_or$libresoc.v:177679$10544_Y
+ attribute \src "libresoc.v:177681.18-177681.106"
+ wire $reduce_or$libresoc.v:177681$10546_Y
+ attribute \src "libresoc.v:177684.18-177684.106"
+ wire $reduce_or$libresoc.v:177684$10549_Y
+ attribute \src "libresoc.v:177686.18-177686.90"
+ wire $reduce_or$libresoc.v:177686$10551_Y
+ attribute \src "libresoc.v:177687.17-177687.103"
+ wire $reduce_or$libresoc.v:177687$10552_Y
+ attribute \src "libresoc.v:177689.17-177689.105"
+ wire $reduce_or$libresoc.v:177689$10554_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:178062$10595
+ cell $not $not$libresoc.v:177678$10543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:178062$10595_Y
+ connect \Y $not$libresoc.v:177678$10543_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:178064$10597
+ cell $not $not$libresoc.v:177680$10545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:178064$10597_Y
+ connect \Y $not$libresoc.v:177680$10545_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:178066$10599
+ cell $not $not$libresoc.v:177682$10547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:178066$10599_Y
+ connect \Y $not$libresoc.v:177682$10547_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:178067$10600
+ cell $not $not$libresoc.v:177683$10548
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \i
- connect \Y $not$libresoc.v:178067$10600_Y
+ connect \Y $not$libresoc.v:177683$10548_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:178069$10602
+ cell $not $not$libresoc.v:177685$10550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:178069$10602_Y
+ connect \Y $not$libresoc.v:177685$10550_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:178072$10605
+ cell $not $not$libresoc.v:177688$10553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:178072$10605_Y
+ connect \Y $not$libresoc.v:177688$10553_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:178063$10596
+ cell $reduce_or $reduce_or$libresoc.v:177679$10544
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:178063$10596_Y
+ connect \Y $reduce_or$libresoc.v:177679$10544_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:178065$10598
+ cell $reduce_or $reduce_or$libresoc.v:177681$10546
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:178065$10598_Y
+ connect \Y $reduce_or$libresoc.v:177681$10546_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:178068$10601
+ cell $reduce_or $reduce_or$libresoc.v:177684$10549
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:178068$10601_Y
+ connect \Y $reduce_or$libresoc.v:177684$10549_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:178070$10603
+ cell $reduce_or $reduce_or$libresoc.v:177686$10551
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:178070$10603_Y
+ connect \Y $reduce_or$libresoc.v:177686$10551_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:178071$10604
+ cell $reduce_or $reduce_or$libresoc.v:177687$10552
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:178071$10604_Y
+ connect \Y $reduce_or$libresoc.v:177687$10552_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:178073$10606
+ cell $reduce_or $reduce_or$libresoc.v:177689$10554
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:178073$10606_Y
- end
- connect \$7 $not$libresoc.v:178062$10595_Y
- connect \$12 $reduce_or$libresoc.v:178063$10596_Y
- connect \$11 $not$libresoc.v:178064$10597_Y
- connect \$16 $reduce_or$libresoc.v:178065$10598_Y
- connect \$15 $not$libresoc.v:178066$10599_Y
- connect \$1 $not$libresoc.v:178067$10600_Y
- connect \$20 $reduce_or$libresoc.v:178068$10601_Y
- connect \$19 $not$libresoc.v:178069$10602_Y
- connect \$23 $reduce_or$libresoc.v:178070$10603_Y
- connect \$4 $reduce_or$libresoc.v:178071$10604_Y
- connect \$3 $not$libresoc.v:178072$10605_Y
- connect \$8 $reduce_or$libresoc.v:178073$10606_Y
+ connect \Y $reduce_or$libresoc.v:177689$10554_Y
+ end
+ connect \$7 $not$libresoc.v:177678$10543_Y
+ connect \$12 $reduce_or$libresoc.v:177679$10544_Y
+ connect \$11 $not$libresoc.v:177680$10545_Y
+ connect \$16 $reduce_or$libresoc.v:177681$10546_Y
+ connect \$15 $not$libresoc.v:177682$10547_Y
+ connect \$1 $not$libresoc.v:177683$10548_Y
+ connect \$20 $reduce_or$libresoc.v:177684$10549_Y
+ connect \$19 $not$libresoc.v:177685$10550_Y
+ connect \$23 $reduce_or$libresoc.v:177686$10551_Y
+ connect \$4 $reduce_or$libresoc.v:177687$10552_Y
+ connect \$3 $not$libresoc.v:177688$10553_Y
+ connect \$8 $reduce_or$libresoc.v:177689$10554_Y
connect \en_o \$23
connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t5 \$19
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:178087.1-178642.10"
+attribute \src "libresoc.v:177703.1-178174.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0"
attribute \generator "nMigen"
module \reg_0
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $0\cr_pred0__data_o$next[3:0]$10621
- attribute \src "libresoc.v:178193.3-178194.49"
- wire width 4 $0\cr_pred0__data_o[3:0]
- attribute \src "libresoc.v:178088.7-178088.20"
+ attribute \src "libresoc.v:177704.7-177704.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $0\r0__data_o$next[3:0]$10692
- attribute \src "libresoc.v:178185.3-178186.37"
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $0\r0__data_o$next[3:0]$10610
+ attribute \src "libresoc.v:177789.3-177790.37"
wire width 4 $0\r0__data_o[3:0]
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $0\r20__data_o$next[3:0]$10630
- attribute \src "libresoc.v:178183.3-178184.39"
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $0\r20__data_o$next[3:0]$10624
+ attribute \src "libresoc.v:177787.3-177788.39"
wire width 4 $0\r20__data_o[3:0]
- attribute \src "libresoc.v:178335.3-178361.6"
- wire width 4 $0\reg$next[3:0]$10644
- attribute \src "libresoc.v:178181.3-178182.25"
+ attribute \src "libresoc.v:177867.3-177893.6"
+ wire width 4 $0\reg$next[3:0]$10576
+ attribute \src "libresoc.v:177785.3-177786.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $0\src10__data_o$next[3:0]$10650
- attribute \src "libresoc.v:178191.3-178192.43"
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $0\src10__data_o$next[3:0]$10567
+ attribute \src "libresoc.v:177795.3-177796.43"
wire width 4 $0\src10__data_o[3:0]
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $0\src20__data_o$next[3:0]$10664
- attribute \src "libresoc.v:178189.3-178190.43"
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $0\src20__data_o$next[3:0]$10582
+ attribute \src "libresoc.v:177793.3-177794.43"
wire width 4 $0\src20__data_o[3:0]
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $0\src30__data_o$next[3:0]$10678
- attribute \src "libresoc.v:178187.3-178188.43"
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $0\src30__data_o$next[3:0]$10596
+ attribute \src "libresoc.v:177791.3-177792.43"
wire width 4 $0\src30__data_o[3:0]
- attribute \src "libresoc.v:178542.3-178571.6"
- wire $0\wr_detect$10[0:0]$10686
- attribute \src "libresoc.v:178612.3-178641.6"
- wire $0\wr_detect$13[0:0]$10700
- attribute \src "libresoc.v:178305.3-178334.6"
- wire $0\wr_detect$16[0:0]$10638
- attribute \src "libresoc.v:178402.3-178431.6"
- wire $0\wr_detect$4[0:0]$10658
- attribute \src "libresoc.v:178472.3-178501.6"
- wire $0\wr_detect$7[0:0]$10672
- attribute \src "libresoc.v:178235.3-178264.6"
+ attribute \src "libresoc.v:178074.3-178103.6"
+ wire $0\wr_detect$10[0:0]$10618
+ attribute \src "libresoc.v:178144.3-178173.6"
+ wire $0\wr_detect$13[0:0]$10632
+ attribute \src "libresoc.v:177934.3-177963.6"
+ wire $0\wr_detect$4[0:0]$10590
+ attribute \src "libresoc.v:178004.3-178033.6"
+ wire $0\wr_detect$7[0:0]$10604
+ attribute \src "libresoc.v:177837.3-177866.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $1\cr_pred0__data_o$next[3:0]$10622
- attribute \src "libresoc.v:178107.13-178107.36"
- wire width 4 $1\cr_pred0__data_o[3:0]
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $1\r0__data_o$next[3:0]$10693
- attribute \src "libresoc.v:178122.13-178122.30"
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $1\r0__data_o$next[3:0]$10611
+ attribute \src "libresoc.v:177729.13-177729.30"
wire width 4 $1\r0__data_o[3:0]
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $1\r20__data_o$next[3:0]$10631
- attribute \src "libresoc.v:178129.13-178129.31"
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $1\r20__data_o$next[3:0]$10625
+ attribute \src "libresoc.v:177736.13-177736.31"
wire width 4 $1\r20__data_o[3:0]
- attribute \src "libresoc.v:178335.3-178361.6"
- wire width 4 $1\reg$next[3:0]$10645
- attribute \src "libresoc.v:178135.13-178135.25"
+ attribute \src "libresoc.v:177867.3-177893.6"
+ wire width 4 $1\reg$next[3:0]$10577
+ attribute \src "libresoc.v:177742.13-177742.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $1\src10__data_o$next[3:0]$10651
- attribute \src "libresoc.v:178140.13-178140.33"
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $1\src10__data_o$next[3:0]$10568
+ attribute \src "libresoc.v:177747.13-177747.33"
wire width 4 $1\src10__data_o[3:0]
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $1\src20__data_o$next[3:0]$10665
- attribute \src "libresoc.v:178147.13-178147.33"
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $1\src20__data_o$next[3:0]$10583
+ attribute \src "libresoc.v:177754.13-177754.33"
wire width 4 $1\src20__data_o[3:0]
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $1\src30__data_o$next[3:0]$10679
- attribute \src "libresoc.v:178154.13-178154.33"
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $1\src30__data_o$next[3:0]$10597
+ attribute \src "libresoc.v:177761.13-177761.33"
wire width 4 $1\src30__data_o[3:0]
- attribute \src "libresoc.v:178542.3-178571.6"
- wire $1\wr_detect$10[0:0]$10687
- attribute \src "libresoc.v:178612.3-178641.6"
- wire $1\wr_detect$13[0:0]$10701
- attribute \src "libresoc.v:178305.3-178334.6"
- wire $1\wr_detect$16[0:0]$10639
- attribute \src "libresoc.v:178402.3-178431.6"
- wire $1\wr_detect$4[0:0]$10659
- attribute \src "libresoc.v:178472.3-178501.6"
- wire $1\wr_detect$7[0:0]$10673
- attribute \src "libresoc.v:178235.3-178264.6"
+ attribute \src "libresoc.v:178074.3-178103.6"
+ wire $1\wr_detect$10[0:0]$10619
+ attribute \src "libresoc.v:178144.3-178173.6"
+ wire $1\wr_detect$13[0:0]$10633
+ attribute \src "libresoc.v:177934.3-177963.6"
+ wire $1\wr_detect$4[0:0]$10591
+ attribute \src "libresoc.v:178004.3-178033.6"
+ wire $1\wr_detect$7[0:0]$10605
+ attribute \src "libresoc.v:177837.3-177866.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $2\cr_pred0__data_o$next[3:0]$10623
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $2\r0__data_o$next[3:0]$10694
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $2\r20__data_o$next[3:0]$10632
- attribute \src "libresoc.v:178335.3-178361.6"
- wire width 4 $2\reg$next[3:0]$10646
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $2\src10__data_o$next[3:0]$10652
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $2\src20__data_o$next[3:0]$10666
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $2\src30__data_o$next[3:0]$10680
- attribute \src "libresoc.v:178542.3-178571.6"
- wire $2\wr_detect$10[0:0]$10688
- attribute \src "libresoc.v:178612.3-178641.6"
- wire $2\wr_detect$13[0:0]$10702
- attribute \src "libresoc.v:178305.3-178334.6"
- wire $2\wr_detect$16[0:0]$10640
- attribute \src "libresoc.v:178402.3-178431.6"
- wire $2\wr_detect$4[0:0]$10660
- attribute \src "libresoc.v:178472.3-178501.6"
- wire $2\wr_detect$7[0:0]$10674
- attribute \src "libresoc.v:178235.3-178264.6"
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $2\r0__data_o$next[3:0]$10612
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $2\r20__data_o$next[3:0]$10626
+ attribute \src "libresoc.v:177867.3-177893.6"
+ wire width 4 $2\reg$next[3:0]$10578
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $2\src10__data_o$next[3:0]$10569
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $2\src20__data_o$next[3:0]$10584
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $2\src30__data_o$next[3:0]$10598
+ attribute \src "libresoc.v:178074.3-178103.6"
+ wire $2\wr_detect$10[0:0]$10620
+ attribute \src "libresoc.v:178144.3-178173.6"
+ wire $2\wr_detect$13[0:0]$10634
+ attribute \src "libresoc.v:177934.3-177963.6"
+ wire $2\wr_detect$4[0:0]$10592
+ attribute \src "libresoc.v:178004.3-178033.6"
+ wire $2\wr_detect$7[0:0]$10606
+ attribute \src "libresoc.v:177837.3-177866.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $3\cr_pred0__data_o$next[3:0]$10624
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $3\r0__data_o$next[3:0]$10695
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $3\r20__data_o$next[3:0]$10633
- attribute \src "libresoc.v:178335.3-178361.6"
- wire width 4 $3\reg$next[3:0]$10647
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $3\src10__data_o$next[3:0]$10653
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $3\src20__data_o$next[3:0]$10667
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $3\src30__data_o$next[3:0]$10681
- attribute \src "libresoc.v:178542.3-178571.6"
- wire $3\wr_detect$10[0:0]$10689
- attribute \src "libresoc.v:178612.3-178641.6"
- wire $3\wr_detect$13[0:0]$10703
- attribute \src "libresoc.v:178305.3-178334.6"
- wire $3\wr_detect$16[0:0]$10641
- attribute \src "libresoc.v:178402.3-178431.6"
- wire $3\wr_detect$4[0:0]$10661
- attribute \src "libresoc.v:178472.3-178501.6"
- wire $3\wr_detect$7[0:0]$10675
- attribute \src "libresoc.v:178235.3-178264.6"
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $3\r0__data_o$next[3:0]$10613
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $3\r20__data_o$next[3:0]$10627
+ attribute \src "libresoc.v:177867.3-177893.6"
+ wire width 4 $3\reg$next[3:0]$10579
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $3\src10__data_o$next[3:0]$10570
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $3\src20__data_o$next[3:0]$10585
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $3\src30__data_o$next[3:0]$10599
+ attribute \src "libresoc.v:178074.3-178103.6"
+ wire $3\wr_detect$10[0:0]$10621
+ attribute \src "libresoc.v:178144.3-178173.6"
+ wire $3\wr_detect$13[0:0]$10635
+ attribute \src "libresoc.v:177934.3-177963.6"
+ wire $3\wr_detect$4[0:0]$10593
+ attribute \src "libresoc.v:178004.3-178033.6"
+ wire $3\wr_detect$7[0:0]$10607
+ attribute \src "libresoc.v:177837.3-177866.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $4\cr_pred0__data_o$next[3:0]$10625
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $4\r0__data_o$next[3:0]$10696
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $4\r20__data_o$next[3:0]$10634
- attribute \src "libresoc.v:178335.3-178361.6"
- wire width 4 $4\reg$next[3:0]$10648
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $4\src10__data_o$next[3:0]$10654
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $4\src20__data_o$next[3:0]$10668
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $4\src30__data_o$next[3:0]$10682
- attribute \src "libresoc.v:178542.3-178571.6"
- wire $4\wr_detect$10[0:0]$10690
- attribute \src "libresoc.v:178612.3-178641.6"
- wire $4\wr_detect$13[0:0]$10704
- attribute \src "libresoc.v:178305.3-178334.6"
- wire $4\wr_detect$16[0:0]$10642
- attribute \src "libresoc.v:178402.3-178431.6"
- wire $4\wr_detect$4[0:0]$10662
- attribute \src "libresoc.v:178472.3-178501.6"
- wire $4\wr_detect$7[0:0]$10676
- attribute \src "libresoc.v:178235.3-178264.6"
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $4\r0__data_o$next[3:0]$10614
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $4\r20__data_o$next[3:0]$10628
+ attribute \src "libresoc.v:177867.3-177893.6"
+ wire width 4 $4\reg$next[3:0]$10580
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $4\src10__data_o$next[3:0]$10571
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $4\src20__data_o$next[3:0]$10586
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $4\src30__data_o$next[3:0]$10600
+ attribute \src "libresoc.v:178074.3-178103.6"
+ wire $4\wr_detect$10[0:0]$10622
+ attribute \src "libresoc.v:178144.3-178173.6"
+ wire $4\wr_detect$13[0:0]$10636
+ attribute \src "libresoc.v:177934.3-177963.6"
+ wire $4\wr_detect$4[0:0]$10594
+ attribute \src "libresoc.v:178004.3-178033.6"
+ wire $4\wr_detect$7[0:0]$10608
+ attribute \src "libresoc.v:177837.3-177866.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $5\cr_pred0__data_o$next[3:0]$10626
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $5\r0__data_o$next[3:0]$10697
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $5\r20__data_o$next[3:0]$10635
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $5\src10__data_o$next[3:0]$10655
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $5\src20__data_o$next[3:0]$10669
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $5\src30__data_o$next[3:0]$10683
- attribute \src "libresoc.v:178195.3-178234.6"
- wire width 4 $6\cr_pred0__data_o$next[3:0]$10627
- attribute \src "libresoc.v:178572.3-178611.6"
- wire width 4 $6\r0__data_o$next[3:0]$10698
- attribute \src "libresoc.v:178265.3-178304.6"
- wire width 4 $6\r20__data_o$next[3:0]$10636
- attribute \src "libresoc.v:178362.3-178401.6"
- wire width 4 $6\src10__data_o$next[3:0]$10656
- attribute \src "libresoc.v:178432.3-178471.6"
- wire width 4 $6\src20__data_o$next[3:0]$10670
- attribute \src "libresoc.v:178502.3-178541.6"
- wire width 4 $6\src30__data_o$next[3:0]$10684
- attribute \src "libresoc.v:178175.17-178175.104"
- wire $not$libresoc.v:178175$10607_Y
- attribute \src "libresoc.v:178176.18-178176.105"
- wire $not$libresoc.v:178176$10608_Y
- attribute \src "libresoc.v:178177.18-178177.105"
- wire $not$libresoc.v:178177$10609_Y
- attribute \src "libresoc.v:178178.17-178178.100"
- wire $not$libresoc.v:178178$10610_Y
- attribute \src "libresoc.v:178179.17-178179.103"
- wire $not$libresoc.v:178179$10611_Y
- attribute \src "libresoc.v:178180.17-178180.103"
- wire $not$libresoc.v:178180$10612_Y
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $5\r0__data_o$next[3:0]$10615
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $5\r20__data_o$next[3:0]$10629
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $5\src10__data_o$next[3:0]$10572
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $5\src20__data_o$next[3:0]$10587
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $5\src30__data_o$next[3:0]$10601
+ attribute \src "libresoc.v:178034.3-178073.6"
+ wire width 4 $6\r0__data_o$next[3:0]$10616
+ attribute \src "libresoc.v:178104.3-178143.6"
+ wire width 4 $6\r20__data_o$next[3:0]$10630
+ attribute \src "libresoc.v:177797.3-177836.6"
+ wire width 4 $6\src10__data_o$next[3:0]$10573
+ attribute \src "libresoc.v:177894.3-177933.6"
+ wire width 4 $6\src20__data_o$next[3:0]$10588
+ attribute \src "libresoc.v:177964.3-178003.6"
+ wire width 4 $6\src30__data_o$next[3:0]$10602
+ attribute \src "libresoc.v:177780.17-177780.104"
+ wire $not$libresoc.v:177780$10555_Y
+ attribute \src "libresoc.v:177781.18-177781.105"
+ wire $not$libresoc.v:177781$10556_Y
+ attribute \src "libresoc.v:177782.17-177782.100"
+ wire $not$libresoc.v:177782$10557_Y
+ attribute \src "libresoc.v:177783.17-177783.103"
+ wire $not$libresoc.v:177783$10558_Y
+ attribute \src "libresoc.v:177784.17-177784.103"
+ wire $not$libresoc.v:177784$10559_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred0__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred0__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred0__ren
+ wire width 4 input 9 \dest10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest10__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest10__wen
+ wire input 8 \dest10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest20__data_i
+ wire width 4 input 11 \dest20__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest20__wen
- attribute \src "libresoc.v:178088.7-178088.15"
+ wire input 10 \dest20__wen
+ attribute \src "libresoc.v:177704.7-177704.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r0__data_o
+ wire width 4 output 12 \r0__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r0__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r0__ren
+ wire input 13 \r0__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r20__data_o
+ wire width 4 output 14 \r20__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r20__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r20__ren
+ wire input 15 \r20__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src10__data_o
+ wire width 4 output 3 \src10__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src10__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src10__ren
+ wire input 2 \src10__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src20__data_o
+ wire width 4 output 5 \src20__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src20__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src20__ren
+ wire input 4 \src20__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src30__data_o
+ wire width 4 output 7 \src30__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src30__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src30__ren
+ wire input 6 \src30__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w0__data_i
+ wire width 4 input 16 \w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w0__wen
+ wire input 17 \w0__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178175$10607
+ cell $not $not$libresoc.v:177780$10555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:178175$10607_Y
+ connect \Y $not$libresoc.v:177780$10555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178176$10608
+ cell $not $not$libresoc.v:177781$10556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:178176$10608_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178177$10609
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:178177$10609_Y
+ connect \Y $not$libresoc.v:177781$10556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178178$10610
+ cell $not $not$libresoc.v:177782$10557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:178178$10610_Y
+ connect \Y $not$libresoc.v:177782$10557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178179$10611
+ cell $not $not$libresoc.v:177783$10558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:178179$10611_Y
+ connect \Y $not$libresoc.v:177783$10558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178180$10612
+ cell $not $not$libresoc.v:177784$10559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:178180$10612_Y
+ connect \Y $not$libresoc.v:177784$10559_Y
end
- attribute \src "libresoc.v:178088.7-178088.20"
- process $proc$libresoc.v:178088$10705
+ attribute \src "libresoc.v:177704.7-177704.20"
+ process $proc$libresoc.v:177704$10637
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:178107.13-178107.36"
- process $proc$libresoc.v:178107$10706
- assign { } { }
- assign $1\cr_pred0__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred0__data_o $1\cr_pred0__data_o[3:0]
- end
- attribute \src "libresoc.v:178122.13-178122.30"
- process $proc$libresoc.v:178122$10707
+ attribute \src "libresoc.v:177729.13-177729.30"
+ process $proc$libresoc.v:177729$10638
assign { } { }
assign $1\r0__data_o[3:0] 4'0000
sync always
sync init
update \r0__data_o $1\r0__data_o[3:0]
end
- attribute \src "libresoc.v:178129.13-178129.31"
- process $proc$libresoc.v:178129$10708
+ attribute \src "libresoc.v:177736.13-177736.31"
+ process $proc$libresoc.v:177736$10639
assign { } { }
assign $1\r20__data_o[3:0] 4'0000
sync always
sync init
update \r20__data_o $1\r20__data_o[3:0]
end
- attribute \src "libresoc.v:178135.13-178135.25"
- process $proc$libresoc.v:178135$10709
+ attribute \src "libresoc.v:177742.13-177742.25"
+ process $proc$libresoc.v:177742$10640
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:178140.13-178140.33"
- process $proc$libresoc.v:178140$10710
+ attribute \src "libresoc.v:177747.13-177747.33"
+ process $proc$libresoc.v:177747$10641
assign { } { }
assign $1\src10__data_o[3:0] 4'0000
sync always
sync init
update \src10__data_o $1\src10__data_o[3:0]
end
- attribute \src "libresoc.v:178147.13-178147.33"
- process $proc$libresoc.v:178147$10711
+ attribute \src "libresoc.v:177754.13-177754.33"
+ process $proc$libresoc.v:177754$10642
assign { } { }
assign $1\src20__data_o[3:0] 4'0000
sync always
sync init
update \src20__data_o $1\src20__data_o[3:0]
end
- attribute \src "libresoc.v:178154.13-178154.33"
- process $proc$libresoc.v:178154$10712
+ attribute \src "libresoc.v:177761.13-177761.33"
+ process $proc$libresoc.v:177761$10643
assign { } { }
assign $1\src30__data_o[3:0] 4'0000
sync always
sync init
update \src30__data_o $1\src30__data_o[3:0]
end
- attribute \src "libresoc.v:178181.3-178182.25"
- process $proc$libresoc.v:178181$10613
+ attribute \src "libresoc.v:177785.3-177786.25"
+ process $proc$libresoc.v:177785$10560
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:178183.3-178184.39"
- process $proc$libresoc.v:178183$10614
+ attribute \src "libresoc.v:177787.3-177788.39"
+ process $proc$libresoc.v:177787$10561
assign { } { }
assign $0\r20__data_o[3:0] \r20__data_o$next
sync posedge \coresync_clk
update \r20__data_o $0\r20__data_o[3:0]
end
- attribute \src "libresoc.v:178185.3-178186.37"
- process $proc$libresoc.v:178185$10615
+ attribute \src "libresoc.v:177789.3-177790.37"
+ process $proc$libresoc.v:177789$10562
assign { } { }
assign $0\r0__data_o[3:0] \r0__data_o$next
sync posedge \coresync_clk
update \r0__data_o $0\r0__data_o[3:0]
end
- attribute \src "libresoc.v:178187.3-178188.43"
- process $proc$libresoc.v:178187$10616
+ attribute \src "libresoc.v:177791.3-177792.43"
+ process $proc$libresoc.v:177791$10563
assign { } { }
assign $0\src30__data_o[3:0] \src30__data_o$next
sync posedge \coresync_clk
update \src30__data_o $0\src30__data_o[3:0]
end
- attribute \src "libresoc.v:178189.3-178190.43"
- process $proc$libresoc.v:178189$10617
+ attribute \src "libresoc.v:177793.3-177794.43"
+ process $proc$libresoc.v:177793$10564
assign { } { }
assign $0\src20__data_o[3:0] \src20__data_o$next
sync posedge \coresync_clk
update \src20__data_o $0\src20__data_o[3:0]
end
- attribute \src "libresoc.v:178191.3-178192.43"
- process $proc$libresoc.v:178191$10618
+ attribute \src "libresoc.v:177795.3-177796.43"
+ process $proc$libresoc.v:177795$10565
assign { } { }
assign $0\src10__data_o[3:0] \src10__data_o$next
sync posedge \coresync_clk
update \src10__data_o $0\src10__data_o[3:0]
end
- attribute \src "libresoc.v:178193.3-178194.49"
- process $proc$libresoc.v:178193$10619
+ attribute \src "libresoc.v:177797.3-177836.6"
+ process $proc$libresoc.v:177797$10566
assign { } { }
- assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next
- sync posedge \coresync_clk
- update \cr_pred0__data_o $0\cr_pred0__data_o[3:0]
- end
- attribute \src "libresoc.v:178195.3-178234.6"
- process $proc$libresoc.v:178195$10620
assign { } { }
assign { } { }
- assign { } { }
- assign $0\cr_pred0__data_o$next[3:0]$10621 $6\cr_pred0__data_o$next[3:0]$10627
- attribute \src "libresoc.v:178196.5-178196.29"
+ assign $0\src10__data_o$next[3:0]$10567 $6\src10__data_o$next[3:0]$10573
+ attribute \src "libresoc.v:177798.5-177798.29"
switch \initial
- attribute \src "libresoc.v:178196.9-178196.17"
+ attribute \src "libresoc.v:177798.9-177798.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred0__ren
+ switch \src10__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred0__data_o$next[3:0]$10622 $5\cr_pred0__data_o$next[3:0]$10626
+ assign $1\src10__data_o$next[3:0]$10568 $5\src10__data_o$next[3:0]$10572
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred0__data_o$next[3:0]$10623 \dest10__data_i
+ assign $2\src10__data_o$next[3:0]$10569 \dest10__data_i
case
- assign $2\cr_pred0__data_o$next[3:0]$10623 4'0000
+ assign $2\src10__data_o$next[3:0]$10569 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred0__data_o$next[3:0]$10624 \dest20__data_i
+ assign $3\src10__data_o$next[3:0]$10570 \dest20__data_i
case
- assign $3\cr_pred0__data_o$next[3:0]$10624 $2\cr_pred0__data_o$next[3:0]$10623
+ assign $3\src10__data_o$next[3:0]$10570 $2\src10__data_o$next[3:0]$10569
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred0__data_o$next[3:0]$10625 \w0__data_i
+ assign $4\src10__data_o$next[3:0]$10571 \w0__data_i
case
- assign $4\cr_pred0__data_o$next[3:0]$10625 $3\cr_pred0__data_o$next[3:0]$10624
+ assign $4\src10__data_o$next[3:0]$10571 $3\src10__data_o$next[3:0]$10570
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred0__data_o$next[3:0]$10626 \reg
+ assign $5\src10__data_o$next[3:0]$10572 \reg
case
- assign $5\cr_pred0__data_o$next[3:0]$10626 $4\cr_pred0__data_o$next[3:0]$10625
+ assign $5\src10__data_o$next[3:0]$10572 $4\src10__data_o$next[3:0]$10571
end
case
- assign $1\cr_pred0__data_o$next[3:0]$10622 4'0000
+ assign $1\src10__data_o$next[3:0]$10568 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred0__data_o$next[3:0]$10627 4'0000
+ assign $6\src10__data_o$next[3:0]$10573 4'0000
case
- assign $6\cr_pred0__data_o$next[3:0]$10627 $1\cr_pred0__data_o$next[3:0]$10622
+ assign $6\src10__data_o$next[3:0]$10573 $1\src10__data_o$next[3:0]$10568
end
sync always
- update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10621
+ update \src10__data_o$next $0\src10__data_o$next[3:0]$10567
end
- attribute \src "libresoc.v:178235.3-178264.6"
- process $proc$libresoc.v:178235$10628
+ attribute \src "libresoc.v:177837.3-177866.6"
+ process $proc$libresoc.v:177837$10574
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:178236.5-178236.29"
+ attribute \src "libresoc.v:177838.5-177838.29"
switch \initial
- attribute \src "libresoc.v:178236.9-178236.17"
+ attribute \src "libresoc.v:177838.9-177838.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred0__ren
+ switch \src10__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:178265.3-178304.6"
- process $proc$libresoc.v:178265$10629
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\r20__data_o$next[3:0]$10630 $6\r20__data_o$next[3:0]$10636
- attribute \src "libresoc.v:178266.5-178266.29"
- switch \initial
- attribute \src "libresoc.v:178266.9-178266.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r20__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\r20__data_o$next[3:0]$10631 $5\r20__data_o$next[3:0]$10635
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest10__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r20__data_o$next[3:0]$10632 \dest10__data_i
- case
- assign $2\r20__data_o$next[3:0]$10632 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest20__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r20__data_o$next[3:0]$10633 \dest20__data_i
- case
- assign $3\r20__data_o$next[3:0]$10633 $2\r20__data_o$next[3:0]$10632
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w0__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r20__data_o$next[3:0]$10634 \w0__data_i
- case
- assign $4\r20__data_o$next[3:0]$10634 $3\r20__data_o$next[3:0]$10633
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r20__data_o$next[3:0]$10635 \reg
- case
- assign $5\r20__data_o$next[3:0]$10635 $4\r20__data_o$next[3:0]$10634
- end
- case
- assign $1\r20__data_o$next[3:0]$10631 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\r20__data_o$next[3:0]$10636 4'0000
- case
- assign $6\r20__data_o$next[3:0]$10636 $1\r20__data_o$next[3:0]$10631
- end
- sync always
- update \r20__data_o$next $0\r20__data_o$next[3:0]$10630
- end
- attribute \src "libresoc.v:178305.3-178334.6"
- process $proc$libresoc.v:178305$10637
- assign { } { }
- assign { } { }
- assign $0\wr_detect$16[0:0]$10638 $1\wr_detect$16[0:0]$10639
- attribute \src "libresoc.v:178306.5-178306.29"
- switch \initial
- attribute \src "libresoc.v:178306.9-178306.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r20__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$16[0:0]$10639 $4\wr_detect$16[0:0]$10642
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest10__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$16[0:0]$10640 1'1
- case
- assign $2\wr_detect$16[0:0]$10640 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest20__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$16[0:0]$10641 1'1
- case
- assign $3\wr_detect$16[0:0]$10641 $2\wr_detect$16[0:0]$10640
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w0__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$16[0:0]$10642 1'1
- case
- assign $4\wr_detect$16[0:0]$10642 $3\wr_detect$16[0:0]$10641
- end
- case
- assign $1\wr_detect$16[0:0]$10639 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$10638
- end
- attribute \src "libresoc.v:178335.3-178361.6"
- process $proc$libresoc.v:178335$10643
+ attribute \src "libresoc.v:177867.3-177893.6"
+ process $proc$libresoc.v:177867$10575
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$10644 $4\reg$next[3:0]$10648
- attribute \src "libresoc.v:178336.5-178336.29"
+ assign $0\reg$next[3:0]$10576 $4\reg$next[3:0]$10580
+ attribute \src "libresoc.v:177868.5-177868.29"
switch \initial
- attribute \src "libresoc.v:178336.9-178336.17"
+ attribute \src "libresoc.v:177868.9-177868.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$10645 \dest10__data_i
+ assign $1\reg$next[3:0]$10577 \dest10__data_i
case
- assign $1\reg$next[3:0]$10645 \reg
+ assign $1\reg$next[3:0]$10577 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$10646 \dest20__data_i
+ assign $2\reg$next[3:0]$10578 \dest20__data_i
case
- assign $2\reg$next[3:0]$10646 $1\reg$next[3:0]$10645
+ assign $2\reg$next[3:0]$10578 $1\reg$next[3:0]$10577
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$10647 \w0__data_i
- case
- assign $3\reg$next[3:0]$10647 $2\reg$next[3:0]$10646
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\reg$next[3:0]$10648 4'0000
- case
- assign $4\reg$next[3:0]$10648 $3\reg$next[3:0]$10647
- end
- sync always
- update \reg$next $0\reg$next[3:0]$10644
- end
- attribute \src "libresoc.v:178362.3-178401.6"
- process $proc$libresoc.v:178362$10649
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\src10__data_o$next[3:0]$10650 $6\src10__data_o$next[3:0]$10656
- attribute \src "libresoc.v:178363.5-178363.29"
- switch \initial
- attribute \src "libresoc.v:178363.9-178363.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src10__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\src10__data_o$next[3:0]$10651 $5\src10__data_o$next[3:0]$10655
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest10__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\src10__data_o$next[3:0]$10652 \dest10__data_i
- case
- assign $2\src10__data_o$next[3:0]$10652 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest20__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\src10__data_o$next[3:0]$10653 \dest20__data_i
- case
- assign $3\src10__data_o$next[3:0]$10653 $2\src10__data_o$next[3:0]$10652
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w0__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\src10__data_o$next[3:0]$10654 \w0__data_i
- case
- assign $4\src10__data_o$next[3:0]$10654 $3\src10__data_o$next[3:0]$10653
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$3
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\src10__data_o$next[3:0]$10655 \reg
- case
- assign $5\src10__data_o$next[3:0]$10655 $4\src10__data_o$next[3:0]$10654
- end
+ assign $3\reg$next[3:0]$10579 \w0__data_i
case
- assign $1\src10__data_o$next[3:0]$10651 4'0000
+ assign $3\reg$next[3:0]$10579 $2\reg$next[3:0]$10578
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src10__data_o$next[3:0]$10656 4'0000
- case
- assign $6\src10__data_o$next[3:0]$10656 $1\src10__data_o$next[3:0]$10651
- end
- sync always
- update \src10__data_o$next $0\src10__data_o$next[3:0]$10650
- end
- attribute \src "libresoc.v:178402.3-178431.6"
- process $proc$libresoc.v:178402$10657
- assign { } { }
- assign { } { }
- assign $0\wr_detect$4[0:0]$10658 $1\wr_detect$4[0:0]$10659
- attribute \src "libresoc.v:178403.5-178403.29"
- switch \initial
- attribute \src "libresoc.v:178403.9-178403.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src10__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$4[0:0]$10659 $4\wr_detect$4[0:0]$10662
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest10__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$4[0:0]$10660 1'1
- case
- assign $2\wr_detect$4[0:0]$10660 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest20__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$4[0:0]$10661 1'1
- case
- assign $3\wr_detect$4[0:0]$10661 $2\wr_detect$4[0:0]$10660
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w0__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$4[0:0]$10662 1'1
- case
- assign $4\wr_detect$4[0:0]$10662 $3\wr_detect$4[0:0]$10661
- end
+ assign $4\reg$next[3:0]$10580 4'0000
case
- assign $1\wr_detect$4[0:0]$10659 1'0
+ assign $4\reg$next[3:0]$10580 $3\reg$next[3:0]$10579
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10658
+ update \reg$next $0\reg$next[3:0]$10576
end
- attribute \src "libresoc.v:178432.3-178471.6"
- process $proc$libresoc.v:178432$10663
+ attribute \src "libresoc.v:177894.3-177933.6"
+ process $proc$libresoc.v:177894$10581
assign { } { }
assign { } { }
assign { } { }
- assign $0\src20__data_o$next[3:0]$10664 $6\src20__data_o$next[3:0]$10670
- attribute \src "libresoc.v:178433.5-178433.29"
+ assign $0\src20__data_o$next[3:0]$10582 $6\src20__data_o$next[3:0]$10588
+ attribute \src "libresoc.v:177895.5-177895.29"
switch \initial
- attribute \src "libresoc.v:178433.9-178433.17"
+ attribute \src "libresoc.v:177895.9-177895.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src20__data_o$next[3:0]$10665 $5\src20__data_o$next[3:0]$10669
+ assign $1\src20__data_o$next[3:0]$10583 $5\src20__data_o$next[3:0]$10587
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src20__data_o$next[3:0]$10666 \dest10__data_i
+ assign $2\src20__data_o$next[3:0]$10584 \dest10__data_i
case
- assign $2\src20__data_o$next[3:0]$10666 4'0000
+ assign $2\src20__data_o$next[3:0]$10584 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src20__data_o$next[3:0]$10667 \dest20__data_i
+ assign $3\src20__data_o$next[3:0]$10585 \dest20__data_i
case
- assign $3\src20__data_o$next[3:0]$10667 $2\src20__data_o$next[3:0]$10666
+ assign $3\src20__data_o$next[3:0]$10585 $2\src20__data_o$next[3:0]$10584
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src20__data_o$next[3:0]$10668 \w0__data_i
+ assign $4\src20__data_o$next[3:0]$10586 \w0__data_i
case
- assign $4\src20__data_o$next[3:0]$10668 $3\src20__data_o$next[3:0]$10667
+ assign $4\src20__data_o$next[3:0]$10586 $3\src20__data_o$next[3:0]$10585
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$6
+ switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src20__data_o$next[3:0]$10669 \reg
+ assign $5\src20__data_o$next[3:0]$10587 \reg
case
- assign $5\src20__data_o$next[3:0]$10669 $4\src20__data_o$next[3:0]$10668
+ assign $5\src20__data_o$next[3:0]$10587 $4\src20__data_o$next[3:0]$10586
end
case
- assign $1\src20__data_o$next[3:0]$10665 4'0000
+ assign $1\src20__data_o$next[3:0]$10583 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src20__data_o$next[3:0]$10670 4'0000
+ assign $6\src20__data_o$next[3:0]$10588 4'0000
case
- assign $6\src20__data_o$next[3:0]$10670 $1\src20__data_o$next[3:0]$10665
+ assign $6\src20__data_o$next[3:0]$10588 $1\src20__data_o$next[3:0]$10583
end
sync always
- update \src20__data_o$next $0\src20__data_o$next[3:0]$10664
+ update \src20__data_o$next $0\src20__data_o$next[3:0]$10582
end
- attribute \src "libresoc.v:178472.3-178501.6"
- process $proc$libresoc.v:178472$10671
+ attribute \src "libresoc.v:177934.3-177963.6"
+ process $proc$libresoc.v:177934$10589
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10672 $1\wr_detect$7[0:0]$10673
- attribute \src "libresoc.v:178473.5-178473.29"
+ assign $0\wr_detect$4[0:0]$10590 $1\wr_detect$4[0:0]$10591
+ attribute \src "libresoc.v:177935.5-177935.29"
switch \initial
- attribute \src "libresoc.v:178473.9-178473.17"
+ attribute \src "libresoc.v:177935.9-177935.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10673 $4\wr_detect$7[0:0]$10676
+ assign $1\wr_detect$4[0:0]$10591 $4\wr_detect$4[0:0]$10594
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10674 1'1
+ assign $2\wr_detect$4[0:0]$10592 1'1
case
- assign $2\wr_detect$7[0:0]$10674 1'0
+ assign $2\wr_detect$4[0:0]$10592 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10675 1'1
+ assign $3\wr_detect$4[0:0]$10593 1'1
case
- assign $3\wr_detect$7[0:0]$10675 $2\wr_detect$7[0:0]$10674
+ assign $3\wr_detect$4[0:0]$10593 $2\wr_detect$4[0:0]$10592
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10676 1'1
+ assign $4\wr_detect$4[0:0]$10594 1'1
case
- assign $4\wr_detect$7[0:0]$10676 $3\wr_detect$7[0:0]$10675
+ assign $4\wr_detect$4[0:0]$10594 $3\wr_detect$4[0:0]$10593
end
case
- assign $1\wr_detect$7[0:0]$10673 1'0
+ assign $1\wr_detect$4[0:0]$10591 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10672
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10590
end
- attribute \src "libresoc.v:178502.3-178541.6"
- process $proc$libresoc.v:178502$10677
+ attribute \src "libresoc.v:177964.3-178003.6"
+ process $proc$libresoc.v:177964$10595
assign { } { }
assign { } { }
assign { } { }
- assign $0\src30__data_o$next[3:0]$10678 $6\src30__data_o$next[3:0]$10684
- attribute \src "libresoc.v:178503.5-178503.29"
+ assign $0\src30__data_o$next[3:0]$10596 $6\src30__data_o$next[3:0]$10602
+ attribute \src "libresoc.v:177965.5-177965.29"
switch \initial
- attribute \src "libresoc.v:178503.9-178503.17"
+ attribute \src "libresoc.v:177965.9-177965.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src30__data_o$next[3:0]$10679 $5\src30__data_o$next[3:0]$10683
+ assign $1\src30__data_o$next[3:0]$10597 $5\src30__data_o$next[3:0]$10601
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src30__data_o$next[3:0]$10680 \dest10__data_i
+ assign $2\src30__data_o$next[3:0]$10598 \dest10__data_i
case
- assign $2\src30__data_o$next[3:0]$10680 4'0000
+ assign $2\src30__data_o$next[3:0]$10598 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src30__data_o$next[3:0]$10681 \dest20__data_i
+ assign $3\src30__data_o$next[3:0]$10599 \dest20__data_i
case
- assign $3\src30__data_o$next[3:0]$10681 $2\src30__data_o$next[3:0]$10680
+ assign $3\src30__data_o$next[3:0]$10599 $2\src30__data_o$next[3:0]$10598
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src30__data_o$next[3:0]$10682 \w0__data_i
+ assign $4\src30__data_o$next[3:0]$10600 \w0__data_i
case
- assign $4\src30__data_o$next[3:0]$10682 $3\src30__data_o$next[3:0]$10681
+ assign $4\src30__data_o$next[3:0]$10600 $3\src30__data_o$next[3:0]$10599
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$9
+ switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src30__data_o$next[3:0]$10683 \reg
+ assign $5\src30__data_o$next[3:0]$10601 \reg
case
- assign $5\src30__data_o$next[3:0]$10683 $4\src30__data_o$next[3:0]$10682
+ assign $5\src30__data_o$next[3:0]$10601 $4\src30__data_o$next[3:0]$10600
end
case
- assign $1\src30__data_o$next[3:0]$10679 4'0000
+ assign $1\src30__data_o$next[3:0]$10597 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src30__data_o$next[3:0]$10684 4'0000
+ assign $6\src30__data_o$next[3:0]$10602 4'0000
case
- assign $6\src30__data_o$next[3:0]$10684 $1\src30__data_o$next[3:0]$10679
+ assign $6\src30__data_o$next[3:0]$10602 $1\src30__data_o$next[3:0]$10597
end
sync always
- update \src30__data_o$next $0\src30__data_o$next[3:0]$10678
+ update \src30__data_o$next $0\src30__data_o$next[3:0]$10596
end
- attribute \src "libresoc.v:178542.3-178571.6"
- process $proc$libresoc.v:178542$10685
+ attribute \src "libresoc.v:178004.3-178033.6"
+ process $proc$libresoc.v:178004$10603
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10686 $1\wr_detect$10[0:0]$10687
- attribute \src "libresoc.v:178543.5-178543.29"
+ assign $0\wr_detect$7[0:0]$10604 $1\wr_detect$7[0:0]$10605
+ attribute \src "libresoc.v:178005.5-178005.29"
switch \initial
- attribute \src "libresoc.v:178543.9-178543.17"
+ attribute \src "libresoc.v:178005.9-178005.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10687 $4\wr_detect$10[0:0]$10690
+ assign $1\wr_detect$7[0:0]$10605 $4\wr_detect$7[0:0]$10608
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10688 1'1
+ assign $2\wr_detect$7[0:0]$10606 1'1
case
- assign $2\wr_detect$10[0:0]$10688 1'0
+ assign $2\wr_detect$7[0:0]$10606 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10689 1'1
+ assign $3\wr_detect$7[0:0]$10607 1'1
case
- assign $3\wr_detect$10[0:0]$10689 $2\wr_detect$10[0:0]$10688
+ assign $3\wr_detect$7[0:0]$10607 $2\wr_detect$7[0:0]$10606
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10690 1'1
+ assign $4\wr_detect$7[0:0]$10608 1'1
case
- assign $4\wr_detect$10[0:0]$10690 $3\wr_detect$10[0:0]$10689
+ assign $4\wr_detect$7[0:0]$10608 $3\wr_detect$7[0:0]$10607
end
case
- assign $1\wr_detect$10[0:0]$10687 1'0
+ assign $1\wr_detect$7[0:0]$10605 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10686
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10604
end
- attribute \src "libresoc.v:178572.3-178611.6"
- process $proc$libresoc.v:178572$10691
+ attribute \src "libresoc.v:178034.3-178073.6"
+ process $proc$libresoc.v:178034$10609
assign { } { }
assign { } { }
assign { } { }
- assign $0\r0__data_o$next[3:0]$10692 $6\r0__data_o$next[3:0]$10698
- attribute \src "libresoc.v:178573.5-178573.29"
+ assign $0\r0__data_o$next[3:0]$10610 $6\r0__data_o$next[3:0]$10616
+ attribute \src "libresoc.v:178035.5-178035.29"
switch \initial
- attribute \src "libresoc.v:178573.9-178573.17"
+ attribute \src "libresoc.v:178035.9-178035.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r0__data_o$next[3:0]$10693 $5\r0__data_o$next[3:0]$10697
+ assign $1\r0__data_o$next[3:0]$10611 $5\r0__data_o$next[3:0]$10615
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r0__data_o$next[3:0]$10694 \dest10__data_i
+ assign $2\r0__data_o$next[3:0]$10612 \dest10__data_i
case
- assign $2\r0__data_o$next[3:0]$10694 4'0000
+ assign $2\r0__data_o$next[3:0]$10612 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r0__data_o$next[3:0]$10695 \dest20__data_i
+ assign $3\r0__data_o$next[3:0]$10613 \dest20__data_i
case
- assign $3\r0__data_o$next[3:0]$10695 $2\r0__data_o$next[3:0]$10694
+ assign $3\r0__data_o$next[3:0]$10613 $2\r0__data_o$next[3:0]$10612
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r0__data_o$next[3:0]$10696 \w0__data_i
+ assign $4\r0__data_o$next[3:0]$10614 \w0__data_i
case
- assign $4\r0__data_o$next[3:0]$10696 $3\r0__data_o$next[3:0]$10695
+ assign $4\r0__data_o$next[3:0]$10614 $3\r0__data_o$next[3:0]$10613
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$12
+ switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r0__data_o$next[3:0]$10697 \reg
+ assign $5\r0__data_o$next[3:0]$10615 \reg
case
- assign $5\r0__data_o$next[3:0]$10697 $4\r0__data_o$next[3:0]$10696
+ assign $5\r0__data_o$next[3:0]$10615 $4\r0__data_o$next[3:0]$10614
end
case
- assign $1\r0__data_o$next[3:0]$10693 4'0000
+ assign $1\r0__data_o$next[3:0]$10611 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r0__data_o$next[3:0]$10698 4'0000
+ assign $6\r0__data_o$next[3:0]$10616 4'0000
case
- assign $6\r0__data_o$next[3:0]$10698 $1\r0__data_o$next[3:0]$10693
+ assign $6\r0__data_o$next[3:0]$10616 $1\r0__data_o$next[3:0]$10611
end
sync always
- update \r0__data_o$next $0\r0__data_o$next[3:0]$10692
+ update \r0__data_o$next $0\r0__data_o$next[3:0]$10610
end
- attribute \src "libresoc.v:178612.3-178641.6"
- process $proc$libresoc.v:178612$10699
+ attribute \src "libresoc.v:178074.3-178103.6"
+ process $proc$libresoc.v:178074$10617
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$10700 $1\wr_detect$13[0:0]$10701
- attribute \src "libresoc.v:178613.5-178613.29"
+ assign $0\wr_detect$10[0:0]$10618 $1\wr_detect$10[0:0]$10619
+ attribute \src "libresoc.v:178075.5-178075.29"
switch \initial
- attribute \src "libresoc.v:178613.9-178613.17"
+ attribute \src "libresoc.v:178075.9-178075.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$10701 $4\wr_detect$13[0:0]$10704
+ assign $1\wr_detect$10[0:0]$10619 $4\wr_detect$10[0:0]$10622
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$10702 1'1
+ assign $2\wr_detect$10[0:0]$10620 1'1
case
- assign $2\wr_detect$13[0:0]$10702 1'0
+ assign $2\wr_detect$10[0:0]$10620 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$10703 1'1
+ assign $3\wr_detect$10[0:0]$10621 1'1
case
- assign $3\wr_detect$13[0:0]$10703 $2\wr_detect$13[0:0]$10702
+ assign $3\wr_detect$10[0:0]$10621 $2\wr_detect$10[0:0]$10620
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$10704 1'1
+ assign $4\wr_detect$10[0:0]$10622 1'1
case
- assign $4\wr_detect$13[0:0]$10704 $3\wr_detect$13[0:0]$10703
+ assign $4\wr_detect$10[0:0]$10622 $3\wr_detect$10[0:0]$10621
end
case
- assign $1\wr_detect$13[0:0]$10701 1'0
+ assign $1\wr_detect$10[0:0]$10619 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$10700
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10618
end
- connect \$9 $not$libresoc.v:178175$10607_Y
- connect \$12 $not$libresoc.v:178176$10608_Y
- connect \$15 $not$libresoc.v:178177$10609_Y
- connect \$1 $not$libresoc.v:178178$10610_Y
- connect \$3 $not$libresoc.v:178179$10611_Y
- connect \$6 $not$libresoc.v:178180$10612_Y
+ attribute \src "libresoc.v:178104.3-178143.6"
+ process $proc$libresoc.v:178104$10623
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\r20__data_o$next[3:0]$10624 $6\r20__data_o$next[3:0]$10630
+ attribute \src "libresoc.v:178105.5-178105.29"
+ switch \initial
+ attribute \src "libresoc.v:178105.9-178105.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch \r20__ren
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $1\r20__data_o$next[3:0]$10625 $5\r20__data_o$next[3:0]$10629
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \dest10__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\r20__data_o$next[3:0]$10626 \dest10__data_i
+ case
+ assign $2\r20__data_o$next[3:0]$10626 4'0000
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \dest20__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\r20__data_o$next[3:0]$10627 \dest20__data_i
+ case
+ assign $3\r20__data_o$next[3:0]$10627 $2\r20__data_o$next[3:0]$10626
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \w0__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\r20__data_o$next[3:0]$10628 \w0__data_i
+ case
+ assign $4\r20__data_o$next[3:0]$10628 $3\r20__data_o$next[3:0]$10627
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
+ switch \$12
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\r20__data_o$next[3:0]$10629 \reg
+ case
+ assign $5\r20__data_o$next[3:0]$10629 $4\r20__data_o$next[3:0]$10628
+ end
+ case
+ assign $1\r20__data_o$next[3:0]$10625 4'0000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\r20__data_o$next[3:0]$10630 4'0000
+ case
+ assign $6\r20__data_o$next[3:0]$10630 $1\r20__data_o$next[3:0]$10625
+ end
+ sync always
+ update \r20__data_o$next $0\r20__data_o$next[3:0]$10624
+ end
+ attribute \src "libresoc.v:178144.3-178173.6"
+ process $proc$libresoc.v:178144$10631
+ assign { } { }
+ assign { } { }
+ assign $0\wr_detect$13[0:0]$10632 $1\wr_detect$13[0:0]$10633
+ attribute \src "libresoc.v:178145.5-178145.29"
+ switch \initial
+ attribute \src "libresoc.v:178145.9-178145.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch \r20__ren
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $1\wr_detect$13[0:0]$10633 $4\wr_detect$13[0:0]$10636
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \dest10__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\wr_detect$13[0:0]$10634 1'1
+ case
+ assign $2\wr_detect$13[0:0]$10634 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \dest20__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\wr_detect$13[0:0]$10635 1'1
+ case
+ assign $3\wr_detect$13[0:0]$10635 $2\wr_detect$13[0:0]$10634
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
+ switch \w0__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\wr_detect$13[0:0]$10636 1'1
+ case
+ assign $4\wr_detect$13[0:0]$10636 $3\wr_detect$13[0:0]$10635
+ end
+ case
+ assign $1\wr_detect$13[0:0]$10633 1'0
+ end
+ sync always
+ update \wr_detect$13 $0\wr_detect$13[0:0]$10632
+ end
+ connect \$9 $not$libresoc.v:177780$10555_Y
+ connect \$12 $not$libresoc.v:177781$10556_Y
+ connect \$1 $not$libresoc.v:177782$10557_Y
+ connect \$3 $not$libresoc.v:177783$10558_Y
+ connect \$6 $not$libresoc.v:177784$10559_Y
end
-attribute \src "libresoc.v:178646.1-179091.10"
+attribute \src "libresoc.v:178178.1-178623.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0"
attribute \generator "nMigen"
module \reg_0$132
- attribute \src "libresoc.v:178647.7-178647.20"
+ attribute \src "libresoc.v:178179.7-178179.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $0\r0__data_o$next[1:0]$10765
- attribute \src "libresoc.v:178722.3-178723.37"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $0\r0__data_o$next[1:0]$10696
+ attribute \src "libresoc.v:178254.3-178255.37"
wire width 2 $0\r0__data_o[1:0]
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $0\reg$next[1:0]$10781
- attribute \src "libresoc.v:178720.3-178721.25"
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $0\reg$next[1:0]$10712
+ attribute \src "libresoc.v:178252.3-178253.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $0\src10__data_o$next[1:0]$10723
- attribute \src "libresoc.v:178728.3-178729.43"
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $0\src10__data_o$next[1:0]$10654
+ attribute \src "libresoc.v:178260.3-178261.43"
wire width 2 $0\src10__data_o[1:0]
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $0\src20__data_o$next[1:0]$10733
- attribute \src "libresoc.v:178726.3-178727.43"
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $0\src20__data_o$next[1:0]$10664
+ attribute \src "libresoc.v:178258.3-178259.43"
wire width 2 $0\src20__data_o[1:0]
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $0\src30__data_o$next[1:0]$10749
- attribute \src "libresoc.v:178724.3-178725.43"
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $0\src30__data_o$next[1:0]$10680
+ attribute \src "libresoc.v:178256.3-178257.43"
wire width 2 $0\src30__data_o[1:0]
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $0\wr_detect$10[0:0]$10774
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $0\wr_detect$4[0:0]$10742
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $0\wr_detect$7[0:0]$10758
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $0\wr_detect$10[0:0]$10705
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $0\wr_detect$4[0:0]$10673
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $0\wr_detect$7[0:0]$10689
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $1\r0__data_o$next[1:0]$10766
- attribute \src "libresoc.v:178674.13-178674.30"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $1\r0__data_o$next[1:0]$10697
+ attribute \src "libresoc.v:178206.13-178206.30"
wire width 2 $1\r0__data_o[1:0]
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $1\reg$next[1:0]$10782
- attribute \src "libresoc.v:178680.13-178680.25"
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $1\reg$next[1:0]$10713
+ attribute \src "libresoc.v:178212.13-178212.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $1\src10__data_o$next[1:0]$10724
- attribute \src "libresoc.v:178685.13-178685.33"
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $1\src10__data_o$next[1:0]$10655
+ attribute \src "libresoc.v:178217.13-178217.33"
wire width 2 $1\src10__data_o[1:0]
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $1\src20__data_o$next[1:0]$10734
- attribute \src "libresoc.v:178692.13-178692.33"
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $1\src20__data_o$next[1:0]$10665
+ attribute \src "libresoc.v:178224.13-178224.33"
wire width 2 $1\src20__data_o[1:0]
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $1\src30__data_o$next[1:0]$10750
- attribute \src "libresoc.v:178699.13-178699.33"
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $1\src30__data_o$next[1:0]$10681
+ attribute \src "libresoc.v:178231.13-178231.33"
wire width 2 $1\src30__data_o[1:0]
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $1\wr_detect$10[0:0]$10775
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $1\wr_detect$4[0:0]$10743
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $1\wr_detect$7[0:0]$10759
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $1\wr_detect$10[0:0]$10706
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $1\wr_detect$4[0:0]$10674
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $1\wr_detect$7[0:0]$10690
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $2\r0__data_o$next[1:0]$10767
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $2\reg$next[1:0]$10783
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $2\src10__data_o$next[1:0]$10725
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $2\src20__data_o$next[1:0]$10735
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $2\src30__data_o$next[1:0]$10751
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $2\wr_detect$10[0:0]$10776
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $2\wr_detect$4[0:0]$10744
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $2\wr_detect$7[0:0]$10760
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $2\r0__data_o$next[1:0]$10698
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $2\reg$next[1:0]$10714
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $2\src10__data_o$next[1:0]$10656
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $2\src20__data_o$next[1:0]$10666
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $2\src30__data_o$next[1:0]$10682
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $2\wr_detect$10[0:0]$10707
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $2\wr_detect$4[0:0]$10675
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $2\wr_detect$7[0:0]$10691
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $3\r0__data_o$next[1:0]$10768
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $3\reg$next[1:0]$10784
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $3\src10__data_o$next[1:0]$10726
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $3\src20__data_o$next[1:0]$10736
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $3\src30__data_o$next[1:0]$10752
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $3\wr_detect$10[0:0]$10777
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $3\wr_detect$4[0:0]$10745
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $3\wr_detect$7[0:0]$10761
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $3\r0__data_o$next[1:0]$10699
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $3\reg$next[1:0]$10715
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $3\src10__data_o$next[1:0]$10657
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $3\src20__data_o$next[1:0]$10667
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $3\src30__data_o$next[1:0]$10683
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $3\wr_detect$10[0:0]$10708
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $3\wr_detect$4[0:0]$10676
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $3\wr_detect$7[0:0]$10692
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $4\r0__data_o$next[1:0]$10769
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $4\reg$next[1:0]$10785
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $4\src10__data_o$next[1:0]$10727
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $4\src20__data_o$next[1:0]$10737
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $4\src30__data_o$next[1:0]$10753
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $4\wr_detect$10[0:0]$10778
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $4\wr_detect$4[0:0]$10746
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $4\wr_detect$7[0:0]$10762
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $4\r0__data_o$next[1:0]$10700
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $4\reg$next[1:0]$10716
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $4\src10__data_o$next[1:0]$10658
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $4\src20__data_o$next[1:0]$10668
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $4\src30__data_o$next[1:0]$10684
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $4\wr_detect$10[0:0]$10709
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $4\wr_detect$4[0:0]$10677
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $4\wr_detect$7[0:0]$10693
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $5\r0__data_o$next[1:0]$10770
- attribute \src "libresoc.v:179058.3-179090.6"
- wire width 2 $5\reg$next[1:0]$10786
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $5\src10__data_o$next[1:0]$10728
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $5\src20__data_o$next[1:0]$10738
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $5\src30__data_o$next[1:0]$10754
- attribute \src "libresoc.v:179022.3-179057.6"
- wire $5\wr_detect$10[0:0]$10779
- attribute \src "libresoc.v:178858.3-178893.6"
- wire $5\wr_detect$4[0:0]$10747
- attribute \src "libresoc.v:178940.3-178975.6"
- wire $5\wr_detect$7[0:0]$10763
- attribute \src "libresoc.v:178776.3-178811.6"
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $5\r0__data_o$next[1:0]$10701
+ attribute \src "libresoc.v:178590.3-178622.6"
+ wire width 2 $5\reg$next[1:0]$10717
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $5\src10__data_o$next[1:0]$10659
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $5\src20__data_o$next[1:0]$10669
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $5\src30__data_o$next[1:0]$10685
+ attribute \src "libresoc.v:178554.3-178589.6"
+ wire $5\wr_detect$10[0:0]$10710
+ attribute \src "libresoc.v:178390.3-178425.6"
+ wire $5\wr_detect$4[0:0]$10678
+ attribute \src "libresoc.v:178472.3-178507.6"
+ wire $5\wr_detect$7[0:0]$10694
+ attribute \src "libresoc.v:178308.3-178343.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $6\r0__data_o$next[1:0]$10771
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $6\src10__data_o$next[1:0]$10729
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $6\src20__data_o$next[1:0]$10739
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $6\src30__data_o$next[1:0]$10755
- attribute \src "libresoc.v:178976.3-179021.6"
- wire width 2 $7\r0__data_o$next[1:0]$10772
- attribute \src "libresoc.v:178730.3-178775.6"
- wire width 2 $7\src10__data_o$next[1:0]$10730
- attribute \src "libresoc.v:178812.3-178857.6"
- wire width 2 $7\src20__data_o$next[1:0]$10740
- attribute \src "libresoc.v:178894.3-178939.6"
- wire width 2 $7\src30__data_o$next[1:0]$10756
- attribute \src "libresoc.v:178716.17-178716.104"
- wire $not$libresoc.v:178716$10713_Y
- attribute \src "libresoc.v:178717.17-178717.100"
- wire $not$libresoc.v:178717$10714_Y
- attribute \src "libresoc.v:178718.17-178718.103"
- wire $not$libresoc.v:178718$10715_Y
- attribute \src "libresoc.v:178719.17-178719.103"
- wire $not$libresoc.v:178719$10716_Y
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $6\r0__data_o$next[1:0]$10702
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $6\src10__data_o$next[1:0]$10660
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $6\src20__data_o$next[1:0]$10670
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $6\src30__data_o$next[1:0]$10686
+ attribute \src "libresoc.v:178508.3-178553.6"
+ wire width 2 $7\r0__data_o$next[1:0]$10703
+ attribute \src "libresoc.v:178262.3-178307.6"
+ wire width 2 $7\src10__data_o$next[1:0]$10661
+ attribute \src "libresoc.v:178344.3-178389.6"
+ wire width 2 $7\src20__data_o$next[1:0]$10671
+ attribute \src "libresoc.v:178426.3-178471.6"
+ wire width 2 $7\src30__data_o$next[1:0]$10687
+ attribute \src "libresoc.v:178248.17-178248.104"
+ wire $not$libresoc.v:178248$10644_Y
+ attribute \src "libresoc.v:178249.17-178249.100"
+ wire $not$libresoc.v:178249$10645_Y
+ attribute \src "libresoc.v:178250.17-178250.103"
+ wire $not$libresoc.v:178250$10646_Y
+ attribute \src "libresoc.v:178251.17-178251.103"
+ wire $not$libresoc.v:178251$10647_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest10__data_i
wire width 2 input 13 \dest30__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest30__wen
- attribute \src "libresoc.v:178647.7-178647.15"
+ attribute \src "libresoc.v:178179.7-178179.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r0__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178716$10713
+ cell $not $not$libresoc.v:178248$10644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:178716$10713_Y
+ connect \Y $not$libresoc.v:178248$10644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178717$10714
+ cell $not $not$libresoc.v:178249$10645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:178717$10714_Y
+ connect \Y $not$libresoc.v:178249$10645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178718$10715
+ cell $not $not$libresoc.v:178250$10646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:178718$10715_Y
+ connect \Y $not$libresoc.v:178250$10646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178719$10716
+ cell $not $not$libresoc.v:178251$10647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:178719$10716_Y
+ connect \Y $not$libresoc.v:178251$10647_Y
end
- attribute \src "libresoc.v:178647.7-178647.20"
- process $proc$libresoc.v:178647$10787
+ attribute \src "libresoc.v:178179.7-178179.20"
+ process $proc$libresoc.v:178179$10718
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:178674.13-178674.30"
- process $proc$libresoc.v:178674$10788
+ attribute \src "libresoc.v:178206.13-178206.30"
+ process $proc$libresoc.v:178206$10719
assign { } { }
assign $1\r0__data_o[1:0] 2'00
sync always
sync init
update \r0__data_o $1\r0__data_o[1:0]
end
- attribute \src "libresoc.v:178680.13-178680.25"
- process $proc$libresoc.v:178680$10789
+ attribute \src "libresoc.v:178212.13-178212.25"
+ process $proc$libresoc.v:178212$10720
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:178685.13-178685.33"
- process $proc$libresoc.v:178685$10790
+ attribute \src "libresoc.v:178217.13-178217.33"
+ process $proc$libresoc.v:178217$10721
assign { } { }
assign $1\src10__data_o[1:0] 2'00
sync always
sync init
update \src10__data_o $1\src10__data_o[1:0]
end
- attribute \src "libresoc.v:178692.13-178692.33"
- process $proc$libresoc.v:178692$10791
+ attribute \src "libresoc.v:178224.13-178224.33"
+ process $proc$libresoc.v:178224$10722
assign { } { }
assign $1\src20__data_o[1:0] 2'00
sync always
sync init
update \src20__data_o $1\src20__data_o[1:0]
end
- attribute \src "libresoc.v:178699.13-178699.33"
- process $proc$libresoc.v:178699$10792
+ attribute \src "libresoc.v:178231.13-178231.33"
+ process $proc$libresoc.v:178231$10723
assign { } { }
assign $1\src30__data_o[1:0] 2'00
sync always
sync init
update \src30__data_o $1\src30__data_o[1:0]
end
- attribute \src "libresoc.v:178720.3-178721.25"
- process $proc$libresoc.v:178720$10717
+ attribute \src "libresoc.v:178252.3-178253.25"
+ process $proc$libresoc.v:178252$10648
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:178722.3-178723.37"
- process $proc$libresoc.v:178722$10718
+ attribute \src "libresoc.v:178254.3-178255.37"
+ process $proc$libresoc.v:178254$10649
assign { } { }
assign $0\r0__data_o[1:0] \r0__data_o$next
sync posedge \coresync_clk
update \r0__data_o $0\r0__data_o[1:0]
end
- attribute \src "libresoc.v:178724.3-178725.43"
- process $proc$libresoc.v:178724$10719
+ attribute \src "libresoc.v:178256.3-178257.43"
+ process $proc$libresoc.v:178256$10650
assign { } { }
assign $0\src30__data_o[1:0] \src30__data_o$next
sync posedge \coresync_clk
update \src30__data_o $0\src30__data_o[1:0]
end
- attribute \src "libresoc.v:178726.3-178727.43"
- process $proc$libresoc.v:178726$10720
+ attribute \src "libresoc.v:178258.3-178259.43"
+ process $proc$libresoc.v:178258$10651
assign { } { }
assign $0\src20__data_o[1:0] \src20__data_o$next
sync posedge \coresync_clk
update \src20__data_o $0\src20__data_o[1:0]
end
- attribute \src "libresoc.v:178728.3-178729.43"
- process $proc$libresoc.v:178728$10721
+ attribute \src "libresoc.v:178260.3-178261.43"
+ process $proc$libresoc.v:178260$10652
assign { } { }
assign $0\src10__data_o[1:0] \src10__data_o$next
sync posedge \coresync_clk
update \src10__data_o $0\src10__data_o[1:0]
end
- attribute \src "libresoc.v:178730.3-178775.6"
- process $proc$libresoc.v:178730$10722
+ attribute \src "libresoc.v:178262.3-178307.6"
+ process $proc$libresoc.v:178262$10653
assign { } { }
assign { } { }
assign { } { }
- assign $0\src10__data_o$next[1:0]$10723 $7\src10__data_o$next[1:0]$10730
- attribute \src "libresoc.v:178731.5-178731.29"
+ assign $0\src10__data_o$next[1:0]$10654 $7\src10__data_o$next[1:0]$10661
+ attribute \src "libresoc.v:178263.5-178263.29"
switch \initial
- attribute \src "libresoc.v:178731.9-178731.17"
+ attribute \src "libresoc.v:178263.9-178263.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src10__data_o$next[1:0]$10724 $6\src10__data_o$next[1:0]$10729
+ assign $1\src10__data_o$next[1:0]$10655 $6\src10__data_o$next[1:0]$10660
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src10__data_o$next[1:0]$10725 \dest10__data_i
+ assign $2\src10__data_o$next[1:0]$10656 \dest10__data_i
case
- assign $2\src10__data_o$next[1:0]$10725 2'00
+ assign $2\src10__data_o$next[1:0]$10656 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src10__data_o$next[1:0]$10726 \dest20__data_i
+ assign $3\src10__data_o$next[1:0]$10657 \dest20__data_i
case
- assign $3\src10__data_o$next[1:0]$10726 $2\src10__data_o$next[1:0]$10725
+ assign $3\src10__data_o$next[1:0]$10657 $2\src10__data_o$next[1:0]$10656
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src10__data_o$next[1:0]$10727 \dest30__data_i
+ assign $4\src10__data_o$next[1:0]$10658 \dest30__data_i
case
- assign $4\src10__data_o$next[1:0]$10727 $3\src10__data_o$next[1:0]$10726
+ assign $4\src10__data_o$next[1:0]$10658 $3\src10__data_o$next[1:0]$10657
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src10__data_o$next[1:0]$10728 \w0__data_i
+ assign $5\src10__data_o$next[1:0]$10659 \w0__data_i
case
- assign $5\src10__data_o$next[1:0]$10728 $4\src10__data_o$next[1:0]$10727
+ assign $5\src10__data_o$next[1:0]$10659 $4\src10__data_o$next[1:0]$10658
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src10__data_o$next[1:0]$10729 \reg
+ assign $6\src10__data_o$next[1:0]$10660 \reg
case
- assign $6\src10__data_o$next[1:0]$10729 $5\src10__data_o$next[1:0]$10728
+ assign $6\src10__data_o$next[1:0]$10660 $5\src10__data_o$next[1:0]$10659
end
case
- assign $1\src10__data_o$next[1:0]$10724 2'00
+ assign $1\src10__data_o$next[1:0]$10655 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src10__data_o$next[1:0]$10730 2'00
+ assign $7\src10__data_o$next[1:0]$10661 2'00
case
- assign $7\src10__data_o$next[1:0]$10730 $1\src10__data_o$next[1:0]$10724
+ assign $7\src10__data_o$next[1:0]$10661 $1\src10__data_o$next[1:0]$10655
end
sync always
- update \src10__data_o$next $0\src10__data_o$next[1:0]$10723
+ update \src10__data_o$next $0\src10__data_o$next[1:0]$10654
end
- attribute \src "libresoc.v:178776.3-178811.6"
- process $proc$libresoc.v:178776$10731
+ attribute \src "libresoc.v:178308.3-178343.6"
+ process $proc$libresoc.v:178308$10662
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:178777.5-178777.29"
+ attribute \src "libresoc.v:178309.5-178309.29"
switch \initial
- attribute \src "libresoc.v:178777.9-178777.17"
+ attribute \src "libresoc.v:178309.9-178309.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:178812.3-178857.6"
- process $proc$libresoc.v:178812$10732
+ attribute \src "libresoc.v:178344.3-178389.6"
+ process $proc$libresoc.v:178344$10663
assign { } { }
assign { } { }
assign { } { }
- assign $0\src20__data_o$next[1:0]$10733 $7\src20__data_o$next[1:0]$10740
- attribute \src "libresoc.v:178813.5-178813.29"
+ assign $0\src20__data_o$next[1:0]$10664 $7\src20__data_o$next[1:0]$10671
+ attribute \src "libresoc.v:178345.5-178345.29"
switch \initial
- attribute \src "libresoc.v:178813.9-178813.17"
+ attribute \src "libresoc.v:178345.9-178345.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src20__data_o$next[1:0]$10734 $6\src20__data_o$next[1:0]$10739
+ assign $1\src20__data_o$next[1:0]$10665 $6\src20__data_o$next[1:0]$10670
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src20__data_o$next[1:0]$10735 \dest10__data_i
+ assign $2\src20__data_o$next[1:0]$10666 \dest10__data_i
case
- assign $2\src20__data_o$next[1:0]$10735 2'00
+ assign $2\src20__data_o$next[1:0]$10666 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src20__data_o$next[1:0]$10736 \dest20__data_i
+ assign $3\src20__data_o$next[1:0]$10667 \dest20__data_i
case
- assign $3\src20__data_o$next[1:0]$10736 $2\src20__data_o$next[1:0]$10735
+ assign $3\src20__data_o$next[1:0]$10667 $2\src20__data_o$next[1:0]$10666
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src20__data_o$next[1:0]$10737 \dest30__data_i
+ assign $4\src20__data_o$next[1:0]$10668 \dest30__data_i
case
- assign $4\src20__data_o$next[1:0]$10737 $3\src20__data_o$next[1:0]$10736
+ assign $4\src20__data_o$next[1:0]$10668 $3\src20__data_o$next[1:0]$10667
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src20__data_o$next[1:0]$10738 \w0__data_i
+ assign $5\src20__data_o$next[1:0]$10669 \w0__data_i
case
- assign $5\src20__data_o$next[1:0]$10738 $4\src20__data_o$next[1:0]$10737
+ assign $5\src20__data_o$next[1:0]$10669 $4\src20__data_o$next[1:0]$10668
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src20__data_o$next[1:0]$10739 \reg
+ assign $6\src20__data_o$next[1:0]$10670 \reg
case
- assign $6\src20__data_o$next[1:0]$10739 $5\src20__data_o$next[1:0]$10738
+ assign $6\src20__data_o$next[1:0]$10670 $5\src20__data_o$next[1:0]$10669
end
case
- assign $1\src20__data_o$next[1:0]$10734 2'00
+ assign $1\src20__data_o$next[1:0]$10665 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src20__data_o$next[1:0]$10740 2'00
+ assign $7\src20__data_o$next[1:0]$10671 2'00
case
- assign $7\src20__data_o$next[1:0]$10740 $1\src20__data_o$next[1:0]$10734
+ assign $7\src20__data_o$next[1:0]$10671 $1\src20__data_o$next[1:0]$10665
end
sync always
- update \src20__data_o$next $0\src20__data_o$next[1:0]$10733
+ update \src20__data_o$next $0\src20__data_o$next[1:0]$10664
end
- attribute \src "libresoc.v:178858.3-178893.6"
- process $proc$libresoc.v:178858$10741
+ attribute \src "libresoc.v:178390.3-178425.6"
+ process $proc$libresoc.v:178390$10672
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10742 $1\wr_detect$4[0:0]$10743
- attribute \src "libresoc.v:178859.5-178859.29"
+ assign $0\wr_detect$4[0:0]$10673 $1\wr_detect$4[0:0]$10674
+ attribute \src "libresoc.v:178391.5-178391.29"
switch \initial
- attribute \src "libresoc.v:178859.9-178859.17"
+ attribute \src "libresoc.v:178391.9-178391.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10743 $5\wr_detect$4[0:0]$10747
+ assign $1\wr_detect$4[0:0]$10674 $5\wr_detect$4[0:0]$10678
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10744 1'1
+ assign $2\wr_detect$4[0:0]$10675 1'1
case
- assign $2\wr_detect$4[0:0]$10744 1'0
+ assign $2\wr_detect$4[0:0]$10675 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10745 1'1
+ assign $3\wr_detect$4[0:0]$10676 1'1
case
- assign $3\wr_detect$4[0:0]$10745 $2\wr_detect$4[0:0]$10744
+ assign $3\wr_detect$4[0:0]$10676 $2\wr_detect$4[0:0]$10675
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10746 1'1
+ assign $4\wr_detect$4[0:0]$10677 1'1
case
- assign $4\wr_detect$4[0:0]$10746 $3\wr_detect$4[0:0]$10745
+ assign $4\wr_detect$4[0:0]$10677 $3\wr_detect$4[0:0]$10676
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10747 1'1
+ assign $5\wr_detect$4[0:0]$10678 1'1
case
- assign $5\wr_detect$4[0:0]$10747 $4\wr_detect$4[0:0]$10746
+ assign $5\wr_detect$4[0:0]$10678 $4\wr_detect$4[0:0]$10677
end
case
- assign $1\wr_detect$4[0:0]$10743 1'0
+ assign $1\wr_detect$4[0:0]$10674 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10742
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10673
end
- attribute \src "libresoc.v:178894.3-178939.6"
- process $proc$libresoc.v:178894$10748
+ attribute \src "libresoc.v:178426.3-178471.6"
+ process $proc$libresoc.v:178426$10679
assign { } { }
assign { } { }
assign { } { }
- assign $0\src30__data_o$next[1:0]$10749 $7\src30__data_o$next[1:0]$10756
- attribute \src "libresoc.v:178895.5-178895.29"
+ assign $0\src30__data_o$next[1:0]$10680 $7\src30__data_o$next[1:0]$10687
+ attribute \src "libresoc.v:178427.5-178427.29"
switch \initial
- attribute \src "libresoc.v:178895.9-178895.17"
+ attribute \src "libresoc.v:178427.9-178427.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src30__data_o$next[1:0]$10750 $6\src30__data_o$next[1:0]$10755
+ assign $1\src30__data_o$next[1:0]$10681 $6\src30__data_o$next[1:0]$10686
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src30__data_o$next[1:0]$10751 \dest10__data_i
+ assign $2\src30__data_o$next[1:0]$10682 \dest10__data_i
case
- assign $2\src30__data_o$next[1:0]$10751 2'00
+ assign $2\src30__data_o$next[1:0]$10682 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src30__data_o$next[1:0]$10752 \dest20__data_i
+ assign $3\src30__data_o$next[1:0]$10683 \dest20__data_i
case
- assign $3\src30__data_o$next[1:0]$10752 $2\src30__data_o$next[1:0]$10751
+ assign $3\src30__data_o$next[1:0]$10683 $2\src30__data_o$next[1:0]$10682
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src30__data_o$next[1:0]$10753 \dest30__data_i
+ assign $4\src30__data_o$next[1:0]$10684 \dest30__data_i
case
- assign $4\src30__data_o$next[1:0]$10753 $3\src30__data_o$next[1:0]$10752
+ assign $4\src30__data_o$next[1:0]$10684 $3\src30__data_o$next[1:0]$10683
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src30__data_o$next[1:0]$10754 \w0__data_i
+ assign $5\src30__data_o$next[1:0]$10685 \w0__data_i
case
- assign $5\src30__data_o$next[1:0]$10754 $4\src30__data_o$next[1:0]$10753
+ assign $5\src30__data_o$next[1:0]$10685 $4\src30__data_o$next[1:0]$10684
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src30__data_o$next[1:0]$10755 \reg
+ assign $6\src30__data_o$next[1:0]$10686 \reg
case
- assign $6\src30__data_o$next[1:0]$10755 $5\src30__data_o$next[1:0]$10754
+ assign $6\src30__data_o$next[1:0]$10686 $5\src30__data_o$next[1:0]$10685
end
case
- assign $1\src30__data_o$next[1:0]$10750 2'00
+ assign $1\src30__data_o$next[1:0]$10681 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src30__data_o$next[1:0]$10756 2'00
+ assign $7\src30__data_o$next[1:0]$10687 2'00
case
- assign $7\src30__data_o$next[1:0]$10756 $1\src30__data_o$next[1:0]$10750
+ assign $7\src30__data_o$next[1:0]$10687 $1\src30__data_o$next[1:0]$10681
end
sync always
- update \src30__data_o$next $0\src30__data_o$next[1:0]$10749
+ update \src30__data_o$next $0\src30__data_o$next[1:0]$10680
end
- attribute \src "libresoc.v:178940.3-178975.6"
- process $proc$libresoc.v:178940$10757
+ attribute \src "libresoc.v:178472.3-178507.6"
+ process $proc$libresoc.v:178472$10688
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10758 $1\wr_detect$7[0:0]$10759
- attribute \src "libresoc.v:178941.5-178941.29"
+ assign $0\wr_detect$7[0:0]$10689 $1\wr_detect$7[0:0]$10690
+ attribute \src "libresoc.v:178473.5-178473.29"
switch \initial
- attribute \src "libresoc.v:178941.9-178941.17"
+ attribute \src "libresoc.v:178473.9-178473.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10759 $5\wr_detect$7[0:0]$10763
+ assign $1\wr_detect$7[0:0]$10690 $5\wr_detect$7[0:0]$10694
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10760 1'1
+ assign $2\wr_detect$7[0:0]$10691 1'1
case
- assign $2\wr_detect$7[0:0]$10760 1'0
+ assign $2\wr_detect$7[0:0]$10691 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10761 1'1
+ assign $3\wr_detect$7[0:0]$10692 1'1
case
- assign $3\wr_detect$7[0:0]$10761 $2\wr_detect$7[0:0]$10760
+ assign $3\wr_detect$7[0:0]$10692 $2\wr_detect$7[0:0]$10691
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10762 1'1
+ assign $4\wr_detect$7[0:0]$10693 1'1
case
- assign $4\wr_detect$7[0:0]$10762 $3\wr_detect$7[0:0]$10761
+ assign $4\wr_detect$7[0:0]$10693 $3\wr_detect$7[0:0]$10692
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$10763 1'1
+ assign $5\wr_detect$7[0:0]$10694 1'1
case
- assign $5\wr_detect$7[0:0]$10763 $4\wr_detect$7[0:0]$10762
+ assign $5\wr_detect$7[0:0]$10694 $4\wr_detect$7[0:0]$10693
end
case
- assign $1\wr_detect$7[0:0]$10759 1'0
+ assign $1\wr_detect$7[0:0]$10690 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10758
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10689
end
- attribute \src "libresoc.v:178976.3-179021.6"
- process $proc$libresoc.v:178976$10764
+ attribute \src "libresoc.v:178508.3-178553.6"
+ process $proc$libresoc.v:178508$10695
assign { } { }
assign { } { }
assign { } { }
- assign $0\r0__data_o$next[1:0]$10765 $7\r0__data_o$next[1:0]$10772
- attribute \src "libresoc.v:178977.5-178977.29"
+ assign $0\r0__data_o$next[1:0]$10696 $7\r0__data_o$next[1:0]$10703
+ attribute \src "libresoc.v:178509.5-178509.29"
switch \initial
- attribute \src "libresoc.v:178977.9-178977.17"
+ attribute \src "libresoc.v:178509.9-178509.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r0__data_o$next[1:0]$10766 $6\r0__data_o$next[1:0]$10771
+ assign $1\r0__data_o$next[1:0]$10697 $6\r0__data_o$next[1:0]$10702
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r0__data_o$next[1:0]$10767 \dest10__data_i
+ assign $2\r0__data_o$next[1:0]$10698 \dest10__data_i
case
- assign $2\r0__data_o$next[1:0]$10767 2'00
+ assign $2\r0__data_o$next[1:0]$10698 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r0__data_o$next[1:0]$10768 \dest20__data_i
+ assign $3\r0__data_o$next[1:0]$10699 \dest20__data_i
case
- assign $3\r0__data_o$next[1:0]$10768 $2\r0__data_o$next[1:0]$10767
+ assign $3\r0__data_o$next[1:0]$10699 $2\r0__data_o$next[1:0]$10698
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r0__data_o$next[1:0]$10769 \dest30__data_i
+ assign $4\r0__data_o$next[1:0]$10700 \dest30__data_i
case
- assign $4\r0__data_o$next[1:0]$10769 $3\r0__data_o$next[1:0]$10768
+ assign $4\r0__data_o$next[1:0]$10700 $3\r0__data_o$next[1:0]$10699
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r0__data_o$next[1:0]$10770 \w0__data_i
+ assign $5\r0__data_o$next[1:0]$10701 \w0__data_i
case
- assign $5\r0__data_o$next[1:0]$10770 $4\r0__data_o$next[1:0]$10769
+ assign $5\r0__data_o$next[1:0]$10701 $4\r0__data_o$next[1:0]$10700
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r0__data_o$next[1:0]$10771 \reg
+ assign $6\r0__data_o$next[1:0]$10702 \reg
case
- assign $6\r0__data_o$next[1:0]$10771 $5\r0__data_o$next[1:0]$10770
+ assign $6\r0__data_o$next[1:0]$10702 $5\r0__data_o$next[1:0]$10701
end
case
- assign $1\r0__data_o$next[1:0]$10766 2'00
+ assign $1\r0__data_o$next[1:0]$10697 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r0__data_o$next[1:0]$10772 2'00
+ assign $7\r0__data_o$next[1:0]$10703 2'00
case
- assign $7\r0__data_o$next[1:0]$10772 $1\r0__data_o$next[1:0]$10766
+ assign $7\r0__data_o$next[1:0]$10703 $1\r0__data_o$next[1:0]$10697
end
sync always
- update \r0__data_o$next $0\r0__data_o$next[1:0]$10765
+ update \r0__data_o$next $0\r0__data_o$next[1:0]$10696
end
- attribute \src "libresoc.v:179022.3-179057.6"
- process $proc$libresoc.v:179022$10773
+ attribute \src "libresoc.v:178554.3-178589.6"
+ process $proc$libresoc.v:178554$10704
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10774 $1\wr_detect$10[0:0]$10775
- attribute \src "libresoc.v:179023.5-179023.29"
+ assign $0\wr_detect$10[0:0]$10705 $1\wr_detect$10[0:0]$10706
+ attribute \src "libresoc.v:178555.5-178555.29"
switch \initial
- attribute \src "libresoc.v:179023.9-179023.17"
+ attribute \src "libresoc.v:178555.9-178555.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10775 $5\wr_detect$10[0:0]$10779
+ assign $1\wr_detect$10[0:0]$10706 $5\wr_detect$10[0:0]$10710
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10776 1'1
+ assign $2\wr_detect$10[0:0]$10707 1'1
case
- assign $2\wr_detect$10[0:0]$10776 1'0
+ assign $2\wr_detect$10[0:0]$10707 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10777 1'1
+ assign $3\wr_detect$10[0:0]$10708 1'1
case
- assign $3\wr_detect$10[0:0]$10777 $2\wr_detect$10[0:0]$10776
+ assign $3\wr_detect$10[0:0]$10708 $2\wr_detect$10[0:0]$10707
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10778 1'1
+ assign $4\wr_detect$10[0:0]$10709 1'1
case
- assign $4\wr_detect$10[0:0]$10778 $3\wr_detect$10[0:0]$10777
+ assign $4\wr_detect$10[0:0]$10709 $3\wr_detect$10[0:0]$10708
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$10779 1'1
+ assign $5\wr_detect$10[0:0]$10710 1'1
case
- assign $5\wr_detect$10[0:0]$10779 $4\wr_detect$10[0:0]$10778
+ assign $5\wr_detect$10[0:0]$10710 $4\wr_detect$10[0:0]$10709
end
case
- assign $1\wr_detect$10[0:0]$10775 1'0
+ assign $1\wr_detect$10[0:0]$10706 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10774
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10705
end
- attribute \src "libresoc.v:179058.3-179090.6"
- process $proc$libresoc.v:179058$10780
+ attribute \src "libresoc.v:178590.3-178622.6"
+ process $proc$libresoc.v:178590$10711
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$10781 $5\reg$next[1:0]$10786
- attribute \src "libresoc.v:179059.5-179059.29"
+ assign $0\reg$next[1:0]$10712 $5\reg$next[1:0]$10717
+ attribute \src "libresoc.v:178591.5-178591.29"
switch \initial
- attribute \src "libresoc.v:179059.9-179059.17"
+ attribute \src "libresoc.v:178591.9-178591.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$10782 \dest10__data_i
+ assign $1\reg$next[1:0]$10713 \dest10__data_i
case
- assign $1\reg$next[1:0]$10782 \reg
+ assign $1\reg$next[1:0]$10713 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$10783 \dest20__data_i
+ assign $2\reg$next[1:0]$10714 \dest20__data_i
case
- assign $2\reg$next[1:0]$10783 $1\reg$next[1:0]$10782
+ assign $2\reg$next[1:0]$10714 $1\reg$next[1:0]$10713
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$10784 \dest30__data_i
+ assign $3\reg$next[1:0]$10715 \dest30__data_i
case
- assign $3\reg$next[1:0]$10784 $2\reg$next[1:0]$10783
+ assign $3\reg$next[1:0]$10715 $2\reg$next[1:0]$10714
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$10785 \w0__data_i
+ assign $4\reg$next[1:0]$10716 \w0__data_i
case
- assign $4\reg$next[1:0]$10785 $3\reg$next[1:0]$10784
+ assign $4\reg$next[1:0]$10716 $3\reg$next[1:0]$10715
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$10786 2'00
+ assign $5\reg$next[1:0]$10717 2'00
case
- assign $5\reg$next[1:0]$10786 $4\reg$next[1:0]$10785
+ assign $5\reg$next[1:0]$10717 $4\reg$next[1:0]$10716
end
sync always
- update \reg$next $0\reg$next[1:0]$10781
+ update \reg$next $0\reg$next[1:0]$10712
end
- connect \$9 $not$libresoc.v:178716$10713_Y
- connect \$1 $not$libresoc.v:178717$10714_Y
- connect \$3 $not$libresoc.v:178718$10715_Y
- connect \$6 $not$libresoc.v:178719$10716_Y
+ connect \$9 $not$libresoc.v:178248$10644_Y
+ connect \$1 $not$libresoc.v:178249$10645_Y
+ connect \$3 $not$libresoc.v:178250$10646_Y
+ connect \$6 $not$libresoc.v:178251$10647_Y
end
-attribute \src "libresoc.v:179095.1-179444.10"
+attribute \src "libresoc.v:178627.1-178976.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0"
attribute \generator "nMigen"
module \reg_0$135
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $0\cia0__data_o$next[63:0]$10801
- attribute \src "libresoc.v:179163.3-179164.41"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $0\cia0__data_o$next[63:0]$10732
+ attribute \src "libresoc.v:178695.3-178696.41"
wire width 64 $0\cia0__data_o[63:0]
- attribute \src "libresoc.v:179096.7-179096.20"
+ attribute \src "libresoc.v:178628.7-178628.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $0\msr0__data_o$next[63:0]$10811
- attribute \src "libresoc.v:179161.3-179162.41"
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $0\msr0__data_o$next[63:0]$10742
+ attribute \src "libresoc.v:178693.3-178694.41"
wire width 64 $0\msr0__data_o[63:0]
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $0\reg$next[63:0]$10843
- attribute \src "libresoc.v:179157.3-179158.25"
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $0\reg$next[63:0]$10774
+ attribute \src "libresoc.v:178689.3-178690.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $0\sv0__data_o$next[63:0]$10827
- attribute \src "libresoc.v:179159.3-179160.39"
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $0\sv0__data_o$next[63:0]$10758
+ attribute \src "libresoc.v:178691.3-178692.39"
wire width 64 $0\sv0__data_o[63:0]
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $0\wr_detect$4[0:0]$10820
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $0\wr_detect$7[0:0]$10836
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $0\wr_detect$4[0:0]$10751
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $0\wr_detect$7[0:0]$10767
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $1\cia0__data_o$next[63:0]$10802
- attribute \src "libresoc.v:179105.14-179105.49"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $1\cia0__data_o$next[63:0]$10733
+ attribute \src "libresoc.v:178637.14-178637.49"
wire width 64 $1\cia0__data_o[63:0]
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $1\msr0__data_o$next[63:0]$10812
- attribute \src "libresoc.v:179122.14-179122.49"
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $1\msr0__data_o$next[63:0]$10743
+ attribute \src "libresoc.v:178654.14-178654.49"
wire width 64 $1\msr0__data_o[63:0]
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $1\reg$next[63:0]$10844
- attribute \src "libresoc.v:179134.14-179134.42"
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $1\reg$next[63:0]$10775
+ attribute \src "libresoc.v:178666.14-178666.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $1\sv0__data_o$next[63:0]$10828
- attribute \src "libresoc.v:179141.14-179141.48"
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $1\sv0__data_o$next[63:0]$10759
+ attribute \src "libresoc.v:178673.14-178673.48"
wire width 64 $1\sv0__data_o[63:0]
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $1\wr_detect$4[0:0]$10821
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $1\wr_detect$7[0:0]$10837
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $1\wr_detect$4[0:0]$10752
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $1\wr_detect$7[0:0]$10768
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $2\cia0__data_o$next[63:0]$10803
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $2\msr0__data_o$next[63:0]$10813
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $2\reg$next[63:0]$10845
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $2\sv0__data_o$next[63:0]$10829
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $2\wr_detect$4[0:0]$10822
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $2\wr_detect$7[0:0]$10838
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $2\cia0__data_o$next[63:0]$10734
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $2\msr0__data_o$next[63:0]$10744
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $2\reg$next[63:0]$10776
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $2\sv0__data_o$next[63:0]$10760
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $2\wr_detect$4[0:0]$10753
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $2\wr_detect$7[0:0]$10769
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $3\cia0__data_o$next[63:0]$10804
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $3\msr0__data_o$next[63:0]$10814
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $3\reg$next[63:0]$10846
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $3\sv0__data_o$next[63:0]$10830
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $3\wr_detect$4[0:0]$10823
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $3\wr_detect$7[0:0]$10839
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $3\cia0__data_o$next[63:0]$10735
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $3\msr0__data_o$next[63:0]$10745
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $3\reg$next[63:0]$10777
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $3\sv0__data_o$next[63:0]$10761
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $3\wr_detect$4[0:0]$10754
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $3\wr_detect$7[0:0]$10770
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $4\cia0__data_o$next[63:0]$10805
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $4\msr0__data_o$next[63:0]$10815
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $4\reg$next[63:0]$10847
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $4\sv0__data_o$next[63:0]$10831
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $4\wr_detect$4[0:0]$10824
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $4\wr_detect$7[0:0]$10840
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $4\cia0__data_o$next[63:0]$10736
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $4\msr0__data_o$next[63:0]$10746
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $4\reg$next[63:0]$10778
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $4\sv0__data_o$next[63:0]$10762
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $4\wr_detect$4[0:0]$10755
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $4\wr_detect$7[0:0]$10771
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $5\cia0__data_o$next[63:0]$10806
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $5\msr0__data_o$next[63:0]$10816
- attribute \src "libresoc.v:179411.3-179443.6"
- wire width 64 $5\reg$next[63:0]$10848
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $5\sv0__data_o$next[63:0]$10832
- attribute \src "libresoc.v:179293.3-179328.6"
- wire $5\wr_detect$4[0:0]$10825
- attribute \src "libresoc.v:179375.3-179410.6"
- wire $5\wr_detect$7[0:0]$10841
- attribute \src "libresoc.v:179211.3-179246.6"
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $5\cia0__data_o$next[63:0]$10737
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $5\msr0__data_o$next[63:0]$10747
+ attribute \src "libresoc.v:178943.3-178975.6"
+ wire width 64 $5\reg$next[63:0]$10779
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $5\sv0__data_o$next[63:0]$10763
+ attribute \src "libresoc.v:178825.3-178860.6"
+ wire $5\wr_detect$4[0:0]$10756
+ attribute \src "libresoc.v:178907.3-178942.6"
+ wire $5\wr_detect$7[0:0]$10772
+ attribute \src "libresoc.v:178743.3-178778.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $6\cia0__data_o$next[63:0]$10807
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $6\msr0__data_o$next[63:0]$10817
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $6\sv0__data_o$next[63:0]$10833
- attribute \src "libresoc.v:179165.3-179210.6"
- wire width 64 $7\cia0__data_o$next[63:0]$10808
- attribute \src "libresoc.v:179247.3-179292.6"
- wire width 64 $7\msr0__data_o$next[63:0]$10818
- attribute \src "libresoc.v:179329.3-179374.6"
- wire width 64 $7\sv0__data_o$next[63:0]$10834
- attribute \src "libresoc.v:179154.17-179154.100"
- wire $not$libresoc.v:179154$10793_Y
- attribute \src "libresoc.v:179155.17-179155.103"
- wire $not$libresoc.v:179155$10794_Y
- attribute \src "libresoc.v:179156.17-179156.103"
- wire $not$libresoc.v:179156$10795_Y
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $6\cia0__data_o$next[63:0]$10738
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $6\msr0__data_o$next[63:0]$10748
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $6\sv0__data_o$next[63:0]$10764
+ attribute \src "libresoc.v:178697.3-178742.6"
+ wire width 64 $7\cia0__data_o$next[63:0]$10739
+ attribute \src "libresoc.v:178779.3-178824.6"
+ wire width 64 $7\msr0__data_o$next[63:0]$10749
+ attribute \src "libresoc.v:178861.3-178906.6"
+ wire width 64 $7\sv0__data_o$next[63:0]$10765
+ attribute \src "libresoc.v:178686.17-178686.100"
+ wire $not$libresoc.v:178686$10724_Y
+ attribute \src "libresoc.v:178687.17-178687.103"
+ wire $not$libresoc.v:178687$10725_Y
+ attribute \src "libresoc.v:178688.17-178688.103"
+ wire $not$libresoc.v:178688$10726_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia0__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia0__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr10__wen
- attribute \src "libresoc.v:179096.7-179096.15"
+ attribute \src "libresoc.v:178628.7-178628.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr0__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179154$10793
+ cell $not $not$libresoc.v:178686$10724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:179154$10793_Y
+ connect \Y $not$libresoc.v:178686$10724_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179155$10794
+ cell $not $not$libresoc.v:178687$10725
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:179155$10794_Y
+ connect \Y $not$libresoc.v:178687$10725_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179156$10795
+ cell $not $not$libresoc.v:178688$10726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:179156$10795_Y
+ connect \Y $not$libresoc.v:178688$10726_Y
end
- attribute \src "libresoc.v:179096.7-179096.20"
- process $proc$libresoc.v:179096$10849
+ attribute \src "libresoc.v:178628.7-178628.20"
+ process $proc$libresoc.v:178628$10780
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:179105.14-179105.49"
- process $proc$libresoc.v:179105$10850
+ attribute \src "libresoc.v:178637.14-178637.49"
+ process $proc$libresoc.v:178637$10781
assign { } { }
assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia0__data_o $1\cia0__data_o[63:0]
end
- attribute \src "libresoc.v:179122.14-179122.49"
- process $proc$libresoc.v:179122$10851
+ attribute \src "libresoc.v:178654.14-178654.49"
+ process $proc$libresoc.v:178654$10782
assign { } { }
assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr0__data_o $1\msr0__data_o[63:0]
end
- attribute \src "libresoc.v:179134.14-179134.42"
- process $proc$libresoc.v:179134$10852
+ attribute \src "libresoc.v:178666.14-178666.42"
+ process $proc$libresoc.v:178666$10783
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:179141.14-179141.48"
- process $proc$libresoc.v:179141$10853
+ attribute \src "libresoc.v:178673.14-178673.48"
+ process $proc$libresoc.v:178673$10784
assign { } { }
assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv0__data_o $1\sv0__data_o[63:0]
end
- attribute \src "libresoc.v:179157.3-179158.25"
- process $proc$libresoc.v:179157$10796
+ attribute \src "libresoc.v:178689.3-178690.25"
+ process $proc$libresoc.v:178689$10727
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:179159.3-179160.39"
- process $proc$libresoc.v:179159$10797
+ attribute \src "libresoc.v:178691.3-178692.39"
+ process $proc$libresoc.v:178691$10728
assign { } { }
assign $0\sv0__data_o[63:0] \sv0__data_o$next
sync posedge \coresync_clk
update \sv0__data_o $0\sv0__data_o[63:0]
end
- attribute \src "libresoc.v:179161.3-179162.41"
- process $proc$libresoc.v:179161$10798
+ attribute \src "libresoc.v:178693.3-178694.41"
+ process $proc$libresoc.v:178693$10729
assign { } { }
assign $0\msr0__data_o[63:0] \msr0__data_o$next
sync posedge \coresync_clk
update \msr0__data_o $0\msr0__data_o[63:0]
end
- attribute \src "libresoc.v:179163.3-179164.41"
- process $proc$libresoc.v:179163$10799
+ attribute \src "libresoc.v:178695.3-178696.41"
+ process $proc$libresoc.v:178695$10730
assign { } { }
assign $0\cia0__data_o[63:0] \cia0__data_o$next
sync posedge \coresync_clk
update \cia0__data_o $0\cia0__data_o[63:0]
end
- attribute \src "libresoc.v:179165.3-179210.6"
- process $proc$libresoc.v:179165$10800
+ attribute \src "libresoc.v:178697.3-178742.6"
+ process $proc$libresoc.v:178697$10731
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia0__data_o$next[63:0]$10801 $7\cia0__data_o$next[63:0]$10808
- attribute \src "libresoc.v:179166.5-179166.29"
+ assign $0\cia0__data_o$next[63:0]$10732 $7\cia0__data_o$next[63:0]$10739
+ attribute \src "libresoc.v:178698.5-178698.29"
switch \initial
- attribute \src "libresoc.v:179166.9-179166.17"
+ attribute \src "libresoc.v:178698.9-178698.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia0__data_o$next[63:0]$10802 $6\cia0__data_o$next[63:0]$10807
+ assign $1\cia0__data_o$next[63:0]$10733 $6\cia0__data_o$next[63:0]$10738
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia0__data_o$next[63:0]$10803 \nia0__data_i
+ assign $2\cia0__data_o$next[63:0]$10734 \nia0__data_i
case
- assign $2\cia0__data_o$next[63:0]$10803 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia0__data_o$next[63:0]$10734 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia0__data_o$next[63:0]$10804 \msr0__data_i
+ assign $3\cia0__data_o$next[63:0]$10735 \msr0__data_i
case
- assign $3\cia0__data_o$next[63:0]$10804 $2\cia0__data_o$next[63:0]$10803
+ assign $3\cia0__data_o$next[63:0]$10735 $2\cia0__data_o$next[63:0]$10734
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia0__data_o$next[63:0]$10805 \sv0__data_i
+ assign $4\cia0__data_o$next[63:0]$10736 \sv0__data_i
case
- assign $4\cia0__data_o$next[63:0]$10805 $3\cia0__data_o$next[63:0]$10804
+ assign $4\cia0__data_o$next[63:0]$10736 $3\cia0__data_o$next[63:0]$10735
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia0__data_o$next[63:0]$10806 \d_wr10__data_i
+ assign $5\cia0__data_o$next[63:0]$10737 \d_wr10__data_i
case
- assign $5\cia0__data_o$next[63:0]$10806 $4\cia0__data_o$next[63:0]$10805
+ assign $5\cia0__data_o$next[63:0]$10737 $4\cia0__data_o$next[63:0]$10736
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia0__data_o$next[63:0]$10807 \reg
+ assign $6\cia0__data_o$next[63:0]$10738 \reg
case
- assign $6\cia0__data_o$next[63:0]$10807 $5\cia0__data_o$next[63:0]$10806
+ assign $6\cia0__data_o$next[63:0]$10738 $5\cia0__data_o$next[63:0]$10737
end
case
- assign $1\cia0__data_o$next[63:0]$10802 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia0__data_o$next[63:0]$10733 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia0__data_o$next[63:0]$10808 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia0__data_o$next[63:0]$10739 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia0__data_o$next[63:0]$10808 $1\cia0__data_o$next[63:0]$10802
+ assign $7\cia0__data_o$next[63:0]$10739 $1\cia0__data_o$next[63:0]$10733
end
sync always
- update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10801
+ update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10732
end
- attribute \src "libresoc.v:179211.3-179246.6"
- process $proc$libresoc.v:179211$10809
+ attribute \src "libresoc.v:178743.3-178778.6"
+ process $proc$libresoc.v:178743$10740
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:179212.5-179212.29"
+ attribute \src "libresoc.v:178744.5-178744.29"
switch \initial
- attribute \src "libresoc.v:179212.9-179212.17"
+ attribute \src "libresoc.v:178744.9-178744.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:179247.3-179292.6"
- process $proc$libresoc.v:179247$10810
+ attribute \src "libresoc.v:178779.3-178824.6"
+ process $proc$libresoc.v:178779$10741
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr0__data_o$next[63:0]$10811 $7\msr0__data_o$next[63:0]$10818
- attribute \src "libresoc.v:179248.5-179248.29"
+ assign $0\msr0__data_o$next[63:0]$10742 $7\msr0__data_o$next[63:0]$10749
+ attribute \src "libresoc.v:178780.5-178780.29"
switch \initial
- attribute \src "libresoc.v:179248.9-179248.17"
+ attribute \src "libresoc.v:178780.9-178780.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr0__data_o$next[63:0]$10812 $6\msr0__data_o$next[63:0]$10817
+ assign $1\msr0__data_o$next[63:0]$10743 $6\msr0__data_o$next[63:0]$10748
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr0__data_o$next[63:0]$10813 \nia0__data_i
+ assign $2\msr0__data_o$next[63:0]$10744 \nia0__data_i
case
- assign $2\msr0__data_o$next[63:0]$10813 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr0__data_o$next[63:0]$10744 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr0__data_o$next[63:0]$10814 \msr0__data_i
+ assign $3\msr0__data_o$next[63:0]$10745 \msr0__data_i
case
- assign $3\msr0__data_o$next[63:0]$10814 $2\msr0__data_o$next[63:0]$10813
+ assign $3\msr0__data_o$next[63:0]$10745 $2\msr0__data_o$next[63:0]$10744
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr0__data_o$next[63:0]$10815 \sv0__data_i
+ assign $4\msr0__data_o$next[63:0]$10746 \sv0__data_i
case
- assign $4\msr0__data_o$next[63:0]$10815 $3\msr0__data_o$next[63:0]$10814
+ assign $4\msr0__data_o$next[63:0]$10746 $3\msr0__data_o$next[63:0]$10745
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr0__data_o$next[63:0]$10816 \d_wr10__data_i
+ assign $5\msr0__data_o$next[63:0]$10747 \d_wr10__data_i
case
- assign $5\msr0__data_o$next[63:0]$10816 $4\msr0__data_o$next[63:0]$10815
+ assign $5\msr0__data_o$next[63:0]$10747 $4\msr0__data_o$next[63:0]$10746
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr0__data_o$next[63:0]$10817 \reg
+ assign $6\msr0__data_o$next[63:0]$10748 \reg
case
- assign $6\msr0__data_o$next[63:0]$10817 $5\msr0__data_o$next[63:0]$10816
+ assign $6\msr0__data_o$next[63:0]$10748 $5\msr0__data_o$next[63:0]$10747
end
case
- assign $1\msr0__data_o$next[63:0]$10812 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr0__data_o$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr0__data_o$next[63:0]$10749 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr0__data_o$next[63:0]$10818 $1\msr0__data_o$next[63:0]$10812
+ assign $7\msr0__data_o$next[63:0]$10749 $1\msr0__data_o$next[63:0]$10743
end
sync always
- update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10811
+ update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10742
end
- attribute \src "libresoc.v:179293.3-179328.6"
- process $proc$libresoc.v:179293$10819
+ attribute \src "libresoc.v:178825.3-178860.6"
+ process $proc$libresoc.v:178825$10750
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10820 $1\wr_detect$4[0:0]$10821
- attribute \src "libresoc.v:179294.5-179294.29"
+ assign $0\wr_detect$4[0:0]$10751 $1\wr_detect$4[0:0]$10752
+ attribute \src "libresoc.v:178826.5-178826.29"
switch \initial
- attribute \src "libresoc.v:179294.9-179294.17"
+ attribute \src "libresoc.v:178826.9-178826.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10821 $5\wr_detect$4[0:0]$10825
+ assign $1\wr_detect$4[0:0]$10752 $5\wr_detect$4[0:0]$10756
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10822 1'1
+ assign $2\wr_detect$4[0:0]$10753 1'1
case
- assign $2\wr_detect$4[0:0]$10822 1'0
+ assign $2\wr_detect$4[0:0]$10753 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10823 1'1
+ assign $3\wr_detect$4[0:0]$10754 1'1
case
- assign $3\wr_detect$4[0:0]$10823 $2\wr_detect$4[0:0]$10822
+ assign $3\wr_detect$4[0:0]$10754 $2\wr_detect$4[0:0]$10753
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10824 1'1
+ assign $4\wr_detect$4[0:0]$10755 1'1
case
- assign $4\wr_detect$4[0:0]$10824 $3\wr_detect$4[0:0]$10823
+ assign $4\wr_detect$4[0:0]$10755 $3\wr_detect$4[0:0]$10754
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10825 1'1
+ assign $5\wr_detect$4[0:0]$10756 1'1
case
- assign $5\wr_detect$4[0:0]$10825 $4\wr_detect$4[0:0]$10824
+ assign $5\wr_detect$4[0:0]$10756 $4\wr_detect$4[0:0]$10755
end
case
- assign $1\wr_detect$4[0:0]$10821 1'0
+ assign $1\wr_detect$4[0:0]$10752 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10820
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10751
end
- attribute \src "libresoc.v:179329.3-179374.6"
- process $proc$libresoc.v:179329$10826
+ attribute \src "libresoc.v:178861.3-178906.6"
+ process $proc$libresoc.v:178861$10757
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv0__data_o$next[63:0]$10827 $7\sv0__data_o$next[63:0]$10834
- attribute \src "libresoc.v:179330.5-179330.29"
+ assign $0\sv0__data_o$next[63:0]$10758 $7\sv0__data_o$next[63:0]$10765
+ attribute \src "libresoc.v:178862.5-178862.29"
switch \initial
- attribute \src "libresoc.v:179330.9-179330.17"
+ attribute \src "libresoc.v:178862.9-178862.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv0__data_o$next[63:0]$10828 $6\sv0__data_o$next[63:0]$10833
+ assign $1\sv0__data_o$next[63:0]$10759 $6\sv0__data_o$next[63:0]$10764
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv0__data_o$next[63:0]$10829 \nia0__data_i
+ assign $2\sv0__data_o$next[63:0]$10760 \nia0__data_i
case
- assign $2\sv0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv0__data_o$next[63:0]$10760 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv0__data_o$next[63:0]$10830 \msr0__data_i
+ assign $3\sv0__data_o$next[63:0]$10761 \msr0__data_i
case
- assign $3\sv0__data_o$next[63:0]$10830 $2\sv0__data_o$next[63:0]$10829
+ assign $3\sv0__data_o$next[63:0]$10761 $2\sv0__data_o$next[63:0]$10760
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv0__data_o$next[63:0]$10831 \sv0__data_i
+ assign $4\sv0__data_o$next[63:0]$10762 \sv0__data_i
case
- assign $4\sv0__data_o$next[63:0]$10831 $3\sv0__data_o$next[63:0]$10830
+ assign $4\sv0__data_o$next[63:0]$10762 $3\sv0__data_o$next[63:0]$10761
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv0__data_o$next[63:0]$10832 \d_wr10__data_i
+ assign $5\sv0__data_o$next[63:0]$10763 \d_wr10__data_i
case
- assign $5\sv0__data_o$next[63:0]$10832 $4\sv0__data_o$next[63:0]$10831
+ assign $5\sv0__data_o$next[63:0]$10763 $4\sv0__data_o$next[63:0]$10762
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv0__data_o$next[63:0]$10833 \reg
+ assign $6\sv0__data_o$next[63:0]$10764 \reg
case
- assign $6\sv0__data_o$next[63:0]$10833 $5\sv0__data_o$next[63:0]$10832
+ assign $6\sv0__data_o$next[63:0]$10764 $5\sv0__data_o$next[63:0]$10763
end
case
- assign $1\sv0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv0__data_o$next[63:0]$10765 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv0__data_o$next[63:0]$10834 $1\sv0__data_o$next[63:0]$10828
+ assign $7\sv0__data_o$next[63:0]$10765 $1\sv0__data_o$next[63:0]$10759
end
sync always
- update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10827
+ update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10758
end
- attribute \src "libresoc.v:179375.3-179410.6"
- process $proc$libresoc.v:179375$10835
+ attribute \src "libresoc.v:178907.3-178942.6"
+ process $proc$libresoc.v:178907$10766
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10836 $1\wr_detect$7[0:0]$10837
- attribute \src "libresoc.v:179376.5-179376.29"
+ assign $0\wr_detect$7[0:0]$10767 $1\wr_detect$7[0:0]$10768
+ attribute \src "libresoc.v:178908.5-178908.29"
switch \initial
- attribute \src "libresoc.v:179376.9-179376.17"
+ attribute \src "libresoc.v:178908.9-178908.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10837 $5\wr_detect$7[0:0]$10841
+ assign $1\wr_detect$7[0:0]$10768 $5\wr_detect$7[0:0]$10772
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10838 1'1
+ assign $2\wr_detect$7[0:0]$10769 1'1
case
- assign $2\wr_detect$7[0:0]$10838 1'0
+ assign $2\wr_detect$7[0:0]$10769 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10839 1'1
+ assign $3\wr_detect$7[0:0]$10770 1'1
case
- assign $3\wr_detect$7[0:0]$10839 $2\wr_detect$7[0:0]$10838
+ assign $3\wr_detect$7[0:0]$10770 $2\wr_detect$7[0:0]$10769
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10840 1'1
+ assign $4\wr_detect$7[0:0]$10771 1'1
case
- assign $4\wr_detect$7[0:0]$10840 $3\wr_detect$7[0:0]$10839
+ assign $4\wr_detect$7[0:0]$10771 $3\wr_detect$7[0:0]$10770
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$10841 1'1
+ assign $5\wr_detect$7[0:0]$10772 1'1
case
- assign $5\wr_detect$7[0:0]$10841 $4\wr_detect$7[0:0]$10840
+ assign $5\wr_detect$7[0:0]$10772 $4\wr_detect$7[0:0]$10771
end
case
- assign $1\wr_detect$7[0:0]$10837 1'0
+ assign $1\wr_detect$7[0:0]$10768 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10836
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10767
end
- attribute \src "libresoc.v:179411.3-179443.6"
- process $proc$libresoc.v:179411$10842
+ attribute \src "libresoc.v:178943.3-178975.6"
+ process $proc$libresoc.v:178943$10773
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$10843 $5\reg$next[63:0]$10848
- attribute \src "libresoc.v:179412.5-179412.29"
+ assign $0\reg$next[63:0]$10774 $5\reg$next[63:0]$10779
+ attribute \src "libresoc.v:178944.5-178944.29"
switch \initial
- attribute \src "libresoc.v:179412.9-179412.17"
+ attribute \src "libresoc.v:178944.9-178944.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$10844 \nia0__data_i
+ assign $1\reg$next[63:0]$10775 \nia0__data_i
case
- assign $1\reg$next[63:0]$10844 \reg
+ assign $1\reg$next[63:0]$10775 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$10845 \msr0__data_i
+ assign $2\reg$next[63:0]$10776 \msr0__data_i
case
- assign $2\reg$next[63:0]$10845 $1\reg$next[63:0]$10844
+ assign $2\reg$next[63:0]$10776 $1\reg$next[63:0]$10775
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$10846 \sv0__data_i
+ assign $3\reg$next[63:0]$10777 \sv0__data_i
case
- assign $3\reg$next[63:0]$10846 $2\reg$next[63:0]$10845
+ assign $3\reg$next[63:0]$10777 $2\reg$next[63:0]$10776
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$10847 \d_wr10__data_i
+ assign $4\reg$next[63:0]$10778 \d_wr10__data_i
case
- assign $4\reg$next[63:0]$10847 $3\reg$next[63:0]$10846
+ assign $4\reg$next[63:0]$10778 $3\reg$next[63:0]$10777
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$10848 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$10848 $4\reg$next[63:0]$10847
+ assign $5\reg$next[63:0]$10779 $4\reg$next[63:0]$10778
end
sync always
- update \reg$next $0\reg$next[63:0]$10843
+ update \reg$next $0\reg$next[63:0]$10774
end
- connect \$1 $not$libresoc.v:179154$10793_Y
- connect \$3 $not$libresoc.v:179155$10794_Y
- connect \$6 $not$libresoc.v:179156$10795_Y
+ connect \$1 $not$libresoc.v:178686$10724_Y
+ connect \$3 $not$libresoc.v:178687$10725_Y
+ connect \$6 $not$libresoc.v:178688$10726_Y
end
-attribute \src "libresoc.v:179448.1-180003.10"
+attribute \src "libresoc.v:178980.1-179451.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1"
attribute \generator "nMigen"
module \reg_1
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $0\cr_pred1__data_o$next[3:0]$10868
- attribute \src "libresoc.v:179554.3-179555.49"
- wire width 4 $0\cr_pred1__data_o[3:0]
- attribute \src "libresoc.v:179449.7-179449.20"
+ attribute \src "libresoc.v:178981.7-178981.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $0\r1__data_o$next[3:0]$10939
- attribute \src "libresoc.v:179546.3-179547.37"
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $0\r1__data_o$next[3:0]$10840
+ attribute \src "libresoc.v:179066.3-179067.37"
wire width 4 $0\r1__data_o[3:0]
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $0\r21__data_o$next[3:0]$10877
- attribute \src "libresoc.v:179544.3-179545.39"
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $0\r21__data_o$next[3:0]$10854
+ attribute \src "libresoc.v:179064.3-179065.39"
wire width 4 $0\r21__data_o[3:0]
- attribute \src "libresoc.v:179696.3-179722.6"
- wire width 4 $0\reg$next[3:0]$10891
- attribute \src "libresoc.v:179542.3-179543.25"
+ attribute \src "libresoc.v:179144.3-179170.6"
+ wire width 4 $0\reg$next[3:0]$10806
+ attribute \src "libresoc.v:179062.3-179063.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $0\src11__data_o$next[3:0]$10897
- attribute \src "libresoc.v:179552.3-179553.43"
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $0\src11__data_o$next[3:0]$10797
+ attribute \src "libresoc.v:179072.3-179073.43"
wire width 4 $0\src11__data_o[3:0]
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $0\src21__data_o$next[3:0]$10911
- attribute \src "libresoc.v:179550.3-179551.43"
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $0\src21__data_o$next[3:0]$10812
+ attribute \src "libresoc.v:179070.3-179071.43"
wire width 4 $0\src21__data_o[3:0]
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $0\src31__data_o$next[3:0]$10925
- attribute \src "libresoc.v:179548.3-179549.43"
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $0\src31__data_o$next[3:0]$10826
+ attribute \src "libresoc.v:179068.3-179069.43"
wire width 4 $0\src31__data_o[3:0]
- attribute \src "libresoc.v:179903.3-179932.6"
- wire $0\wr_detect$10[0:0]$10933
- attribute \src "libresoc.v:179973.3-180002.6"
- wire $0\wr_detect$13[0:0]$10947
- attribute \src "libresoc.v:179666.3-179695.6"
- wire $0\wr_detect$16[0:0]$10885
- attribute \src "libresoc.v:179763.3-179792.6"
- wire $0\wr_detect$4[0:0]$10905
- attribute \src "libresoc.v:179833.3-179862.6"
- wire $0\wr_detect$7[0:0]$10919
- attribute \src "libresoc.v:179596.3-179625.6"
+ attribute \src "libresoc.v:179351.3-179380.6"
+ wire $0\wr_detect$10[0:0]$10848
+ attribute \src "libresoc.v:179421.3-179450.6"
+ wire $0\wr_detect$13[0:0]$10862
+ attribute \src "libresoc.v:179211.3-179240.6"
+ wire $0\wr_detect$4[0:0]$10820
+ attribute \src "libresoc.v:179281.3-179310.6"
+ wire $0\wr_detect$7[0:0]$10834
+ attribute \src "libresoc.v:179114.3-179143.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $1\cr_pred1__data_o$next[3:0]$10869
- attribute \src "libresoc.v:179468.13-179468.36"
- wire width 4 $1\cr_pred1__data_o[3:0]
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $1\r1__data_o$next[3:0]$10940
- attribute \src "libresoc.v:179483.13-179483.30"
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $1\r1__data_o$next[3:0]$10841
+ attribute \src "libresoc.v:179006.13-179006.30"
wire width 4 $1\r1__data_o[3:0]
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $1\r21__data_o$next[3:0]$10878
- attribute \src "libresoc.v:179490.13-179490.31"
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $1\r21__data_o$next[3:0]$10855
+ attribute \src "libresoc.v:179013.13-179013.31"
wire width 4 $1\r21__data_o[3:0]
- attribute \src "libresoc.v:179696.3-179722.6"
- wire width 4 $1\reg$next[3:0]$10892
- attribute \src "libresoc.v:179496.13-179496.25"
+ attribute \src "libresoc.v:179144.3-179170.6"
+ wire width 4 $1\reg$next[3:0]$10807
+ attribute \src "libresoc.v:179019.13-179019.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $1\src11__data_o$next[3:0]$10898
- attribute \src "libresoc.v:179501.13-179501.33"
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $1\src11__data_o$next[3:0]$10798
+ attribute \src "libresoc.v:179024.13-179024.33"
wire width 4 $1\src11__data_o[3:0]
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $1\src21__data_o$next[3:0]$10912
- attribute \src "libresoc.v:179508.13-179508.33"
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $1\src21__data_o$next[3:0]$10813
+ attribute \src "libresoc.v:179031.13-179031.33"
wire width 4 $1\src21__data_o[3:0]
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $1\src31__data_o$next[3:0]$10926
- attribute \src "libresoc.v:179515.13-179515.33"
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $1\src31__data_o$next[3:0]$10827
+ attribute \src "libresoc.v:179038.13-179038.33"
wire width 4 $1\src31__data_o[3:0]
- attribute \src "libresoc.v:179903.3-179932.6"
- wire $1\wr_detect$10[0:0]$10934
- attribute \src "libresoc.v:179973.3-180002.6"
- wire $1\wr_detect$13[0:0]$10948
- attribute \src "libresoc.v:179666.3-179695.6"
- wire $1\wr_detect$16[0:0]$10886
- attribute \src "libresoc.v:179763.3-179792.6"
- wire $1\wr_detect$4[0:0]$10906
- attribute \src "libresoc.v:179833.3-179862.6"
- wire $1\wr_detect$7[0:0]$10920
- attribute \src "libresoc.v:179596.3-179625.6"
+ attribute \src "libresoc.v:179351.3-179380.6"
+ wire $1\wr_detect$10[0:0]$10849
+ attribute \src "libresoc.v:179421.3-179450.6"
+ wire $1\wr_detect$13[0:0]$10863
+ attribute \src "libresoc.v:179211.3-179240.6"
+ wire $1\wr_detect$4[0:0]$10821
+ attribute \src "libresoc.v:179281.3-179310.6"
+ wire $1\wr_detect$7[0:0]$10835
+ attribute \src "libresoc.v:179114.3-179143.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $2\cr_pred1__data_o$next[3:0]$10870
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $2\r1__data_o$next[3:0]$10941
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $2\r21__data_o$next[3:0]$10879
- attribute \src "libresoc.v:179696.3-179722.6"
- wire width 4 $2\reg$next[3:0]$10893
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $2\src11__data_o$next[3:0]$10899
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $2\src21__data_o$next[3:0]$10913
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $2\src31__data_o$next[3:0]$10927
- attribute \src "libresoc.v:179903.3-179932.6"
- wire $2\wr_detect$10[0:0]$10935
- attribute \src "libresoc.v:179973.3-180002.6"
- wire $2\wr_detect$13[0:0]$10949
- attribute \src "libresoc.v:179666.3-179695.6"
- wire $2\wr_detect$16[0:0]$10887
- attribute \src "libresoc.v:179763.3-179792.6"
- wire $2\wr_detect$4[0:0]$10907
- attribute \src "libresoc.v:179833.3-179862.6"
- wire $2\wr_detect$7[0:0]$10921
- attribute \src "libresoc.v:179596.3-179625.6"
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $2\r1__data_o$next[3:0]$10842
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $2\r21__data_o$next[3:0]$10856
+ attribute \src "libresoc.v:179144.3-179170.6"
+ wire width 4 $2\reg$next[3:0]$10808
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $2\src11__data_o$next[3:0]$10799
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $2\src21__data_o$next[3:0]$10814
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $2\src31__data_o$next[3:0]$10828
+ attribute \src "libresoc.v:179351.3-179380.6"
+ wire $2\wr_detect$10[0:0]$10850
+ attribute \src "libresoc.v:179421.3-179450.6"
+ wire $2\wr_detect$13[0:0]$10864
+ attribute \src "libresoc.v:179211.3-179240.6"
+ wire $2\wr_detect$4[0:0]$10822
+ attribute \src "libresoc.v:179281.3-179310.6"
+ wire $2\wr_detect$7[0:0]$10836
+ attribute \src "libresoc.v:179114.3-179143.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $3\cr_pred1__data_o$next[3:0]$10871
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $3\r1__data_o$next[3:0]$10942
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $3\r21__data_o$next[3:0]$10880
- attribute \src "libresoc.v:179696.3-179722.6"
- wire width 4 $3\reg$next[3:0]$10894
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $3\src11__data_o$next[3:0]$10900
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $3\src21__data_o$next[3:0]$10914
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $3\src31__data_o$next[3:0]$10928
- attribute \src "libresoc.v:179903.3-179932.6"
- wire $3\wr_detect$10[0:0]$10936
- attribute \src "libresoc.v:179973.3-180002.6"
- wire $3\wr_detect$13[0:0]$10950
- attribute \src "libresoc.v:179666.3-179695.6"
- wire $3\wr_detect$16[0:0]$10888
- attribute \src "libresoc.v:179763.3-179792.6"
- wire $3\wr_detect$4[0:0]$10908
- attribute \src "libresoc.v:179833.3-179862.6"
- wire $3\wr_detect$7[0:0]$10922
- attribute \src "libresoc.v:179596.3-179625.6"
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $3\r1__data_o$next[3:0]$10843
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $3\r21__data_o$next[3:0]$10857
+ attribute \src "libresoc.v:179144.3-179170.6"
+ wire width 4 $3\reg$next[3:0]$10809
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $3\src11__data_o$next[3:0]$10800
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $3\src21__data_o$next[3:0]$10815
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $3\src31__data_o$next[3:0]$10829
+ attribute \src "libresoc.v:179351.3-179380.6"
+ wire $3\wr_detect$10[0:0]$10851
+ attribute \src "libresoc.v:179421.3-179450.6"
+ wire $3\wr_detect$13[0:0]$10865
+ attribute \src "libresoc.v:179211.3-179240.6"
+ wire $3\wr_detect$4[0:0]$10823
+ attribute \src "libresoc.v:179281.3-179310.6"
+ wire $3\wr_detect$7[0:0]$10837
+ attribute \src "libresoc.v:179114.3-179143.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $4\cr_pred1__data_o$next[3:0]$10872
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $4\r1__data_o$next[3:0]$10943
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $4\r21__data_o$next[3:0]$10881
- attribute \src "libresoc.v:179696.3-179722.6"
- wire width 4 $4\reg$next[3:0]$10895
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $4\src11__data_o$next[3:0]$10901
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $4\src21__data_o$next[3:0]$10915
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $4\src31__data_o$next[3:0]$10929
- attribute \src "libresoc.v:179903.3-179932.6"
- wire $4\wr_detect$10[0:0]$10937
- attribute \src "libresoc.v:179973.3-180002.6"
- wire $4\wr_detect$13[0:0]$10951
- attribute \src "libresoc.v:179666.3-179695.6"
- wire $4\wr_detect$16[0:0]$10889
- attribute \src "libresoc.v:179763.3-179792.6"
- wire $4\wr_detect$4[0:0]$10909
- attribute \src "libresoc.v:179833.3-179862.6"
- wire $4\wr_detect$7[0:0]$10923
- attribute \src "libresoc.v:179596.3-179625.6"
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $4\r1__data_o$next[3:0]$10844
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $4\r21__data_o$next[3:0]$10858
+ attribute \src "libresoc.v:179144.3-179170.6"
+ wire width 4 $4\reg$next[3:0]$10810
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $4\src11__data_o$next[3:0]$10801
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $4\src21__data_o$next[3:0]$10816
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $4\src31__data_o$next[3:0]$10830
+ attribute \src "libresoc.v:179351.3-179380.6"
+ wire $4\wr_detect$10[0:0]$10852
+ attribute \src "libresoc.v:179421.3-179450.6"
+ wire $4\wr_detect$13[0:0]$10866
+ attribute \src "libresoc.v:179211.3-179240.6"
+ wire $4\wr_detect$4[0:0]$10824
+ attribute \src "libresoc.v:179281.3-179310.6"
+ wire $4\wr_detect$7[0:0]$10838
+ attribute \src "libresoc.v:179114.3-179143.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $5\cr_pred1__data_o$next[3:0]$10873
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $5\r1__data_o$next[3:0]$10944
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $5\r21__data_o$next[3:0]$10882
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $5\src11__data_o$next[3:0]$10902
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $5\src21__data_o$next[3:0]$10916
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $5\src31__data_o$next[3:0]$10930
- attribute \src "libresoc.v:179556.3-179595.6"
- wire width 4 $6\cr_pred1__data_o$next[3:0]$10874
- attribute \src "libresoc.v:179933.3-179972.6"
- wire width 4 $6\r1__data_o$next[3:0]$10945
- attribute \src "libresoc.v:179626.3-179665.6"
- wire width 4 $6\r21__data_o$next[3:0]$10883
- attribute \src "libresoc.v:179723.3-179762.6"
- wire width 4 $6\src11__data_o$next[3:0]$10903
- attribute \src "libresoc.v:179793.3-179832.6"
- wire width 4 $6\src21__data_o$next[3:0]$10917
- attribute \src "libresoc.v:179863.3-179902.6"
- wire width 4 $6\src31__data_o$next[3:0]$10931
- attribute \src "libresoc.v:179536.17-179536.104"
- wire $not$libresoc.v:179536$10854_Y
- attribute \src "libresoc.v:179537.18-179537.105"
- wire $not$libresoc.v:179537$10855_Y
- attribute \src "libresoc.v:179538.18-179538.105"
- wire $not$libresoc.v:179538$10856_Y
- attribute \src "libresoc.v:179539.17-179539.100"
- wire $not$libresoc.v:179539$10857_Y
- attribute \src "libresoc.v:179540.17-179540.103"
- wire $not$libresoc.v:179540$10858_Y
- attribute \src "libresoc.v:179541.17-179541.103"
- wire $not$libresoc.v:179541$10859_Y
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $5\r1__data_o$next[3:0]$10845
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $5\r21__data_o$next[3:0]$10859
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $5\src11__data_o$next[3:0]$10802
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $5\src21__data_o$next[3:0]$10817
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $5\src31__data_o$next[3:0]$10831
+ attribute \src "libresoc.v:179311.3-179350.6"
+ wire width 4 $6\r1__data_o$next[3:0]$10846
+ attribute \src "libresoc.v:179381.3-179420.6"
+ wire width 4 $6\r21__data_o$next[3:0]$10860
+ attribute \src "libresoc.v:179074.3-179113.6"
+ wire width 4 $6\src11__data_o$next[3:0]$10803
+ attribute \src "libresoc.v:179171.3-179210.6"
+ wire width 4 $6\src21__data_o$next[3:0]$10818
+ attribute \src "libresoc.v:179241.3-179280.6"
+ wire width 4 $6\src31__data_o$next[3:0]$10832
+ attribute \src "libresoc.v:179057.17-179057.104"
+ wire $not$libresoc.v:179057$10785_Y
+ attribute \src "libresoc.v:179058.18-179058.105"
+ wire $not$libresoc.v:179058$10786_Y
+ attribute \src "libresoc.v:179059.17-179059.100"
+ wire $not$libresoc.v:179059$10787_Y
+ attribute \src "libresoc.v:179060.17-179060.103"
+ wire $not$libresoc.v:179060$10788_Y
+ attribute \src "libresoc.v:179061.17-179061.103"
+ wire $not$libresoc.v:179061$10789_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred1__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest11__data_i
+ wire width 4 input 9 \dest11__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest11__wen
+ wire input 8 \dest11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest21__data_i
+ wire width 4 input 11 \dest21__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest21__wen
- attribute \src "libresoc.v:179449.7-179449.15"
+ wire input 10 \dest21__wen
+ attribute \src "libresoc.v:178981.7-178981.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r1__data_o
+ wire width 4 output 12 \r1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r1__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r1__ren
+ wire input 13 \r1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r21__data_o
+ wire width 4 output 14 \r21__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r21__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r21__ren
+ wire input 15 \r21__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src11__data_o
+ wire width 4 output 3 \src11__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src11__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src11__ren
+ wire input 2 \src11__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src21__data_o
+ wire width 4 output 5 \src21__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src21__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src21__ren
+ wire input 4 \src21__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src31__data_o
+ wire width 4 output 7 \src31__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src31__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src31__ren
+ wire input 6 \src31__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w1__data_i
+ wire width 4 input 16 \w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w1__wen
+ wire input 17 \w1__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179536$10854
+ cell $not $not$libresoc.v:179057$10785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:179536$10854_Y
+ connect \Y $not$libresoc.v:179057$10785_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179537$10855
+ cell $not $not$libresoc.v:179058$10786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:179537$10855_Y
+ connect \Y $not$libresoc.v:179058$10786_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179538$10856
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:179538$10856_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179539$10857
+ cell $not $not$libresoc.v:179059$10787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:179539$10857_Y
+ connect \Y $not$libresoc.v:179059$10787_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179540$10858
+ cell $not $not$libresoc.v:179060$10788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:179540$10858_Y
+ connect \Y $not$libresoc.v:179060$10788_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179541$10859
+ cell $not $not$libresoc.v:179061$10789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:179541$10859_Y
+ connect \Y $not$libresoc.v:179061$10789_Y
end
- attribute \src "libresoc.v:179449.7-179449.20"
- process $proc$libresoc.v:179449$10952
+ attribute \src "libresoc.v:178981.7-178981.20"
+ process $proc$libresoc.v:178981$10867
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:179468.13-179468.36"
- process $proc$libresoc.v:179468$10953
- assign { } { }
- assign $1\cr_pred1__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred1__data_o $1\cr_pred1__data_o[3:0]
- end
- attribute \src "libresoc.v:179483.13-179483.30"
- process $proc$libresoc.v:179483$10954
+ attribute \src "libresoc.v:179006.13-179006.30"
+ process $proc$libresoc.v:179006$10868
assign { } { }
assign $1\r1__data_o[3:0] 4'0000
sync always
sync init
update \r1__data_o $1\r1__data_o[3:0]
end
- attribute \src "libresoc.v:179490.13-179490.31"
- process $proc$libresoc.v:179490$10955
+ attribute \src "libresoc.v:179013.13-179013.31"
+ process $proc$libresoc.v:179013$10869
assign { } { }
assign $1\r21__data_o[3:0] 4'0000
sync always
sync init
update \r21__data_o $1\r21__data_o[3:0]
end
- attribute \src "libresoc.v:179496.13-179496.25"
- process $proc$libresoc.v:179496$10956
+ attribute \src "libresoc.v:179019.13-179019.25"
+ process $proc$libresoc.v:179019$10870
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:179501.13-179501.33"
- process $proc$libresoc.v:179501$10957
+ attribute \src "libresoc.v:179024.13-179024.33"
+ process $proc$libresoc.v:179024$10871
assign { } { }
assign $1\src11__data_o[3:0] 4'0000
sync always
sync init
update \src11__data_o $1\src11__data_o[3:0]
end
- attribute \src "libresoc.v:179508.13-179508.33"
- process $proc$libresoc.v:179508$10958
+ attribute \src "libresoc.v:179031.13-179031.33"
+ process $proc$libresoc.v:179031$10872
assign { } { }
assign $1\src21__data_o[3:0] 4'0000
sync always
sync init
update \src21__data_o $1\src21__data_o[3:0]
end
- attribute \src "libresoc.v:179515.13-179515.33"
- process $proc$libresoc.v:179515$10959
+ attribute \src "libresoc.v:179038.13-179038.33"
+ process $proc$libresoc.v:179038$10873
assign { } { }
assign $1\src31__data_o[3:0] 4'0000
sync always
sync init
update \src31__data_o $1\src31__data_o[3:0]
end
- attribute \src "libresoc.v:179542.3-179543.25"
- process $proc$libresoc.v:179542$10860
+ attribute \src "libresoc.v:179062.3-179063.25"
+ process $proc$libresoc.v:179062$10790
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:179544.3-179545.39"
- process $proc$libresoc.v:179544$10861
+ attribute \src "libresoc.v:179064.3-179065.39"
+ process $proc$libresoc.v:179064$10791
assign { } { }
assign $0\r21__data_o[3:0] \r21__data_o$next
sync posedge \coresync_clk
update \r21__data_o $0\r21__data_o[3:0]
end
- attribute \src "libresoc.v:179546.3-179547.37"
- process $proc$libresoc.v:179546$10862
+ attribute \src "libresoc.v:179066.3-179067.37"
+ process $proc$libresoc.v:179066$10792
assign { } { }
assign $0\r1__data_o[3:0] \r1__data_o$next
sync posedge \coresync_clk
update \r1__data_o $0\r1__data_o[3:0]
end
- attribute \src "libresoc.v:179548.3-179549.43"
- process $proc$libresoc.v:179548$10863
+ attribute \src "libresoc.v:179068.3-179069.43"
+ process $proc$libresoc.v:179068$10793
assign { } { }
assign $0\src31__data_o[3:0] \src31__data_o$next
sync posedge \coresync_clk
update \src31__data_o $0\src31__data_o[3:0]
end
- attribute \src "libresoc.v:179550.3-179551.43"
- process $proc$libresoc.v:179550$10864
+ attribute \src "libresoc.v:179070.3-179071.43"
+ process $proc$libresoc.v:179070$10794
assign { } { }
assign $0\src21__data_o[3:0] \src21__data_o$next
sync posedge \coresync_clk
update \src21__data_o $0\src21__data_o[3:0]
end
- attribute \src "libresoc.v:179552.3-179553.43"
- process $proc$libresoc.v:179552$10865
+ attribute \src "libresoc.v:179072.3-179073.43"
+ process $proc$libresoc.v:179072$10795
assign { } { }
assign $0\src11__data_o[3:0] \src11__data_o$next
sync posedge \coresync_clk
update \src11__data_o $0\src11__data_o[3:0]
end
- attribute \src "libresoc.v:179554.3-179555.49"
- process $proc$libresoc.v:179554$10866
+ attribute \src "libresoc.v:179074.3-179113.6"
+ process $proc$libresoc.v:179074$10796
assign { } { }
- assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next
- sync posedge \coresync_clk
- update \cr_pred1__data_o $0\cr_pred1__data_o[3:0]
- end
- attribute \src "libresoc.v:179556.3-179595.6"
- process $proc$libresoc.v:179556$10867
assign { } { }
assign { } { }
- assign { } { }
- assign $0\cr_pred1__data_o$next[3:0]$10868 $6\cr_pred1__data_o$next[3:0]$10874
- attribute \src "libresoc.v:179557.5-179557.29"
+ assign $0\src11__data_o$next[3:0]$10797 $6\src11__data_o$next[3:0]$10803
+ attribute \src "libresoc.v:179075.5-179075.29"
switch \initial
- attribute \src "libresoc.v:179557.9-179557.17"
+ attribute \src "libresoc.v:179075.9-179075.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred1__ren
+ switch \src11__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred1__data_o$next[3:0]$10869 $5\cr_pred1__data_o$next[3:0]$10873
+ assign $1\src11__data_o$next[3:0]$10798 $5\src11__data_o$next[3:0]$10802
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred1__data_o$next[3:0]$10870 \dest11__data_i
+ assign $2\src11__data_o$next[3:0]$10799 \dest11__data_i
case
- assign $2\cr_pred1__data_o$next[3:0]$10870 4'0000
+ assign $2\src11__data_o$next[3:0]$10799 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred1__data_o$next[3:0]$10871 \dest21__data_i
+ assign $3\src11__data_o$next[3:0]$10800 \dest21__data_i
case
- assign $3\cr_pred1__data_o$next[3:0]$10871 $2\cr_pred1__data_o$next[3:0]$10870
+ assign $3\src11__data_o$next[3:0]$10800 $2\src11__data_o$next[3:0]$10799
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred1__data_o$next[3:0]$10872 \w1__data_i
+ assign $4\src11__data_o$next[3:0]$10801 \w1__data_i
case
- assign $4\cr_pred1__data_o$next[3:0]$10872 $3\cr_pred1__data_o$next[3:0]$10871
+ assign $4\src11__data_o$next[3:0]$10801 $3\src11__data_o$next[3:0]$10800
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred1__data_o$next[3:0]$10873 \reg
+ assign $5\src11__data_o$next[3:0]$10802 \reg
case
- assign $5\cr_pred1__data_o$next[3:0]$10873 $4\cr_pred1__data_o$next[3:0]$10872
+ assign $5\src11__data_o$next[3:0]$10802 $4\src11__data_o$next[3:0]$10801
end
case
- assign $1\cr_pred1__data_o$next[3:0]$10869 4'0000
+ assign $1\src11__data_o$next[3:0]$10798 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred1__data_o$next[3:0]$10874 4'0000
+ assign $6\src11__data_o$next[3:0]$10803 4'0000
case
- assign $6\cr_pred1__data_o$next[3:0]$10874 $1\cr_pred1__data_o$next[3:0]$10869
+ assign $6\src11__data_o$next[3:0]$10803 $1\src11__data_o$next[3:0]$10798
end
sync always
- update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10868
+ update \src11__data_o$next $0\src11__data_o$next[3:0]$10797
end
- attribute \src "libresoc.v:179596.3-179625.6"
- process $proc$libresoc.v:179596$10875
+ attribute \src "libresoc.v:179114.3-179143.6"
+ process $proc$libresoc.v:179114$10804
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:179597.5-179597.29"
+ attribute \src "libresoc.v:179115.5-179115.29"
switch \initial
- attribute \src "libresoc.v:179597.9-179597.17"
+ attribute \src "libresoc.v:179115.9-179115.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred1__ren
+ switch \src11__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:179626.3-179665.6"
- process $proc$libresoc.v:179626$10876
+ attribute \src "libresoc.v:179144.3-179170.6"
+ process $proc$libresoc.v:179144$10805
assign { } { }
assign { } { }
assign { } { }
- assign $0\r21__data_o$next[3:0]$10877 $6\r21__data_o$next[3:0]$10883
- attribute \src "libresoc.v:179627.5-179627.29"
- switch \initial
- attribute \src "libresoc.v:179627.9-179627.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r21__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\r21__data_o$next[3:0]$10878 $5\r21__data_o$next[3:0]$10882
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest11__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r21__data_o$next[3:0]$10879 \dest11__data_i
- case
- assign $2\r21__data_o$next[3:0]$10879 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest21__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r21__data_o$next[3:0]$10880 \dest21__data_i
- case
- assign $3\r21__data_o$next[3:0]$10880 $2\r21__data_o$next[3:0]$10879
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w1__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r21__data_o$next[3:0]$10881 \w1__data_i
- case
- assign $4\r21__data_o$next[3:0]$10881 $3\r21__data_o$next[3:0]$10880
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r21__data_o$next[3:0]$10882 \reg
- case
- assign $5\r21__data_o$next[3:0]$10882 $4\r21__data_o$next[3:0]$10881
- end
- case
- assign $1\r21__data_o$next[3:0]$10878 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\r21__data_o$next[3:0]$10883 4'0000
- case
- assign $6\r21__data_o$next[3:0]$10883 $1\r21__data_o$next[3:0]$10878
- end
- sync always
- update \r21__data_o$next $0\r21__data_o$next[3:0]$10877
- end
- attribute \src "libresoc.v:179666.3-179695.6"
- process $proc$libresoc.v:179666$10884
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$10885 $1\wr_detect$16[0:0]$10886
- attribute \src "libresoc.v:179667.5-179667.29"
+ assign $0\reg$next[3:0]$10806 $4\reg$next[3:0]$10810
+ attribute \src "libresoc.v:179145.5-179145.29"
switch \initial
- attribute \src "libresoc.v:179667.9-179667.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r21__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$16[0:0]$10886 $4\wr_detect$16[0:0]$10889
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest11__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$16[0:0]$10887 1'1
- case
- assign $2\wr_detect$16[0:0]$10887 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest21__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$16[0:0]$10888 1'1
- case
- assign $3\wr_detect$16[0:0]$10888 $2\wr_detect$16[0:0]$10887
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w1__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$16[0:0]$10889 1'1
- case
- assign $4\wr_detect$16[0:0]$10889 $3\wr_detect$16[0:0]$10888
- end
- case
- assign $1\wr_detect$16[0:0]$10886 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$10885
- end
- attribute \src "libresoc.v:179696.3-179722.6"
- process $proc$libresoc.v:179696$10890
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$10891 $4\reg$next[3:0]$10895
- attribute \src "libresoc.v:179697.5-179697.29"
- switch \initial
- attribute \src "libresoc.v:179697.9-179697.17"
+ attribute \src "libresoc.v:179145.9-179145.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$10892 \dest11__data_i
+ assign $1\reg$next[3:0]$10807 \dest11__data_i
case
- assign $1\reg$next[3:0]$10892 \reg
+ assign $1\reg$next[3:0]$10807 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$10893 \dest21__data_i
+ assign $2\reg$next[3:0]$10808 \dest21__data_i
case
- assign $2\reg$next[3:0]$10893 $1\reg$next[3:0]$10892
+ assign $2\reg$next[3:0]$10808 $1\reg$next[3:0]$10807
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$10894 \w1__data_i
+ assign $3\reg$next[3:0]$10809 \w1__data_i
case
- assign $3\reg$next[3:0]$10894 $2\reg$next[3:0]$10893
+ assign $3\reg$next[3:0]$10809 $2\reg$next[3:0]$10808
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$10895 4'0000
+ assign $4\reg$next[3:0]$10810 4'0000
case
- assign $4\reg$next[3:0]$10895 $3\reg$next[3:0]$10894
+ assign $4\reg$next[3:0]$10810 $3\reg$next[3:0]$10809
end
sync always
- update \reg$next $0\reg$next[3:0]$10891
+ update \reg$next $0\reg$next[3:0]$10806
end
- attribute \src "libresoc.v:179723.3-179762.6"
- process $proc$libresoc.v:179723$10896
+ attribute \src "libresoc.v:179171.3-179210.6"
+ process $proc$libresoc.v:179171$10811
assign { } { }
assign { } { }
assign { } { }
- assign $0\src11__data_o$next[3:0]$10897 $6\src11__data_o$next[3:0]$10903
- attribute \src "libresoc.v:179724.5-179724.29"
+ assign $0\src21__data_o$next[3:0]$10812 $6\src21__data_o$next[3:0]$10818
+ attribute \src "libresoc.v:179172.5-179172.29"
switch \initial
- attribute \src "libresoc.v:179724.9-179724.17"
+ attribute \src "libresoc.v:179172.9-179172.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src11__ren
+ switch \src21__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src11__data_o$next[3:0]$10898 $5\src11__data_o$next[3:0]$10902
+ assign $1\src21__data_o$next[3:0]$10813 $5\src21__data_o$next[3:0]$10817
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src11__data_o$next[3:0]$10899 \dest11__data_i
+ assign $2\src21__data_o$next[3:0]$10814 \dest11__data_i
case
- assign $2\src11__data_o$next[3:0]$10899 4'0000
+ assign $2\src21__data_o$next[3:0]$10814 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src11__data_o$next[3:0]$10900 \dest21__data_i
+ assign $3\src21__data_o$next[3:0]$10815 \dest21__data_i
case
- assign $3\src11__data_o$next[3:0]$10900 $2\src11__data_o$next[3:0]$10899
+ assign $3\src21__data_o$next[3:0]$10815 $2\src21__data_o$next[3:0]$10814
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src11__data_o$next[3:0]$10901 \w1__data_i
+ assign $4\src21__data_o$next[3:0]$10816 \w1__data_i
case
- assign $4\src11__data_o$next[3:0]$10901 $3\src11__data_o$next[3:0]$10900
+ assign $4\src21__data_o$next[3:0]$10816 $3\src21__data_o$next[3:0]$10815
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src11__data_o$next[3:0]$10902 \reg
+ assign $5\src21__data_o$next[3:0]$10817 \reg
case
- assign $5\src11__data_o$next[3:0]$10902 $4\src11__data_o$next[3:0]$10901
+ assign $5\src21__data_o$next[3:0]$10817 $4\src21__data_o$next[3:0]$10816
end
case
- assign $1\src11__data_o$next[3:0]$10898 4'0000
+ assign $1\src21__data_o$next[3:0]$10813 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src11__data_o$next[3:0]$10903 4'0000
+ assign $6\src21__data_o$next[3:0]$10818 4'0000
case
- assign $6\src11__data_o$next[3:0]$10903 $1\src11__data_o$next[3:0]$10898
+ assign $6\src21__data_o$next[3:0]$10818 $1\src21__data_o$next[3:0]$10813
end
sync always
- update \src11__data_o$next $0\src11__data_o$next[3:0]$10897
+ update \src21__data_o$next $0\src21__data_o$next[3:0]$10812
end
- attribute \src "libresoc.v:179763.3-179792.6"
- process $proc$libresoc.v:179763$10904
+ attribute \src "libresoc.v:179211.3-179240.6"
+ process $proc$libresoc.v:179211$10819
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10905 $1\wr_detect$4[0:0]$10906
- attribute \src "libresoc.v:179764.5-179764.29"
+ assign $0\wr_detect$4[0:0]$10820 $1\wr_detect$4[0:0]$10821
+ attribute \src "libresoc.v:179212.5-179212.29"
switch \initial
- attribute \src "libresoc.v:179764.9-179764.17"
+ attribute \src "libresoc.v:179212.9-179212.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src11__ren
+ switch \src21__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10906 $4\wr_detect$4[0:0]$10909
+ assign $1\wr_detect$4[0:0]$10821 $4\wr_detect$4[0:0]$10824
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10907 1'1
+ assign $2\wr_detect$4[0:0]$10822 1'1
case
- assign $2\wr_detect$4[0:0]$10907 1'0
+ assign $2\wr_detect$4[0:0]$10822 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10908 1'1
+ assign $3\wr_detect$4[0:0]$10823 1'1
case
- assign $3\wr_detect$4[0:0]$10908 $2\wr_detect$4[0:0]$10907
+ assign $3\wr_detect$4[0:0]$10823 $2\wr_detect$4[0:0]$10822
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10909 1'1
+ assign $4\wr_detect$4[0:0]$10824 1'1
case
- assign $4\wr_detect$4[0:0]$10909 $3\wr_detect$4[0:0]$10908
+ assign $4\wr_detect$4[0:0]$10824 $3\wr_detect$4[0:0]$10823
end
case
- assign $1\wr_detect$4[0:0]$10906 1'0
+ assign $1\wr_detect$4[0:0]$10821 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10905
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10820
end
- attribute \src "libresoc.v:179793.3-179832.6"
- process $proc$libresoc.v:179793$10910
+ attribute \src "libresoc.v:179241.3-179280.6"
+ process $proc$libresoc.v:179241$10825
assign { } { }
assign { } { }
assign { } { }
- assign $0\src21__data_o$next[3:0]$10911 $6\src21__data_o$next[3:0]$10917
- attribute \src "libresoc.v:179794.5-179794.29"
+ assign $0\src31__data_o$next[3:0]$10826 $6\src31__data_o$next[3:0]$10832
+ attribute \src "libresoc.v:179242.5-179242.29"
switch \initial
- attribute \src "libresoc.v:179794.9-179794.17"
+ attribute \src "libresoc.v:179242.9-179242.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src21__ren
+ switch \src31__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src21__data_o$next[3:0]$10912 $5\src21__data_o$next[3:0]$10916
+ assign $1\src31__data_o$next[3:0]$10827 $5\src31__data_o$next[3:0]$10831
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src21__data_o$next[3:0]$10913 \dest11__data_i
+ assign $2\src31__data_o$next[3:0]$10828 \dest11__data_i
case
- assign $2\src21__data_o$next[3:0]$10913 4'0000
+ assign $2\src31__data_o$next[3:0]$10828 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src21__data_o$next[3:0]$10914 \dest21__data_i
+ assign $3\src31__data_o$next[3:0]$10829 \dest21__data_i
case
- assign $3\src21__data_o$next[3:0]$10914 $2\src21__data_o$next[3:0]$10913
+ assign $3\src31__data_o$next[3:0]$10829 $2\src31__data_o$next[3:0]$10828
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src21__data_o$next[3:0]$10915 \w1__data_i
+ assign $4\src31__data_o$next[3:0]$10830 \w1__data_i
case
- assign $4\src21__data_o$next[3:0]$10915 $3\src21__data_o$next[3:0]$10914
+ assign $4\src31__data_o$next[3:0]$10830 $3\src31__data_o$next[3:0]$10829
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src21__data_o$next[3:0]$10916 \reg
+ assign $5\src31__data_o$next[3:0]$10831 \reg
case
- assign $5\src21__data_o$next[3:0]$10916 $4\src21__data_o$next[3:0]$10915
+ assign $5\src31__data_o$next[3:0]$10831 $4\src31__data_o$next[3:0]$10830
end
case
- assign $1\src21__data_o$next[3:0]$10912 4'0000
+ assign $1\src31__data_o$next[3:0]$10827 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src21__data_o$next[3:0]$10917 4'0000
+ assign $6\src31__data_o$next[3:0]$10832 4'0000
case
- assign $6\src21__data_o$next[3:0]$10917 $1\src21__data_o$next[3:0]$10912
+ assign $6\src31__data_o$next[3:0]$10832 $1\src31__data_o$next[3:0]$10827
end
sync always
- update \src21__data_o$next $0\src21__data_o$next[3:0]$10911
+ update \src31__data_o$next $0\src31__data_o$next[3:0]$10826
end
- attribute \src "libresoc.v:179833.3-179862.6"
- process $proc$libresoc.v:179833$10918
+ attribute \src "libresoc.v:179281.3-179310.6"
+ process $proc$libresoc.v:179281$10833
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10919 $1\wr_detect$7[0:0]$10920
- attribute \src "libresoc.v:179834.5-179834.29"
+ assign $0\wr_detect$7[0:0]$10834 $1\wr_detect$7[0:0]$10835
+ attribute \src "libresoc.v:179282.5-179282.29"
switch \initial
- attribute \src "libresoc.v:179834.9-179834.17"
+ attribute \src "libresoc.v:179282.9-179282.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src21__ren
+ switch \src31__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10920 $4\wr_detect$7[0:0]$10923
+ assign $1\wr_detect$7[0:0]$10835 $4\wr_detect$7[0:0]$10838
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10921 1'1
+ assign $2\wr_detect$7[0:0]$10836 1'1
case
- assign $2\wr_detect$7[0:0]$10921 1'0
+ assign $2\wr_detect$7[0:0]$10836 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10922 1'1
+ assign $3\wr_detect$7[0:0]$10837 1'1
case
- assign $3\wr_detect$7[0:0]$10922 $2\wr_detect$7[0:0]$10921
+ assign $3\wr_detect$7[0:0]$10837 $2\wr_detect$7[0:0]$10836
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10923 1'1
+ assign $4\wr_detect$7[0:0]$10838 1'1
case
- assign $4\wr_detect$7[0:0]$10923 $3\wr_detect$7[0:0]$10922
+ assign $4\wr_detect$7[0:0]$10838 $3\wr_detect$7[0:0]$10837
end
case
- assign $1\wr_detect$7[0:0]$10920 1'0
+ assign $1\wr_detect$7[0:0]$10835 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10919
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10834
end
- attribute \src "libresoc.v:179863.3-179902.6"
- process $proc$libresoc.v:179863$10924
+ attribute \src "libresoc.v:179311.3-179350.6"
+ process $proc$libresoc.v:179311$10839
assign { } { }
assign { } { }
assign { } { }
- assign $0\src31__data_o$next[3:0]$10925 $6\src31__data_o$next[3:0]$10931
- attribute \src "libresoc.v:179864.5-179864.29"
+ assign $0\r1__data_o$next[3:0]$10840 $6\r1__data_o$next[3:0]$10846
+ attribute \src "libresoc.v:179312.5-179312.29"
switch \initial
- attribute \src "libresoc.v:179864.9-179864.17"
+ attribute \src "libresoc.v:179312.9-179312.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src31__ren
+ switch \r1__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src31__data_o$next[3:0]$10926 $5\src31__data_o$next[3:0]$10930
+ assign $1\r1__data_o$next[3:0]$10841 $5\r1__data_o$next[3:0]$10845
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src31__data_o$next[3:0]$10927 \dest11__data_i
+ assign $2\r1__data_o$next[3:0]$10842 \dest11__data_i
case
- assign $2\src31__data_o$next[3:0]$10927 4'0000
+ assign $2\r1__data_o$next[3:0]$10842 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src31__data_o$next[3:0]$10928 \dest21__data_i
+ assign $3\r1__data_o$next[3:0]$10843 \dest21__data_i
case
- assign $3\src31__data_o$next[3:0]$10928 $2\src31__data_o$next[3:0]$10927
+ assign $3\r1__data_o$next[3:0]$10843 $2\r1__data_o$next[3:0]$10842
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src31__data_o$next[3:0]$10929 \w1__data_i
+ assign $4\r1__data_o$next[3:0]$10844 \w1__data_i
case
- assign $4\src31__data_o$next[3:0]$10929 $3\src31__data_o$next[3:0]$10928
+ assign $4\r1__data_o$next[3:0]$10844 $3\r1__data_o$next[3:0]$10843
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src31__data_o$next[3:0]$10930 \reg
+ assign $5\r1__data_o$next[3:0]$10845 \reg
case
- assign $5\src31__data_o$next[3:0]$10930 $4\src31__data_o$next[3:0]$10929
+ assign $5\r1__data_o$next[3:0]$10845 $4\r1__data_o$next[3:0]$10844
end
case
- assign $1\src31__data_o$next[3:0]$10926 4'0000
+ assign $1\r1__data_o$next[3:0]$10841 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src31__data_o$next[3:0]$10931 4'0000
+ assign $6\r1__data_o$next[3:0]$10846 4'0000
case
- assign $6\src31__data_o$next[3:0]$10931 $1\src31__data_o$next[3:0]$10926
+ assign $6\r1__data_o$next[3:0]$10846 $1\r1__data_o$next[3:0]$10841
end
sync always
- update \src31__data_o$next $0\src31__data_o$next[3:0]$10925
+ update \r1__data_o$next $0\r1__data_o$next[3:0]$10840
end
- attribute \src "libresoc.v:179903.3-179932.6"
- process $proc$libresoc.v:179903$10932
+ attribute \src "libresoc.v:179351.3-179380.6"
+ process $proc$libresoc.v:179351$10847
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10933 $1\wr_detect$10[0:0]$10934
- attribute \src "libresoc.v:179904.5-179904.29"
+ assign $0\wr_detect$10[0:0]$10848 $1\wr_detect$10[0:0]$10849
+ attribute \src "libresoc.v:179352.5-179352.29"
switch \initial
- attribute \src "libresoc.v:179904.9-179904.17"
+ attribute \src "libresoc.v:179352.9-179352.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src31__ren
+ switch \r1__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10934 $4\wr_detect$10[0:0]$10937
+ assign $1\wr_detect$10[0:0]$10849 $4\wr_detect$10[0:0]$10852
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10935 1'1
+ assign $2\wr_detect$10[0:0]$10850 1'1
case
- assign $2\wr_detect$10[0:0]$10935 1'0
+ assign $2\wr_detect$10[0:0]$10850 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10936 1'1
+ assign $3\wr_detect$10[0:0]$10851 1'1
case
- assign $3\wr_detect$10[0:0]$10936 $2\wr_detect$10[0:0]$10935
+ assign $3\wr_detect$10[0:0]$10851 $2\wr_detect$10[0:0]$10850
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10937 1'1
+ assign $4\wr_detect$10[0:0]$10852 1'1
case
- assign $4\wr_detect$10[0:0]$10937 $3\wr_detect$10[0:0]$10936
+ assign $4\wr_detect$10[0:0]$10852 $3\wr_detect$10[0:0]$10851
end
case
- assign $1\wr_detect$10[0:0]$10934 1'0
+ assign $1\wr_detect$10[0:0]$10849 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10933
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10848
end
- attribute \src "libresoc.v:179933.3-179972.6"
- process $proc$libresoc.v:179933$10938
+ attribute \src "libresoc.v:179381.3-179420.6"
+ process $proc$libresoc.v:179381$10853
assign { } { }
assign { } { }
assign { } { }
- assign $0\r1__data_o$next[3:0]$10939 $6\r1__data_o$next[3:0]$10945
- attribute \src "libresoc.v:179934.5-179934.29"
+ assign $0\r21__data_o$next[3:0]$10854 $6\r21__data_o$next[3:0]$10860
+ attribute \src "libresoc.v:179382.5-179382.29"
switch \initial
- attribute \src "libresoc.v:179934.9-179934.17"
+ attribute \src "libresoc.v:179382.9-179382.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r1__ren
+ switch \r21__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r1__data_o$next[3:0]$10940 $5\r1__data_o$next[3:0]$10944
+ assign $1\r21__data_o$next[3:0]$10855 $5\r21__data_o$next[3:0]$10859
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r1__data_o$next[3:0]$10941 \dest11__data_i
+ assign $2\r21__data_o$next[3:0]$10856 \dest11__data_i
case
- assign $2\r1__data_o$next[3:0]$10941 4'0000
+ assign $2\r21__data_o$next[3:0]$10856 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r1__data_o$next[3:0]$10942 \dest21__data_i
+ assign $3\r21__data_o$next[3:0]$10857 \dest21__data_i
case
- assign $3\r1__data_o$next[3:0]$10942 $2\r1__data_o$next[3:0]$10941
+ assign $3\r21__data_o$next[3:0]$10857 $2\r21__data_o$next[3:0]$10856
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r1__data_o$next[3:0]$10943 \w1__data_i
+ assign $4\r21__data_o$next[3:0]$10858 \w1__data_i
case
- assign $4\r1__data_o$next[3:0]$10943 $3\r1__data_o$next[3:0]$10942
+ assign $4\r21__data_o$next[3:0]$10858 $3\r21__data_o$next[3:0]$10857
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r1__data_o$next[3:0]$10944 \reg
+ assign $5\r21__data_o$next[3:0]$10859 \reg
case
- assign $5\r1__data_o$next[3:0]$10944 $4\r1__data_o$next[3:0]$10943
+ assign $5\r21__data_o$next[3:0]$10859 $4\r21__data_o$next[3:0]$10858
end
case
- assign $1\r1__data_o$next[3:0]$10940 4'0000
+ assign $1\r21__data_o$next[3:0]$10855 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r1__data_o$next[3:0]$10945 4'0000
+ assign $6\r21__data_o$next[3:0]$10860 4'0000
case
- assign $6\r1__data_o$next[3:0]$10945 $1\r1__data_o$next[3:0]$10940
+ assign $6\r21__data_o$next[3:0]$10860 $1\r21__data_o$next[3:0]$10855
end
sync always
- update \r1__data_o$next $0\r1__data_o$next[3:0]$10939
+ update \r21__data_o$next $0\r21__data_o$next[3:0]$10854
end
- attribute \src "libresoc.v:179973.3-180002.6"
- process $proc$libresoc.v:179973$10946
+ attribute \src "libresoc.v:179421.3-179450.6"
+ process $proc$libresoc.v:179421$10861
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$10947 $1\wr_detect$13[0:0]$10948
- attribute \src "libresoc.v:179974.5-179974.29"
+ assign $0\wr_detect$13[0:0]$10862 $1\wr_detect$13[0:0]$10863
+ attribute \src "libresoc.v:179422.5-179422.29"
switch \initial
- attribute \src "libresoc.v:179974.9-179974.17"
+ attribute \src "libresoc.v:179422.9-179422.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r1__ren
+ switch \r21__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$10948 $4\wr_detect$13[0:0]$10951
+ assign $1\wr_detect$13[0:0]$10863 $4\wr_detect$13[0:0]$10866
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$10949 1'1
+ assign $2\wr_detect$13[0:0]$10864 1'1
case
- assign $2\wr_detect$13[0:0]$10949 1'0
+ assign $2\wr_detect$13[0:0]$10864 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$10950 1'1
+ assign $3\wr_detect$13[0:0]$10865 1'1
case
- assign $3\wr_detect$13[0:0]$10950 $2\wr_detect$13[0:0]$10949
+ assign $3\wr_detect$13[0:0]$10865 $2\wr_detect$13[0:0]$10864
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$10951 1'1
+ assign $4\wr_detect$13[0:0]$10866 1'1
case
- assign $4\wr_detect$13[0:0]$10951 $3\wr_detect$13[0:0]$10950
+ assign $4\wr_detect$13[0:0]$10866 $3\wr_detect$13[0:0]$10865
end
case
- assign $1\wr_detect$13[0:0]$10948 1'0
+ assign $1\wr_detect$13[0:0]$10863 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$10947
+ update \wr_detect$13 $0\wr_detect$13[0:0]$10862
end
- connect \$9 $not$libresoc.v:179536$10854_Y
- connect \$12 $not$libresoc.v:179537$10855_Y
- connect \$15 $not$libresoc.v:179538$10856_Y
- connect \$1 $not$libresoc.v:179539$10857_Y
- connect \$3 $not$libresoc.v:179540$10858_Y
- connect \$6 $not$libresoc.v:179541$10859_Y
+ connect \$9 $not$libresoc.v:179057$10785_Y
+ connect \$12 $not$libresoc.v:179058$10786_Y
+ connect \$1 $not$libresoc.v:179059$10787_Y
+ connect \$3 $not$libresoc.v:179060$10788_Y
+ connect \$6 $not$libresoc.v:179061$10789_Y
end
-attribute \src "libresoc.v:180007.1-180452.10"
+attribute \src "libresoc.v:179455.1-179900.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1"
attribute \generator "nMigen"
module \reg_1$133
- attribute \src "libresoc.v:180008.7-180008.20"
+ attribute \src "libresoc.v:179456.7-179456.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $0\r1__data_o$next[1:0]$11012
- attribute \src "libresoc.v:180083.3-180084.37"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $0\r1__data_o$next[1:0]$10926
+ attribute \src "libresoc.v:179531.3-179532.37"
wire width 2 $0\r1__data_o[1:0]
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $0\reg$next[1:0]$11028
- attribute \src "libresoc.v:180081.3-180082.25"
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $0\reg$next[1:0]$10942
+ attribute \src "libresoc.v:179529.3-179530.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $0\src11__data_o$next[1:0]$10970
- attribute \src "libresoc.v:180089.3-180090.43"
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $0\src11__data_o$next[1:0]$10884
+ attribute \src "libresoc.v:179537.3-179538.43"
wire width 2 $0\src11__data_o[1:0]
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $0\src21__data_o$next[1:0]$10980
- attribute \src "libresoc.v:180087.3-180088.43"
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $0\src21__data_o$next[1:0]$10894
+ attribute \src "libresoc.v:179535.3-179536.43"
wire width 2 $0\src21__data_o[1:0]
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $0\src31__data_o$next[1:0]$10996
- attribute \src "libresoc.v:180085.3-180086.43"
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $0\src31__data_o$next[1:0]$10910
+ attribute \src "libresoc.v:179533.3-179534.43"
wire width 2 $0\src31__data_o[1:0]
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $0\wr_detect$10[0:0]$11021
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $0\wr_detect$4[0:0]$10989
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $0\wr_detect$7[0:0]$11005
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $0\wr_detect$10[0:0]$10935
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $0\wr_detect$4[0:0]$10903
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $0\wr_detect$7[0:0]$10919
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $1\r1__data_o$next[1:0]$11013
- attribute \src "libresoc.v:180035.13-180035.30"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $1\r1__data_o$next[1:0]$10927
+ attribute \src "libresoc.v:179483.13-179483.30"
wire width 2 $1\r1__data_o[1:0]
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $1\reg$next[1:0]$11029
- attribute \src "libresoc.v:180041.13-180041.25"
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $1\reg$next[1:0]$10943
+ attribute \src "libresoc.v:179489.13-179489.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $1\src11__data_o$next[1:0]$10971
- attribute \src "libresoc.v:180046.13-180046.33"
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $1\src11__data_o$next[1:0]$10885
+ attribute \src "libresoc.v:179494.13-179494.33"
wire width 2 $1\src11__data_o[1:0]
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $1\src21__data_o$next[1:0]$10981
- attribute \src "libresoc.v:180053.13-180053.33"
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $1\src21__data_o$next[1:0]$10895
+ attribute \src "libresoc.v:179501.13-179501.33"
wire width 2 $1\src21__data_o[1:0]
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $1\src31__data_o$next[1:0]$10997
- attribute \src "libresoc.v:180060.13-180060.33"
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $1\src31__data_o$next[1:0]$10911
+ attribute \src "libresoc.v:179508.13-179508.33"
wire width 2 $1\src31__data_o[1:0]
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $1\wr_detect$10[0:0]$11022
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $1\wr_detect$4[0:0]$10990
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $1\wr_detect$7[0:0]$11006
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $1\wr_detect$10[0:0]$10936
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $1\wr_detect$4[0:0]$10904
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $1\wr_detect$7[0:0]$10920
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $2\r1__data_o$next[1:0]$11014
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $2\reg$next[1:0]$11030
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $2\src11__data_o$next[1:0]$10972
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $2\src21__data_o$next[1:0]$10982
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $2\src31__data_o$next[1:0]$10998
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $2\wr_detect$10[0:0]$11023
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $2\wr_detect$4[0:0]$10991
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $2\wr_detect$7[0:0]$11007
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $2\r1__data_o$next[1:0]$10928
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $2\reg$next[1:0]$10944
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $2\src11__data_o$next[1:0]$10886
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $2\src21__data_o$next[1:0]$10896
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $2\src31__data_o$next[1:0]$10912
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $2\wr_detect$10[0:0]$10937
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $2\wr_detect$4[0:0]$10905
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $2\wr_detect$7[0:0]$10921
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $3\r1__data_o$next[1:0]$11015
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $3\reg$next[1:0]$11031
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $3\src11__data_o$next[1:0]$10973
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $3\src21__data_o$next[1:0]$10983
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $3\src31__data_o$next[1:0]$10999
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $3\wr_detect$10[0:0]$11024
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $3\wr_detect$4[0:0]$10992
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $3\wr_detect$7[0:0]$11008
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $3\r1__data_o$next[1:0]$10929
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $3\reg$next[1:0]$10945
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $3\src11__data_o$next[1:0]$10887
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $3\src21__data_o$next[1:0]$10897
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $3\src31__data_o$next[1:0]$10913
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $3\wr_detect$10[0:0]$10938
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $3\wr_detect$4[0:0]$10906
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $3\wr_detect$7[0:0]$10922
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $4\r1__data_o$next[1:0]$11016
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $4\reg$next[1:0]$11032
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $4\src11__data_o$next[1:0]$10974
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $4\src21__data_o$next[1:0]$10984
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $4\src31__data_o$next[1:0]$11000
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $4\wr_detect$10[0:0]$11025
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $4\wr_detect$4[0:0]$10993
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $4\wr_detect$7[0:0]$11009
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $4\r1__data_o$next[1:0]$10930
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $4\reg$next[1:0]$10946
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $4\src11__data_o$next[1:0]$10888
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $4\src21__data_o$next[1:0]$10898
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $4\src31__data_o$next[1:0]$10914
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $4\wr_detect$10[0:0]$10939
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $4\wr_detect$4[0:0]$10907
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $4\wr_detect$7[0:0]$10923
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $5\r1__data_o$next[1:0]$11017
- attribute \src "libresoc.v:180419.3-180451.6"
- wire width 2 $5\reg$next[1:0]$11033
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $5\src11__data_o$next[1:0]$10975
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $5\src21__data_o$next[1:0]$10985
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $5\src31__data_o$next[1:0]$11001
- attribute \src "libresoc.v:180383.3-180418.6"
- wire $5\wr_detect$10[0:0]$11026
- attribute \src "libresoc.v:180219.3-180254.6"
- wire $5\wr_detect$4[0:0]$10994
- attribute \src "libresoc.v:180301.3-180336.6"
- wire $5\wr_detect$7[0:0]$11010
- attribute \src "libresoc.v:180137.3-180172.6"
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $5\r1__data_o$next[1:0]$10931
+ attribute \src "libresoc.v:179867.3-179899.6"
+ wire width 2 $5\reg$next[1:0]$10947
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $5\src11__data_o$next[1:0]$10889
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $5\src21__data_o$next[1:0]$10899
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $5\src31__data_o$next[1:0]$10915
+ attribute \src "libresoc.v:179831.3-179866.6"
+ wire $5\wr_detect$10[0:0]$10940
+ attribute \src "libresoc.v:179667.3-179702.6"
+ wire $5\wr_detect$4[0:0]$10908
+ attribute \src "libresoc.v:179749.3-179784.6"
+ wire $5\wr_detect$7[0:0]$10924
+ attribute \src "libresoc.v:179585.3-179620.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $6\r1__data_o$next[1:0]$11018
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $6\src11__data_o$next[1:0]$10976
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $6\src21__data_o$next[1:0]$10986
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $6\src31__data_o$next[1:0]$11002
- attribute \src "libresoc.v:180337.3-180382.6"
- wire width 2 $7\r1__data_o$next[1:0]$11019
- attribute \src "libresoc.v:180091.3-180136.6"
- wire width 2 $7\src11__data_o$next[1:0]$10977
- attribute \src "libresoc.v:180173.3-180218.6"
- wire width 2 $7\src21__data_o$next[1:0]$10987
- attribute \src "libresoc.v:180255.3-180300.6"
- wire width 2 $7\src31__data_o$next[1:0]$11003
- attribute \src "libresoc.v:180077.17-180077.104"
- wire $not$libresoc.v:180077$10960_Y
- attribute \src "libresoc.v:180078.17-180078.100"
- wire $not$libresoc.v:180078$10961_Y
- attribute \src "libresoc.v:180079.17-180079.103"
- wire $not$libresoc.v:180079$10962_Y
- attribute \src "libresoc.v:180080.17-180080.103"
- wire $not$libresoc.v:180080$10963_Y
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $6\r1__data_o$next[1:0]$10932
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $6\src11__data_o$next[1:0]$10890
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $6\src21__data_o$next[1:0]$10900
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $6\src31__data_o$next[1:0]$10916
+ attribute \src "libresoc.v:179785.3-179830.6"
+ wire width 2 $7\r1__data_o$next[1:0]$10933
+ attribute \src "libresoc.v:179539.3-179584.6"
+ wire width 2 $7\src11__data_o$next[1:0]$10891
+ attribute \src "libresoc.v:179621.3-179666.6"
+ wire width 2 $7\src21__data_o$next[1:0]$10901
+ attribute \src "libresoc.v:179703.3-179748.6"
+ wire width 2 $7\src31__data_o$next[1:0]$10917
+ attribute \src "libresoc.v:179525.17-179525.104"
+ wire $not$libresoc.v:179525$10874_Y
+ attribute \src "libresoc.v:179526.17-179526.100"
+ wire $not$libresoc.v:179526$10875_Y
+ attribute \src "libresoc.v:179527.17-179527.103"
+ wire $not$libresoc.v:179527$10876_Y
+ attribute \src "libresoc.v:179528.17-179528.103"
+ wire $not$libresoc.v:179528$10877_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest11__data_i
wire width 2 input 13 \dest31__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest31__wen
- attribute \src "libresoc.v:180008.7-180008.15"
+ attribute \src "libresoc.v:179456.7-179456.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r1__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180077$10960
+ cell $not $not$libresoc.v:179525$10874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:180077$10960_Y
+ connect \Y $not$libresoc.v:179525$10874_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180078$10961
+ cell $not $not$libresoc.v:179526$10875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:180078$10961_Y
+ connect \Y $not$libresoc.v:179526$10875_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180079$10962
+ cell $not $not$libresoc.v:179527$10876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:180079$10962_Y
+ connect \Y $not$libresoc.v:179527$10876_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180080$10963
+ cell $not $not$libresoc.v:179528$10877
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:180080$10963_Y
+ connect \Y $not$libresoc.v:179528$10877_Y
end
- attribute \src "libresoc.v:180008.7-180008.20"
- process $proc$libresoc.v:180008$11034
+ attribute \src "libresoc.v:179456.7-179456.20"
+ process $proc$libresoc.v:179456$10948
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:180035.13-180035.30"
- process $proc$libresoc.v:180035$11035
+ attribute \src "libresoc.v:179483.13-179483.30"
+ process $proc$libresoc.v:179483$10949
assign { } { }
assign $1\r1__data_o[1:0] 2'00
sync always
sync init
update \r1__data_o $1\r1__data_o[1:0]
end
- attribute \src "libresoc.v:180041.13-180041.25"
- process $proc$libresoc.v:180041$11036
+ attribute \src "libresoc.v:179489.13-179489.25"
+ process $proc$libresoc.v:179489$10950
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:180046.13-180046.33"
- process $proc$libresoc.v:180046$11037
+ attribute \src "libresoc.v:179494.13-179494.33"
+ process $proc$libresoc.v:179494$10951
assign { } { }
assign $1\src11__data_o[1:0] 2'00
sync always
sync init
update \src11__data_o $1\src11__data_o[1:0]
end
- attribute \src "libresoc.v:180053.13-180053.33"
- process $proc$libresoc.v:180053$11038
+ attribute \src "libresoc.v:179501.13-179501.33"
+ process $proc$libresoc.v:179501$10952
assign { } { }
assign $1\src21__data_o[1:0] 2'00
sync always
sync init
update \src21__data_o $1\src21__data_o[1:0]
end
- attribute \src "libresoc.v:180060.13-180060.33"
- process $proc$libresoc.v:180060$11039
+ attribute \src "libresoc.v:179508.13-179508.33"
+ process $proc$libresoc.v:179508$10953
assign { } { }
assign $1\src31__data_o[1:0] 2'00
sync always
sync init
update \src31__data_o $1\src31__data_o[1:0]
end
- attribute \src "libresoc.v:180081.3-180082.25"
- process $proc$libresoc.v:180081$10964
+ attribute \src "libresoc.v:179529.3-179530.25"
+ process $proc$libresoc.v:179529$10878
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:180083.3-180084.37"
- process $proc$libresoc.v:180083$10965
+ attribute \src "libresoc.v:179531.3-179532.37"
+ process $proc$libresoc.v:179531$10879
assign { } { }
assign $0\r1__data_o[1:0] \r1__data_o$next
sync posedge \coresync_clk
update \r1__data_o $0\r1__data_o[1:0]
end
- attribute \src "libresoc.v:180085.3-180086.43"
- process $proc$libresoc.v:180085$10966
+ attribute \src "libresoc.v:179533.3-179534.43"
+ process $proc$libresoc.v:179533$10880
assign { } { }
assign $0\src31__data_o[1:0] \src31__data_o$next
sync posedge \coresync_clk
update \src31__data_o $0\src31__data_o[1:0]
end
- attribute \src "libresoc.v:180087.3-180088.43"
- process $proc$libresoc.v:180087$10967
+ attribute \src "libresoc.v:179535.3-179536.43"
+ process $proc$libresoc.v:179535$10881
assign { } { }
assign $0\src21__data_o[1:0] \src21__data_o$next
sync posedge \coresync_clk
update \src21__data_o $0\src21__data_o[1:0]
end
- attribute \src "libresoc.v:180089.3-180090.43"
- process $proc$libresoc.v:180089$10968
+ attribute \src "libresoc.v:179537.3-179538.43"
+ process $proc$libresoc.v:179537$10882
assign { } { }
assign $0\src11__data_o[1:0] \src11__data_o$next
sync posedge \coresync_clk
update \src11__data_o $0\src11__data_o[1:0]
end
- attribute \src "libresoc.v:180091.3-180136.6"
- process $proc$libresoc.v:180091$10969
+ attribute \src "libresoc.v:179539.3-179584.6"
+ process $proc$libresoc.v:179539$10883
assign { } { }
assign { } { }
assign { } { }
- assign $0\src11__data_o$next[1:0]$10970 $7\src11__data_o$next[1:0]$10977
- attribute \src "libresoc.v:180092.5-180092.29"
+ assign $0\src11__data_o$next[1:0]$10884 $7\src11__data_o$next[1:0]$10891
+ attribute \src "libresoc.v:179540.5-179540.29"
switch \initial
- attribute \src "libresoc.v:180092.9-180092.17"
+ attribute \src "libresoc.v:179540.9-179540.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src11__data_o$next[1:0]$10971 $6\src11__data_o$next[1:0]$10976
+ assign $1\src11__data_o$next[1:0]$10885 $6\src11__data_o$next[1:0]$10890
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src11__data_o$next[1:0]$10972 \dest11__data_i
+ assign $2\src11__data_o$next[1:0]$10886 \dest11__data_i
case
- assign $2\src11__data_o$next[1:0]$10972 2'00
+ assign $2\src11__data_o$next[1:0]$10886 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src11__data_o$next[1:0]$10973 \dest21__data_i
+ assign $3\src11__data_o$next[1:0]$10887 \dest21__data_i
case
- assign $3\src11__data_o$next[1:0]$10973 $2\src11__data_o$next[1:0]$10972
+ assign $3\src11__data_o$next[1:0]$10887 $2\src11__data_o$next[1:0]$10886
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src11__data_o$next[1:0]$10974 \dest31__data_i
+ assign $4\src11__data_o$next[1:0]$10888 \dest31__data_i
case
- assign $4\src11__data_o$next[1:0]$10974 $3\src11__data_o$next[1:0]$10973
+ assign $4\src11__data_o$next[1:0]$10888 $3\src11__data_o$next[1:0]$10887
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src11__data_o$next[1:0]$10975 \w1__data_i
+ assign $5\src11__data_o$next[1:0]$10889 \w1__data_i
case
- assign $5\src11__data_o$next[1:0]$10975 $4\src11__data_o$next[1:0]$10974
+ assign $5\src11__data_o$next[1:0]$10889 $4\src11__data_o$next[1:0]$10888
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src11__data_o$next[1:0]$10976 \reg
+ assign $6\src11__data_o$next[1:0]$10890 \reg
case
- assign $6\src11__data_o$next[1:0]$10976 $5\src11__data_o$next[1:0]$10975
+ assign $6\src11__data_o$next[1:0]$10890 $5\src11__data_o$next[1:0]$10889
end
case
- assign $1\src11__data_o$next[1:0]$10971 2'00
+ assign $1\src11__data_o$next[1:0]$10885 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src11__data_o$next[1:0]$10977 2'00
+ assign $7\src11__data_o$next[1:0]$10891 2'00
case
- assign $7\src11__data_o$next[1:0]$10977 $1\src11__data_o$next[1:0]$10971
+ assign $7\src11__data_o$next[1:0]$10891 $1\src11__data_o$next[1:0]$10885
end
sync always
- update \src11__data_o$next $0\src11__data_o$next[1:0]$10970
+ update \src11__data_o$next $0\src11__data_o$next[1:0]$10884
end
- attribute \src "libresoc.v:180137.3-180172.6"
- process $proc$libresoc.v:180137$10978
+ attribute \src "libresoc.v:179585.3-179620.6"
+ process $proc$libresoc.v:179585$10892
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:180138.5-180138.29"
+ attribute \src "libresoc.v:179586.5-179586.29"
switch \initial
- attribute \src "libresoc.v:180138.9-180138.17"
+ attribute \src "libresoc.v:179586.9-179586.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:180173.3-180218.6"
- process $proc$libresoc.v:180173$10979
+ attribute \src "libresoc.v:179621.3-179666.6"
+ process $proc$libresoc.v:179621$10893
assign { } { }
assign { } { }
assign { } { }
- assign $0\src21__data_o$next[1:0]$10980 $7\src21__data_o$next[1:0]$10987
- attribute \src "libresoc.v:180174.5-180174.29"
+ assign $0\src21__data_o$next[1:0]$10894 $7\src21__data_o$next[1:0]$10901
+ attribute \src "libresoc.v:179622.5-179622.29"
switch \initial
- attribute \src "libresoc.v:180174.9-180174.17"
+ attribute \src "libresoc.v:179622.9-179622.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src21__data_o$next[1:0]$10981 $6\src21__data_o$next[1:0]$10986
+ assign $1\src21__data_o$next[1:0]$10895 $6\src21__data_o$next[1:0]$10900
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src21__data_o$next[1:0]$10982 \dest11__data_i
+ assign $2\src21__data_o$next[1:0]$10896 \dest11__data_i
case
- assign $2\src21__data_o$next[1:0]$10982 2'00
+ assign $2\src21__data_o$next[1:0]$10896 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src21__data_o$next[1:0]$10983 \dest21__data_i
+ assign $3\src21__data_o$next[1:0]$10897 \dest21__data_i
case
- assign $3\src21__data_o$next[1:0]$10983 $2\src21__data_o$next[1:0]$10982
+ assign $3\src21__data_o$next[1:0]$10897 $2\src21__data_o$next[1:0]$10896
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src21__data_o$next[1:0]$10984 \dest31__data_i
+ assign $4\src21__data_o$next[1:0]$10898 \dest31__data_i
case
- assign $4\src21__data_o$next[1:0]$10984 $3\src21__data_o$next[1:0]$10983
+ assign $4\src21__data_o$next[1:0]$10898 $3\src21__data_o$next[1:0]$10897
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src21__data_o$next[1:0]$10985 \w1__data_i
+ assign $5\src21__data_o$next[1:0]$10899 \w1__data_i
case
- assign $5\src21__data_o$next[1:0]$10985 $4\src21__data_o$next[1:0]$10984
+ assign $5\src21__data_o$next[1:0]$10899 $4\src21__data_o$next[1:0]$10898
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src21__data_o$next[1:0]$10986 \reg
+ assign $6\src21__data_o$next[1:0]$10900 \reg
case
- assign $6\src21__data_o$next[1:0]$10986 $5\src21__data_o$next[1:0]$10985
+ assign $6\src21__data_o$next[1:0]$10900 $5\src21__data_o$next[1:0]$10899
end
case
- assign $1\src21__data_o$next[1:0]$10981 2'00
+ assign $1\src21__data_o$next[1:0]$10895 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src21__data_o$next[1:0]$10987 2'00
+ assign $7\src21__data_o$next[1:0]$10901 2'00
case
- assign $7\src21__data_o$next[1:0]$10987 $1\src21__data_o$next[1:0]$10981
+ assign $7\src21__data_o$next[1:0]$10901 $1\src21__data_o$next[1:0]$10895
end
sync always
- update \src21__data_o$next $0\src21__data_o$next[1:0]$10980
+ update \src21__data_o$next $0\src21__data_o$next[1:0]$10894
end
- attribute \src "libresoc.v:180219.3-180254.6"
- process $proc$libresoc.v:180219$10988
+ attribute \src "libresoc.v:179667.3-179702.6"
+ process $proc$libresoc.v:179667$10902
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10989 $1\wr_detect$4[0:0]$10990
- attribute \src "libresoc.v:180220.5-180220.29"
+ assign $0\wr_detect$4[0:0]$10903 $1\wr_detect$4[0:0]$10904
+ attribute \src "libresoc.v:179668.5-179668.29"
switch \initial
- attribute \src "libresoc.v:180220.9-180220.17"
+ attribute \src "libresoc.v:179668.9-179668.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10990 $5\wr_detect$4[0:0]$10994
+ assign $1\wr_detect$4[0:0]$10904 $5\wr_detect$4[0:0]$10908
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10991 1'1
+ assign $2\wr_detect$4[0:0]$10905 1'1
case
- assign $2\wr_detect$4[0:0]$10991 1'0
+ assign $2\wr_detect$4[0:0]$10905 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10992 1'1
+ assign $3\wr_detect$4[0:0]$10906 1'1
case
- assign $3\wr_detect$4[0:0]$10992 $2\wr_detect$4[0:0]$10991
+ assign $3\wr_detect$4[0:0]$10906 $2\wr_detect$4[0:0]$10905
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10993 1'1
+ assign $4\wr_detect$4[0:0]$10907 1'1
case
- assign $4\wr_detect$4[0:0]$10993 $3\wr_detect$4[0:0]$10992
+ assign $4\wr_detect$4[0:0]$10907 $3\wr_detect$4[0:0]$10906
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10994 1'1
+ assign $5\wr_detect$4[0:0]$10908 1'1
case
- assign $5\wr_detect$4[0:0]$10994 $4\wr_detect$4[0:0]$10993
+ assign $5\wr_detect$4[0:0]$10908 $4\wr_detect$4[0:0]$10907
end
case
- assign $1\wr_detect$4[0:0]$10990 1'0
+ assign $1\wr_detect$4[0:0]$10904 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10989
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10903
end
- attribute \src "libresoc.v:180255.3-180300.6"
- process $proc$libresoc.v:180255$10995
+ attribute \src "libresoc.v:179703.3-179748.6"
+ process $proc$libresoc.v:179703$10909
assign { } { }
assign { } { }
assign { } { }
- assign $0\src31__data_o$next[1:0]$10996 $7\src31__data_o$next[1:0]$11003
- attribute \src "libresoc.v:180256.5-180256.29"
+ assign $0\src31__data_o$next[1:0]$10910 $7\src31__data_o$next[1:0]$10917
+ attribute \src "libresoc.v:179704.5-179704.29"
switch \initial
- attribute \src "libresoc.v:180256.9-180256.17"
+ attribute \src "libresoc.v:179704.9-179704.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src31__data_o$next[1:0]$10997 $6\src31__data_o$next[1:0]$11002
+ assign $1\src31__data_o$next[1:0]$10911 $6\src31__data_o$next[1:0]$10916
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src31__data_o$next[1:0]$10998 \dest11__data_i
+ assign $2\src31__data_o$next[1:0]$10912 \dest11__data_i
case
- assign $2\src31__data_o$next[1:0]$10998 2'00
+ assign $2\src31__data_o$next[1:0]$10912 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src31__data_o$next[1:0]$10999 \dest21__data_i
+ assign $3\src31__data_o$next[1:0]$10913 \dest21__data_i
case
- assign $3\src31__data_o$next[1:0]$10999 $2\src31__data_o$next[1:0]$10998
+ assign $3\src31__data_o$next[1:0]$10913 $2\src31__data_o$next[1:0]$10912
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src31__data_o$next[1:0]$11000 \dest31__data_i
+ assign $4\src31__data_o$next[1:0]$10914 \dest31__data_i
case
- assign $4\src31__data_o$next[1:0]$11000 $3\src31__data_o$next[1:0]$10999
+ assign $4\src31__data_o$next[1:0]$10914 $3\src31__data_o$next[1:0]$10913
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src31__data_o$next[1:0]$11001 \w1__data_i
+ assign $5\src31__data_o$next[1:0]$10915 \w1__data_i
case
- assign $5\src31__data_o$next[1:0]$11001 $4\src31__data_o$next[1:0]$11000
+ assign $5\src31__data_o$next[1:0]$10915 $4\src31__data_o$next[1:0]$10914
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src31__data_o$next[1:0]$11002 \reg
+ assign $6\src31__data_o$next[1:0]$10916 \reg
case
- assign $6\src31__data_o$next[1:0]$11002 $5\src31__data_o$next[1:0]$11001
+ assign $6\src31__data_o$next[1:0]$10916 $5\src31__data_o$next[1:0]$10915
end
case
- assign $1\src31__data_o$next[1:0]$10997 2'00
+ assign $1\src31__data_o$next[1:0]$10911 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src31__data_o$next[1:0]$11003 2'00
+ assign $7\src31__data_o$next[1:0]$10917 2'00
case
- assign $7\src31__data_o$next[1:0]$11003 $1\src31__data_o$next[1:0]$10997
+ assign $7\src31__data_o$next[1:0]$10917 $1\src31__data_o$next[1:0]$10911
end
sync always
- update \src31__data_o$next $0\src31__data_o$next[1:0]$10996
+ update \src31__data_o$next $0\src31__data_o$next[1:0]$10910
end
- attribute \src "libresoc.v:180301.3-180336.6"
- process $proc$libresoc.v:180301$11004
+ attribute \src "libresoc.v:179749.3-179784.6"
+ process $proc$libresoc.v:179749$10918
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11005 $1\wr_detect$7[0:0]$11006
- attribute \src "libresoc.v:180302.5-180302.29"
+ assign $0\wr_detect$7[0:0]$10919 $1\wr_detect$7[0:0]$10920
+ attribute \src "libresoc.v:179750.5-179750.29"
switch \initial
- attribute \src "libresoc.v:180302.9-180302.17"
+ attribute \src "libresoc.v:179750.9-179750.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11006 $5\wr_detect$7[0:0]$11010
+ assign $1\wr_detect$7[0:0]$10920 $5\wr_detect$7[0:0]$10924
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11007 1'1
+ assign $2\wr_detect$7[0:0]$10921 1'1
case
- assign $2\wr_detect$7[0:0]$11007 1'0
+ assign $2\wr_detect$7[0:0]$10921 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11008 1'1
+ assign $3\wr_detect$7[0:0]$10922 1'1
case
- assign $3\wr_detect$7[0:0]$11008 $2\wr_detect$7[0:0]$11007
+ assign $3\wr_detect$7[0:0]$10922 $2\wr_detect$7[0:0]$10921
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11009 1'1
+ assign $4\wr_detect$7[0:0]$10923 1'1
case
- assign $4\wr_detect$7[0:0]$11009 $3\wr_detect$7[0:0]$11008
+ assign $4\wr_detect$7[0:0]$10923 $3\wr_detect$7[0:0]$10922
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11010 1'1
+ assign $5\wr_detect$7[0:0]$10924 1'1
case
- assign $5\wr_detect$7[0:0]$11010 $4\wr_detect$7[0:0]$11009
+ assign $5\wr_detect$7[0:0]$10924 $4\wr_detect$7[0:0]$10923
end
case
- assign $1\wr_detect$7[0:0]$11006 1'0
+ assign $1\wr_detect$7[0:0]$10920 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11005
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10919
end
- attribute \src "libresoc.v:180337.3-180382.6"
- process $proc$libresoc.v:180337$11011
+ attribute \src "libresoc.v:179785.3-179830.6"
+ process $proc$libresoc.v:179785$10925
assign { } { }
assign { } { }
assign { } { }
- assign $0\r1__data_o$next[1:0]$11012 $7\r1__data_o$next[1:0]$11019
- attribute \src "libresoc.v:180338.5-180338.29"
+ assign $0\r1__data_o$next[1:0]$10926 $7\r1__data_o$next[1:0]$10933
+ attribute \src "libresoc.v:179786.5-179786.29"
switch \initial
- attribute \src "libresoc.v:180338.9-180338.17"
+ attribute \src "libresoc.v:179786.9-179786.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r1__data_o$next[1:0]$11013 $6\r1__data_o$next[1:0]$11018
+ assign $1\r1__data_o$next[1:0]$10927 $6\r1__data_o$next[1:0]$10932
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r1__data_o$next[1:0]$11014 \dest11__data_i
+ assign $2\r1__data_o$next[1:0]$10928 \dest11__data_i
case
- assign $2\r1__data_o$next[1:0]$11014 2'00
+ assign $2\r1__data_o$next[1:0]$10928 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r1__data_o$next[1:0]$11015 \dest21__data_i
+ assign $3\r1__data_o$next[1:0]$10929 \dest21__data_i
case
- assign $3\r1__data_o$next[1:0]$11015 $2\r1__data_o$next[1:0]$11014
+ assign $3\r1__data_o$next[1:0]$10929 $2\r1__data_o$next[1:0]$10928
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r1__data_o$next[1:0]$11016 \dest31__data_i
+ assign $4\r1__data_o$next[1:0]$10930 \dest31__data_i
case
- assign $4\r1__data_o$next[1:0]$11016 $3\r1__data_o$next[1:0]$11015
+ assign $4\r1__data_o$next[1:0]$10930 $3\r1__data_o$next[1:0]$10929
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r1__data_o$next[1:0]$11017 \w1__data_i
+ assign $5\r1__data_o$next[1:0]$10931 \w1__data_i
case
- assign $5\r1__data_o$next[1:0]$11017 $4\r1__data_o$next[1:0]$11016
+ assign $5\r1__data_o$next[1:0]$10931 $4\r1__data_o$next[1:0]$10930
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r1__data_o$next[1:0]$11018 \reg
+ assign $6\r1__data_o$next[1:0]$10932 \reg
case
- assign $6\r1__data_o$next[1:0]$11018 $5\r1__data_o$next[1:0]$11017
+ assign $6\r1__data_o$next[1:0]$10932 $5\r1__data_o$next[1:0]$10931
end
case
- assign $1\r1__data_o$next[1:0]$11013 2'00
+ assign $1\r1__data_o$next[1:0]$10927 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r1__data_o$next[1:0]$11019 2'00
+ assign $7\r1__data_o$next[1:0]$10933 2'00
case
- assign $7\r1__data_o$next[1:0]$11019 $1\r1__data_o$next[1:0]$11013
+ assign $7\r1__data_o$next[1:0]$10933 $1\r1__data_o$next[1:0]$10927
end
sync always
- update \r1__data_o$next $0\r1__data_o$next[1:0]$11012
+ update \r1__data_o$next $0\r1__data_o$next[1:0]$10926
end
- attribute \src "libresoc.v:180383.3-180418.6"
- process $proc$libresoc.v:180383$11020
+ attribute \src "libresoc.v:179831.3-179866.6"
+ process $proc$libresoc.v:179831$10934
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11021 $1\wr_detect$10[0:0]$11022
- attribute \src "libresoc.v:180384.5-180384.29"
+ assign $0\wr_detect$10[0:0]$10935 $1\wr_detect$10[0:0]$10936
+ attribute \src "libresoc.v:179832.5-179832.29"
switch \initial
- attribute \src "libresoc.v:180384.9-180384.17"
+ attribute \src "libresoc.v:179832.9-179832.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11022 $5\wr_detect$10[0:0]$11026
+ assign $1\wr_detect$10[0:0]$10936 $5\wr_detect$10[0:0]$10940
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11023 1'1
+ assign $2\wr_detect$10[0:0]$10937 1'1
case
- assign $2\wr_detect$10[0:0]$11023 1'0
+ assign $2\wr_detect$10[0:0]$10937 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11024 1'1
+ assign $3\wr_detect$10[0:0]$10938 1'1
case
- assign $3\wr_detect$10[0:0]$11024 $2\wr_detect$10[0:0]$11023
+ assign $3\wr_detect$10[0:0]$10938 $2\wr_detect$10[0:0]$10937
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11025 1'1
+ assign $4\wr_detect$10[0:0]$10939 1'1
case
- assign $4\wr_detect$10[0:0]$11025 $3\wr_detect$10[0:0]$11024
+ assign $4\wr_detect$10[0:0]$10939 $3\wr_detect$10[0:0]$10938
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$11026 1'1
+ assign $5\wr_detect$10[0:0]$10940 1'1
case
- assign $5\wr_detect$10[0:0]$11026 $4\wr_detect$10[0:0]$11025
+ assign $5\wr_detect$10[0:0]$10940 $4\wr_detect$10[0:0]$10939
end
case
- assign $1\wr_detect$10[0:0]$11022 1'0
+ assign $1\wr_detect$10[0:0]$10936 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11021
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10935
end
- attribute \src "libresoc.v:180419.3-180451.6"
- process $proc$libresoc.v:180419$11027
+ attribute \src "libresoc.v:179867.3-179899.6"
+ process $proc$libresoc.v:179867$10941
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$11028 $5\reg$next[1:0]$11033
- attribute \src "libresoc.v:180420.5-180420.29"
+ assign $0\reg$next[1:0]$10942 $5\reg$next[1:0]$10947
+ attribute \src "libresoc.v:179868.5-179868.29"
switch \initial
- attribute \src "libresoc.v:180420.9-180420.17"
+ attribute \src "libresoc.v:179868.9-179868.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$11029 \dest11__data_i
+ assign $1\reg$next[1:0]$10943 \dest11__data_i
case
- assign $1\reg$next[1:0]$11029 \reg
+ assign $1\reg$next[1:0]$10943 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$11030 \dest21__data_i
+ assign $2\reg$next[1:0]$10944 \dest21__data_i
case
- assign $2\reg$next[1:0]$11030 $1\reg$next[1:0]$11029
+ assign $2\reg$next[1:0]$10944 $1\reg$next[1:0]$10943
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$11031 \dest31__data_i
+ assign $3\reg$next[1:0]$10945 \dest31__data_i
case
- assign $3\reg$next[1:0]$11031 $2\reg$next[1:0]$11030
+ assign $3\reg$next[1:0]$10945 $2\reg$next[1:0]$10944
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$11032 \w1__data_i
+ assign $4\reg$next[1:0]$10946 \w1__data_i
case
- assign $4\reg$next[1:0]$11032 $3\reg$next[1:0]$11031
+ assign $4\reg$next[1:0]$10946 $3\reg$next[1:0]$10945
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$11033 2'00
+ assign $5\reg$next[1:0]$10947 2'00
case
- assign $5\reg$next[1:0]$11033 $4\reg$next[1:0]$11032
+ assign $5\reg$next[1:0]$10947 $4\reg$next[1:0]$10946
end
sync always
- update \reg$next $0\reg$next[1:0]$11028
+ update \reg$next $0\reg$next[1:0]$10942
end
- connect \$9 $not$libresoc.v:180077$10960_Y
- connect \$1 $not$libresoc.v:180078$10961_Y
- connect \$3 $not$libresoc.v:180079$10962_Y
- connect \$6 $not$libresoc.v:180080$10963_Y
+ connect \$9 $not$libresoc.v:179525$10874_Y
+ connect \$1 $not$libresoc.v:179526$10875_Y
+ connect \$3 $not$libresoc.v:179527$10876_Y
+ connect \$6 $not$libresoc.v:179528$10877_Y
end
-attribute \src "libresoc.v:180456.1-180805.10"
+attribute \src "libresoc.v:179904.1-180253.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1"
attribute \generator "nMigen"
module \reg_1$136
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $0\cia1__data_o$next[63:0]$11048
- attribute \src "libresoc.v:180524.3-180525.41"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $0\cia1__data_o$next[63:0]$10962
+ attribute \src "libresoc.v:179972.3-179973.41"
wire width 64 $0\cia1__data_o[63:0]
- attribute \src "libresoc.v:180457.7-180457.20"
+ attribute \src "libresoc.v:179905.7-179905.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $0\msr1__data_o$next[63:0]$11058
- attribute \src "libresoc.v:180522.3-180523.41"
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $0\msr1__data_o$next[63:0]$10972
+ attribute \src "libresoc.v:179970.3-179971.41"
wire width 64 $0\msr1__data_o[63:0]
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $0\reg$next[63:0]$11090
- attribute \src "libresoc.v:180518.3-180519.25"
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $0\reg$next[63:0]$11004
+ attribute \src "libresoc.v:179966.3-179967.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $0\sv1__data_o$next[63:0]$11074
- attribute \src "libresoc.v:180520.3-180521.39"
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $0\sv1__data_o$next[63:0]$10988
+ attribute \src "libresoc.v:179968.3-179969.39"
wire width 64 $0\sv1__data_o[63:0]
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $0\wr_detect$4[0:0]$11067
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $0\wr_detect$7[0:0]$11083
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $0\wr_detect$4[0:0]$10981
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $0\wr_detect$7[0:0]$10997
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $1\cia1__data_o$next[63:0]$11049
- attribute \src "libresoc.v:180466.14-180466.49"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $1\cia1__data_o$next[63:0]$10963
+ attribute \src "libresoc.v:179914.14-179914.49"
wire width 64 $1\cia1__data_o[63:0]
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $1\msr1__data_o$next[63:0]$11059
- attribute \src "libresoc.v:180483.14-180483.49"
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $1\msr1__data_o$next[63:0]$10973
+ attribute \src "libresoc.v:179931.14-179931.49"
wire width 64 $1\msr1__data_o[63:0]
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $1\reg$next[63:0]$11091
- attribute \src "libresoc.v:180495.14-180495.42"
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $1\reg$next[63:0]$11005
+ attribute \src "libresoc.v:179943.14-179943.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $1\sv1__data_o$next[63:0]$11075
- attribute \src "libresoc.v:180502.14-180502.48"
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $1\sv1__data_o$next[63:0]$10989
+ attribute \src "libresoc.v:179950.14-179950.48"
wire width 64 $1\sv1__data_o[63:0]
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $1\wr_detect$4[0:0]$11068
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $1\wr_detect$7[0:0]$11084
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $1\wr_detect$4[0:0]$10982
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $1\wr_detect$7[0:0]$10998
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $2\cia1__data_o$next[63:0]$11050
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $2\msr1__data_o$next[63:0]$11060
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $2\reg$next[63:0]$11092
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $2\sv1__data_o$next[63:0]$11076
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $2\wr_detect$4[0:0]$11069
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $2\wr_detect$7[0:0]$11085
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $2\cia1__data_o$next[63:0]$10964
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $2\msr1__data_o$next[63:0]$10974
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $2\reg$next[63:0]$11006
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $2\sv1__data_o$next[63:0]$10990
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $2\wr_detect$4[0:0]$10983
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $2\wr_detect$7[0:0]$10999
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $3\cia1__data_o$next[63:0]$11051
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $3\msr1__data_o$next[63:0]$11061
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $3\reg$next[63:0]$11093
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $3\sv1__data_o$next[63:0]$11077
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $3\wr_detect$4[0:0]$11070
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $3\wr_detect$7[0:0]$11086
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $3\cia1__data_o$next[63:0]$10965
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $3\msr1__data_o$next[63:0]$10975
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $3\reg$next[63:0]$11007
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $3\sv1__data_o$next[63:0]$10991
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $3\wr_detect$4[0:0]$10984
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $3\wr_detect$7[0:0]$11000
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $4\cia1__data_o$next[63:0]$11052
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $4\msr1__data_o$next[63:0]$11062
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $4\reg$next[63:0]$11094
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $4\sv1__data_o$next[63:0]$11078
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $4\wr_detect$4[0:0]$11071
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $4\wr_detect$7[0:0]$11087
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $4\cia1__data_o$next[63:0]$10966
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $4\msr1__data_o$next[63:0]$10976
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $4\reg$next[63:0]$11008
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $4\sv1__data_o$next[63:0]$10992
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $4\wr_detect$4[0:0]$10985
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $4\wr_detect$7[0:0]$11001
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $5\cia1__data_o$next[63:0]$11053
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $5\msr1__data_o$next[63:0]$11063
- attribute \src "libresoc.v:180772.3-180804.6"
- wire width 64 $5\reg$next[63:0]$11095
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $5\sv1__data_o$next[63:0]$11079
- attribute \src "libresoc.v:180654.3-180689.6"
- wire $5\wr_detect$4[0:0]$11072
- attribute \src "libresoc.v:180736.3-180771.6"
- wire $5\wr_detect$7[0:0]$11088
- attribute \src "libresoc.v:180572.3-180607.6"
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $5\cia1__data_o$next[63:0]$10967
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $5\msr1__data_o$next[63:0]$10977
+ attribute \src "libresoc.v:180220.3-180252.6"
+ wire width 64 $5\reg$next[63:0]$11009
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $5\sv1__data_o$next[63:0]$10993
+ attribute \src "libresoc.v:180102.3-180137.6"
+ wire $5\wr_detect$4[0:0]$10986
+ attribute \src "libresoc.v:180184.3-180219.6"
+ wire $5\wr_detect$7[0:0]$11002
+ attribute \src "libresoc.v:180020.3-180055.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $6\cia1__data_o$next[63:0]$11054
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $6\msr1__data_o$next[63:0]$11064
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $6\sv1__data_o$next[63:0]$11080
- attribute \src "libresoc.v:180526.3-180571.6"
- wire width 64 $7\cia1__data_o$next[63:0]$11055
- attribute \src "libresoc.v:180608.3-180653.6"
- wire width 64 $7\msr1__data_o$next[63:0]$11065
- attribute \src "libresoc.v:180690.3-180735.6"
- wire width 64 $7\sv1__data_o$next[63:0]$11081
- attribute \src "libresoc.v:180515.17-180515.100"
- wire $not$libresoc.v:180515$11040_Y
- attribute \src "libresoc.v:180516.17-180516.103"
- wire $not$libresoc.v:180516$11041_Y
- attribute \src "libresoc.v:180517.17-180517.103"
- wire $not$libresoc.v:180517$11042_Y
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $6\cia1__data_o$next[63:0]$10968
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $6\msr1__data_o$next[63:0]$10978
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $6\sv1__data_o$next[63:0]$10994
+ attribute \src "libresoc.v:179974.3-180019.6"
+ wire width 64 $7\cia1__data_o$next[63:0]$10969
+ attribute \src "libresoc.v:180056.3-180101.6"
+ wire width 64 $7\msr1__data_o$next[63:0]$10979
+ attribute \src "libresoc.v:180138.3-180183.6"
+ wire width 64 $7\sv1__data_o$next[63:0]$10995
+ attribute \src "libresoc.v:179963.17-179963.100"
+ wire $not$libresoc.v:179963$10954_Y
+ attribute \src "libresoc.v:179964.17-179964.103"
+ wire $not$libresoc.v:179964$10955_Y
+ attribute \src "libresoc.v:179965.17-179965.103"
+ wire $not$libresoc.v:179965$10956_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia1__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia1__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr11__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr11__wen
- attribute \src "libresoc.v:180457.7-180457.15"
+ attribute \src "libresoc.v:179905.7-179905.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr1__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180515$11040
+ cell $not $not$libresoc.v:179963$10954
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:180515$11040_Y
+ connect \Y $not$libresoc.v:179963$10954_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180516$11041
+ cell $not $not$libresoc.v:179964$10955
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:180516$11041_Y
+ connect \Y $not$libresoc.v:179964$10955_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180517$11042
+ cell $not $not$libresoc.v:179965$10956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:180517$11042_Y
+ connect \Y $not$libresoc.v:179965$10956_Y
end
- attribute \src "libresoc.v:180457.7-180457.20"
- process $proc$libresoc.v:180457$11096
+ attribute \src "libresoc.v:179905.7-179905.20"
+ process $proc$libresoc.v:179905$11010
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:180466.14-180466.49"
- process $proc$libresoc.v:180466$11097
+ attribute \src "libresoc.v:179914.14-179914.49"
+ process $proc$libresoc.v:179914$11011
assign { } { }
assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia1__data_o $1\cia1__data_o[63:0]
end
- attribute \src "libresoc.v:180483.14-180483.49"
- process $proc$libresoc.v:180483$11098
+ attribute \src "libresoc.v:179931.14-179931.49"
+ process $proc$libresoc.v:179931$11012
assign { } { }
assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr1__data_o $1\msr1__data_o[63:0]
end
- attribute \src "libresoc.v:180495.14-180495.42"
- process $proc$libresoc.v:180495$11099
+ attribute \src "libresoc.v:179943.14-179943.42"
+ process $proc$libresoc.v:179943$11013
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:180502.14-180502.48"
- process $proc$libresoc.v:180502$11100
+ attribute \src "libresoc.v:179950.14-179950.48"
+ process $proc$libresoc.v:179950$11014
assign { } { }
assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv1__data_o $1\sv1__data_o[63:0]
end
- attribute \src "libresoc.v:180518.3-180519.25"
- process $proc$libresoc.v:180518$11043
+ attribute \src "libresoc.v:179966.3-179967.25"
+ process $proc$libresoc.v:179966$10957
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:180520.3-180521.39"
- process $proc$libresoc.v:180520$11044
+ attribute \src "libresoc.v:179968.3-179969.39"
+ process $proc$libresoc.v:179968$10958
assign { } { }
assign $0\sv1__data_o[63:0] \sv1__data_o$next
sync posedge \coresync_clk
update \sv1__data_o $0\sv1__data_o[63:0]
end
- attribute \src "libresoc.v:180522.3-180523.41"
- process $proc$libresoc.v:180522$11045
+ attribute \src "libresoc.v:179970.3-179971.41"
+ process $proc$libresoc.v:179970$10959
assign { } { }
assign $0\msr1__data_o[63:0] \msr1__data_o$next
sync posedge \coresync_clk
update \msr1__data_o $0\msr1__data_o[63:0]
end
- attribute \src "libresoc.v:180524.3-180525.41"
- process $proc$libresoc.v:180524$11046
+ attribute \src "libresoc.v:179972.3-179973.41"
+ process $proc$libresoc.v:179972$10960
assign { } { }
assign $0\cia1__data_o[63:0] \cia1__data_o$next
sync posedge \coresync_clk
update \cia1__data_o $0\cia1__data_o[63:0]
end
- attribute \src "libresoc.v:180526.3-180571.6"
- process $proc$libresoc.v:180526$11047
+ attribute \src "libresoc.v:179974.3-180019.6"
+ process $proc$libresoc.v:179974$10961
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia1__data_o$next[63:0]$11048 $7\cia1__data_o$next[63:0]$11055
- attribute \src "libresoc.v:180527.5-180527.29"
+ assign $0\cia1__data_o$next[63:0]$10962 $7\cia1__data_o$next[63:0]$10969
+ attribute \src "libresoc.v:179975.5-179975.29"
switch \initial
- attribute \src "libresoc.v:180527.9-180527.17"
+ attribute \src "libresoc.v:179975.9-179975.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia1__data_o$next[63:0]$11049 $6\cia1__data_o$next[63:0]$11054
+ assign $1\cia1__data_o$next[63:0]$10963 $6\cia1__data_o$next[63:0]$10968
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia1__data_o$next[63:0]$11050 \nia1__data_i
+ assign $2\cia1__data_o$next[63:0]$10964 \nia1__data_i
case
- assign $2\cia1__data_o$next[63:0]$11050 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia1__data_o$next[63:0]$10964 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia1__data_o$next[63:0]$11051 \msr1__data_i
+ assign $3\cia1__data_o$next[63:0]$10965 \msr1__data_i
case
- assign $3\cia1__data_o$next[63:0]$11051 $2\cia1__data_o$next[63:0]$11050
+ assign $3\cia1__data_o$next[63:0]$10965 $2\cia1__data_o$next[63:0]$10964
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia1__data_o$next[63:0]$11052 \sv1__data_i
+ assign $4\cia1__data_o$next[63:0]$10966 \sv1__data_i
case
- assign $4\cia1__data_o$next[63:0]$11052 $3\cia1__data_o$next[63:0]$11051
+ assign $4\cia1__data_o$next[63:0]$10966 $3\cia1__data_o$next[63:0]$10965
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia1__data_o$next[63:0]$11053 \d_wr11__data_i
+ assign $5\cia1__data_o$next[63:0]$10967 \d_wr11__data_i
case
- assign $5\cia1__data_o$next[63:0]$11053 $4\cia1__data_o$next[63:0]$11052
+ assign $5\cia1__data_o$next[63:0]$10967 $4\cia1__data_o$next[63:0]$10966
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia1__data_o$next[63:0]$11054 \reg
+ assign $6\cia1__data_o$next[63:0]$10968 \reg
case
- assign $6\cia1__data_o$next[63:0]$11054 $5\cia1__data_o$next[63:0]$11053
+ assign $6\cia1__data_o$next[63:0]$10968 $5\cia1__data_o$next[63:0]$10967
end
case
- assign $1\cia1__data_o$next[63:0]$11049 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia1__data_o$next[63:0]$11055 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia1__data_o$next[63:0]$10969 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia1__data_o$next[63:0]$11055 $1\cia1__data_o$next[63:0]$11049
+ assign $7\cia1__data_o$next[63:0]$10969 $1\cia1__data_o$next[63:0]$10963
end
sync always
- update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11048
+ update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10962
end
- attribute \src "libresoc.v:180572.3-180607.6"
- process $proc$libresoc.v:180572$11056
+ attribute \src "libresoc.v:180020.3-180055.6"
+ process $proc$libresoc.v:180020$10970
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:180573.5-180573.29"
+ attribute \src "libresoc.v:180021.5-180021.29"
switch \initial
- attribute \src "libresoc.v:180573.9-180573.17"
+ attribute \src "libresoc.v:180021.9-180021.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:180608.3-180653.6"
- process $proc$libresoc.v:180608$11057
+ attribute \src "libresoc.v:180056.3-180101.6"
+ process $proc$libresoc.v:180056$10971
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr1__data_o$next[63:0]$11058 $7\msr1__data_o$next[63:0]$11065
- attribute \src "libresoc.v:180609.5-180609.29"
+ assign $0\msr1__data_o$next[63:0]$10972 $7\msr1__data_o$next[63:0]$10979
+ attribute \src "libresoc.v:180057.5-180057.29"
switch \initial
- attribute \src "libresoc.v:180609.9-180609.17"
+ attribute \src "libresoc.v:180057.9-180057.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr1__data_o$next[63:0]$11059 $6\msr1__data_o$next[63:0]$11064
+ assign $1\msr1__data_o$next[63:0]$10973 $6\msr1__data_o$next[63:0]$10978
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr1__data_o$next[63:0]$11060 \nia1__data_i
+ assign $2\msr1__data_o$next[63:0]$10974 \nia1__data_i
case
- assign $2\msr1__data_o$next[63:0]$11060 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr1__data_o$next[63:0]$10974 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr1__data_o$next[63:0]$11061 \msr1__data_i
+ assign $3\msr1__data_o$next[63:0]$10975 \msr1__data_i
case
- assign $3\msr1__data_o$next[63:0]$11061 $2\msr1__data_o$next[63:0]$11060
+ assign $3\msr1__data_o$next[63:0]$10975 $2\msr1__data_o$next[63:0]$10974
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr1__data_o$next[63:0]$11062 \sv1__data_i
+ assign $4\msr1__data_o$next[63:0]$10976 \sv1__data_i
case
- assign $4\msr1__data_o$next[63:0]$11062 $3\msr1__data_o$next[63:0]$11061
+ assign $4\msr1__data_o$next[63:0]$10976 $3\msr1__data_o$next[63:0]$10975
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr1__data_o$next[63:0]$11063 \d_wr11__data_i
+ assign $5\msr1__data_o$next[63:0]$10977 \d_wr11__data_i
case
- assign $5\msr1__data_o$next[63:0]$11063 $4\msr1__data_o$next[63:0]$11062
+ assign $5\msr1__data_o$next[63:0]$10977 $4\msr1__data_o$next[63:0]$10976
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr1__data_o$next[63:0]$11064 \reg
+ assign $6\msr1__data_o$next[63:0]$10978 \reg
case
- assign $6\msr1__data_o$next[63:0]$11064 $5\msr1__data_o$next[63:0]$11063
+ assign $6\msr1__data_o$next[63:0]$10978 $5\msr1__data_o$next[63:0]$10977
end
case
- assign $1\msr1__data_o$next[63:0]$11059 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr1__data_o$next[63:0]$10973 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr1__data_o$next[63:0]$10979 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr1__data_o$next[63:0]$11065 $1\msr1__data_o$next[63:0]$11059
+ assign $7\msr1__data_o$next[63:0]$10979 $1\msr1__data_o$next[63:0]$10973
end
sync always
- update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11058
+ update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10972
end
- attribute \src "libresoc.v:180654.3-180689.6"
- process $proc$libresoc.v:180654$11066
+ attribute \src "libresoc.v:180102.3-180137.6"
+ process $proc$libresoc.v:180102$10980
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11067 $1\wr_detect$4[0:0]$11068
- attribute \src "libresoc.v:180655.5-180655.29"
+ assign $0\wr_detect$4[0:0]$10981 $1\wr_detect$4[0:0]$10982
+ attribute \src "libresoc.v:180103.5-180103.29"
switch \initial
- attribute \src "libresoc.v:180655.9-180655.17"
+ attribute \src "libresoc.v:180103.9-180103.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11068 $5\wr_detect$4[0:0]$11072
+ assign $1\wr_detect$4[0:0]$10982 $5\wr_detect$4[0:0]$10986
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11069 1'1
+ assign $2\wr_detect$4[0:0]$10983 1'1
case
- assign $2\wr_detect$4[0:0]$11069 1'0
+ assign $2\wr_detect$4[0:0]$10983 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11070 1'1
+ assign $3\wr_detect$4[0:0]$10984 1'1
case
- assign $3\wr_detect$4[0:0]$11070 $2\wr_detect$4[0:0]$11069
+ assign $3\wr_detect$4[0:0]$10984 $2\wr_detect$4[0:0]$10983
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11071 1'1
+ assign $4\wr_detect$4[0:0]$10985 1'1
case
- assign $4\wr_detect$4[0:0]$11071 $3\wr_detect$4[0:0]$11070
+ assign $4\wr_detect$4[0:0]$10985 $3\wr_detect$4[0:0]$10984
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11072 1'1
+ assign $5\wr_detect$4[0:0]$10986 1'1
case
- assign $5\wr_detect$4[0:0]$11072 $4\wr_detect$4[0:0]$11071
+ assign $5\wr_detect$4[0:0]$10986 $4\wr_detect$4[0:0]$10985
end
case
- assign $1\wr_detect$4[0:0]$11068 1'0
+ assign $1\wr_detect$4[0:0]$10982 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11067
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10981
end
- attribute \src "libresoc.v:180690.3-180735.6"
- process $proc$libresoc.v:180690$11073
+ attribute \src "libresoc.v:180138.3-180183.6"
+ process $proc$libresoc.v:180138$10987
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv1__data_o$next[63:0]$11074 $7\sv1__data_o$next[63:0]$11081
- attribute \src "libresoc.v:180691.5-180691.29"
+ assign $0\sv1__data_o$next[63:0]$10988 $7\sv1__data_o$next[63:0]$10995
+ attribute \src "libresoc.v:180139.5-180139.29"
switch \initial
- attribute \src "libresoc.v:180691.9-180691.17"
+ attribute \src "libresoc.v:180139.9-180139.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv1__data_o$next[63:0]$11075 $6\sv1__data_o$next[63:0]$11080
+ assign $1\sv1__data_o$next[63:0]$10989 $6\sv1__data_o$next[63:0]$10994
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv1__data_o$next[63:0]$11076 \nia1__data_i
+ assign $2\sv1__data_o$next[63:0]$10990 \nia1__data_i
case
- assign $2\sv1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv1__data_o$next[63:0]$10990 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv1__data_o$next[63:0]$11077 \msr1__data_i
+ assign $3\sv1__data_o$next[63:0]$10991 \msr1__data_i
case
- assign $3\sv1__data_o$next[63:0]$11077 $2\sv1__data_o$next[63:0]$11076
+ assign $3\sv1__data_o$next[63:0]$10991 $2\sv1__data_o$next[63:0]$10990
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv1__data_o$next[63:0]$11078 \sv1__data_i
+ assign $4\sv1__data_o$next[63:0]$10992 \sv1__data_i
case
- assign $4\sv1__data_o$next[63:0]$11078 $3\sv1__data_o$next[63:0]$11077
+ assign $4\sv1__data_o$next[63:0]$10992 $3\sv1__data_o$next[63:0]$10991
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv1__data_o$next[63:0]$11079 \d_wr11__data_i
+ assign $5\sv1__data_o$next[63:0]$10993 \d_wr11__data_i
case
- assign $5\sv1__data_o$next[63:0]$11079 $4\sv1__data_o$next[63:0]$11078
+ assign $5\sv1__data_o$next[63:0]$10993 $4\sv1__data_o$next[63:0]$10992
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv1__data_o$next[63:0]$11080 \reg
+ assign $6\sv1__data_o$next[63:0]$10994 \reg
case
- assign $6\sv1__data_o$next[63:0]$11080 $5\sv1__data_o$next[63:0]$11079
+ assign $6\sv1__data_o$next[63:0]$10994 $5\sv1__data_o$next[63:0]$10993
end
case
- assign $1\sv1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv1__data_o$next[63:0]$10995 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv1__data_o$next[63:0]$11081 $1\sv1__data_o$next[63:0]$11075
+ assign $7\sv1__data_o$next[63:0]$10995 $1\sv1__data_o$next[63:0]$10989
end
sync always
- update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11074
+ update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10988
end
- attribute \src "libresoc.v:180736.3-180771.6"
- process $proc$libresoc.v:180736$11082
+ attribute \src "libresoc.v:180184.3-180219.6"
+ process $proc$libresoc.v:180184$10996
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11083 $1\wr_detect$7[0:0]$11084
- attribute \src "libresoc.v:180737.5-180737.29"
+ assign $0\wr_detect$7[0:0]$10997 $1\wr_detect$7[0:0]$10998
+ attribute \src "libresoc.v:180185.5-180185.29"
switch \initial
- attribute \src "libresoc.v:180737.9-180737.17"
+ attribute \src "libresoc.v:180185.9-180185.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11084 $5\wr_detect$7[0:0]$11088
+ assign $1\wr_detect$7[0:0]$10998 $5\wr_detect$7[0:0]$11002
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11085 1'1
+ assign $2\wr_detect$7[0:0]$10999 1'1
case
- assign $2\wr_detect$7[0:0]$11085 1'0
+ assign $2\wr_detect$7[0:0]$10999 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11086 1'1
+ assign $3\wr_detect$7[0:0]$11000 1'1
case
- assign $3\wr_detect$7[0:0]$11086 $2\wr_detect$7[0:0]$11085
+ assign $3\wr_detect$7[0:0]$11000 $2\wr_detect$7[0:0]$10999
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11087 1'1
+ assign $4\wr_detect$7[0:0]$11001 1'1
case
- assign $4\wr_detect$7[0:0]$11087 $3\wr_detect$7[0:0]$11086
+ assign $4\wr_detect$7[0:0]$11001 $3\wr_detect$7[0:0]$11000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11088 1'1
+ assign $5\wr_detect$7[0:0]$11002 1'1
case
- assign $5\wr_detect$7[0:0]$11088 $4\wr_detect$7[0:0]$11087
+ assign $5\wr_detect$7[0:0]$11002 $4\wr_detect$7[0:0]$11001
end
case
- assign $1\wr_detect$7[0:0]$11084 1'0
+ assign $1\wr_detect$7[0:0]$10998 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11083
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10997
end
- attribute \src "libresoc.v:180772.3-180804.6"
- process $proc$libresoc.v:180772$11089
+ attribute \src "libresoc.v:180220.3-180252.6"
+ process $proc$libresoc.v:180220$11003
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$11090 $5\reg$next[63:0]$11095
- attribute \src "libresoc.v:180773.5-180773.29"
+ assign $0\reg$next[63:0]$11004 $5\reg$next[63:0]$11009
+ attribute \src "libresoc.v:180221.5-180221.29"
switch \initial
- attribute \src "libresoc.v:180773.9-180773.17"
+ attribute \src "libresoc.v:180221.9-180221.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$11091 \nia1__data_i
+ assign $1\reg$next[63:0]$11005 \nia1__data_i
case
- assign $1\reg$next[63:0]$11091 \reg
+ assign $1\reg$next[63:0]$11005 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$11092 \msr1__data_i
+ assign $2\reg$next[63:0]$11006 \msr1__data_i
case
- assign $2\reg$next[63:0]$11092 $1\reg$next[63:0]$11091
+ assign $2\reg$next[63:0]$11006 $1\reg$next[63:0]$11005
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$11093 \sv1__data_i
+ assign $3\reg$next[63:0]$11007 \sv1__data_i
case
- assign $3\reg$next[63:0]$11093 $2\reg$next[63:0]$11092
+ assign $3\reg$next[63:0]$11007 $2\reg$next[63:0]$11006
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$11094 \d_wr11__data_i
+ assign $4\reg$next[63:0]$11008 \d_wr11__data_i
case
- assign $4\reg$next[63:0]$11094 $3\reg$next[63:0]$11093
+ assign $4\reg$next[63:0]$11008 $3\reg$next[63:0]$11007
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$11095 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$11095 $4\reg$next[63:0]$11094
+ assign $5\reg$next[63:0]$11009 $4\reg$next[63:0]$11008
end
sync always
- update \reg$next $0\reg$next[63:0]$11090
+ update \reg$next $0\reg$next[63:0]$11004
end
- connect \$1 $not$libresoc.v:180515$11040_Y
- connect \$3 $not$libresoc.v:180516$11041_Y
- connect \$6 $not$libresoc.v:180517$11042_Y
+ connect \$1 $not$libresoc.v:179963$10954_Y
+ connect \$3 $not$libresoc.v:179964$10955_Y
+ connect \$6 $not$libresoc.v:179965$10956_Y
end
-attribute \src "libresoc.v:180809.1-181364.10"
+attribute \src "libresoc.v:180257.1-180728.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2"
attribute \generator "nMigen"
module \reg_2
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $0\cr_pred2__data_o$next[3:0]$11115
- attribute \src "libresoc.v:180915.3-180916.49"
- wire width 4 $0\cr_pred2__data_o[3:0]
- attribute \src "libresoc.v:180810.7-180810.20"
+ attribute \src "libresoc.v:180258.7-180258.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $0\r22__data_o$next[3:0]$11124
- attribute \src "libresoc.v:180905.3-180906.39"
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $0\r22__data_o$next[3:0]$11084
+ attribute \src "libresoc.v:180341.3-180342.39"
wire width 4 $0\r22__data_o[3:0]
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $0\r2__data_o$next[3:0]$11186
- attribute \src "libresoc.v:180907.3-180908.37"
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $0\r2__data_o$next[3:0]$11070
+ attribute \src "libresoc.v:180343.3-180344.37"
wire width 4 $0\r2__data_o[3:0]
- attribute \src "libresoc.v:181057.3-181083.6"
- wire width 4 $0\reg$next[3:0]$11138
- attribute \src "libresoc.v:180903.3-180904.25"
+ attribute \src "libresoc.v:180421.3-180447.6"
+ wire width 4 $0\reg$next[3:0]$11036
+ attribute \src "libresoc.v:180339.3-180340.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $0\src12__data_o$next[3:0]$11144
- attribute \src "libresoc.v:180913.3-180914.43"
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $0\src12__data_o$next[3:0]$11027
+ attribute \src "libresoc.v:180349.3-180350.43"
wire width 4 $0\src12__data_o[3:0]
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $0\src22__data_o$next[3:0]$11158
- attribute \src "libresoc.v:180911.3-180912.43"
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $0\src22__data_o$next[3:0]$11042
+ attribute \src "libresoc.v:180347.3-180348.43"
wire width 4 $0\src22__data_o[3:0]
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $0\src32__data_o$next[3:0]$11172
- attribute \src "libresoc.v:180909.3-180910.43"
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $0\src32__data_o$next[3:0]$11056
+ attribute \src "libresoc.v:180345.3-180346.43"
wire width 4 $0\src32__data_o[3:0]
- attribute \src "libresoc.v:181264.3-181293.6"
- wire $0\wr_detect$10[0:0]$11180
- attribute \src "libresoc.v:181334.3-181363.6"
- wire $0\wr_detect$13[0:0]$11194
- attribute \src "libresoc.v:181027.3-181056.6"
- wire $0\wr_detect$16[0:0]$11132
- attribute \src "libresoc.v:181124.3-181153.6"
- wire $0\wr_detect$4[0:0]$11152
- attribute \src "libresoc.v:181194.3-181223.6"
- wire $0\wr_detect$7[0:0]$11166
- attribute \src "libresoc.v:180957.3-180986.6"
+ attribute \src "libresoc.v:180628.3-180657.6"
+ wire $0\wr_detect$10[0:0]$11078
+ attribute \src "libresoc.v:180698.3-180727.6"
+ wire $0\wr_detect$13[0:0]$11092
+ attribute \src "libresoc.v:180488.3-180517.6"
+ wire $0\wr_detect$4[0:0]$11050
+ attribute \src "libresoc.v:180558.3-180587.6"
+ wire $0\wr_detect$7[0:0]$11064
+ attribute \src "libresoc.v:180391.3-180420.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $1\cr_pred2__data_o$next[3:0]$11116
- attribute \src "libresoc.v:180829.13-180829.36"
- wire width 4 $1\cr_pred2__data_o[3:0]
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $1\r22__data_o$next[3:0]$11125
- attribute \src "libresoc.v:180844.13-180844.31"
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $1\r22__data_o$next[3:0]$11085
+ attribute \src "libresoc.v:180283.13-180283.31"
wire width 4 $1\r22__data_o[3:0]
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $1\r2__data_o$next[3:0]$11187
- attribute \src "libresoc.v:180851.13-180851.30"
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $1\r2__data_o$next[3:0]$11071
+ attribute \src "libresoc.v:180290.13-180290.30"
wire width 4 $1\r2__data_o[3:0]
- attribute \src "libresoc.v:181057.3-181083.6"
- wire width 4 $1\reg$next[3:0]$11139
- attribute \src "libresoc.v:180857.13-180857.25"
+ attribute \src "libresoc.v:180421.3-180447.6"
+ wire width 4 $1\reg$next[3:0]$11037
+ attribute \src "libresoc.v:180296.13-180296.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $1\src12__data_o$next[3:0]$11145
- attribute \src "libresoc.v:180862.13-180862.33"
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $1\src12__data_o$next[3:0]$11028
+ attribute \src "libresoc.v:180301.13-180301.33"
wire width 4 $1\src12__data_o[3:0]
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $1\src22__data_o$next[3:0]$11159
- attribute \src "libresoc.v:180869.13-180869.33"
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $1\src22__data_o$next[3:0]$11043
+ attribute \src "libresoc.v:180308.13-180308.33"
wire width 4 $1\src22__data_o[3:0]
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $1\src32__data_o$next[3:0]$11173
- attribute \src "libresoc.v:180876.13-180876.33"
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $1\src32__data_o$next[3:0]$11057
+ attribute \src "libresoc.v:180315.13-180315.33"
wire width 4 $1\src32__data_o[3:0]
- attribute \src "libresoc.v:181264.3-181293.6"
- wire $1\wr_detect$10[0:0]$11181
- attribute \src "libresoc.v:181334.3-181363.6"
- wire $1\wr_detect$13[0:0]$11195
- attribute \src "libresoc.v:181027.3-181056.6"
- wire $1\wr_detect$16[0:0]$11133
- attribute \src "libresoc.v:181124.3-181153.6"
- wire $1\wr_detect$4[0:0]$11153
- attribute \src "libresoc.v:181194.3-181223.6"
- wire $1\wr_detect$7[0:0]$11167
- attribute \src "libresoc.v:180957.3-180986.6"
+ attribute \src "libresoc.v:180628.3-180657.6"
+ wire $1\wr_detect$10[0:0]$11079
+ attribute \src "libresoc.v:180698.3-180727.6"
+ wire $1\wr_detect$13[0:0]$11093
+ attribute \src "libresoc.v:180488.3-180517.6"
+ wire $1\wr_detect$4[0:0]$11051
+ attribute \src "libresoc.v:180558.3-180587.6"
+ wire $1\wr_detect$7[0:0]$11065
+ attribute \src "libresoc.v:180391.3-180420.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $2\cr_pred2__data_o$next[3:0]$11117
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $2\r22__data_o$next[3:0]$11126
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $2\r2__data_o$next[3:0]$11188
- attribute \src "libresoc.v:181057.3-181083.6"
- wire width 4 $2\reg$next[3:0]$11140
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $2\src12__data_o$next[3:0]$11146
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $2\src22__data_o$next[3:0]$11160
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $2\src32__data_o$next[3:0]$11174
- attribute \src "libresoc.v:181264.3-181293.6"
- wire $2\wr_detect$10[0:0]$11182
- attribute \src "libresoc.v:181334.3-181363.6"
- wire $2\wr_detect$13[0:0]$11196
- attribute \src "libresoc.v:181027.3-181056.6"
- wire $2\wr_detect$16[0:0]$11134
- attribute \src "libresoc.v:181124.3-181153.6"
- wire $2\wr_detect$4[0:0]$11154
- attribute \src "libresoc.v:181194.3-181223.6"
- wire $2\wr_detect$7[0:0]$11168
- attribute \src "libresoc.v:180957.3-180986.6"
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $2\r22__data_o$next[3:0]$11086
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $2\r2__data_o$next[3:0]$11072
+ attribute \src "libresoc.v:180421.3-180447.6"
+ wire width 4 $2\reg$next[3:0]$11038
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $2\src12__data_o$next[3:0]$11029
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $2\src22__data_o$next[3:0]$11044
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $2\src32__data_o$next[3:0]$11058
+ attribute \src "libresoc.v:180628.3-180657.6"
+ wire $2\wr_detect$10[0:0]$11080
+ attribute \src "libresoc.v:180698.3-180727.6"
+ wire $2\wr_detect$13[0:0]$11094
+ attribute \src "libresoc.v:180488.3-180517.6"
+ wire $2\wr_detect$4[0:0]$11052
+ attribute \src "libresoc.v:180558.3-180587.6"
+ wire $2\wr_detect$7[0:0]$11066
+ attribute \src "libresoc.v:180391.3-180420.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $3\cr_pred2__data_o$next[3:0]$11118
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $3\r22__data_o$next[3:0]$11127
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $3\r2__data_o$next[3:0]$11189
- attribute \src "libresoc.v:181057.3-181083.6"
- wire width 4 $3\reg$next[3:0]$11141
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $3\src12__data_o$next[3:0]$11147
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $3\src22__data_o$next[3:0]$11161
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $3\src32__data_o$next[3:0]$11175
- attribute \src "libresoc.v:181264.3-181293.6"
- wire $3\wr_detect$10[0:0]$11183
- attribute \src "libresoc.v:181334.3-181363.6"
- wire $3\wr_detect$13[0:0]$11197
- attribute \src "libresoc.v:181027.3-181056.6"
- wire $3\wr_detect$16[0:0]$11135
- attribute \src "libresoc.v:181124.3-181153.6"
- wire $3\wr_detect$4[0:0]$11155
- attribute \src "libresoc.v:181194.3-181223.6"
- wire $3\wr_detect$7[0:0]$11169
- attribute \src "libresoc.v:180957.3-180986.6"
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $3\r22__data_o$next[3:0]$11087
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $3\r2__data_o$next[3:0]$11073
+ attribute \src "libresoc.v:180421.3-180447.6"
+ wire width 4 $3\reg$next[3:0]$11039
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $3\src12__data_o$next[3:0]$11030
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $3\src22__data_o$next[3:0]$11045
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $3\src32__data_o$next[3:0]$11059
+ attribute \src "libresoc.v:180628.3-180657.6"
+ wire $3\wr_detect$10[0:0]$11081
+ attribute \src "libresoc.v:180698.3-180727.6"
+ wire $3\wr_detect$13[0:0]$11095
+ attribute \src "libresoc.v:180488.3-180517.6"
+ wire $3\wr_detect$4[0:0]$11053
+ attribute \src "libresoc.v:180558.3-180587.6"
+ wire $3\wr_detect$7[0:0]$11067
+ attribute \src "libresoc.v:180391.3-180420.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $4\cr_pred2__data_o$next[3:0]$11119
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $4\r22__data_o$next[3:0]$11128
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $4\r2__data_o$next[3:0]$11190
- attribute \src "libresoc.v:181057.3-181083.6"
- wire width 4 $4\reg$next[3:0]$11142
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $4\src12__data_o$next[3:0]$11148
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $4\src22__data_o$next[3:0]$11162
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $4\src32__data_o$next[3:0]$11176
- attribute \src "libresoc.v:181264.3-181293.6"
- wire $4\wr_detect$10[0:0]$11184
- attribute \src "libresoc.v:181334.3-181363.6"
- wire $4\wr_detect$13[0:0]$11198
- attribute \src "libresoc.v:181027.3-181056.6"
- wire $4\wr_detect$16[0:0]$11136
- attribute \src "libresoc.v:181124.3-181153.6"
- wire $4\wr_detect$4[0:0]$11156
- attribute \src "libresoc.v:181194.3-181223.6"
- wire $4\wr_detect$7[0:0]$11170
- attribute \src "libresoc.v:180957.3-180986.6"
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $4\r22__data_o$next[3:0]$11088
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $4\r2__data_o$next[3:0]$11074
+ attribute \src "libresoc.v:180421.3-180447.6"
+ wire width 4 $4\reg$next[3:0]$11040
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $4\src12__data_o$next[3:0]$11031
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $4\src22__data_o$next[3:0]$11046
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $4\src32__data_o$next[3:0]$11060
+ attribute \src "libresoc.v:180628.3-180657.6"
+ wire $4\wr_detect$10[0:0]$11082
+ attribute \src "libresoc.v:180698.3-180727.6"
+ wire $4\wr_detect$13[0:0]$11096
+ attribute \src "libresoc.v:180488.3-180517.6"
+ wire $4\wr_detect$4[0:0]$11054
+ attribute \src "libresoc.v:180558.3-180587.6"
+ wire $4\wr_detect$7[0:0]$11068
+ attribute \src "libresoc.v:180391.3-180420.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $5\cr_pred2__data_o$next[3:0]$11120
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $5\r22__data_o$next[3:0]$11129
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $5\r2__data_o$next[3:0]$11191
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $5\src12__data_o$next[3:0]$11149
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $5\src22__data_o$next[3:0]$11163
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $5\src32__data_o$next[3:0]$11177
- attribute \src "libresoc.v:180917.3-180956.6"
- wire width 4 $6\cr_pred2__data_o$next[3:0]$11121
- attribute \src "libresoc.v:180987.3-181026.6"
- wire width 4 $6\r22__data_o$next[3:0]$11130
- attribute \src "libresoc.v:181294.3-181333.6"
- wire width 4 $6\r2__data_o$next[3:0]$11192
- attribute \src "libresoc.v:181084.3-181123.6"
- wire width 4 $6\src12__data_o$next[3:0]$11150
- attribute \src "libresoc.v:181154.3-181193.6"
- wire width 4 $6\src22__data_o$next[3:0]$11164
- attribute \src "libresoc.v:181224.3-181263.6"
- wire width 4 $6\src32__data_o$next[3:0]$11178
- attribute \src "libresoc.v:180897.17-180897.104"
- wire $not$libresoc.v:180897$11101_Y
- attribute \src "libresoc.v:180898.18-180898.105"
- wire $not$libresoc.v:180898$11102_Y
- attribute \src "libresoc.v:180899.18-180899.105"
- wire $not$libresoc.v:180899$11103_Y
- attribute \src "libresoc.v:180900.17-180900.100"
- wire $not$libresoc.v:180900$11104_Y
- attribute \src "libresoc.v:180901.17-180901.103"
- wire $not$libresoc.v:180901$11105_Y
- attribute \src "libresoc.v:180902.17-180902.103"
- wire $not$libresoc.v:180902$11106_Y
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $5\r22__data_o$next[3:0]$11089
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $5\r2__data_o$next[3:0]$11075
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $5\src12__data_o$next[3:0]$11032
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $5\src22__data_o$next[3:0]$11047
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $5\src32__data_o$next[3:0]$11061
+ attribute \src "libresoc.v:180658.3-180697.6"
+ wire width 4 $6\r22__data_o$next[3:0]$11090
+ attribute \src "libresoc.v:180588.3-180627.6"
+ wire width 4 $6\r2__data_o$next[3:0]$11076
+ attribute \src "libresoc.v:180351.3-180390.6"
+ wire width 4 $6\src12__data_o$next[3:0]$11033
+ attribute \src "libresoc.v:180448.3-180487.6"
+ wire width 4 $6\src22__data_o$next[3:0]$11048
+ attribute \src "libresoc.v:180518.3-180557.6"
+ wire width 4 $6\src32__data_o$next[3:0]$11062
+ attribute \src "libresoc.v:180334.17-180334.104"
+ wire $not$libresoc.v:180334$11015_Y
+ attribute \src "libresoc.v:180335.18-180335.105"
+ wire $not$libresoc.v:180335$11016_Y
+ attribute \src "libresoc.v:180336.17-180336.100"
+ wire $not$libresoc.v:180336$11017_Y
+ attribute \src "libresoc.v:180337.17-180337.103"
+ wire $not$libresoc.v:180337$11018_Y
+ attribute \src "libresoc.v:180338.17-180338.103"
+ wire $not$libresoc.v:180338$11019_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred2__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred2__ren
+ wire width 4 input 9 \dest12__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest12__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest12__wen
+ wire input 8 \dest12__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest22__data_i
+ wire width 4 input 11 \dest22__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest22__wen
- attribute \src "libresoc.v:180810.7-180810.15"
+ wire input 10 \dest22__wen
+ attribute \src "libresoc.v:180258.7-180258.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r22__data_o
+ wire width 4 output 14 \r22__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r22__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r22__ren
+ wire input 15 \r22__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r2__data_o
+ wire width 4 output 12 \r2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r2__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r2__ren
+ wire input 13 \r2__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src12__data_o
+ wire width 4 output 3 \src12__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src12__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src12__ren
+ wire input 2 \src12__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src22__data_o
+ wire width 4 output 5 \src22__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src22__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src22__ren
+ wire input 4 \src22__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src32__data_o
+ wire width 4 output 7 \src32__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src32__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src32__ren
+ wire input 6 \src32__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w2__data_i
+ wire width 4 input 16 \w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w2__wen
+ wire input 17 \w2__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180897$11101
+ cell $not $not$libresoc.v:180334$11015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:180897$11101_Y
+ connect \Y $not$libresoc.v:180334$11015_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180898$11102
+ cell $not $not$libresoc.v:180335$11016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:180898$11102_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180899$11103
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:180899$11103_Y
+ connect \Y $not$libresoc.v:180335$11016_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180900$11104
+ cell $not $not$libresoc.v:180336$11017
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:180900$11104_Y
+ connect \Y $not$libresoc.v:180336$11017_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180901$11105
+ cell $not $not$libresoc.v:180337$11018
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:180901$11105_Y
+ connect \Y $not$libresoc.v:180337$11018_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180902$11106
+ cell $not $not$libresoc.v:180338$11019
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:180902$11106_Y
+ connect \Y $not$libresoc.v:180338$11019_Y
end
- attribute \src "libresoc.v:180810.7-180810.20"
- process $proc$libresoc.v:180810$11199
+ attribute \src "libresoc.v:180258.7-180258.20"
+ process $proc$libresoc.v:180258$11097
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:180829.13-180829.36"
- process $proc$libresoc.v:180829$11200
- assign { } { }
- assign $1\cr_pred2__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred2__data_o $1\cr_pred2__data_o[3:0]
- end
- attribute \src "libresoc.v:180844.13-180844.31"
- process $proc$libresoc.v:180844$11201
+ attribute \src "libresoc.v:180283.13-180283.31"
+ process $proc$libresoc.v:180283$11098
assign { } { }
assign $1\r22__data_o[3:0] 4'0000
sync always
sync init
update \r22__data_o $1\r22__data_o[3:0]
end
- attribute \src "libresoc.v:180851.13-180851.30"
- process $proc$libresoc.v:180851$11202
+ attribute \src "libresoc.v:180290.13-180290.30"
+ process $proc$libresoc.v:180290$11099
assign { } { }
assign $1\r2__data_o[3:0] 4'0000
sync always
sync init
update \r2__data_o $1\r2__data_o[3:0]
end
- attribute \src "libresoc.v:180857.13-180857.25"
- process $proc$libresoc.v:180857$11203
+ attribute \src "libresoc.v:180296.13-180296.25"
+ process $proc$libresoc.v:180296$11100
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:180862.13-180862.33"
- process $proc$libresoc.v:180862$11204
+ attribute \src "libresoc.v:180301.13-180301.33"
+ process $proc$libresoc.v:180301$11101
assign { } { }
assign $1\src12__data_o[3:0] 4'0000
sync always
sync init
update \src12__data_o $1\src12__data_o[3:0]
end
- attribute \src "libresoc.v:180869.13-180869.33"
- process $proc$libresoc.v:180869$11205
+ attribute \src "libresoc.v:180308.13-180308.33"
+ process $proc$libresoc.v:180308$11102
assign { } { }
assign $1\src22__data_o[3:0] 4'0000
sync always
sync init
update \src22__data_o $1\src22__data_o[3:0]
end
- attribute \src "libresoc.v:180876.13-180876.33"
- process $proc$libresoc.v:180876$11206
+ attribute \src "libresoc.v:180315.13-180315.33"
+ process $proc$libresoc.v:180315$11103
assign { } { }
assign $1\src32__data_o[3:0] 4'0000
sync always
sync init
update \src32__data_o $1\src32__data_o[3:0]
end
- attribute \src "libresoc.v:180903.3-180904.25"
- process $proc$libresoc.v:180903$11107
+ attribute \src "libresoc.v:180339.3-180340.25"
+ process $proc$libresoc.v:180339$11020
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:180905.3-180906.39"
- process $proc$libresoc.v:180905$11108
+ attribute \src "libresoc.v:180341.3-180342.39"
+ process $proc$libresoc.v:180341$11021
assign { } { }
assign $0\r22__data_o[3:0] \r22__data_o$next
sync posedge \coresync_clk
update \r22__data_o $0\r22__data_o[3:0]
end
- attribute \src "libresoc.v:180907.3-180908.37"
- process $proc$libresoc.v:180907$11109
+ attribute \src "libresoc.v:180343.3-180344.37"
+ process $proc$libresoc.v:180343$11022
assign { } { }
assign $0\r2__data_o[3:0] \r2__data_o$next
sync posedge \coresync_clk
update \r2__data_o $0\r2__data_o[3:0]
end
- attribute \src "libresoc.v:180909.3-180910.43"
- process $proc$libresoc.v:180909$11110
+ attribute \src "libresoc.v:180345.3-180346.43"
+ process $proc$libresoc.v:180345$11023
assign { } { }
assign $0\src32__data_o[3:0] \src32__data_o$next
sync posedge \coresync_clk
update \src32__data_o $0\src32__data_o[3:0]
end
- attribute \src "libresoc.v:180911.3-180912.43"
- process $proc$libresoc.v:180911$11111
+ attribute \src "libresoc.v:180347.3-180348.43"
+ process $proc$libresoc.v:180347$11024
assign { } { }
assign $0\src22__data_o[3:0] \src22__data_o$next
sync posedge \coresync_clk
update \src22__data_o $0\src22__data_o[3:0]
end
- attribute \src "libresoc.v:180913.3-180914.43"
- process $proc$libresoc.v:180913$11112
+ attribute \src "libresoc.v:180349.3-180350.43"
+ process $proc$libresoc.v:180349$11025
assign { } { }
assign $0\src12__data_o[3:0] \src12__data_o$next
sync posedge \coresync_clk
update \src12__data_o $0\src12__data_o[3:0]
end
- attribute \src "libresoc.v:180915.3-180916.49"
- process $proc$libresoc.v:180915$11113
- assign { } { }
- assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next
- sync posedge \coresync_clk
- update \cr_pred2__data_o $0\cr_pred2__data_o[3:0]
- end
- attribute \src "libresoc.v:180917.3-180956.6"
- process $proc$libresoc.v:180917$11114
+ attribute \src "libresoc.v:180351.3-180390.6"
+ process $proc$libresoc.v:180351$11026
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_pred2__data_o$next[3:0]$11115 $6\cr_pred2__data_o$next[3:0]$11121
- attribute \src "libresoc.v:180918.5-180918.29"
+ assign $0\src12__data_o$next[3:0]$11027 $6\src12__data_o$next[3:0]$11033
+ attribute \src "libresoc.v:180352.5-180352.29"
switch \initial
- attribute \src "libresoc.v:180918.9-180918.17"
+ attribute \src "libresoc.v:180352.9-180352.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred2__ren
+ switch \src12__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred2__data_o$next[3:0]$11116 $5\cr_pred2__data_o$next[3:0]$11120
+ assign $1\src12__data_o$next[3:0]$11028 $5\src12__data_o$next[3:0]$11032
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred2__data_o$next[3:0]$11117 \dest12__data_i
+ assign $2\src12__data_o$next[3:0]$11029 \dest12__data_i
case
- assign $2\cr_pred2__data_o$next[3:0]$11117 4'0000
+ assign $2\src12__data_o$next[3:0]$11029 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred2__data_o$next[3:0]$11118 \dest22__data_i
+ assign $3\src12__data_o$next[3:0]$11030 \dest22__data_i
case
- assign $3\cr_pred2__data_o$next[3:0]$11118 $2\cr_pred2__data_o$next[3:0]$11117
+ assign $3\src12__data_o$next[3:0]$11030 $2\src12__data_o$next[3:0]$11029
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred2__data_o$next[3:0]$11119 \w2__data_i
+ assign $4\src12__data_o$next[3:0]$11031 \w2__data_i
case
- assign $4\cr_pred2__data_o$next[3:0]$11119 $3\cr_pred2__data_o$next[3:0]$11118
+ assign $4\src12__data_o$next[3:0]$11031 $3\src12__data_o$next[3:0]$11030
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred2__data_o$next[3:0]$11120 \reg
+ assign $5\src12__data_o$next[3:0]$11032 \reg
case
- assign $5\cr_pred2__data_o$next[3:0]$11120 $4\cr_pred2__data_o$next[3:0]$11119
+ assign $5\src12__data_o$next[3:0]$11032 $4\src12__data_o$next[3:0]$11031
end
case
- assign $1\cr_pred2__data_o$next[3:0]$11116 4'0000
+ assign $1\src12__data_o$next[3:0]$11028 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred2__data_o$next[3:0]$11121 4'0000
+ assign $6\src12__data_o$next[3:0]$11033 4'0000
case
- assign $6\cr_pred2__data_o$next[3:0]$11121 $1\cr_pred2__data_o$next[3:0]$11116
+ assign $6\src12__data_o$next[3:0]$11033 $1\src12__data_o$next[3:0]$11028
end
sync always
- update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11115
+ update \src12__data_o$next $0\src12__data_o$next[3:0]$11027
end
- attribute \src "libresoc.v:180957.3-180986.6"
- process $proc$libresoc.v:180957$11122
+ attribute \src "libresoc.v:180391.3-180420.6"
+ process $proc$libresoc.v:180391$11034
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:180958.5-180958.29"
+ attribute \src "libresoc.v:180392.5-180392.29"
switch \initial
- attribute \src "libresoc.v:180958.9-180958.17"
+ attribute \src "libresoc.v:180392.9-180392.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred2__ren
+ switch \src12__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:180987.3-181026.6"
- process $proc$libresoc.v:180987$11123
+ attribute \src "libresoc.v:180421.3-180447.6"
+ process $proc$libresoc.v:180421$11035
assign { } { }
assign { } { }
assign { } { }
- assign $0\r22__data_o$next[3:0]$11124 $6\r22__data_o$next[3:0]$11130
- attribute \src "libresoc.v:180988.5-180988.29"
- switch \initial
- attribute \src "libresoc.v:180988.9-180988.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r22__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\r22__data_o$next[3:0]$11125 $5\r22__data_o$next[3:0]$11129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest12__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r22__data_o$next[3:0]$11126 \dest12__data_i
- case
- assign $2\r22__data_o$next[3:0]$11126 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest22__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r22__data_o$next[3:0]$11127 \dest22__data_i
- case
- assign $3\r22__data_o$next[3:0]$11127 $2\r22__data_o$next[3:0]$11126
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w2__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r22__data_o$next[3:0]$11128 \w2__data_i
- case
- assign $4\r22__data_o$next[3:0]$11128 $3\r22__data_o$next[3:0]$11127
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r22__data_o$next[3:0]$11129 \reg
- case
- assign $5\r22__data_o$next[3:0]$11129 $4\r22__data_o$next[3:0]$11128
- end
- case
- assign $1\r22__data_o$next[3:0]$11125 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\r22__data_o$next[3:0]$11130 4'0000
- case
- assign $6\r22__data_o$next[3:0]$11130 $1\r22__data_o$next[3:0]$11125
- end
- sync always
- update \r22__data_o$next $0\r22__data_o$next[3:0]$11124
- end
- attribute \src "libresoc.v:181027.3-181056.6"
- process $proc$libresoc.v:181027$11131
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$11132 $1\wr_detect$16[0:0]$11133
- attribute \src "libresoc.v:181028.5-181028.29"
+ assign $0\reg$next[3:0]$11036 $4\reg$next[3:0]$11040
+ attribute \src "libresoc.v:180422.5-180422.29"
switch \initial
- attribute \src "libresoc.v:181028.9-181028.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r22__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$16[0:0]$11133 $4\wr_detect$16[0:0]$11136
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest12__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$16[0:0]$11134 1'1
- case
- assign $2\wr_detect$16[0:0]$11134 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest22__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$16[0:0]$11135 1'1
- case
- assign $3\wr_detect$16[0:0]$11135 $2\wr_detect$16[0:0]$11134
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w2__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$16[0:0]$11136 1'1
- case
- assign $4\wr_detect$16[0:0]$11136 $3\wr_detect$16[0:0]$11135
- end
- case
- assign $1\wr_detect$16[0:0]$11133 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11132
- end
- attribute \src "libresoc.v:181057.3-181083.6"
- process $proc$libresoc.v:181057$11137
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$11138 $4\reg$next[3:0]$11142
- attribute \src "libresoc.v:181058.5-181058.29"
- switch \initial
- attribute \src "libresoc.v:181058.9-181058.17"
+ attribute \src "libresoc.v:180422.9-180422.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11139 \dest12__data_i
+ assign $1\reg$next[3:0]$11037 \dest12__data_i
case
- assign $1\reg$next[3:0]$11139 \reg
+ assign $1\reg$next[3:0]$11037 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11140 \dest22__data_i
+ assign $2\reg$next[3:0]$11038 \dest22__data_i
case
- assign $2\reg$next[3:0]$11140 $1\reg$next[3:0]$11139
+ assign $2\reg$next[3:0]$11038 $1\reg$next[3:0]$11037
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11141 \w2__data_i
+ assign $3\reg$next[3:0]$11039 \w2__data_i
case
- assign $3\reg$next[3:0]$11141 $2\reg$next[3:0]$11140
+ assign $3\reg$next[3:0]$11039 $2\reg$next[3:0]$11038
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11142 4'0000
+ assign $4\reg$next[3:0]$11040 4'0000
case
- assign $4\reg$next[3:0]$11142 $3\reg$next[3:0]$11141
+ assign $4\reg$next[3:0]$11040 $3\reg$next[3:0]$11039
end
sync always
- update \reg$next $0\reg$next[3:0]$11138
+ update \reg$next $0\reg$next[3:0]$11036
end
- attribute \src "libresoc.v:181084.3-181123.6"
- process $proc$libresoc.v:181084$11143
+ attribute \src "libresoc.v:180448.3-180487.6"
+ process $proc$libresoc.v:180448$11041
assign { } { }
assign { } { }
assign { } { }
- assign $0\src12__data_o$next[3:0]$11144 $6\src12__data_o$next[3:0]$11150
- attribute \src "libresoc.v:181085.5-181085.29"
+ assign $0\src22__data_o$next[3:0]$11042 $6\src22__data_o$next[3:0]$11048
+ attribute \src "libresoc.v:180449.5-180449.29"
switch \initial
- attribute \src "libresoc.v:181085.9-181085.17"
+ attribute \src "libresoc.v:180449.9-180449.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src12__ren
+ switch \src22__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src12__data_o$next[3:0]$11145 $5\src12__data_o$next[3:0]$11149
+ assign $1\src22__data_o$next[3:0]$11043 $5\src22__data_o$next[3:0]$11047
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src12__data_o$next[3:0]$11146 \dest12__data_i
+ assign $2\src22__data_o$next[3:0]$11044 \dest12__data_i
case
- assign $2\src12__data_o$next[3:0]$11146 4'0000
+ assign $2\src22__data_o$next[3:0]$11044 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src12__data_o$next[3:0]$11147 \dest22__data_i
+ assign $3\src22__data_o$next[3:0]$11045 \dest22__data_i
case
- assign $3\src12__data_o$next[3:0]$11147 $2\src12__data_o$next[3:0]$11146
+ assign $3\src22__data_o$next[3:0]$11045 $2\src22__data_o$next[3:0]$11044
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src12__data_o$next[3:0]$11148 \w2__data_i
+ assign $4\src22__data_o$next[3:0]$11046 \w2__data_i
case
- assign $4\src12__data_o$next[3:0]$11148 $3\src12__data_o$next[3:0]$11147
+ assign $4\src22__data_o$next[3:0]$11046 $3\src22__data_o$next[3:0]$11045
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src12__data_o$next[3:0]$11149 \reg
+ assign $5\src22__data_o$next[3:0]$11047 \reg
case
- assign $5\src12__data_o$next[3:0]$11149 $4\src12__data_o$next[3:0]$11148
+ assign $5\src22__data_o$next[3:0]$11047 $4\src22__data_o$next[3:0]$11046
end
case
- assign $1\src12__data_o$next[3:0]$11145 4'0000
+ assign $1\src22__data_o$next[3:0]$11043 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src12__data_o$next[3:0]$11150 4'0000
+ assign $6\src22__data_o$next[3:0]$11048 4'0000
case
- assign $6\src12__data_o$next[3:0]$11150 $1\src12__data_o$next[3:0]$11145
+ assign $6\src22__data_o$next[3:0]$11048 $1\src22__data_o$next[3:0]$11043
end
sync always
- update \src12__data_o$next $0\src12__data_o$next[3:0]$11144
+ update \src22__data_o$next $0\src22__data_o$next[3:0]$11042
end
- attribute \src "libresoc.v:181124.3-181153.6"
- process $proc$libresoc.v:181124$11151
+ attribute \src "libresoc.v:180488.3-180517.6"
+ process $proc$libresoc.v:180488$11049
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11152 $1\wr_detect$4[0:0]$11153
- attribute \src "libresoc.v:181125.5-181125.29"
+ assign $0\wr_detect$4[0:0]$11050 $1\wr_detect$4[0:0]$11051
+ attribute \src "libresoc.v:180489.5-180489.29"
switch \initial
- attribute \src "libresoc.v:181125.9-181125.17"
+ attribute \src "libresoc.v:180489.9-180489.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src12__ren
+ switch \src22__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11153 $4\wr_detect$4[0:0]$11156
+ assign $1\wr_detect$4[0:0]$11051 $4\wr_detect$4[0:0]$11054
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11154 1'1
+ assign $2\wr_detect$4[0:0]$11052 1'1
case
- assign $2\wr_detect$4[0:0]$11154 1'0
+ assign $2\wr_detect$4[0:0]$11052 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11155 1'1
+ assign $3\wr_detect$4[0:0]$11053 1'1
case
- assign $3\wr_detect$4[0:0]$11155 $2\wr_detect$4[0:0]$11154
+ assign $3\wr_detect$4[0:0]$11053 $2\wr_detect$4[0:0]$11052
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11156 1'1
+ assign $4\wr_detect$4[0:0]$11054 1'1
case
- assign $4\wr_detect$4[0:0]$11156 $3\wr_detect$4[0:0]$11155
+ assign $4\wr_detect$4[0:0]$11054 $3\wr_detect$4[0:0]$11053
end
case
- assign $1\wr_detect$4[0:0]$11153 1'0
+ assign $1\wr_detect$4[0:0]$11051 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11152
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11050
end
- attribute \src "libresoc.v:181154.3-181193.6"
- process $proc$libresoc.v:181154$11157
+ attribute \src "libresoc.v:180518.3-180557.6"
+ process $proc$libresoc.v:180518$11055
assign { } { }
assign { } { }
assign { } { }
- assign $0\src22__data_o$next[3:0]$11158 $6\src22__data_o$next[3:0]$11164
- attribute \src "libresoc.v:181155.5-181155.29"
+ assign $0\src32__data_o$next[3:0]$11056 $6\src32__data_o$next[3:0]$11062
+ attribute \src "libresoc.v:180519.5-180519.29"
switch \initial
- attribute \src "libresoc.v:181155.9-181155.17"
+ attribute \src "libresoc.v:180519.9-180519.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src22__ren
+ switch \src32__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src22__data_o$next[3:0]$11159 $5\src22__data_o$next[3:0]$11163
+ assign $1\src32__data_o$next[3:0]$11057 $5\src32__data_o$next[3:0]$11061
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src22__data_o$next[3:0]$11160 \dest12__data_i
+ assign $2\src32__data_o$next[3:0]$11058 \dest12__data_i
case
- assign $2\src22__data_o$next[3:0]$11160 4'0000
+ assign $2\src32__data_o$next[3:0]$11058 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src22__data_o$next[3:0]$11161 \dest22__data_i
+ assign $3\src32__data_o$next[3:0]$11059 \dest22__data_i
case
- assign $3\src22__data_o$next[3:0]$11161 $2\src22__data_o$next[3:0]$11160
+ assign $3\src32__data_o$next[3:0]$11059 $2\src32__data_o$next[3:0]$11058
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src22__data_o$next[3:0]$11162 \w2__data_i
+ assign $4\src32__data_o$next[3:0]$11060 \w2__data_i
case
- assign $4\src22__data_o$next[3:0]$11162 $3\src22__data_o$next[3:0]$11161
+ assign $4\src32__data_o$next[3:0]$11060 $3\src32__data_o$next[3:0]$11059
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src22__data_o$next[3:0]$11163 \reg
+ assign $5\src32__data_o$next[3:0]$11061 \reg
case
- assign $5\src22__data_o$next[3:0]$11163 $4\src22__data_o$next[3:0]$11162
+ assign $5\src32__data_o$next[3:0]$11061 $4\src32__data_o$next[3:0]$11060
end
case
- assign $1\src22__data_o$next[3:0]$11159 4'0000
+ assign $1\src32__data_o$next[3:0]$11057 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src22__data_o$next[3:0]$11164 4'0000
+ assign $6\src32__data_o$next[3:0]$11062 4'0000
case
- assign $6\src22__data_o$next[3:0]$11164 $1\src22__data_o$next[3:0]$11159
+ assign $6\src32__data_o$next[3:0]$11062 $1\src32__data_o$next[3:0]$11057
end
sync always
- update \src22__data_o$next $0\src22__data_o$next[3:0]$11158
+ update \src32__data_o$next $0\src32__data_o$next[3:0]$11056
end
- attribute \src "libresoc.v:181194.3-181223.6"
- process $proc$libresoc.v:181194$11165
+ attribute \src "libresoc.v:180558.3-180587.6"
+ process $proc$libresoc.v:180558$11063
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11166 $1\wr_detect$7[0:0]$11167
- attribute \src "libresoc.v:181195.5-181195.29"
+ assign $0\wr_detect$7[0:0]$11064 $1\wr_detect$7[0:0]$11065
+ attribute \src "libresoc.v:180559.5-180559.29"
switch \initial
- attribute \src "libresoc.v:181195.9-181195.17"
+ attribute \src "libresoc.v:180559.9-180559.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src22__ren
+ switch \src32__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11167 $4\wr_detect$7[0:0]$11170
+ assign $1\wr_detect$7[0:0]$11065 $4\wr_detect$7[0:0]$11068
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11168 1'1
+ assign $2\wr_detect$7[0:0]$11066 1'1
case
- assign $2\wr_detect$7[0:0]$11168 1'0
+ assign $2\wr_detect$7[0:0]$11066 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11169 1'1
+ assign $3\wr_detect$7[0:0]$11067 1'1
case
- assign $3\wr_detect$7[0:0]$11169 $2\wr_detect$7[0:0]$11168
+ assign $3\wr_detect$7[0:0]$11067 $2\wr_detect$7[0:0]$11066
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11170 1'1
+ assign $4\wr_detect$7[0:0]$11068 1'1
case
- assign $4\wr_detect$7[0:0]$11170 $3\wr_detect$7[0:0]$11169
+ assign $4\wr_detect$7[0:0]$11068 $3\wr_detect$7[0:0]$11067
end
case
- assign $1\wr_detect$7[0:0]$11167 1'0
+ assign $1\wr_detect$7[0:0]$11065 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11166
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11064
end
- attribute \src "libresoc.v:181224.3-181263.6"
- process $proc$libresoc.v:181224$11171
+ attribute \src "libresoc.v:180588.3-180627.6"
+ process $proc$libresoc.v:180588$11069
assign { } { }
assign { } { }
assign { } { }
- assign $0\src32__data_o$next[3:0]$11172 $6\src32__data_o$next[3:0]$11178
- attribute \src "libresoc.v:181225.5-181225.29"
+ assign $0\r2__data_o$next[3:0]$11070 $6\r2__data_o$next[3:0]$11076
+ attribute \src "libresoc.v:180589.5-180589.29"
switch \initial
- attribute \src "libresoc.v:181225.9-181225.17"
+ attribute \src "libresoc.v:180589.9-180589.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src32__ren
+ switch \r2__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src32__data_o$next[3:0]$11173 $5\src32__data_o$next[3:0]$11177
+ assign $1\r2__data_o$next[3:0]$11071 $5\r2__data_o$next[3:0]$11075
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src32__data_o$next[3:0]$11174 \dest12__data_i
+ assign $2\r2__data_o$next[3:0]$11072 \dest12__data_i
case
- assign $2\src32__data_o$next[3:0]$11174 4'0000
+ assign $2\r2__data_o$next[3:0]$11072 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src32__data_o$next[3:0]$11175 \dest22__data_i
+ assign $3\r2__data_o$next[3:0]$11073 \dest22__data_i
case
- assign $3\src32__data_o$next[3:0]$11175 $2\src32__data_o$next[3:0]$11174
+ assign $3\r2__data_o$next[3:0]$11073 $2\r2__data_o$next[3:0]$11072
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src32__data_o$next[3:0]$11176 \w2__data_i
+ assign $4\r2__data_o$next[3:0]$11074 \w2__data_i
case
- assign $4\src32__data_o$next[3:0]$11176 $3\src32__data_o$next[3:0]$11175
+ assign $4\r2__data_o$next[3:0]$11074 $3\r2__data_o$next[3:0]$11073
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src32__data_o$next[3:0]$11177 \reg
+ assign $5\r2__data_o$next[3:0]$11075 \reg
case
- assign $5\src32__data_o$next[3:0]$11177 $4\src32__data_o$next[3:0]$11176
+ assign $5\r2__data_o$next[3:0]$11075 $4\r2__data_o$next[3:0]$11074
end
case
- assign $1\src32__data_o$next[3:0]$11173 4'0000
+ assign $1\r2__data_o$next[3:0]$11071 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src32__data_o$next[3:0]$11178 4'0000
+ assign $6\r2__data_o$next[3:0]$11076 4'0000
case
- assign $6\src32__data_o$next[3:0]$11178 $1\src32__data_o$next[3:0]$11173
+ assign $6\r2__data_o$next[3:0]$11076 $1\r2__data_o$next[3:0]$11071
end
sync always
- update \src32__data_o$next $0\src32__data_o$next[3:0]$11172
+ update \r2__data_o$next $0\r2__data_o$next[3:0]$11070
end
- attribute \src "libresoc.v:181264.3-181293.6"
- process $proc$libresoc.v:181264$11179
+ attribute \src "libresoc.v:180628.3-180657.6"
+ process $proc$libresoc.v:180628$11077
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11180 $1\wr_detect$10[0:0]$11181
- attribute \src "libresoc.v:181265.5-181265.29"
+ assign $0\wr_detect$10[0:0]$11078 $1\wr_detect$10[0:0]$11079
+ attribute \src "libresoc.v:180629.5-180629.29"
switch \initial
- attribute \src "libresoc.v:181265.9-181265.17"
+ attribute \src "libresoc.v:180629.9-180629.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src32__ren
+ switch \r2__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11181 $4\wr_detect$10[0:0]$11184
+ assign $1\wr_detect$10[0:0]$11079 $4\wr_detect$10[0:0]$11082
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11182 1'1
+ assign $2\wr_detect$10[0:0]$11080 1'1
case
- assign $2\wr_detect$10[0:0]$11182 1'0
+ assign $2\wr_detect$10[0:0]$11080 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11183 1'1
+ assign $3\wr_detect$10[0:0]$11081 1'1
case
- assign $3\wr_detect$10[0:0]$11183 $2\wr_detect$10[0:0]$11182
+ assign $3\wr_detect$10[0:0]$11081 $2\wr_detect$10[0:0]$11080
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11184 1'1
+ assign $4\wr_detect$10[0:0]$11082 1'1
case
- assign $4\wr_detect$10[0:0]$11184 $3\wr_detect$10[0:0]$11183
+ assign $4\wr_detect$10[0:0]$11082 $3\wr_detect$10[0:0]$11081
end
case
- assign $1\wr_detect$10[0:0]$11181 1'0
+ assign $1\wr_detect$10[0:0]$11079 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11180
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11078
end
- attribute \src "libresoc.v:181294.3-181333.6"
- process $proc$libresoc.v:181294$11185
+ attribute \src "libresoc.v:180658.3-180697.6"
+ process $proc$libresoc.v:180658$11083
assign { } { }
assign { } { }
assign { } { }
- assign $0\r2__data_o$next[3:0]$11186 $6\r2__data_o$next[3:0]$11192
- attribute \src "libresoc.v:181295.5-181295.29"
+ assign $0\r22__data_o$next[3:0]$11084 $6\r22__data_o$next[3:0]$11090
+ attribute \src "libresoc.v:180659.5-180659.29"
switch \initial
- attribute \src "libresoc.v:181295.9-181295.17"
+ attribute \src "libresoc.v:180659.9-180659.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r2__ren
+ switch \r22__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r2__data_o$next[3:0]$11187 $5\r2__data_o$next[3:0]$11191
+ assign $1\r22__data_o$next[3:0]$11085 $5\r22__data_o$next[3:0]$11089
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r2__data_o$next[3:0]$11188 \dest12__data_i
+ assign $2\r22__data_o$next[3:0]$11086 \dest12__data_i
case
- assign $2\r2__data_o$next[3:0]$11188 4'0000
+ assign $2\r22__data_o$next[3:0]$11086 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r2__data_o$next[3:0]$11189 \dest22__data_i
+ assign $3\r22__data_o$next[3:0]$11087 \dest22__data_i
case
- assign $3\r2__data_o$next[3:0]$11189 $2\r2__data_o$next[3:0]$11188
+ assign $3\r22__data_o$next[3:0]$11087 $2\r22__data_o$next[3:0]$11086
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r2__data_o$next[3:0]$11190 \w2__data_i
+ assign $4\r22__data_o$next[3:0]$11088 \w2__data_i
case
- assign $4\r2__data_o$next[3:0]$11190 $3\r2__data_o$next[3:0]$11189
+ assign $4\r22__data_o$next[3:0]$11088 $3\r22__data_o$next[3:0]$11087
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r2__data_o$next[3:0]$11191 \reg
+ assign $5\r22__data_o$next[3:0]$11089 \reg
case
- assign $5\r2__data_o$next[3:0]$11191 $4\r2__data_o$next[3:0]$11190
+ assign $5\r22__data_o$next[3:0]$11089 $4\r22__data_o$next[3:0]$11088
end
case
- assign $1\r2__data_o$next[3:0]$11187 4'0000
+ assign $1\r22__data_o$next[3:0]$11085 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r2__data_o$next[3:0]$11192 4'0000
+ assign $6\r22__data_o$next[3:0]$11090 4'0000
case
- assign $6\r2__data_o$next[3:0]$11192 $1\r2__data_o$next[3:0]$11187
+ assign $6\r22__data_o$next[3:0]$11090 $1\r22__data_o$next[3:0]$11085
end
sync always
- update \r2__data_o$next $0\r2__data_o$next[3:0]$11186
+ update \r22__data_o$next $0\r22__data_o$next[3:0]$11084
end
- attribute \src "libresoc.v:181334.3-181363.6"
- process $proc$libresoc.v:181334$11193
+ attribute \src "libresoc.v:180698.3-180727.6"
+ process $proc$libresoc.v:180698$11091
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11194 $1\wr_detect$13[0:0]$11195
- attribute \src "libresoc.v:181335.5-181335.29"
+ assign $0\wr_detect$13[0:0]$11092 $1\wr_detect$13[0:0]$11093
+ attribute \src "libresoc.v:180699.5-180699.29"
switch \initial
- attribute \src "libresoc.v:181335.9-181335.17"
+ attribute \src "libresoc.v:180699.9-180699.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r2__ren
+ switch \r22__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11195 $4\wr_detect$13[0:0]$11198
+ assign $1\wr_detect$13[0:0]$11093 $4\wr_detect$13[0:0]$11096
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11196 1'1
+ assign $2\wr_detect$13[0:0]$11094 1'1
case
- assign $2\wr_detect$13[0:0]$11196 1'0
+ assign $2\wr_detect$13[0:0]$11094 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11197 1'1
+ assign $3\wr_detect$13[0:0]$11095 1'1
case
- assign $3\wr_detect$13[0:0]$11197 $2\wr_detect$13[0:0]$11196
+ assign $3\wr_detect$13[0:0]$11095 $2\wr_detect$13[0:0]$11094
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11198 1'1
+ assign $4\wr_detect$13[0:0]$11096 1'1
case
- assign $4\wr_detect$13[0:0]$11198 $3\wr_detect$13[0:0]$11197
+ assign $4\wr_detect$13[0:0]$11096 $3\wr_detect$13[0:0]$11095
end
case
- assign $1\wr_detect$13[0:0]$11195 1'0
+ assign $1\wr_detect$13[0:0]$11093 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11194
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11092
end
- connect \$9 $not$libresoc.v:180897$11101_Y
- connect \$12 $not$libresoc.v:180898$11102_Y
- connect \$15 $not$libresoc.v:180899$11103_Y
- connect \$1 $not$libresoc.v:180900$11104_Y
- connect \$3 $not$libresoc.v:180901$11105_Y
- connect \$6 $not$libresoc.v:180902$11106_Y
+ connect \$9 $not$libresoc.v:180334$11015_Y
+ connect \$12 $not$libresoc.v:180335$11016_Y
+ connect \$1 $not$libresoc.v:180336$11017_Y
+ connect \$3 $not$libresoc.v:180337$11018_Y
+ connect \$6 $not$libresoc.v:180338$11019_Y
end
-attribute \src "libresoc.v:181368.1-181813.10"
+attribute \src "libresoc.v:180732.1-181177.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2"
attribute \generator "nMigen"
module \reg_2$134
- attribute \src "libresoc.v:181369.7-181369.20"
+ attribute \src "libresoc.v:180733.7-180733.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $0\r2__data_o$next[1:0]$11259
- attribute \src "libresoc.v:181444.3-181445.37"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $0\r2__data_o$next[1:0]$11156
+ attribute \src "libresoc.v:180808.3-180809.37"
wire width 2 $0\r2__data_o[1:0]
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $0\reg$next[1:0]$11275
- attribute \src "libresoc.v:181442.3-181443.25"
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $0\reg$next[1:0]$11172
+ attribute \src "libresoc.v:180806.3-180807.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $0\src12__data_o$next[1:0]$11217
- attribute \src "libresoc.v:181450.3-181451.43"
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $0\src12__data_o$next[1:0]$11114
+ attribute \src "libresoc.v:180814.3-180815.43"
wire width 2 $0\src12__data_o[1:0]
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $0\src22__data_o$next[1:0]$11227
- attribute \src "libresoc.v:181448.3-181449.43"
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $0\src22__data_o$next[1:0]$11124
+ attribute \src "libresoc.v:180812.3-180813.43"
wire width 2 $0\src22__data_o[1:0]
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $0\src32__data_o$next[1:0]$11243
- attribute \src "libresoc.v:181446.3-181447.43"
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $0\src32__data_o$next[1:0]$11140
+ attribute \src "libresoc.v:180810.3-180811.43"
wire width 2 $0\src32__data_o[1:0]
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $0\wr_detect$10[0:0]$11268
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $0\wr_detect$4[0:0]$11236
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $0\wr_detect$7[0:0]$11252
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $0\wr_detect$10[0:0]$11165
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $0\wr_detect$4[0:0]$11133
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $0\wr_detect$7[0:0]$11149
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $1\r2__data_o$next[1:0]$11260
- attribute \src "libresoc.v:181396.13-181396.30"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $1\r2__data_o$next[1:0]$11157
+ attribute \src "libresoc.v:180760.13-180760.30"
wire width 2 $1\r2__data_o[1:0]
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $1\reg$next[1:0]$11276
- attribute \src "libresoc.v:181402.13-181402.25"
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $1\reg$next[1:0]$11173
+ attribute \src "libresoc.v:180766.13-180766.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $1\src12__data_o$next[1:0]$11218
- attribute \src "libresoc.v:181407.13-181407.33"
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $1\src12__data_o$next[1:0]$11115
+ attribute \src "libresoc.v:180771.13-180771.33"
wire width 2 $1\src12__data_o[1:0]
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $1\src22__data_o$next[1:0]$11228
- attribute \src "libresoc.v:181414.13-181414.33"
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $1\src22__data_o$next[1:0]$11125
+ attribute \src "libresoc.v:180778.13-180778.33"
wire width 2 $1\src22__data_o[1:0]
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $1\src32__data_o$next[1:0]$11244
- attribute \src "libresoc.v:181421.13-181421.33"
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $1\src32__data_o$next[1:0]$11141
+ attribute \src "libresoc.v:180785.13-180785.33"
wire width 2 $1\src32__data_o[1:0]
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $1\wr_detect$10[0:0]$11269
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $1\wr_detect$4[0:0]$11237
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $1\wr_detect$7[0:0]$11253
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $1\wr_detect$10[0:0]$11166
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $1\wr_detect$4[0:0]$11134
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $1\wr_detect$7[0:0]$11150
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $2\r2__data_o$next[1:0]$11261
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $2\reg$next[1:0]$11277
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $2\src12__data_o$next[1:0]$11219
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $2\src22__data_o$next[1:0]$11229
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $2\src32__data_o$next[1:0]$11245
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $2\wr_detect$10[0:0]$11270
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $2\wr_detect$4[0:0]$11238
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $2\wr_detect$7[0:0]$11254
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $2\r2__data_o$next[1:0]$11158
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $2\reg$next[1:0]$11174
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $2\src12__data_o$next[1:0]$11116
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $2\src22__data_o$next[1:0]$11126
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $2\src32__data_o$next[1:0]$11142
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $2\wr_detect$10[0:0]$11167
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $2\wr_detect$4[0:0]$11135
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $2\wr_detect$7[0:0]$11151
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $3\r2__data_o$next[1:0]$11262
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $3\reg$next[1:0]$11278
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $3\src12__data_o$next[1:0]$11220
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $3\src22__data_o$next[1:0]$11230
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $3\src32__data_o$next[1:0]$11246
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $3\wr_detect$10[0:0]$11271
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $3\wr_detect$4[0:0]$11239
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $3\wr_detect$7[0:0]$11255
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $3\r2__data_o$next[1:0]$11159
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $3\reg$next[1:0]$11175
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $3\src12__data_o$next[1:0]$11117
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $3\src22__data_o$next[1:0]$11127
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $3\src32__data_o$next[1:0]$11143
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $3\wr_detect$10[0:0]$11168
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $3\wr_detect$4[0:0]$11136
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $3\wr_detect$7[0:0]$11152
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $4\r2__data_o$next[1:0]$11263
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $4\reg$next[1:0]$11279
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $4\src12__data_o$next[1:0]$11221
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $4\src22__data_o$next[1:0]$11231
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $4\src32__data_o$next[1:0]$11247
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $4\wr_detect$10[0:0]$11272
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $4\wr_detect$4[0:0]$11240
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $4\wr_detect$7[0:0]$11256
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $4\r2__data_o$next[1:0]$11160
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $4\reg$next[1:0]$11176
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $4\src12__data_o$next[1:0]$11118
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $4\src22__data_o$next[1:0]$11128
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $4\src32__data_o$next[1:0]$11144
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $4\wr_detect$10[0:0]$11169
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $4\wr_detect$4[0:0]$11137
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $4\wr_detect$7[0:0]$11153
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $5\r2__data_o$next[1:0]$11264
- attribute \src "libresoc.v:181780.3-181812.6"
- wire width 2 $5\reg$next[1:0]$11280
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $5\src12__data_o$next[1:0]$11222
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $5\src22__data_o$next[1:0]$11232
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $5\src32__data_o$next[1:0]$11248
- attribute \src "libresoc.v:181744.3-181779.6"
- wire $5\wr_detect$10[0:0]$11273
- attribute \src "libresoc.v:181580.3-181615.6"
- wire $5\wr_detect$4[0:0]$11241
- attribute \src "libresoc.v:181662.3-181697.6"
- wire $5\wr_detect$7[0:0]$11257
- attribute \src "libresoc.v:181498.3-181533.6"
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $5\r2__data_o$next[1:0]$11161
+ attribute \src "libresoc.v:181144.3-181176.6"
+ wire width 2 $5\reg$next[1:0]$11177
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $5\src12__data_o$next[1:0]$11119
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $5\src22__data_o$next[1:0]$11129
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $5\src32__data_o$next[1:0]$11145
+ attribute \src "libresoc.v:181108.3-181143.6"
+ wire $5\wr_detect$10[0:0]$11170
+ attribute \src "libresoc.v:180944.3-180979.6"
+ wire $5\wr_detect$4[0:0]$11138
+ attribute \src "libresoc.v:181026.3-181061.6"
+ wire $5\wr_detect$7[0:0]$11154
+ attribute \src "libresoc.v:180862.3-180897.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $6\r2__data_o$next[1:0]$11265
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $6\src12__data_o$next[1:0]$11223
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $6\src22__data_o$next[1:0]$11233
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $6\src32__data_o$next[1:0]$11249
- attribute \src "libresoc.v:181698.3-181743.6"
- wire width 2 $7\r2__data_o$next[1:0]$11266
- attribute \src "libresoc.v:181452.3-181497.6"
- wire width 2 $7\src12__data_o$next[1:0]$11224
- attribute \src "libresoc.v:181534.3-181579.6"
- wire width 2 $7\src22__data_o$next[1:0]$11234
- attribute \src "libresoc.v:181616.3-181661.6"
- wire width 2 $7\src32__data_o$next[1:0]$11250
- attribute \src "libresoc.v:181438.17-181438.104"
- wire $not$libresoc.v:181438$11207_Y
- attribute \src "libresoc.v:181439.17-181439.100"
- wire $not$libresoc.v:181439$11208_Y
- attribute \src "libresoc.v:181440.17-181440.103"
- wire $not$libresoc.v:181440$11209_Y
- attribute \src "libresoc.v:181441.17-181441.103"
- wire $not$libresoc.v:181441$11210_Y
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $6\r2__data_o$next[1:0]$11162
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $6\src12__data_o$next[1:0]$11120
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $6\src22__data_o$next[1:0]$11130
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $6\src32__data_o$next[1:0]$11146
+ attribute \src "libresoc.v:181062.3-181107.6"
+ wire width 2 $7\r2__data_o$next[1:0]$11163
+ attribute \src "libresoc.v:180816.3-180861.6"
+ wire width 2 $7\src12__data_o$next[1:0]$11121
+ attribute \src "libresoc.v:180898.3-180943.6"
+ wire width 2 $7\src22__data_o$next[1:0]$11131
+ attribute \src "libresoc.v:180980.3-181025.6"
+ wire width 2 $7\src32__data_o$next[1:0]$11147
+ attribute \src "libresoc.v:180802.17-180802.104"
+ wire $not$libresoc.v:180802$11104_Y
+ attribute \src "libresoc.v:180803.17-180803.100"
+ wire $not$libresoc.v:180803$11105_Y
+ attribute \src "libresoc.v:180804.17-180804.103"
+ wire $not$libresoc.v:180804$11106_Y
+ attribute \src "libresoc.v:180805.17-180805.103"
+ wire $not$libresoc.v:180805$11107_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest12__data_i
wire width 2 input 13 \dest32__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest32__wen
- attribute \src "libresoc.v:181369.7-181369.15"
+ attribute \src "libresoc.v:180733.7-180733.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r2__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181438$11207
+ cell $not $not$libresoc.v:180802$11104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:181438$11207_Y
+ connect \Y $not$libresoc.v:180802$11104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181439$11208
+ cell $not $not$libresoc.v:180803$11105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:181439$11208_Y
+ connect \Y $not$libresoc.v:180803$11105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181440$11209
+ cell $not $not$libresoc.v:180804$11106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:181440$11209_Y
+ connect \Y $not$libresoc.v:180804$11106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181441$11210
+ cell $not $not$libresoc.v:180805$11107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:181441$11210_Y
+ connect \Y $not$libresoc.v:180805$11107_Y
end
- attribute \src "libresoc.v:181369.7-181369.20"
- process $proc$libresoc.v:181369$11281
+ attribute \src "libresoc.v:180733.7-180733.20"
+ process $proc$libresoc.v:180733$11178
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181396.13-181396.30"
- process $proc$libresoc.v:181396$11282
+ attribute \src "libresoc.v:180760.13-180760.30"
+ process $proc$libresoc.v:180760$11179
assign { } { }
assign $1\r2__data_o[1:0] 2'00
sync always
sync init
update \r2__data_o $1\r2__data_o[1:0]
end
- attribute \src "libresoc.v:181402.13-181402.25"
- process $proc$libresoc.v:181402$11283
+ attribute \src "libresoc.v:180766.13-180766.25"
+ process $proc$libresoc.v:180766$11180
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:181407.13-181407.33"
- process $proc$libresoc.v:181407$11284
+ attribute \src "libresoc.v:180771.13-180771.33"
+ process $proc$libresoc.v:180771$11181
assign { } { }
assign $1\src12__data_o[1:0] 2'00
sync always
sync init
update \src12__data_o $1\src12__data_o[1:0]
end
- attribute \src "libresoc.v:181414.13-181414.33"
- process $proc$libresoc.v:181414$11285
+ attribute \src "libresoc.v:180778.13-180778.33"
+ process $proc$libresoc.v:180778$11182
assign { } { }
assign $1\src22__data_o[1:0] 2'00
sync always
sync init
update \src22__data_o $1\src22__data_o[1:0]
end
- attribute \src "libresoc.v:181421.13-181421.33"
- process $proc$libresoc.v:181421$11286
+ attribute \src "libresoc.v:180785.13-180785.33"
+ process $proc$libresoc.v:180785$11183
assign { } { }
assign $1\src32__data_o[1:0] 2'00
sync always
sync init
update \src32__data_o $1\src32__data_o[1:0]
end
- attribute \src "libresoc.v:181442.3-181443.25"
- process $proc$libresoc.v:181442$11211
+ attribute \src "libresoc.v:180806.3-180807.25"
+ process $proc$libresoc.v:180806$11108
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:181444.3-181445.37"
- process $proc$libresoc.v:181444$11212
+ attribute \src "libresoc.v:180808.3-180809.37"
+ process $proc$libresoc.v:180808$11109
assign { } { }
assign $0\r2__data_o[1:0] \r2__data_o$next
sync posedge \coresync_clk
update \r2__data_o $0\r2__data_o[1:0]
end
- attribute \src "libresoc.v:181446.3-181447.43"
- process $proc$libresoc.v:181446$11213
+ attribute \src "libresoc.v:180810.3-180811.43"
+ process $proc$libresoc.v:180810$11110
assign { } { }
assign $0\src32__data_o[1:0] \src32__data_o$next
sync posedge \coresync_clk
update \src32__data_o $0\src32__data_o[1:0]
end
- attribute \src "libresoc.v:181448.3-181449.43"
- process $proc$libresoc.v:181448$11214
+ attribute \src "libresoc.v:180812.3-180813.43"
+ process $proc$libresoc.v:180812$11111
assign { } { }
assign $0\src22__data_o[1:0] \src22__data_o$next
sync posedge \coresync_clk
update \src22__data_o $0\src22__data_o[1:0]
end
- attribute \src "libresoc.v:181450.3-181451.43"
- process $proc$libresoc.v:181450$11215
+ attribute \src "libresoc.v:180814.3-180815.43"
+ process $proc$libresoc.v:180814$11112
assign { } { }
assign $0\src12__data_o[1:0] \src12__data_o$next
sync posedge \coresync_clk
update \src12__data_o $0\src12__data_o[1:0]
end
- attribute \src "libresoc.v:181452.3-181497.6"
- process $proc$libresoc.v:181452$11216
+ attribute \src "libresoc.v:180816.3-180861.6"
+ process $proc$libresoc.v:180816$11113
assign { } { }
assign { } { }
assign { } { }
- assign $0\src12__data_o$next[1:0]$11217 $7\src12__data_o$next[1:0]$11224
- attribute \src "libresoc.v:181453.5-181453.29"
+ assign $0\src12__data_o$next[1:0]$11114 $7\src12__data_o$next[1:0]$11121
+ attribute \src "libresoc.v:180817.5-180817.29"
switch \initial
- attribute \src "libresoc.v:181453.9-181453.17"
+ attribute \src "libresoc.v:180817.9-180817.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src12__data_o$next[1:0]$11218 $6\src12__data_o$next[1:0]$11223
+ assign $1\src12__data_o$next[1:0]$11115 $6\src12__data_o$next[1:0]$11120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src12__data_o$next[1:0]$11219 \dest12__data_i
+ assign $2\src12__data_o$next[1:0]$11116 \dest12__data_i
case
- assign $2\src12__data_o$next[1:0]$11219 2'00
+ assign $2\src12__data_o$next[1:0]$11116 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src12__data_o$next[1:0]$11220 \dest22__data_i
+ assign $3\src12__data_o$next[1:0]$11117 \dest22__data_i
case
- assign $3\src12__data_o$next[1:0]$11220 $2\src12__data_o$next[1:0]$11219
+ assign $3\src12__data_o$next[1:0]$11117 $2\src12__data_o$next[1:0]$11116
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src12__data_o$next[1:0]$11221 \dest32__data_i
+ assign $4\src12__data_o$next[1:0]$11118 \dest32__data_i
case
- assign $4\src12__data_o$next[1:0]$11221 $3\src12__data_o$next[1:0]$11220
+ assign $4\src12__data_o$next[1:0]$11118 $3\src12__data_o$next[1:0]$11117
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src12__data_o$next[1:0]$11222 \w2__data_i
+ assign $5\src12__data_o$next[1:0]$11119 \w2__data_i
case
- assign $5\src12__data_o$next[1:0]$11222 $4\src12__data_o$next[1:0]$11221
+ assign $5\src12__data_o$next[1:0]$11119 $4\src12__data_o$next[1:0]$11118
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src12__data_o$next[1:0]$11223 \reg
+ assign $6\src12__data_o$next[1:0]$11120 \reg
case
- assign $6\src12__data_o$next[1:0]$11223 $5\src12__data_o$next[1:0]$11222
+ assign $6\src12__data_o$next[1:0]$11120 $5\src12__data_o$next[1:0]$11119
end
case
- assign $1\src12__data_o$next[1:0]$11218 2'00
+ assign $1\src12__data_o$next[1:0]$11115 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src12__data_o$next[1:0]$11224 2'00
+ assign $7\src12__data_o$next[1:0]$11121 2'00
case
- assign $7\src12__data_o$next[1:0]$11224 $1\src12__data_o$next[1:0]$11218
+ assign $7\src12__data_o$next[1:0]$11121 $1\src12__data_o$next[1:0]$11115
end
sync always
- update \src12__data_o$next $0\src12__data_o$next[1:0]$11217
+ update \src12__data_o$next $0\src12__data_o$next[1:0]$11114
end
- attribute \src "libresoc.v:181498.3-181533.6"
- process $proc$libresoc.v:181498$11225
+ attribute \src "libresoc.v:180862.3-180897.6"
+ process $proc$libresoc.v:180862$11122
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:181499.5-181499.29"
+ attribute \src "libresoc.v:180863.5-180863.29"
switch \initial
- attribute \src "libresoc.v:181499.9-181499.17"
+ attribute \src "libresoc.v:180863.9-180863.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:181534.3-181579.6"
- process $proc$libresoc.v:181534$11226
+ attribute \src "libresoc.v:180898.3-180943.6"
+ process $proc$libresoc.v:180898$11123
assign { } { }
assign { } { }
assign { } { }
- assign $0\src22__data_o$next[1:0]$11227 $7\src22__data_o$next[1:0]$11234
- attribute \src "libresoc.v:181535.5-181535.29"
+ assign $0\src22__data_o$next[1:0]$11124 $7\src22__data_o$next[1:0]$11131
+ attribute \src "libresoc.v:180899.5-180899.29"
switch \initial
- attribute \src "libresoc.v:181535.9-181535.17"
+ attribute \src "libresoc.v:180899.9-180899.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src22__data_o$next[1:0]$11228 $6\src22__data_o$next[1:0]$11233
+ assign $1\src22__data_o$next[1:0]$11125 $6\src22__data_o$next[1:0]$11130
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src22__data_o$next[1:0]$11229 \dest12__data_i
+ assign $2\src22__data_o$next[1:0]$11126 \dest12__data_i
case
- assign $2\src22__data_o$next[1:0]$11229 2'00
+ assign $2\src22__data_o$next[1:0]$11126 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src22__data_o$next[1:0]$11230 \dest22__data_i
+ assign $3\src22__data_o$next[1:0]$11127 \dest22__data_i
case
- assign $3\src22__data_o$next[1:0]$11230 $2\src22__data_o$next[1:0]$11229
+ assign $3\src22__data_o$next[1:0]$11127 $2\src22__data_o$next[1:0]$11126
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src22__data_o$next[1:0]$11231 \dest32__data_i
+ assign $4\src22__data_o$next[1:0]$11128 \dest32__data_i
case
- assign $4\src22__data_o$next[1:0]$11231 $3\src22__data_o$next[1:0]$11230
+ assign $4\src22__data_o$next[1:0]$11128 $3\src22__data_o$next[1:0]$11127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src22__data_o$next[1:0]$11232 \w2__data_i
+ assign $5\src22__data_o$next[1:0]$11129 \w2__data_i
case
- assign $5\src22__data_o$next[1:0]$11232 $4\src22__data_o$next[1:0]$11231
+ assign $5\src22__data_o$next[1:0]$11129 $4\src22__data_o$next[1:0]$11128
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src22__data_o$next[1:0]$11233 \reg
+ assign $6\src22__data_o$next[1:0]$11130 \reg
case
- assign $6\src22__data_o$next[1:0]$11233 $5\src22__data_o$next[1:0]$11232
+ assign $6\src22__data_o$next[1:0]$11130 $5\src22__data_o$next[1:0]$11129
end
case
- assign $1\src22__data_o$next[1:0]$11228 2'00
+ assign $1\src22__data_o$next[1:0]$11125 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src22__data_o$next[1:0]$11234 2'00
+ assign $7\src22__data_o$next[1:0]$11131 2'00
case
- assign $7\src22__data_o$next[1:0]$11234 $1\src22__data_o$next[1:0]$11228
+ assign $7\src22__data_o$next[1:0]$11131 $1\src22__data_o$next[1:0]$11125
end
sync always
- update \src22__data_o$next $0\src22__data_o$next[1:0]$11227
+ update \src22__data_o$next $0\src22__data_o$next[1:0]$11124
end
- attribute \src "libresoc.v:181580.3-181615.6"
- process $proc$libresoc.v:181580$11235
+ attribute \src "libresoc.v:180944.3-180979.6"
+ process $proc$libresoc.v:180944$11132
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11236 $1\wr_detect$4[0:0]$11237
- attribute \src "libresoc.v:181581.5-181581.29"
+ assign $0\wr_detect$4[0:0]$11133 $1\wr_detect$4[0:0]$11134
+ attribute \src "libresoc.v:180945.5-180945.29"
switch \initial
- attribute \src "libresoc.v:181581.9-181581.17"
+ attribute \src "libresoc.v:180945.9-180945.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11237 $5\wr_detect$4[0:0]$11241
+ assign $1\wr_detect$4[0:0]$11134 $5\wr_detect$4[0:0]$11138
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11238 1'1
+ assign $2\wr_detect$4[0:0]$11135 1'1
case
- assign $2\wr_detect$4[0:0]$11238 1'0
+ assign $2\wr_detect$4[0:0]$11135 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11239 1'1
+ assign $3\wr_detect$4[0:0]$11136 1'1
case
- assign $3\wr_detect$4[0:0]$11239 $2\wr_detect$4[0:0]$11238
+ assign $3\wr_detect$4[0:0]$11136 $2\wr_detect$4[0:0]$11135
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11240 1'1
+ assign $4\wr_detect$4[0:0]$11137 1'1
case
- assign $4\wr_detect$4[0:0]$11240 $3\wr_detect$4[0:0]$11239
+ assign $4\wr_detect$4[0:0]$11137 $3\wr_detect$4[0:0]$11136
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11241 1'1
+ assign $5\wr_detect$4[0:0]$11138 1'1
case
- assign $5\wr_detect$4[0:0]$11241 $4\wr_detect$4[0:0]$11240
+ assign $5\wr_detect$4[0:0]$11138 $4\wr_detect$4[0:0]$11137
end
case
- assign $1\wr_detect$4[0:0]$11237 1'0
+ assign $1\wr_detect$4[0:0]$11134 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11236
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11133
end
- attribute \src "libresoc.v:181616.3-181661.6"
- process $proc$libresoc.v:181616$11242
+ attribute \src "libresoc.v:180980.3-181025.6"
+ process $proc$libresoc.v:180980$11139
assign { } { }
assign { } { }
assign { } { }
- assign $0\src32__data_o$next[1:0]$11243 $7\src32__data_o$next[1:0]$11250
- attribute \src "libresoc.v:181617.5-181617.29"
+ assign $0\src32__data_o$next[1:0]$11140 $7\src32__data_o$next[1:0]$11147
+ attribute \src "libresoc.v:180981.5-180981.29"
switch \initial
- attribute \src "libresoc.v:181617.9-181617.17"
+ attribute \src "libresoc.v:180981.9-180981.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src32__data_o$next[1:0]$11244 $6\src32__data_o$next[1:0]$11249
+ assign $1\src32__data_o$next[1:0]$11141 $6\src32__data_o$next[1:0]$11146
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src32__data_o$next[1:0]$11245 \dest12__data_i
+ assign $2\src32__data_o$next[1:0]$11142 \dest12__data_i
case
- assign $2\src32__data_o$next[1:0]$11245 2'00
+ assign $2\src32__data_o$next[1:0]$11142 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src32__data_o$next[1:0]$11246 \dest22__data_i
+ assign $3\src32__data_o$next[1:0]$11143 \dest22__data_i
case
- assign $3\src32__data_o$next[1:0]$11246 $2\src32__data_o$next[1:0]$11245
+ assign $3\src32__data_o$next[1:0]$11143 $2\src32__data_o$next[1:0]$11142
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src32__data_o$next[1:0]$11247 \dest32__data_i
+ assign $4\src32__data_o$next[1:0]$11144 \dest32__data_i
case
- assign $4\src32__data_o$next[1:0]$11247 $3\src32__data_o$next[1:0]$11246
+ assign $4\src32__data_o$next[1:0]$11144 $3\src32__data_o$next[1:0]$11143
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src32__data_o$next[1:0]$11248 \w2__data_i
+ assign $5\src32__data_o$next[1:0]$11145 \w2__data_i
case
- assign $5\src32__data_o$next[1:0]$11248 $4\src32__data_o$next[1:0]$11247
+ assign $5\src32__data_o$next[1:0]$11145 $4\src32__data_o$next[1:0]$11144
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src32__data_o$next[1:0]$11249 \reg
+ assign $6\src32__data_o$next[1:0]$11146 \reg
case
- assign $6\src32__data_o$next[1:0]$11249 $5\src32__data_o$next[1:0]$11248
+ assign $6\src32__data_o$next[1:0]$11146 $5\src32__data_o$next[1:0]$11145
end
case
- assign $1\src32__data_o$next[1:0]$11244 2'00
+ assign $1\src32__data_o$next[1:0]$11141 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src32__data_o$next[1:0]$11250 2'00
+ assign $7\src32__data_o$next[1:0]$11147 2'00
case
- assign $7\src32__data_o$next[1:0]$11250 $1\src32__data_o$next[1:0]$11244
+ assign $7\src32__data_o$next[1:0]$11147 $1\src32__data_o$next[1:0]$11141
end
sync always
- update \src32__data_o$next $0\src32__data_o$next[1:0]$11243
+ update \src32__data_o$next $0\src32__data_o$next[1:0]$11140
end
- attribute \src "libresoc.v:181662.3-181697.6"
- process $proc$libresoc.v:181662$11251
+ attribute \src "libresoc.v:181026.3-181061.6"
+ process $proc$libresoc.v:181026$11148
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11252 $1\wr_detect$7[0:0]$11253
- attribute \src "libresoc.v:181663.5-181663.29"
+ assign $0\wr_detect$7[0:0]$11149 $1\wr_detect$7[0:0]$11150
+ attribute \src "libresoc.v:181027.5-181027.29"
switch \initial
- attribute \src "libresoc.v:181663.9-181663.17"
+ attribute \src "libresoc.v:181027.9-181027.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11253 $5\wr_detect$7[0:0]$11257
+ assign $1\wr_detect$7[0:0]$11150 $5\wr_detect$7[0:0]$11154
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11254 1'1
+ assign $2\wr_detect$7[0:0]$11151 1'1
case
- assign $2\wr_detect$7[0:0]$11254 1'0
+ assign $2\wr_detect$7[0:0]$11151 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11255 1'1
+ assign $3\wr_detect$7[0:0]$11152 1'1
case
- assign $3\wr_detect$7[0:0]$11255 $2\wr_detect$7[0:0]$11254
+ assign $3\wr_detect$7[0:0]$11152 $2\wr_detect$7[0:0]$11151
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11256 1'1
+ assign $4\wr_detect$7[0:0]$11153 1'1
case
- assign $4\wr_detect$7[0:0]$11256 $3\wr_detect$7[0:0]$11255
+ assign $4\wr_detect$7[0:0]$11153 $3\wr_detect$7[0:0]$11152
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11257 1'1
+ assign $5\wr_detect$7[0:0]$11154 1'1
case
- assign $5\wr_detect$7[0:0]$11257 $4\wr_detect$7[0:0]$11256
+ assign $5\wr_detect$7[0:0]$11154 $4\wr_detect$7[0:0]$11153
end
case
- assign $1\wr_detect$7[0:0]$11253 1'0
+ assign $1\wr_detect$7[0:0]$11150 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11252
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11149
end
- attribute \src "libresoc.v:181698.3-181743.6"
- process $proc$libresoc.v:181698$11258
+ attribute \src "libresoc.v:181062.3-181107.6"
+ process $proc$libresoc.v:181062$11155
assign { } { }
assign { } { }
assign { } { }
- assign $0\r2__data_o$next[1:0]$11259 $7\r2__data_o$next[1:0]$11266
- attribute \src "libresoc.v:181699.5-181699.29"
+ assign $0\r2__data_o$next[1:0]$11156 $7\r2__data_o$next[1:0]$11163
+ attribute \src "libresoc.v:181063.5-181063.29"
switch \initial
- attribute \src "libresoc.v:181699.9-181699.17"
+ attribute \src "libresoc.v:181063.9-181063.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r2__data_o$next[1:0]$11260 $6\r2__data_o$next[1:0]$11265
+ assign $1\r2__data_o$next[1:0]$11157 $6\r2__data_o$next[1:0]$11162
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r2__data_o$next[1:0]$11261 \dest12__data_i
+ assign $2\r2__data_o$next[1:0]$11158 \dest12__data_i
case
- assign $2\r2__data_o$next[1:0]$11261 2'00
+ assign $2\r2__data_o$next[1:0]$11158 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r2__data_o$next[1:0]$11262 \dest22__data_i
+ assign $3\r2__data_o$next[1:0]$11159 \dest22__data_i
case
- assign $3\r2__data_o$next[1:0]$11262 $2\r2__data_o$next[1:0]$11261
+ assign $3\r2__data_o$next[1:0]$11159 $2\r2__data_o$next[1:0]$11158
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r2__data_o$next[1:0]$11263 \dest32__data_i
+ assign $4\r2__data_o$next[1:0]$11160 \dest32__data_i
case
- assign $4\r2__data_o$next[1:0]$11263 $3\r2__data_o$next[1:0]$11262
+ assign $4\r2__data_o$next[1:0]$11160 $3\r2__data_o$next[1:0]$11159
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r2__data_o$next[1:0]$11264 \w2__data_i
+ assign $5\r2__data_o$next[1:0]$11161 \w2__data_i
case
- assign $5\r2__data_o$next[1:0]$11264 $4\r2__data_o$next[1:0]$11263
+ assign $5\r2__data_o$next[1:0]$11161 $4\r2__data_o$next[1:0]$11160
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r2__data_o$next[1:0]$11265 \reg
+ assign $6\r2__data_o$next[1:0]$11162 \reg
case
- assign $6\r2__data_o$next[1:0]$11265 $5\r2__data_o$next[1:0]$11264
+ assign $6\r2__data_o$next[1:0]$11162 $5\r2__data_o$next[1:0]$11161
end
case
- assign $1\r2__data_o$next[1:0]$11260 2'00
+ assign $1\r2__data_o$next[1:0]$11157 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r2__data_o$next[1:0]$11266 2'00
+ assign $7\r2__data_o$next[1:0]$11163 2'00
case
- assign $7\r2__data_o$next[1:0]$11266 $1\r2__data_o$next[1:0]$11260
+ assign $7\r2__data_o$next[1:0]$11163 $1\r2__data_o$next[1:0]$11157
end
sync always
- update \r2__data_o$next $0\r2__data_o$next[1:0]$11259
+ update \r2__data_o$next $0\r2__data_o$next[1:0]$11156
end
- attribute \src "libresoc.v:181744.3-181779.6"
- process $proc$libresoc.v:181744$11267
+ attribute \src "libresoc.v:181108.3-181143.6"
+ process $proc$libresoc.v:181108$11164
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11268 $1\wr_detect$10[0:0]$11269
- attribute \src "libresoc.v:181745.5-181745.29"
+ assign $0\wr_detect$10[0:0]$11165 $1\wr_detect$10[0:0]$11166
+ attribute \src "libresoc.v:181109.5-181109.29"
switch \initial
- attribute \src "libresoc.v:181745.9-181745.17"
+ attribute \src "libresoc.v:181109.9-181109.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11269 $5\wr_detect$10[0:0]$11273
+ assign $1\wr_detect$10[0:0]$11166 $5\wr_detect$10[0:0]$11170
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11270 1'1
+ assign $2\wr_detect$10[0:0]$11167 1'1
case
- assign $2\wr_detect$10[0:0]$11270 1'0
+ assign $2\wr_detect$10[0:0]$11167 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11271 1'1
+ assign $3\wr_detect$10[0:0]$11168 1'1
case
- assign $3\wr_detect$10[0:0]$11271 $2\wr_detect$10[0:0]$11270
+ assign $3\wr_detect$10[0:0]$11168 $2\wr_detect$10[0:0]$11167
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11272 1'1
+ assign $4\wr_detect$10[0:0]$11169 1'1
case
- assign $4\wr_detect$10[0:0]$11272 $3\wr_detect$10[0:0]$11271
+ assign $4\wr_detect$10[0:0]$11169 $3\wr_detect$10[0:0]$11168
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$11273 1'1
+ assign $5\wr_detect$10[0:0]$11170 1'1
case
- assign $5\wr_detect$10[0:0]$11273 $4\wr_detect$10[0:0]$11272
+ assign $5\wr_detect$10[0:0]$11170 $4\wr_detect$10[0:0]$11169
end
case
- assign $1\wr_detect$10[0:0]$11269 1'0
+ assign $1\wr_detect$10[0:0]$11166 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11268
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11165
end
- attribute \src "libresoc.v:181780.3-181812.6"
- process $proc$libresoc.v:181780$11274
+ attribute \src "libresoc.v:181144.3-181176.6"
+ process $proc$libresoc.v:181144$11171
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$11275 $5\reg$next[1:0]$11280
- attribute \src "libresoc.v:181781.5-181781.29"
+ assign $0\reg$next[1:0]$11172 $5\reg$next[1:0]$11177
+ attribute \src "libresoc.v:181145.5-181145.29"
switch \initial
- attribute \src "libresoc.v:181781.9-181781.17"
+ attribute \src "libresoc.v:181145.9-181145.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$11276 \dest12__data_i
+ assign $1\reg$next[1:0]$11173 \dest12__data_i
case
- assign $1\reg$next[1:0]$11276 \reg
+ assign $1\reg$next[1:0]$11173 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$11277 \dest22__data_i
+ assign $2\reg$next[1:0]$11174 \dest22__data_i
case
- assign $2\reg$next[1:0]$11277 $1\reg$next[1:0]$11276
+ assign $2\reg$next[1:0]$11174 $1\reg$next[1:0]$11173
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$11278 \dest32__data_i
+ assign $3\reg$next[1:0]$11175 \dest32__data_i
case
- assign $3\reg$next[1:0]$11278 $2\reg$next[1:0]$11277
+ assign $3\reg$next[1:0]$11175 $2\reg$next[1:0]$11174
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$11279 \w2__data_i
+ assign $4\reg$next[1:0]$11176 \w2__data_i
case
- assign $4\reg$next[1:0]$11279 $3\reg$next[1:0]$11278
+ assign $4\reg$next[1:0]$11176 $3\reg$next[1:0]$11175
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$11280 2'00
+ assign $5\reg$next[1:0]$11177 2'00
case
- assign $5\reg$next[1:0]$11280 $4\reg$next[1:0]$11279
+ assign $5\reg$next[1:0]$11177 $4\reg$next[1:0]$11176
end
sync always
- update \reg$next $0\reg$next[1:0]$11275
+ update \reg$next $0\reg$next[1:0]$11172
end
- connect \$9 $not$libresoc.v:181438$11207_Y
- connect \$1 $not$libresoc.v:181439$11208_Y
- connect \$3 $not$libresoc.v:181440$11209_Y
- connect \$6 $not$libresoc.v:181441$11210_Y
+ connect \$9 $not$libresoc.v:180802$11104_Y
+ connect \$1 $not$libresoc.v:180803$11105_Y
+ connect \$3 $not$libresoc.v:180804$11106_Y
+ connect \$6 $not$libresoc.v:180805$11107_Y
end
-attribute \src "libresoc.v:181817.1-182166.10"
+attribute \src "libresoc.v:181181.1-181530.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2"
attribute \generator "nMigen"
module \reg_2$137
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $0\cia2__data_o$next[63:0]$11295
- attribute \src "libresoc.v:181885.3-181886.41"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $0\cia2__data_o$next[63:0]$11192
+ attribute \src "libresoc.v:181249.3-181250.41"
wire width 64 $0\cia2__data_o[63:0]
- attribute \src "libresoc.v:181818.7-181818.20"
+ attribute \src "libresoc.v:181182.7-181182.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $0\msr2__data_o$next[63:0]$11305
- attribute \src "libresoc.v:181883.3-181884.41"
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $0\msr2__data_o$next[63:0]$11202
+ attribute \src "libresoc.v:181247.3-181248.41"
wire width 64 $0\msr2__data_o[63:0]
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $0\reg$next[63:0]$11337
- attribute \src "libresoc.v:181879.3-181880.25"
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $0\reg$next[63:0]$11234
+ attribute \src "libresoc.v:181243.3-181244.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $0\sv2__data_o$next[63:0]$11321
- attribute \src "libresoc.v:181881.3-181882.39"
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $0\sv2__data_o$next[63:0]$11218
+ attribute \src "libresoc.v:181245.3-181246.39"
wire width 64 $0\sv2__data_o[63:0]
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $0\wr_detect$4[0:0]$11314
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $0\wr_detect$7[0:0]$11330
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $0\wr_detect$4[0:0]$11211
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $0\wr_detect$7[0:0]$11227
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $1\cia2__data_o$next[63:0]$11296
- attribute \src "libresoc.v:181827.14-181827.49"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $1\cia2__data_o$next[63:0]$11193
+ attribute \src "libresoc.v:181191.14-181191.49"
wire width 64 $1\cia2__data_o[63:0]
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $1\msr2__data_o$next[63:0]$11306
- attribute \src "libresoc.v:181844.14-181844.49"
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $1\msr2__data_o$next[63:0]$11203
+ attribute \src "libresoc.v:181208.14-181208.49"
wire width 64 $1\msr2__data_o[63:0]
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $1\reg$next[63:0]$11338
- attribute \src "libresoc.v:181856.14-181856.42"
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $1\reg$next[63:0]$11235
+ attribute \src "libresoc.v:181220.14-181220.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $1\sv2__data_o$next[63:0]$11322
- attribute \src "libresoc.v:181863.14-181863.48"
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $1\sv2__data_o$next[63:0]$11219
+ attribute \src "libresoc.v:181227.14-181227.48"
wire width 64 $1\sv2__data_o[63:0]
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $1\wr_detect$4[0:0]$11315
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $1\wr_detect$7[0:0]$11331
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $1\wr_detect$4[0:0]$11212
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $1\wr_detect$7[0:0]$11228
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $2\cia2__data_o$next[63:0]$11297
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $2\msr2__data_o$next[63:0]$11307
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $2\reg$next[63:0]$11339
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $2\sv2__data_o$next[63:0]$11323
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $2\wr_detect$4[0:0]$11316
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $2\wr_detect$7[0:0]$11332
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $2\cia2__data_o$next[63:0]$11194
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $2\msr2__data_o$next[63:0]$11204
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $2\reg$next[63:0]$11236
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $2\sv2__data_o$next[63:0]$11220
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $2\wr_detect$4[0:0]$11213
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $2\wr_detect$7[0:0]$11229
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $3\cia2__data_o$next[63:0]$11298
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $3\msr2__data_o$next[63:0]$11308
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $3\reg$next[63:0]$11340
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $3\sv2__data_o$next[63:0]$11324
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $3\wr_detect$4[0:0]$11317
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $3\wr_detect$7[0:0]$11333
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $3\cia2__data_o$next[63:0]$11195
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $3\msr2__data_o$next[63:0]$11205
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $3\reg$next[63:0]$11237
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $3\sv2__data_o$next[63:0]$11221
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $3\wr_detect$4[0:0]$11214
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $3\wr_detect$7[0:0]$11230
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $4\cia2__data_o$next[63:0]$11299
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $4\msr2__data_o$next[63:0]$11309
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $4\reg$next[63:0]$11341
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $4\sv2__data_o$next[63:0]$11325
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $4\wr_detect$4[0:0]$11318
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $4\wr_detect$7[0:0]$11334
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $4\cia2__data_o$next[63:0]$11196
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $4\msr2__data_o$next[63:0]$11206
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $4\reg$next[63:0]$11238
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $4\sv2__data_o$next[63:0]$11222
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $4\wr_detect$4[0:0]$11215
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $4\wr_detect$7[0:0]$11231
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $5\cia2__data_o$next[63:0]$11300
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $5\msr2__data_o$next[63:0]$11310
- attribute \src "libresoc.v:182133.3-182165.6"
- wire width 64 $5\reg$next[63:0]$11342
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $5\sv2__data_o$next[63:0]$11326
- attribute \src "libresoc.v:182015.3-182050.6"
- wire $5\wr_detect$4[0:0]$11319
- attribute \src "libresoc.v:182097.3-182132.6"
- wire $5\wr_detect$7[0:0]$11335
- attribute \src "libresoc.v:181933.3-181968.6"
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $5\cia2__data_o$next[63:0]$11197
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $5\msr2__data_o$next[63:0]$11207
+ attribute \src "libresoc.v:181497.3-181529.6"
+ wire width 64 $5\reg$next[63:0]$11239
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $5\sv2__data_o$next[63:0]$11223
+ attribute \src "libresoc.v:181379.3-181414.6"
+ wire $5\wr_detect$4[0:0]$11216
+ attribute \src "libresoc.v:181461.3-181496.6"
+ wire $5\wr_detect$7[0:0]$11232
+ attribute \src "libresoc.v:181297.3-181332.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $6\cia2__data_o$next[63:0]$11301
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $6\msr2__data_o$next[63:0]$11311
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $6\sv2__data_o$next[63:0]$11327
- attribute \src "libresoc.v:181887.3-181932.6"
- wire width 64 $7\cia2__data_o$next[63:0]$11302
- attribute \src "libresoc.v:181969.3-182014.6"
- wire width 64 $7\msr2__data_o$next[63:0]$11312
- attribute \src "libresoc.v:182051.3-182096.6"
- wire width 64 $7\sv2__data_o$next[63:0]$11328
- attribute \src "libresoc.v:181876.17-181876.100"
- wire $not$libresoc.v:181876$11287_Y
- attribute \src "libresoc.v:181877.17-181877.103"
- wire $not$libresoc.v:181877$11288_Y
- attribute \src "libresoc.v:181878.17-181878.103"
- wire $not$libresoc.v:181878$11289_Y
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $6\cia2__data_o$next[63:0]$11198
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $6\msr2__data_o$next[63:0]$11208
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $6\sv2__data_o$next[63:0]$11224
+ attribute \src "libresoc.v:181251.3-181296.6"
+ wire width 64 $7\cia2__data_o$next[63:0]$11199
+ attribute \src "libresoc.v:181333.3-181378.6"
+ wire width 64 $7\msr2__data_o$next[63:0]$11209
+ attribute \src "libresoc.v:181415.3-181460.6"
+ wire width 64 $7\sv2__data_o$next[63:0]$11225
+ attribute \src "libresoc.v:181240.17-181240.100"
+ wire $not$libresoc.v:181240$11184_Y
+ attribute \src "libresoc.v:181241.17-181241.103"
+ wire $not$libresoc.v:181241$11185_Y
+ attribute \src "libresoc.v:181242.17-181242.103"
+ wire $not$libresoc.v:181242$11186_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia2__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia2__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr12__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr12__wen
- attribute \src "libresoc.v:181818.7-181818.15"
+ attribute \src "libresoc.v:181182.7-181182.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr2__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181876$11287
+ cell $not $not$libresoc.v:181240$11184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:181876$11287_Y
+ connect \Y $not$libresoc.v:181240$11184_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181877$11288
+ cell $not $not$libresoc.v:181241$11185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:181877$11288_Y
+ connect \Y $not$libresoc.v:181241$11185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181878$11289
+ cell $not $not$libresoc.v:181242$11186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:181878$11289_Y
+ connect \Y $not$libresoc.v:181242$11186_Y
end
- attribute \src "libresoc.v:181818.7-181818.20"
- process $proc$libresoc.v:181818$11343
+ attribute \src "libresoc.v:181182.7-181182.20"
+ process $proc$libresoc.v:181182$11240
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181827.14-181827.49"
- process $proc$libresoc.v:181827$11344
+ attribute \src "libresoc.v:181191.14-181191.49"
+ process $proc$libresoc.v:181191$11241
assign { } { }
assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia2__data_o $1\cia2__data_o[63:0]
end
- attribute \src "libresoc.v:181844.14-181844.49"
- process $proc$libresoc.v:181844$11345
+ attribute \src "libresoc.v:181208.14-181208.49"
+ process $proc$libresoc.v:181208$11242
assign { } { }
assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr2__data_o $1\msr2__data_o[63:0]
end
- attribute \src "libresoc.v:181856.14-181856.42"
- process $proc$libresoc.v:181856$11346
+ attribute \src "libresoc.v:181220.14-181220.42"
+ process $proc$libresoc.v:181220$11243
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:181863.14-181863.48"
- process $proc$libresoc.v:181863$11347
+ attribute \src "libresoc.v:181227.14-181227.48"
+ process $proc$libresoc.v:181227$11244
assign { } { }
assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv2__data_o $1\sv2__data_o[63:0]
end
- attribute \src "libresoc.v:181879.3-181880.25"
- process $proc$libresoc.v:181879$11290
+ attribute \src "libresoc.v:181243.3-181244.25"
+ process $proc$libresoc.v:181243$11187
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:181881.3-181882.39"
- process $proc$libresoc.v:181881$11291
+ attribute \src "libresoc.v:181245.3-181246.39"
+ process $proc$libresoc.v:181245$11188
assign { } { }
assign $0\sv2__data_o[63:0] \sv2__data_o$next
sync posedge \coresync_clk
update \sv2__data_o $0\sv2__data_o[63:0]
end
- attribute \src "libresoc.v:181883.3-181884.41"
- process $proc$libresoc.v:181883$11292
+ attribute \src "libresoc.v:181247.3-181248.41"
+ process $proc$libresoc.v:181247$11189
assign { } { }
assign $0\msr2__data_o[63:0] \msr2__data_o$next
sync posedge \coresync_clk
update \msr2__data_o $0\msr2__data_o[63:0]
end
- attribute \src "libresoc.v:181885.3-181886.41"
- process $proc$libresoc.v:181885$11293
+ attribute \src "libresoc.v:181249.3-181250.41"
+ process $proc$libresoc.v:181249$11190
assign { } { }
assign $0\cia2__data_o[63:0] \cia2__data_o$next
sync posedge \coresync_clk
update \cia2__data_o $0\cia2__data_o[63:0]
end
- attribute \src "libresoc.v:181887.3-181932.6"
- process $proc$libresoc.v:181887$11294
+ attribute \src "libresoc.v:181251.3-181296.6"
+ process $proc$libresoc.v:181251$11191
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia2__data_o$next[63:0]$11295 $7\cia2__data_o$next[63:0]$11302
- attribute \src "libresoc.v:181888.5-181888.29"
+ assign $0\cia2__data_o$next[63:0]$11192 $7\cia2__data_o$next[63:0]$11199
+ attribute \src "libresoc.v:181252.5-181252.29"
switch \initial
- attribute \src "libresoc.v:181888.9-181888.17"
+ attribute \src "libresoc.v:181252.9-181252.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia2__data_o$next[63:0]$11296 $6\cia2__data_o$next[63:0]$11301
+ assign $1\cia2__data_o$next[63:0]$11193 $6\cia2__data_o$next[63:0]$11198
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia2__data_o$next[63:0]$11297 \nia2__data_i
+ assign $2\cia2__data_o$next[63:0]$11194 \nia2__data_i
case
- assign $2\cia2__data_o$next[63:0]$11297 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia2__data_o$next[63:0]$11194 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia2__data_o$next[63:0]$11298 \msr2__data_i
+ assign $3\cia2__data_o$next[63:0]$11195 \msr2__data_i
case
- assign $3\cia2__data_o$next[63:0]$11298 $2\cia2__data_o$next[63:0]$11297
+ assign $3\cia2__data_o$next[63:0]$11195 $2\cia2__data_o$next[63:0]$11194
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia2__data_o$next[63:0]$11299 \sv2__data_i
+ assign $4\cia2__data_o$next[63:0]$11196 \sv2__data_i
case
- assign $4\cia2__data_o$next[63:0]$11299 $3\cia2__data_o$next[63:0]$11298
+ assign $4\cia2__data_o$next[63:0]$11196 $3\cia2__data_o$next[63:0]$11195
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia2__data_o$next[63:0]$11300 \d_wr12__data_i
+ assign $5\cia2__data_o$next[63:0]$11197 \d_wr12__data_i
case
- assign $5\cia2__data_o$next[63:0]$11300 $4\cia2__data_o$next[63:0]$11299
+ assign $5\cia2__data_o$next[63:0]$11197 $4\cia2__data_o$next[63:0]$11196
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia2__data_o$next[63:0]$11301 \reg
+ assign $6\cia2__data_o$next[63:0]$11198 \reg
case
- assign $6\cia2__data_o$next[63:0]$11301 $5\cia2__data_o$next[63:0]$11300
+ assign $6\cia2__data_o$next[63:0]$11198 $5\cia2__data_o$next[63:0]$11197
end
case
- assign $1\cia2__data_o$next[63:0]$11296 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia2__data_o$next[63:0]$11193 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia2__data_o$next[63:0]$11302 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia2__data_o$next[63:0]$11199 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia2__data_o$next[63:0]$11302 $1\cia2__data_o$next[63:0]$11296
+ assign $7\cia2__data_o$next[63:0]$11199 $1\cia2__data_o$next[63:0]$11193
end
sync always
- update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11295
+ update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11192
end
- attribute \src "libresoc.v:181933.3-181968.6"
- process $proc$libresoc.v:181933$11303
+ attribute \src "libresoc.v:181297.3-181332.6"
+ process $proc$libresoc.v:181297$11200
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:181934.5-181934.29"
+ attribute \src "libresoc.v:181298.5-181298.29"
switch \initial
- attribute \src "libresoc.v:181934.9-181934.17"
+ attribute \src "libresoc.v:181298.9-181298.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:181969.3-182014.6"
- process $proc$libresoc.v:181969$11304
+ attribute \src "libresoc.v:181333.3-181378.6"
+ process $proc$libresoc.v:181333$11201
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr2__data_o$next[63:0]$11305 $7\msr2__data_o$next[63:0]$11312
- attribute \src "libresoc.v:181970.5-181970.29"
+ assign $0\msr2__data_o$next[63:0]$11202 $7\msr2__data_o$next[63:0]$11209
+ attribute \src "libresoc.v:181334.5-181334.29"
switch \initial
- attribute \src "libresoc.v:181970.9-181970.17"
+ attribute \src "libresoc.v:181334.9-181334.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr2__data_o$next[63:0]$11306 $6\msr2__data_o$next[63:0]$11311
+ assign $1\msr2__data_o$next[63:0]$11203 $6\msr2__data_o$next[63:0]$11208
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr2__data_o$next[63:0]$11307 \nia2__data_i
+ assign $2\msr2__data_o$next[63:0]$11204 \nia2__data_i
case
- assign $2\msr2__data_o$next[63:0]$11307 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr2__data_o$next[63:0]$11204 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr2__data_o$next[63:0]$11308 \msr2__data_i
+ assign $3\msr2__data_o$next[63:0]$11205 \msr2__data_i
case
- assign $3\msr2__data_o$next[63:0]$11308 $2\msr2__data_o$next[63:0]$11307
+ assign $3\msr2__data_o$next[63:0]$11205 $2\msr2__data_o$next[63:0]$11204
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr2__data_o$next[63:0]$11309 \sv2__data_i
+ assign $4\msr2__data_o$next[63:0]$11206 \sv2__data_i
case
- assign $4\msr2__data_o$next[63:0]$11309 $3\msr2__data_o$next[63:0]$11308
+ assign $4\msr2__data_o$next[63:0]$11206 $3\msr2__data_o$next[63:0]$11205
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr2__data_o$next[63:0]$11310 \d_wr12__data_i
+ assign $5\msr2__data_o$next[63:0]$11207 \d_wr12__data_i
case
- assign $5\msr2__data_o$next[63:0]$11310 $4\msr2__data_o$next[63:0]$11309
+ assign $5\msr2__data_o$next[63:0]$11207 $4\msr2__data_o$next[63:0]$11206
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr2__data_o$next[63:0]$11311 \reg
+ assign $6\msr2__data_o$next[63:0]$11208 \reg
case
- assign $6\msr2__data_o$next[63:0]$11311 $5\msr2__data_o$next[63:0]$11310
+ assign $6\msr2__data_o$next[63:0]$11208 $5\msr2__data_o$next[63:0]$11207
end
case
- assign $1\msr2__data_o$next[63:0]$11306 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr2__data_o$next[63:0]$11203 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr2__data_o$next[63:0]$11209 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr2__data_o$next[63:0]$11312 $1\msr2__data_o$next[63:0]$11306
+ assign $7\msr2__data_o$next[63:0]$11209 $1\msr2__data_o$next[63:0]$11203
end
sync always
- update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11305
+ update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11202
end
- attribute \src "libresoc.v:182015.3-182050.6"
- process $proc$libresoc.v:182015$11313
+ attribute \src "libresoc.v:181379.3-181414.6"
+ process $proc$libresoc.v:181379$11210
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11314 $1\wr_detect$4[0:0]$11315
- attribute \src "libresoc.v:182016.5-182016.29"
+ assign $0\wr_detect$4[0:0]$11211 $1\wr_detect$4[0:0]$11212
+ attribute \src "libresoc.v:181380.5-181380.29"
switch \initial
- attribute \src "libresoc.v:182016.9-182016.17"
+ attribute \src "libresoc.v:181380.9-181380.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11315 $5\wr_detect$4[0:0]$11319
+ assign $1\wr_detect$4[0:0]$11212 $5\wr_detect$4[0:0]$11216
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11316 1'1
+ assign $2\wr_detect$4[0:0]$11213 1'1
case
- assign $2\wr_detect$4[0:0]$11316 1'0
+ assign $2\wr_detect$4[0:0]$11213 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11317 1'1
+ assign $3\wr_detect$4[0:0]$11214 1'1
case
- assign $3\wr_detect$4[0:0]$11317 $2\wr_detect$4[0:0]$11316
+ assign $3\wr_detect$4[0:0]$11214 $2\wr_detect$4[0:0]$11213
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11318 1'1
+ assign $4\wr_detect$4[0:0]$11215 1'1
case
- assign $4\wr_detect$4[0:0]$11318 $3\wr_detect$4[0:0]$11317
+ assign $4\wr_detect$4[0:0]$11215 $3\wr_detect$4[0:0]$11214
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11319 1'1
+ assign $5\wr_detect$4[0:0]$11216 1'1
case
- assign $5\wr_detect$4[0:0]$11319 $4\wr_detect$4[0:0]$11318
+ assign $5\wr_detect$4[0:0]$11216 $4\wr_detect$4[0:0]$11215
end
case
- assign $1\wr_detect$4[0:0]$11315 1'0
+ assign $1\wr_detect$4[0:0]$11212 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11314
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11211
end
- attribute \src "libresoc.v:182051.3-182096.6"
- process $proc$libresoc.v:182051$11320
+ attribute \src "libresoc.v:181415.3-181460.6"
+ process $proc$libresoc.v:181415$11217
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv2__data_o$next[63:0]$11321 $7\sv2__data_o$next[63:0]$11328
- attribute \src "libresoc.v:182052.5-182052.29"
+ assign $0\sv2__data_o$next[63:0]$11218 $7\sv2__data_o$next[63:0]$11225
+ attribute \src "libresoc.v:181416.5-181416.29"
switch \initial
- attribute \src "libresoc.v:182052.9-182052.17"
+ attribute \src "libresoc.v:181416.9-181416.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv2__data_o$next[63:0]$11322 $6\sv2__data_o$next[63:0]$11327
+ assign $1\sv2__data_o$next[63:0]$11219 $6\sv2__data_o$next[63:0]$11224
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv2__data_o$next[63:0]$11323 \nia2__data_i
+ assign $2\sv2__data_o$next[63:0]$11220 \nia2__data_i
case
- assign $2\sv2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv2__data_o$next[63:0]$11220 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv2__data_o$next[63:0]$11324 \msr2__data_i
+ assign $3\sv2__data_o$next[63:0]$11221 \msr2__data_i
case
- assign $3\sv2__data_o$next[63:0]$11324 $2\sv2__data_o$next[63:0]$11323
+ assign $3\sv2__data_o$next[63:0]$11221 $2\sv2__data_o$next[63:0]$11220
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv2__data_o$next[63:0]$11325 \sv2__data_i
+ assign $4\sv2__data_o$next[63:0]$11222 \sv2__data_i
case
- assign $4\sv2__data_o$next[63:0]$11325 $3\sv2__data_o$next[63:0]$11324
+ assign $4\sv2__data_o$next[63:0]$11222 $3\sv2__data_o$next[63:0]$11221
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv2__data_o$next[63:0]$11326 \d_wr12__data_i
+ assign $5\sv2__data_o$next[63:0]$11223 \d_wr12__data_i
case
- assign $5\sv2__data_o$next[63:0]$11326 $4\sv2__data_o$next[63:0]$11325
+ assign $5\sv2__data_o$next[63:0]$11223 $4\sv2__data_o$next[63:0]$11222
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv2__data_o$next[63:0]$11327 \reg
+ assign $6\sv2__data_o$next[63:0]$11224 \reg
case
- assign $6\sv2__data_o$next[63:0]$11327 $5\sv2__data_o$next[63:0]$11326
+ assign $6\sv2__data_o$next[63:0]$11224 $5\sv2__data_o$next[63:0]$11223
end
case
- assign $1\sv2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv2__data_o$next[63:0]$11225 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv2__data_o$next[63:0]$11328 $1\sv2__data_o$next[63:0]$11322
+ assign $7\sv2__data_o$next[63:0]$11225 $1\sv2__data_o$next[63:0]$11219
end
sync always
- update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11321
+ update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11218
end
- attribute \src "libresoc.v:182097.3-182132.6"
- process $proc$libresoc.v:182097$11329
+ attribute \src "libresoc.v:181461.3-181496.6"
+ process $proc$libresoc.v:181461$11226
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11330 $1\wr_detect$7[0:0]$11331
- attribute \src "libresoc.v:182098.5-182098.29"
+ assign $0\wr_detect$7[0:0]$11227 $1\wr_detect$7[0:0]$11228
+ attribute \src "libresoc.v:181462.5-181462.29"
switch \initial
- attribute \src "libresoc.v:182098.9-182098.17"
+ attribute \src "libresoc.v:181462.9-181462.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11331 $5\wr_detect$7[0:0]$11335
+ assign $1\wr_detect$7[0:0]$11228 $5\wr_detect$7[0:0]$11232
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11332 1'1
+ assign $2\wr_detect$7[0:0]$11229 1'1
case
- assign $2\wr_detect$7[0:0]$11332 1'0
+ assign $2\wr_detect$7[0:0]$11229 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11333 1'1
+ assign $3\wr_detect$7[0:0]$11230 1'1
case
- assign $3\wr_detect$7[0:0]$11333 $2\wr_detect$7[0:0]$11332
+ assign $3\wr_detect$7[0:0]$11230 $2\wr_detect$7[0:0]$11229
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11334 1'1
+ assign $4\wr_detect$7[0:0]$11231 1'1
case
- assign $4\wr_detect$7[0:0]$11334 $3\wr_detect$7[0:0]$11333
+ assign $4\wr_detect$7[0:0]$11231 $3\wr_detect$7[0:0]$11230
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11335 1'1
+ assign $5\wr_detect$7[0:0]$11232 1'1
case
- assign $5\wr_detect$7[0:0]$11335 $4\wr_detect$7[0:0]$11334
+ assign $5\wr_detect$7[0:0]$11232 $4\wr_detect$7[0:0]$11231
end
case
- assign $1\wr_detect$7[0:0]$11331 1'0
+ assign $1\wr_detect$7[0:0]$11228 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11330
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11227
end
- attribute \src "libresoc.v:182133.3-182165.6"
- process $proc$libresoc.v:182133$11336
+ attribute \src "libresoc.v:181497.3-181529.6"
+ process $proc$libresoc.v:181497$11233
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$11337 $5\reg$next[63:0]$11342
- attribute \src "libresoc.v:182134.5-182134.29"
+ assign $0\reg$next[63:0]$11234 $5\reg$next[63:0]$11239
+ attribute \src "libresoc.v:181498.5-181498.29"
switch \initial
- attribute \src "libresoc.v:182134.9-182134.17"
+ attribute \src "libresoc.v:181498.9-181498.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$11338 \nia2__data_i
+ assign $1\reg$next[63:0]$11235 \nia2__data_i
case
- assign $1\reg$next[63:0]$11338 \reg
+ assign $1\reg$next[63:0]$11235 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$11339 \msr2__data_i
+ assign $2\reg$next[63:0]$11236 \msr2__data_i
case
- assign $2\reg$next[63:0]$11339 $1\reg$next[63:0]$11338
+ assign $2\reg$next[63:0]$11236 $1\reg$next[63:0]$11235
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$11340 \sv2__data_i
+ assign $3\reg$next[63:0]$11237 \sv2__data_i
case
- assign $3\reg$next[63:0]$11340 $2\reg$next[63:0]$11339
+ assign $3\reg$next[63:0]$11237 $2\reg$next[63:0]$11236
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$11341 \d_wr12__data_i
+ assign $4\reg$next[63:0]$11238 \d_wr12__data_i
case
- assign $4\reg$next[63:0]$11341 $3\reg$next[63:0]$11340
+ assign $4\reg$next[63:0]$11238 $3\reg$next[63:0]$11237
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$11342 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$11342 $4\reg$next[63:0]$11341
+ assign $5\reg$next[63:0]$11239 $4\reg$next[63:0]$11238
end
sync always
- update \reg$next $0\reg$next[63:0]$11337
+ update \reg$next $0\reg$next[63:0]$11234
end
- connect \$1 $not$libresoc.v:181876$11287_Y
- connect \$3 $not$libresoc.v:181877$11288_Y
- connect \$6 $not$libresoc.v:181878$11289_Y
+ connect \$1 $not$libresoc.v:181240$11184_Y
+ connect \$3 $not$libresoc.v:181241$11185_Y
+ connect \$6 $not$libresoc.v:181242$11186_Y
end
-attribute \src "libresoc.v:182170.1-182725.10"
+attribute \src "libresoc.v:181534.1-182005.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3"
attribute \generator "nMigen"
module \reg_3
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $0\cr_pred3__data_o$next[3:0]$11362
- attribute \src "libresoc.v:182276.3-182277.49"
- wire width 4 $0\cr_pred3__data_o[3:0]
- attribute \src "libresoc.v:182171.7-182171.20"
+ attribute \src "libresoc.v:181535.7-181535.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $0\r23__data_o$next[3:0]$11371
- attribute \src "libresoc.v:182266.3-182267.39"
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $0\r23__data_o$next[3:0]$11314
+ attribute \src "libresoc.v:181618.3-181619.39"
wire width 4 $0\r23__data_o[3:0]
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $0\r3__data_o$next[3:0]$11433
- attribute \src "libresoc.v:182268.3-182269.37"
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $0\r3__data_o$next[3:0]$11300
+ attribute \src "libresoc.v:181620.3-181621.37"
wire width 4 $0\r3__data_o[3:0]
- attribute \src "libresoc.v:182418.3-182444.6"
- wire width 4 $0\reg$next[3:0]$11385
- attribute \src "libresoc.v:182264.3-182265.25"
+ attribute \src "libresoc.v:181698.3-181724.6"
+ wire width 4 $0\reg$next[3:0]$11266
+ attribute \src "libresoc.v:181616.3-181617.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $0\src13__data_o$next[3:0]$11391
- attribute \src "libresoc.v:182274.3-182275.43"
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $0\src13__data_o$next[3:0]$11257
+ attribute \src "libresoc.v:181626.3-181627.43"
wire width 4 $0\src13__data_o[3:0]
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $0\src23__data_o$next[3:0]$11405
- attribute \src "libresoc.v:182272.3-182273.43"
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $0\src23__data_o$next[3:0]$11272
+ attribute \src "libresoc.v:181624.3-181625.43"
wire width 4 $0\src23__data_o[3:0]
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $0\src33__data_o$next[3:0]$11419
- attribute \src "libresoc.v:182270.3-182271.43"
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $0\src33__data_o$next[3:0]$11286
+ attribute \src "libresoc.v:181622.3-181623.43"
wire width 4 $0\src33__data_o[3:0]
- attribute \src "libresoc.v:182625.3-182654.6"
- wire $0\wr_detect$10[0:0]$11427
- attribute \src "libresoc.v:182695.3-182724.6"
- wire $0\wr_detect$13[0:0]$11441
- attribute \src "libresoc.v:182388.3-182417.6"
- wire $0\wr_detect$16[0:0]$11379
- attribute \src "libresoc.v:182485.3-182514.6"
- wire $0\wr_detect$4[0:0]$11399
- attribute \src "libresoc.v:182555.3-182584.6"
- wire $0\wr_detect$7[0:0]$11413
- attribute \src "libresoc.v:182318.3-182347.6"
+ attribute \src "libresoc.v:181905.3-181934.6"
+ wire $0\wr_detect$10[0:0]$11308
+ attribute \src "libresoc.v:181975.3-182004.6"
+ wire $0\wr_detect$13[0:0]$11322
+ attribute \src "libresoc.v:181765.3-181794.6"
+ wire $0\wr_detect$4[0:0]$11280
+ attribute \src "libresoc.v:181835.3-181864.6"
+ wire $0\wr_detect$7[0:0]$11294
+ attribute \src "libresoc.v:181668.3-181697.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $1\cr_pred3__data_o$next[3:0]$11363
- attribute \src "libresoc.v:182190.13-182190.36"
- wire width 4 $1\cr_pred3__data_o[3:0]
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $1\r23__data_o$next[3:0]$11372
- attribute \src "libresoc.v:182205.13-182205.31"
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $1\r23__data_o$next[3:0]$11315
+ attribute \src "libresoc.v:181560.13-181560.31"
wire width 4 $1\r23__data_o[3:0]
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $1\r3__data_o$next[3:0]$11434
- attribute \src "libresoc.v:182212.13-182212.30"
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $1\r3__data_o$next[3:0]$11301
+ attribute \src "libresoc.v:181567.13-181567.30"
wire width 4 $1\r3__data_o[3:0]
- attribute \src "libresoc.v:182418.3-182444.6"
- wire width 4 $1\reg$next[3:0]$11386
- attribute \src "libresoc.v:182218.13-182218.25"
+ attribute \src "libresoc.v:181698.3-181724.6"
+ wire width 4 $1\reg$next[3:0]$11267
+ attribute \src "libresoc.v:181573.13-181573.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $1\src13__data_o$next[3:0]$11392
- attribute \src "libresoc.v:182223.13-182223.33"
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $1\src13__data_o$next[3:0]$11258
+ attribute \src "libresoc.v:181578.13-181578.33"
wire width 4 $1\src13__data_o[3:0]
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $1\src23__data_o$next[3:0]$11406
- attribute \src "libresoc.v:182230.13-182230.33"
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $1\src23__data_o$next[3:0]$11273
+ attribute \src "libresoc.v:181585.13-181585.33"
wire width 4 $1\src23__data_o[3:0]
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $1\src33__data_o$next[3:0]$11420
- attribute \src "libresoc.v:182237.13-182237.33"
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $1\src33__data_o$next[3:0]$11287
+ attribute \src "libresoc.v:181592.13-181592.33"
wire width 4 $1\src33__data_o[3:0]
- attribute \src "libresoc.v:182625.3-182654.6"
- wire $1\wr_detect$10[0:0]$11428
- attribute \src "libresoc.v:182695.3-182724.6"
- wire $1\wr_detect$13[0:0]$11442
- attribute \src "libresoc.v:182388.3-182417.6"
- wire $1\wr_detect$16[0:0]$11380
- attribute \src "libresoc.v:182485.3-182514.6"
- wire $1\wr_detect$4[0:0]$11400
- attribute \src "libresoc.v:182555.3-182584.6"
- wire $1\wr_detect$7[0:0]$11414
- attribute \src "libresoc.v:182318.3-182347.6"
+ attribute \src "libresoc.v:181905.3-181934.6"
+ wire $1\wr_detect$10[0:0]$11309
+ attribute \src "libresoc.v:181975.3-182004.6"
+ wire $1\wr_detect$13[0:0]$11323
+ attribute \src "libresoc.v:181765.3-181794.6"
+ wire $1\wr_detect$4[0:0]$11281
+ attribute \src "libresoc.v:181835.3-181864.6"
+ wire $1\wr_detect$7[0:0]$11295
+ attribute \src "libresoc.v:181668.3-181697.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $2\cr_pred3__data_o$next[3:0]$11364
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $2\r23__data_o$next[3:0]$11373
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $2\r3__data_o$next[3:0]$11435
- attribute \src "libresoc.v:182418.3-182444.6"
- wire width 4 $2\reg$next[3:0]$11387
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $2\src13__data_o$next[3:0]$11393
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $2\src23__data_o$next[3:0]$11407
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $2\src33__data_o$next[3:0]$11421
- attribute \src "libresoc.v:182625.3-182654.6"
- wire $2\wr_detect$10[0:0]$11429
- attribute \src "libresoc.v:182695.3-182724.6"
- wire $2\wr_detect$13[0:0]$11443
- attribute \src "libresoc.v:182388.3-182417.6"
- wire $2\wr_detect$16[0:0]$11381
- attribute \src "libresoc.v:182485.3-182514.6"
- wire $2\wr_detect$4[0:0]$11401
- attribute \src "libresoc.v:182555.3-182584.6"
- wire $2\wr_detect$7[0:0]$11415
- attribute \src "libresoc.v:182318.3-182347.6"
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $2\r23__data_o$next[3:0]$11316
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $2\r3__data_o$next[3:0]$11302
+ attribute \src "libresoc.v:181698.3-181724.6"
+ wire width 4 $2\reg$next[3:0]$11268
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $2\src13__data_o$next[3:0]$11259
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $2\src23__data_o$next[3:0]$11274
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $2\src33__data_o$next[3:0]$11288
+ attribute \src "libresoc.v:181905.3-181934.6"
+ wire $2\wr_detect$10[0:0]$11310
+ attribute \src "libresoc.v:181975.3-182004.6"
+ wire $2\wr_detect$13[0:0]$11324
+ attribute \src "libresoc.v:181765.3-181794.6"
+ wire $2\wr_detect$4[0:0]$11282
+ attribute \src "libresoc.v:181835.3-181864.6"
+ wire $2\wr_detect$7[0:0]$11296
+ attribute \src "libresoc.v:181668.3-181697.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $3\cr_pred3__data_o$next[3:0]$11365
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $3\r23__data_o$next[3:0]$11374
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $3\r3__data_o$next[3:0]$11436
- attribute \src "libresoc.v:182418.3-182444.6"
- wire width 4 $3\reg$next[3:0]$11388
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $3\src13__data_o$next[3:0]$11394
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $3\src23__data_o$next[3:0]$11408
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $3\src33__data_o$next[3:0]$11422
- attribute \src "libresoc.v:182625.3-182654.6"
- wire $3\wr_detect$10[0:0]$11430
- attribute \src "libresoc.v:182695.3-182724.6"
- wire $3\wr_detect$13[0:0]$11444
- attribute \src "libresoc.v:182388.3-182417.6"
- wire $3\wr_detect$16[0:0]$11382
- attribute \src "libresoc.v:182485.3-182514.6"
- wire $3\wr_detect$4[0:0]$11402
- attribute \src "libresoc.v:182555.3-182584.6"
- wire $3\wr_detect$7[0:0]$11416
- attribute \src "libresoc.v:182318.3-182347.6"
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $3\r23__data_o$next[3:0]$11317
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $3\r3__data_o$next[3:0]$11303
+ attribute \src "libresoc.v:181698.3-181724.6"
+ wire width 4 $3\reg$next[3:0]$11269
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $3\src13__data_o$next[3:0]$11260
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $3\src23__data_o$next[3:0]$11275
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $3\src33__data_o$next[3:0]$11289
+ attribute \src "libresoc.v:181905.3-181934.6"
+ wire $3\wr_detect$10[0:0]$11311
+ attribute \src "libresoc.v:181975.3-182004.6"
+ wire $3\wr_detect$13[0:0]$11325
+ attribute \src "libresoc.v:181765.3-181794.6"
+ wire $3\wr_detect$4[0:0]$11283
+ attribute \src "libresoc.v:181835.3-181864.6"
+ wire $3\wr_detect$7[0:0]$11297
+ attribute \src "libresoc.v:181668.3-181697.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $4\cr_pred3__data_o$next[3:0]$11366
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $4\r23__data_o$next[3:0]$11375
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $4\r3__data_o$next[3:0]$11437
- attribute \src "libresoc.v:182418.3-182444.6"
- wire width 4 $4\reg$next[3:0]$11389
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $4\src13__data_o$next[3:0]$11395
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $4\src23__data_o$next[3:0]$11409
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $4\src33__data_o$next[3:0]$11423
- attribute \src "libresoc.v:182625.3-182654.6"
- wire $4\wr_detect$10[0:0]$11431
- attribute \src "libresoc.v:182695.3-182724.6"
- wire $4\wr_detect$13[0:0]$11445
- attribute \src "libresoc.v:182388.3-182417.6"
- wire $4\wr_detect$16[0:0]$11383
- attribute \src "libresoc.v:182485.3-182514.6"
- wire $4\wr_detect$4[0:0]$11403
- attribute \src "libresoc.v:182555.3-182584.6"
- wire $4\wr_detect$7[0:0]$11417
- attribute \src "libresoc.v:182318.3-182347.6"
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $4\r23__data_o$next[3:0]$11318
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $4\r3__data_o$next[3:0]$11304
+ attribute \src "libresoc.v:181698.3-181724.6"
+ wire width 4 $4\reg$next[3:0]$11270
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $4\src13__data_o$next[3:0]$11261
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $4\src23__data_o$next[3:0]$11276
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $4\src33__data_o$next[3:0]$11290
+ attribute \src "libresoc.v:181905.3-181934.6"
+ wire $4\wr_detect$10[0:0]$11312
+ attribute \src "libresoc.v:181975.3-182004.6"
+ wire $4\wr_detect$13[0:0]$11326
+ attribute \src "libresoc.v:181765.3-181794.6"
+ wire $4\wr_detect$4[0:0]$11284
+ attribute \src "libresoc.v:181835.3-181864.6"
+ wire $4\wr_detect$7[0:0]$11298
+ attribute \src "libresoc.v:181668.3-181697.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $5\cr_pred3__data_o$next[3:0]$11367
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $5\r23__data_o$next[3:0]$11376
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $5\r3__data_o$next[3:0]$11438
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $5\src13__data_o$next[3:0]$11396
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $5\src23__data_o$next[3:0]$11410
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $5\src33__data_o$next[3:0]$11424
- attribute \src "libresoc.v:182278.3-182317.6"
- wire width 4 $6\cr_pred3__data_o$next[3:0]$11368
- attribute \src "libresoc.v:182348.3-182387.6"
- wire width 4 $6\r23__data_o$next[3:0]$11377
- attribute \src "libresoc.v:182655.3-182694.6"
- wire width 4 $6\r3__data_o$next[3:0]$11439
- attribute \src "libresoc.v:182445.3-182484.6"
- wire width 4 $6\src13__data_o$next[3:0]$11397
- attribute \src "libresoc.v:182515.3-182554.6"
- wire width 4 $6\src23__data_o$next[3:0]$11411
- attribute \src "libresoc.v:182585.3-182624.6"
- wire width 4 $6\src33__data_o$next[3:0]$11425
- attribute \src "libresoc.v:182258.17-182258.104"
- wire $not$libresoc.v:182258$11348_Y
- attribute \src "libresoc.v:182259.18-182259.105"
- wire $not$libresoc.v:182259$11349_Y
- attribute \src "libresoc.v:182260.18-182260.105"
- wire $not$libresoc.v:182260$11350_Y
- attribute \src "libresoc.v:182261.17-182261.100"
- wire $not$libresoc.v:182261$11351_Y
- attribute \src "libresoc.v:182262.17-182262.103"
- wire $not$libresoc.v:182262$11352_Y
- attribute \src "libresoc.v:182263.17-182263.103"
- wire $not$libresoc.v:182263$11353_Y
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $5\r23__data_o$next[3:0]$11319
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $5\r3__data_o$next[3:0]$11305
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $5\src13__data_o$next[3:0]$11262
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $5\src23__data_o$next[3:0]$11277
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $5\src33__data_o$next[3:0]$11291
+ attribute \src "libresoc.v:181935.3-181974.6"
+ wire width 4 $6\r23__data_o$next[3:0]$11320
+ attribute \src "libresoc.v:181865.3-181904.6"
+ wire width 4 $6\r3__data_o$next[3:0]$11306
+ attribute \src "libresoc.v:181628.3-181667.6"
+ wire width 4 $6\src13__data_o$next[3:0]$11263
+ attribute \src "libresoc.v:181725.3-181764.6"
+ wire width 4 $6\src23__data_o$next[3:0]$11278
+ attribute \src "libresoc.v:181795.3-181834.6"
+ wire width 4 $6\src33__data_o$next[3:0]$11292
+ attribute \src "libresoc.v:181611.17-181611.104"
+ wire $not$libresoc.v:181611$11245_Y
+ attribute \src "libresoc.v:181612.18-181612.105"
+ wire $not$libresoc.v:181612$11246_Y
+ attribute \src "libresoc.v:181613.17-181613.100"
+ wire $not$libresoc.v:181613$11247_Y
+ attribute \src "libresoc.v:181614.17-181614.103"
+ wire $not$libresoc.v:181614$11248_Y
+ attribute \src "libresoc.v:181615.17-181615.103"
+ wire $not$libresoc.v:181615$11249_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred3__data_o$next
+ wire width 4 input 9 \dest13__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred3__ren
+ wire input 8 \dest13__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest13__data_i
+ wire width 4 input 11 \dest23__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest13__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest23__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest23__wen
- attribute \src "libresoc.v:182171.7-182171.15"
+ wire input 10 \dest23__wen
+ attribute \src "libresoc.v:181535.7-181535.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r23__data_o
+ wire width 4 output 14 \r23__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r23__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r23__ren
+ wire input 15 \r23__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r3__data_o
+ wire width 4 output 12 \r3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r3__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r3__ren
+ wire input 13 \r3__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src13__data_o
+ wire width 4 output 3 \src13__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src13__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src13__ren
+ wire input 2 \src13__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src23__data_o
+ wire width 4 output 5 \src23__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src23__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src23__ren
+ wire input 4 \src23__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src33__data_o
+ wire width 4 output 7 \src33__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src33__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src33__ren
+ wire input 6 \src33__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w3__data_i
+ wire width 4 input 16 \w3__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w3__wen
+ wire input 17 \w3__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182258$11348
+ cell $not $not$libresoc.v:181611$11245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:182258$11348_Y
+ connect \Y $not$libresoc.v:181611$11245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182259$11349
+ cell $not $not$libresoc.v:181612$11246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:182259$11349_Y
+ connect \Y $not$libresoc.v:181612$11246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182260$11350
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:182260$11350_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182261$11351
+ cell $not $not$libresoc.v:181613$11247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:182261$11351_Y
+ connect \Y $not$libresoc.v:181613$11247_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182262$11352
+ cell $not $not$libresoc.v:181614$11248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:182262$11352_Y
+ connect \Y $not$libresoc.v:181614$11248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182263$11353
+ cell $not $not$libresoc.v:181615$11249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:182263$11353_Y
+ connect \Y $not$libresoc.v:181615$11249_Y
end
- attribute \src "libresoc.v:182171.7-182171.20"
- process $proc$libresoc.v:182171$11446
+ attribute \src "libresoc.v:181535.7-181535.20"
+ process $proc$libresoc.v:181535$11327
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182190.13-182190.36"
- process $proc$libresoc.v:182190$11447
- assign { } { }
- assign $1\cr_pred3__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred3__data_o $1\cr_pred3__data_o[3:0]
- end
- attribute \src "libresoc.v:182205.13-182205.31"
- process $proc$libresoc.v:182205$11448
+ attribute \src "libresoc.v:181560.13-181560.31"
+ process $proc$libresoc.v:181560$11328
assign { } { }
assign $1\r23__data_o[3:0] 4'0000
sync always
sync init
update \r23__data_o $1\r23__data_o[3:0]
end
- attribute \src "libresoc.v:182212.13-182212.30"
- process $proc$libresoc.v:182212$11449
+ attribute \src "libresoc.v:181567.13-181567.30"
+ process $proc$libresoc.v:181567$11329
assign { } { }
assign $1\r3__data_o[3:0] 4'0000
sync always
sync init
update \r3__data_o $1\r3__data_o[3:0]
end
- attribute \src "libresoc.v:182218.13-182218.25"
- process $proc$libresoc.v:182218$11450
+ attribute \src "libresoc.v:181573.13-181573.25"
+ process $proc$libresoc.v:181573$11330
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:182223.13-182223.33"
- process $proc$libresoc.v:182223$11451
+ attribute \src "libresoc.v:181578.13-181578.33"
+ process $proc$libresoc.v:181578$11331
assign { } { }
assign $1\src13__data_o[3:0] 4'0000
sync always
sync init
update \src13__data_o $1\src13__data_o[3:0]
end
- attribute \src "libresoc.v:182230.13-182230.33"
- process $proc$libresoc.v:182230$11452
+ attribute \src "libresoc.v:181585.13-181585.33"
+ process $proc$libresoc.v:181585$11332
assign { } { }
assign $1\src23__data_o[3:0] 4'0000
sync always
sync init
update \src23__data_o $1\src23__data_o[3:0]
end
- attribute \src "libresoc.v:182237.13-182237.33"
- process $proc$libresoc.v:182237$11453
+ attribute \src "libresoc.v:181592.13-181592.33"
+ process $proc$libresoc.v:181592$11333
assign { } { }
assign $1\src33__data_o[3:0] 4'0000
sync always
sync init
update \src33__data_o $1\src33__data_o[3:0]
end
- attribute \src "libresoc.v:182264.3-182265.25"
- process $proc$libresoc.v:182264$11354
+ attribute \src "libresoc.v:181616.3-181617.25"
+ process $proc$libresoc.v:181616$11250
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:182266.3-182267.39"
- process $proc$libresoc.v:182266$11355
+ attribute \src "libresoc.v:181618.3-181619.39"
+ process $proc$libresoc.v:181618$11251
assign { } { }
assign $0\r23__data_o[3:0] \r23__data_o$next
sync posedge \coresync_clk
update \r23__data_o $0\r23__data_o[3:0]
end
- attribute \src "libresoc.v:182268.3-182269.37"
- process $proc$libresoc.v:182268$11356
+ attribute \src "libresoc.v:181620.3-181621.37"
+ process $proc$libresoc.v:181620$11252
assign { } { }
assign $0\r3__data_o[3:0] \r3__data_o$next
sync posedge \coresync_clk
update \r3__data_o $0\r3__data_o[3:0]
end
- attribute \src "libresoc.v:182270.3-182271.43"
- process $proc$libresoc.v:182270$11357
+ attribute \src "libresoc.v:181622.3-181623.43"
+ process $proc$libresoc.v:181622$11253
assign { } { }
assign $0\src33__data_o[3:0] \src33__data_o$next
sync posedge \coresync_clk
update \src33__data_o $0\src33__data_o[3:0]
end
- attribute \src "libresoc.v:182272.3-182273.43"
- process $proc$libresoc.v:182272$11358
+ attribute \src "libresoc.v:181624.3-181625.43"
+ process $proc$libresoc.v:181624$11254
assign { } { }
assign $0\src23__data_o[3:0] \src23__data_o$next
sync posedge \coresync_clk
update \src23__data_o $0\src23__data_o[3:0]
end
- attribute \src "libresoc.v:182274.3-182275.43"
- process $proc$libresoc.v:182274$11359
+ attribute \src "libresoc.v:181626.3-181627.43"
+ process $proc$libresoc.v:181626$11255
assign { } { }
assign $0\src13__data_o[3:0] \src13__data_o$next
sync posedge \coresync_clk
update \src13__data_o $0\src13__data_o[3:0]
end
- attribute \src "libresoc.v:182276.3-182277.49"
- process $proc$libresoc.v:182276$11360
- assign { } { }
- assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next
- sync posedge \coresync_clk
- update \cr_pred3__data_o $0\cr_pred3__data_o[3:0]
- end
- attribute \src "libresoc.v:182278.3-182317.6"
- process $proc$libresoc.v:182278$11361
+ attribute \src "libresoc.v:181628.3-181667.6"
+ process $proc$libresoc.v:181628$11256
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_pred3__data_o$next[3:0]$11362 $6\cr_pred3__data_o$next[3:0]$11368
- attribute \src "libresoc.v:182279.5-182279.29"
+ assign $0\src13__data_o$next[3:0]$11257 $6\src13__data_o$next[3:0]$11263
+ attribute \src "libresoc.v:181629.5-181629.29"
switch \initial
- attribute \src "libresoc.v:182279.9-182279.17"
+ attribute \src "libresoc.v:181629.9-181629.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred3__ren
+ switch \src13__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred3__data_o$next[3:0]$11363 $5\cr_pred3__data_o$next[3:0]$11367
+ assign $1\src13__data_o$next[3:0]$11258 $5\src13__data_o$next[3:0]$11262
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred3__data_o$next[3:0]$11364 \dest13__data_i
+ assign $2\src13__data_o$next[3:0]$11259 \dest13__data_i
case
- assign $2\cr_pred3__data_o$next[3:0]$11364 4'0000
+ assign $2\src13__data_o$next[3:0]$11259 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred3__data_o$next[3:0]$11365 \dest23__data_i
+ assign $3\src13__data_o$next[3:0]$11260 \dest23__data_i
case
- assign $3\cr_pred3__data_o$next[3:0]$11365 $2\cr_pred3__data_o$next[3:0]$11364
+ assign $3\src13__data_o$next[3:0]$11260 $2\src13__data_o$next[3:0]$11259
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred3__data_o$next[3:0]$11366 \w3__data_i
+ assign $4\src13__data_o$next[3:0]$11261 \w3__data_i
case
- assign $4\cr_pred3__data_o$next[3:0]$11366 $3\cr_pred3__data_o$next[3:0]$11365
+ assign $4\src13__data_o$next[3:0]$11261 $3\src13__data_o$next[3:0]$11260
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred3__data_o$next[3:0]$11367 \reg
+ assign $5\src13__data_o$next[3:0]$11262 \reg
case
- assign $5\cr_pred3__data_o$next[3:0]$11367 $4\cr_pred3__data_o$next[3:0]$11366
+ assign $5\src13__data_o$next[3:0]$11262 $4\src13__data_o$next[3:0]$11261
end
case
- assign $1\cr_pred3__data_o$next[3:0]$11363 4'0000
+ assign $1\src13__data_o$next[3:0]$11258 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred3__data_o$next[3:0]$11368 4'0000
+ assign $6\src13__data_o$next[3:0]$11263 4'0000
case
- assign $6\cr_pred3__data_o$next[3:0]$11368 $1\cr_pred3__data_o$next[3:0]$11363
+ assign $6\src13__data_o$next[3:0]$11263 $1\src13__data_o$next[3:0]$11258
end
sync always
- update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11362
+ update \src13__data_o$next $0\src13__data_o$next[3:0]$11257
end
- attribute \src "libresoc.v:182318.3-182347.6"
- process $proc$libresoc.v:182318$11369
+ attribute \src "libresoc.v:181668.3-181697.6"
+ process $proc$libresoc.v:181668$11264
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:182319.5-182319.29"
+ attribute \src "libresoc.v:181669.5-181669.29"
switch \initial
- attribute \src "libresoc.v:182319.9-182319.17"
+ attribute \src "libresoc.v:181669.9-181669.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred3__ren
+ switch \src13__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:182348.3-182387.6"
- process $proc$libresoc.v:182348$11370
+ attribute \src "libresoc.v:181698.3-181724.6"
+ process $proc$libresoc.v:181698$11265
assign { } { }
assign { } { }
assign { } { }
- assign $0\r23__data_o$next[3:0]$11371 $6\r23__data_o$next[3:0]$11377
- attribute \src "libresoc.v:182349.5-182349.29"
+ assign { } { }
+ assign { } { }
+ assign $0\reg$next[3:0]$11266 $4\reg$next[3:0]$11270
+ attribute \src "libresoc.v:181699.5-181699.29"
switch \initial
- attribute \src "libresoc.v:182349.9-182349.17"
+ attribute \src "libresoc.v:181699.9-181699.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r23__ren
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
+ assign $1\reg$next[3:0]$11267 \dest13__data_i
+ case
+ assign $1\reg$next[3:0]$11267 \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest23__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
+ assign $2\reg$next[3:0]$11268 \dest23__data_i
+ case
+ assign $2\reg$next[3:0]$11268 $1\reg$next[3:0]$11267
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \w3__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
- assign { } { }
- assign $1\r23__data_o$next[3:0]$11372 $5\r23__data_o$next[3:0]$11376
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest13__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r23__data_o$next[3:0]$11373 \dest13__data_i
- case
- assign $2\r23__data_o$next[3:0]$11373 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest23__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r23__data_o$next[3:0]$11374 \dest23__data_i
- case
- assign $3\r23__data_o$next[3:0]$11374 $2\r23__data_o$next[3:0]$11373
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w3__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r23__data_o$next[3:0]$11375 \w3__data_i
- case
- assign $4\r23__data_o$next[3:0]$11375 $3\r23__data_o$next[3:0]$11374
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r23__data_o$next[3:0]$11376 \reg
- case
- assign $5\r23__data_o$next[3:0]$11376 $4\r23__data_o$next[3:0]$11375
- end
+ assign $3\reg$next[3:0]$11269 \w3__data_i
case
- assign $1\r23__data_o$next[3:0]$11372 4'0000
+ assign $3\reg$next[3:0]$11269 $2\reg$next[3:0]$11268
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r23__data_o$next[3:0]$11377 4'0000
+ assign $4\reg$next[3:0]$11270 4'0000
case
- assign $6\r23__data_o$next[3:0]$11377 $1\r23__data_o$next[3:0]$11372
+ assign $4\reg$next[3:0]$11270 $3\reg$next[3:0]$11269
end
sync always
- update \r23__data_o$next $0\r23__data_o$next[3:0]$11371
+ update \reg$next $0\reg$next[3:0]$11266
end
- attribute \src "libresoc.v:182388.3-182417.6"
- process $proc$libresoc.v:182388$11378
+ attribute \src "libresoc.v:181725.3-181764.6"
+ process $proc$libresoc.v:181725$11271
+ assign { } { }
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$11379 $1\wr_detect$16[0:0]$11380
- attribute \src "libresoc.v:182389.5-182389.29"
+ assign $0\src23__data_o$next[3:0]$11272 $6\src23__data_o$next[3:0]$11278
+ attribute \src "libresoc.v:181726.5-181726.29"
switch \initial
- attribute \src "libresoc.v:182389.9-182389.17"
+ attribute \src "libresoc.v:181726.9-181726.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r23__ren
+ switch \src23__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$16[0:0]$11380 $4\wr_detect$16[0:0]$11383
+ assign $1\src23__data_o$next[3:0]$11273 $5\src23__data_o$next[3:0]$11277
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$16[0:0]$11381 1'1
+ assign $2\src23__data_o$next[3:0]$11274 \dest13__data_i
case
- assign $2\wr_detect$16[0:0]$11381 1'0
+ assign $2\src23__data_o$next[3:0]$11274 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$16[0:0]$11382 1'1
+ assign $3\src23__data_o$next[3:0]$11275 \dest23__data_i
case
- assign $3\wr_detect$16[0:0]$11382 $2\wr_detect$16[0:0]$11381
+ assign $3\src23__data_o$next[3:0]$11275 $2\src23__data_o$next[3:0]$11274
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$16[0:0]$11383 1'1
+ assign $4\src23__data_o$next[3:0]$11276 \w3__data_i
case
- assign $4\wr_detect$16[0:0]$11383 $3\wr_detect$16[0:0]$11382
- end
- case
- assign $1\wr_detect$16[0:0]$11380 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11379
- end
- attribute \src "libresoc.v:182418.3-182444.6"
- process $proc$libresoc.v:182418$11384
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$11385 $4\reg$next[3:0]$11389
- attribute \src "libresoc.v:182419.5-182419.29"
- switch \initial
- attribute \src "libresoc.v:182419.9-182419.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest13__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg$next[3:0]$11386 \dest13__data_i
- case
- assign $1\reg$next[3:0]$11386 \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest23__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\reg$next[3:0]$11387 \dest23__data_i
- case
- assign $2\reg$next[3:0]$11387 $1\reg$next[3:0]$11386
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \w3__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\reg$next[3:0]$11388 \w3__data_i
- case
- assign $3\reg$next[3:0]$11388 $2\reg$next[3:0]$11387
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\reg$next[3:0]$11389 4'0000
- case
- assign $4\reg$next[3:0]$11389 $3\reg$next[3:0]$11388
- end
- sync always
- update \reg$next $0\reg$next[3:0]$11385
- end
- attribute \src "libresoc.v:182445.3-182484.6"
- process $proc$libresoc.v:182445$11390
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\src13__data_o$next[3:0]$11391 $6\src13__data_o$next[3:0]$11397
- attribute \src "libresoc.v:182446.5-182446.29"
- switch \initial
- attribute \src "libresoc.v:182446.9-182446.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src13__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\src13__data_o$next[3:0]$11392 $5\src13__data_o$next[3:0]$11396
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest13__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\src13__data_o$next[3:0]$11393 \dest13__data_i
- case
- assign $2\src13__data_o$next[3:0]$11393 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest23__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\src13__data_o$next[3:0]$11394 \dest23__data_i
- case
- assign $3\src13__data_o$next[3:0]$11394 $2\src13__data_o$next[3:0]$11393
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w3__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\src13__data_o$next[3:0]$11395 \w3__data_i
- case
- assign $4\src13__data_o$next[3:0]$11395 $3\src13__data_o$next[3:0]$11394
+ assign $4\src23__data_o$next[3:0]$11276 $3\src23__data_o$next[3:0]$11275
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src13__data_o$next[3:0]$11396 \reg
+ assign $5\src23__data_o$next[3:0]$11277 \reg
case
- assign $5\src13__data_o$next[3:0]$11396 $4\src13__data_o$next[3:0]$11395
+ assign $5\src23__data_o$next[3:0]$11277 $4\src23__data_o$next[3:0]$11276
end
case
- assign $1\src13__data_o$next[3:0]$11392 4'0000
+ assign $1\src23__data_o$next[3:0]$11273 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src13__data_o$next[3:0]$11397 4'0000
+ assign $6\src23__data_o$next[3:0]$11278 4'0000
case
- assign $6\src13__data_o$next[3:0]$11397 $1\src13__data_o$next[3:0]$11392
+ assign $6\src23__data_o$next[3:0]$11278 $1\src23__data_o$next[3:0]$11273
end
sync always
- update \src13__data_o$next $0\src13__data_o$next[3:0]$11391
+ update \src23__data_o$next $0\src23__data_o$next[3:0]$11272
end
- attribute \src "libresoc.v:182485.3-182514.6"
- process $proc$libresoc.v:182485$11398
+ attribute \src "libresoc.v:181765.3-181794.6"
+ process $proc$libresoc.v:181765$11279
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11399 $1\wr_detect$4[0:0]$11400
- attribute \src "libresoc.v:182486.5-182486.29"
+ assign $0\wr_detect$4[0:0]$11280 $1\wr_detect$4[0:0]$11281
+ attribute \src "libresoc.v:181766.5-181766.29"
switch \initial
- attribute \src "libresoc.v:182486.9-182486.17"
+ attribute \src "libresoc.v:181766.9-181766.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src13__ren
+ switch \src23__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11400 $4\wr_detect$4[0:0]$11403
+ assign $1\wr_detect$4[0:0]$11281 $4\wr_detect$4[0:0]$11284
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11401 1'1
+ assign $2\wr_detect$4[0:0]$11282 1'1
case
- assign $2\wr_detect$4[0:0]$11401 1'0
+ assign $2\wr_detect$4[0:0]$11282 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11402 1'1
+ assign $3\wr_detect$4[0:0]$11283 1'1
case
- assign $3\wr_detect$4[0:0]$11402 $2\wr_detect$4[0:0]$11401
+ assign $3\wr_detect$4[0:0]$11283 $2\wr_detect$4[0:0]$11282
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11403 1'1
+ assign $4\wr_detect$4[0:0]$11284 1'1
case
- assign $4\wr_detect$4[0:0]$11403 $3\wr_detect$4[0:0]$11402
+ assign $4\wr_detect$4[0:0]$11284 $3\wr_detect$4[0:0]$11283
end
case
- assign $1\wr_detect$4[0:0]$11400 1'0
+ assign $1\wr_detect$4[0:0]$11281 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11399
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11280
end
- attribute \src "libresoc.v:182515.3-182554.6"
- process $proc$libresoc.v:182515$11404
+ attribute \src "libresoc.v:181795.3-181834.6"
+ process $proc$libresoc.v:181795$11285
assign { } { }
assign { } { }
assign { } { }
- assign $0\src23__data_o$next[3:0]$11405 $6\src23__data_o$next[3:0]$11411
- attribute \src "libresoc.v:182516.5-182516.29"
+ assign $0\src33__data_o$next[3:0]$11286 $6\src33__data_o$next[3:0]$11292
+ attribute \src "libresoc.v:181796.5-181796.29"
switch \initial
- attribute \src "libresoc.v:182516.9-182516.17"
+ attribute \src "libresoc.v:181796.9-181796.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src23__ren
+ switch \src33__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src23__data_o$next[3:0]$11406 $5\src23__data_o$next[3:0]$11410
+ assign $1\src33__data_o$next[3:0]$11287 $5\src33__data_o$next[3:0]$11291
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src23__data_o$next[3:0]$11407 \dest13__data_i
+ assign $2\src33__data_o$next[3:0]$11288 \dest13__data_i
case
- assign $2\src23__data_o$next[3:0]$11407 4'0000
+ assign $2\src33__data_o$next[3:0]$11288 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src23__data_o$next[3:0]$11408 \dest23__data_i
+ assign $3\src33__data_o$next[3:0]$11289 \dest23__data_i
case
- assign $3\src23__data_o$next[3:0]$11408 $2\src23__data_o$next[3:0]$11407
+ assign $3\src33__data_o$next[3:0]$11289 $2\src33__data_o$next[3:0]$11288
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src23__data_o$next[3:0]$11409 \w3__data_i
+ assign $4\src33__data_o$next[3:0]$11290 \w3__data_i
case
- assign $4\src23__data_o$next[3:0]$11409 $3\src23__data_o$next[3:0]$11408
+ assign $4\src33__data_o$next[3:0]$11290 $3\src33__data_o$next[3:0]$11289
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src23__data_o$next[3:0]$11410 \reg
+ assign $5\src33__data_o$next[3:0]$11291 \reg
case
- assign $5\src23__data_o$next[3:0]$11410 $4\src23__data_o$next[3:0]$11409
+ assign $5\src33__data_o$next[3:0]$11291 $4\src33__data_o$next[3:0]$11290
end
case
- assign $1\src23__data_o$next[3:0]$11406 4'0000
+ assign $1\src33__data_o$next[3:0]$11287 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src23__data_o$next[3:0]$11411 4'0000
+ assign $6\src33__data_o$next[3:0]$11292 4'0000
case
- assign $6\src23__data_o$next[3:0]$11411 $1\src23__data_o$next[3:0]$11406
+ assign $6\src33__data_o$next[3:0]$11292 $1\src33__data_o$next[3:0]$11287
end
sync always
- update \src23__data_o$next $0\src23__data_o$next[3:0]$11405
+ update \src33__data_o$next $0\src33__data_o$next[3:0]$11286
end
- attribute \src "libresoc.v:182555.3-182584.6"
- process $proc$libresoc.v:182555$11412
+ attribute \src "libresoc.v:181835.3-181864.6"
+ process $proc$libresoc.v:181835$11293
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11413 $1\wr_detect$7[0:0]$11414
- attribute \src "libresoc.v:182556.5-182556.29"
+ assign $0\wr_detect$7[0:0]$11294 $1\wr_detect$7[0:0]$11295
+ attribute \src "libresoc.v:181836.5-181836.29"
switch \initial
- attribute \src "libresoc.v:182556.9-182556.17"
+ attribute \src "libresoc.v:181836.9-181836.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src23__ren
+ switch \src33__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11414 $4\wr_detect$7[0:0]$11417
+ assign $1\wr_detect$7[0:0]$11295 $4\wr_detect$7[0:0]$11298
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11415 1'1
+ assign $2\wr_detect$7[0:0]$11296 1'1
case
- assign $2\wr_detect$7[0:0]$11415 1'0
+ assign $2\wr_detect$7[0:0]$11296 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11416 1'1
+ assign $3\wr_detect$7[0:0]$11297 1'1
case
- assign $3\wr_detect$7[0:0]$11416 $2\wr_detect$7[0:0]$11415
+ assign $3\wr_detect$7[0:0]$11297 $2\wr_detect$7[0:0]$11296
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11417 1'1
+ assign $4\wr_detect$7[0:0]$11298 1'1
case
- assign $4\wr_detect$7[0:0]$11417 $3\wr_detect$7[0:0]$11416
+ assign $4\wr_detect$7[0:0]$11298 $3\wr_detect$7[0:0]$11297
end
case
- assign $1\wr_detect$7[0:0]$11414 1'0
+ assign $1\wr_detect$7[0:0]$11295 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11413
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11294
end
- attribute \src "libresoc.v:182585.3-182624.6"
- process $proc$libresoc.v:182585$11418
+ attribute \src "libresoc.v:181865.3-181904.6"
+ process $proc$libresoc.v:181865$11299
assign { } { }
assign { } { }
assign { } { }
- assign $0\src33__data_o$next[3:0]$11419 $6\src33__data_o$next[3:0]$11425
- attribute \src "libresoc.v:182586.5-182586.29"
+ assign $0\r3__data_o$next[3:0]$11300 $6\r3__data_o$next[3:0]$11306
+ attribute \src "libresoc.v:181866.5-181866.29"
switch \initial
- attribute \src "libresoc.v:182586.9-182586.17"
+ attribute \src "libresoc.v:181866.9-181866.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src33__ren
+ switch \r3__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src33__data_o$next[3:0]$11420 $5\src33__data_o$next[3:0]$11424
+ assign $1\r3__data_o$next[3:0]$11301 $5\r3__data_o$next[3:0]$11305
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src33__data_o$next[3:0]$11421 \dest13__data_i
+ assign $2\r3__data_o$next[3:0]$11302 \dest13__data_i
case
- assign $2\src33__data_o$next[3:0]$11421 4'0000
+ assign $2\r3__data_o$next[3:0]$11302 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src33__data_o$next[3:0]$11422 \dest23__data_i
+ assign $3\r3__data_o$next[3:0]$11303 \dest23__data_i
case
- assign $3\src33__data_o$next[3:0]$11422 $2\src33__data_o$next[3:0]$11421
+ assign $3\r3__data_o$next[3:0]$11303 $2\r3__data_o$next[3:0]$11302
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src33__data_o$next[3:0]$11423 \w3__data_i
+ assign $4\r3__data_o$next[3:0]$11304 \w3__data_i
case
- assign $4\src33__data_o$next[3:0]$11423 $3\src33__data_o$next[3:0]$11422
+ assign $4\r3__data_o$next[3:0]$11304 $3\r3__data_o$next[3:0]$11303
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src33__data_o$next[3:0]$11424 \reg
+ assign $5\r3__data_o$next[3:0]$11305 \reg
case
- assign $5\src33__data_o$next[3:0]$11424 $4\src33__data_o$next[3:0]$11423
+ assign $5\r3__data_o$next[3:0]$11305 $4\r3__data_o$next[3:0]$11304
end
case
- assign $1\src33__data_o$next[3:0]$11420 4'0000
+ assign $1\r3__data_o$next[3:0]$11301 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src33__data_o$next[3:0]$11425 4'0000
+ assign $6\r3__data_o$next[3:0]$11306 4'0000
case
- assign $6\src33__data_o$next[3:0]$11425 $1\src33__data_o$next[3:0]$11420
+ assign $6\r3__data_o$next[3:0]$11306 $1\r3__data_o$next[3:0]$11301
end
sync always
- update \src33__data_o$next $0\src33__data_o$next[3:0]$11419
+ update \r3__data_o$next $0\r3__data_o$next[3:0]$11300
end
- attribute \src "libresoc.v:182625.3-182654.6"
- process $proc$libresoc.v:182625$11426
+ attribute \src "libresoc.v:181905.3-181934.6"
+ process $proc$libresoc.v:181905$11307
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11427 $1\wr_detect$10[0:0]$11428
- attribute \src "libresoc.v:182626.5-182626.29"
+ assign $0\wr_detect$10[0:0]$11308 $1\wr_detect$10[0:0]$11309
+ attribute \src "libresoc.v:181906.5-181906.29"
switch \initial
- attribute \src "libresoc.v:182626.9-182626.17"
+ attribute \src "libresoc.v:181906.9-181906.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src33__ren
+ switch \r3__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11428 $4\wr_detect$10[0:0]$11431
+ assign $1\wr_detect$10[0:0]$11309 $4\wr_detect$10[0:0]$11312
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11429 1'1
+ assign $2\wr_detect$10[0:0]$11310 1'1
case
- assign $2\wr_detect$10[0:0]$11429 1'0
+ assign $2\wr_detect$10[0:0]$11310 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11430 1'1
+ assign $3\wr_detect$10[0:0]$11311 1'1
case
- assign $3\wr_detect$10[0:0]$11430 $2\wr_detect$10[0:0]$11429
+ assign $3\wr_detect$10[0:0]$11311 $2\wr_detect$10[0:0]$11310
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11431 1'1
+ assign $4\wr_detect$10[0:0]$11312 1'1
case
- assign $4\wr_detect$10[0:0]$11431 $3\wr_detect$10[0:0]$11430
+ assign $4\wr_detect$10[0:0]$11312 $3\wr_detect$10[0:0]$11311
end
case
- assign $1\wr_detect$10[0:0]$11428 1'0
+ assign $1\wr_detect$10[0:0]$11309 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11427
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11308
end
- attribute \src "libresoc.v:182655.3-182694.6"
- process $proc$libresoc.v:182655$11432
+ attribute \src "libresoc.v:181935.3-181974.6"
+ process $proc$libresoc.v:181935$11313
assign { } { }
assign { } { }
assign { } { }
- assign $0\r3__data_o$next[3:0]$11433 $6\r3__data_o$next[3:0]$11439
- attribute \src "libresoc.v:182656.5-182656.29"
+ assign $0\r23__data_o$next[3:0]$11314 $6\r23__data_o$next[3:0]$11320
+ attribute \src "libresoc.v:181936.5-181936.29"
switch \initial
- attribute \src "libresoc.v:182656.9-182656.17"
+ attribute \src "libresoc.v:181936.9-181936.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r3__ren
+ switch \r23__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r3__data_o$next[3:0]$11434 $5\r3__data_o$next[3:0]$11438
+ assign $1\r23__data_o$next[3:0]$11315 $5\r23__data_o$next[3:0]$11319
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r3__data_o$next[3:0]$11435 \dest13__data_i
+ assign $2\r23__data_o$next[3:0]$11316 \dest13__data_i
case
- assign $2\r3__data_o$next[3:0]$11435 4'0000
+ assign $2\r23__data_o$next[3:0]$11316 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r3__data_o$next[3:0]$11436 \dest23__data_i
+ assign $3\r23__data_o$next[3:0]$11317 \dest23__data_i
case
- assign $3\r3__data_o$next[3:0]$11436 $2\r3__data_o$next[3:0]$11435
+ assign $3\r23__data_o$next[3:0]$11317 $2\r23__data_o$next[3:0]$11316
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r3__data_o$next[3:0]$11437 \w3__data_i
+ assign $4\r23__data_o$next[3:0]$11318 \w3__data_i
case
- assign $4\r3__data_o$next[3:0]$11437 $3\r3__data_o$next[3:0]$11436
+ assign $4\r23__data_o$next[3:0]$11318 $3\r23__data_o$next[3:0]$11317
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r3__data_o$next[3:0]$11438 \reg
+ assign $5\r23__data_o$next[3:0]$11319 \reg
case
- assign $5\r3__data_o$next[3:0]$11438 $4\r3__data_o$next[3:0]$11437
+ assign $5\r23__data_o$next[3:0]$11319 $4\r23__data_o$next[3:0]$11318
end
case
- assign $1\r3__data_o$next[3:0]$11434 4'0000
+ assign $1\r23__data_o$next[3:0]$11315 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r3__data_o$next[3:0]$11439 4'0000
+ assign $6\r23__data_o$next[3:0]$11320 4'0000
case
- assign $6\r3__data_o$next[3:0]$11439 $1\r3__data_o$next[3:0]$11434
+ assign $6\r23__data_o$next[3:0]$11320 $1\r23__data_o$next[3:0]$11315
end
sync always
- update \r3__data_o$next $0\r3__data_o$next[3:0]$11433
+ update \r23__data_o$next $0\r23__data_o$next[3:0]$11314
end
- attribute \src "libresoc.v:182695.3-182724.6"
- process $proc$libresoc.v:182695$11440
+ attribute \src "libresoc.v:181975.3-182004.6"
+ process $proc$libresoc.v:181975$11321
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11441 $1\wr_detect$13[0:0]$11442
- attribute \src "libresoc.v:182696.5-182696.29"
+ assign $0\wr_detect$13[0:0]$11322 $1\wr_detect$13[0:0]$11323
+ attribute \src "libresoc.v:181976.5-181976.29"
switch \initial
- attribute \src "libresoc.v:182696.9-182696.17"
+ attribute \src "libresoc.v:181976.9-181976.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r3__ren
+ switch \r23__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11442 $4\wr_detect$13[0:0]$11445
+ assign $1\wr_detect$13[0:0]$11323 $4\wr_detect$13[0:0]$11326
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11443 1'1
+ assign $2\wr_detect$13[0:0]$11324 1'1
case
- assign $2\wr_detect$13[0:0]$11443 1'0
+ assign $2\wr_detect$13[0:0]$11324 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11444 1'1
+ assign $3\wr_detect$13[0:0]$11325 1'1
case
- assign $3\wr_detect$13[0:0]$11444 $2\wr_detect$13[0:0]$11443
+ assign $3\wr_detect$13[0:0]$11325 $2\wr_detect$13[0:0]$11324
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11445 1'1
+ assign $4\wr_detect$13[0:0]$11326 1'1
case
- assign $4\wr_detect$13[0:0]$11445 $3\wr_detect$13[0:0]$11444
+ assign $4\wr_detect$13[0:0]$11326 $3\wr_detect$13[0:0]$11325
end
case
- assign $1\wr_detect$13[0:0]$11442 1'0
+ assign $1\wr_detect$13[0:0]$11323 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11441
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11322
end
- connect \$9 $not$libresoc.v:182258$11348_Y
- connect \$12 $not$libresoc.v:182259$11349_Y
- connect \$15 $not$libresoc.v:182260$11350_Y
- connect \$1 $not$libresoc.v:182261$11351_Y
- connect \$3 $not$libresoc.v:182262$11352_Y
- connect \$6 $not$libresoc.v:182263$11353_Y
+ connect \$9 $not$libresoc.v:181611$11245_Y
+ connect \$12 $not$libresoc.v:181612$11246_Y
+ connect \$1 $not$libresoc.v:181613$11247_Y
+ connect \$3 $not$libresoc.v:181614$11248_Y
+ connect \$6 $not$libresoc.v:181615$11249_Y
end
-attribute \src "libresoc.v:182729.1-183284.10"
+attribute \src "libresoc.v:182009.1-182480.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4"
attribute \generator "nMigen"
module \reg_4
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $0\cr_pred4__data_o$next[3:0]$11468
- attribute \src "libresoc.v:182835.3-182836.49"
- wire width 4 $0\cr_pred4__data_o[3:0]
- attribute \src "libresoc.v:182730.7-182730.20"
+ attribute \src "libresoc.v:182010.7-182010.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $0\r24__data_o$next[3:0]$11477
- attribute \src "libresoc.v:182825.3-182826.39"
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $0\r24__data_o$next[3:0]$11403
+ attribute \src "libresoc.v:182093.3-182094.39"
wire width 4 $0\r24__data_o[3:0]
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $0\r4__data_o$next[3:0]$11539
- attribute \src "libresoc.v:182827.3-182828.37"
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $0\r4__data_o$next[3:0]$11389
+ attribute \src "libresoc.v:182095.3-182096.37"
wire width 4 $0\r4__data_o[3:0]
- attribute \src "libresoc.v:182977.3-183003.6"
- wire width 4 $0\reg$next[3:0]$11491
- attribute \src "libresoc.v:182823.3-182824.25"
+ attribute \src "libresoc.v:182173.3-182199.6"
+ wire width 4 $0\reg$next[3:0]$11355
+ attribute \src "libresoc.v:182091.3-182092.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $0\src14__data_o$next[3:0]$11497
- attribute \src "libresoc.v:182833.3-182834.43"
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $0\src14__data_o$next[3:0]$11346
+ attribute \src "libresoc.v:182101.3-182102.43"
wire width 4 $0\src14__data_o[3:0]
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $0\src24__data_o$next[3:0]$11511
- attribute \src "libresoc.v:182831.3-182832.43"
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $0\src24__data_o$next[3:0]$11361
+ attribute \src "libresoc.v:182099.3-182100.43"
wire width 4 $0\src24__data_o[3:0]
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $0\src34__data_o$next[3:0]$11525
- attribute \src "libresoc.v:182829.3-182830.43"
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $0\src34__data_o$next[3:0]$11375
+ attribute \src "libresoc.v:182097.3-182098.43"
wire width 4 $0\src34__data_o[3:0]
- attribute \src "libresoc.v:183184.3-183213.6"
- wire $0\wr_detect$10[0:0]$11533
- attribute \src "libresoc.v:183254.3-183283.6"
- wire $0\wr_detect$13[0:0]$11547
- attribute \src "libresoc.v:182947.3-182976.6"
- wire $0\wr_detect$16[0:0]$11485
- attribute \src "libresoc.v:183044.3-183073.6"
- wire $0\wr_detect$4[0:0]$11505
- attribute \src "libresoc.v:183114.3-183143.6"
- wire $0\wr_detect$7[0:0]$11519
- attribute \src "libresoc.v:182877.3-182906.6"
+ attribute \src "libresoc.v:182380.3-182409.6"
+ wire $0\wr_detect$10[0:0]$11397
+ attribute \src "libresoc.v:182450.3-182479.6"
+ wire $0\wr_detect$13[0:0]$11411
+ attribute \src "libresoc.v:182240.3-182269.6"
+ wire $0\wr_detect$4[0:0]$11369
+ attribute \src "libresoc.v:182310.3-182339.6"
+ wire $0\wr_detect$7[0:0]$11383
+ attribute \src "libresoc.v:182143.3-182172.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $1\cr_pred4__data_o$next[3:0]$11469
- attribute \src "libresoc.v:182749.13-182749.36"
- wire width 4 $1\cr_pred4__data_o[3:0]
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $1\r24__data_o$next[3:0]$11478
- attribute \src "libresoc.v:182764.13-182764.31"
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $1\r24__data_o$next[3:0]$11404
+ attribute \src "libresoc.v:182035.13-182035.31"
wire width 4 $1\r24__data_o[3:0]
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $1\r4__data_o$next[3:0]$11540
- attribute \src "libresoc.v:182771.13-182771.30"
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $1\r4__data_o$next[3:0]$11390
+ attribute \src "libresoc.v:182042.13-182042.30"
wire width 4 $1\r4__data_o[3:0]
- attribute \src "libresoc.v:182977.3-183003.6"
- wire width 4 $1\reg$next[3:0]$11492
- attribute \src "libresoc.v:182777.13-182777.25"
+ attribute \src "libresoc.v:182173.3-182199.6"
+ wire width 4 $1\reg$next[3:0]$11356
+ attribute \src "libresoc.v:182048.13-182048.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $1\src14__data_o$next[3:0]$11498
- attribute \src "libresoc.v:182782.13-182782.33"
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $1\src14__data_o$next[3:0]$11347
+ attribute \src "libresoc.v:182053.13-182053.33"
wire width 4 $1\src14__data_o[3:0]
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $1\src24__data_o$next[3:0]$11512
- attribute \src "libresoc.v:182789.13-182789.33"
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $1\src24__data_o$next[3:0]$11362
+ attribute \src "libresoc.v:182060.13-182060.33"
wire width 4 $1\src24__data_o[3:0]
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $1\src34__data_o$next[3:0]$11526
- attribute \src "libresoc.v:182796.13-182796.33"
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $1\src34__data_o$next[3:0]$11376
+ attribute \src "libresoc.v:182067.13-182067.33"
wire width 4 $1\src34__data_o[3:0]
- attribute \src "libresoc.v:183184.3-183213.6"
- wire $1\wr_detect$10[0:0]$11534
- attribute \src "libresoc.v:183254.3-183283.6"
- wire $1\wr_detect$13[0:0]$11548
- attribute \src "libresoc.v:182947.3-182976.6"
- wire $1\wr_detect$16[0:0]$11486
- attribute \src "libresoc.v:183044.3-183073.6"
- wire $1\wr_detect$4[0:0]$11506
- attribute \src "libresoc.v:183114.3-183143.6"
- wire $1\wr_detect$7[0:0]$11520
- attribute \src "libresoc.v:182877.3-182906.6"
+ attribute \src "libresoc.v:182380.3-182409.6"
+ wire $1\wr_detect$10[0:0]$11398
+ attribute \src "libresoc.v:182450.3-182479.6"
+ wire $1\wr_detect$13[0:0]$11412
+ attribute \src "libresoc.v:182240.3-182269.6"
+ wire $1\wr_detect$4[0:0]$11370
+ attribute \src "libresoc.v:182310.3-182339.6"
+ wire $1\wr_detect$7[0:0]$11384
+ attribute \src "libresoc.v:182143.3-182172.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $2\cr_pred4__data_o$next[3:0]$11470
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $2\r24__data_o$next[3:0]$11479
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $2\r4__data_o$next[3:0]$11541
- attribute \src "libresoc.v:182977.3-183003.6"
- wire width 4 $2\reg$next[3:0]$11493
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $2\src14__data_o$next[3:0]$11499
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $2\src24__data_o$next[3:0]$11513
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $2\src34__data_o$next[3:0]$11527
- attribute \src "libresoc.v:183184.3-183213.6"
- wire $2\wr_detect$10[0:0]$11535
- attribute \src "libresoc.v:183254.3-183283.6"
- wire $2\wr_detect$13[0:0]$11549
- attribute \src "libresoc.v:182947.3-182976.6"
- wire $2\wr_detect$16[0:0]$11487
- attribute \src "libresoc.v:183044.3-183073.6"
- wire $2\wr_detect$4[0:0]$11507
- attribute \src "libresoc.v:183114.3-183143.6"
- wire $2\wr_detect$7[0:0]$11521
- attribute \src "libresoc.v:182877.3-182906.6"
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $2\r24__data_o$next[3:0]$11405
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $2\r4__data_o$next[3:0]$11391
+ attribute \src "libresoc.v:182173.3-182199.6"
+ wire width 4 $2\reg$next[3:0]$11357
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $2\src14__data_o$next[3:0]$11348
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $2\src24__data_o$next[3:0]$11363
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $2\src34__data_o$next[3:0]$11377
+ attribute \src "libresoc.v:182380.3-182409.6"
+ wire $2\wr_detect$10[0:0]$11399
+ attribute \src "libresoc.v:182450.3-182479.6"
+ wire $2\wr_detect$13[0:0]$11413
+ attribute \src "libresoc.v:182240.3-182269.6"
+ wire $2\wr_detect$4[0:0]$11371
+ attribute \src "libresoc.v:182310.3-182339.6"
+ wire $2\wr_detect$7[0:0]$11385
+ attribute \src "libresoc.v:182143.3-182172.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $3\cr_pred4__data_o$next[3:0]$11471
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $3\r24__data_o$next[3:0]$11480
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $3\r4__data_o$next[3:0]$11542
- attribute \src "libresoc.v:182977.3-183003.6"
- wire width 4 $3\reg$next[3:0]$11494
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $3\src14__data_o$next[3:0]$11500
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $3\src24__data_o$next[3:0]$11514
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $3\src34__data_o$next[3:0]$11528
- attribute \src "libresoc.v:183184.3-183213.6"
- wire $3\wr_detect$10[0:0]$11536
- attribute \src "libresoc.v:183254.3-183283.6"
- wire $3\wr_detect$13[0:0]$11550
- attribute \src "libresoc.v:182947.3-182976.6"
- wire $3\wr_detect$16[0:0]$11488
- attribute \src "libresoc.v:183044.3-183073.6"
- wire $3\wr_detect$4[0:0]$11508
- attribute \src "libresoc.v:183114.3-183143.6"
- wire $3\wr_detect$7[0:0]$11522
- attribute \src "libresoc.v:182877.3-182906.6"
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $3\r24__data_o$next[3:0]$11406
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $3\r4__data_o$next[3:0]$11392
+ attribute \src "libresoc.v:182173.3-182199.6"
+ wire width 4 $3\reg$next[3:0]$11358
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $3\src14__data_o$next[3:0]$11349
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $3\src24__data_o$next[3:0]$11364
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $3\src34__data_o$next[3:0]$11378
+ attribute \src "libresoc.v:182380.3-182409.6"
+ wire $3\wr_detect$10[0:0]$11400
+ attribute \src "libresoc.v:182450.3-182479.6"
+ wire $3\wr_detect$13[0:0]$11414
+ attribute \src "libresoc.v:182240.3-182269.6"
+ wire $3\wr_detect$4[0:0]$11372
+ attribute \src "libresoc.v:182310.3-182339.6"
+ wire $3\wr_detect$7[0:0]$11386
+ attribute \src "libresoc.v:182143.3-182172.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $4\cr_pred4__data_o$next[3:0]$11472
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $4\r24__data_o$next[3:0]$11481
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $4\r4__data_o$next[3:0]$11543
- attribute \src "libresoc.v:182977.3-183003.6"
- wire width 4 $4\reg$next[3:0]$11495
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $4\src14__data_o$next[3:0]$11501
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $4\src24__data_o$next[3:0]$11515
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $4\src34__data_o$next[3:0]$11529
- attribute \src "libresoc.v:183184.3-183213.6"
- wire $4\wr_detect$10[0:0]$11537
- attribute \src "libresoc.v:183254.3-183283.6"
- wire $4\wr_detect$13[0:0]$11551
- attribute \src "libresoc.v:182947.3-182976.6"
- wire $4\wr_detect$16[0:0]$11489
- attribute \src "libresoc.v:183044.3-183073.6"
- wire $4\wr_detect$4[0:0]$11509
- attribute \src "libresoc.v:183114.3-183143.6"
- wire $4\wr_detect$7[0:0]$11523
- attribute \src "libresoc.v:182877.3-182906.6"
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $4\r24__data_o$next[3:0]$11407
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $4\r4__data_o$next[3:0]$11393
+ attribute \src "libresoc.v:182173.3-182199.6"
+ wire width 4 $4\reg$next[3:0]$11359
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $4\src14__data_o$next[3:0]$11350
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $4\src24__data_o$next[3:0]$11365
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $4\src34__data_o$next[3:0]$11379
+ attribute \src "libresoc.v:182380.3-182409.6"
+ wire $4\wr_detect$10[0:0]$11401
+ attribute \src "libresoc.v:182450.3-182479.6"
+ wire $4\wr_detect$13[0:0]$11415
+ attribute \src "libresoc.v:182240.3-182269.6"
+ wire $4\wr_detect$4[0:0]$11373
+ attribute \src "libresoc.v:182310.3-182339.6"
+ wire $4\wr_detect$7[0:0]$11387
+ attribute \src "libresoc.v:182143.3-182172.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $5\cr_pred4__data_o$next[3:0]$11473
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $5\r24__data_o$next[3:0]$11482
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $5\r4__data_o$next[3:0]$11544
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $5\src14__data_o$next[3:0]$11502
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $5\src24__data_o$next[3:0]$11516
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $5\src34__data_o$next[3:0]$11530
- attribute \src "libresoc.v:182837.3-182876.6"
- wire width 4 $6\cr_pred4__data_o$next[3:0]$11474
- attribute \src "libresoc.v:182907.3-182946.6"
- wire width 4 $6\r24__data_o$next[3:0]$11483
- attribute \src "libresoc.v:183214.3-183253.6"
- wire width 4 $6\r4__data_o$next[3:0]$11545
- attribute \src "libresoc.v:183004.3-183043.6"
- wire width 4 $6\src14__data_o$next[3:0]$11503
- attribute \src "libresoc.v:183074.3-183113.6"
- wire width 4 $6\src24__data_o$next[3:0]$11517
- attribute \src "libresoc.v:183144.3-183183.6"
- wire width 4 $6\src34__data_o$next[3:0]$11531
- attribute \src "libresoc.v:182817.17-182817.104"
- wire $not$libresoc.v:182817$11454_Y
- attribute \src "libresoc.v:182818.18-182818.105"
- wire $not$libresoc.v:182818$11455_Y
- attribute \src "libresoc.v:182819.18-182819.105"
- wire $not$libresoc.v:182819$11456_Y
- attribute \src "libresoc.v:182820.17-182820.100"
- wire $not$libresoc.v:182820$11457_Y
- attribute \src "libresoc.v:182821.17-182821.103"
- wire $not$libresoc.v:182821$11458_Y
- attribute \src "libresoc.v:182822.17-182822.103"
- wire $not$libresoc.v:182822$11459_Y
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $5\r24__data_o$next[3:0]$11408
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $5\r4__data_o$next[3:0]$11394
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $5\src14__data_o$next[3:0]$11351
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $5\src24__data_o$next[3:0]$11366
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $5\src34__data_o$next[3:0]$11380
+ attribute \src "libresoc.v:182410.3-182449.6"
+ wire width 4 $6\r24__data_o$next[3:0]$11409
+ attribute \src "libresoc.v:182340.3-182379.6"
+ wire width 4 $6\r4__data_o$next[3:0]$11395
+ attribute \src "libresoc.v:182103.3-182142.6"
+ wire width 4 $6\src14__data_o$next[3:0]$11352
+ attribute \src "libresoc.v:182200.3-182239.6"
+ wire width 4 $6\src24__data_o$next[3:0]$11367
+ attribute \src "libresoc.v:182270.3-182309.6"
+ wire width 4 $6\src34__data_o$next[3:0]$11381
+ attribute \src "libresoc.v:182086.17-182086.104"
+ wire $not$libresoc.v:182086$11334_Y
+ attribute \src "libresoc.v:182087.18-182087.105"
+ wire $not$libresoc.v:182087$11335_Y
+ attribute \src "libresoc.v:182088.17-182088.100"
+ wire $not$libresoc.v:182088$11336_Y
+ attribute \src "libresoc.v:182089.17-182089.103"
+ wire $not$libresoc.v:182089$11337_Y
+ attribute \src "libresoc.v:182090.17-182090.103"
+ wire $not$libresoc.v:182090$11338_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred4__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred4__data_o$next
+ wire width 4 input 9 \dest14__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred4__ren
+ wire input 8 \dest14__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest14__data_i
+ wire width 4 input 11 \dest24__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest14__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest24__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest24__wen
- attribute \src "libresoc.v:182730.7-182730.15"
+ wire input 10 \dest24__wen
+ attribute \src "libresoc.v:182010.7-182010.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r24__data_o
+ wire width 4 output 14 \r24__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r24__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r24__ren
+ wire input 15 \r24__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r4__data_o
+ wire width 4 output 12 \r4__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r4__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r4__ren
+ wire input 13 \r4__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src14__data_o
+ wire width 4 output 3 \src14__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src14__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src14__ren
+ wire input 2 \src14__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src24__data_o
+ wire width 4 output 5 \src24__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src24__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src24__ren
+ wire input 4 \src24__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src34__data_o
+ wire width 4 output 7 \src34__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src34__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src34__ren
+ wire input 6 \src34__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w4__data_i
+ wire width 4 input 16 \w4__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w4__wen
+ wire input 17 \w4__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182817$11454
+ cell $not $not$libresoc.v:182086$11334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:182817$11454_Y
+ connect \Y $not$libresoc.v:182086$11334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182818$11455
+ cell $not $not$libresoc.v:182087$11335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:182818$11455_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182819$11456
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:182819$11456_Y
+ connect \Y $not$libresoc.v:182087$11335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182820$11457
+ cell $not $not$libresoc.v:182088$11336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:182820$11457_Y
+ connect \Y $not$libresoc.v:182088$11336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182821$11458
+ cell $not $not$libresoc.v:182089$11337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:182821$11458_Y
+ connect \Y $not$libresoc.v:182089$11337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:182822$11459
+ cell $not $not$libresoc.v:182090$11338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:182822$11459_Y
+ connect \Y $not$libresoc.v:182090$11338_Y
end
- attribute \src "libresoc.v:182730.7-182730.20"
- process $proc$libresoc.v:182730$11552
+ attribute \src "libresoc.v:182010.7-182010.20"
+ process $proc$libresoc.v:182010$11416
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182749.13-182749.36"
- process $proc$libresoc.v:182749$11553
- assign { } { }
- assign $1\cr_pred4__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred4__data_o $1\cr_pred4__data_o[3:0]
- end
- attribute \src "libresoc.v:182764.13-182764.31"
- process $proc$libresoc.v:182764$11554
+ attribute \src "libresoc.v:182035.13-182035.31"
+ process $proc$libresoc.v:182035$11417
assign { } { }
assign $1\r24__data_o[3:0] 4'0000
sync always
sync init
update \r24__data_o $1\r24__data_o[3:0]
end
- attribute \src "libresoc.v:182771.13-182771.30"
- process $proc$libresoc.v:182771$11555
+ attribute \src "libresoc.v:182042.13-182042.30"
+ process $proc$libresoc.v:182042$11418
assign { } { }
assign $1\r4__data_o[3:0] 4'0000
sync always
sync init
update \r4__data_o $1\r4__data_o[3:0]
end
- attribute \src "libresoc.v:182777.13-182777.25"
- process $proc$libresoc.v:182777$11556
+ attribute \src "libresoc.v:182048.13-182048.25"
+ process $proc$libresoc.v:182048$11419
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:182782.13-182782.33"
- process $proc$libresoc.v:182782$11557
+ attribute \src "libresoc.v:182053.13-182053.33"
+ process $proc$libresoc.v:182053$11420
assign { } { }
assign $1\src14__data_o[3:0] 4'0000
sync always
sync init
update \src14__data_o $1\src14__data_o[3:0]
end
- attribute \src "libresoc.v:182789.13-182789.33"
- process $proc$libresoc.v:182789$11558
+ attribute \src "libresoc.v:182060.13-182060.33"
+ process $proc$libresoc.v:182060$11421
assign { } { }
assign $1\src24__data_o[3:0] 4'0000
sync always
sync init
update \src24__data_o $1\src24__data_o[3:0]
end
- attribute \src "libresoc.v:182796.13-182796.33"
- process $proc$libresoc.v:182796$11559
+ attribute \src "libresoc.v:182067.13-182067.33"
+ process $proc$libresoc.v:182067$11422
assign { } { }
assign $1\src34__data_o[3:0] 4'0000
sync always
sync init
update \src34__data_o $1\src34__data_o[3:0]
end
- attribute \src "libresoc.v:182823.3-182824.25"
- process $proc$libresoc.v:182823$11460
+ attribute \src "libresoc.v:182091.3-182092.25"
+ process $proc$libresoc.v:182091$11339
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:182825.3-182826.39"
- process $proc$libresoc.v:182825$11461
+ attribute \src "libresoc.v:182093.3-182094.39"
+ process $proc$libresoc.v:182093$11340
assign { } { }
assign $0\r24__data_o[3:0] \r24__data_o$next
sync posedge \coresync_clk
update \r24__data_o $0\r24__data_o[3:0]
end
- attribute \src "libresoc.v:182827.3-182828.37"
- process $proc$libresoc.v:182827$11462
+ attribute \src "libresoc.v:182095.3-182096.37"
+ process $proc$libresoc.v:182095$11341
assign { } { }
assign $0\r4__data_o[3:0] \r4__data_o$next
sync posedge \coresync_clk
update \r4__data_o $0\r4__data_o[3:0]
end
- attribute \src "libresoc.v:182829.3-182830.43"
- process $proc$libresoc.v:182829$11463
+ attribute \src "libresoc.v:182097.3-182098.43"
+ process $proc$libresoc.v:182097$11342
assign { } { }
assign $0\src34__data_o[3:0] \src34__data_o$next
sync posedge \coresync_clk
update \src34__data_o $0\src34__data_o[3:0]
end
- attribute \src "libresoc.v:182831.3-182832.43"
- process $proc$libresoc.v:182831$11464
+ attribute \src "libresoc.v:182099.3-182100.43"
+ process $proc$libresoc.v:182099$11343
assign { } { }
assign $0\src24__data_o[3:0] \src24__data_o$next
sync posedge \coresync_clk
update \src24__data_o $0\src24__data_o[3:0]
end
- attribute \src "libresoc.v:182833.3-182834.43"
- process $proc$libresoc.v:182833$11465
+ attribute \src "libresoc.v:182101.3-182102.43"
+ process $proc$libresoc.v:182101$11344
assign { } { }
assign $0\src14__data_o[3:0] \src14__data_o$next
sync posedge \coresync_clk
update \src14__data_o $0\src14__data_o[3:0]
end
- attribute \src "libresoc.v:182835.3-182836.49"
- process $proc$libresoc.v:182835$11466
- assign { } { }
- assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next
- sync posedge \coresync_clk
- update \cr_pred4__data_o $0\cr_pred4__data_o[3:0]
- end
- attribute \src "libresoc.v:182837.3-182876.6"
- process $proc$libresoc.v:182837$11467
+ attribute \src "libresoc.v:182103.3-182142.6"
+ process $proc$libresoc.v:182103$11345
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_pred4__data_o$next[3:0]$11468 $6\cr_pred4__data_o$next[3:0]$11474
- attribute \src "libresoc.v:182838.5-182838.29"
+ assign $0\src14__data_o$next[3:0]$11346 $6\src14__data_o$next[3:0]$11352
+ attribute \src "libresoc.v:182104.5-182104.29"
switch \initial
- attribute \src "libresoc.v:182838.9-182838.17"
+ attribute \src "libresoc.v:182104.9-182104.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred4__ren
+ switch \src14__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred4__data_o$next[3:0]$11469 $5\cr_pred4__data_o$next[3:0]$11473
+ assign $1\src14__data_o$next[3:0]$11347 $5\src14__data_o$next[3:0]$11351
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred4__data_o$next[3:0]$11470 \dest14__data_i
+ assign $2\src14__data_o$next[3:0]$11348 \dest14__data_i
case
- assign $2\cr_pred4__data_o$next[3:0]$11470 4'0000
+ assign $2\src14__data_o$next[3:0]$11348 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred4__data_o$next[3:0]$11471 \dest24__data_i
+ assign $3\src14__data_o$next[3:0]$11349 \dest24__data_i
case
- assign $3\cr_pred4__data_o$next[3:0]$11471 $2\cr_pred4__data_o$next[3:0]$11470
+ assign $3\src14__data_o$next[3:0]$11349 $2\src14__data_o$next[3:0]$11348
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred4__data_o$next[3:0]$11472 \w4__data_i
+ assign $4\src14__data_o$next[3:0]$11350 \w4__data_i
case
- assign $4\cr_pred4__data_o$next[3:0]$11472 $3\cr_pred4__data_o$next[3:0]$11471
+ assign $4\src14__data_o$next[3:0]$11350 $3\src14__data_o$next[3:0]$11349
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred4__data_o$next[3:0]$11473 \reg
+ assign $5\src14__data_o$next[3:0]$11351 \reg
case
- assign $5\cr_pred4__data_o$next[3:0]$11473 $4\cr_pred4__data_o$next[3:0]$11472
+ assign $5\src14__data_o$next[3:0]$11351 $4\src14__data_o$next[3:0]$11350
end
case
- assign $1\cr_pred4__data_o$next[3:0]$11469 4'0000
+ assign $1\src14__data_o$next[3:0]$11347 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred4__data_o$next[3:0]$11474 4'0000
+ assign $6\src14__data_o$next[3:0]$11352 4'0000
case
- assign $6\cr_pred4__data_o$next[3:0]$11474 $1\cr_pred4__data_o$next[3:0]$11469
+ assign $6\src14__data_o$next[3:0]$11352 $1\src14__data_o$next[3:0]$11347
end
sync always
- update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11468
+ update \src14__data_o$next $0\src14__data_o$next[3:0]$11346
end
- attribute \src "libresoc.v:182877.3-182906.6"
- process $proc$libresoc.v:182877$11475
+ attribute \src "libresoc.v:182143.3-182172.6"
+ process $proc$libresoc.v:182143$11353
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:182878.5-182878.29"
+ attribute \src "libresoc.v:182144.5-182144.29"
switch \initial
- attribute \src "libresoc.v:182878.9-182878.17"
+ attribute \src "libresoc.v:182144.9-182144.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred4__ren
+ switch \src14__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:182907.3-182946.6"
- process $proc$libresoc.v:182907$11476
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\r24__data_o$next[3:0]$11477 $6\r24__data_o$next[3:0]$11483
- attribute \src "libresoc.v:182908.5-182908.29"
- switch \initial
- attribute \src "libresoc.v:182908.9-182908.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r24__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\r24__data_o$next[3:0]$11478 $5\r24__data_o$next[3:0]$11482
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest14__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r24__data_o$next[3:0]$11479 \dest14__data_i
- case
- assign $2\r24__data_o$next[3:0]$11479 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest24__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r24__data_o$next[3:0]$11480 \dest24__data_i
- case
- assign $3\r24__data_o$next[3:0]$11480 $2\r24__data_o$next[3:0]$11479
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w4__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r24__data_o$next[3:0]$11481 \w4__data_i
- case
- assign $4\r24__data_o$next[3:0]$11481 $3\r24__data_o$next[3:0]$11480
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r24__data_o$next[3:0]$11482 \reg
- case
- assign $5\r24__data_o$next[3:0]$11482 $4\r24__data_o$next[3:0]$11481
- end
- case
- assign $1\r24__data_o$next[3:0]$11478 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\r24__data_o$next[3:0]$11483 4'0000
- case
- assign $6\r24__data_o$next[3:0]$11483 $1\r24__data_o$next[3:0]$11478
- end
- sync always
- update \r24__data_o$next $0\r24__data_o$next[3:0]$11477
- end
- attribute \src "libresoc.v:182947.3-182976.6"
- process $proc$libresoc.v:182947$11484
- assign { } { }
- assign { } { }
- assign $0\wr_detect$16[0:0]$11485 $1\wr_detect$16[0:0]$11486
- attribute \src "libresoc.v:182948.5-182948.29"
- switch \initial
- attribute \src "libresoc.v:182948.9-182948.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r24__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$16[0:0]$11486 $4\wr_detect$16[0:0]$11489
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest14__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$16[0:0]$11487 1'1
- case
- assign $2\wr_detect$16[0:0]$11487 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest24__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$16[0:0]$11488 1'1
- case
- assign $3\wr_detect$16[0:0]$11488 $2\wr_detect$16[0:0]$11487
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w4__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$16[0:0]$11489 1'1
- case
- assign $4\wr_detect$16[0:0]$11489 $3\wr_detect$16[0:0]$11488
- end
- case
- assign $1\wr_detect$16[0:0]$11486 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11485
- end
- attribute \src "libresoc.v:182977.3-183003.6"
- process $proc$libresoc.v:182977$11490
+ attribute \src "libresoc.v:182173.3-182199.6"
+ process $proc$libresoc.v:182173$11354
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11491 $4\reg$next[3:0]$11495
- attribute \src "libresoc.v:182978.5-182978.29"
+ assign $0\reg$next[3:0]$11355 $4\reg$next[3:0]$11359
+ attribute \src "libresoc.v:182174.5-182174.29"
switch \initial
- attribute \src "libresoc.v:182978.9-182978.17"
+ attribute \src "libresoc.v:182174.9-182174.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11492 \dest14__data_i
+ assign $1\reg$next[3:0]$11356 \dest14__data_i
case
- assign $1\reg$next[3:0]$11492 \reg
+ assign $1\reg$next[3:0]$11356 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11493 \dest24__data_i
+ assign $2\reg$next[3:0]$11357 \dest24__data_i
case
- assign $2\reg$next[3:0]$11493 $1\reg$next[3:0]$11492
+ assign $2\reg$next[3:0]$11357 $1\reg$next[3:0]$11356
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11494 \w4__data_i
+ assign $3\reg$next[3:0]$11358 \w4__data_i
case
- assign $3\reg$next[3:0]$11494 $2\reg$next[3:0]$11493
+ assign $3\reg$next[3:0]$11358 $2\reg$next[3:0]$11357
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11495 4'0000
+ assign $4\reg$next[3:0]$11359 4'0000
case
- assign $4\reg$next[3:0]$11495 $3\reg$next[3:0]$11494
+ assign $4\reg$next[3:0]$11359 $3\reg$next[3:0]$11358
end
sync always
- update \reg$next $0\reg$next[3:0]$11491
+ update \reg$next $0\reg$next[3:0]$11355
end
- attribute \src "libresoc.v:183004.3-183043.6"
- process $proc$libresoc.v:183004$11496
+ attribute \src "libresoc.v:182200.3-182239.6"
+ process $proc$libresoc.v:182200$11360
assign { } { }
assign { } { }
assign { } { }
- assign $0\src14__data_o$next[3:0]$11497 $6\src14__data_o$next[3:0]$11503
- attribute \src "libresoc.v:183005.5-183005.29"
+ assign $0\src24__data_o$next[3:0]$11361 $6\src24__data_o$next[3:0]$11367
+ attribute \src "libresoc.v:182201.5-182201.29"
switch \initial
- attribute \src "libresoc.v:183005.9-183005.17"
+ attribute \src "libresoc.v:182201.9-182201.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src14__ren
+ switch \src24__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src14__data_o$next[3:0]$11498 $5\src14__data_o$next[3:0]$11502
+ assign $1\src24__data_o$next[3:0]$11362 $5\src24__data_o$next[3:0]$11366
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src14__data_o$next[3:0]$11499 \dest14__data_i
+ assign $2\src24__data_o$next[3:0]$11363 \dest14__data_i
case
- assign $2\src14__data_o$next[3:0]$11499 4'0000
+ assign $2\src24__data_o$next[3:0]$11363 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src14__data_o$next[3:0]$11500 \dest24__data_i
+ assign $3\src24__data_o$next[3:0]$11364 \dest24__data_i
case
- assign $3\src14__data_o$next[3:0]$11500 $2\src14__data_o$next[3:0]$11499
+ assign $3\src24__data_o$next[3:0]$11364 $2\src24__data_o$next[3:0]$11363
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src14__data_o$next[3:0]$11501 \w4__data_i
+ assign $4\src24__data_o$next[3:0]$11365 \w4__data_i
case
- assign $4\src14__data_o$next[3:0]$11501 $3\src14__data_o$next[3:0]$11500
+ assign $4\src24__data_o$next[3:0]$11365 $3\src24__data_o$next[3:0]$11364
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src14__data_o$next[3:0]$11502 \reg
+ assign $5\src24__data_o$next[3:0]$11366 \reg
case
- assign $5\src14__data_o$next[3:0]$11502 $4\src14__data_o$next[3:0]$11501
+ assign $5\src24__data_o$next[3:0]$11366 $4\src24__data_o$next[3:0]$11365
end
case
- assign $1\src14__data_o$next[3:0]$11498 4'0000
+ assign $1\src24__data_o$next[3:0]$11362 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src14__data_o$next[3:0]$11503 4'0000
+ assign $6\src24__data_o$next[3:0]$11367 4'0000
case
- assign $6\src14__data_o$next[3:0]$11503 $1\src14__data_o$next[3:0]$11498
+ assign $6\src24__data_o$next[3:0]$11367 $1\src24__data_o$next[3:0]$11362
end
sync always
- update \src14__data_o$next $0\src14__data_o$next[3:0]$11497
+ update \src24__data_o$next $0\src24__data_o$next[3:0]$11361
end
- attribute \src "libresoc.v:183044.3-183073.6"
- process $proc$libresoc.v:183044$11504
+ attribute \src "libresoc.v:182240.3-182269.6"
+ process $proc$libresoc.v:182240$11368
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11505 $1\wr_detect$4[0:0]$11506
- attribute \src "libresoc.v:183045.5-183045.29"
+ assign $0\wr_detect$4[0:0]$11369 $1\wr_detect$4[0:0]$11370
+ attribute \src "libresoc.v:182241.5-182241.29"
switch \initial
- attribute \src "libresoc.v:183045.9-183045.17"
+ attribute \src "libresoc.v:182241.9-182241.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src14__ren
+ switch \src24__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11506 $4\wr_detect$4[0:0]$11509
+ assign $1\wr_detect$4[0:0]$11370 $4\wr_detect$4[0:0]$11373
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11507 1'1
+ assign $2\wr_detect$4[0:0]$11371 1'1
case
- assign $2\wr_detect$4[0:0]$11507 1'0
+ assign $2\wr_detect$4[0:0]$11371 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11508 1'1
+ assign $3\wr_detect$4[0:0]$11372 1'1
case
- assign $3\wr_detect$4[0:0]$11508 $2\wr_detect$4[0:0]$11507
+ assign $3\wr_detect$4[0:0]$11372 $2\wr_detect$4[0:0]$11371
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11509 1'1
+ assign $4\wr_detect$4[0:0]$11373 1'1
case
- assign $4\wr_detect$4[0:0]$11509 $3\wr_detect$4[0:0]$11508
+ assign $4\wr_detect$4[0:0]$11373 $3\wr_detect$4[0:0]$11372
end
case
- assign $1\wr_detect$4[0:0]$11506 1'0
+ assign $1\wr_detect$4[0:0]$11370 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11505
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11369
end
- attribute \src "libresoc.v:183074.3-183113.6"
- process $proc$libresoc.v:183074$11510
+ attribute \src "libresoc.v:182270.3-182309.6"
+ process $proc$libresoc.v:182270$11374
assign { } { }
assign { } { }
assign { } { }
- assign $0\src24__data_o$next[3:0]$11511 $6\src24__data_o$next[3:0]$11517
- attribute \src "libresoc.v:183075.5-183075.29"
+ assign $0\src34__data_o$next[3:0]$11375 $6\src34__data_o$next[3:0]$11381
+ attribute \src "libresoc.v:182271.5-182271.29"
switch \initial
- attribute \src "libresoc.v:183075.9-183075.17"
+ attribute \src "libresoc.v:182271.9-182271.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src24__ren
+ switch \src34__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src24__data_o$next[3:0]$11512 $5\src24__data_o$next[3:0]$11516
+ assign $1\src34__data_o$next[3:0]$11376 $5\src34__data_o$next[3:0]$11380
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src24__data_o$next[3:0]$11513 \dest14__data_i
+ assign $2\src34__data_o$next[3:0]$11377 \dest14__data_i
case
- assign $2\src24__data_o$next[3:0]$11513 4'0000
+ assign $2\src34__data_o$next[3:0]$11377 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src24__data_o$next[3:0]$11514 \dest24__data_i
+ assign $3\src34__data_o$next[3:0]$11378 \dest24__data_i
case
- assign $3\src24__data_o$next[3:0]$11514 $2\src24__data_o$next[3:0]$11513
+ assign $3\src34__data_o$next[3:0]$11378 $2\src34__data_o$next[3:0]$11377
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src24__data_o$next[3:0]$11515 \w4__data_i
+ assign $4\src34__data_o$next[3:0]$11379 \w4__data_i
case
- assign $4\src24__data_o$next[3:0]$11515 $3\src24__data_o$next[3:0]$11514
+ assign $4\src34__data_o$next[3:0]$11379 $3\src34__data_o$next[3:0]$11378
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src24__data_o$next[3:0]$11516 \reg
+ assign $5\src34__data_o$next[3:0]$11380 \reg
case
- assign $5\src24__data_o$next[3:0]$11516 $4\src24__data_o$next[3:0]$11515
+ assign $5\src34__data_o$next[3:0]$11380 $4\src34__data_o$next[3:0]$11379
end
case
- assign $1\src24__data_o$next[3:0]$11512 4'0000
+ assign $1\src34__data_o$next[3:0]$11376 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src24__data_o$next[3:0]$11517 4'0000
+ assign $6\src34__data_o$next[3:0]$11381 4'0000
case
- assign $6\src24__data_o$next[3:0]$11517 $1\src24__data_o$next[3:0]$11512
+ assign $6\src34__data_o$next[3:0]$11381 $1\src34__data_o$next[3:0]$11376
end
sync always
- update \src24__data_o$next $0\src24__data_o$next[3:0]$11511
+ update \src34__data_o$next $0\src34__data_o$next[3:0]$11375
end
- attribute \src "libresoc.v:183114.3-183143.6"
- process $proc$libresoc.v:183114$11518
+ attribute \src "libresoc.v:182310.3-182339.6"
+ process $proc$libresoc.v:182310$11382
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11519 $1\wr_detect$7[0:0]$11520
- attribute \src "libresoc.v:183115.5-183115.29"
+ assign $0\wr_detect$7[0:0]$11383 $1\wr_detect$7[0:0]$11384
+ attribute \src "libresoc.v:182311.5-182311.29"
switch \initial
- attribute \src "libresoc.v:183115.9-183115.17"
+ attribute \src "libresoc.v:182311.9-182311.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src24__ren
+ switch \src34__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11520 $4\wr_detect$7[0:0]$11523
+ assign $1\wr_detect$7[0:0]$11384 $4\wr_detect$7[0:0]$11387
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11521 1'1
+ assign $2\wr_detect$7[0:0]$11385 1'1
case
- assign $2\wr_detect$7[0:0]$11521 1'0
+ assign $2\wr_detect$7[0:0]$11385 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11522 1'1
+ assign $3\wr_detect$7[0:0]$11386 1'1
case
- assign $3\wr_detect$7[0:0]$11522 $2\wr_detect$7[0:0]$11521
+ assign $3\wr_detect$7[0:0]$11386 $2\wr_detect$7[0:0]$11385
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11523 1'1
+ assign $4\wr_detect$7[0:0]$11387 1'1
case
- assign $4\wr_detect$7[0:0]$11523 $3\wr_detect$7[0:0]$11522
+ assign $4\wr_detect$7[0:0]$11387 $3\wr_detect$7[0:0]$11386
end
case
- assign $1\wr_detect$7[0:0]$11520 1'0
+ assign $1\wr_detect$7[0:0]$11384 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11519
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11383
end
- attribute \src "libresoc.v:183144.3-183183.6"
- process $proc$libresoc.v:183144$11524
+ attribute \src "libresoc.v:182340.3-182379.6"
+ process $proc$libresoc.v:182340$11388
assign { } { }
assign { } { }
assign { } { }
- assign $0\src34__data_o$next[3:0]$11525 $6\src34__data_o$next[3:0]$11531
- attribute \src "libresoc.v:183145.5-183145.29"
+ assign $0\r4__data_o$next[3:0]$11389 $6\r4__data_o$next[3:0]$11395
+ attribute \src "libresoc.v:182341.5-182341.29"
switch \initial
- attribute \src "libresoc.v:183145.9-183145.17"
+ attribute \src "libresoc.v:182341.9-182341.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src34__ren
+ switch \r4__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src34__data_o$next[3:0]$11526 $5\src34__data_o$next[3:0]$11530
+ assign $1\r4__data_o$next[3:0]$11390 $5\r4__data_o$next[3:0]$11394
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src34__data_o$next[3:0]$11527 \dest14__data_i
+ assign $2\r4__data_o$next[3:0]$11391 \dest14__data_i
case
- assign $2\src34__data_o$next[3:0]$11527 4'0000
+ assign $2\r4__data_o$next[3:0]$11391 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src34__data_o$next[3:0]$11528 \dest24__data_i
+ assign $3\r4__data_o$next[3:0]$11392 \dest24__data_i
case
- assign $3\src34__data_o$next[3:0]$11528 $2\src34__data_o$next[3:0]$11527
+ assign $3\r4__data_o$next[3:0]$11392 $2\r4__data_o$next[3:0]$11391
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src34__data_o$next[3:0]$11529 \w4__data_i
+ assign $4\r4__data_o$next[3:0]$11393 \w4__data_i
case
- assign $4\src34__data_o$next[3:0]$11529 $3\src34__data_o$next[3:0]$11528
+ assign $4\r4__data_o$next[3:0]$11393 $3\r4__data_o$next[3:0]$11392
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src34__data_o$next[3:0]$11530 \reg
+ assign $5\r4__data_o$next[3:0]$11394 \reg
case
- assign $5\src34__data_o$next[3:0]$11530 $4\src34__data_o$next[3:0]$11529
+ assign $5\r4__data_o$next[3:0]$11394 $4\r4__data_o$next[3:0]$11393
end
case
- assign $1\src34__data_o$next[3:0]$11526 4'0000
+ assign $1\r4__data_o$next[3:0]$11390 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src34__data_o$next[3:0]$11531 4'0000
+ assign $6\r4__data_o$next[3:0]$11395 4'0000
case
- assign $6\src34__data_o$next[3:0]$11531 $1\src34__data_o$next[3:0]$11526
+ assign $6\r4__data_o$next[3:0]$11395 $1\r4__data_o$next[3:0]$11390
end
sync always
- update \src34__data_o$next $0\src34__data_o$next[3:0]$11525
+ update \r4__data_o$next $0\r4__data_o$next[3:0]$11389
end
- attribute \src "libresoc.v:183184.3-183213.6"
- process $proc$libresoc.v:183184$11532
+ attribute \src "libresoc.v:182380.3-182409.6"
+ process $proc$libresoc.v:182380$11396
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11533 $1\wr_detect$10[0:0]$11534
- attribute \src "libresoc.v:183185.5-183185.29"
+ assign $0\wr_detect$10[0:0]$11397 $1\wr_detect$10[0:0]$11398
+ attribute \src "libresoc.v:182381.5-182381.29"
switch \initial
- attribute \src "libresoc.v:183185.9-183185.17"
+ attribute \src "libresoc.v:182381.9-182381.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src34__ren
+ switch \r4__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11534 $4\wr_detect$10[0:0]$11537
+ assign $1\wr_detect$10[0:0]$11398 $4\wr_detect$10[0:0]$11401
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11535 1'1
+ assign $2\wr_detect$10[0:0]$11399 1'1
case
- assign $2\wr_detect$10[0:0]$11535 1'0
+ assign $2\wr_detect$10[0:0]$11399 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11536 1'1
+ assign $3\wr_detect$10[0:0]$11400 1'1
case
- assign $3\wr_detect$10[0:0]$11536 $2\wr_detect$10[0:0]$11535
+ assign $3\wr_detect$10[0:0]$11400 $2\wr_detect$10[0:0]$11399
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11537 1'1
+ assign $4\wr_detect$10[0:0]$11401 1'1
case
- assign $4\wr_detect$10[0:0]$11537 $3\wr_detect$10[0:0]$11536
+ assign $4\wr_detect$10[0:0]$11401 $3\wr_detect$10[0:0]$11400
end
case
- assign $1\wr_detect$10[0:0]$11534 1'0
+ assign $1\wr_detect$10[0:0]$11398 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11533
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11397
end
- attribute \src "libresoc.v:183214.3-183253.6"
- process $proc$libresoc.v:183214$11538
+ attribute \src "libresoc.v:182410.3-182449.6"
+ process $proc$libresoc.v:182410$11402
assign { } { }
assign { } { }
assign { } { }
- assign $0\r4__data_o$next[3:0]$11539 $6\r4__data_o$next[3:0]$11545
- attribute \src "libresoc.v:183215.5-183215.29"
+ assign $0\r24__data_o$next[3:0]$11403 $6\r24__data_o$next[3:0]$11409
+ attribute \src "libresoc.v:182411.5-182411.29"
switch \initial
- attribute \src "libresoc.v:183215.9-183215.17"
+ attribute \src "libresoc.v:182411.9-182411.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r4__ren
+ switch \r24__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r4__data_o$next[3:0]$11540 $5\r4__data_o$next[3:0]$11544
+ assign $1\r24__data_o$next[3:0]$11404 $5\r24__data_o$next[3:0]$11408
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r4__data_o$next[3:0]$11541 \dest14__data_i
+ assign $2\r24__data_o$next[3:0]$11405 \dest14__data_i
case
- assign $2\r4__data_o$next[3:0]$11541 4'0000
+ assign $2\r24__data_o$next[3:0]$11405 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r4__data_o$next[3:0]$11542 \dest24__data_i
+ assign $3\r24__data_o$next[3:0]$11406 \dest24__data_i
case
- assign $3\r4__data_o$next[3:0]$11542 $2\r4__data_o$next[3:0]$11541
+ assign $3\r24__data_o$next[3:0]$11406 $2\r24__data_o$next[3:0]$11405
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r4__data_o$next[3:0]$11543 \w4__data_i
+ assign $4\r24__data_o$next[3:0]$11407 \w4__data_i
case
- assign $4\r4__data_o$next[3:0]$11543 $3\r4__data_o$next[3:0]$11542
+ assign $4\r24__data_o$next[3:0]$11407 $3\r24__data_o$next[3:0]$11406
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r4__data_o$next[3:0]$11544 \reg
+ assign $5\r24__data_o$next[3:0]$11408 \reg
case
- assign $5\r4__data_o$next[3:0]$11544 $4\r4__data_o$next[3:0]$11543
+ assign $5\r24__data_o$next[3:0]$11408 $4\r24__data_o$next[3:0]$11407
end
case
- assign $1\r4__data_o$next[3:0]$11540 4'0000
+ assign $1\r24__data_o$next[3:0]$11404 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r4__data_o$next[3:0]$11545 4'0000
+ assign $6\r24__data_o$next[3:0]$11409 4'0000
case
- assign $6\r4__data_o$next[3:0]$11545 $1\r4__data_o$next[3:0]$11540
+ assign $6\r24__data_o$next[3:0]$11409 $1\r24__data_o$next[3:0]$11404
end
sync always
- update \r4__data_o$next $0\r4__data_o$next[3:0]$11539
+ update \r24__data_o$next $0\r24__data_o$next[3:0]$11403
end
- attribute \src "libresoc.v:183254.3-183283.6"
- process $proc$libresoc.v:183254$11546
+ attribute \src "libresoc.v:182450.3-182479.6"
+ process $proc$libresoc.v:182450$11410
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11547 $1\wr_detect$13[0:0]$11548
- attribute \src "libresoc.v:183255.5-183255.29"
+ assign $0\wr_detect$13[0:0]$11411 $1\wr_detect$13[0:0]$11412
+ attribute \src "libresoc.v:182451.5-182451.29"
switch \initial
- attribute \src "libresoc.v:183255.9-183255.17"
+ attribute \src "libresoc.v:182451.9-182451.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r4__ren
+ switch \r24__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11548 $4\wr_detect$13[0:0]$11551
+ assign $1\wr_detect$13[0:0]$11412 $4\wr_detect$13[0:0]$11415
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11549 1'1
+ assign $2\wr_detect$13[0:0]$11413 1'1
case
- assign $2\wr_detect$13[0:0]$11549 1'0
+ assign $2\wr_detect$13[0:0]$11413 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11550 1'1
+ assign $3\wr_detect$13[0:0]$11414 1'1
case
- assign $3\wr_detect$13[0:0]$11550 $2\wr_detect$13[0:0]$11549
+ assign $3\wr_detect$13[0:0]$11414 $2\wr_detect$13[0:0]$11413
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11551 1'1
+ assign $4\wr_detect$13[0:0]$11415 1'1
case
- assign $4\wr_detect$13[0:0]$11551 $3\wr_detect$13[0:0]$11550
+ assign $4\wr_detect$13[0:0]$11415 $3\wr_detect$13[0:0]$11414
end
case
- assign $1\wr_detect$13[0:0]$11548 1'0
+ assign $1\wr_detect$13[0:0]$11412 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11547
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11411
end
- connect \$9 $not$libresoc.v:182817$11454_Y
- connect \$12 $not$libresoc.v:182818$11455_Y
- connect \$15 $not$libresoc.v:182819$11456_Y
- connect \$1 $not$libresoc.v:182820$11457_Y
- connect \$3 $not$libresoc.v:182821$11458_Y
- connect \$6 $not$libresoc.v:182822$11459_Y
+ connect \$9 $not$libresoc.v:182086$11334_Y
+ connect \$12 $not$libresoc.v:182087$11335_Y
+ connect \$1 $not$libresoc.v:182088$11336_Y
+ connect \$3 $not$libresoc.v:182089$11337_Y
+ connect \$6 $not$libresoc.v:182090$11338_Y
end
-attribute \src "libresoc.v:183288.1-183843.10"
+attribute \src "libresoc.v:182484.1-182955.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5"
attribute \generator "nMigen"
module \reg_5
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $0\cr_pred5__data_o$next[3:0]$11574
- attribute \src "libresoc.v:183394.3-183395.49"
- wire width 4 $0\cr_pred5__data_o[3:0]
- attribute \src "libresoc.v:183289.7-183289.20"
+ attribute \src "libresoc.v:182485.7-182485.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $0\r25__data_o$next[3:0]$11583
- attribute \src "libresoc.v:183384.3-183385.39"
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $0\r25__data_o$next[3:0]$11492
+ attribute \src "libresoc.v:182568.3-182569.39"
wire width 4 $0\r25__data_o[3:0]
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $0\r5__data_o$next[3:0]$11645
- attribute \src "libresoc.v:183386.3-183387.37"
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $0\r5__data_o$next[3:0]$11478
+ attribute \src "libresoc.v:182570.3-182571.37"
wire width 4 $0\r5__data_o[3:0]
- attribute \src "libresoc.v:183536.3-183562.6"
- wire width 4 $0\reg$next[3:0]$11597
- attribute \src "libresoc.v:183382.3-183383.25"
+ attribute \src "libresoc.v:182648.3-182674.6"
+ wire width 4 $0\reg$next[3:0]$11444
+ attribute \src "libresoc.v:182566.3-182567.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $0\src15__data_o$next[3:0]$11603
- attribute \src "libresoc.v:183392.3-183393.43"
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $0\src15__data_o$next[3:0]$11435
+ attribute \src "libresoc.v:182576.3-182577.43"
wire width 4 $0\src15__data_o[3:0]
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $0\src25__data_o$next[3:0]$11617
- attribute \src "libresoc.v:183390.3-183391.43"
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $0\src25__data_o$next[3:0]$11450
+ attribute \src "libresoc.v:182574.3-182575.43"
wire width 4 $0\src25__data_o[3:0]
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $0\src35__data_o$next[3:0]$11631
- attribute \src "libresoc.v:183388.3-183389.43"
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $0\src35__data_o$next[3:0]$11464
+ attribute \src "libresoc.v:182572.3-182573.43"
wire width 4 $0\src35__data_o[3:0]
- attribute \src "libresoc.v:183743.3-183772.6"
- wire $0\wr_detect$10[0:0]$11639
- attribute \src "libresoc.v:183813.3-183842.6"
- wire $0\wr_detect$13[0:0]$11653
- attribute \src "libresoc.v:183506.3-183535.6"
- wire $0\wr_detect$16[0:0]$11591
- attribute \src "libresoc.v:183603.3-183632.6"
- wire $0\wr_detect$4[0:0]$11611
- attribute \src "libresoc.v:183673.3-183702.6"
- wire $0\wr_detect$7[0:0]$11625
- attribute \src "libresoc.v:183436.3-183465.6"
+ attribute \src "libresoc.v:182855.3-182884.6"
+ wire $0\wr_detect$10[0:0]$11486
+ attribute \src "libresoc.v:182925.3-182954.6"
+ wire $0\wr_detect$13[0:0]$11500
+ attribute \src "libresoc.v:182715.3-182744.6"
+ wire $0\wr_detect$4[0:0]$11458
+ attribute \src "libresoc.v:182785.3-182814.6"
+ wire $0\wr_detect$7[0:0]$11472
+ attribute \src "libresoc.v:182618.3-182647.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $1\cr_pred5__data_o$next[3:0]$11575
- attribute \src "libresoc.v:183308.13-183308.36"
- wire width 4 $1\cr_pred5__data_o[3:0]
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $1\r25__data_o$next[3:0]$11584
- attribute \src "libresoc.v:183323.13-183323.31"
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $1\r25__data_o$next[3:0]$11493
+ attribute \src "libresoc.v:182510.13-182510.31"
wire width 4 $1\r25__data_o[3:0]
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $1\r5__data_o$next[3:0]$11646
- attribute \src "libresoc.v:183330.13-183330.30"
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $1\r5__data_o$next[3:0]$11479
+ attribute \src "libresoc.v:182517.13-182517.30"
wire width 4 $1\r5__data_o[3:0]
- attribute \src "libresoc.v:183536.3-183562.6"
- wire width 4 $1\reg$next[3:0]$11598
- attribute \src "libresoc.v:183336.13-183336.25"
+ attribute \src "libresoc.v:182648.3-182674.6"
+ wire width 4 $1\reg$next[3:0]$11445
+ attribute \src "libresoc.v:182523.13-182523.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $1\src15__data_o$next[3:0]$11604
- attribute \src "libresoc.v:183341.13-183341.33"
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $1\src15__data_o$next[3:0]$11436
+ attribute \src "libresoc.v:182528.13-182528.33"
wire width 4 $1\src15__data_o[3:0]
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $1\src25__data_o$next[3:0]$11618
- attribute \src "libresoc.v:183348.13-183348.33"
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $1\src25__data_o$next[3:0]$11451
+ attribute \src "libresoc.v:182535.13-182535.33"
wire width 4 $1\src25__data_o[3:0]
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $1\src35__data_o$next[3:0]$11632
- attribute \src "libresoc.v:183355.13-183355.33"
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $1\src35__data_o$next[3:0]$11465
+ attribute \src "libresoc.v:182542.13-182542.33"
wire width 4 $1\src35__data_o[3:0]
- attribute \src "libresoc.v:183743.3-183772.6"
- wire $1\wr_detect$10[0:0]$11640
- attribute \src "libresoc.v:183813.3-183842.6"
- wire $1\wr_detect$13[0:0]$11654
- attribute \src "libresoc.v:183506.3-183535.6"
- wire $1\wr_detect$16[0:0]$11592
- attribute \src "libresoc.v:183603.3-183632.6"
- wire $1\wr_detect$4[0:0]$11612
- attribute \src "libresoc.v:183673.3-183702.6"
- wire $1\wr_detect$7[0:0]$11626
- attribute \src "libresoc.v:183436.3-183465.6"
+ attribute \src "libresoc.v:182855.3-182884.6"
+ wire $1\wr_detect$10[0:0]$11487
+ attribute \src "libresoc.v:182925.3-182954.6"
+ wire $1\wr_detect$13[0:0]$11501
+ attribute \src "libresoc.v:182715.3-182744.6"
+ wire $1\wr_detect$4[0:0]$11459
+ attribute \src "libresoc.v:182785.3-182814.6"
+ wire $1\wr_detect$7[0:0]$11473
+ attribute \src "libresoc.v:182618.3-182647.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $2\cr_pred5__data_o$next[3:0]$11576
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $2\r25__data_o$next[3:0]$11585
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $2\r5__data_o$next[3:0]$11647
- attribute \src "libresoc.v:183536.3-183562.6"
- wire width 4 $2\reg$next[3:0]$11599
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $2\src15__data_o$next[3:0]$11605
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $2\src25__data_o$next[3:0]$11619
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $2\src35__data_o$next[3:0]$11633
- attribute \src "libresoc.v:183743.3-183772.6"
- wire $2\wr_detect$10[0:0]$11641
- attribute \src "libresoc.v:183813.3-183842.6"
- wire $2\wr_detect$13[0:0]$11655
- attribute \src "libresoc.v:183506.3-183535.6"
- wire $2\wr_detect$16[0:0]$11593
- attribute \src "libresoc.v:183603.3-183632.6"
- wire $2\wr_detect$4[0:0]$11613
- attribute \src "libresoc.v:183673.3-183702.6"
- wire $2\wr_detect$7[0:0]$11627
- attribute \src "libresoc.v:183436.3-183465.6"
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $2\r25__data_o$next[3:0]$11494
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $2\r5__data_o$next[3:0]$11480
+ attribute \src "libresoc.v:182648.3-182674.6"
+ wire width 4 $2\reg$next[3:0]$11446
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $2\src15__data_o$next[3:0]$11437
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $2\src25__data_o$next[3:0]$11452
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $2\src35__data_o$next[3:0]$11466
+ attribute \src "libresoc.v:182855.3-182884.6"
+ wire $2\wr_detect$10[0:0]$11488
+ attribute \src "libresoc.v:182925.3-182954.6"
+ wire $2\wr_detect$13[0:0]$11502
+ attribute \src "libresoc.v:182715.3-182744.6"
+ wire $2\wr_detect$4[0:0]$11460
+ attribute \src "libresoc.v:182785.3-182814.6"
+ wire $2\wr_detect$7[0:0]$11474
+ attribute \src "libresoc.v:182618.3-182647.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $3\cr_pred5__data_o$next[3:0]$11577
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $3\r25__data_o$next[3:0]$11586
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $3\r5__data_o$next[3:0]$11648
- attribute \src "libresoc.v:183536.3-183562.6"
- wire width 4 $3\reg$next[3:0]$11600
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $3\src15__data_o$next[3:0]$11606
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $3\src25__data_o$next[3:0]$11620
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $3\src35__data_o$next[3:0]$11634
- attribute \src "libresoc.v:183743.3-183772.6"
- wire $3\wr_detect$10[0:0]$11642
- attribute \src "libresoc.v:183813.3-183842.6"
- wire $3\wr_detect$13[0:0]$11656
- attribute \src "libresoc.v:183506.3-183535.6"
- wire $3\wr_detect$16[0:0]$11594
- attribute \src "libresoc.v:183603.3-183632.6"
- wire $3\wr_detect$4[0:0]$11614
- attribute \src "libresoc.v:183673.3-183702.6"
- wire $3\wr_detect$7[0:0]$11628
- attribute \src "libresoc.v:183436.3-183465.6"
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $3\r25__data_o$next[3:0]$11495
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $3\r5__data_o$next[3:0]$11481
+ attribute \src "libresoc.v:182648.3-182674.6"
+ wire width 4 $3\reg$next[3:0]$11447
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $3\src15__data_o$next[3:0]$11438
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $3\src25__data_o$next[3:0]$11453
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $3\src35__data_o$next[3:0]$11467
+ attribute \src "libresoc.v:182855.3-182884.6"
+ wire $3\wr_detect$10[0:0]$11489
+ attribute \src "libresoc.v:182925.3-182954.6"
+ wire $3\wr_detect$13[0:0]$11503
+ attribute \src "libresoc.v:182715.3-182744.6"
+ wire $3\wr_detect$4[0:0]$11461
+ attribute \src "libresoc.v:182785.3-182814.6"
+ wire $3\wr_detect$7[0:0]$11475
+ attribute \src "libresoc.v:182618.3-182647.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $4\cr_pred5__data_o$next[3:0]$11578
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $4\r25__data_o$next[3:0]$11587
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $4\r5__data_o$next[3:0]$11649
- attribute \src "libresoc.v:183536.3-183562.6"
- wire width 4 $4\reg$next[3:0]$11601
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $4\src15__data_o$next[3:0]$11607
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $4\src25__data_o$next[3:0]$11621
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $4\src35__data_o$next[3:0]$11635
- attribute \src "libresoc.v:183743.3-183772.6"
- wire $4\wr_detect$10[0:0]$11643
- attribute \src "libresoc.v:183813.3-183842.6"
- wire $4\wr_detect$13[0:0]$11657
- attribute \src "libresoc.v:183506.3-183535.6"
- wire $4\wr_detect$16[0:0]$11595
- attribute \src "libresoc.v:183603.3-183632.6"
- wire $4\wr_detect$4[0:0]$11615
- attribute \src "libresoc.v:183673.3-183702.6"
- wire $4\wr_detect$7[0:0]$11629
- attribute \src "libresoc.v:183436.3-183465.6"
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $4\r25__data_o$next[3:0]$11496
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $4\r5__data_o$next[3:0]$11482
+ attribute \src "libresoc.v:182648.3-182674.6"
+ wire width 4 $4\reg$next[3:0]$11448
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $4\src15__data_o$next[3:0]$11439
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $4\src25__data_o$next[3:0]$11454
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $4\src35__data_o$next[3:0]$11468
+ attribute \src "libresoc.v:182855.3-182884.6"
+ wire $4\wr_detect$10[0:0]$11490
+ attribute \src "libresoc.v:182925.3-182954.6"
+ wire $4\wr_detect$13[0:0]$11504
+ attribute \src "libresoc.v:182715.3-182744.6"
+ wire $4\wr_detect$4[0:0]$11462
+ attribute \src "libresoc.v:182785.3-182814.6"
+ wire $4\wr_detect$7[0:0]$11476
+ attribute \src "libresoc.v:182618.3-182647.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $5\cr_pred5__data_o$next[3:0]$11579
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $5\r25__data_o$next[3:0]$11588
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $5\r5__data_o$next[3:0]$11650
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $5\src15__data_o$next[3:0]$11608
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $5\src25__data_o$next[3:0]$11622
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $5\src35__data_o$next[3:0]$11636
- attribute \src "libresoc.v:183396.3-183435.6"
- wire width 4 $6\cr_pred5__data_o$next[3:0]$11580
- attribute \src "libresoc.v:183466.3-183505.6"
- wire width 4 $6\r25__data_o$next[3:0]$11589
- attribute \src "libresoc.v:183773.3-183812.6"
- wire width 4 $6\r5__data_o$next[3:0]$11651
- attribute \src "libresoc.v:183563.3-183602.6"
- wire width 4 $6\src15__data_o$next[3:0]$11609
- attribute \src "libresoc.v:183633.3-183672.6"
- wire width 4 $6\src25__data_o$next[3:0]$11623
- attribute \src "libresoc.v:183703.3-183742.6"
- wire width 4 $6\src35__data_o$next[3:0]$11637
- attribute \src "libresoc.v:183376.17-183376.104"
- wire $not$libresoc.v:183376$11560_Y
- attribute \src "libresoc.v:183377.18-183377.105"
- wire $not$libresoc.v:183377$11561_Y
- attribute \src "libresoc.v:183378.18-183378.105"
- wire $not$libresoc.v:183378$11562_Y
- attribute \src "libresoc.v:183379.17-183379.100"
- wire $not$libresoc.v:183379$11563_Y
- attribute \src "libresoc.v:183380.17-183380.103"
- wire $not$libresoc.v:183380$11564_Y
- attribute \src "libresoc.v:183381.17-183381.103"
- wire $not$libresoc.v:183381$11565_Y
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $5\r25__data_o$next[3:0]$11497
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $5\r5__data_o$next[3:0]$11483
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $5\src15__data_o$next[3:0]$11440
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $5\src25__data_o$next[3:0]$11455
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $5\src35__data_o$next[3:0]$11469
+ attribute \src "libresoc.v:182885.3-182924.6"
+ wire width 4 $6\r25__data_o$next[3:0]$11498
+ attribute \src "libresoc.v:182815.3-182854.6"
+ wire width 4 $6\r5__data_o$next[3:0]$11484
+ attribute \src "libresoc.v:182578.3-182617.6"
+ wire width 4 $6\src15__data_o$next[3:0]$11441
+ attribute \src "libresoc.v:182675.3-182714.6"
+ wire width 4 $6\src25__data_o$next[3:0]$11456
+ attribute \src "libresoc.v:182745.3-182784.6"
+ wire width 4 $6\src35__data_o$next[3:0]$11470
+ attribute \src "libresoc.v:182561.17-182561.104"
+ wire $not$libresoc.v:182561$11423_Y
+ attribute \src "libresoc.v:182562.18-182562.105"
+ wire $not$libresoc.v:182562$11424_Y
+ attribute \src "libresoc.v:182563.17-182563.100"
+ wire $not$libresoc.v:182563$11425_Y
+ attribute \src "libresoc.v:182564.17-182564.103"
+ wire $not$libresoc.v:182564$11426_Y
+ attribute \src "libresoc.v:182565.17-182565.103"
+ wire $not$libresoc.v:182565$11427_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred5__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred5__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred5__ren
+ wire width 4 input 9 \dest15__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest15__data_i
+ wire input 8 \dest15__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest15__wen
+ wire width 4 input 11 \dest25__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest25__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest25__wen
- attribute \src "libresoc.v:183289.7-183289.15"
+ wire input 10 \dest25__wen
+ attribute \src "libresoc.v:182485.7-182485.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r25__data_o
+ wire width 4 output 14 \r25__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r25__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r25__ren
+ wire input 15 \r25__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r5__data_o
+ wire width 4 output 12 \r5__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r5__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r5__ren
+ wire input 13 \r5__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src15__data_o
+ wire width 4 output 3 \src15__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src15__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src15__ren
+ wire input 2 \src15__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src25__data_o
+ wire width 4 output 5 \src25__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src25__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src25__ren
+ wire input 4 \src25__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src35__data_o
+ wire width 4 output 7 \src35__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src35__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src35__ren
+ wire input 6 \src35__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w5__data_i
+ wire width 4 input 16 \w5__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w5__wen
+ wire input 17 \w5__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183376$11560
+ cell $not $not$libresoc.v:182561$11423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:183376$11560_Y
+ connect \Y $not$libresoc.v:182561$11423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183377$11561
+ cell $not $not$libresoc.v:182562$11424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:183377$11561_Y
+ connect \Y $not$libresoc.v:182562$11424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183378$11562
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:183378$11562_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183379$11563
+ cell $not $not$libresoc.v:182563$11425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:183379$11563_Y
+ connect \Y $not$libresoc.v:182563$11425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183380$11564
+ cell $not $not$libresoc.v:182564$11426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:183380$11564_Y
+ connect \Y $not$libresoc.v:182564$11426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183381$11565
+ cell $not $not$libresoc.v:182565$11427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:183381$11565_Y
+ connect \Y $not$libresoc.v:182565$11427_Y
end
- attribute \src "libresoc.v:183289.7-183289.20"
- process $proc$libresoc.v:183289$11658
+ attribute \src "libresoc.v:182485.7-182485.20"
+ process $proc$libresoc.v:182485$11505
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183308.13-183308.36"
- process $proc$libresoc.v:183308$11659
- assign { } { }
- assign $1\cr_pred5__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred5__data_o $1\cr_pred5__data_o[3:0]
- end
- attribute \src "libresoc.v:183323.13-183323.31"
- process $proc$libresoc.v:183323$11660
+ attribute \src "libresoc.v:182510.13-182510.31"
+ process $proc$libresoc.v:182510$11506
assign { } { }
assign $1\r25__data_o[3:0] 4'0000
sync always
sync init
update \r25__data_o $1\r25__data_o[3:0]
end
- attribute \src "libresoc.v:183330.13-183330.30"
- process $proc$libresoc.v:183330$11661
+ attribute \src "libresoc.v:182517.13-182517.30"
+ process $proc$libresoc.v:182517$11507
assign { } { }
assign $1\r5__data_o[3:0] 4'0000
sync always
sync init
update \r5__data_o $1\r5__data_o[3:0]
end
- attribute \src "libresoc.v:183336.13-183336.25"
- process $proc$libresoc.v:183336$11662
+ attribute \src "libresoc.v:182523.13-182523.25"
+ process $proc$libresoc.v:182523$11508
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:183341.13-183341.33"
- process $proc$libresoc.v:183341$11663
+ attribute \src "libresoc.v:182528.13-182528.33"
+ process $proc$libresoc.v:182528$11509
assign { } { }
assign $1\src15__data_o[3:0] 4'0000
sync always
sync init
update \src15__data_o $1\src15__data_o[3:0]
end
- attribute \src "libresoc.v:183348.13-183348.33"
- process $proc$libresoc.v:183348$11664
+ attribute \src "libresoc.v:182535.13-182535.33"
+ process $proc$libresoc.v:182535$11510
assign { } { }
assign $1\src25__data_o[3:0] 4'0000
sync always
sync init
update \src25__data_o $1\src25__data_o[3:0]
end
- attribute \src "libresoc.v:183355.13-183355.33"
- process $proc$libresoc.v:183355$11665
+ attribute \src "libresoc.v:182542.13-182542.33"
+ process $proc$libresoc.v:182542$11511
assign { } { }
assign $1\src35__data_o[3:0] 4'0000
sync always
sync init
update \src35__data_o $1\src35__data_o[3:0]
end
- attribute \src "libresoc.v:183382.3-183383.25"
- process $proc$libresoc.v:183382$11566
+ attribute \src "libresoc.v:182566.3-182567.25"
+ process $proc$libresoc.v:182566$11428
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:183384.3-183385.39"
- process $proc$libresoc.v:183384$11567
+ attribute \src "libresoc.v:182568.3-182569.39"
+ process $proc$libresoc.v:182568$11429
assign { } { }
assign $0\r25__data_o[3:0] \r25__data_o$next
sync posedge \coresync_clk
update \r25__data_o $0\r25__data_o[3:0]
end
- attribute \src "libresoc.v:183386.3-183387.37"
- process $proc$libresoc.v:183386$11568
+ attribute \src "libresoc.v:182570.3-182571.37"
+ process $proc$libresoc.v:182570$11430
assign { } { }
assign $0\r5__data_o[3:0] \r5__data_o$next
sync posedge \coresync_clk
update \r5__data_o $0\r5__data_o[3:0]
end
- attribute \src "libresoc.v:183388.3-183389.43"
- process $proc$libresoc.v:183388$11569
+ attribute \src "libresoc.v:182572.3-182573.43"
+ process $proc$libresoc.v:182572$11431
assign { } { }
assign $0\src35__data_o[3:0] \src35__data_o$next
sync posedge \coresync_clk
update \src35__data_o $0\src35__data_o[3:0]
end
- attribute \src "libresoc.v:183390.3-183391.43"
- process $proc$libresoc.v:183390$11570
+ attribute \src "libresoc.v:182574.3-182575.43"
+ process $proc$libresoc.v:182574$11432
assign { } { }
assign $0\src25__data_o[3:0] \src25__data_o$next
sync posedge \coresync_clk
update \src25__data_o $0\src25__data_o[3:0]
end
- attribute \src "libresoc.v:183392.3-183393.43"
- process $proc$libresoc.v:183392$11571
+ attribute \src "libresoc.v:182576.3-182577.43"
+ process $proc$libresoc.v:182576$11433
assign { } { }
assign $0\src15__data_o[3:0] \src15__data_o$next
sync posedge \coresync_clk
update \src15__data_o $0\src15__data_o[3:0]
end
- attribute \src "libresoc.v:183394.3-183395.49"
- process $proc$libresoc.v:183394$11572
- assign { } { }
- assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next
- sync posedge \coresync_clk
- update \cr_pred5__data_o $0\cr_pred5__data_o[3:0]
- end
- attribute \src "libresoc.v:183396.3-183435.6"
- process $proc$libresoc.v:183396$11573
+ attribute \src "libresoc.v:182578.3-182617.6"
+ process $proc$libresoc.v:182578$11434
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_pred5__data_o$next[3:0]$11574 $6\cr_pred5__data_o$next[3:0]$11580
- attribute \src "libresoc.v:183397.5-183397.29"
+ assign $0\src15__data_o$next[3:0]$11435 $6\src15__data_o$next[3:0]$11441
+ attribute \src "libresoc.v:182579.5-182579.29"
switch \initial
- attribute \src "libresoc.v:183397.9-183397.17"
+ attribute \src "libresoc.v:182579.9-182579.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred5__ren
+ switch \src15__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred5__data_o$next[3:0]$11575 $5\cr_pred5__data_o$next[3:0]$11579
+ assign $1\src15__data_o$next[3:0]$11436 $5\src15__data_o$next[3:0]$11440
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred5__data_o$next[3:0]$11576 \dest15__data_i
+ assign $2\src15__data_o$next[3:0]$11437 \dest15__data_i
case
- assign $2\cr_pred5__data_o$next[3:0]$11576 4'0000
+ assign $2\src15__data_o$next[3:0]$11437 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred5__data_o$next[3:0]$11577 \dest25__data_i
+ assign $3\src15__data_o$next[3:0]$11438 \dest25__data_i
case
- assign $3\cr_pred5__data_o$next[3:0]$11577 $2\cr_pred5__data_o$next[3:0]$11576
+ assign $3\src15__data_o$next[3:0]$11438 $2\src15__data_o$next[3:0]$11437
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred5__data_o$next[3:0]$11578 \w5__data_i
+ assign $4\src15__data_o$next[3:0]$11439 \w5__data_i
case
- assign $4\cr_pred5__data_o$next[3:0]$11578 $3\cr_pred5__data_o$next[3:0]$11577
+ assign $4\src15__data_o$next[3:0]$11439 $3\src15__data_o$next[3:0]$11438
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred5__data_o$next[3:0]$11579 \reg
+ assign $5\src15__data_o$next[3:0]$11440 \reg
case
- assign $5\cr_pred5__data_o$next[3:0]$11579 $4\cr_pred5__data_o$next[3:0]$11578
+ assign $5\src15__data_o$next[3:0]$11440 $4\src15__data_o$next[3:0]$11439
end
case
- assign $1\cr_pred5__data_o$next[3:0]$11575 4'0000
+ assign $1\src15__data_o$next[3:0]$11436 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred5__data_o$next[3:0]$11580 4'0000
+ assign $6\src15__data_o$next[3:0]$11441 4'0000
case
- assign $6\cr_pred5__data_o$next[3:0]$11580 $1\cr_pred5__data_o$next[3:0]$11575
+ assign $6\src15__data_o$next[3:0]$11441 $1\src15__data_o$next[3:0]$11436
end
sync always
- update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11574
+ update \src15__data_o$next $0\src15__data_o$next[3:0]$11435
end
- attribute \src "libresoc.v:183436.3-183465.6"
- process $proc$libresoc.v:183436$11581
+ attribute \src "libresoc.v:182618.3-182647.6"
+ process $proc$libresoc.v:182618$11442
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:183437.5-183437.29"
+ attribute \src "libresoc.v:182619.5-182619.29"
switch \initial
- attribute \src "libresoc.v:183437.9-183437.17"
+ attribute \src "libresoc.v:182619.9-182619.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred5__ren
+ switch \src15__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:183466.3-183505.6"
- process $proc$libresoc.v:183466$11582
+ attribute \src "libresoc.v:182648.3-182674.6"
+ process $proc$libresoc.v:182648$11443
assign { } { }
assign { } { }
assign { } { }
- assign $0\r25__data_o$next[3:0]$11583 $6\r25__data_o$next[3:0]$11589
- attribute \src "libresoc.v:183467.5-183467.29"
+ assign { } { }
+ assign { } { }
+ assign $0\reg$next[3:0]$11444 $4\reg$next[3:0]$11448
+ attribute \src "libresoc.v:182649.5-182649.29"
switch \initial
- attribute \src "libresoc.v:183467.9-183467.17"
+ attribute \src "libresoc.v:182649.9-182649.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r25__ren
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
+ assign $1\reg$next[3:0]$11445 \dest15__data_i
+ case
+ assign $1\reg$next[3:0]$11445 \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest25__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
+ assign $2\reg$next[3:0]$11446 \dest25__data_i
+ case
+ assign $2\reg$next[3:0]$11446 $1\reg$next[3:0]$11445
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \w5__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
- assign { } { }
- assign $1\r25__data_o$next[3:0]$11584 $5\r25__data_o$next[3:0]$11588
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest15__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r25__data_o$next[3:0]$11585 \dest15__data_i
- case
- assign $2\r25__data_o$next[3:0]$11585 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest25__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r25__data_o$next[3:0]$11586 \dest25__data_i
- case
- assign $3\r25__data_o$next[3:0]$11586 $2\r25__data_o$next[3:0]$11585
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w5__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r25__data_o$next[3:0]$11587 \w5__data_i
- case
- assign $4\r25__data_o$next[3:0]$11587 $3\r25__data_o$next[3:0]$11586
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r25__data_o$next[3:0]$11588 \reg
- case
- assign $5\r25__data_o$next[3:0]$11588 $4\r25__data_o$next[3:0]$11587
- end
+ assign $3\reg$next[3:0]$11447 \w5__data_i
case
- assign $1\r25__data_o$next[3:0]$11584 4'0000
+ assign $3\reg$next[3:0]$11447 $2\reg$next[3:0]$11446
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r25__data_o$next[3:0]$11589 4'0000
+ assign $4\reg$next[3:0]$11448 4'0000
case
- assign $6\r25__data_o$next[3:0]$11589 $1\r25__data_o$next[3:0]$11584
+ assign $4\reg$next[3:0]$11448 $3\reg$next[3:0]$11447
end
sync always
- update \r25__data_o$next $0\r25__data_o$next[3:0]$11583
+ update \reg$next $0\reg$next[3:0]$11444
end
- attribute \src "libresoc.v:183506.3-183535.6"
- process $proc$libresoc.v:183506$11590
+ attribute \src "libresoc.v:182675.3-182714.6"
+ process $proc$libresoc.v:182675$11449
+ assign { } { }
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$11591 $1\wr_detect$16[0:0]$11592
- attribute \src "libresoc.v:183507.5-183507.29"
+ assign $0\src25__data_o$next[3:0]$11450 $6\src25__data_o$next[3:0]$11456
+ attribute \src "libresoc.v:182676.5-182676.29"
switch \initial
- attribute \src "libresoc.v:183507.9-183507.17"
+ attribute \src "libresoc.v:182676.9-182676.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r25__ren
+ switch \src25__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$16[0:0]$11592 $4\wr_detect$16[0:0]$11595
+ assign $1\src25__data_o$next[3:0]$11451 $5\src25__data_o$next[3:0]$11455
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$16[0:0]$11593 1'1
+ assign $2\src25__data_o$next[3:0]$11452 \dest15__data_i
case
- assign $2\wr_detect$16[0:0]$11593 1'0
+ assign $2\src25__data_o$next[3:0]$11452 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$16[0:0]$11594 1'1
+ assign $3\src25__data_o$next[3:0]$11453 \dest25__data_i
case
- assign $3\wr_detect$16[0:0]$11594 $2\wr_detect$16[0:0]$11593
+ assign $3\src25__data_o$next[3:0]$11453 $2\src25__data_o$next[3:0]$11452
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$16[0:0]$11595 1'1
+ assign $4\src25__data_o$next[3:0]$11454 \w5__data_i
case
- assign $4\wr_detect$16[0:0]$11595 $3\wr_detect$16[0:0]$11594
- end
- case
- assign $1\wr_detect$16[0:0]$11592 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11591
- end
- attribute \src "libresoc.v:183536.3-183562.6"
- process $proc$libresoc.v:183536$11596
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$11597 $4\reg$next[3:0]$11601
- attribute \src "libresoc.v:183537.5-183537.29"
- switch \initial
- attribute \src "libresoc.v:183537.9-183537.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest15__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg$next[3:0]$11598 \dest15__data_i
- case
- assign $1\reg$next[3:0]$11598 \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest25__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\reg$next[3:0]$11599 \dest25__data_i
- case
- assign $2\reg$next[3:0]$11599 $1\reg$next[3:0]$11598
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \w5__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\reg$next[3:0]$11600 \w5__data_i
- case
- assign $3\reg$next[3:0]$11600 $2\reg$next[3:0]$11599
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\reg$next[3:0]$11601 4'0000
- case
- assign $4\reg$next[3:0]$11601 $3\reg$next[3:0]$11600
- end
- sync always
- update \reg$next $0\reg$next[3:0]$11597
- end
- attribute \src "libresoc.v:183563.3-183602.6"
- process $proc$libresoc.v:183563$11602
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\src15__data_o$next[3:0]$11603 $6\src15__data_o$next[3:0]$11609
- attribute \src "libresoc.v:183564.5-183564.29"
- switch \initial
- attribute \src "libresoc.v:183564.9-183564.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src15__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\src15__data_o$next[3:0]$11604 $5\src15__data_o$next[3:0]$11608
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest15__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\src15__data_o$next[3:0]$11605 \dest15__data_i
- case
- assign $2\src15__data_o$next[3:0]$11605 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest25__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\src15__data_o$next[3:0]$11606 \dest25__data_i
- case
- assign $3\src15__data_o$next[3:0]$11606 $2\src15__data_o$next[3:0]$11605
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w5__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\src15__data_o$next[3:0]$11607 \w5__data_i
- case
- assign $4\src15__data_o$next[3:0]$11607 $3\src15__data_o$next[3:0]$11606
+ assign $4\src25__data_o$next[3:0]$11454 $3\src25__data_o$next[3:0]$11453
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src15__data_o$next[3:0]$11608 \reg
+ assign $5\src25__data_o$next[3:0]$11455 \reg
case
- assign $5\src15__data_o$next[3:0]$11608 $4\src15__data_o$next[3:0]$11607
+ assign $5\src25__data_o$next[3:0]$11455 $4\src25__data_o$next[3:0]$11454
end
case
- assign $1\src15__data_o$next[3:0]$11604 4'0000
+ assign $1\src25__data_o$next[3:0]$11451 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src15__data_o$next[3:0]$11609 4'0000
+ assign $6\src25__data_o$next[3:0]$11456 4'0000
case
- assign $6\src15__data_o$next[3:0]$11609 $1\src15__data_o$next[3:0]$11604
+ assign $6\src25__data_o$next[3:0]$11456 $1\src25__data_o$next[3:0]$11451
end
sync always
- update \src15__data_o$next $0\src15__data_o$next[3:0]$11603
+ update \src25__data_o$next $0\src25__data_o$next[3:0]$11450
end
- attribute \src "libresoc.v:183603.3-183632.6"
- process $proc$libresoc.v:183603$11610
+ attribute \src "libresoc.v:182715.3-182744.6"
+ process $proc$libresoc.v:182715$11457
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11611 $1\wr_detect$4[0:0]$11612
- attribute \src "libresoc.v:183604.5-183604.29"
+ assign $0\wr_detect$4[0:0]$11458 $1\wr_detect$4[0:0]$11459
+ attribute \src "libresoc.v:182716.5-182716.29"
switch \initial
- attribute \src "libresoc.v:183604.9-183604.17"
+ attribute \src "libresoc.v:182716.9-182716.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src15__ren
+ switch \src25__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11612 $4\wr_detect$4[0:0]$11615
+ assign $1\wr_detect$4[0:0]$11459 $4\wr_detect$4[0:0]$11462
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11613 1'1
+ assign $2\wr_detect$4[0:0]$11460 1'1
case
- assign $2\wr_detect$4[0:0]$11613 1'0
+ assign $2\wr_detect$4[0:0]$11460 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11614 1'1
+ assign $3\wr_detect$4[0:0]$11461 1'1
case
- assign $3\wr_detect$4[0:0]$11614 $2\wr_detect$4[0:0]$11613
+ assign $3\wr_detect$4[0:0]$11461 $2\wr_detect$4[0:0]$11460
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11615 1'1
+ assign $4\wr_detect$4[0:0]$11462 1'1
case
- assign $4\wr_detect$4[0:0]$11615 $3\wr_detect$4[0:0]$11614
+ assign $4\wr_detect$4[0:0]$11462 $3\wr_detect$4[0:0]$11461
end
case
- assign $1\wr_detect$4[0:0]$11612 1'0
+ assign $1\wr_detect$4[0:0]$11459 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11611
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11458
end
- attribute \src "libresoc.v:183633.3-183672.6"
- process $proc$libresoc.v:183633$11616
+ attribute \src "libresoc.v:182745.3-182784.6"
+ process $proc$libresoc.v:182745$11463
assign { } { }
assign { } { }
assign { } { }
- assign $0\src25__data_o$next[3:0]$11617 $6\src25__data_o$next[3:0]$11623
- attribute \src "libresoc.v:183634.5-183634.29"
+ assign $0\src35__data_o$next[3:0]$11464 $6\src35__data_o$next[3:0]$11470
+ attribute \src "libresoc.v:182746.5-182746.29"
switch \initial
- attribute \src "libresoc.v:183634.9-183634.17"
+ attribute \src "libresoc.v:182746.9-182746.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src25__ren
+ switch \src35__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src25__data_o$next[3:0]$11618 $5\src25__data_o$next[3:0]$11622
+ assign $1\src35__data_o$next[3:0]$11465 $5\src35__data_o$next[3:0]$11469
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src25__data_o$next[3:0]$11619 \dest15__data_i
+ assign $2\src35__data_o$next[3:0]$11466 \dest15__data_i
case
- assign $2\src25__data_o$next[3:0]$11619 4'0000
+ assign $2\src35__data_o$next[3:0]$11466 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src25__data_o$next[3:0]$11620 \dest25__data_i
+ assign $3\src35__data_o$next[3:0]$11467 \dest25__data_i
case
- assign $3\src25__data_o$next[3:0]$11620 $2\src25__data_o$next[3:0]$11619
+ assign $3\src35__data_o$next[3:0]$11467 $2\src35__data_o$next[3:0]$11466
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src25__data_o$next[3:0]$11621 \w5__data_i
+ assign $4\src35__data_o$next[3:0]$11468 \w5__data_i
case
- assign $4\src25__data_o$next[3:0]$11621 $3\src25__data_o$next[3:0]$11620
+ assign $4\src35__data_o$next[3:0]$11468 $3\src35__data_o$next[3:0]$11467
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src25__data_o$next[3:0]$11622 \reg
+ assign $5\src35__data_o$next[3:0]$11469 \reg
case
- assign $5\src25__data_o$next[3:0]$11622 $4\src25__data_o$next[3:0]$11621
+ assign $5\src35__data_o$next[3:0]$11469 $4\src35__data_o$next[3:0]$11468
end
case
- assign $1\src25__data_o$next[3:0]$11618 4'0000
+ assign $1\src35__data_o$next[3:0]$11465 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src25__data_o$next[3:0]$11623 4'0000
+ assign $6\src35__data_o$next[3:0]$11470 4'0000
case
- assign $6\src25__data_o$next[3:0]$11623 $1\src25__data_o$next[3:0]$11618
+ assign $6\src35__data_o$next[3:0]$11470 $1\src35__data_o$next[3:0]$11465
end
sync always
- update \src25__data_o$next $0\src25__data_o$next[3:0]$11617
+ update \src35__data_o$next $0\src35__data_o$next[3:0]$11464
end
- attribute \src "libresoc.v:183673.3-183702.6"
- process $proc$libresoc.v:183673$11624
+ attribute \src "libresoc.v:182785.3-182814.6"
+ process $proc$libresoc.v:182785$11471
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11625 $1\wr_detect$7[0:0]$11626
- attribute \src "libresoc.v:183674.5-183674.29"
+ assign $0\wr_detect$7[0:0]$11472 $1\wr_detect$7[0:0]$11473
+ attribute \src "libresoc.v:182786.5-182786.29"
switch \initial
- attribute \src "libresoc.v:183674.9-183674.17"
+ attribute \src "libresoc.v:182786.9-182786.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src25__ren
+ switch \src35__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11626 $4\wr_detect$7[0:0]$11629
+ assign $1\wr_detect$7[0:0]$11473 $4\wr_detect$7[0:0]$11476
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11627 1'1
+ assign $2\wr_detect$7[0:0]$11474 1'1
case
- assign $2\wr_detect$7[0:0]$11627 1'0
+ assign $2\wr_detect$7[0:0]$11474 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11628 1'1
+ assign $3\wr_detect$7[0:0]$11475 1'1
case
- assign $3\wr_detect$7[0:0]$11628 $2\wr_detect$7[0:0]$11627
+ assign $3\wr_detect$7[0:0]$11475 $2\wr_detect$7[0:0]$11474
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11629 1'1
+ assign $4\wr_detect$7[0:0]$11476 1'1
case
- assign $4\wr_detect$7[0:0]$11629 $3\wr_detect$7[0:0]$11628
+ assign $4\wr_detect$7[0:0]$11476 $3\wr_detect$7[0:0]$11475
end
case
- assign $1\wr_detect$7[0:0]$11626 1'0
+ assign $1\wr_detect$7[0:0]$11473 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11625
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11472
end
- attribute \src "libresoc.v:183703.3-183742.6"
- process $proc$libresoc.v:183703$11630
+ attribute \src "libresoc.v:182815.3-182854.6"
+ process $proc$libresoc.v:182815$11477
assign { } { }
assign { } { }
assign { } { }
- assign $0\src35__data_o$next[3:0]$11631 $6\src35__data_o$next[3:0]$11637
- attribute \src "libresoc.v:183704.5-183704.29"
+ assign $0\r5__data_o$next[3:0]$11478 $6\r5__data_o$next[3:0]$11484
+ attribute \src "libresoc.v:182816.5-182816.29"
switch \initial
- attribute \src "libresoc.v:183704.9-183704.17"
+ attribute \src "libresoc.v:182816.9-182816.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src35__ren
+ switch \r5__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src35__data_o$next[3:0]$11632 $5\src35__data_o$next[3:0]$11636
+ assign $1\r5__data_o$next[3:0]$11479 $5\r5__data_o$next[3:0]$11483
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src35__data_o$next[3:0]$11633 \dest15__data_i
+ assign $2\r5__data_o$next[3:0]$11480 \dest15__data_i
case
- assign $2\src35__data_o$next[3:0]$11633 4'0000
+ assign $2\r5__data_o$next[3:0]$11480 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src35__data_o$next[3:0]$11634 \dest25__data_i
+ assign $3\r5__data_o$next[3:0]$11481 \dest25__data_i
case
- assign $3\src35__data_o$next[3:0]$11634 $2\src35__data_o$next[3:0]$11633
+ assign $3\r5__data_o$next[3:0]$11481 $2\r5__data_o$next[3:0]$11480
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src35__data_o$next[3:0]$11635 \w5__data_i
+ assign $4\r5__data_o$next[3:0]$11482 \w5__data_i
case
- assign $4\src35__data_o$next[3:0]$11635 $3\src35__data_o$next[3:0]$11634
+ assign $4\r5__data_o$next[3:0]$11482 $3\r5__data_o$next[3:0]$11481
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src35__data_o$next[3:0]$11636 \reg
+ assign $5\r5__data_o$next[3:0]$11483 \reg
case
- assign $5\src35__data_o$next[3:0]$11636 $4\src35__data_o$next[3:0]$11635
+ assign $5\r5__data_o$next[3:0]$11483 $4\r5__data_o$next[3:0]$11482
end
case
- assign $1\src35__data_o$next[3:0]$11632 4'0000
+ assign $1\r5__data_o$next[3:0]$11479 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src35__data_o$next[3:0]$11637 4'0000
+ assign $6\r5__data_o$next[3:0]$11484 4'0000
case
- assign $6\src35__data_o$next[3:0]$11637 $1\src35__data_o$next[3:0]$11632
+ assign $6\r5__data_o$next[3:0]$11484 $1\r5__data_o$next[3:0]$11479
end
sync always
- update \src35__data_o$next $0\src35__data_o$next[3:0]$11631
+ update \r5__data_o$next $0\r5__data_o$next[3:0]$11478
end
- attribute \src "libresoc.v:183743.3-183772.6"
- process $proc$libresoc.v:183743$11638
+ attribute \src "libresoc.v:182855.3-182884.6"
+ process $proc$libresoc.v:182855$11485
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11639 $1\wr_detect$10[0:0]$11640
- attribute \src "libresoc.v:183744.5-183744.29"
+ assign $0\wr_detect$10[0:0]$11486 $1\wr_detect$10[0:0]$11487
+ attribute \src "libresoc.v:182856.5-182856.29"
switch \initial
- attribute \src "libresoc.v:183744.9-183744.17"
+ attribute \src "libresoc.v:182856.9-182856.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src35__ren
+ switch \r5__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11640 $4\wr_detect$10[0:0]$11643
+ assign $1\wr_detect$10[0:0]$11487 $4\wr_detect$10[0:0]$11490
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11641 1'1
+ assign $2\wr_detect$10[0:0]$11488 1'1
case
- assign $2\wr_detect$10[0:0]$11641 1'0
+ assign $2\wr_detect$10[0:0]$11488 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11642 1'1
+ assign $3\wr_detect$10[0:0]$11489 1'1
case
- assign $3\wr_detect$10[0:0]$11642 $2\wr_detect$10[0:0]$11641
+ assign $3\wr_detect$10[0:0]$11489 $2\wr_detect$10[0:0]$11488
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11643 1'1
+ assign $4\wr_detect$10[0:0]$11490 1'1
case
- assign $4\wr_detect$10[0:0]$11643 $3\wr_detect$10[0:0]$11642
+ assign $4\wr_detect$10[0:0]$11490 $3\wr_detect$10[0:0]$11489
end
case
- assign $1\wr_detect$10[0:0]$11640 1'0
+ assign $1\wr_detect$10[0:0]$11487 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11639
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11486
end
- attribute \src "libresoc.v:183773.3-183812.6"
- process $proc$libresoc.v:183773$11644
+ attribute \src "libresoc.v:182885.3-182924.6"
+ process $proc$libresoc.v:182885$11491
assign { } { }
assign { } { }
assign { } { }
- assign $0\r5__data_o$next[3:0]$11645 $6\r5__data_o$next[3:0]$11651
- attribute \src "libresoc.v:183774.5-183774.29"
+ assign $0\r25__data_o$next[3:0]$11492 $6\r25__data_o$next[3:0]$11498
+ attribute \src "libresoc.v:182886.5-182886.29"
switch \initial
- attribute \src "libresoc.v:183774.9-183774.17"
+ attribute \src "libresoc.v:182886.9-182886.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r5__ren
+ switch \r25__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r5__data_o$next[3:0]$11646 $5\r5__data_o$next[3:0]$11650
+ assign $1\r25__data_o$next[3:0]$11493 $5\r25__data_o$next[3:0]$11497
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r5__data_o$next[3:0]$11647 \dest15__data_i
+ assign $2\r25__data_o$next[3:0]$11494 \dest15__data_i
case
- assign $2\r5__data_o$next[3:0]$11647 4'0000
+ assign $2\r25__data_o$next[3:0]$11494 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r5__data_o$next[3:0]$11648 \dest25__data_i
+ assign $3\r25__data_o$next[3:0]$11495 \dest25__data_i
case
- assign $3\r5__data_o$next[3:0]$11648 $2\r5__data_o$next[3:0]$11647
+ assign $3\r25__data_o$next[3:0]$11495 $2\r25__data_o$next[3:0]$11494
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r5__data_o$next[3:0]$11649 \w5__data_i
+ assign $4\r25__data_o$next[3:0]$11496 \w5__data_i
case
- assign $4\r5__data_o$next[3:0]$11649 $3\r5__data_o$next[3:0]$11648
+ assign $4\r25__data_o$next[3:0]$11496 $3\r25__data_o$next[3:0]$11495
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r5__data_o$next[3:0]$11650 \reg
+ assign $5\r25__data_o$next[3:0]$11497 \reg
case
- assign $5\r5__data_o$next[3:0]$11650 $4\r5__data_o$next[3:0]$11649
+ assign $5\r25__data_o$next[3:0]$11497 $4\r25__data_o$next[3:0]$11496
end
case
- assign $1\r5__data_o$next[3:0]$11646 4'0000
+ assign $1\r25__data_o$next[3:0]$11493 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r5__data_o$next[3:0]$11651 4'0000
+ assign $6\r25__data_o$next[3:0]$11498 4'0000
case
- assign $6\r5__data_o$next[3:0]$11651 $1\r5__data_o$next[3:0]$11646
+ assign $6\r25__data_o$next[3:0]$11498 $1\r25__data_o$next[3:0]$11493
end
sync always
- update \r5__data_o$next $0\r5__data_o$next[3:0]$11645
+ update \r25__data_o$next $0\r25__data_o$next[3:0]$11492
end
- attribute \src "libresoc.v:183813.3-183842.6"
- process $proc$libresoc.v:183813$11652
+ attribute \src "libresoc.v:182925.3-182954.6"
+ process $proc$libresoc.v:182925$11499
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11653 $1\wr_detect$13[0:0]$11654
- attribute \src "libresoc.v:183814.5-183814.29"
+ assign $0\wr_detect$13[0:0]$11500 $1\wr_detect$13[0:0]$11501
+ attribute \src "libresoc.v:182926.5-182926.29"
switch \initial
- attribute \src "libresoc.v:183814.9-183814.17"
+ attribute \src "libresoc.v:182926.9-182926.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r5__ren
+ switch \r25__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11654 $4\wr_detect$13[0:0]$11657
+ assign $1\wr_detect$13[0:0]$11501 $4\wr_detect$13[0:0]$11504
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11655 1'1
+ assign $2\wr_detect$13[0:0]$11502 1'1
case
- assign $2\wr_detect$13[0:0]$11655 1'0
+ assign $2\wr_detect$13[0:0]$11502 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11656 1'1
+ assign $3\wr_detect$13[0:0]$11503 1'1
case
- assign $3\wr_detect$13[0:0]$11656 $2\wr_detect$13[0:0]$11655
+ assign $3\wr_detect$13[0:0]$11503 $2\wr_detect$13[0:0]$11502
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11657 1'1
+ assign $4\wr_detect$13[0:0]$11504 1'1
case
- assign $4\wr_detect$13[0:0]$11657 $3\wr_detect$13[0:0]$11656
+ assign $4\wr_detect$13[0:0]$11504 $3\wr_detect$13[0:0]$11503
end
case
- assign $1\wr_detect$13[0:0]$11654 1'0
+ assign $1\wr_detect$13[0:0]$11501 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11653
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11500
end
- connect \$9 $not$libresoc.v:183376$11560_Y
- connect \$12 $not$libresoc.v:183377$11561_Y
- connect \$15 $not$libresoc.v:183378$11562_Y
- connect \$1 $not$libresoc.v:183379$11563_Y
- connect \$3 $not$libresoc.v:183380$11564_Y
- connect \$6 $not$libresoc.v:183381$11565_Y
+ connect \$9 $not$libresoc.v:182561$11423_Y
+ connect \$12 $not$libresoc.v:182562$11424_Y
+ connect \$1 $not$libresoc.v:182563$11425_Y
+ connect \$3 $not$libresoc.v:182564$11426_Y
+ connect \$6 $not$libresoc.v:182565$11427_Y
end
-attribute \src "libresoc.v:183847.1-184402.10"
+attribute \src "libresoc.v:182959.1-183430.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6"
attribute \generator "nMigen"
module \reg_6
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $0\cr_pred6__data_o$next[3:0]$11680
- attribute \src "libresoc.v:183953.3-183954.49"
- wire width 4 $0\cr_pred6__data_o[3:0]
- attribute \src "libresoc.v:183848.7-183848.20"
+ attribute \src "libresoc.v:182960.7-182960.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $0\r26__data_o$next[3:0]$11689
- attribute \src "libresoc.v:183943.3-183944.39"
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $0\r26__data_o$next[3:0]$11581
+ attribute \src "libresoc.v:183043.3-183044.39"
wire width 4 $0\r26__data_o[3:0]
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $0\r6__data_o$next[3:0]$11751
- attribute \src "libresoc.v:183945.3-183946.37"
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $0\r6__data_o$next[3:0]$11567
+ attribute \src "libresoc.v:183045.3-183046.37"
wire width 4 $0\r6__data_o[3:0]
- attribute \src "libresoc.v:184095.3-184121.6"
- wire width 4 $0\reg$next[3:0]$11703
- attribute \src "libresoc.v:183941.3-183942.25"
+ attribute \src "libresoc.v:183123.3-183149.6"
+ wire width 4 $0\reg$next[3:0]$11533
+ attribute \src "libresoc.v:183041.3-183042.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $0\src16__data_o$next[3:0]$11709
- attribute \src "libresoc.v:183951.3-183952.43"
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $0\src16__data_o$next[3:0]$11524
+ attribute \src "libresoc.v:183051.3-183052.43"
wire width 4 $0\src16__data_o[3:0]
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $0\src26__data_o$next[3:0]$11723
- attribute \src "libresoc.v:183949.3-183950.43"
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $0\src26__data_o$next[3:0]$11539
+ attribute \src "libresoc.v:183049.3-183050.43"
wire width 4 $0\src26__data_o[3:0]
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $0\src36__data_o$next[3:0]$11737
- attribute \src "libresoc.v:183947.3-183948.43"
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $0\src36__data_o$next[3:0]$11553
+ attribute \src "libresoc.v:183047.3-183048.43"
wire width 4 $0\src36__data_o[3:0]
- attribute \src "libresoc.v:184302.3-184331.6"
- wire $0\wr_detect$10[0:0]$11745
- attribute \src "libresoc.v:184372.3-184401.6"
- wire $0\wr_detect$13[0:0]$11759
- attribute \src "libresoc.v:184065.3-184094.6"
- wire $0\wr_detect$16[0:0]$11697
- attribute \src "libresoc.v:184162.3-184191.6"
- wire $0\wr_detect$4[0:0]$11717
- attribute \src "libresoc.v:184232.3-184261.6"
- wire $0\wr_detect$7[0:0]$11731
- attribute \src "libresoc.v:183995.3-184024.6"
+ attribute \src "libresoc.v:183330.3-183359.6"
+ wire $0\wr_detect$10[0:0]$11575
+ attribute \src "libresoc.v:183400.3-183429.6"
+ wire $0\wr_detect$13[0:0]$11589
+ attribute \src "libresoc.v:183190.3-183219.6"
+ wire $0\wr_detect$4[0:0]$11547
+ attribute \src "libresoc.v:183260.3-183289.6"
+ wire $0\wr_detect$7[0:0]$11561
+ attribute \src "libresoc.v:183093.3-183122.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $1\cr_pred6__data_o$next[3:0]$11681
- attribute \src "libresoc.v:183867.13-183867.36"
- wire width 4 $1\cr_pred6__data_o[3:0]
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $1\r26__data_o$next[3:0]$11690
- attribute \src "libresoc.v:183882.13-183882.31"
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $1\r26__data_o$next[3:0]$11582
+ attribute \src "libresoc.v:182985.13-182985.31"
wire width 4 $1\r26__data_o[3:0]
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $1\r6__data_o$next[3:0]$11752
- attribute \src "libresoc.v:183889.13-183889.30"
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $1\r6__data_o$next[3:0]$11568
+ attribute \src "libresoc.v:182992.13-182992.30"
wire width 4 $1\r6__data_o[3:0]
- attribute \src "libresoc.v:184095.3-184121.6"
- wire width 4 $1\reg$next[3:0]$11704
- attribute \src "libresoc.v:183895.13-183895.25"
+ attribute \src "libresoc.v:183123.3-183149.6"
+ wire width 4 $1\reg$next[3:0]$11534
+ attribute \src "libresoc.v:182998.13-182998.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $1\src16__data_o$next[3:0]$11710
- attribute \src "libresoc.v:183900.13-183900.33"
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $1\src16__data_o$next[3:0]$11525
+ attribute \src "libresoc.v:183003.13-183003.33"
wire width 4 $1\src16__data_o[3:0]
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $1\src26__data_o$next[3:0]$11724
- attribute \src "libresoc.v:183907.13-183907.33"
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $1\src26__data_o$next[3:0]$11540
+ attribute \src "libresoc.v:183010.13-183010.33"
wire width 4 $1\src26__data_o[3:0]
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $1\src36__data_o$next[3:0]$11738
- attribute \src "libresoc.v:183914.13-183914.33"
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $1\src36__data_o$next[3:0]$11554
+ attribute \src "libresoc.v:183017.13-183017.33"
wire width 4 $1\src36__data_o[3:0]
- attribute \src "libresoc.v:184302.3-184331.6"
- wire $1\wr_detect$10[0:0]$11746
- attribute \src "libresoc.v:184372.3-184401.6"
- wire $1\wr_detect$13[0:0]$11760
- attribute \src "libresoc.v:184065.3-184094.6"
- wire $1\wr_detect$16[0:0]$11698
- attribute \src "libresoc.v:184162.3-184191.6"
- wire $1\wr_detect$4[0:0]$11718
- attribute \src "libresoc.v:184232.3-184261.6"
- wire $1\wr_detect$7[0:0]$11732
- attribute \src "libresoc.v:183995.3-184024.6"
+ attribute \src "libresoc.v:183330.3-183359.6"
+ wire $1\wr_detect$10[0:0]$11576
+ attribute \src "libresoc.v:183400.3-183429.6"
+ wire $1\wr_detect$13[0:0]$11590
+ attribute \src "libresoc.v:183190.3-183219.6"
+ wire $1\wr_detect$4[0:0]$11548
+ attribute \src "libresoc.v:183260.3-183289.6"
+ wire $1\wr_detect$7[0:0]$11562
+ attribute \src "libresoc.v:183093.3-183122.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $2\cr_pred6__data_o$next[3:0]$11682
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $2\r26__data_o$next[3:0]$11691
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $2\r6__data_o$next[3:0]$11753
- attribute \src "libresoc.v:184095.3-184121.6"
- wire width 4 $2\reg$next[3:0]$11705
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $2\src16__data_o$next[3:0]$11711
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $2\src26__data_o$next[3:0]$11725
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $2\src36__data_o$next[3:0]$11739
- attribute \src "libresoc.v:184302.3-184331.6"
- wire $2\wr_detect$10[0:0]$11747
- attribute \src "libresoc.v:184372.3-184401.6"
- wire $2\wr_detect$13[0:0]$11761
- attribute \src "libresoc.v:184065.3-184094.6"
- wire $2\wr_detect$16[0:0]$11699
- attribute \src "libresoc.v:184162.3-184191.6"
- wire $2\wr_detect$4[0:0]$11719
- attribute \src "libresoc.v:184232.3-184261.6"
- wire $2\wr_detect$7[0:0]$11733
- attribute \src "libresoc.v:183995.3-184024.6"
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $2\r26__data_o$next[3:0]$11583
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $2\r6__data_o$next[3:0]$11569
+ attribute \src "libresoc.v:183123.3-183149.6"
+ wire width 4 $2\reg$next[3:0]$11535
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $2\src16__data_o$next[3:0]$11526
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $2\src26__data_o$next[3:0]$11541
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $2\src36__data_o$next[3:0]$11555
+ attribute \src "libresoc.v:183330.3-183359.6"
+ wire $2\wr_detect$10[0:0]$11577
+ attribute \src "libresoc.v:183400.3-183429.6"
+ wire $2\wr_detect$13[0:0]$11591
+ attribute \src "libresoc.v:183190.3-183219.6"
+ wire $2\wr_detect$4[0:0]$11549
+ attribute \src "libresoc.v:183260.3-183289.6"
+ wire $2\wr_detect$7[0:0]$11563
+ attribute \src "libresoc.v:183093.3-183122.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $3\cr_pred6__data_o$next[3:0]$11683
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $3\r26__data_o$next[3:0]$11692
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $3\r6__data_o$next[3:0]$11754
- attribute \src "libresoc.v:184095.3-184121.6"
- wire width 4 $3\reg$next[3:0]$11706
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $3\src16__data_o$next[3:0]$11712
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $3\src26__data_o$next[3:0]$11726
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $3\src36__data_o$next[3:0]$11740
- attribute \src "libresoc.v:184302.3-184331.6"
- wire $3\wr_detect$10[0:0]$11748
- attribute \src "libresoc.v:184372.3-184401.6"
- wire $3\wr_detect$13[0:0]$11762
- attribute \src "libresoc.v:184065.3-184094.6"
- wire $3\wr_detect$16[0:0]$11700
- attribute \src "libresoc.v:184162.3-184191.6"
- wire $3\wr_detect$4[0:0]$11720
- attribute \src "libresoc.v:184232.3-184261.6"
- wire $3\wr_detect$7[0:0]$11734
- attribute \src "libresoc.v:183995.3-184024.6"
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $3\r26__data_o$next[3:0]$11584
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $3\r6__data_o$next[3:0]$11570
+ attribute \src "libresoc.v:183123.3-183149.6"
+ wire width 4 $3\reg$next[3:0]$11536
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $3\src16__data_o$next[3:0]$11527
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $3\src26__data_o$next[3:0]$11542
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $3\src36__data_o$next[3:0]$11556
+ attribute \src "libresoc.v:183330.3-183359.6"
+ wire $3\wr_detect$10[0:0]$11578
+ attribute \src "libresoc.v:183400.3-183429.6"
+ wire $3\wr_detect$13[0:0]$11592
+ attribute \src "libresoc.v:183190.3-183219.6"
+ wire $3\wr_detect$4[0:0]$11550
+ attribute \src "libresoc.v:183260.3-183289.6"
+ wire $3\wr_detect$7[0:0]$11564
+ attribute \src "libresoc.v:183093.3-183122.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $4\cr_pred6__data_o$next[3:0]$11684
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $4\r26__data_o$next[3:0]$11693
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $4\r6__data_o$next[3:0]$11755
- attribute \src "libresoc.v:184095.3-184121.6"
- wire width 4 $4\reg$next[3:0]$11707
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $4\src16__data_o$next[3:0]$11713
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $4\src26__data_o$next[3:0]$11727
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $4\src36__data_o$next[3:0]$11741
- attribute \src "libresoc.v:184302.3-184331.6"
- wire $4\wr_detect$10[0:0]$11749
- attribute \src "libresoc.v:184372.3-184401.6"
- wire $4\wr_detect$13[0:0]$11763
- attribute \src "libresoc.v:184065.3-184094.6"
- wire $4\wr_detect$16[0:0]$11701
- attribute \src "libresoc.v:184162.3-184191.6"
- wire $4\wr_detect$4[0:0]$11721
- attribute \src "libresoc.v:184232.3-184261.6"
- wire $4\wr_detect$7[0:0]$11735
- attribute \src "libresoc.v:183995.3-184024.6"
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $4\r26__data_o$next[3:0]$11585
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $4\r6__data_o$next[3:0]$11571
+ attribute \src "libresoc.v:183123.3-183149.6"
+ wire width 4 $4\reg$next[3:0]$11537
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $4\src16__data_o$next[3:0]$11528
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $4\src26__data_o$next[3:0]$11543
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $4\src36__data_o$next[3:0]$11557
+ attribute \src "libresoc.v:183330.3-183359.6"
+ wire $4\wr_detect$10[0:0]$11579
+ attribute \src "libresoc.v:183400.3-183429.6"
+ wire $4\wr_detect$13[0:0]$11593
+ attribute \src "libresoc.v:183190.3-183219.6"
+ wire $4\wr_detect$4[0:0]$11551
+ attribute \src "libresoc.v:183260.3-183289.6"
+ wire $4\wr_detect$7[0:0]$11565
+ attribute \src "libresoc.v:183093.3-183122.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $5\cr_pred6__data_o$next[3:0]$11685
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $5\r26__data_o$next[3:0]$11694
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $5\r6__data_o$next[3:0]$11756
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $5\src16__data_o$next[3:0]$11714
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $5\src26__data_o$next[3:0]$11728
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $5\src36__data_o$next[3:0]$11742
- attribute \src "libresoc.v:183955.3-183994.6"
- wire width 4 $6\cr_pred6__data_o$next[3:0]$11686
- attribute \src "libresoc.v:184025.3-184064.6"
- wire width 4 $6\r26__data_o$next[3:0]$11695
- attribute \src "libresoc.v:184332.3-184371.6"
- wire width 4 $6\r6__data_o$next[3:0]$11757
- attribute \src "libresoc.v:184122.3-184161.6"
- wire width 4 $6\src16__data_o$next[3:0]$11715
- attribute \src "libresoc.v:184192.3-184231.6"
- wire width 4 $6\src26__data_o$next[3:0]$11729
- attribute \src "libresoc.v:184262.3-184301.6"
- wire width 4 $6\src36__data_o$next[3:0]$11743
- attribute \src "libresoc.v:183935.17-183935.104"
- wire $not$libresoc.v:183935$11666_Y
- attribute \src "libresoc.v:183936.18-183936.105"
- wire $not$libresoc.v:183936$11667_Y
- attribute \src "libresoc.v:183937.18-183937.105"
- wire $not$libresoc.v:183937$11668_Y
- attribute \src "libresoc.v:183938.17-183938.100"
- wire $not$libresoc.v:183938$11669_Y
- attribute \src "libresoc.v:183939.17-183939.103"
- wire $not$libresoc.v:183939$11670_Y
- attribute \src "libresoc.v:183940.17-183940.103"
- wire $not$libresoc.v:183940$11671_Y
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $5\r26__data_o$next[3:0]$11586
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $5\r6__data_o$next[3:0]$11572
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $5\src16__data_o$next[3:0]$11529
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $5\src26__data_o$next[3:0]$11544
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $5\src36__data_o$next[3:0]$11558
+ attribute \src "libresoc.v:183360.3-183399.6"
+ wire width 4 $6\r26__data_o$next[3:0]$11587
+ attribute \src "libresoc.v:183290.3-183329.6"
+ wire width 4 $6\r6__data_o$next[3:0]$11573
+ attribute \src "libresoc.v:183053.3-183092.6"
+ wire width 4 $6\src16__data_o$next[3:0]$11530
+ attribute \src "libresoc.v:183150.3-183189.6"
+ wire width 4 $6\src26__data_o$next[3:0]$11545
+ attribute \src "libresoc.v:183220.3-183259.6"
+ wire width 4 $6\src36__data_o$next[3:0]$11559
+ attribute \src "libresoc.v:183036.17-183036.104"
+ wire $not$libresoc.v:183036$11512_Y
+ attribute \src "libresoc.v:183037.18-183037.105"
+ wire $not$libresoc.v:183037$11513_Y
+ attribute \src "libresoc.v:183038.17-183038.100"
+ wire $not$libresoc.v:183038$11514_Y
+ attribute \src "libresoc.v:183039.17-183039.103"
+ wire $not$libresoc.v:183039$11515_Y
+ attribute \src "libresoc.v:183040.17-183040.103"
+ wire $not$libresoc.v:183040$11516_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred6__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred6__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred6__ren
+ wire width 4 input 9 \dest16__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest16__data_i
+ wire input 8 \dest16__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest16__wen
+ wire width 4 input 11 \dest26__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest26__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest26__wen
- attribute \src "libresoc.v:183848.7-183848.15"
+ wire input 10 \dest26__wen
+ attribute \src "libresoc.v:182960.7-182960.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r26__data_o
+ wire width 4 output 14 \r26__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r26__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r26__ren
+ wire input 15 \r26__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r6__data_o
+ wire width 4 output 12 \r6__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r6__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r6__ren
+ wire input 13 \r6__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src16__data_o
+ wire width 4 output 3 \src16__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src16__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src16__ren
+ wire input 2 \src16__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src26__data_o
+ wire width 4 output 5 \src26__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src26__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src26__ren
+ wire input 4 \src26__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src36__data_o
+ wire width 4 output 7 \src36__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src36__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src36__ren
+ wire input 6 \src36__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w6__data_i
+ wire width 4 input 16 \w6__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w6__wen
+ wire input 17 \w6__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183935$11666
+ cell $not $not$libresoc.v:183036$11512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:183935$11666_Y
+ connect \Y $not$libresoc.v:183036$11512_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183936$11667
+ cell $not $not$libresoc.v:183037$11513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:183936$11667_Y
+ connect \Y $not$libresoc.v:183037$11513_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183937$11668
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:183937$11668_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183938$11669
+ cell $not $not$libresoc.v:183038$11514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:183938$11669_Y
+ connect \Y $not$libresoc.v:183038$11514_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183939$11670
+ cell $not $not$libresoc.v:183039$11515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:183939$11670_Y
+ connect \Y $not$libresoc.v:183039$11515_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:183940$11671
+ cell $not $not$libresoc.v:183040$11516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:183940$11671_Y
+ connect \Y $not$libresoc.v:183040$11516_Y
end
- attribute \src "libresoc.v:183848.7-183848.20"
- process $proc$libresoc.v:183848$11764
+ attribute \src "libresoc.v:182960.7-182960.20"
+ process $proc$libresoc.v:182960$11594
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183867.13-183867.36"
- process $proc$libresoc.v:183867$11765
- assign { } { }
- assign $1\cr_pred6__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred6__data_o $1\cr_pred6__data_o[3:0]
- end
- attribute \src "libresoc.v:183882.13-183882.31"
- process $proc$libresoc.v:183882$11766
+ attribute \src "libresoc.v:182985.13-182985.31"
+ process $proc$libresoc.v:182985$11595
assign { } { }
assign $1\r26__data_o[3:0] 4'0000
sync always
sync init
update \r26__data_o $1\r26__data_o[3:0]
end
- attribute \src "libresoc.v:183889.13-183889.30"
- process $proc$libresoc.v:183889$11767
+ attribute \src "libresoc.v:182992.13-182992.30"
+ process $proc$libresoc.v:182992$11596
assign { } { }
assign $1\r6__data_o[3:0] 4'0000
sync always
sync init
update \r6__data_o $1\r6__data_o[3:0]
end
- attribute \src "libresoc.v:183895.13-183895.25"
- process $proc$libresoc.v:183895$11768
+ attribute \src "libresoc.v:182998.13-182998.25"
+ process $proc$libresoc.v:182998$11597
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:183900.13-183900.33"
- process $proc$libresoc.v:183900$11769
+ attribute \src "libresoc.v:183003.13-183003.33"
+ process $proc$libresoc.v:183003$11598
assign { } { }
assign $1\src16__data_o[3:0] 4'0000
sync always
sync init
update \src16__data_o $1\src16__data_o[3:0]
end
- attribute \src "libresoc.v:183907.13-183907.33"
- process $proc$libresoc.v:183907$11770
+ attribute \src "libresoc.v:183010.13-183010.33"
+ process $proc$libresoc.v:183010$11599
assign { } { }
assign $1\src26__data_o[3:0] 4'0000
sync always
sync init
update \src26__data_o $1\src26__data_o[3:0]
end
- attribute \src "libresoc.v:183914.13-183914.33"
- process $proc$libresoc.v:183914$11771
+ attribute \src "libresoc.v:183017.13-183017.33"
+ process $proc$libresoc.v:183017$11600
assign { } { }
assign $1\src36__data_o[3:0] 4'0000
sync always
sync init
update \src36__data_o $1\src36__data_o[3:0]
end
- attribute \src "libresoc.v:183941.3-183942.25"
- process $proc$libresoc.v:183941$11672
+ attribute \src "libresoc.v:183041.3-183042.25"
+ process $proc$libresoc.v:183041$11517
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:183943.3-183944.39"
- process $proc$libresoc.v:183943$11673
+ attribute \src "libresoc.v:183043.3-183044.39"
+ process $proc$libresoc.v:183043$11518
assign { } { }
assign $0\r26__data_o[3:0] \r26__data_o$next
sync posedge \coresync_clk
update \r26__data_o $0\r26__data_o[3:0]
end
- attribute \src "libresoc.v:183945.3-183946.37"
- process $proc$libresoc.v:183945$11674
+ attribute \src "libresoc.v:183045.3-183046.37"
+ process $proc$libresoc.v:183045$11519
assign { } { }
assign $0\r6__data_o[3:0] \r6__data_o$next
sync posedge \coresync_clk
update \r6__data_o $0\r6__data_o[3:0]
end
- attribute \src "libresoc.v:183947.3-183948.43"
- process $proc$libresoc.v:183947$11675
+ attribute \src "libresoc.v:183047.3-183048.43"
+ process $proc$libresoc.v:183047$11520
assign { } { }
assign $0\src36__data_o[3:0] \src36__data_o$next
sync posedge \coresync_clk
update \src36__data_o $0\src36__data_o[3:0]
end
- attribute \src "libresoc.v:183949.3-183950.43"
- process $proc$libresoc.v:183949$11676
+ attribute \src "libresoc.v:183049.3-183050.43"
+ process $proc$libresoc.v:183049$11521
assign { } { }
assign $0\src26__data_o[3:0] \src26__data_o$next
sync posedge \coresync_clk
update \src26__data_o $0\src26__data_o[3:0]
end
- attribute \src "libresoc.v:183951.3-183952.43"
- process $proc$libresoc.v:183951$11677
+ attribute \src "libresoc.v:183051.3-183052.43"
+ process $proc$libresoc.v:183051$11522
assign { } { }
assign $0\src16__data_o[3:0] \src16__data_o$next
sync posedge \coresync_clk
update \src16__data_o $0\src16__data_o[3:0]
end
- attribute \src "libresoc.v:183953.3-183954.49"
- process $proc$libresoc.v:183953$11678
- assign { } { }
- assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next
- sync posedge \coresync_clk
- update \cr_pred6__data_o $0\cr_pred6__data_o[3:0]
- end
- attribute \src "libresoc.v:183955.3-183994.6"
- process $proc$libresoc.v:183955$11679
+ attribute \src "libresoc.v:183053.3-183092.6"
+ process $proc$libresoc.v:183053$11523
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_pred6__data_o$next[3:0]$11680 $6\cr_pred6__data_o$next[3:0]$11686
- attribute \src "libresoc.v:183956.5-183956.29"
+ assign $0\src16__data_o$next[3:0]$11524 $6\src16__data_o$next[3:0]$11530
+ attribute \src "libresoc.v:183054.5-183054.29"
switch \initial
- attribute \src "libresoc.v:183956.9-183956.17"
+ attribute \src "libresoc.v:183054.9-183054.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred6__ren
+ switch \src16__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred6__data_o$next[3:0]$11681 $5\cr_pred6__data_o$next[3:0]$11685
+ assign $1\src16__data_o$next[3:0]$11525 $5\src16__data_o$next[3:0]$11529
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred6__data_o$next[3:0]$11682 \dest16__data_i
+ assign $2\src16__data_o$next[3:0]$11526 \dest16__data_i
case
- assign $2\cr_pred6__data_o$next[3:0]$11682 4'0000
+ assign $2\src16__data_o$next[3:0]$11526 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred6__data_o$next[3:0]$11683 \dest26__data_i
+ assign $3\src16__data_o$next[3:0]$11527 \dest26__data_i
case
- assign $3\cr_pred6__data_o$next[3:0]$11683 $2\cr_pred6__data_o$next[3:0]$11682
+ assign $3\src16__data_o$next[3:0]$11527 $2\src16__data_o$next[3:0]$11526
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred6__data_o$next[3:0]$11684 \w6__data_i
+ assign $4\src16__data_o$next[3:0]$11528 \w6__data_i
case
- assign $4\cr_pred6__data_o$next[3:0]$11684 $3\cr_pred6__data_o$next[3:0]$11683
+ assign $4\src16__data_o$next[3:0]$11528 $3\src16__data_o$next[3:0]$11527
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred6__data_o$next[3:0]$11685 \reg
+ assign $5\src16__data_o$next[3:0]$11529 \reg
case
- assign $5\cr_pred6__data_o$next[3:0]$11685 $4\cr_pred6__data_o$next[3:0]$11684
+ assign $5\src16__data_o$next[3:0]$11529 $4\src16__data_o$next[3:0]$11528
end
case
- assign $1\cr_pred6__data_o$next[3:0]$11681 4'0000
+ assign $1\src16__data_o$next[3:0]$11525 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred6__data_o$next[3:0]$11686 4'0000
+ assign $6\src16__data_o$next[3:0]$11530 4'0000
case
- assign $6\cr_pred6__data_o$next[3:0]$11686 $1\cr_pred6__data_o$next[3:0]$11681
+ assign $6\src16__data_o$next[3:0]$11530 $1\src16__data_o$next[3:0]$11525
end
sync always
- update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11680
+ update \src16__data_o$next $0\src16__data_o$next[3:0]$11524
end
- attribute \src "libresoc.v:183995.3-184024.6"
- process $proc$libresoc.v:183995$11687
+ attribute \src "libresoc.v:183093.3-183122.6"
+ process $proc$libresoc.v:183093$11531
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:183996.5-183996.29"
+ attribute \src "libresoc.v:183094.5-183094.29"
switch \initial
- attribute \src "libresoc.v:183996.9-183996.17"
+ attribute \src "libresoc.v:183094.9-183094.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred6__ren
+ switch \src16__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:184025.3-184064.6"
- process $proc$libresoc.v:184025$11688
+ attribute \src "libresoc.v:183123.3-183149.6"
+ process $proc$libresoc.v:183123$11532
assign { } { }
assign { } { }
assign { } { }
- assign $0\r26__data_o$next[3:0]$11689 $6\r26__data_o$next[3:0]$11695
- attribute \src "libresoc.v:184026.5-184026.29"
- switch \initial
- attribute \src "libresoc.v:184026.9-184026.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r26__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\r26__data_o$next[3:0]$11690 $5\r26__data_o$next[3:0]$11694
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest16__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r26__data_o$next[3:0]$11691 \dest16__data_i
- case
- assign $2\r26__data_o$next[3:0]$11691 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest26__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r26__data_o$next[3:0]$11692 \dest26__data_i
- case
- assign $3\r26__data_o$next[3:0]$11692 $2\r26__data_o$next[3:0]$11691
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w6__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r26__data_o$next[3:0]$11693 \w6__data_i
- case
- assign $4\r26__data_o$next[3:0]$11693 $3\r26__data_o$next[3:0]$11692
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r26__data_o$next[3:0]$11694 \reg
- case
- assign $5\r26__data_o$next[3:0]$11694 $4\r26__data_o$next[3:0]$11693
- end
- case
- assign $1\r26__data_o$next[3:0]$11690 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\r26__data_o$next[3:0]$11695 4'0000
- case
- assign $6\r26__data_o$next[3:0]$11695 $1\r26__data_o$next[3:0]$11690
- end
- sync always
- update \r26__data_o$next $0\r26__data_o$next[3:0]$11689
- end
- attribute \src "libresoc.v:184065.3-184094.6"
- process $proc$libresoc.v:184065$11696
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$11697 $1\wr_detect$16[0:0]$11698
- attribute \src "libresoc.v:184066.5-184066.29"
+ assign $0\reg$next[3:0]$11533 $4\reg$next[3:0]$11537
+ attribute \src "libresoc.v:183124.5-183124.29"
switch \initial
- attribute \src "libresoc.v:184066.9-184066.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r26__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\wr_detect$16[0:0]$11698 $4\wr_detect$16[0:0]$11701
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest16__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\wr_detect$16[0:0]$11699 1'1
- case
- assign $2\wr_detect$16[0:0]$11699 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest26__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\wr_detect$16[0:0]$11700 1'1
- case
- assign $3\wr_detect$16[0:0]$11700 $2\wr_detect$16[0:0]$11699
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w6__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\wr_detect$16[0:0]$11701 1'1
- case
- assign $4\wr_detect$16[0:0]$11701 $3\wr_detect$16[0:0]$11700
- end
- case
- assign $1\wr_detect$16[0:0]$11698 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11697
- end
- attribute \src "libresoc.v:184095.3-184121.6"
- process $proc$libresoc.v:184095$11702
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$11703 $4\reg$next[3:0]$11707
- attribute \src "libresoc.v:184096.5-184096.29"
- switch \initial
- attribute \src "libresoc.v:184096.9-184096.17"
+ attribute \src "libresoc.v:183124.9-183124.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11704 \dest16__data_i
+ assign $1\reg$next[3:0]$11534 \dest16__data_i
case
- assign $1\reg$next[3:0]$11704 \reg
+ assign $1\reg$next[3:0]$11534 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11705 \dest26__data_i
+ assign $2\reg$next[3:0]$11535 \dest26__data_i
case
- assign $2\reg$next[3:0]$11705 $1\reg$next[3:0]$11704
+ assign $2\reg$next[3:0]$11535 $1\reg$next[3:0]$11534
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11706 \w6__data_i
+ assign $3\reg$next[3:0]$11536 \w6__data_i
case
- assign $3\reg$next[3:0]$11706 $2\reg$next[3:0]$11705
+ assign $3\reg$next[3:0]$11536 $2\reg$next[3:0]$11535
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11707 4'0000
+ assign $4\reg$next[3:0]$11537 4'0000
case
- assign $4\reg$next[3:0]$11707 $3\reg$next[3:0]$11706
+ assign $4\reg$next[3:0]$11537 $3\reg$next[3:0]$11536
end
sync always
- update \reg$next $0\reg$next[3:0]$11703
+ update \reg$next $0\reg$next[3:0]$11533
end
- attribute \src "libresoc.v:184122.3-184161.6"
- process $proc$libresoc.v:184122$11708
+ attribute \src "libresoc.v:183150.3-183189.6"
+ process $proc$libresoc.v:183150$11538
assign { } { }
assign { } { }
assign { } { }
- assign $0\src16__data_o$next[3:0]$11709 $6\src16__data_o$next[3:0]$11715
- attribute \src "libresoc.v:184123.5-184123.29"
+ assign $0\src26__data_o$next[3:0]$11539 $6\src26__data_o$next[3:0]$11545
+ attribute \src "libresoc.v:183151.5-183151.29"
switch \initial
- attribute \src "libresoc.v:184123.9-184123.17"
+ attribute \src "libresoc.v:183151.9-183151.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src16__ren
+ switch \src26__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src16__data_o$next[3:0]$11710 $5\src16__data_o$next[3:0]$11714
+ assign $1\src26__data_o$next[3:0]$11540 $5\src26__data_o$next[3:0]$11544
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src16__data_o$next[3:0]$11711 \dest16__data_i
+ assign $2\src26__data_o$next[3:0]$11541 \dest16__data_i
case
- assign $2\src16__data_o$next[3:0]$11711 4'0000
+ assign $2\src26__data_o$next[3:0]$11541 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src16__data_o$next[3:0]$11712 \dest26__data_i
+ assign $3\src26__data_o$next[3:0]$11542 \dest26__data_i
case
- assign $3\src16__data_o$next[3:0]$11712 $2\src16__data_o$next[3:0]$11711
+ assign $3\src26__data_o$next[3:0]$11542 $2\src26__data_o$next[3:0]$11541
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src16__data_o$next[3:0]$11713 \w6__data_i
+ assign $4\src26__data_o$next[3:0]$11543 \w6__data_i
case
- assign $4\src16__data_o$next[3:0]$11713 $3\src16__data_o$next[3:0]$11712
+ assign $4\src26__data_o$next[3:0]$11543 $3\src26__data_o$next[3:0]$11542
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src16__data_o$next[3:0]$11714 \reg
+ assign $5\src26__data_o$next[3:0]$11544 \reg
case
- assign $5\src16__data_o$next[3:0]$11714 $4\src16__data_o$next[3:0]$11713
+ assign $5\src26__data_o$next[3:0]$11544 $4\src26__data_o$next[3:0]$11543
end
case
- assign $1\src16__data_o$next[3:0]$11710 4'0000
+ assign $1\src26__data_o$next[3:0]$11540 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src16__data_o$next[3:0]$11715 4'0000
+ assign $6\src26__data_o$next[3:0]$11545 4'0000
case
- assign $6\src16__data_o$next[3:0]$11715 $1\src16__data_o$next[3:0]$11710
+ assign $6\src26__data_o$next[3:0]$11545 $1\src26__data_o$next[3:0]$11540
end
sync always
- update \src16__data_o$next $0\src16__data_o$next[3:0]$11709
+ update \src26__data_o$next $0\src26__data_o$next[3:0]$11539
end
- attribute \src "libresoc.v:184162.3-184191.6"
- process $proc$libresoc.v:184162$11716
+ attribute \src "libresoc.v:183190.3-183219.6"
+ process $proc$libresoc.v:183190$11546
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11717 $1\wr_detect$4[0:0]$11718
- attribute \src "libresoc.v:184163.5-184163.29"
+ assign $0\wr_detect$4[0:0]$11547 $1\wr_detect$4[0:0]$11548
+ attribute \src "libresoc.v:183191.5-183191.29"
switch \initial
- attribute \src "libresoc.v:184163.9-184163.17"
+ attribute \src "libresoc.v:183191.9-183191.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src16__ren
+ switch \src26__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11718 $4\wr_detect$4[0:0]$11721
+ assign $1\wr_detect$4[0:0]$11548 $4\wr_detect$4[0:0]$11551
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11719 1'1
+ assign $2\wr_detect$4[0:0]$11549 1'1
case
- assign $2\wr_detect$4[0:0]$11719 1'0
+ assign $2\wr_detect$4[0:0]$11549 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11720 1'1
+ assign $3\wr_detect$4[0:0]$11550 1'1
case
- assign $3\wr_detect$4[0:0]$11720 $2\wr_detect$4[0:0]$11719
+ assign $3\wr_detect$4[0:0]$11550 $2\wr_detect$4[0:0]$11549
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11721 1'1
+ assign $4\wr_detect$4[0:0]$11551 1'1
case
- assign $4\wr_detect$4[0:0]$11721 $3\wr_detect$4[0:0]$11720
+ assign $4\wr_detect$4[0:0]$11551 $3\wr_detect$4[0:0]$11550
end
case
- assign $1\wr_detect$4[0:0]$11718 1'0
+ assign $1\wr_detect$4[0:0]$11548 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11717
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11547
end
- attribute \src "libresoc.v:184192.3-184231.6"
- process $proc$libresoc.v:184192$11722
+ attribute \src "libresoc.v:183220.3-183259.6"
+ process $proc$libresoc.v:183220$11552
assign { } { }
assign { } { }
assign { } { }
- assign $0\src26__data_o$next[3:0]$11723 $6\src26__data_o$next[3:0]$11729
- attribute \src "libresoc.v:184193.5-184193.29"
+ assign $0\src36__data_o$next[3:0]$11553 $6\src36__data_o$next[3:0]$11559
+ attribute \src "libresoc.v:183221.5-183221.29"
switch \initial
- attribute \src "libresoc.v:184193.9-184193.17"
+ attribute \src "libresoc.v:183221.9-183221.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src26__ren
+ switch \src36__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src26__data_o$next[3:0]$11724 $5\src26__data_o$next[3:0]$11728
+ assign $1\src36__data_o$next[3:0]$11554 $5\src36__data_o$next[3:0]$11558
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src26__data_o$next[3:0]$11725 \dest16__data_i
+ assign $2\src36__data_o$next[3:0]$11555 \dest16__data_i
case
- assign $2\src26__data_o$next[3:0]$11725 4'0000
+ assign $2\src36__data_o$next[3:0]$11555 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src26__data_o$next[3:0]$11726 \dest26__data_i
+ assign $3\src36__data_o$next[3:0]$11556 \dest26__data_i
case
- assign $3\src26__data_o$next[3:0]$11726 $2\src26__data_o$next[3:0]$11725
+ assign $3\src36__data_o$next[3:0]$11556 $2\src36__data_o$next[3:0]$11555
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src26__data_o$next[3:0]$11727 \w6__data_i
+ assign $4\src36__data_o$next[3:0]$11557 \w6__data_i
case
- assign $4\src26__data_o$next[3:0]$11727 $3\src26__data_o$next[3:0]$11726
+ assign $4\src36__data_o$next[3:0]$11557 $3\src36__data_o$next[3:0]$11556
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src26__data_o$next[3:0]$11728 \reg
+ assign $5\src36__data_o$next[3:0]$11558 \reg
case
- assign $5\src26__data_o$next[3:0]$11728 $4\src26__data_o$next[3:0]$11727
+ assign $5\src36__data_o$next[3:0]$11558 $4\src36__data_o$next[3:0]$11557
end
case
- assign $1\src26__data_o$next[3:0]$11724 4'0000
+ assign $1\src36__data_o$next[3:0]$11554 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src26__data_o$next[3:0]$11729 4'0000
+ assign $6\src36__data_o$next[3:0]$11559 4'0000
case
- assign $6\src26__data_o$next[3:0]$11729 $1\src26__data_o$next[3:0]$11724
+ assign $6\src36__data_o$next[3:0]$11559 $1\src36__data_o$next[3:0]$11554
end
sync always
- update \src26__data_o$next $0\src26__data_o$next[3:0]$11723
+ update \src36__data_o$next $0\src36__data_o$next[3:0]$11553
end
- attribute \src "libresoc.v:184232.3-184261.6"
- process $proc$libresoc.v:184232$11730
+ attribute \src "libresoc.v:183260.3-183289.6"
+ process $proc$libresoc.v:183260$11560
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11731 $1\wr_detect$7[0:0]$11732
- attribute \src "libresoc.v:184233.5-184233.29"
+ assign $0\wr_detect$7[0:0]$11561 $1\wr_detect$7[0:0]$11562
+ attribute \src "libresoc.v:183261.5-183261.29"
switch \initial
- attribute \src "libresoc.v:184233.9-184233.17"
+ attribute \src "libresoc.v:183261.9-183261.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src26__ren
+ switch \src36__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11732 $4\wr_detect$7[0:0]$11735
+ assign $1\wr_detect$7[0:0]$11562 $4\wr_detect$7[0:0]$11565
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11733 1'1
+ assign $2\wr_detect$7[0:0]$11563 1'1
case
- assign $2\wr_detect$7[0:0]$11733 1'0
+ assign $2\wr_detect$7[0:0]$11563 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11734 1'1
+ assign $3\wr_detect$7[0:0]$11564 1'1
case
- assign $3\wr_detect$7[0:0]$11734 $2\wr_detect$7[0:0]$11733
+ assign $3\wr_detect$7[0:0]$11564 $2\wr_detect$7[0:0]$11563
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11735 1'1
+ assign $4\wr_detect$7[0:0]$11565 1'1
case
- assign $4\wr_detect$7[0:0]$11735 $3\wr_detect$7[0:0]$11734
+ assign $4\wr_detect$7[0:0]$11565 $3\wr_detect$7[0:0]$11564
end
case
- assign $1\wr_detect$7[0:0]$11732 1'0
+ assign $1\wr_detect$7[0:0]$11562 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11731
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11561
end
- attribute \src "libresoc.v:184262.3-184301.6"
- process $proc$libresoc.v:184262$11736
+ attribute \src "libresoc.v:183290.3-183329.6"
+ process $proc$libresoc.v:183290$11566
assign { } { }
assign { } { }
assign { } { }
- assign $0\src36__data_o$next[3:0]$11737 $6\src36__data_o$next[3:0]$11743
- attribute \src "libresoc.v:184263.5-184263.29"
+ assign $0\r6__data_o$next[3:0]$11567 $6\r6__data_o$next[3:0]$11573
+ attribute \src "libresoc.v:183291.5-183291.29"
switch \initial
- attribute \src "libresoc.v:184263.9-184263.17"
+ attribute \src "libresoc.v:183291.9-183291.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src36__ren
+ switch \r6__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src36__data_o$next[3:0]$11738 $5\src36__data_o$next[3:0]$11742
+ assign $1\r6__data_o$next[3:0]$11568 $5\r6__data_o$next[3:0]$11572
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src36__data_o$next[3:0]$11739 \dest16__data_i
+ assign $2\r6__data_o$next[3:0]$11569 \dest16__data_i
case
- assign $2\src36__data_o$next[3:0]$11739 4'0000
+ assign $2\r6__data_o$next[3:0]$11569 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src36__data_o$next[3:0]$11740 \dest26__data_i
+ assign $3\r6__data_o$next[3:0]$11570 \dest26__data_i
case
- assign $3\src36__data_o$next[3:0]$11740 $2\src36__data_o$next[3:0]$11739
+ assign $3\r6__data_o$next[3:0]$11570 $2\r6__data_o$next[3:0]$11569
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src36__data_o$next[3:0]$11741 \w6__data_i
+ assign $4\r6__data_o$next[3:0]$11571 \w6__data_i
case
- assign $4\src36__data_o$next[3:0]$11741 $3\src36__data_o$next[3:0]$11740
+ assign $4\r6__data_o$next[3:0]$11571 $3\r6__data_o$next[3:0]$11570
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src36__data_o$next[3:0]$11742 \reg
+ assign $5\r6__data_o$next[3:0]$11572 \reg
case
- assign $5\src36__data_o$next[3:0]$11742 $4\src36__data_o$next[3:0]$11741
+ assign $5\r6__data_o$next[3:0]$11572 $4\r6__data_o$next[3:0]$11571
end
case
- assign $1\src36__data_o$next[3:0]$11738 4'0000
+ assign $1\r6__data_o$next[3:0]$11568 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src36__data_o$next[3:0]$11743 4'0000
+ assign $6\r6__data_o$next[3:0]$11573 4'0000
case
- assign $6\src36__data_o$next[3:0]$11743 $1\src36__data_o$next[3:0]$11738
+ assign $6\r6__data_o$next[3:0]$11573 $1\r6__data_o$next[3:0]$11568
end
sync always
- update \src36__data_o$next $0\src36__data_o$next[3:0]$11737
+ update \r6__data_o$next $0\r6__data_o$next[3:0]$11567
end
- attribute \src "libresoc.v:184302.3-184331.6"
- process $proc$libresoc.v:184302$11744
+ attribute \src "libresoc.v:183330.3-183359.6"
+ process $proc$libresoc.v:183330$11574
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11745 $1\wr_detect$10[0:0]$11746
- attribute \src "libresoc.v:184303.5-184303.29"
+ assign $0\wr_detect$10[0:0]$11575 $1\wr_detect$10[0:0]$11576
+ attribute \src "libresoc.v:183331.5-183331.29"
switch \initial
- attribute \src "libresoc.v:184303.9-184303.17"
+ attribute \src "libresoc.v:183331.9-183331.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src36__ren
+ switch \r6__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11746 $4\wr_detect$10[0:0]$11749
+ assign $1\wr_detect$10[0:0]$11576 $4\wr_detect$10[0:0]$11579
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11747 1'1
+ assign $2\wr_detect$10[0:0]$11577 1'1
case
- assign $2\wr_detect$10[0:0]$11747 1'0
+ assign $2\wr_detect$10[0:0]$11577 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11748 1'1
+ assign $3\wr_detect$10[0:0]$11578 1'1
case
- assign $3\wr_detect$10[0:0]$11748 $2\wr_detect$10[0:0]$11747
+ assign $3\wr_detect$10[0:0]$11578 $2\wr_detect$10[0:0]$11577
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11749 1'1
+ assign $4\wr_detect$10[0:0]$11579 1'1
case
- assign $4\wr_detect$10[0:0]$11749 $3\wr_detect$10[0:0]$11748
+ assign $4\wr_detect$10[0:0]$11579 $3\wr_detect$10[0:0]$11578
end
case
- assign $1\wr_detect$10[0:0]$11746 1'0
+ assign $1\wr_detect$10[0:0]$11576 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11745
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11575
end
- attribute \src "libresoc.v:184332.3-184371.6"
- process $proc$libresoc.v:184332$11750
+ attribute \src "libresoc.v:183360.3-183399.6"
+ process $proc$libresoc.v:183360$11580
assign { } { }
assign { } { }
assign { } { }
- assign $0\r6__data_o$next[3:0]$11751 $6\r6__data_o$next[3:0]$11757
- attribute \src "libresoc.v:184333.5-184333.29"
+ assign $0\r26__data_o$next[3:0]$11581 $6\r26__data_o$next[3:0]$11587
+ attribute \src "libresoc.v:183361.5-183361.29"
switch \initial
- attribute \src "libresoc.v:184333.9-184333.17"
+ attribute \src "libresoc.v:183361.9-183361.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r6__ren
+ switch \r26__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r6__data_o$next[3:0]$11752 $5\r6__data_o$next[3:0]$11756
+ assign $1\r26__data_o$next[3:0]$11582 $5\r26__data_o$next[3:0]$11586
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r6__data_o$next[3:0]$11753 \dest16__data_i
+ assign $2\r26__data_o$next[3:0]$11583 \dest16__data_i
case
- assign $2\r6__data_o$next[3:0]$11753 4'0000
+ assign $2\r26__data_o$next[3:0]$11583 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r6__data_o$next[3:0]$11754 \dest26__data_i
+ assign $3\r26__data_o$next[3:0]$11584 \dest26__data_i
case
- assign $3\r6__data_o$next[3:0]$11754 $2\r6__data_o$next[3:0]$11753
+ assign $3\r26__data_o$next[3:0]$11584 $2\r26__data_o$next[3:0]$11583
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r6__data_o$next[3:0]$11755 \w6__data_i
+ assign $4\r26__data_o$next[3:0]$11585 \w6__data_i
case
- assign $4\r6__data_o$next[3:0]$11755 $3\r6__data_o$next[3:0]$11754
+ assign $4\r26__data_o$next[3:0]$11585 $3\r26__data_o$next[3:0]$11584
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r6__data_o$next[3:0]$11756 \reg
+ assign $5\r26__data_o$next[3:0]$11586 \reg
case
- assign $5\r6__data_o$next[3:0]$11756 $4\r6__data_o$next[3:0]$11755
+ assign $5\r26__data_o$next[3:0]$11586 $4\r26__data_o$next[3:0]$11585
end
case
- assign $1\r6__data_o$next[3:0]$11752 4'0000
+ assign $1\r26__data_o$next[3:0]$11582 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r6__data_o$next[3:0]$11757 4'0000
+ assign $6\r26__data_o$next[3:0]$11587 4'0000
case
- assign $6\r6__data_o$next[3:0]$11757 $1\r6__data_o$next[3:0]$11752
+ assign $6\r26__data_o$next[3:0]$11587 $1\r26__data_o$next[3:0]$11582
end
sync always
- update \r6__data_o$next $0\r6__data_o$next[3:0]$11751
+ update \r26__data_o$next $0\r26__data_o$next[3:0]$11581
end
- attribute \src "libresoc.v:184372.3-184401.6"
- process $proc$libresoc.v:184372$11758
+ attribute \src "libresoc.v:183400.3-183429.6"
+ process $proc$libresoc.v:183400$11588
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11759 $1\wr_detect$13[0:0]$11760
- attribute \src "libresoc.v:184373.5-184373.29"
+ assign $0\wr_detect$13[0:0]$11589 $1\wr_detect$13[0:0]$11590
+ attribute \src "libresoc.v:183401.5-183401.29"
switch \initial
- attribute \src "libresoc.v:184373.9-184373.17"
+ attribute \src "libresoc.v:183401.9-183401.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r6__ren
+ switch \r26__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11760 $4\wr_detect$13[0:0]$11763
+ assign $1\wr_detect$13[0:0]$11590 $4\wr_detect$13[0:0]$11593
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11761 1'1
+ assign $2\wr_detect$13[0:0]$11591 1'1
case
- assign $2\wr_detect$13[0:0]$11761 1'0
+ assign $2\wr_detect$13[0:0]$11591 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11762 1'1
+ assign $3\wr_detect$13[0:0]$11592 1'1
case
- assign $3\wr_detect$13[0:0]$11762 $2\wr_detect$13[0:0]$11761
+ assign $3\wr_detect$13[0:0]$11592 $2\wr_detect$13[0:0]$11591
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11763 1'1
+ assign $4\wr_detect$13[0:0]$11593 1'1
case
- assign $4\wr_detect$13[0:0]$11763 $3\wr_detect$13[0:0]$11762
+ assign $4\wr_detect$13[0:0]$11593 $3\wr_detect$13[0:0]$11592
end
case
- assign $1\wr_detect$13[0:0]$11760 1'0
+ assign $1\wr_detect$13[0:0]$11590 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11759
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11589
end
- connect \$9 $not$libresoc.v:183935$11666_Y
- connect \$12 $not$libresoc.v:183936$11667_Y
- connect \$15 $not$libresoc.v:183937$11668_Y
- connect \$1 $not$libresoc.v:183938$11669_Y
- connect \$3 $not$libresoc.v:183939$11670_Y
- connect \$6 $not$libresoc.v:183940$11671_Y
+ connect \$9 $not$libresoc.v:183036$11512_Y
+ connect \$12 $not$libresoc.v:183037$11513_Y
+ connect \$1 $not$libresoc.v:183038$11514_Y
+ connect \$3 $not$libresoc.v:183039$11515_Y
+ connect \$6 $not$libresoc.v:183040$11516_Y
end
-attribute \src "libresoc.v:184406.1-184961.10"
+attribute \src "libresoc.v:183434.1-183905.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7"
attribute \generator "nMigen"
module \reg_7
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $0\cr_pred7__data_o$next[3:0]$11786
- attribute \src "libresoc.v:184512.3-184513.49"
- wire width 4 $0\cr_pred7__data_o[3:0]
- attribute \src "libresoc.v:184407.7-184407.20"
+ attribute \src "libresoc.v:183435.7-183435.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $0\r27__data_o$next[3:0]$11795
- attribute \src "libresoc.v:184502.3-184503.39"
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $0\r27__data_o$next[3:0]$11670
+ attribute \src "libresoc.v:183518.3-183519.39"
wire width 4 $0\r27__data_o[3:0]
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $0\r7__data_o$next[3:0]$11857
- attribute \src "libresoc.v:184504.3-184505.37"
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $0\r7__data_o$next[3:0]$11656
+ attribute \src "libresoc.v:183520.3-183521.37"
wire width 4 $0\r7__data_o[3:0]
- attribute \src "libresoc.v:184654.3-184680.6"
- wire width 4 $0\reg$next[3:0]$11809
- attribute \src "libresoc.v:184500.3-184501.25"
+ attribute \src "libresoc.v:183598.3-183624.6"
+ wire width 4 $0\reg$next[3:0]$11622
+ attribute \src "libresoc.v:183516.3-183517.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $0\src17__data_o$next[3:0]$11815
- attribute \src "libresoc.v:184510.3-184511.43"
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $0\src17__data_o$next[3:0]$11613
+ attribute \src "libresoc.v:183526.3-183527.43"
wire width 4 $0\src17__data_o[3:0]
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $0\src27__data_o$next[3:0]$11829
- attribute \src "libresoc.v:184508.3-184509.43"
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $0\src27__data_o$next[3:0]$11628
+ attribute \src "libresoc.v:183524.3-183525.43"
wire width 4 $0\src27__data_o[3:0]
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $0\src37__data_o$next[3:0]$11843
- attribute \src "libresoc.v:184506.3-184507.43"
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $0\src37__data_o$next[3:0]$11642
+ attribute \src "libresoc.v:183522.3-183523.43"
wire width 4 $0\src37__data_o[3:0]
- attribute \src "libresoc.v:184861.3-184890.6"
- wire $0\wr_detect$10[0:0]$11851
- attribute \src "libresoc.v:184931.3-184960.6"
- wire $0\wr_detect$13[0:0]$11865
- attribute \src "libresoc.v:184624.3-184653.6"
- wire $0\wr_detect$16[0:0]$11803
- attribute \src "libresoc.v:184721.3-184750.6"
- wire $0\wr_detect$4[0:0]$11823
- attribute \src "libresoc.v:184791.3-184820.6"
- wire $0\wr_detect$7[0:0]$11837
- attribute \src "libresoc.v:184554.3-184583.6"
+ attribute \src "libresoc.v:183805.3-183834.6"
+ wire $0\wr_detect$10[0:0]$11664
+ attribute \src "libresoc.v:183875.3-183904.6"
+ wire $0\wr_detect$13[0:0]$11678
+ attribute \src "libresoc.v:183665.3-183694.6"
+ wire $0\wr_detect$4[0:0]$11636
+ attribute \src "libresoc.v:183735.3-183764.6"
+ wire $0\wr_detect$7[0:0]$11650
+ attribute \src "libresoc.v:183568.3-183597.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $1\cr_pred7__data_o$next[3:0]$11787
- attribute \src "libresoc.v:184426.13-184426.36"
- wire width 4 $1\cr_pred7__data_o[3:0]
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $1\r27__data_o$next[3:0]$11796
- attribute \src "libresoc.v:184441.13-184441.31"
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $1\r27__data_o$next[3:0]$11671
+ attribute \src "libresoc.v:183460.13-183460.31"
wire width 4 $1\r27__data_o[3:0]
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $1\r7__data_o$next[3:0]$11858
- attribute \src "libresoc.v:184448.13-184448.30"
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $1\r7__data_o$next[3:0]$11657
+ attribute \src "libresoc.v:183467.13-183467.30"
wire width 4 $1\r7__data_o[3:0]
- attribute \src "libresoc.v:184654.3-184680.6"
- wire width 4 $1\reg$next[3:0]$11810
- attribute \src "libresoc.v:184454.13-184454.25"
+ attribute \src "libresoc.v:183598.3-183624.6"
+ wire width 4 $1\reg$next[3:0]$11623
+ attribute \src "libresoc.v:183473.13-183473.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $1\src17__data_o$next[3:0]$11816
- attribute \src "libresoc.v:184459.13-184459.33"
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $1\src17__data_o$next[3:0]$11614
+ attribute \src "libresoc.v:183478.13-183478.33"
wire width 4 $1\src17__data_o[3:0]
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $1\src27__data_o$next[3:0]$11830
- attribute \src "libresoc.v:184466.13-184466.33"
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $1\src27__data_o$next[3:0]$11629
+ attribute \src "libresoc.v:183485.13-183485.33"
wire width 4 $1\src27__data_o[3:0]
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $1\src37__data_o$next[3:0]$11844
- attribute \src "libresoc.v:184473.13-184473.33"
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $1\src37__data_o$next[3:0]$11643
+ attribute \src "libresoc.v:183492.13-183492.33"
wire width 4 $1\src37__data_o[3:0]
- attribute \src "libresoc.v:184861.3-184890.6"
- wire $1\wr_detect$10[0:0]$11852
- attribute \src "libresoc.v:184931.3-184960.6"
- wire $1\wr_detect$13[0:0]$11866
- attribute \src "libresoc.v:184624.3-184653.6"
- wire $1\wr_detect$16[0:0]$11804
- attribute \src "libresoc.v:184721.3-184750.6"
- wire $1\wr_detect$4[0:0]$11824
- attribute \src "libresoc.v:184791.3-184820.6"
- wire $1\wr_detect$7[0:0]$11838
- attribute \src "libresoc.v:184554.3-184583.6"
+ attribute \src "libresoc.v:183805.3-183834.6"
+ wire $1\wr_detect$10[0:0]$11665
+ attribute \src "libresoc.v:183875.3-183904.6"
+ wire $1\wr_detect$13[0:0]$11679
+ attribute \src "libresoc.v:183665.3-183694.6"
+ wire $1\wr_detect$4[0:0]$11637
+ attribute \src "libresoc.v:183735.3-183764.6"
+ wire $1\wr_detect$7[0:0]$11651
+ attribute \src "libresoc.v:183568.3-183597.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $2\cr_pred7__data_o$next[3:0]$11788
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $2\r27__data_o$next[3:0]$11797
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $2\r7__data_o$next[3:0]$11859
- attribute \src "libresoc.v:184654.3-184680.6"
- wire width 4 $2\reg$next[3:0]$11811
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $2\src17__data_o$next[3:0]$11817
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $2\src27__data_o$next[3:0]$11831
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $2\src37__data_o$next[3:0]$11845
- attribute \src "libresoc.v:184861.3-184890.6"
- wire $2\wr_detect$10[0:0]$11853
- attribute \src "libresoc.v:184931.3-184960.6"
- wire $2\wr_detect$13[0:0]$11867
- attribute \src "libresoc.v:184624.3-184653.6"
- wire $2\wr_detect$16[0:0]$11805
- attribute \src "libresoc.v:184721.3-184750.6"
- wire $2\wr_detect$4[0:0]$11825
- attribute \src "libresoc.v:184791.3-184820.6"
- wire $2\wr_detect$7[0:0]$11839
- attribute \src "libresoc.v:184554.3-184583.6"
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $2\r27__data_o$next[3:0]$11672
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $2\r7__data_o$next[3:0]$11658
+ attribute \src "libresoc.v:183598.3-183624.6"
+ wire width 4 $2\reg$next[3:0]$11624
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $2\src17__data_o$next[3:0]$11615
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $2\src27__data_o$next[3:0]$11630
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $2\src37__data_o$next[3:0]$11644
+ attribute \src "libresoc.v:183805.3-183834.6"
+ wire $2\wr_detect$10[0:0]$11666
+ attribute \src "libresoc.v:183875.3-183904.6"
+ wire $2\wr_detect$13[0:0]$11680
+ attribute \src "libresoc.v:183665.3-183694.6"
+ wire $2\wr_detect$4[0:0]$11638
+ attribute \src "libresoc.v:183735.3-183764.6"
+ wire $2\wr_detect$7[0:0]$11652
+ attribute \src "libresoc.v:183568.3-183597.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $3\cr_pred7__data_o$next[3:0]$11789
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $3\r27__data_o$next[3:0]$11798
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $3\r7__data_o$next[3:0]$11860
- attribute \src "libresoc.v:184654.3-184680.6"
- wire width 4 $3\reg$next[3:0]$11812
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $3\src17__data_o$next[3:0]$11818
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $3\src27__data_o$next[3:0]$11832
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $3\src37__data_o$next[3:0]$11846
- attribute \src "libresoc.v:184861.3-184890.6"
- wire $3\wr_detect$10[0:0]$11854
- attribute \src "libresoc.v:184931.3-184960.6"
- wire $3\wr_detect$13[0:0]$11868
- attribute \src "libresoc.v:184624.3-184653.6"
- wire $3\wr_detect$16[0:0]$11806
- attribute \src "libresoc.v:184721.3-184750.6"
- wire $3\wr_detect$4[0:0]$11826
- attribute \src "libresoc.v:184791.3-184820.6"
- wire $3\wr_detect$7[0:0]$11840
- attribute \src "libresoc.v:184554.3-184583.6"
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $3\r27__data_o$next[3:0]$11673
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $3\r7__data_o$next[3:0]$11659
+ attribute \src "libresoc.v:183598.3-183624.6"
+ wire width 4 $3\reg$next[3:0]$11625
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $3\src17__data_o$next[3:0]$11616
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $3\src27__data_o$next[3:0]$11631
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $3\src37__data_o$next[3:0]$11645
+ attribute \src "libresoc.v:183805.3-183834.6"
+ wire $3\wr_detect$10[0:0]$11667
+ attribute \src "libresoc.v:183875.3-183904.6"
+ wire $3\wr_detect$13[0:0]$11681
+ attribute \src "libresoc.v:183665.3-183694.6"
+ wire $3\wr_detect$4[0:0]$11639
+ attribute \src "libresoc.v:183735.3-183764.6"
+ wire $3\wr_detect$7[0:0]$11653
+ attribute \src "libresoc.v:183568.3-183597.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $4\cr_pred7__data_o$next[3:0]$11790
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $4\r27__data_o$next[3:0]$11799
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $4\r7__data_o$next[3:0]$11861
- attribute \src "libresoc.v:184654.3-184680.6"
- wire width 4 $4\reg$next[3:0]$11813
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $4\src17__data_o$next[3:0]$11819
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $4\src27__data_o$next[3:0]$11833
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $4\src37__data_o$next[3:0]$11847
- attribute \src "libresoc.v:184861.3-184890.6"
- wire $4\wr_detect$10[0:0]$11855
- attribute \src "libresoc.v:184931.3-184960.6"
- wire $4\wr_detect$13[0:0]$11869
- attribute \src "libresoc.v:184624.3-184653.6"
- wire $4\wr_detect$16[0:0]$11807
- attribute \src "libresoc.v:184721.3-184750.6"
- wire $4\wr_detect$4[0:0]$11827
- attribute \src "libresoc.v:184791.3-184820.6"
- wire $4\wr_detect$7[0:0]$11841
- attribute \src "libresoc.v:184554.3-184583.6"
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $4\r27__data_o$next[3:0]$11674
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $4\r7__data_o$next[3:0]$11660
+ attribute \src "libresoc.v:183598.3-183624.6"
+ wire width 4 $4\reg$next[3:0]$11626
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $4\src17__data_o$next[3:0]$11617
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $4\src27__data_o$next[3:0]$11632
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $4\src37__data_o$next[3:0]$11646
+ attribute \src "libresoc.v:183805.3-183834.6"
+ wire $4\wr_detect$10[0:0]$11668
+ attribute \src "libresoc.v:183875.3-183904.6"
+ wire $4\wr_detect$13[0:0]$11682
+ attribute \src "libresoc.v:183665.3-183694.6"
+ wire $4\wr_detect$4[0:0]$11640
+ attribute \src "libresoc.v:183735.3-183764.6"
+ wire $4\wr_detect$7[0:0]$11654
+ attribute \src "libresoc.v:183568.3-183597.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $5\cr_pred7__data_o$next[3:0]$11791
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $5\r27__data_o$next[3:0]$11800
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $5\r7__data_o$next[3:0]$11862
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $5\src17__data_o$next[3:0]$11820
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $5\src27__data_o$next[3:0]$11834
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $5\src37__data_o$next[3:0]$11848
- attribute \src "libresoc.v:184514.3-184553.6"
- wire width 4 $6\cr_pred7__data_o$next[3:0]$11792
- attribute \src "libresoc.v:184584.3-184623.6"
- wire width 4 $6\r27__data_o$next[3:0]$11801
- attribute \src "libresoc.v:184891.3-184930.6"
- wire width 4 $6\r7__data_o$next[3:0]$11863
- attribute \src "libresoc.v:184681.3-184720.6"
- wire width 4 $6\src17__data_o$next[3:0]$11821
- attribute \src "libresoc.v:184751.3-184790.6"
- wire width 4 $6\src27__data_o$next[3:0]$11835
- attribute \src "libresoc.v:184821.3-184860.6"
- wire width 4 $6\src37__data_o$next[3:0]$11849
- attribute \src "libresoc.v:184494.17-184494.104"
- wire $not$libresoc.v:184494$11772_Y
- attribute \src "libresoc.v:184495.18-184495.105"
- wire $not$libresoc.v:184495$11773_Y
- attribute \src "libresoc.v:184496.18-184496.105"
- wire $not$libresoc.v:184496$11774_Y
- attribute \src "libresoc.v:184497.17-184497.100"
- wire $not$libresoc.v:184497$11775_Y
- attribute \src "libresoc.v:184498.17-184498.103"
- wire $not$libresoc.v:184498$11776_Y
- attribute \src "libresoc.v:184499.17-184499.103"
- wire $not$libresoc.v:184499$11777_Y
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $5\r27__data_o$next[3:0]$11675
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $5\r7__data_o$next[3:0]$11661
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $5\src17__data_o$next[3:0]$11618
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $5\src27__data_o$next[3:0]$11633
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $5\src37__data_o$next[3:0]$11647
+ attribute \src "libresoc.v:183835.3-183874.6"
+ wire width 4 $6\r27__data_o$next[3:0]$11676
+ attribute \src "libresoc.v:183765.3-183804.6"
+ wire width 4 $6\r7__data_o$next[3:0]$11662
+ attribute \src "libresoc.v:183528.3-183567.6"
+ wire width 4 $6\src17__data_o$next[3:0]$11619
+ attribute \src "libresoc.v:183625.3-183664.6"
+ wire width 4 $6\src27__data_o$next[3:0]$11634
+ attribute \src "libresoc.v:183695.3-183734.6"
+ wire width 4 $6\src37__data_o$next[3:0]$11648
+ attribute \src "libresoc.v:183511.17-183511.104"
+ wire $not$libresoc.v:183511$11601_Y
+ attribute \src "libresoc.v:183512.18-183512.105"
+ wire $not$libresoc.v:183512$11602_Y
+ attribute \src "libresoc.v:183513.17-183513.100"
+ wire $not$libresoc.v:183513$11603_Y
+ attribute \src "libresoc.v:183514.17-183514.103"
+ wire $not$libresoc.v:183514$11604_Y
+ attribute \src "libresoc.v:183515.17-183515.103"
+ wire $not$libresoc.v:183515$11605_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
- wire input 20 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire input 18 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 3 \cr_pred7__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 \cr_pred7__data_o$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 2 \cr_pred7__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 11 \dest17__data_i
+ wire width 4 input 9 \dest17__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 10 \dest17__wen
+ wire input 8 \dest17__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 13 \dest27__data_i
+ wire width 4 input 11 \dest27__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 12 \dest27__wen
- attribute \src "libresoc.v:184407.7-184407.15"
+ wire input 10 \dest27__wen
+ attribute \src "libresoc.v:183435.7-183435.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 16 \r27__data_o
+ wire width 4 output 14 \r27__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r27__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 17 \r27__ren
+ wire input 15 \r27__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 14 \r7__data_o
+ wire width 4 output 12 \r7__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \r7__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 15 \r7__ren
+ wire input 13 \r7__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 4 \reg$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 5 \src17__data_o
+ wire width 4 output 3 \src17__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src17__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 4 \src17__ren
+ wire input 2 \src17__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 7 \src27__data_o
+ wire width 4 output 5 \src27__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src27__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 6 \src27__ren
+ wire input 4 \src27__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 output 9 \src37__data_o
+ wire width 4 output 7 \src37__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 \src37__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 8 \src37__ren
+ wire input 6 \src37__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 4 input 18 \w7__data_i
+ wire width 4 input 16 \w7__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire input 19 \w7__wen
+ wire input 17 \w7__wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- wire \wr_detect$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184494$11772
+ cell $not $not$libresoc.v:183511$11601
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:184494$11772_Y
+ connect \Y $not$libresoc.v:183511$11601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184495$11773
+ cell $not $not$libresoc.v:183512$11602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:184495$11773_Y
+ connect \Y $not$libresoc.v:183512$11602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184496$11774
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$16
- connect \Y $not$libresoc.v:184496$11774_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184497$11775
+ cell $not $not$libresoc.v:183513$11603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:184497$11775_Y
+ connect \Y $not$libresoc.v:183513$11603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184498$11776
+ cell $not $not$libresoc.v:183514$11604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:184498$11776_Y
+ connect \Y $not$libresoc.v:183514$11604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:184499$11777
+ cell $not $not$libresoc.v:183515$11605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:184499$11777_Y
+ connect \Y $not$libresoc.v:183515$11605_Y
end
- attribute \src "libresoc.v:184407.7-184407.20"
- process $proc$libresoc.v:184407$11870
+ attribute \src "libresoc.v:183435.7-183435.20"
+ process $proc$libresoc.v:183435$11683
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184426.13-184426.36"
- process $proc$libresoc.v:184426$11871
- assign { } { }
- assign $1\cr_pred7__data_o[3:0] 4'0000
- sync always
- sync init
- update \cr_pred7__data_o $1\cr_pred7__data_o[3:0]
- end
- attribute \src "libresoc.v:184441.13-184441.31"
- process $proc$libresoc.v:184441$11872
+ attribute \src "libresoc.v:183460.13-183460.31"
+ process $proc$libresoc.v:183460$11684
assign { } { }
assign $1\r27__data_o[3:0] 4'0000
sync always
sync init
update \r27__data_o $1\r27__data_o[3:0]
end
- attribute \src "libresoc.v:184448.13-184448.30"
- process $proc$libresoc.v:184448$11873
+ attribute \src "libresoc.v:183467.13-183467.30"
+ process $proc$libresoc.v:183467$11685
assign { } { }
assign $1\r7__data_o[3:0] 4'0000
sync always
sync init
update \r7__data_o $1\r7__data_o[3:0]
end
- attribute \src "libresoc.v:184454.13-184454.25"
- process $proc$libresoc.v:184454$11874
+ attribute \src "libresoc.v:183473.13-183473.25"
+ process $proc$libresoc.v:183473$11686
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:184459.13-184459.33"
- process $proc$libresoc.v:184459$11875
+ attribute \src "libresoc.v:183478.13-183478.33"
+ process $proc$libresoc.v:183478$11687
assign { } { }
assign $1\src17__data_o[3:0] 4'0000
sync always
sync init
update \src17__data_o $1\src17__data_o[3:0]
end
- attribute \src "libresoc.v:184466.13-184466.33"
- process $proc$libresoc.v:184466$11876
+ attribute \src "libresoc.v:183485.13-183485.33"
+ process $proc$libresoc.v:183485$11688
assign { } { }
assign $1\src27__data_o[3:0] 4'0000
sync always
sync init
update \src27__data_o $1\src27__data_o[3:0]
end
- attribute \src "libresoc.v:184473.13-184473.33"
- process $proc$libresoc.v:184473$11877
+ attribute \src "libresoc.v:183492.13-183492.33"
+ process $proc$libresoc.v:183492$11689
assign { } { }
assign $1\src37__data_o[3:0] 4'0000
sync always
sync init
update \src37__data_o $1\src37__data_o[3:0]
end
- attribute \src "libresoc.v:184500.3-184501.25"
- process $proc$libresoc.v:184500$11778
+ attribute \src "libresoc.v:183516.3-183517.25"
+ process $proc$libresoc.v:183516$11606
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:184502.3-184503.39"
- process $proc$libresoc.v:184502$11779
+ attribute \src "libresoc.v:183518.3-183519.39"
+ process $proc$libresoc.v:183518$11607
assign { } { }
assign $0\r27__data_o[3:0] \r27__data_o$next
sync posedge \coresync_clk
update \r27__data_o $0\r27__data_o[3:0]
end
- attribute \src "libresoc.v:184504.3-184505.37"
- process $proc$libresoc.v:184504$11780
+ attribute \src "libresoc.v:183520.3-183521.37"
+ process $proc$libresoc.v:183520$11608
assign { } { }
assign $0\r7__data_o[3:0] \r7__data_o$next
sync posedge \coresync_clk
update \r7__data_o $0\r7__data_o[3:0]
end
- attribute \src "libresoc.v:184506.3-184507.43"
- process $proc$libresoc.v:184506$11781
+ attribute \src "libresoc.v:183522.3-183523.43"
+ process $proc$libresoc.v:183522$11609
assign { } { }
assign $0\src37__data_o[3:0] \src37__data_o$next
sync posedge \coresync_clk
update \src37__data_o $0\src37__data_o[3:0]
end
- attribute \src "libresoc.v:184508.3-184509.43"
- process $proc$libresoc.v:184508$11782
+ attribute \src "libresoc.v:183524.3-183525.43"
+ process $proc$libresoc.v:183524$11610
assign { } { }
assign $0\src27__data_o[3:0] \src27__data_o$next
sync posedge \coresync_clk
update \src27__data_o $0\src27__data_o[3:0]
end
- attribute \src "libresoc.v:184510.3-184511.43"
- process $proc$libresoc.v:184510$11783
+ attribute \src "libresoc.v:183526.3-183527.43"
+ process $proc$libresoc.v:183526$11611
assign { } { }
assign $0\src17__data_o[3:0] \src17__data_o$next
sync posedge \coresync_clk
update \src17__data_o $0\src17__data_o[3:0]
end
- attribute \src "libresoc.v:184512.3-184513.49"
- process $proc$libresoc.v:184512$11784
+ attribute \src "libresoc.v:183528.3-183567.6"
+ process $proc$libresoc.v:183528$11612
assign { } { }
- assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next
- sync posedge \coresync_clk
- update \cr_pred7__data_o $0\cr_pred7__data_o[3:0]
- end
- attribute \src "libresoc.v:184514.3-184553.6"
- process $proc$libresoc.v:184514$11785
assign { } { }
assign { } { }
- assign { } { }
- assign $0\cr_pred7__data_o$next[3:0]$11786 $6\cr_pred7__data_o$next[3:0]$11792
- attribute \src "libresoc.v:184515.5-184515.29"
+ assign $0\src17__data_o$next[3:0]$11613 $6\src17__data_o$next[3:0]$11619
+ attribute \src "libresoc.v:183529.5-183529.29"
switch \initial
- attribute \src "libresoc.v:184515.9-184515.17"
+ attribute \src "libresoc.v:183529.9-183529.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred7__ren
+ switch \src17__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_pred7__data_o$next[3:0]$11787 $5\cr_pred7__data_o$next[3:0]$11791
+ assign $1\src17__data_o$next[3:0]$11614 $5\src17__data_o$next[3:0]$11618
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_pred7__data_o$next[3:0]$11788 \dest17__data_i
+ assign $2\src17__data_o$next[3:0]$11615 \dest17__data_i
case
- assign $2\cr_pred7__data_o$next[3:0]$11788 4'0000
+ assign $2\src17__data_o$next[3:0]$11615 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cr_pred7__data_o$next[3:0]$11789 \dest27__data_i
+ assign $3\src17__data_o$next[3:0]$11616 \dest27__data_i
case
- assign $3\cr_pred7__data_o$next[3:0]$11789 $2\cr_pred7__data_o$next[3:0]$11788
+ assign $3\src17__data_o$next[3:0]$11616 $2\src17__data_o$next[3:0]$11615
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cr_pred7__data_o$next[3:0]$11790 \w7__data_i
+ assign $4\src17__data_o$next[3:0]$11617 \w7__data_i
case
- assign $4\cr_pred7__data_o$next[3:0]$11790 $3\cr_pred7__data_o$next[3:0]$11789
+ assign $4\src17__data_o$next[3:0]$11617 $3\src17__data_o$next[3:0]$11616
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cr_pred7__data_o$next[3:0]$11791 \reg
+ assign $5\src17__data_o$next[3:0]$11618 \reg
case
- assign $5\cr_pred7__data_o$next[3:0]$11791 $4\cr_pred7__data_o$next[3:0]$11790
+ assign $5\src17__data_o$next[3:0]$11618 $4\src17__data_o$next[3:0]$11617
end
case
- assign $1\cr_pred7__data_o$next[3:0]$11787 4'0000
+ assign $1\src17__data_o$next[3:0]$11614 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cr_pred7__data_o$next[3:0]$11792 4'0000
+ assign $6\src17__data_o$next[3:0]$11619 4'0000
case
- assign $6\cr_pred7__data_o$next[3:0]$11792 $1\cr_pred7__data_o$next[3:0]$11787
+ assign $6\src17__data_o$next[3:0]$11619 $1\src17__data_o$next[3:0]$11614
end
sync always
- update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11786
+ update \src17__data_o$next $0\src17__data_o$next[3:0]$11613
end
- attribute \src "libresoc.v:184554.3-184583.6"
- process $proc$libresoc.v:184554$11793
+ attribute \src "libresoc.v:183568.3-183597.6"
+ process $proc$libresoc.v:183568$11620
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:184555.5-184555.29"
+ attribute \src "libresoc.v:183569.5-183569.29"
switch \initial
- attribute \src "libresoc.v:184555.9-184555.17"
+ attribute \src "libresoc.v:183569.9-183569.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \cr_pred7__ren
+ switch \src17__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:184584.3-184623.6"
- process $proc$libresoc.v:184584$11794
+ attribute \src "libresoc.v:183598.3-183624.6"
+ process $proc$libresoc.v:183598$11621
+ assign { } { }
+ assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\r27__data_o$next[3:0]$11795 $6\r27__data_o$next[3:0]$11801
- attribute \src "libresoc.v:184585.5-184585.29"
+ assign $0\reg$next[3:0]$11622 $4\reg$next[3:0]$11626
+ attribute \src "libresoc.v:183599.5-183599.29"
switch \initial
- attribute \src "libresoc.v:184585.9-184585.17"
+ attribute \src "libresoc.v:183599.9-183599.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r27__ren
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
+ assign $1\reg$next[3:0]$11623 \dest17__data_i
+ case
+ assign $1\reg$next[3:0]$11623 \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \dest27__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
+ assign $2\reg$next[3:0]$11624 \dest27__data_i
+ case
+ assign $2\reg$next[3:0]$11624 $1\reg$next[3:0]$11623
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
+ switch \w7__wen
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
assign { } { }
- assign { } { }
- assign $1\r27__data_o$next[3:0]$11796 $5\r27__data_o$next[3:0]$11800
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest17__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r27__data_o$next[3:0]$11797 \dest17__data_i
- case
- assign $2\r27__data_o$next[3:0]$11797 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest27__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\r27__data_o$next[3:0]$11798 \dest27__data_i
- case
- assign $3\r27__data_o$next[3:0]$11798 $2\r27__data_o$next[3:0]$11797
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w7__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\r27__data_o$next[3:0]$11799 \w7__data_i
- case
- assign $4\r27__data_o$next[3:0]$11799 $3\r27__data_o$next[3:0]$11798
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- switch \$15
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\r27__data_o$next[3:0]$11800 \reg
- case
- assign $5\r27__data_o$next[3:0]$11800 $4\r27__data_o$next[3:0]$11799
- end
+ assign $3\reg$next[3:0]$11625 \w7__data_i
case
- assign $1\r27__data_o$next[3:0]$11796 4'0000
+ assign $3\reg$next[3:0]$11625 $2\reg$next[3:0]$11624
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r27__data_o$next[3:0]$11801 4'0000
+ assign $4\reg$next[3:0]$11626 4'0000
case
- assign $6\r27__data_o$next[3:0]$11801 $1\r27__data_o$next[3:0]$11796
+ assign $4\reg$next[3:0]$11626 $3\reg$next[3:0]$11625
end
sync always
- update \r27__data_o$next $0\r27__data_o$next[3:0]$11795
+ update \reg$next $0\reg$next[3:0]$11622
end
- attribute \src "libresoc.v:184624.3-184653.6"
- process $proc$libresoc.v:184624$11802
+ attribute \src "libresoc.v:183625.3-183664.6"
+ process $proc$libresoc.v:183625$11627
+ assign { } { }
assign { } { }
assign { } { }
- assign $0\wr_detect$16[0:0]$11803 $1\wr_detect$16[0:0]$11804
- attribute \src "libresoc.v:184625.5-184625.29"
+ assign $0\src27__data_o$next[3:0]$11628 $6\src27__data_o$next[3:0]$11634
+ attribute \src "libresoc.v:183626.5-183626.29"
switch \initial
- attribute \src "libresoc.v:184625.9-184625.17"
+ attribute \src "libresoc.v:183626.9-183626.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r27__ren
+ switch \src27__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$16[0:0]$11804 $4\wr_detect$16[0:0]$11807
+ assign $1\src27__data_o$next[3:0]$11629 $5\src27__data_o$next[3:0]$11633
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$16[0:0]$11805 1'1
+ assign $2\src27__data_o$next[3:0]$11630 \dest17__data_i
case
- assign $2\wr_detect$16[0:0]$11805 1'0
+ assign $2\src27__data_o$next[3:0]$11630 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$16[0:0]$11806 1'1
+ assign $3\src27__data_o$next[3:0]$11631 \dest27__data_i
case
- assign $3\wr_detect$16[0:0]$11806 $2\wr_detect$16[0:0]$11805
+ assign $3\src27__data_o$next[3:0]$11631 $2\src27__data_o$next[3:0]$11630
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$16[0:0]$11807 1'1
+ assign $4\src27__data_o$next[3:0]$11632 \w7__data_i
case
- assign $4\wr_detect$16[0:0]$11807 $3\wr_detect$16[0:0]$11806
- end
- case
- assign $1\wr_detect$16[0:0]$11804 1'0
- end
- sync always
- update \wr_detect$16 $0\wr_detect$16[0:0]$11803
- end
- attribute \src "libresoc.v:184654.3-184680.6"
- process $proc$libresoc.v:184654$11808
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\reg$next[3:0]$11809 $4\reg$next[3:0]$11813
- attribute \src "libresoc.v:184655.5-184655.29"
- switch \initial
- attribute \src "libresoc.v:184655.9-184655.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest17__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg$next[3:0]$11810 \dest17__data_i
- case
- assign $1\reg$next[3:0]$11810 \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \dest27__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\reg$next[3:0]$11811 \dest27__data_i
- case
- assign $2\reg$next[3:0]$11811 $1\reg$next[3:0]$11810
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
- switch \w7__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\reg$next[3:0]$11812 \w7__data_i
- case
- assign $3\reg$next[3:0]$11812 $2\reg$next[3:0]$11811
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\reg$next[3:0]$11813 4'0000
- case
- assign $4\reg$next[3:0]$11813 $3\reg$next[3:0]$11812
- end
- sync always
- update \reg$next $0\reg$next[3:0]$11809
- end
- attribute \src "libresoc.v:184681.3-184720.6"
- process $proc$libresoc.v:184681$11814
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\src17__data_o$next[3:0]$11815 $6\src17__data_o$next[3:0]$11821
- attribute \src "libresoc.v:184682.5-184682.29"
- switch \initial
- attribute \src "libresoc.v:184682.9-184682.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src17__ren
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $1\src17__data_o$next[3:0]$11816 $5\src17__data_o$next[3:0]$11820
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest17__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\src17__data_o$next[3:0]$11817 \dest17__data_i
- case
- assign $2\src17__data_o$next[3:0]$11817 4'0000
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \dest27__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\src17__data_o$next[3:0]$11818 \dest27__data_i
- case
- assign $3\src17__data_o$next[3:0]$11818 $2\src17__data_o$next[3:0]$11817
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
- switch \w7__wen
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\src17__data_o$next[3:0]$11819 \w7__data_i
- case
- assign $4\src17__data_o$next[3:0]$11819 $3\src17__data_o$next[3:0]$11818
+ assign $4\src27__data_o$next[3:0]$11632 $3\src27__data_o$next[3:0]$11631
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src17__data_o$next[3:0]$11820 \reg
+ assign $5\src27__data_o$next[3:0]$11633 \reg
case
- assign $5\src17__data_o$next[3:0]$11820 $4\src17__data_o$next[3:0]$11819
+ assign $5\src27__data_o$next[3:0]$11633 $4\src27__data_o$next[3:0]$11632
end
case
- assign $1\src17__data_o$next[3:0]$11816 4'0000
+ assign $1\src27__data_o$next[3:0]$11629 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src17__data_o$next[3:0]$11821 4'0000
+ assign $6\src27__data_o$next[3:0]$11634 4'0000
case
- assign $6\src17__data_o$next[3:0]$11821 $1\src17__data_o$next[3:0]$11816
+ assign $6\src27__data_o$next[3:0]$11634 $1\src27__data_o$next[3:0]$11629
end
sync always
- update \src17__data_o$next $0\src17__data_o$next[3:0]$11815
+ update \src27__data_o$next $0\src27__data_o$next[3:0]$11628
end
- attribute \src "libresoc.v:184721.3-184750.6"
- process $proc$libresoc.v:184721$11822
+ attribute \src "libresoc.v:183665.3-183694.6"
+ process $proc$libresoc.v:183665$11635
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11823 $1\wr_detect$4[0:0]$11824
- attribute \src "libresoc.v:184722.5-184722.29"
+ assign $0\wr_detect$4[0:0]$11636 $1\wr_detect$4[0:0]$11637
+ attribute \src "libresoc.v:183666.5-183666.29"
switch \initial
- attribute \src "libresoc.v:184722.9-184722.17"
+ attribute \src "libresoc.v:183666.9-183666.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src17__ren
+ switch \src27__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11824 $4\wr_detect$4[0:0]$11827
+ assign $1\wr_detect$4[0:0]$11637 $4\wr_detect$4[0:0]$11640
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11825 1'1
+ assign $2\wr_detect$4[0:0]$11638 1'1
case
- assign $2\wr_detect$4[0:0]$11825 1'0
+ assign $2\wr_detect$4[0:0]$11638 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11826 1'1
+ assign $3\wr_detect$4[0:0]$11639 1'1
case
- assign $3\wr_detect$4[0:0]$11826 $2\wr_detect$4[0:0]$11825
+ assign $3\wr_detect$4[0:0]$11639 $2\wr_detect$4[0:0]$11638
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11827 1'1
+ assign $4\wr_detect$4[0:0]$11640 1'1
case
- assign $4\wr_detect$4[0:0]$11827 $3\wr_detect$4[0:0]$11826
+ assign $4\wr_detect$4[0:0]$11640 $3\wr_detect$4[0:0]$11639
end
case
- assign $1\wr_detect$4[0:0]$11824 1'0
+ assign $1\wr_detect$4[0:0]$11637 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11823
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11636
end
- attribute \src "libresoc.v:184751.3-184790.6"
- process $proc$libresoc.v:184751$11828
+ attribute \src "libresoc.v:183695.3-183734.6"
+ process $proc$libresoc.v:183695$11641
assign { } { }
assign { } { }
assign { } { }
- assign $0\src27__data_o$next[3:0]$11829 $6\src27__data_o$next[3:0]$11835
- attribute \src "libresoc.v:184752.5-184752.29"
+ assign $0\src37__data_o$next[3:0]$11642 $6\src37__data_o$next[3:0]$11648
+ attribute \src "libresoc.v:183696.5-183696.29"
switch \initial
- attribute \src "libresoc.v:184752.9-184752.17"
+ attribute \src "libresoc.v:183696.9-183696.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src27__ren
+ switch \src37__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src27__data_o$next[3:0]$11830 $5\src27__data_o$next[3:0]$11834
+ assign $1\src37__data_o$next[3:0]$11643 $5\src37__data_o$next[3:0]$11647
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src27__data_o$next[3:0]$11831 \dest17__data_i
+ assign $2\src37__data_o$next[3:0]$11644 \dest17__data_i
case
- assign $2\src27__data_o$next[3:0]$11831 4'0000
+ assign $2\src37__data_o$next[3:0]$11644 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src27__data_o$next[3:0]$11832 \dest27__data_i
+ assign $3\src37__data_o$next[3:0]$11645 \dest27__data_i
case
- assign $3\src27__data_o$next[3:0]$11832 $2\src27__data_o$next[3:0]$11831
+ assign $3\src37__data_o$next[3:0]$11645 $2\src37__data_o$next[3:0]$11644
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src27__data_o$next[3:0]$11833 \w7__data_i
+ assign $4\src37__data_o$next[3:0]$11646 \w7__data_i
case
- assign $4\src27__data_o$next[3:0]$11833 $3\src27__data_o$next[3:0]$11832
+ assign $4\src37__data_o$next[3:0]$11646 $3\src37__data_o$next[3:0]$11645
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src27__data_o$next[3:0]$11834 \reg
+ assign $5\src37__data_o$next[3:0]$11647 \reg
case
- assign $5\src27__data_o$next[3:0]$11834 $4\src27__data_o$next[3:0]$11833
+ assign $5\src37__data_o$next[3:0]$11647 $4\src37__data_o$next[3:0]$11646
end
case
- assign $1\src27__data_o$next[3:0]$11830 4'0000
+ assign $1\src37__data_o$next[3:0]$11643 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src27__data_o$next[3:0]$11835 4'0000
+ assign $6\src37__data_o$next[3:0]$11648 4'0000
case
- assign $6\src27__data_o$next[3:0]$11835 $1\src27__data_o$next[3:0]$11830
+ assign $6\src37__data_o$next[3:0]$11648 $1\src37__data_o$next[3:0]$11643
end
sync always
- update \src27__data_o$next $0\src27__data_o$next[3:0]$11829
+ update \src37__data_o$next $0\src37__data_o$next[3:0]$11642
end
- attribute \src "libresoc.v:184791.3-184820.6"
- process $proc$libresoc.v:184791$11836
+ attribute \src "libresoc.v:183735.3-183764.6"
+ process $proc$libresoc.v:183735$11649
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11837 $1\wr_detect$7[0:0]$11838
- attribute \src "libresoc.v:184792.5-184792.29"
+ assign $0\wr_detect$7[0:0]$11650 $1\wr_detect$7[0:0]$11651
+ attribute \src "libresoc.v:183736.5-183736.29"
switch \initial
- attribute \src "libresoc.v:184792.9-184792.17"
+ attribute \src "libresoc.v:183736.9-183736.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src27__ren
+ switch \src37__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11838 $4\wr_detect$7[0:0]$11841
+ assign $1\wr_detect$7[0:0]$11651 $4\wr_detect$7[0:0]$11654
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11839 1'1
+ assign $2\wr_detect$7[0:0]$11652 1'1
case
- assign $2\wr_detect$7[0:0]$11839 1'0
+ assign $2\wr_detect$7[0:0]$11652 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11840 1'1
+ assign $3\wr_detect$7[0:0]$11653 1'1
case
- assign $3\wr_detect$7[0:0]$11840 $2\wr_detect$7[0:0]$11839
+ assign $3\wr_detect$7[0:0]$11653 $2\wr_detect$7[0:0]$11652
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11841 1'1
+ assign $4\wr_detect$7[0:0]$11654 1'1
case
- assign $4\wr_detect$7[0:0]$11841 $3\wr_detect$7[0:0]$11840
+ assign $4\wr_detect$7[0:0]$11654 $3\wr_detect$7[0:0]$11653
end
case
- assign $1\wr_detect$7[0:0]$11838 1'0
+ assign $1\wr_detect$7[0:0]$11651 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11837
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11650
end
- attribute \src "libresoc.v:184821.3-184860.6"
- process $proc$libresoc.v:184821$11842
+ attribute \src "libresoc.v:183765.3-183804.6"
+ process $proc$libresoc.v:183765$11655
assign { } { }
assign { } { }
assign { } { }
- assign $0\src37__data_o$next[3:0]$11843 $6\src37__data_o$next[3:0]$11849
- attribute \src "libresoc.v:184822.5-184822.29"
+ assign $0\r7__data_o$next[3:0]$11656 $6\r7__data_o$next[3:0]$11662
+ attribute \src "libresoc.v:183766.5-183766.29"
switch \initial
- attribute \src "libresoc.v:184822.9-184822.17"
+ attribute \src "libresoc.v:183766.9-183766.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src37__ren
+ switch \r7__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\src37__data_o$next[3:0]$11844 $5\src37__data_o$next[3:0]$11848
+ assign $1\r7__data_o$next[3:0]$11657 $5\r7__data_o$next[3:0]$11661
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src37__data_o$next[3:0]$11845 \dest17__data_i
+ assign $2\r7__data_o$next[3:0]$11658 \dest17__data_i
case
- assign $2\src37__data_o$next[3:0]$11845 4'0000
+ assign $2\r7__data_o$next[3:0]$11658 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src37__data_o$next[3:0]$11846 \dest27__data_i
+ assign $3\r7__data_o$next[3:0]$11659 \dest27__data_i
case
- assign $3\src37__data_o$next[3:0]$11846 $2\src37__data_o$next[3:0]$11845
+ assign $3\r7__data_o$next[3:0]$11659 $2\r7__data_o$next[3:0]$11658
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src37__data_o$next[3:0]$11847 \w7__data_i
+ assign $4\r7__data_o$next[3:0]$11660 \w7__data_i
case
- assign $4\src37__data_o$next[3:0]$11847 $3\src37__data_o$next[3:0]$11846
+ assign $4\r7__data_o$next[3:0]$11660 $3\r7__data_o$next[3:0]$11659
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src37__data_o$next[3:0]$11848 \reg
+ assign $5\r7__data_o$next[3:0]$11661 \reg
case
- assign $5\src37__data_o$next[3:0]$11848 $4\src37__data_o$next[3:0]$11847
+ assign $5\r7__data_o$next[3:0]$11661 $4\r7__data_o$next[3:0]$11660
end
case
- assign $1\src37__data_o$next[3:0]$11844 4'0000
+ assign $1\r7__data_o$next[3:0]$11657 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src37__data_o$next[3:0]$11849 4'0000
+ assign $6\r7__data_o$next[3:0]$11662 4'0000
case
- assign $6\src37__data_o$next[3:0]$11849 $1\src37__data_o$next[3:0]$11844
+ assign $6\r7__data_o$next[3:0]$11662 $1\r7__data_o$next[3:0]$11657
end
sync always
- update \src37__data_o$next $0\src37__data_o$next[3:0]$11843
+ update \r7__data_o$next $0\r7__data_o$next[3:0]$11656
end
- attribute \src "libresoc.v:184861.3-184890.6"
- process $proc$libresoc.v:184861$11850
+ attribute \src "libresoc.v:183805.3-183834.6"
+ process $proc$libresoc.v:183805$11663
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11851 $1\wr_detect$10[0:0]$11852
- attribute \src "libresoc.v:184862.5-184862.29"
+ assign $0\wr_detect$10[0:0]$11664 $1\wr_detect$10[0:0]$11665
+ attribute \src "libresoc.v:183806.5-183806.29"
switch \initial
- attribute \src "libresoc.v:184862.9-184862.17"
+ attribute \src "libresoc.v:183806.9-183806.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \src37__ren
+ switch \r7__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11852 $4\wr_detect$10[0:0]$11855
+ assign $1\wr_detect$10[0:0]$11665 $4\wr_detect$10[0:0]$11668
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11853 1'1
+ assign $2\wr_detect$10[0:0]$11666 1'1
case
- assign $2\wr_detect$10[0:0]$11853 1'0
+ assign $2\wr_detect$10[0:0]$11666 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11854 1'1
+ assign $3\wr_detect$10[0:0]$11667 1'1
case
- assign $3\wr_detect$10[0:0]$11854 $2\wr_detect$10[0:0]$11853
+ assign $3\wr_detect$10[0:0]$11667 $2\wr_detect$10[0:0]$11666
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11855 1'1
+ assign $4\wr_detect$10[0:0]$11668 1'1
case
- assign $4\wr_detect$10[0:0]$11855 $3\wr_detect$10[0:0]$11854
+ assign $4\wr_detect$10[0:0]$11668 $3\wr_detect$10[0:0]$11667
end
case
- assign $1\wr_detect$10[0:0]$11852 1'0
+ assign $1\wr_detect$10[0:0]$11665 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11851
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11664
end
- attribute \src "libresoc.v:184891.3-184930.6"
- process $proc$libresoc.v:184891$11856
+ attribute \src "libresoc.v:183835.3-183874.6"
+ process $proc$libresoc.v:183835$11669
assign { } { }
assign { } { }
assign { } { }
- assign $0\r7__data_o$next[3:0]$11857 $6\r7__data_o$next[3:0]$11863
- attribute \src "libresoc.v:184892.5-184892.29"
+ assign $0\r27__data_o$next[3:0]$11670 $6\r27__data_o$next[3:0]$11676
+ attribute \src "libresoc.v:183836.5-183836.29"
switch \initial
- attribute \src "libresoc.v:184892.9-184892.17"
+ attribute \src "libresoc.v:183836.9-183836.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r7__ren
+ switch \r27__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\r7__data_o$next[3:0]$11858 $5\r7__data_o$next[3:0]$11862
+ assign $1\r27__data_o$next[3:0]$11671 $5\r27__data_o$next[3:0]$11675
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r7__data_o$next[3:0]$11859 \dest17__data_i
+ assign $2\r27__data_o$next[3:0]$11672 \dest17__data_i
case
- assign $2\r7__data_o$next[3:0]$11859 4'0000
+ assign $2\r27__data_o$next[3:0]$11672 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r7__data_o$next[3:0]$11860 \dest27__data_i
+ assign $3\r27__data_o$next[3:0]$11673 \dest27__data_i
case
- assign $3\r7__data_o$next[3:0]$11860 $2\r7__data_o$next[3:0]$11859
+ assign $3\r27__data_o$next[3:0]$11673 $2\r27__data_o$next[3:0]$11672
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r7__data_o$next[3:0]$11861 \w7__data_i
+ assign $4\r27__data_o$next[3:0]$11674 \w7__data_i
case
- assign $4\r7__data_o$next[3:0]$11861 $3\r7__data_o$next[3:0]$11860
+ assign $4\r27__data_o$next[3:0]$11674 $3\r27__data_o$next[3:0]$11673
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r7__data_o$next[3:0]$11862 \reg
+ assign $5\r27__data_o$next[3:0]$11675 \reg
case
- assign $5\r7__data_o$next[3:0]$11862 $4\r7__data_o$next[3:0]$11861
+ assign $5\r27__data_o$next[3:0]$11675 $4\r27__data_o$next[3:0]$11674
end
case
- assign $1\r7__data_o$next[3:0]$11858 4'0000
+ assign $1\r27__data_o$next[3:0]$11671 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r7__data_o$next[3:0]$11863 4'0000
+ assign $6\r27__data_o$next[3:0]$11676 4'0000
case
- assign $6\r7__data_o$next[3:0]$11863 $1\r7__data_o$next[3:0]$11858
+ assign $6\r27__data_o$next[3:0]$11676 $1\r27__data_o$next[3:0]$11671
end
sync always
- update \r7__data_o$next $0\r7__data_o$next[3:0]$11857
+ update \r27__data_o$next $0\r27__data_o$next[3:0]$11670
end
- attribute \src "libresoc.v:184931.3-184960.6"
- process $proc$libresoc.v:184931$11864
+ attribute \src "libresoc.v:183875.3-183904.6"
+ process $proc$libresoc.v:183875$11677
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11865 $1\wr_detect$13[0:0]$11866
- attribute \src "libresoc.v:184932.5-184932.29"
+ assign $0\wr_detect$13[0:0]$11678 $1\wr_detect$13[0:0]$11679
+ attribute \src "libresoc.v:183876.5-183876.29"
switch \initial
- attribute \src "libresoc.v:184932.9-184932.17"
+ attribute \src "libresoc.v:183876.9-183876.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
- switch \r7__ren
+ switch \r27__ren
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11866 $4\wr_detect$13[0:0]$11869
+ assign $1\wr_detect$13[0:0]$11679 $4\wr_detect$13[0:0]$11682
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11867 1'1
+ assign $2\wr_detect$13[0:0]$11680 1'1
case
- assign $2\wr_detect$13[0:0]$11867 1'0
+ assign $2\wr_detect$13[0:0]$11680 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11868 1'1
+ assign $3\wr_detect$13[0:0]$11681 1'1
case
- assign $3\wr_detect$13[0:0]$11868 $2\wr_detect$13[0:0]$11867
+ assign $3\wr_detect$13[0:0]$11681 $2\wr_detect$13[0:0]$11680
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11869 1'1
+ assign $4\wr_detect$13[0:0]$11682 1'1
case
- assign $4\wr_detect$13[0:0]$11869 $3\wr_detect$13[0:0]$11868
+ assign $4\wr_detect$13[0:0]$11682 $3\wr_detect$13[0:0]$11681
end
case
- assign $1\wr_detect$13[0:0]$11866 1'0
+ assign $1\wr_detect$13[0:0]$11679 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11865
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11678
end
- connect \$9 $not$libresoc.v:184494$11772_Y
- connect \$12 $not$libresoc.v:184495$11773_Y
- connect \$15 $not$libresoc.v:184496$11774_Y
- connect \$1 $not$libresoc.v:184497$11775_Y
- connect \$3 $not$libresoc.v:184498$11776_Y
- connect \$6 $not$libresoc.v:184499$11777_Y
+ connect \$9 $not$libresoc.v:183511$11601_Y
+ connect \$12 $not$libresoc.v:183512$11602_Y
+ connect \$1 $not$libresoc.v:183513$11603_Y
+ connect \$3 $not$libresoc.v:183514$11604_Y
+ connect \$6 $not$libresoc.v:183515$11605_Y
end
-attribute \src "libresoc.v:184965.1-185023.10"
+attribute \src "libresoc.v:183909.1-183967.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l"
attribute \generator "nMigen"
module \req_l
- attribute \src "libresoc.v:184966.7-184966.20"
+ attribute \src "libresoc.v:183910.7-183910.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185011.3-185019.6"
- wire width 5 $0\q_int$next[4:0]$11888
- attribute \src "libresoc.v:185009.3-185010.27"
+ attribute \src "libresoc.v:183955.3-183963.6"
+ wire width 5 $0\q_int$next[4:0]$11700
+ attribute \src "libresoc.v:183953.3-183954.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:185011.3-185019.6"
- wire width 5 $1\q_int$next[4:0]$11889
- attribute \src "libresoc.v:184988.13-184988.26"
+ attribute \src "libresoc.v:183955.3-183963.6"
+ wire width 5 $1\q_int$next[4:0]$11701
+ attribute \src "libresoc.v:183932.13-183932.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:185001.17-185001.96"
- wire width 5 $and$libresoc.v:185001$11878_Y
- attribute \src "libresoc.v:185006.17-185006.96"
- wire width 5 $and$libresoc.v:185006$11883_Y
- attribute \src "libresoc.v:185003.18-185003.93"
- wire width 5 $not$libresoc.v:185003$11880_Y
- attribute \src "libresoc.v:185005.17-185005.92"
- wire width 5 $not$libresoc.v:185005$11882_Y
- attribute \src "libresoc.v:185008.17-185008.92"
- wire width 5 $not$libresoc.v:185008$11885_Y
- attribute \src "libresoc.v:185002.18-185002.98"
- wire width 5 $or$libresoc.v:185002$11879_Y
- attribute \src "libresoc.v:185004.18-185004.99"
- wire width 5 $or$libresoc.v:185004$11881_Y
- attribute \src "libresoc.v:185007.17-185007.97"
- wire width 5 $or$libresoc.v:185007$11884_Y
+ attribute \src "libresoc.v:183945.17-183945.96"
+ wire width 5 $and$libresoc.v:183945$11690_Y
+ attribute \src "libresoc.v:183950.17-183950.96"
+ wire width 5 $and$libresoc.v:183950$11695_Y
+ attribute \src "libresoc.v:183947.18-183947.93"
+ wire width 5 $not$libresoc.v:183947$11692_Y
+ attribute \src "libresoc.v:183949.17-183949.92"
+ wire width 5 $not$libresoc.v:183949$11694_Y
+ attribute \src "libresoc.v:183952.17-183952.92"
+ wire width 5 $not$libresoc.v:183952$11697_Y
+ attribute \src "libresoc.v:183946.18-183946.98"
+ wire width 5 $or$libresoc.v:183946$11691_Y
+ attribute \src "libresoc.v:183948.18-183948.99"
+ wire width 5 $or$libresoc.v:183948$11693_Y
+ attribute \src "libresoc.v:183951.17-183951.97"
+ wire width 5 $or$libresoc.v:183951$11696_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184966.7-184966.15"
+ attribute \src "libresoc.v:183910.7-183910.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185001$11878
+ cell $and $and$libresoc.v:183945$11690
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185001$11878_Y
+ connect \Y $and$libresoc.v:183945$11690_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185006$11883
+ cell $and $and$libresoc.v:183950$11695
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185006$11883_Y
+ connect \Y $and$libresoc.v:183950$11695_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185003$11880
+ cell $not $not$libresoc.v:183947$11692
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_req
- connect \Y $not$libresoc.v:185003$11880_Y
+ connect \Y $not$libresoc.v:183947$11692_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185005$11882
+ cell $not $not$libresoc.v:183949$11694
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:185005$11882_Y
+ connect \Y $not$libresoc.v:183949$11694_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185008$11885
+ cell $not $not$libresoc.v:183952$11697
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:185008$11885_Y
+ connect \Y $not$libresoc.v:183952$11697_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185002$11879
+ cell $or $or$libresoc.v:183946$11691
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185002$11879_Y
+ connect \Y $or$libresoc.v:183946$11691_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185004$11881
+ cell $or $or$libresoc.v:183948$11693
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185004$11881_Y
+ connect \Y $or$libresoc.v:183948$11693_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185007$11884
+ cell $or $or$libresoc.v:183951$11696
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185007$11884_Y
+ connect \Y $or$libresoc.v:183951$11696_Y
end
- attribute \src "libresoc.v:184966.7-184966.20"
- process $proc$libresoc.v:184966$11890
+ attribute \src "libresoc.v:183910.7-183910.20"
+ process $proc$libresoc.v:183910$11702
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184988.13-184988.26"
- process $proc$libresoc.v:184988$11891
+ attribute \src "libresoc.v:183932.13-183932.26"
+ process $proc$libresoc.v:183932$11703
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:185009.3-185010.27"
- process $proc$libresoc.v:185009$11886
+ attribute \src "libresoc.v:183953.3-183954.27"
+ process $proc$libresoc.v:183953$11698
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:185011.3-185019.6"
- process $proc$libresoc.v:185011$11887
+ attribute \src "libresoc.v:183955.3-183963.6"
+ process $proc$libresoc.v:183955$11699
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$11888 $1\q_int$next[4:0]$11889
- attribute \src "libresoc.v:185012.5-185012.29"
+ assign $0\q_int$next[4:0]$11700 $1\q_int$next[4:0]$11701
+ attribute \src "libresoc.v:183956.5-183956.29"
switch \initial
- attribute \src "libresoc.v:185012.9-185012.17"
+ attribute \src "libresoc.v:183956.9-183956.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$11889 5'00000
+ assign $1\q_int$next[4:0]$11701 5'00000
case
- assign $1\q_int$next[4:0]$11889 \$5
+ assign $1\q_int$next[4:0]$11701 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$11888
+ update \q_int$next $0\q_int$next[4:0]$11700
end
- connect \$9 $and$libresoc.v:185001$11878_Y
- connect \$11 $or$libresoc.v:185002$11879_Y
- connect \$13 $not$libresoc.v:185003$11880_Y
- connect \$15 $or$libresoc.v:185004$11881_Y
- connect \$1 $not$libresoc.v:185005$11882_Y
- connect \$3 $and$libresoc.v:185006$11883_Y
- connect \$5 $or$libresoc.v:185007$11884_Y
- connect \$7 $not$libresoc.v:185008$11885_Y
+ connect \$9 $and$libresoc.v:183945$11690_Y
+ connect \$11 $or$libresoc.v:183946$11691_Y
+ connect \$13 $not$libresoc.v:183947$11692_Y
+ connect \$15 $or$libresoc.v:183948$11693_Y
+ connect \$1 $not$libresoc.v:183949$11694_Y
+ connect \$3 $and$libresoc.v:183950$11695_Y
+ connect \$5 $or$libresoc.v:183951$11696_Y
+ connect \$7 $not$libresoc.v:183952$11697_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185027.1-185085.10"
+attribute \src "libresoc.v:183971.1-184029.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l"
attribute \generator "nMigen"
module \req_l$103
- attribute \src "libresoc.v:185028.7-185028.20"
+ attribute \src "libresoc.v:183972.7-183972.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185073.3-185081.6"
- wire width 4 $0\q_int$next[3:0]$11902
- attribute \src "libresoc.v:185071.3-185072.27"
+ attribute \src "libresoc.v:184017.3-184025.6"
+ wire width 4 $0\q_int$next[3:0]$11714
+ attribute \src "libresoc.v:184015.3-184016.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:185073.3-185081.6"
- wire width 4 $1\q_int$next[3:0]$11903
- attribute \src "libresoc.v:185050.13-185050.25"
+ attribute \src "libresoc.v:184017.3-184025.6"
+ wire width 4 $1\q_int$next[3:0]$11715
+ attribute \src "libresoc.v:183994.13-183994.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:185063.17-185063.96"
- wire width 4 $and$libresoc.v:185063$11892_Y
- attribute \src "libresoc.v:185068.17-185068.96"
- wire width 4 $and$libresoc.v:185068$11897_Y
- attribute \src "libresoc.v:185065.18-185065.93"
- wire width 4 $not$libresoc.v:185065$11894_Y
- attribute \src "libresoc.v:185067.17-185067.92"
- wire width 4 $not$libresoc.v:185067$11896_Y
- attribute \src "libresoc.v:185070.17-185070.92"
- wire width 4 $not$libresoc.v:185070$11899_Y
- attribute \src "libresoc.v:185064.18-185064.98"
- wire width 4 $or$libresoc.v:185064$11893_Y
- attribute \src "libresoc.v:185066.18-185066.99"
- wire width 4 $or$libresoc.v:185066$11895_Y
- attribute \src "libresoc.v:185069.17-185069.97"
- wire width 4 $or$libresoc.v:185069$11898_Y
+ attribute \src "libresoc.v:184007.17-184007.96"
+ wire width 4 $and$libresoc.v:184007$11704_Y
+ attribute \src "libresoc.v:184012.17-184012.96"
+ wire width 4 $and$libresoc.v:184012$11709_Y
+ attribute \src "libresoc.v:184009.18-184009.93"
+ wire width 4 $not$libresoc.v:184009$11706_Y
+ attribute \src "libresoc.v:184011.17-184011.92"
+ wire width 4 $not$libresoc.v:184011$11708_Y
+ attribute \src "libresoc.v:184014.17-184014.92"
+ wire width 4 $not$libresoc.v:184014$11711_Y
+ attribute \src "libresoc.v:184008.18-184008.98"
+ wire width 4 $or$libresoc.v:184008$11705_Y
+ attribute \src "libresoc.v:184010.18-184010.99"
+ wire width 4 $or$libresoc.v:184010$11707_Y
+ attribute \src "libresoc.v:184013.17-184013.97"
+ wire width 4 $or$libresoc.v:184013$11710_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185028.7-185028.15"
+ attribute \src "libresoc.v:183972.7-183972.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185063$11892
+ cell $and $and$libresoc.v:184007$11704
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185063$11892_Y
+ connect \Y $and$libresoc.v:184007$11704_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185068$11897
+ cell $and $and$libresoc.v:184012$11709
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185068$11897_Y
+ connect \Y $and$libresoc.v:184012$11709_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185065$11894
+ cell $not $not$libresoc.v:184009$11706
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_req
- connect \Y $not$libresoc.v:185065$11894_Y
+ connect \Y $not$libresoc.v:184009$11706_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185067$11896
+ cell $not $not$libresoc.v:184011$11708
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:185067$11896_Y
+ connect \Y $not$libresoc.v:184011$11708_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185070$11899
+ cell $not $not$libresoc.v:184014$11711
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:185070$11899_Y
+ connect \Y $not$libresoc.v:184014$11711_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185064$11893
+ cell $or $or$libresoc.v:184008$11705
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185064$11893_Y
+ connect \Y $or$libresoc.v:184008$11705_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185066$11895
+ cell $or $or$libresoc.v:184010$11707
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185066$11895_Y
+ connect \Y $or$libresoc.v:184010$11707_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185069$11898
+ cell $or $or$libresoc.v:184013$11710
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185069$11898_Y
+ connect \Y $or$libresoc.v:184013$11710_Y
end
- attribute \src "libresoc.v:185028.7-185028.20"
- process $proc$libresoc.v:185028$11904
+ attribute \src "libresoc.v:183972.7-183972.20"
+ process $proc$libresoc.v:183972$11716
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185050.13-185050.25"
- process $proc$libresoc.v:185050$11905
+ attribute \src "libresoc.v:183994.13-183994.25"
+ process $proc$libresoc.v:183994$11717
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:185071.3-185072.27"
- process $proc$libresoc.v:185071$11900
+ attribute \src "libresoc.v:184015.3-184016.27"
+ process $proc$libresoc.v:184015$11712
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:185073.3-185081.6"
- process $proc$libresoc.v:185073$11901
+ attribute \src "libresoc.v:184017.3-184025.6"
+ process $proc$libresoc.v:184017$11713
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$11902 $1\q_int$next[3:0]$11903
- attribute \src "libresoc.v:185074.5-185074.29"
+ assign $0\q_int$next[3:0]$11714 $1\q_int$next[3:0]$11715
+ attribute \src "libresoc.v:184018.5-184018.29"
switch \initial
- attribute \src "libresoc.v:185074.9-185074.17"
+ attribute \src "libresoc.v:184018.9-184018.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$11903 4'0000
+ assign $1\q_int$next[3:0]$11715 4'0000
case
- assign $1\q_int$next[3:0]$11903 \$5
+ assign $1\q_int$next[3:0]$11715 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$11902
+ update \q_int$next $0\q_int$next[3:0]$11714
end
- connect \$9 $and$libresoc.v:185063$11892_Y
- connect \$11 $or$libresoc.v:185064$11893_Y
- connect \$13 $not$libresoc.v:185065$11894_Y
- connect \$15 $or$libresoc.v:185066$11895_Y
- connect \$1 $not$libresoc.v:185067$11896_Y
- connect \$3 $and$libresoc.v:185068$11897_Y
- connect \$5 $or$libresoc.v:185069$11898_Y
- connect \$7 $not$libresoc.v:185070$11899_Y
+ connect \$9 $and$libresoc.v:184007$11704_Y
+ connect \$11 $or$libresoc.v:184008$11705_Y
+ connect \$13 $not$libresoc.v:184009$11706_Y
+ connect \$15 $or$libresoc.v:184010$11707_Y
+ connect \$1 $not$libresoc.v:184011$11708_Y
+ connect \$3 $and$libresoc.v:184012$11709_Y
+ connect \$5 $or$libresoc.v:184013$11710_Y
+ connect \$7 $not$libresoc.v:184014$11711_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185089.1-185147.10"
+attribute \src "libresoc.v:184033.1-184091.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l"
attribute \generator "nMigen"
module \req_l$12
- attribute \src "libresoc.v:185090.7-185090.20"
+ attribute \src "libresoc.v:184034.7-184034.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185135.3-185143.6"
- wire width 3 $0\q_int$next[2:0]$11916
- attribute \src "libresoc.v:185133.3-185134.27"
+ attribute \src "libresoc.v:184079.3-184087.6"
+ wire width 3 $0\q_int$next[2:0]$11728
+ attribute \src "libresoc.v:184077.3-184078.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:185135.3-185143.6"
- wire width 3 $1\q_int$next[2:0]$11917
- attribute \src "libresoc.v:185112.13-185112.25"
+ attribute \src "libresoc.v:184079.3-184087.6"
+ wire width 3 $1\q_int$next[2:0]$11729
+ attribute \src "libresoc.v:184056.13-184056.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:185125.17-185125.96"
- wire width 3 $and$libresoc.v:185125$11906_Y
- attribute \src "libresoc.v:185130.17-185130.96"
- wire width 3 $and$libresoc.v:185130$11911_Y
- attribute \src "libresoc.v:185127.18-185127.93"
- wire width 3 $not$libresoc.v:185127$11908_Y
- attribute \src "libresoc.v:185129.17-185129.92"
- wire width 3 $not$libresoc.v:185129$11910_Y
- attribute \src "libresoc.v:185132.17-185132.92"
- wire width 3 $not$libresoc.v:185132$11913_Y
- attribute \src "libresoc.v:185126.18-185126.98"
- wire width 3 $or$libresoc.v:185126$11907_Y
- attribute \src "libresoc.v:185128.18-185128.99"
- wire width 3 $or$libresoc.v:185128$11909_Y
- attribute \src "libresoc.v:185131.17-185131.97"
- wire width 3 $or$libresoc.v:185131$11912_Y
+ attribute \src "libresoc.v:184069.17-184069.96"
+ wire width 3 $and$libresoc.v:184069$11718_Y
+ attribute \src "libresoc.v:184074.17-184074.96"
+ wire width 3 $and$libresoc.v:184074$11723_Y
+ attribute \src "libresoc.v:184071.18-184071.93"
+ wire width 3 $not$libresoc.v:184071$11720_Y
+ attribute \src "libresoc.v:184073.17-184073.92"
+ wire width 3 $not$libresoc.v:184073$11722_Y
+ attribute \src "libresoc.v:184076.17-184076.92"
+ wire width 3 $not$libresoc.v:184076$11725_Y
+ attribute \src "libresoc.v:184070.18-184070.98"
+ wire width 3 $or$libresoc.v:184070$11719_Y
+ attribute \src "libresoc.v:184072.18-184072.99"
+ wire width 3 $or$libresoc.v:184072$11721_Y
+ attribute \src "libresoc.v:184075.17-184075.97"
+ wire width 3 $or$libresoc.v:184075$11724_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185090.7-185090.15"
+ attribute \src "libresoc.v:184034.7-184034.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185125$11906
+ cell $and $and$libresoc.v:184069$11718
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185125$11906_Y
+ connect \Y $and$libresoc.v:184069$11718_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185130$11911
+ cell $and $and$libresoc.v:184074$11723
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185130$11911_Y
+ connect \Y $and$libresoc.v:184074$11723_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185127$11908
+ cell $not $not$libresoc.v:184071$11720
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:185127$11908_Y
+ connect \Y $not$libresoc.v:184071$11720_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185129$11910
+ cell $not $not$libresoc.v:184073$11722
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185129$11910_Y
+ connect \Y $not$libresoc.v:184073$11722_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185132$11913
+ cell $not $not$libresoc.v:184076$11725
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185132$11913_Y
+ connect \Y $not$libresoc.v:184076$11725_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185126$11907
+ cell $or $or$libresoc.v:184070$11719
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185126$11907_Y
+ connect \Y $or$libresoc.v:184070$11719_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185128$11909
+ cell $or $or$libresoc.v:184072$11721
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185128$11909_Y
+ connect \Y $or$libresoc.v:184072$11721_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185131$11912
+ cell $or $or$libresoc.v:184075$11724
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185131$11912_Y
+ connect \Y $or$libresoc.v:184075$11724_Y
end
- attribute \src "libresoc.v:185090.7-185090.20"
- process $proc$libresoc.v:185090$11918
+ attribute \src "libresoc.v:184034.7-184034.20"
+ process $proc$libresoc.v:184034$11730
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185112.13-185112.25"
- process $proc$libresoc.v:185112$11919
+ attribute \src "libresoc.v:184056.13-184056.25"
+ process $proc$libresoc.v:184056$11731
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:185133.3-185134.27"
- process $proc$libresoc.v:185133$11914
+ attribute \src "libresoc.v:184077.3-184078.27"
+ process $proc$libresoc.v:184077$11726
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:185135.3-185143.6"
- process $proc$libresoc.v:185135$11915
+ attribute \src "libresoc.v:184079.3-184087.6"
+ process $proc$libresoc.v:184079$11727
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11916 $1\q_int$next[2:0]$11917
- attribute \src "libresoc.v:185136.5-185136.29"
+ assign $0\q_int$next[2:0]$11728 $1\q_int$next[2:0]$11729
+ attribute \src "libresoc.v:184080.5-184080.29"
switch \initial
- attribute \src "libresoc.v:185136.9-185136.17"
+ attribute \src "libresoc.v:184080.9-184080.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11917 3'000
+ assign $1\q_int$next[2:0]$11729 3'000
case
- assign $1\q_int$next[2:0]$11917 \$5
+ assign $1\q_int$next[2:0]$11729 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11916
+ update \q_int$next $0\q_int$next[2:0]$11728
end
- connect \$9 $and$libresoc.v:185125$11906_Y
- connect \$11 $or$libresoc.v:185126$11907_Y
- connect \$13 $not$libresoc.v:185127$11908_Y
- connect \$15 $or$libresoc.v:185128$11909_Y
- connect \$1 $not$libresoc.v:185129$11910_Y
- connect \$3 $and$libresoc.v:185130$11911_Y
- connect \$5 $or$libresoc.v:185131$11912_Y
- connect \$7 $not$libresoc.v:185132$11913_Y
+ connect \$9 $and$libresoc.v:184069$11718_Y
+ connect \$11 $or$libresoc.v:184070$11719_Y
+ connect \$13 $not$libresoc.v:184071$11720_Y
+ connect \$15 $or$libresoc.v:184072$11721_Y
+ connect \$1 $not$libresoc.v:184073$11722_Y
+ connect \$3 $and$libresoc.v:184074$11723_Y
+ connect \$5 $or$libresoc.v:184075$11724_Y
+ connect \$7 $not$libresoc.v:184076$11725_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185151.1-185209.10"
+attribute \src "libresoc.v:184095.1-184153.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l"
attribute \generator "nMigen"
module \req_l$121
- attribute \src "libresoc.v:185152.7-185152.20"
+ attribute \src "libresoc.v:184096.7-184096.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185197.3-185205.6"
- wire width 3 $0\q_int$next[2:0]$11930
- attribute \src "libresoc.v:185195.3-185196.27"
+ attribute \src "libresoc.v:184141.3-184149.6"
+ wire width 3 $0\q_int$next[2:0]$11742
+ attribute \src "libresoc.v:184139.3-184140.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:185197.3-185205.6"
- wire width 3 $1\q_int$next[2:0]$11931
- attribute \src "libresoc.v:185174.13-185174.25"
+ attribute \src "libresoc.v:184141.3-184149.6"
+ wire width 3 $1\q_int$next[2:0]$11743
+ attribute \src "libresoc.v:184118.13-184118.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:185187.17-185187.96"
- wire width 3 $and$libresoc.v:185187$11920_Y
- attribute \src "libresoc.v:185192.17-185192.96"
- wire width 3 $and$libresoc.v:185192$11925_Y
- attribute \src "libresoc.v:185189.18-185189.93"
- wire width 3 $not$libresoc.v:185189$11922_Y
- attribute \src "libresoc.v:185191.17-185191.92"
- wire width 3 $not$libresoc.v:185191$11924_Y
- attribute \src "libresoc.v:185194.17-185194.92"
- wire width 3 $not$libresoc.v:185194$11927_Y
- attribute \src "libresoc.v:185188.18-185188.98"
- wire width 3 $or$libresoc.v:185188$11921_Y
- attribute \src "libresoc.v:185190.18-185190.99"
- wire width 3 $or$libresoc.v:185190$11923_Y
- attribute \src "libresoc.v:185193.17-185193.97"
- wire width 3 $or$libresoc.v:185193$11926_Y
+ attribute \src "libresoc.v:184131.17-184131.96"
+ wire width 3 $and$libresoc.v:184131$11732_Y
+ attribute \src "libresoc.v:184136.17-184136.96"
+ wire width 3 $and$libresoc.v:184136$11737_Y
+ attribute \src "libresoc.v:184133.18-184133.93"
+ wire width 3 $not$libresoc.v:184133$11734_Y
+ attribute \src "libresoc.v:184135.17-184135.92"
+ wire width 3 $not$libresoc.v:184135$11736_Y
+ attribute \src "libresoc.v:184138.17-184138.92"
+ wire width 3 $not$libresoc.v:184138$11739_Y
+ attribute \src "libresoc.v:184132.18-184132.98"
+ wire width 3 $or$libresoc.v:184132$11733_Y
+ attribute \src "libresoc.v:184134.18-184134.99"
+ wire width 3 $or$libresoc.v:184134$11735_Y
+ attribute \src "libresoc.v:184137.17-184137.97"
+ wire width 3 $or$libresoc.v:184137$11738_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185152.7-185152.15"
+ attribute \src "libresoc.v:184096.7-184096.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185187$11920
+ cell $and $and$libresoc.v:184131$11732
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185187$11920_Y
+ connect \Y $and$libresoc.v:184131$11732_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185192$11925
+ cell $and $and$libresoc.v:184136$11737
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185192$11925_Y
+ connect \Y $and$libresoc.v:184136$11737_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185189$11922
+ cell $not $not$libresoc.v:184133$11734
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:185189$11922_Y
+ connect \Y $not$libresoc.v:184133$11734_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185191$11924
+ cell $not $not$libresoc.v:184135$11736
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185191$11924_Y
+ connect \Y $not$libresoc.v:184135$11736_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185194$11927
+ cell $not $not$libresoc.v:184138$11739
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185194$11927_Y
+ connect \Y $not$libresoc.v:184138$11739_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185188$11921
+ cell $or $or$libresoc.v:184132$11733
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185188$11921_Y
+ connect \Y $or$libresoc.v:184132$11733_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185190$11923
+ cell $or $or$libresoc.v:184134$11735
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185190$11923_Y
+ connect \Y $or$libresoc.v:184134$11735_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185193$11926
+ cell $or $or$libresoc.v:184137$11738
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185193$11926_Y
+ connect \Y $or$libresoc.v:184137$11738_Y
end
- attribute \src "libresoc.v:185152.7-185152.20"
- process $proc$libresoc.v:185152$11932
+ attribute \src "libresoc.v:184096.7-184096.20"
+ process $proc$libresoc.v:184096$11744
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185174.13-185174.25"
- process $proc$libresoc.v:185174$11933
+ attribute \src "libresoc.v:184118.13-184118.25"
+ process $proc$libresoc.v:184118$11745
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:185195.3-185196.27"
- process $proc$libresoc.v:185195$11928
+ attribute \src "libresoc.v:184139.3-184140.27"
+ process $proc$libresoc.v:184139$11740
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:185197.3-185205.6"
- process $proc$libresoc.v:185197$11929
+ attribute \src "libresoc.v:184141.3-184149.6"
+ process $proc$libresoc.v:184141$11741
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11930 $1\q_int$next[2:0]$11931
- attribute \src "libresoc.v:185198.5-185198.29"
+ assign $0\q_int$next[2:0]$11742 $1\q_int$next[2:0]$11743
+ attribute \src "libresoc.v:184142.5-184142.29"
switch \initial
- attribute \src "libresoc.v:185198.9-185198.17"
+ attribute \src "libresoc.v:184142.9-184142.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11931 3'000
+ assign $1\q_int$next[2:0]$11743 3'000
case
- assign $1\q_int$next[2:0]$11931 \$5
+ assign $1\q_int$next[2:0]$11743 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11930
+ update \q_int$next $0\q_int$next[2:0]$11742
end
- connect \$9 $and$libresoc.v:185187$11920_Y
- connect \$11 $or$libresoc.v:185188$11921_Y
- connect \$13 $not$libresoc.v:185189$11922_Y
- connect \$15 $or$libresoc.v:185190$11923_Y
- connect \$1 $not$libresoc.v:185191$11924_Y
- connect \$3 $and$libresoc.v:185192$11925_Y
- connect \$5 $or$libresoc.v:185193$11926_Y
- connect \$7 $not$libresoc.v:185194$11927_Y
+ connect \$9 $and$libresoc.v:184131$11732_Y
+ connect \$11 $or$libresoc.v:184132$11733_Y
+ connect \$13 $not$libresoc.v:184133$11734_Y
+ connect \$15 $or$libresoc.v:184134$11735_Y
+ connect \$1 $not$libresoc.v:184135$11736_Y
+ connect \$3 $and$libresoc.v:184136$11737_Y
+ connect \$5 $or$libresoc.v:184137$11738_Y
+ connect \$7 $not$libresoc.v:184138$11739_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185213.1-185271.10"
+attribute \src "libresoc.v:184157.1-184215.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l"
attribute \generator "nMigen"
module \req_l$25
- attribute \src "libresoc.v:185214.7-185214.20"
+ attribute \src "libresoc.v:184158.7-184158.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185259.3-185267.6"
- wire width 3 $0\q_int$next[2:0]$11944
- attribute \src "libresoc.v:185257.3-185258.27"
+ attribute \src "libresoc.v:184203.3-184211.6"
+ wire width 3 $0\q_int$next[2:0]$11756
+ attribute \src "libresoc.v:184201.3-184202.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:185259.3-185267.6"
- wire width 3 $1\q_int$next[2:0]$11945
- attribute \src "libresoc.v:185236.13-185236.25"
+ attribute \src "libresoc.v:184203.3-184211.6"
+ wire width 3 $1\q_int$next[2:0]$11757
+ attribute \src "libresoc.v:184180.13-184180.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:185249.17-185249.96"
- wire width 3 $and$libresoc.v:185249$11934_Y
- attribute \src "libresoc.v:185254.17-185254.96"
- wire width 3 $and$libresoc.v:185254$11939_Y
- attribute \src "libresoc.v:185251.18-185251.93"
- wire width 3 $not$libresoc.v:185251$11936_Y
- attribute \src "libresoc.v:185253.17-185253.92"
- wire width 3 $not$libresoc.v:185253$11938_Y
- attribute \src "libresoc.v:185256.17-185256.92"
- wire width 3 $not$libresoc.v:185256$11941_Y
- attribute \src "libresoc.v:185250.18-185250.98"
- wire width 3 $or$libresoc.v:185250$11935_Y
- attribute \src "libresoc.v:185252.18-185252.99"
- wire width 3 $or$libresoc.v:185252$11937_Y
- attribute \src "libresoc.v:185255.17-185255.97"
- wire width 3 $or$libresoc.v:185255$11940_Y
+ attribute \src "libresoc.v:184193.17-184193.96"
+ wire width 3 $and$libresoc.v:184193$11746_Y
+ attribute \src "libresoc.v:184198.17-184198.96"
+ wire width 3 $and$libresoc.v:184198$11751_Y
+ attribute \src "libresoc.v:184195.18-184195.93"
+ wire width 3 $not$libresoc.v:184195$11748_Y
+ attribute \src "libresoc.v:184197.17-184197.92"
+ wire width 3 $not$libresoc.v:184197$11750_Y
+ attribute \src "libresoc.v:184200.17-184200.92"
+ wire width 3 $not$libresoc.v:184200$11753_Y
+ attribute \src "libresoc.v:184194.18-184194.98"
+ wire width 3 $or$libresoc.v:184194$11747_Y
+ attribute \src "libresoc.v:184196.18-184196.99"
+ wire width 3 $or$libresoc.v:184196$11749_Y
+ attribute \src "libresoc.v:184199.17-184199.97"
+ wire width 3 $or$libresoc.v:184199$11752_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185214.7-185214.15"
+ attribute \src "libresoc.v:184158.7-184158.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185249$11934
+ cell $and $and$libresoc.v:184193$11746
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185249$11934_Y
+ connect \Y $and$libresoc.v:184193$11746_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185254$11939
+ cell $and $and$libresoc.v:184198$11751
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185254$11939_Y
+ connect \Y $and$libresoc.v:184198$11751_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185251$11936
+ cell $not $not$libresoc.v:184195$11748
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:185251$11936_Y
+ connect \Y $not$libresoc.v:184195$11748_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185253$11938
+ cell $not $not$libresoc.v:184197$11750
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185253$11938_Y
+ connect \Y $not$libresoc.v:184197$11750_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185256$11941
+ cell $not $not$libresoc.v:184200$11753
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:185256$11941_Y
+ connect \Y $not$libresoc.v:184200$11753_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185250$11935
+ cell $or $or$libresoc.v:184194$11747
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185250$11935_Y
+ connect \Y $or$libresoc.v:184194$11747_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185252$11937
+ cell $or $or$libresoc.v:184196$11749
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185252$11937_Y
+ connect \Y $or$libresoc.v:184196$11749_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185255$11940
+ cell $or $or$libresoc.v:184199$11752
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185255$11940_Y
+ connect \Y $or$libresoc.v:184199$11752_Y
end
- attribute \src "libresoc.v:185214.7-185214.20"
- process $proc$libresoc.v:185214$11946
+ attribute \src "libresoc.v:184158.7-184158.20"
+ process $proc$libresoc.v:184158$11758
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185236.13-185236.25"
- process $proc$libresoc.v:185236$11947
+ attribute \src "libresoc.v:184180.13-184180.25"
+ process $proc$libresoc.v:184180$11759
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:185257.3-185258.27"
- process $proc$libresoc.v:185257$11942
+ attribute \src "libresoc.v:184201.3-184202.27"
+ process $proc$libresoc.v:184201$11754
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:185259.3-185267.6"
- process $proc$libresoc.v:185259$11943
+ attribute \src "libresoc.v:184203.3-184211.6"
+ process $proc$libresoc.v:184203$11755
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11944 $1\q_int$next[2:0]$11945
- attribute \src "libresoc.v:185260.5-185260.29"
+ assign $0\q_int$next[2:0]$11756 $1\q_int$next[2:0]$11757
+ attribute \src "libresoc.v:184204.5-184204.29"
switch \initial
- attribute \src "libresoc.v:185260.9-185260.17"
+ attribute \src "libresoc.v:184204.9-184204.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11945 3'000
+ assign $1\q_int$next[2:0]$11757 3'000
case
- assign $1\q_int$next[2:0]$11945 \$5
+ assign $1\q_int$next[2:0]$11757 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11944
+ update \q_int$next $0\q_int$next[2:0]$11756
end
- connect \$9 $and$libresoc.v:185249$11934_Y
- connect \$11 $or$libresoc.v:185250$11935_Y
- connect \$13 $not$libresoc.v:185251$11936_Y
- connect \$15 $or$libresoc.v:185252$11937_Y
- connect \$1 $not$libresoc.v:185253$11938_Y
- connect \$3 $and$libresoc.v:185254$11939_Y
- connect \$5 $or$libresoc.v:185255$11940_Y
- connect \$7 $not$libresoc.v:185256$11941_Y
+ connect \$9 $and$libresoc.v:184193$11746_Y
+ connect \$11 $or$libresoc.v:184194$11747_Y
+ connect \$13 $not$libresoc.v:184195$11748_Y
+ connect \$15 $or$libresoc.v:184196$11749_Y
+ connect \$1 $not$libresoc.v:184197$11750_Y
+ connect \$3 $and$libresoc.v:184198$11751_Y
+ connect \$5 $or$libresoc.v:184199$11752_Y
+ connect \$7 $not$libresoc.v:184200$11753_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185275.1-185333.10"
+attribute \src "libresoc.v:184219.1-184277.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l"
attribute \generator "nMigen"
module \req_l$41
- attribute \src "libresoc.v:185276.7-185276.20"
+ attribute \src "libresoc.v:184220.7-184220.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185321.3-185329.6"
- wire width 5 $0\q_int$next[4:0]$11958
- attribute \src "libresoc.v:185319.3-185320.27"
+ attribute \src "libresoc.v:184265.3-184273.6"
+ wire width 5 $0\q_int$next[4:0]$11770
+ attribute \src "libresoc.v:184263.3-184264.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:185321.3-185329.6"
- wire width 5 $1\q_int$next[4:0]$11959
- attribute \src "libresoc.v:185298.13-185298.26"
+ attribute \src "libresoc.v:184265.3-184273.6"
+ wire width 5 $1\q_int$next[4:0]$11771
+ attribute \src "libresoc.v:184242.13-184242.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:185311.17-185311.96"
- wire width 5 $and$libresoc.v:185311$11948_Y
- attribute \src "libresoc.v:185316.17-185316.96"
- wire width 5 $and$libresoc.v:185316$11953_Y
- attribute \src "libresoc.v:185313.18-185313.93"
- wire width 5 $not$libresoc.v:185313$11950_Y
- attribute \src "libresoc.v:185315.17-185315.92"
- wire width 5 $not$libresoc.v:185315$11952_Y
- attribute \src "libresoc.v:185318.17-185318.92"
- wire width 5 $not$libresoc.v:185318$11955_Y
- attribute \src "libresoc.v:185312.18-185312.98"
- wire width 5 $or$libresoc.v:185312$11949_Y
- attribute \src "libresoc.v:185314.18-185314.99"
- wire width 5 $or$libresoc.v:185314$11951_Y
- attribute \src "libresoc.v:185317.17-185317.97"
- wire width 5 $or$libresoc.v:185317$11954_Y
+ attribute \src "libresoc.v:184255.17-184255.96"
+ wire width 5 $and$libresoc.v:184255$11760_Y
+ attribute \src "libresoc.v:184260.17-184260.96"
+ wire width 5 $and$libresoc.v:184260$11765_Y
+ attribute \src "libresoc.v:184257.18-184257.93"
+ wire width 5 $not$libresoc.v:184257$11762_Y
+ attribute \src "libresoc.v:184259.17-184259.92"
+ wire width 5 $not$libresoc.v:184259$11764_Y
+ attribute \src "libresoc.v:184262.17-184262.92"
+ wire width 5 $not$libresoc.v:184262$11767_Y
+ attribute \src "libresoc.v:184256.18-184256.98"
+ wire width 5 $or$libresoc.v:184256$11761_Y
+ attribute \src "libresoc.v:184258.18-184258.99"
+ wire width 5 $or$libresoc.v:184258$11763_Y
+ attribute \src "libresoc.v:184261.17-184261.97"
+ wire width 5 $or$libresoc.v:184261$11766_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185276.7-185276.15"
+ attribute \src "libresoc.v:184220.7-184220.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185311$11948
+ cell $and $and$libresoc.v:184255$11760
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185311$11948_Y
+ connect \Y $and$libresoc.v:184255$11760_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185316$11953
+ cell $and $and$libresoc.v:184260$11765
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185316$11953_Y
+ connect \Y $and$libresoc.v:184260$11765_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185313$11950
+ cell $not $not$libresoc.v:184257$11762
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_req
- connect \Y $not$libresoc.v:185313$11950_Y
+ connect \Y $not$libresoc.v:184257$11762_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185315$11952
+ cell $not $not$libresoc.v:184259$11764
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:185315$11952_Y
+ connect \Y $not$libresoc.v:184259$11764_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185318$11955
+ cell $not $not$libresoc.v:184262$11767
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:185318$11955_Y
+ connect \Y $not$libresoc.v:184262$11767_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185312$11949
+ cell $or $or$libresoc.v:184256$11761
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185312$11949_Y
+ connect \Y $or$libresoc.v:184256$11761_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185314$11951
+ cell $or $or$libresoc.v:184258$11763
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185314$11951_Y
+ connect \Y $or$libresoc.v:184258$11763_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185317$11954
+ cell $or $or$libresoc.v:184261$11766
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185317$11954_Y
+ connect \Y $or$libresoc.v:184261$11766_Y
end
- attribute \src "libresoc.v:185276.7-185276.20"
- process $proc$libresoc.v:185276$11960
+ attribute \src "libresoc.v:184220.7-184220.20"
+ process $proc$libresoc.v:184220$11772
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185298.13-185298.26"
- process $proc$libresoc.v:185298$11961
+ attribute \src "libresoc.v:184242.13-184242.26"
+ process $proc$libresoc.v:184242$11773
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:185319.3-185320.27"
- process $proc$libresoc.v:185319$11956
+ attribute \src "libresoc.v:184263.3-184264.27"
+ process $proc$libresoc.v:184263$11768
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:185321.3-185329.6"
- process $proc$libresoc.v:185321$11957
+ attribute \src "libresoc.v:184265.3-184273.6"
+ process $proc$libresoc.v:184265$11769
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$11958 $1\q_int$next[4:0]$11959
- attribute \src "libresoc.v:185322.5-185322.29"
+ assign $0\q_int$next[4:0]$11770 $1\q_int$next[4:0]$11771
+ attribute \src "libresoc.v:184266.5-184266.29"
switch \initial
- attribute \src "libresoc.v:185322.9-185322.17"
+ attribute \src "libresoc.v:184266.9-184266.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$11959 5'00000
+ assign $1\q_int$next[4:0]$11771 5'00000
case
- assign $1\q_int$next[4:0]$11959 \$5
+ assign $1\q_int$next[4:0]$11771 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$11958
+ update \q_int$next $0\q_int$next[4:0]$11770
end
- connect \$9 $and$libresoc.v:185311$11948_Y
- connect \$11 $or$libresoc.v:185312$11949_Y
- connect \$13 $not$libresoc.v:185313$11950_Y
- connect \$15 $or$libresoc.v:185314$11951_Y
- connect \$1 $not$libresoc.v:185315$11952_Y
- connect \$3 $and$libresoc.v:185316$11953_Y
- connect \$5 $or$libresoc.v:185317$11954_Y
- connect \$7 $not$libresoc.v:185318$11955_Y
+ connect \$9 $and$libresoc.v:184255$11760_Y
+ connect \$11 $or$libresoc.v:184256$11761_Y
+ connect \$13 $not$libresoc.v:184257$11762_Y
+ connect \$15 $or$libresoc.v:184258$11763_Y
+ connect \$1 $not$libresoc.v:184259$11764_Y
+ connect \$3 $and$libresoc.v:184260$11765_Y
+ connect \$5 $or$libresoc.v:184261$11766_Y
+ connect \$7 $not$libresoc.v:184262$11767_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185337.1-185395.10"
+attribute \src "libresoc.v:184281.1-184339.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l"
attribute \generator "nMigen"
module \req_l$57
- attribute \src "libresoc.v:185338.7-185338.20"
+ attribute \src "libresoc.v:184282.7-184282.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185383.3-185391.6"
- wire width 2 $0\q_int$next[1:0]$11972
- attribute \src "libresoc.v:185381.3-185382.27"
+ attribute \src "libresoc.v:184327.3-184335.6"
+ wire width 2 $0\q_int$next[1:0]$11784
+ attribute \src "libresoc.v:184325.3-184326.27"
wire width 2 $0\q_int[1:0]
- attribute \src "libresoc.v:185383.3-185391.6"
- wire width 2 $1\q_int$next[1:0]$11973
- attribute \src "libresoc.v:185360.13-185360.25"
+ attribute \src "libresoc.v:184327.3-184335.6"
+ wire width 2 $1\q_int$next[1:0]$11785
+ attribute \src "libresoc.v:184304.13-184304.25"
wire width 2 $1\q_int[1:0]
- attribute \src "libresoc.v:185373.17-185373.96"
- wire width 2 $and$libresoc.v:185373$11962_Y
- attribute \src "libresoc.v:185378.17-185378.96"
- wire width 2 $and$libresoc.v:185378$11967_Y
- attribute \src "libresoc.v:185375.18-185375.93"
- wire width 2 $not$libresoc.v:185375$11964_Y
- attribute \src "libresoc.v:185377.17-185377.92"
- wire width 2 $not$libresoc.v:185377$11966_Y
- attribute \src "libresoc.v:185380.17-185380.92"
- wire width 2 $not$libresoc.v:185380$11969_Y
- attribute \src "libresoc.v:185374.18-185374.98"
- wire width 2 $or$libresoc.v:185374$11963_Y
- attribute \src "libresoc.v:185376.18-185376.99"
- wire width 2 $or$libresoc.v:185376$11965_Y
- attribute \src "libresoc.v:185379.17-185379.97"
- wire width 2 $or$libresoc.v:185379$11968_Y
+ attribute \src "libresoc.v:184317.17-184317.96"
+ wire width 2 $and$libresoc.v:184317$11774_Y
+ attribute \src "libresoc.v:184322.17-184322.96"
+ wire width 2 $and$libresoc.v:184322$11779_Y
+ attribute \src "libresoc.v:184319.18-184319.93"
+ wire width 2 $not$libresoc.v:184319$11776_Y
+ attribute \src "libresoc.v:184321.17-184321.92"
+ wire width 2 $not$libresoc.v:184321$11778_Y
+ attribute \src "libresoc.v:184324.17-184324.92"
+ wire width 2 $not$libresoc.v:184324$11781_Y
+ attribute \src "libresoc.v:184318.18-184318.98"
+ wire width 2 $or$libresoc.v:184318$11775_Y
+ attribute \src "libresoc.v:184320.18-184320.99"
+ wire width 2 $or$libresoc.v:184320$11777_Y
+ attribute \src "libresoc.v:184323.17-184323.97"
+ wire width 2 $or$libresoc.v:184323$11780_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185338.7-185338.15"
+ attribute \src "libresoc.v:184282.7-184282.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 2 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 2 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185373$11962
+ cell $and $and$libresoc.v:184317$11774
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185373$11962_Y
+ connect \Y $and$libresoc.v:184317$11774_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185378$11967
+ cell $and $and$libresoc.v:184322$11779
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185378$11967_Y
+ connect \Y $and$libresoc.v:184322$11779_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185375$11964
+ cell $not $not$libresoc.v:184319$11776
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \q_req
- connect \Y $not$libresoc.v:185375$11964_Y
+ connect \Y $not$libresoc.v:184319$11776_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185377$11966
+ cell $not $not$libresoc.v:184321$11778
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \r_req
- connect \Y $not$libresoc.v:185377$11966_Y
+ connect \Y $not$libresoc.v:184321$11778_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185380$11969
+ cell $not $not$libresoc.v:184324$11781
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \r_req
- connect \Y $not$libresoc.v:185380$11969_Y
+ connect \Y $not$libresoc.v:184324$11781_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185374$11963
+ cell $or $or$libresoc.v:184318$11775
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185374$11963_Y
+ connect \Y $or$libresoc.v:184318$11775_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185376$11965
+ cell $or $or$libresoc.v:184320$11777
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185376$11965_Y
+ connect \Y $or$libresoc.v:184320$11777_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185379$11968
+ cell $or $or$libresoc.v:184323$11780
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185379$11968_Y
+ connect \Y $or$libresoc.v:184323$11780_Y
end
- attribute \src "libresoc.v:185338.7-185338.20"
- process $proc$libresoc.v:185338$11974
+ attribute \src "libresoc.v:184282.7-184282.20"
+ process $proc$libresoc.v:184282$11786
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185360.13-185360.25"
- process $proc$libresoc.v:185360$11975
+ attribute \src "libresoc.v:184304.13-184304.25"
+ process $proc$libresoc.v:184304$11787
assign { } { }
assign $1\q_int[1:0] 2'00
sync always
sync init
update \q_int $1\q_int[1:0]
end
- attribute \src "libresoc.v:185381.3-185382.27"
- process $proc$libresoc.v:185381$11970
+ attribute \src "libresoc.v:184325.3-184326.27"
+ process $proc$libresoc.v:184325$11782
assign { } { }
assign $0\q_int[1:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[1:0]
end
- attribute \src "libresoc.v:185383.3-185391.6"
- process $proc$libresoc.v:185383$11971
+ attribute \src "libresoc.v:184327.3-184335.6"
+ process $proc$libresoc.v:184327$11783
assign { } { }
assign { } { }
- assign $0\q_int$next[1:0]$11972 $1\q_int$next[1:0]$11973
- attribute \src "libresoc.v:185384.5-185384.29"
+ assign $0\q_int$next[1:0]$11784 $1\q_int$next[1:0]$11785
+ attribute \src "libresoc.v:184328.5-184328.29"
switch \initial
- attribute \src "libresoc.v:185384.9-185384.17"
+ attribute \src "libresoc.v:184328.9-184328.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[1:0]$11973 2'00
+ assign $1\q_int$next[1:0]$11785 2'00
case
- assign $1\q_int$next[1:0]$11973 \$5
+ assign $1\q_int$next[1:0]$11785 \$5
end
sync always
- update \q_int$next $0\q_int$next[1:0]$11972
+ update \q_int$next $0\q_int$next[1:0]$11784
end
- connect \$9 $and$libresoc.v:185373$11962_Y
- connect \$11 $or$libresoc.v:185374$11963_Y
- connect \$13 $not$libresoc.v:185375$11964_Y
- connect \$15 $or$libresoc.v:185376$11965_Y
- connect \$1 $not$libresoc.v:185377$11966_Y
- connect \$3 $and$libresoc.v:185378$11967_Y
- connect \$5 $or$libresoc.v:185379$11968_Y
- connect \$7 $not$libresoc.v:185380$11969_Y
+ connect \$9 $and$libresoc.v:184317$11774_Y
+ connect \$11 $or$libresoc.v:184318$11775_Y
+ connect \$13 $not$libresoc.v:184319$11776_Y
+ connect \$15 $or$libresoc.v:184320$11777_Y
+ connect \$1 $not$libresoc.v:184321$11778_Y
+ connect \$3 $and$libresoc.v:184322$11779_Y
+ connect \$5 $or$libresoc.v:184323$11780_Y
+ connect \$7 $not$libresoc.v:184324$11781_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185399.1-185457.10"
+attribute \src "libresoc.v:184343.1-184401.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l"
attribute \generator "nMigen"
module \req_l$69
- attribute \src "libresoc.v:185400.7-185400.20"
+ attribute \src "libresoc.v:184344.7-184344.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185445.3-185453.6"
- wire width 6 $0\q_int$next[5:0]$11986
- attribute \src "libresoc.v:185443.3-185444.27"
+ attribute \src "libresoc.v:184389.3-184397.6"
+ wire width 6 $0\q_int$next[5:0]$11798
+ attribute \src "libresoc.v:184387.3-184388.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:185445.3-185453.6"
- wire width 6 $1\q_int$next[5:0]$11987
- attribute \src "libresoc.v:185422.13-185422.26"
+ attribute \src "libresoc.v:184389.3-184397.6"
+ wire width 6 $1\q_int$next[5:0]$11799
+ attribute \src "libresoc.v:184366.13-184366.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:185435.17-185435.96"
- wire width 6 $and$libresoc.v:185435$11976_Y
- attribute \src "libresoc.v:185440.17-185440.96"
- wire width 6 $and$libresoc.v:185440$11981_Y
- attribute \src "libresoc.v:185437.18-185437.93"
- wire width 6 $not$libresoc.v:185437$11978_Y
- attribute \src "libresoc.v:185439.17-185439.92"
- wire width 6 $not$libresoc.v:185439$11980_Y
- attribute \src "libresoc.v:185442.17-185442.92"
- wire width 6 $not$libresoc.v:185442$11983_Y
- attribute \src "libresoc.v:185436.18-185436.98"
- wire width 6 $or$libresoc.v:185436$11977_Y
- attribute \src "libresoc.v:185438.18-185438.99"
- wire width 6 $or$libresoc.v:185438$11979_Y
- attribute \src "libresoc.v:185441.17-185441.97"
- wire width 6 $or$libresoc.v:185441$11982_Y
+ attribute \src "libresoc.v:184379.17-184379.96"
+ wire width 6 $and$libresoc.v:184379$11788_Y
+ attribute \src "libresoc.v:184384.17-184384.96"
+ wire width 6 $and$libresoc.v:184384$11793_Y
+ attribute \src "libresoc.v:184381.18-184381.93"
+ wire width 6 $not$libresoc.v:184381$11790_Y
+ attribute \src "libresoc.v:184383.17-184383.92"
+ wire width 6 $not$libresoc.v:184383$11792_Y
+ attribute \src "libresoc.v:184386.17-184386.92"
+ wire width 6 $not$libresoc.v:184386$11795_Y
+ attribute \src "libresoc.v:184380.18-184380.98"
+ wire width 6 $or$libresoc.v:184380$11789_Y
+ attribute \src "libresoc.v:184382.18-184382.99"
+ wire width 6 $or$libresoc.v:184382$11791_Y
+ attribute \src "libresoc.v:184385.17-184385.97"
+ wire width 6 $or$libresoc.v:184385$11794_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185400.7-185400.15"
+ attribute \src "libresoc.v:184344.7-184344.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185435$11976
+ cell $and $and$libresoc.v:184379$11788
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185435$11976_Y
+ connect \Y $and$libresoc.v:184379$11788_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185440$11981
+ cell $and $and$libresoc.v:184384$11793
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185440$11981_Y
+ connect \Y $and$libresoc.v:184384$11793_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185437$11978
+ cell $not $not$libresoc.v:184381$11790
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_req
- connect \Y $not$libresoc.v:185437$11978_Y
+ connect \Y $not$libresoc.v:184381$11790_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185439$11980
+ cell $not $not$libresoc.v:184383$11792
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_req
- connect \Y $not$libresoc.v:185439$11980_Y
+ connect \Y $not$libresoc.v:184383$11792_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185442$11983
+ cell $not $not$libresoc.v:184386$11795
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_req
- connect \Y $not$libresoc.v:185442$11983_Y
+ connect \Y $not$libresoc.v:184386$11795_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185436$11977
+ cell $or $or$libresoc.v:184380$11789
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185436$11977_Y
+ connect \Y $or$libresoc.v:184380$11789_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185438$11979
+ cell $or $or$libresoc.v:184382$11791
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185438$11979_Y
+ connect \Y $or$libresoc.v:184382$11791_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185441$11982
+ cell $or $or$libresoc.v:184385$11794
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185441$11982_Y
+ connect \Y $or$libresoc.v:184385$11794_Y
end
- attribute \src "libresoc.v:185400.7-185400.20"
- process $proc$libresoc.v:185400$11988
+ attribute \src "libresoc.v:184344.7-184344.20"
+ process $proc$libresoc.v:184344$11800
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185422.13-185422.26"
- process $proc$libresoc.v:185422$11989
+ attribute \src "libresoc.v:184366.13-184366.26"
+ process $proc$libresoc.v:184366$11801
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:185443.3-185444.27"
- process $proc$libresoc.v:185443$11984
+ attribute \src "libresoc.v:184387.3-184388.27"
+ process $proc$libresoc.v:184387$11796
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:185445.3-185453.6"
- process $proc$libresoc.v:185445$11985
+ attribute \src "libresoc.v:184389.3-184397.6"
+ process $proc$libresoc.v:184389$11797
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$11986 $1\q_int$next[5:0]$11987
- attribute \src "libresoc.v:185446.5-185446.29"
+ assign $0\q_int$next[5:0]$11798 $1\q_int$next[5:0]$11799
+ attribute \src "libresoc.v:184390.5-184390.29"
switch \initial
- attribute \src "libresoc.v:185446.9-185446.17"
+ attribute \src "libresoc.v:184390.9-184390.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$11987 6'000000
+ assign $1\q_int$next[5:0]$11799 6'000000
case
- assign $1\q_int$next[5:0]$11987 \$5
+ assign $1\q_int$next[5:0]$11799 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$11986
+ update \q_int$next $0\q_int$next[5:0]$11798
end
- connect \$9 $and$libresoc.v:185435$11976_Y
- connect \$11 $or$libresoc.v:185436$11977_Y
- connect \$13 $not$libresoc.v:185437$11978_Y
- connect \$15 $or$libresoc.v:185438$11979_Y
- connect \$1 $not$libresoc.v:185439$11980_Y
- connect \$3 $and$libresoc.v:185440$11981_Y
- connect \$5 $or$libresoc.v:185441$11982_Y
- connect \$7 $not$libresoc.v:185442$11983_Y
+ connect \$9 $and$libresoc.v:184379$11788_Y
+ connect \$11 $or$libresoc.v:184380$11789_Y
+ connect \$13 $not$libresoc.v:184381$11790_Y
+ connect \$15 $or$libresoc.v:184382$11791_Y
+ connect \$1 $not$libresoc.v:184383$11792_Y
+ connect \$3 $and$libresoc.v:184384$11793_Y
+ connect \$5 $or$libresoc.v:184385$11794_Y
+ connect \$7 $not$libresoc.v:184386$11795_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185461.1-185519.10"
+attribute \src "libresoc.v:184405.1-184463.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l"
attribute \generator "nMigen"
module \req_l$86
- attribute \src "libresoc.v:185462.7-185462.20"
+ attribute \src "libresoc.v:184406.7-184406.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185507.3-185515.6"
- wire width 4 $0\q_int$next[3:0]$12000
- attribute \src "libresoc.v:185505.3-185506.27"
+ attribute \src "libresoc.v:184451.3-184459.6"
+ wire width 4 $0\q_int$next[3:0]$11812
+ attribute \src "libresoc.v:184449.3-184450.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:185507.3-185515.6"
- wire width 4 $1\q_int$next[3:0]$12001
- attribute \src "libresoc.v:185484.13-185484.25"
+ attribute \src "libresoc.v:184451.3-184459.6"
+ wire width 4 $1\q_int$next[3:0]$11813
+ attribute \src "libresoc.v:184428.13-184428.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:185497.17-185497.96"
- wire width 4 $and$libresoc.v:185497$11990_Y
- attribute \src "libresoc.v:185502.17-185502.96"
- wire width 4 $and$libresoc.v:185502$11995_Y
- attribute \src "libresoc.v:185499.18-185499.93"
- wire width 4 $not$libresoc.v:185499$11992_Y
- attribute \src "libresoc.v:185501.17-185501.92"
- wire width 4 $not$libresoc.v:185501$11994_Y
- attribute \src "libresoc.v:185504.17-185504.92"
- wire width 4 $not$libresoc.v:185504$11997_Y
- attribute \src "libresoc.v:185498.18-185498.98"
- wire width 4 $or$libresoc.v:185498$11991_Y
- attribute \src "libresoc.v:185500.18-185500.99"
- wire width 4 $or$libresoc.v:185500$11993_Y
- attribute \src "libresoc.v:185503.17-185503.97"
- wire width 4 $or$libresoc.v:185503$11996_Y
+ attribute \src "libresoc.v:184441.17-184441.96"
+ wire width 4 $and$libresoc.v:184441$11802_Y
+ attribute \src "libresoc.v:184446.17-184446.96"
+ wire width 4 $and$libresoc.v:184446$11807_Y
+ attribute \src "libresoc.v:184443.18-184443.93"
+ wire width 4 $not$libresoc.v:184443$11804_Y
+ attribute \src "libresoc.v:184445.17-184445.92"
+ wire width 4 $not$libresoc.v:184445$11806_Y
+ attribute \src "libresoc.v:184448.17-184448.92"
+ wire width 4 $not$libresoc.v:184448$11809_Y
+ attribute \src "libresoc.v:184442.18-184442.98"
+ wire width 4 $or$libresoc.v:184442$11803_Y
+ attribute \src "libresoc.v:184444.18-184444.99"
+ wire width 4 $or$libresoc.v:184444$11805_Y
+ attribute \src "libresoc.v:184447.17-184447.97"
+ wire width 4 $or$libresoc.v:184447$11808_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185462.7-185462.15"
+ attribute \src "libresoc.v:184406.7-184406.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:185497$11990
+ cell $and $and$libresoc.v:184441$11802
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:185497$11990_Y
+ connect \Y $and$libresoc.v:184441$11802_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185502$11995
+ cell $and $and$libresoc.v:184446$11807
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185502$11995_Y
+ connect \Y $and$libresoc.v:184446$11807_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185499$11992
+ cell $not $not$libresoc.v:184443$11804
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_req
- connect \Y $not$libresoc.v:185499$11992_Y
+ connect \Y $not$libresoc.v:184443$11804_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185501$11994
+ cell $not $not$libresoc.v:184445$11806
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:185501$11994_Y
+ connect \Y $not$libresoc.v:184445$11806_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:185504$11997
+ cell $not $not$libresoc.v:184448$11809
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:185504$11997_Y
+ connect \Y $not$libresoc.v:184448$11809_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:185498$11991
+ cell $or $or$libresoc.v:184442$11803
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:185498$11991_Y
+ connect \Y $or$libresoc.v:184442$11803_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185500$11993
+ cell $or $or$libresoc.v:184444$11805
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:185500$11993_Y
+ connect \Y $or$libresoc.v:184444$11805_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185503$11996
+ cell $or $or$libresoc.v:184447$11808
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:185503$11996_Y
+ connect \Y $or$libresoc.v:184447$11808_Y
end
- attribute \src "libresoc.v:185462.7-185462.20"
- process $proc$libresoc.v:185462$12002
+ attribute \src "libresoc.v:184406.7-184406.20"
+ process $proc$libresoc.v:184406$11814
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185484.13-185484.25"
- process $proc$libresoc.v:185484$12003
+ attribute \src "libresoc.v:184428.13-184428.25"
+ process $proc$libresoc.v:184428$11815
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:185505.3-185506.27"
- process $proc$libresoc.v:185505$11998
+ attribute \src "libresoc.v:184449.3-184450.27"
+ process $proc$libresoc.v:184449$11810
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:185507.3-185515.6"
- process $proc$libresoc.v:185507$11999
+ attribute \src "libresoc.v:184451.3-184459.6"
+ process $proc$libresoc.v:184451$11811
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$12000 $1\q_int$next[3:0]$12001
- attribute \src "libresoc.v:185508.5-185508.29"
+ assign $0\q_int$next[3:0]$11812 $1\q_int$next[3:0]$11813
+ attribute \src "libresoc.v:184452.5-184452.29"
switch \initial
- attribute \src "libresoc.v:185508.9-185508.17"
+ attribute \src "libresoc.v:184452.9-184452.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$12001 4'0000
+ assign $1\q_int$next[3:0]$11813 4'0000
case
- assign $1\q_int$next[3:0]$12001 \$5
+ assign $1\q_int$next[3:0]$11813 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$12000
+ update \q_int$next $0\q_int$next[3:0]$11812
end
- connect \$9 $and$libresoc.v:185497$11990_Y
- connect \$11 $or$libresoc.v:185498$11991_Y
- connect \$13 $not$libresoc.v:185499$11992_Y
- connect \$15 $or$libresoc.v:185500$11993_Y
- connect \$1 $not$libresoc.v:185501$11994_Y
- connect \$3 $and$libresoc.v:185502$11995_Y
- connect \$5 $or$libresoc.v:185503$11996_Y
- connect \$7 $not$libresoc.v:185504$11997_Y
+ connect \$9 $and$libresoc.v:184441$11802_Y
+ connect \$11 $or$libresoc.v:184442$11803_Y
+ connect \$13 $not$libresoc.v:184443$11804_Y
+ connect \$15 $or$libresoc.v:184444$11805_Y
+ connect \$1 $not$libresoc.v:184445$11806_Y
+ connect \$3 $and$libresoc.v:184446$11807_Y
+ connect \$5 $or$libresoc.v:184447$11808_Y
+ connect \$7 $not$libresoc.v:184448$11809_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:185523.1-185572.10"
+attribute \src "libresoc.v:184467.1-184516.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l"
attribute \generator "nMigen"
module \reset_l
- attribute \src "libresoc.v:185524.7-185524.20"
+ attribute \src "libresoc.v:184468.7-184468.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185560.3-185568.6"
- wire $0\q_int$next[0:0]$12011
- attribute \src "libresoc.v:185558.3-185559.27"
+ attribute \src "libresoc.v:184504.3-184512.6"
+ wire $0\q_int$next[0:0]$11823
+ attribute \src "libresoc.v:184502.3-184503.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:185560.3-185568.6"
- wire $1\q_int$next[0:0]$12012
- attribute \src "libresoc.v:185540.7-185540.19"
+ attribute \src "libresoc.v:184504.3-184512.6"
+ wire $1\q_int$next[0:0]$11824
+ attribute \src "libresoc.v:184484.7-184484.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:185555.17-185555.96"
- wire $and$libresoc.v:185555$12006_Y
- attribute \src "libresoc.v:185554.17-185554.94"
- wire $not$libresoc.v:185554$12005_Y
- attribute \src "libresoc.v:185557.17-185557.94"
- wire $not$libresoc.v:185557$12008_Y
- attribute \src "libresoc.v:185553.17-185553.100"
- wire $or$libresoc.v:185553$12004_Y
- attribute \src "libresoc.v:185556.17-185556.99"
- wire $or$libresoc.v:185556$12007_Y
+ attribute \src "libresoc.v:184499.17-184499.96"
+ wire $and$libresoc.v:184499$11818_Y
+ attribute \src "libresoc.v:184498.17-184498.94"
+ wire $not$libresoc.v:184498$11817_Y
+ attribute \src "libresoc.v:184501.17-184501.94"
+ wire $not$libresoc.v:184501$11820_Y
+ attribute \src "libresoc.v:184497.17-184497.100"
+ wire $or$libresoc.v:184497$11816_Y
+ attribute \src "libresoc.v:184500.17-184500.99"
+ wire $or$libresoc.v:184500$11819_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185524.7-185524.15"
+ attribute \src "libresoc.v:184468.7-184468.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_reset
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185555$12006
+ cell $and $and$libresoc.v:184499$11818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185555$12006_Y
+ connect \Y $and$libresoc.v:184499$11818_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185554$12005
+ cell $not $not$libresoc.v:184498$11817
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_reset
- connect \Y $not$libresoc.v:185554$12005_Y
+ connect \Y $not$libresoc.v:184498$11817_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185557$12008
+ cell $not $not$libresoc.v:184501$11820
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_reset
- connect \Y $not$libresoc.v:185557$12008_Y
+ connect \Y $not$libresoc.v:184501$11820_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185553$12004
+ cell $or $or$libresoc.v:184497$11816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_reset
connect \B \q_int
- connect \Y $or$libresoc.v:185553$12004_Y
+ connect \Y $or$libresoc.v:184497$11816_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185556$12007
+ cell $or $or$libresoc.v:184500$11819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_reset
- connect \Y $or$libresoc.v:185556$12007_Y
+ connect \Y $or$libresoc.v:184500$11819_Y
end
- attribute \src "libresoc.v:185524.7-185524.20"
- process $proc$libresoc.v:185524$12013
+ attribute \src "libresoc.v:184468.7-184468.20"
+ process $proc$libresoc.v:184468$11825
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185540.7-185540.19"
- process $proc$libresoc.v:185540$12014
+ attribute \src "libresoc.v:184484.7-184484.19"
+ process $proc$libresoc.v:184484$11826
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:185558.3-185559.27"
- process $proc$libresoc.v:185558$12009
+ attribute \src "libresoc.v:184502.3-184503.27"
+ process $proc$libresoc.v:184502$11821
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:185560.3-185568.6"
- process $proc$libresoc.v:185560$12010
+ attribute \src "libresoc.v:184504.3-184512.6"
+ process $proc$libresoc.v:184504$11822
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12011 $1\q_int$next[0:0]$12012
- attribute \src "libresoc.v:185561.5-185561.29"
+ assign $0\q_int$next[0:0]$11823 $1\q_int$next[0:0]$11824
+ attribute \src "libresoc.v:184505.5-184505.29"
switch \initial
- attribute \src "libresoc.v:185561.9-185561.17"
+ attribute \src "libresoc.v:184505.9-184505.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12012 1'0
+ assign $1\q_int$next[0:0]$11824 1'0
case
- assign $1\q_int$next[0:0]$12012 \$5
+ assign $1\q_int$next[0:0]$11824 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12011
+ update \q_int$next $0\q_int$next[0:0]$11823
end
- connect \$9 $or$libresoc.v:185553$12004_Y
- connect \$1 $not$libresoc.v:185554$12005_Y
- connect \$3 $and$libresoc.v:185555$12006_Y
- connect \$5 $or$libresoc.v:185556$12007_Y
- connect \$7 $not$libresoc.v:185557$12008_Y
+ connect \$9 $or$libresoc.v:184497$11816_Y
+ connect \$1 $not$libresoc.v:184498$11817_Y
+ connect \$3 $and$libresoc.v:184499$11818_Y
+ connect \$5 $or$libresoc.v:184500$11819_Y
+ connect \$7 $not$libresoc.v:184501$11820_Y
connect \qlq_reset \$9
connect \qn_reset \$7
connect \q_reset \q_int
end
-attribute \src "libresoc.v:185576.1-185625.10"
+attribute \src "libresoc.v:184520.1-184569.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l"
attribute \generator "nMigen"
module \reset_l$131
- attribute \src "libresoc.v:185577.7-185577.20"
+ attribute \src "libresoc.v:184521.7-184521.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185613.3-185621.6"
- wire $0\q_int$next[0:0]$12022
- attribute \src "libresoc.v:185611.3-185612.27"
+ attribute \src "libresoc.v:184557.3-184565.6"
+ wire $0\q_int$next[0:0]$11834
+ attribute \src "libresoc.v:184555.3-184556.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:185613.3-185621.6"
- wire $1\q_int$next[0:0]$12023
- attribute \src "libresoc.v:185593.7-185593.19"
+ attribute \src "libresoc.v:184557.3-184565.6"
+ wire $1\q_int$next[0:0]$11835
+ attribute \src "libresoc.v:184537.7-184537.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:185608.17-185608.96"
- wire $and$libresoc.v:185608$12017_Y
- attribute \src "libresoc.v:185607.17-185607.94"
- wire $not$libresoc.v:185607$12016_Y
- attribute \src "libresoc.v:185610.17-185610.94"
- wire $not$libresoc.v:185610$12019_Y
- attribute \src "libresoc.v:185606.17-185606.100"
- wire $or$libresoc.v:185606$12015_Y
- attribute \src "libresoc.v:185609.17-185609.99"
- wire $or$libresoc.v:185609$12018_Y
+ attribute \src "libresoc.v:184552.17-184552.96"
+ wire $and$libresoc.v:184552$11829_Y
+ attribute \src "libresoc.v:184551.17-184551.94"
+ wire $not$libresoc.v:184551$11828_Y
+ attribute \src "libresoc.v:184554.17-184554.94"
+ wire $not$libresoc.v:184554$11831_Y
+ attribute \src "libresoc.v:184550.17-184550.100"
+ wire $or$libresoc.v:184550$11827_Y
+ attribute \src "libresoc.v:184553.17-184553.99"
+ wire $or$libresoc.v:184553$11830_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185577.7-185577.15"
+ attribute \src "libresoc.v:184521.7-184521.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_reset
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:185608$12017
+ cell $and $and$libresoc.v:184552$11829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:185608$12017_Y
+ connect \Y $and$libresoc.v:184552$11829_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:185607$12016
+ cell $not $not$libresoc.v:184551$11828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_reset
- connect \Y $not$libresoc.v:185607$12016_Y
+ connect \Y $not$libresoc.v:184551$11828_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:185610$12019
+ cell $not $not$libresoc.v:184554$11831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_reset
- connect \Y $not$libresoc.v:185610$12019_Y
+ connect \Y $not$libresoc.v:184554$11831_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:185606$12015
+ cell $or $or$libresoc.v:184550$11827
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_reset
connect \B \q_int
- connect \Y $or$libresoc.v:185606$12015_Y
+ connect \Y $or$libresoc.v:184550$11827_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:185609$12018
+ cell $or $or$libresoc.v:184553$11830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_reset
- connect \Y $or$libresoc.v:185609$12018_Y
+ connect \Y $or$libresoc.v:184553$11830_Y
end
- attribute \src "libresoc.v:185577.7-185577.20"
- process $proc$libresoc.v:185577$12024
+ attribute \src "libresoc.v:184521.7-184521.20"
+ process $proc$libresoc.v:184521$11836
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185593.7-185593.19"
- process $proc$libresoc.v:185593$12025
+ attribute \src "libresoc.v:184537.7-184537.19"
+ process $proc$libresoc.v:184537$11837
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:185611.3-185612.27"
- process $proc$libresoc.v:185611$12020
+ attribute \src "libresoc.v:184555.3-184556.27"
+ process $proc$libresoc.v:184555$11832
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:185613.3-185621.6"
- process $proc$libresoc.v:185613$12021
+ attribute \src "libresoc.v:184557.3-184565.6"
+ process $proc$libresoc.v:184557$11833
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12022 $1\q_int$next[0:0]$12023
- attribute \src "libresoc.v:185614.5-185614.29"
+ assign $0\q_int$next[0:0]$11834 $1\q_int$next[0:0]$11835
+ attribute \src "libresoc.v:184558.5-184558.29"
switch \initial
- attribute \src "libresoc.v:185614.9-185614.17"
+ attribute \src "libresoc.v:184558.9-184558.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12023 1'0
+ assign $1\q_int$next[0:0]$11835 1'0
case
- assign $1\q_int$next[0:0]$12023 \$5
+ assign $1\q_int$next[0:0]$11835 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12022
+ update \q_int$next $0\q_int$next[0:0]$11834
end
- connect \$9 $or$libresoc.v:185606$12015_Y
- connect \$1 $not$libresoc.v:185607$12016_Y
- connect \$3 $and$libresoc.v:185608$12017_Y
- connect \$5 $or$libresoc.v:185609$12018_Y
- connect \$7 $not$libresoc.v:185610$12019_Y
+ connect \$9 $or$libresoc.v:184550$11827_Y
+ connect \$1 $not$libresoc.v:184551$11828_Y
+ connect \$3 $and$libresoc.v:184552$11829_Y
+ connect \$5 $or$libresoc.v:184553$11830_Y
+ connect \$7 $not$libresoc.v:184554$11831_Y
connect \qlq_reset \$9
connect \qn_reset \$7
connect \q_reset \q_int
end
-attribute \src "libresoc.v:185629.1-186216.10"
+attribute \src "libresoc.v:184573.1-185160.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask"
attribute \generator "nMigen"
module \right_mask
- attribute \src "libresoc.v:185630.7-185630.20"
+ attribute \src "libresoc.v:184574.7-184574.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire width 64 $0\mask[63:0]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $10\mask[9:9]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $11\mask[10:10]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $12\mask[11:11]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $13\mask[12:12]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $14\mask[13:13]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $15\mask[14:14]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $16\mask[15:15]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $17\mask[16:16]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $18\mask[17:17]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $19\mask[18:18]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $1\mask[0:0]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $20\mask[19:19]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $21\mask[20:20]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $22\mask[21:21]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $23\mask[22:22]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $24\mask[23:23]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $25\mask[24:24]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $26\mask[25:25]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $27\mask[26:26]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $28\mask[27:27]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $29\mask[28:28]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $2\mask[1:1]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $30\mask[29:29]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $31\mask[30:30]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $32\mask[31:31]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $33\mask[32:32]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $34\mask[33:33]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $35\mask[34:34]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $36\mask[35:35]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $37\mask[36:36]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $38\mask[37:37]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $39\mask[38:38]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $3\mask[2:2]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $40\mask[39:39]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $41\mask[40:40]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $42\mask[41:41]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $43\mask[42:42]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $44\mask[43:43]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $45\mask[44:44]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $46\mask[45:45]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $47\mask[46:46]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $48\mask[47:47]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $49\mask[48:48]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $4\mask[3:3]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $50\mask[49:49]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $51\mask[50:50]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $52\mask[51:51]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $53\mask[52:52]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $54\mask[53:53]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $55\mask[54:54]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $56\mask[55:55]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $57\mask[56:56]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $58\mask[57:57]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $59\mask[58:58]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $5\mask[4:4]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $60\mask[59:59]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $61\mask[60:60]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $62\mask[61:61]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $63\mask[62:62]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $64\mask[63:63]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $6\mask[5:5]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $7\mask[6:6]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $8\mask[7:7]
- attribute \src "libresoc.v:185828.3-186215.6"
+ attribute \src "libresoc.v:184772.3-185159.6"
wire $9\mask[8:8]
- attribute \src "libresoc.v:185764.17-185764.96"
- wire $gt$libresoc.v:185764$12026_Y
- attribute \src "libresoc.v:185765.18-185765.98"
- wire $gt$libresoc.v:185765$12027_Y
- attribute \src "libresoc.v:185766.19-185766.99"
- wire $gt$libresoc.v:185766$12028_Y
- attribute \src "libresoc.v:185767.19-185767.99"
- wire $gt$libresoc.v:185767$12029_Y
- attribute \src "libresoc.v:185768.19-185768.99"
- wire $gt$libresoc.v:185768$12030_Y
- attribute \src "libresoc.v:185769.19-185769.99"
- wire $gt$libresoc.v:185769$12031_Y
- attribute \src "libresoc.v:185770.19-185770.99"
- wire $gt$libresoc.v:185770$12032_Y
- attribute \src "libresoc.v:185771.19-185771.99"
- wire $gt$libresoc.v:185771$12033_Y
- attribute \src "libresoc.v:185772.19-185772.99"
- wire $gt$libresoc.v:185772$12034_Y
- attribute \src "libresoc.v:185773.19-185773.99"
- wire $gt$libresoc.v:185773$12035_Y
- attribute \src "libresoc.v:185774.19-185774.99"
- wire $gt$libresoc.v:185774$12036_Y
- attribute \src "libresoc.v:185775.18-185775.97"
- wire $gt$libresoc.v:185775$12037_Y
- attribute \src "libresoc.v:185776.19-185776.99"
- wire $gt$libresoc.v:185776$12038_Y
- attribute \src "libresoc.v:185777.19-185777.99"
- wire $gt$libresoc.v:185777$12039_Y
- attribute \src "libresoc.v:185778.19-185778.99"
- wire $gt$libresoc.v:185778$12040_Y
- attribute \src "libresoc.v:185779.19-185779.99"
- wire $gt$libresoc.v:185779$12041_Y
- attribute \src "libresoc.v:185780.19-185780.99"
- wire $gt$libresoc.v:185780$12042_Y
- attribute \src "libresoc.v:185781.18-185781.97"
- wire $gt$libresoc.v:185781$12043_Y
- attribute \src "libresoc.v:185782.18-185782.97"
- wire $gt$libresoc.v:185782$12044_Y
- attribute \src "libresoc.v:185783.18-185783.97"
- wire $gt$libresoc.v:185783$12045_Y
- attribute \src "libresoc.v:185784.17-185784.96"
- wire $gt$libresoc.v:185784$12046_Y
- attribute \src "libresoc.v:185785.18-185785.97"
- wire $gt$libresoc.v:185785$12047_Y
- attribute \src "libresoc.v:185786.18-185786.97"
- wire $gt$libresoc.v:185786$12048_Y
- attribute \src "libresoc.v:185787.18-185787.97"
- wire $gt$libresoc.v:185787$12049_Y
- attribute \src "libresoc.v:185788.18-185788.97"
- wire $gt$libresoc.v:185788$12050_Y
- attribute \src "libresoc.v:185789.18-185789.97"
- wire $gt$libresoc.v:185789$12051_Y
- attribute \src "libresoc.v:185790.18-185790.97"
- wire $gt$libresoc.v:185790$12052_Y
- attribute \src "libresoc.v:185791.18-185791.97"
- wire $gt$libresoc.v:185791$12053_Y
- attribute \src "libresoc.v:185792.18-185792.98"
- wire $gt$libresoc.v:185792$12054_Y
- attribute \src "libresoc.v:185793.18-185793.98"
- wire $gt$libresoc.v:185793$12055_Y
- attribute \src "libresoc.v:185794.18-185794.98"
- wire $gt$libresoc.v:185794$12056_Y
- attribute \src "libresoc.v:185795.17-185795.96"
- wire $gt$libresoc.v:185795$12057_Y
- attribute \src "libresoc.v:185796.18-185796.98"
- wire $gt$libresoc.v:185796$12058_Y
- attribute \src "libresoc.v:185797.18-185797.98"
- wire $gt$libresoc.v:185797$12059_Y
- attribute \src "libresoc.v:185798.18-185798.98"
- wire $gt$libresoc.v:185798$12060_Y
- attribute \src "libresoc.v:185799.18-185799.98"
- wire $gt$libresoc.v:185799$12061_Y
- attribute \src "libresoc.v:185800.18-185800.98"
- wire $gt$libresoc.v:185800$12062_Y
- attribute \src "libresoc.v:185801.18-185801.98"
- wire $gt$libresoc.v:185801$12063_Y
- attribute \src "libresoc.v:185802.18-185802.98"
- wire $gt$libresoc.v:185802$12064_Y
- attribute \src "libresoc.v:185803.18-185803.98"
- wire $gt$libresoc.v:185803$12065_Y
- attribute \src "libresoc.v:185804.18-185804.98"
- wire $gt$libresoc.v:185804$12066_Y
- attribute \src "libresoc.v:185805.18-185805.98"
- wire $gt$libresoc.v:185805$12067_Y
- attribute \src "libresoc.v:185806.17-185806.96"
- wire $gt$libresoc.v:185806$12068_Y
- attribute \src "libresoc.v:185807.18-185807.98"
- wire $gt$libresoc.v:185807$12069_Y
- attribute \src "libresoc.v:185808.18-185808.98"
- wire $gt$libresoc.v:185808$12070_Y
- attribute \src "libresoc.v:185809.18-185809.98"
- wire $gt$libresoc.v:185809$12071_Y
- attribute \src "libresoc.v:185810.18-185810.98"
- wire $gt$libresoc.v:185810$12072_Y
- attribute \src "libresoc.v:185811.18-185811.98"
- wire $gt$libresoc.v:185811$12073_Y
- attribute \src "libresoc.v:185812.18-185812.98"
- wire $gt$libresoc.v:185812$12074_Y
- attribute \src "libresoc.v:185813.18-185813.98"
- wire $gt$libresoc.v:185813$12075_Y
- attribute \src "libresoc.v:185814.18-185814.98"
- wire $gt$libresoc.v:185814$12076_Y
- attribute \src "libresoc.v:185815.18-185815.98"
- wire $gt$libresoc.v:185815$12077_Y
- attribute \src "libresoc.v:185816.18-185816.98"
- wire $gt$libresoc.v:185816$12078_Y
- attribute \src "libresoc.v:185817.17-185817.96"
- wire $gt$libresoc.v:185817$12079_Y
- attribute \src "libresoc.v:185818.18-185818.98"
- wire $gt$libresoc.v:185818$12080_Y
- attribute \src "libresoc.v:185819.18-185819.98"
- wire $gt$libresoc.v:185819$12081_Y
- attribute \src "libresoc.v:185820.18-185820.98"
- wire $gt$libresoc.v:185820$12082_Y
- attribute \src "libresoc.v:185821.18-185821.98"
- wire $gt$libresoc.v:185821$12083_Y
- attribute \src "libresoc.v:185822.18-185822.98"
- wire $gt$libresoc.v:185822$12084_Y
- attribute \src "libresoc.v:185823.18-185823.98"
- wire $gt$libresoc.v:185823$12085_Y
- attribute \src "libresoc.v:185824.18-185824.98"
- wire $gt$libresoc.v:185824$12086_Y
- attribute \src "libresoc.v:185825.18-185825.98"
- wire $gt$libresoc.v:185825$12087_Y
- attribute \src "libresoc.v:185826.18-185826.98"
- wire $gt$libresoc.v:185826$12088_Y
- attribute \src "libresoc.v:185827.18-185827.98"
- wire $gt$libresoc.v:185827$12089_Y
+ attribute \src "libresoc.v:184708.17-184708.96"
+ wire $gt$libresoc.v:184708$11838_Y
+ attribute \src "libresoc.v:184709.18-184709.98"
+ wire $gt$libresoc.v:184709$11839_Y
+ attribute \src "libresoc.v:184710.19-184710.99"
+ wire $gt$libresoc.v:184710$11840_Y
+ attribute \src "libresoc.v:184711.19-184711.99"
+ wire $gt$libresoc.v:184711$11841_Y
+ attribute \src "libresoc.v:184712.19-184712.99"
+ wire $gt$libresoc.v:184712$11842_Y
+ attribute \src "libresoc.v:184713.19-184713.99"
+ wire $gt$libresoc.v:184713$11843_Y
+ attribute \src "libresoc.v:184714.19-184714.99"
+ wire $gt$libresoc.v:184714$11844_Y
+ attribute \src "libresoc.v:184715.19-184715.99"
+ wire $gt$libresoc.v:184715$11845_Y
+ attribute \src "libresoc.v:184716.19-184716.99"
+ wire $gt$libresoc.v:184716$11846_Y
+ attribute \src "libresoc.v:184717.19-184717.99"
+ wire $gt$libresoc.v:184717$11847_Y
+ attribute \src "libresoc.v:184718.19-184718.99"
+ wire $gt$libresoc.v:184718$11848_Y
+ attribute \src "libresoc.v:184719.18-184719.97"
+ wire $gt$libresoc.v:184719$11849_Y
+ attribute \src "libresoc.v:184720.19-184720.99"
+ wire $gt$libresoc.v:184720$11850_Y
+ attribute \src "libresoc.v:184721.19-184721.99"
+ wire $gt$libresoc.v:184721$11851_Y
+ attribute \src "libresoc.v:184722.19-184722.99"
+ wire $gt$libresoc.v:184722$11852_Y
+ attribute \src "libresoc.v:184723.19-184723.99"
+ wire $gt$libresoc.v:184723$11853_Y
+ attribute \src "libresoc.v:184724.19-184724.99"
+ wire $gt$libresoc.v:184724$11854_Y
+ attribute \src "libresoc.v:184725.18-184725.97"
+ wire $gt$libresoc.v:184725$11855_Y
+ attribute \src "libresoc.v:184726.18-184726.97"
+ wire $gt$libresoc.v:184726$11856_Y
+ attribute \src "libresoc.v:184727.18-184727.97"
+ wire $gt$libresoc.v:184727$11857_Y
+ attribute \src "libresoc.v:184728.17-184728.96"
+ wire $gt$libresoc.v:184728$11858_Y
+ attribute \src "libresoc.v:184729.18-184729.97"
+ wire $gt$libresoc.v:184729$11859_Y
+ attribute \src "libresoc.v:184730.18-184730.97"
+ wire $gt$libresoc.v:184730$11860_Y
+ attribute \src "libresoc.v:184731.18-184731.97"
+ wire $gt$libresoc.v:184731$11861_Y
+ attribute \src "libresoc.v:184732.18-184732.97"
+ wire $gt$libresoc.v:184732$11862_Y
+ attribute \src "libresoc.v:184733.18-184733.97"
+ wire $gt$libresoc.v:184733$11863_Y
+ attribute \src "libresoc.v:184734.18-184734.97"
+ wire $gt$libresoc.v:184734$11864_Y
+ attribute \src "libresoc.v:184735.18-184735.97"
+ wire $gt$libresoc.v:184735$11865_Y
+ attribute \src "libresoc.v:184736.18-184736.98"
+ wire $gt$libresoc.v:184736$11866_Y
+ attribute \src "libresoc.v:184737.18-184737.98"
+ wire $gt$libresoc.v:184737$11867_Y
+ attribute \src "libresoc.v:184738.18-184738.98"
+ wire $gt$libresoc.v:184738$11868_Y
+ attribute \src "libresoc.v:184739.17-184739.96"
+ wire $gt$libresoc.v:184739$11869_Y
+ attribute \src "libresoc.v:184740.18-184740.98"
+ wire $gt$libresoc.v:184740$11870_Y
+ attribute \src "libresoc.v:184741.18-184741.98"
+ wire $gt$libresoc.v:184741$11871_Y
+ attribute \src "libresoc.v:184742.18-184742.98"
+ wire $gt$libresoc.v:184742$11872_Y
+ attribute \src "libresoc.v:184743.18-184743.98"
+ wire $gt$libresoc.v:184743$11873_Y
+ attribute \src "libresoc.v:184744.18-184744.98"
+ wire $gt$libresoc.v:184744$11874_Y
+ attribute \src "libresoc.v:184745.18-184745.98"
+ wire $gt$libresoc.v:184745$11875_Y
+ attribute \src "libresoc.v:184746.18-184746.98"
+ wire $gt$libresoc.v:184746$11876_Y
+ attribute \src "libresoc.v:184747.18-184747.98"
+ wire $gt$libresoc.v:184747$11877_Y
+ attribute \src "libresoc.v:184748.18-184748.98"
+ wire $gt$libresoc.v:184748$11878_Y
+ attribute \src "libresoc.v:184749.18-184749.98"
+ wire $gt$libresoc.v:184749$11879_Y
+ attribute \src "libresoc.v:184750.17-184750.96"
+ wire $gt$libresoc.v:184750$11880_Y
+ attribute \src "libresoc.v:184751.18-184751.98"
+ wire $gt$libresoc.v:184751$11881_Y
+ attribute \src "libresoc.v:184752.18-184752.98"
+ wire $gt$libresoc.v:184752$11882_Y
+ attribute \src "libresoc.v:184753.18-184753.98"
+ wire $gt$libresoc.v:184753$11883_Y
+ attribute \src "libresoc.v:184754.18-184754.98"
+ wire $gt$libresoc.v:184754$11884_Y
+ attribute \src "libresoc.v:184755.18-184755.98"
+ wire $gt$libresoc.v:184755$11885_Y
+ attribute \src "libresoc.v:184756.18-184756.98"
+ wire $gt$libresoc.v:184756$11886_Y
+ attribute \src "libresoc.v:184757.18-184757.98"
+ wire $gt$libresoc.v:184757$11887_Y
+ attribute \src "libresoc.v:184758.18-184758.98"
+ wire $gt$libresoc.v:184758$11888_Y
+ attribute \src "libresoc.v:184759.18-184759.98"
+ wire $gt$libresoc.v:184759$11889_Y
+ attribute \src "libresoc.v:184760.18-184760.98"
+ wire $gt$libresoc.v:184760$11890_Y
+ attribute \src "libresoc.v:184761.17-184761.96"
+ wire $gt$libresoc.v:184761$11891_Y
+ attribute \src "libresoc.v:184762.18-184762.98"
+ wire $gt$libresoc.v:184762$11892_Y
+ attribute \src "libresoc.v:184763.18-184763.98"
+ wire $gt$libresoc.v:184763$11893_Y
+ attribute \src "libresoc.v:184764.18-184764.98"
+ wire $gt$libresoc.v:184764$11894_Y
+ attribute \src "libresoc.v:184765.18-184765.98"
+ wire $gt$libresoc.v:184765$11895_Y
+ attribute \src "libresoc.v:184766.18-184766.98"
+ wire $gt$libresoc.v:184766$11896_Y
+ attribute \src "libresoc.v:184767.18-184767.98"
+ wire $gt$libresoc.v:184767$11897_Y
+ attribute \src "libresoc.v:184768.18-184768.98"
+ wire $gt$libresoc.v:184768$11898_Y
+ attribute \src "libresoc.v:184769.18-184769.98"
+ wire $gt$libresoc.v:184769$11899_Y
+ attribute \src "libresoc.v:184770.18-184770.98"
+ wire $gt$libresoc.v:184770$11900_Y
+ attribute \src "libresoc.v:184771.18-184771.98"
+ wire $gt$libresoc.v:184771$11901_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$99
- attribute \src "libresoc.v:185630.7-185630.15"
+ attribute \src "libresoc.v:184574.7-184574.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20"
wire width 64 output 1 \mask
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19"
wire width 7 input 2 \shift
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185764$12026
+ cell $gt $gt$libresoc.v:184708$11838
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'100
- connect \Y $gt$libresoc.v:185764$12026_Y
+ connect \Y $gt$libresoc.v:184708$11838_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185765$12027
+ cell $gt $gt$libresoc.v:184709$11839
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110001
- connect \Y $gt$libresoc.v:185765$12027_Y
+ connect \Y $gt$libresoc.v:184709$11839_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185766$12028
+ cell $gt $gt$libresoc.v:184710$11840
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110010
- connect \Y $gt$libresoc.v:185766$12028_Y
+ connect \Y $gt$libresoc.v:184710$11840_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185767$12029
+ cell $gt $gt$libresoc.v:184711$11841
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110011
- connect \Y $gt$libresoc.v:185767$12029_Y
+ connect \Y $gt$libresoc.v:184711$11841_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185768$12030
+ cell $gt $gt$libresoc.v:184712$11842
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110100
- connect \Y $gt$libresoc.v:185768$12030_Y
+ connect \Y $gt$libresoc.v:184712$11842_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185769$12031
+ cell $gt $gt$libresoc.v:184713$11843
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110101
- connect \Y $gt$libresoc.v:185769$12031_Y
+ connect \Y $gt$libresoc.v:184713$11843_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185770$12032
+ cell $gt $gt$libresoc.v:184714$11844
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110110
- connect \Y $gt$libresoc.v:185770$12032_Y
+ connect \Y $gt$libresoc.v:184714$11844_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185771$12033
+ cell $gt $gt$libresoc.v:184715$11845
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110111
- connect \Y $gt$libresoc.v:185771$12033_Y
+ connect \Y $gt$libresoc.v:184715$11845_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185772$12034
+ cell $gt $gt$libresoc.v:184716$11846
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111000
- connect \Y $gt$libresoc.v:185772$12034_Y
+ connect \Y $gt$libresoc.v:184716$11846_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185773$12035
+ cell $gt $gt$libresoc.v:184717$11847
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111001
- connect \Y $gt$libresoc.v:185773$12035_Y
+ connect \Y $gt$libresoc.v:184717$11847_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185774$12036
+ cell $gt $gt$libresoc.v:184718$11848
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111010
- connect \Y $gt$libresoc.v:185774$12036_Y
+ connect \Y $gt$libresoc.v:184718$11848_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185775$12037
+ cell $gt $gt$libresoc.v:184719$11849
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'101
- connect \Y $gt$libresoc.v:185775$12037_Y
+ connect \Y $gt$libresoc.v:184719$11849_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185776$12038
+ cell $gt $gt$libresoc.v:184720$11850
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111011
- connect \Y $gt$libresoc.v:185776$12038_Y
+ connect \Y $gt$libresoc.v:184720$11850_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185777$12039
+ cell $gt $gt$libresoc.v:184721$11851
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111100
- connect \Y $gt$libresoc.v:185777$12039_Y
+ connect \Y $gt$libresoc.v:184721$11851_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185778$12040
+ cell $gt $gt$libresoc.v:184722$11852
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111101
- connect \Y $gt$libresoc.v:185778$12040_Y
+ connect \Y $gt$libresoc.v:184722$11852_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185779$12041
+ cell $gt $gt$libresoc.v:184723$11853
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111110
- connect \Y $gt$libresoc.v:185779$12041_Y
+ connect \Y $gt$libresoc.v:184723$11853_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185780$12042
+ cell $gt $gt$libresoc.v:184724$11854
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111111
- connect \Y $gt$libresoc.v:185780$12042_Y
+ connect \Y $gt$libresoc.v:184724$11854_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185781$12043
+ cell $gt $gt$libresoc.v:184725$11855
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'110
- connect \Y $gt$libresoc.v:185781$12043_Y
+ connect \Y $gt$libresoc.v:184725$11855_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185782$12044
+ cell $gt $gt$libresoc.v:184726$11856
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'111
- connect \Y $gt$libresoc.v:185782$12044_Y
+ connect \Y $gt$libresoc.v:184726$11856_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185783$12045
+ cell $gt $gt$libresoc.v:184727$11857
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1000
- connect \Y $gt$libresoc.v:185783$12045_Y
+ connect \Y $gt$libresoc.v:184727$11857_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185784$12046
+ cell $gt $gt$libresoc.v:184728$11858
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'0
- connect \Y $gt$libresoc.v:185784$12046_Y
+ connect \Y $gt$libresoc.v:184728$11858_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185785$12047
+ cell $gt $gt$libresoc.v:184729$11859
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1001
- connect \Y $gt$libresoc.v:185785$12047_Y
+ connect \Y $gt$libresoc.v:184729$11859_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185786$12048
+ cell $gt $gt$libresoc.v:184730$11860
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1010
- connect \Y $gt$libresoc.v:185786$12048_Y
+ connect \Y $gt$libresoc.v:184730$11860_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185787$12049
+ cell $gt $gt$libresoc.v:184731$11861
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1011
- connect \Y $gt$libresoc.v:185787$12049_Y
+ connect \Y $gt$libresoc.v:184731$11861_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185788$12050
+ cell $gt $gt$libresoc.v:184732$11862
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1100
- connect \Y $gt$libresoc.v:185788$12050_Y
+ connect \Y $gt$libresoc.v:184732$11862_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185789$12051
+ cell $gt $gt$libresoc.v:184733$11863
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1101
- connect \Y $gt$libresoc.v:185789$12051_Y
+ connect \Y $gt$libresoc.v:184733$11863_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185790$12052
+ cell $gt $gt$libresoc.v:184734$11864
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1110
- connect \Y $gt$libresoc.v:185790$12052_Y
+ connect \Y $gt$libresoc.v:184734$11864_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185791$12053
+ cell $gt $gt$libresoc.v:184735$11865
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1111
- connect \Y $gt$libresoc.v:185791$12053_Y
+ connect \Y $gt$libresoc.v:184735$11865_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185792$12054
+ cell $gt $gt$libresoc.v:184736$11866
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10000
- connect \Y $gt$libresoc.v:185792$12054_Y
+ connect \Y $gt$libresoc.v:184736$11866_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185793$12055
+ cell $gt $gt$libresoc.v:184737$11867
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10001
- connect \Y $gt$libresoc.v:185793$12055_Y
+ connect \Y $gt$libresoc.v:184737$11867_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185794$12056
+ cell $gt $gt$libresoc.v:184738$11868
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10010
- connect \Y $gt$libresoc.v:185794$12056_Y
+ connect \Y $gt$libresoc.v:184738$11868_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185795$12057
+ cell $gt $gt$libresoc.v:184739$11869
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'1
- connect \Y $gt$libresoc.v:185795$12057_Y
+ connect \Y $gt$libresoc.v:184739$11869_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185796$12058
+ cell $gt $gt$libresoc.v:184740$11870
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10011
- connect \Y $gt$libresoc.v:185796$12058_Y
+ connect \Y $gt$libresoc.v:184740$11870_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185797$12059
+ cell $gt $gt$libresoc.v:184741$11871
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10100
- connect \Y $gt$libresoc.v:185797$12059_Y
+ connect \Y $gt$libresoc.v:184741$11871_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185798$12060
+ cell $gt $gt$libresoc.v:184742$11872
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10101
- connect \Y $gt$libresoc.v:185798$12060_Y
+ connect \Y $gt$libresoc.v:184742$11872_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185799$12061
+ cell $gt $gt$libresoc.v:184743$11873
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10110
- connect \Y $gt$libresoc.v:185799$12061_Y
+ connect \Y $gt$libresoc.v:184743$11873_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185800$12062
+ cell $gt $gt$libresoc.v:184744$11874
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10111
- connect \Y $gt$libresoc.v:185800$12062_Y
+ connect \Y $gt$libresoc.v:184744$11874_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185801$12063
+ cell $gt $gt$libresoc.v:184745$11875
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11000
- connect \Y $gt$libresoc.v:185801$12063_Y
+ connect \Y $gt$libresoc.v:184745$11875_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185802$12064
+ cell $gt $gt$libresoc.v:184746$11876
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11001
- connect \Y $gt$libresoc.v:185802$12064_Y
+ connect \Y $gt$libresoc.v:184746$11876_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185803$12065
+ cell $gt $gt$libresoc.v:184747$11877
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11010
- connect \Y $gt$libresoc.v:185803$12065_Y
+ connect \Y $gt$libresoc.v:184747$11877_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185804$12066
+ cell $gt $gt$libresoc.v:184748$11878
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11011
- connect \Y $gt$libresoc.v:185804$12066_Y
+ connect \Y $gt$libresoc.v:184748$11878_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185805$12067
+ cell $gt $gt$libresoc.v:184749$11879
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11100
- connect \Y $gt$libresoc.v:185805$12067_Y
+ connect \Y $gt$libresoc.v:184749$11879_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185806$12068
+ cell $gt $gt$libresoc.v:184750$11880
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'10
- connect \Y $gt$libresoc.v:185806$12068_Y
+ connect \Y $gt$libresoc.v:184750$11880_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185807$12069
+ cell $gt $gt$libresoc.v:184751$11881
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11101
- connect \Y $gt$libresoc.v:185807$12069_Y
+ connect \Y $gt$libresoc.v:184751$11881_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185808$12070
+ cell $gt $gt$libresoc.v:184752$11882
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11110
- connect \Y $gt$libresoc.v:185808$12070_Y
+ connect \Y $gt$libresoc.v:184752$11882_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185809$12071
+ cell $gt $gt$libresoc.v:184753$11883
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11111
- connect \Y $gt$libresoc.v:185809$12071_Y
+ connect \Y $gt$libresoc.v:184753$11883_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185810$12072
+ cell $gt $gt$libresoc.v:184754$11884
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100000
- connect \Y $gt$libresoc.v:185810$12072_Y
+ connect \Y $gt$libresoc.v:184754$11884_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185811$12073
+ cell $gt $gt$libresoc.v:184755$11885
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100001
- connect \Y $gt$libresoc.v:185811$12073_Y
+ connect \Y $gt$libresoc.v:184755$11885_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185812$12074
+ cell $gt $gt$libresoc.v:184756$11886
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100010
- connect \Y $gt$libresoc.v:185812$12074_Y
+ connect \Y $gt$libresoc.v:184756$11886_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185813$12075
+ cell $gt $gt$libresoc.v:184757$11887
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100011
- connect \Y $gt$libresoc.v:185813$12075_Y
+ connect \Y $gt$libresoc.v:184757$11887_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185814$12076
+ cell $gt $gt$libresoc.v:184758$11888
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100100
- connect \Y $gt$libresoc.v:185814$12076_Y
+ connect \Y $gt$libresoc.v:184758$11888_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185815$12077
+ cell $gt $gt$libresoc.v:184759$11889
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100101
- connect \Y $gt$libresoc.v:185815$12077_Y
+ connect \Y $gt$libresoc.v:184759$11889_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185816$12078
+ cell $gt $gt$libresoc.v:184760$11890
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100110
- connect \Y $gt$libresoc.v:185816$12078_Y
+ connect \Y $gt$libresoc.v:184760$11890_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185817$12079
+ cell $gt $gt$libresoc.v:184761$11891
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'11
- connect \Y $gt$libresoc.v:185817$12079_Y
+ connect \Y $gt$libresoc.v:184761$11891_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185818$12080
+ cell $gt $gt$libresoc.v:184762$11892
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100111
- connect \Y $gt$libresoc.v:185818$12080_Y
+ connect \Y $gt$libresoc.v:184762$11892_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185819$12081
+ cell $gt $gt$libresoc.v:184763$11893
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101000
- connect \Y $gt$libresoc.v:185819$12081_Y
+ connect \Y $gt$libresoc.v:184763$11893_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185820$12082
+ cell $gt $gt$libresoc.v:184764$11894
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101001
- connect \Y $gt$libresoc.v:185820$12082_Y
+ connect \Y $gt$libresoc.v:184764$11894_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185821$12083
+ cell $gt $gt$libresoc.v:184765$11895
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101010
- connect \Y $gt$libresoc.v:185821$12083_Y
+ connect \Y $gt$libresoc.v:184765$11895_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185822$12084
+ cell $gt $gt$libresoc.v:184766$11896
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101011
- connect \Y $gt$libresoc.v:185822$12084_Y
+ connect \Y $gt$libresoc.v:184766$11896_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185823$12085
+ cell $gt $gt$libresoc.v:184767$11897
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101100
- connect \Y $gt$libresoc.v:185823$12085_Y
+ connect \Y $gt$libresoc.v:184767$11897_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185824$12086
+ cell $gt $gt$libresoc.v:184768$11898
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101101
- connect \Y $gt$libresoc.v:185824$12086_Y
+ connect \Y $gt$libresoc.v:184768$11898_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185825$12087
+ cell $gt $gt$libresoc.v:184769$11899
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101110
- connect \Y $gt$libresoc.v:185825$12087_Y
+ connect \Y $gt$libresoc.v:184769$11899_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185826$12088
+ cell $gt $gt$libresoc.v:184770$11900
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101111
- connect \Y $gt$libresoc.v:185826$12088_Y
+ connect \Y $gt$libresoc.v:184770$11900_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:185827$12089
+ cell $gt $gt$libresoc.v:184771$11901
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110000
- connect \Y $gt$libresoc.v:185827$12089_Y
+ connect \Y $gt$libresoc.v:184771$11901_Y
end
- attribute \src "libresoc.v:185630.7-185630.20"
- process $proc$libresoc.v:185630$12091
+ attribute \src "libresoc.v:184574.7-184574.20"
+ process $proc$libresoc.v:184574$11903
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185828.3-186215.6"
- process $proc$libresoc.v:185828$12090
+ attribute \src "libresoc.v:184772.3-185159.6"
+ process $proc$libresoc.v:184772$11902
assign { } { }
assign { } { }
assign $0\mask[63:0] [0] $1\mask[0:0]
assign $0\mask[63:0] [61] $62\mask[61:61]
assign $0\mask[63:0] [62] $63\mask[62:62]
assign $0\mask[63:0] [63] $64\mask[63:63]
- attribute \src "libresoc.v:185829.5-185829.29"
+ attribute \src "libresoc.v:184773.5-184773.29"
switch \initial
- attribute \src "libresoc.v:185829.9-185829.17"
+ attribute \src "libresoc.v:184773.9-184773.17"
case 1'1
case
end
sync always
update \mask $0\mask[63:0]
end
- connect \$9 $gt$libresoc.v:185764$12026_Y
- connect \$99 $gt$libresoc.v:185765$12027_Y
- connect \$101 $gt$libresoc.v:185766$12028_Y
- connect \$103 $gt$libresoc.v:185767$12029_Y
- connect \$105 $gt$libresoc.v:185768$12030_Y
- connect \$107 $gt$libresoc.v:185769$12031_Y
- connect \$109 $gt$libresoc.v:185770$12032_Y
- connect \$111 $gt$libresoc.v:185771$12033_Y
- connect \$113 $gt$libresoc.v:185772$12034_Y
- connect \$115 $gt$libresoc.v:185773$12035_Y
- connect \$117 $gt$libresoc.v:185774$12036_Y
- connect \$11 $gt$libresoc.v:185775$12037_Y
- connect \$119 $gt$libresoc.v:185776$12038_Y
- connect \$121 $gt$libresoc.v:185777$12039_Y
- connect \$123 $gt$libresoc.v:185778$12040_Y
- connect \$125 $gt$libresoc.v:185779$12041_Y
- connect \$127 $gt$libresoc.v:185780$12042_Y
- connect \$13 $gt$libresoc.v:185781$12043_Y
- connect \$15 $gt$libresoc.v:185782$12044_Y
- connect \$17 $gt$libresoc.v:185783$12045_Y
- connect \$1 $gt$libresoc.v:185784$12046_Y
- connect \$19 $gt$libresoc.v:185785$12047_Y
- connect \$21 $gt$libresoc.v:185786$12048_Y
- connect \$23 $gt$libresoc.v:185787$12049_Y
- connect \$25 $gt$libresoc.v:185788$12050_Y
- connect \$27 $gt$libresoc.v:185789$12051_Y
- connect \$29 $gt$libresoc.v:185790$12052_Y
- connect \$31 $gt$libresoc.v:185791$12053_Y
- connect \$33 $gt$libresoc.v:185792$12054_Y
- connect \$35 $gt$libresoc.v:185793$12055_Y
- connect \$37 $gt$libresoc.v:185794$12056_Y
- connect \$3 $gt$libresoc.v:185795$12057_Y
- connect \$39 $gt$libresoc.v:185796$12058_Y
- connect \$41 $gt$libresoc.v:185797$12059_Y
- connect \$43 $gt$libresoc.v:185798$12060_Y
- connect \$45 $gt$libresoc.v:185799$12061_Y
- connect \$47 $gt$libresoc.v:185800$12062_Y
- connect \$49 $gt$libresoc.v:185801$12063_Y
- connect \$51 $gt$libresoc.v:185802$12064_Y
- connect \$53 $gt$libresoc.v:185803$12065_Y
- connect \$55 $gt$libresoc.v:185804$12066_Y
- connect \$57 $gt$libresoc.v:185805$12067_Y
- connect \$5 $gt$libresoc.v:185806$12068_Y
- connect \$59 $gt$libresoc.v:185807$12069_Y
- connect \$61 $gt$libresoc.v:185808$12070_Y
- connect \$63 $gt$libresoc.v:185809$12071_Y
- connect \$65 $gt$libresoc.v:185810$12072_Y
- connect \$67 $gt$libresoc.v:185811$12073_Y
- connect \$69 $gt$libresoc.v:185812$12074_Y
- connect \$71 $gt$libresoc.v:185813$12075_Y
- connect \$73 $gt$libresoc.v:185814$12076_Y
- connect \$75 $gt$libresoc.v:185815$12077_Y
- connect \$77 $gt$libresoc.v:185816$12078_Y
- connect \$7 $gt$libresoc.v:185817$12079_Y
- connect \$79 $gt$libresoc.v:185818$12080_Y
- connect \$81 $gt$libresoc.v:185819$12081_Y
- connect \$83 $gt$libresoc.v:185820$12082_Y
- connect \$85 $gt$libresoc.v:185821$12083_Y
- connect \$87 $gt$libresoc.v:185822$12084_Y
- connect \$89 $gt$libresoc.v:185823$12085_Y
- connect \$91 $gt$libresoc.v:185824$12086_Y
- connect \$93 $gt$libresoc.v:185825$12087_Y
- connect \$95 $gt$libresoc.v:185826$12088_Y
- connect \$97 $gt$libresoc.v:185827$12089_Y
+ connect \$9 $gt$libresoc.v:184708$11838_Y
+ connect \$99 $gt$libresoc.v:184709$11839_Y
+ connect \$101 $gt$libresoc.v:184710$11840_Y
+ connect \$103 $gt$libresoc.v:184711$11841_Y
+ connect \$105 $gt$libresoc.v:184712$11842_Y
+ connect \$107 $gt$libresoc.v:184713$11843_Y
+ connect \$109 $gt$libresoc.v:184714$11844_Y
+ connect \$111 $gt$libresoc.v:184715$11845_Y
+ connect \$113 $gt$libresoc.v:184716$11846_Y
+ connect \$115 $gt$libresoc.v:184717$11847_Y
+ connect \$117 $gt$libresoc.v:184718$11848_Y
+ connect \$11 $gt$libresoc.v:184719$11849_Y
+ connect \$119 $gt$libresoc.v:184720$11850_Y
+ connect \$121 $gt$libresoc.v:184721$11851_Y
+ connect \$123 $gt$libresoc.v:184722$11852_Y
+ connect \$125 $gt$libresoc.v:184723$11853_Y
+ connect \$127 $gt$libresoc.v:184724$11854_Y
+ connect \$13 $gt$libresoc.v:184725$11855_Y
+ connect \$15 $gt$libresoc.v:184726$11856_Y
+ connect \$17 $gt$libresoc.v:184727$11857_Y
+ connect \$1 $gt$libresoc.v:184728$11858_Y
+ connect \$19 $gt$libresoc.v:184729$11859_Y
+ connect \$21 $gt$libresoc.v:184730$11860_Y
+ connect \$23 $gt$libresoc.v:184731$11861_Y
+ connect \$25 $gt$libresoc.v:184732$11862_Y
+ connect \$27 $gt$libresoc.v:184733$11863_Y
+ connect \$29 $gt$libresoc.v:184734$11864_Y
+ connect \$31 $gt$libresoc.v:184735$11865_Y
+ connect \$33 $gt$libresoc.v:184736$11866_Y
+ connect \$35 $gt$libresoc.v:184737$11867_Y
+ connect \$37 $gt$libresoc.v:184738$11868_Y
+ connect \$3 $gt$libresoc.v:184739$11869_Y
+ connect \$39 $gt$libresoc.v:184740$11870_Y
+ connect \$41 $gt$libresoc.v:184741$11871_Y
+ connect \$43 $gt$libresoc.v:184742$11872_Y
+ connect \$45 $gt$libresoc.v:184743$11873_Y
+ connect \$47 $gt$libresoc.v:184744$11874_Y
+ connect \$49 $gt$libresoc.v:184745$11875_Y
+ connect \$51 $gt$libresoc.v:184746$11876_Y
+ connect \$53 $gt$libresoc.v:184747$11877_Y
+ connect \$55 $gt$libresoc.v:184748$11878_Y
+ connect \$57 $gt$libresoc.v:184749$11879_Y
+ connect \$5 $gt$libresoc.v:184750$11880_Y
+ connect \$59 $gt$libresoc.v:184751$11881_Y
+ connect \$61 $gt$libresoc.v:184752$11882_Y
+ connect \$63 $gt$libresoc.v:184753$11883_Y
+ connect \$65 $gt$libresoc.v:184754$11884_Y
+ connect \$67 $gt$libresoc.v:184755$11885_Y
+ connect \$69 $gt$libresoc.v:184756$11886_Y
+ connect \$71 $gt$libresoc.v:184757$11887_Y
+ connect \$73 $gt$libresoc.v:184758$11888_Y
+ connect \$75 $gt$libresoc.v:184759$11889_Y
+ connect \$77 $gt$libresoc.v:184760$11890_Y
+ connect \$7 $gt$libresoc.v:184761$11891_Y
+ connect \$79 $gt$libresoc.v:184762$11892_Y
+ connect \$81 $gt$libresoc.v:184763$11893_Y
+ connect \$83 $gt$libresoc.v:184764$11894_Y
+ connect \$85 $gt$libresoc.v:184765$11895_Y
+ connect \$87 $gt$libresoc.v:184766$11896_Y
+ connect \$89 $gt$libresoc.v:184767$11897_Y
+ connect \$91 $gt$libresoc.v:184768$11898_Y
+ connect \$93 $gt$libresoc.v:184769$11899_Y
+ connect \$95 $gt$libresoc.v:184770$11900_Y
+ connect \$97 $gt$libresoc.v:184771$11901_Y
end
-attribute \src "libresoc.v:186220.1-186278.10"
+attribute \src "libresoc.v:185164.1-185222.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l"
attribute \generator "nMigen"
module \rok_l
- attribute \src "libresoc.v:186221.7-186221.20"
+ attribute \src "libresoc.v:185165.7-185165.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186266.3-186274.6"
- wire $0\q_int$next[0:0]$12102
- attribute \src "libresoc.v:186264.3-186265.27"
+ attribute \src "libresoc.v:185210.3-185218.6"
+ wire $0\q_int$next[0:0]$11914
+ attribute \src "libresoc.v:185208.3-185209.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186266.3-186274.6"
- wire $1\q_int$next[0:0]$12103
- attribute \src "libresoc.v:186243.7-186243.19"
+ attribute \src "libresoc.v:185210.3-185218.6"
+ wire $1\q_int$next[0:0]$11915
+ attribute \src "libresoc.v:185187.7-185187.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186256.17-186256.96"
- wire $and$libresoc.v:186256$12092_Y
- attribute \src "libresoc.v:186261.17-186261.96"
- wire $and$libresoc.v:186261$12097_Y
- attribute \src "libresoc.v:186258.18-186258.94"
- wire $not$libresoc.v:186258$12094_Y
- attribute \src "libresoc.v:186260.17-186260.93"
- wire $not$libresoc.v:186260$12096_Y
- attribute \src "libresoc.v:186263.17-186263.93"
- wire $not$libresoc.v:186263$12099_Y
- attribute \src "libresoc.v:186257.18-186257.99"
- wire $or$libresoc.v:186257$12093_Y
- attribute \src "libresoc.v:186259.18-186259.100"
- wire $or$libresoc.v:186259$12095_Y
- attribute \src "libresoc.v:186262.17-186262.98"
- wire $or$libresoc.v:186262$12098_Y
+ attribute \src "libresoc.v:185200.17-185200.96"
+ wire $and$libresoc.v:185200$11904_Y
+ attribute \src "libresoc.v:185205.17-185205.96"
+ wire $and$libresoc.v:185205$11909_Y
+ attribute \src "libresoc.v:185202.18-185202.94"
+ wire $not$libresoc.v:185202$11906_Y
+ attribute \src "libresoc.v:185204.17-185204.93"
+ wire $not$libresoc.v:185204$11908_Y
+ attribute \src "libresoc.v:185207.17-185207.93"
+ wire $not$libresoc.v:185207$11911_Y
+ attribute \src "libresoc.v:185201.18-185201.99"
+ wire $or$libresoc.v:185201$11905_Y
+ attribute \src "libresoc.v:185203.18-185203.100"
+ wire $or$libresoc.v:185203$11907_Y
+ attribute \src "libresoc.v:185206.17-185206.98"
+ wire $or$libresoc.v:185206$11910_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186221.7-186221.15"
+ attribute \src "libresoc.v:185165.7-185165.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186256$12092
+ cell $and $and$libresoc.v:185200$11904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186256$12092_Y
+ connect \Y $and$libresoc.v:185200$11904_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186261$12097
+ cell $and $and$libresoc.v:185205$11909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186261$12097_Y
+ connect \Y $and$libresoc.v:185205$11909_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186258$12094
+ cell $not $not$libresoc.v:185202$11906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186258$12094_Y
+ connect \Y $not$libresoc.v:185202$11906_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186260$12096
+ cell $not $not$libresoc.v:185204$11908
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186260$12096_Y
+ connect \Y $not$libresoc.v:185204$11908_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186263$12099
+ cell $not $not$libresoc.v:185207$11911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186263$12099_Y
+ connect \Y $not$libresoc.v:185207$11911_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186257$12093
+ cell $or $or$libresoc.v:185201$11905
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186257$12093_Y
+ connect \Y $or$libresoc.v:185201$11905_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186259$12095
+ cell $or $or$libresoc.v:185203$11907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186259$12095_Y
+ connect \Y $or$libresoc.v:185203$11907_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186262$12098
+ cell $or $or$libresoc.v:185206$11910
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186262$12098_Y
+ connect \Y $or$libresoc.v:185206$11910_Y
end
- attribute \src "libresoc.v:186221.7-186221.20"
- process $proc$libresoc.v:186221$12104
+ attribute \src "libresoc.v:185165.7-185165.20"
+ process $proc$libresoc.v:185165$11916
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186243.7-186243.19"
- process $proc$libresoc.v:186243$12105
+ attribute \src "libresoc.v:185187.7-185187.19"
+ process $proc$libresoc.v:185187$11917
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186264.3-186265.27"
- process $proc$libresoc.v:186264$12100
+ attribute \src "libresoc.v:185208.3-185209.27"
+ process $proc$libresoc.v:185208$11912
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186266.3-186274.6"
- process $proc$libresoc.v:186266$12101
+ attribute \src "libresoc.v:185210.3-185218.6"
+ process $proc$libresoc.v:185210$11913
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12102 $1\q_int$next[0:0]$12103
- attribute \src "libresoc.v:186267.5-186267.29"
+ assign $0\q_int$next[0:0]$11914 $1\q_int$next[0:0]$11915
+ attribute \src "libresoc.v:185211.5-185211.29"
switch \initial
- attribute \src "libresoc.v:186267.9-186267.17"
+ attribute \src "libresoc.v:185211.9-185211.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12103 1'0
+ assign $1\q_int$next[0:0]$11915 1'0
case
- assign $1\q_int$next[0:0]$12103 \$5
+ assign $1\q_int$next[0:0]$11915 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12102
+ update \q_int$next $0\q_int$next[0:0]$11914
end
- connect \$9 $and$libresoc.v:186256$12092_Y
- connect \$11 $or$libresoc.v:186257$12093_Y
- connect \$13 $not$libresoc.v:186258$12094_Y
- connect \$15 $or$libresoc.v:186259$12095_Y
- connect \$1 $not$libresoc.v:186260$12096_Y
- connect \$3 $and$libresoc.v:186261$12097_Y
- connect \$5 $or$libresoc.v:186262$12098_Y
- connect \$7 $not$libresoc.v:186263$12099_Y
+ connect \$9 $and$libresoc.v:185200$11904_Y
+ connect \$11 $or$libresoc.v:185201$11905_Y
+ connect \$13 $not$libresoc.v:185202$11906_Y
+ connect \$15 $or$libresoc.v:185203$11907_Y
+ connect \$1 $not$libresoc.v:185204$11908_Y
+ connect \$3 $and$libresoc.v:185205$11909_Y
+ connect \$5 $or$libresoc.v:185206$11910_Y
+ connect \$7 $not$libresoc.v:185207$11911_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186282.1-186340.10"
+attribute \src "libresoc.v:185226.1-185284.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l"
attribute \generator "nMigen"
module \rok_l$105
- attribute \src "libresoc.v:186283.7-186283.20"
+ attribute \src "libresoc.v:185227.7-185227.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186328.3-186336.6"
- wire $0\q_int$next[0:0]$12116
- attribute \src "libresoc.v:186326.3-186327.27"
+ attribute \src "libresoc.v:185272.3-185280.6"
+ wire $0\q_int$next[0:0]$11928
+ attribute \src "libresoc.v:185270.3-185271.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186328.3-186336.6"
- wire $1\q_int$next[0:0]$12117
- attribute \src "libresoc.v:186305.7-186305.19"
+ attribute \src "libresoc.v:185272.3-185280.6"
+ wire $1\q_int$next[0:0]$11929
+ attribute \src "libresoc.v:185249.7-185249.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186318.17-186318.96"
- wire $and$libresoc.v:186318$12106_Y
- attribute \src "libresoc.v:186323.17-186323.96"
- wire $and$libresoc.v:186323$12111_Y
- attribute \src "libresoc.v:186320.18-186320.94"
- wire $not$libresoc.v:186320$12108_Y
- attribute \src "libresoc.v:186322.17-186322.93"
- wire $not$libresoc.v:186322$12110_Y
- attribute \src "libresoc.v:186325.17-186325.93"
- wire $not$libresoc.v:186325$12113_Y
- attribute \src "libresoc.v:186319.18-186319.99"
- wire $or$libresoc.v:186319$12107_Y
- attribute \src "libresoc.v:186321.18-186321.100"
- wire $or$libresoc.v:186321$12109_Y
- attribute \src "libresoc.v:186324.17-186324.98"
- wire $or$libresoc.v:186324$12112_Y
+ attribute \src "libresoc.v:185262.17-185262.96"
+ wire $and$libresoc.v:185262$11918_Y
+ attribute \src "libresoc.v:185267.17-185267.96"
+ wire $and$libresoc.v:185267$11923_Y
+ attribute \src "libresoc.v:185264.18-185264.94"
+ wire $not$libresoc.v:185264$11920_Y
+ attribute \src "libresoc.v:185266.17-185266.93"
+ wire $not$libresoc.v:185266$11922_Y
+ attribute \src "libresoc.v:185269.17-185269.93"
+ wire $not$libresoc.v:185269$11925_Y
+ attribute \src "libresoc.v:185263.18-185263.99"
+ wire $or$libresoc.v:185263$11919_Y
+ attribute \src "libresoc.v:185265.18-185265.100"
+ wire $or$libresoc.v:185265$11921_Y
+ attribute \src "libresoc.v:185268.17-185268.98"
+ wire $or$libresoc.v:185268$11924_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186283.7-186283.15"
+ attribute \src "libresoc.v:185227.7-185227.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186318$12106
+ cell $and $and$libresoc.v:185262$11918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186318$12106_Y
+ connect \Y $and$libresoc.v:185262$11918_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186323$12111
+ cell $and $and$libresoc.v:185267$11923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186323$12111_Y
+ connect \Y $and$libresoc.v:185267$11923_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186320$12108
+ cell $not $not$libresoc.v:185264$11920
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186320$12108_Y
+ connect \Y $not$libresoc.v:185264$11920_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186322$12110
+ cell $not $not$libresoc.v:185266$11922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186322$12110_Y
+ connect \Y $not$libresoc.v:185266$11922_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186325$12113
+ cell $not $not$libresoc.v:185269$11925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186325$12113_Y
+ connect \Y $not$libresoc.v:185269$11925_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186319$12107
+ cell $or $or$libresoc.v:185263$11919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186319$12107_Y
+ connect \Y $or$libresoc.v:185263$11919_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186321$12109
+ cell $or $or$libresoc.v:185265$11921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186321$12109_Y
+ connect \Y $or$libresoc.v:185265$11921_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186324$12112
+ cell $or $or$libresoc.v:185268$11924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186324$12112_Y
+ connect \Y $or$libresoc.v:185268$11924_Y
end
- attribute \src "libresoc.v:186283.7-186283.20"
- process $proc$libresoc.v:186283$12118
+ attribute \src "libresoc.v:185227.7-185227.20"
+ process $proc$libresoc.v:185227$11930
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186305.7-186305.19"
- process $proc$libresoc.v:186305$12119
+ attribute \src "libresoc.v:185249.7-185249.19"
+ process $proc$libresoc.v:185249$11931
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186326.3-186327.27"
- process $proc$libresoc.v:186326$12114
+ attribute \src "libresoc.v:185270.3-185271.27"
+ process $proc$libresoc.v:185270$11926
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186328.3-186336.6"
- process $proc$libresoc.v:186328$12115
+ attribute \src "libresoc.v:185272.3-185280.6"
+ process $proc$libresoc.v:185272$11927
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12116 $1\q_int$next[0:0]$12117
- attribute \src "libresoc.v:186329.5-186329.29"
+ assign $0\q_int$next[0:0]$11928 $1\q_int$next[0:0]$11929
+ attribute \src "libresoc.v:185273.5-185273.29"
switch \initial
- attribute \src "libresoc.v:186329.9-186329.17"
+ attribute \src "libresoc.v:185273.9-185273.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12117 1'0
+ assign $1\q_int$next[0:0]$11929 1'0
case
- assign $1\q_int$next[0:0]$12117 \$5
+ assign $1\q_int$next[0:0]$11929 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12116
+ update \q_int$next $0\q_int$next[0:0]$11928
end
- connect \$9 $and$libresoc.v:186318$12106_Y
- connect \$11 $or$libresoc.v:186319$12107_Y
- connect \$13 $not$libresoc.v:186320$12108_Y
- connect \$15 $or$libresoc.v:186321$12109_Y
- connect \$1 $not$libresoc.v:186322$12110_Y
- connect \$3 $and$libresoc.v:186323$12111_Y
- connect \$5 $or$libresoc.v:186324$12112_Y
- connect \$7 $not$libresoc.v:186325$12113_Y
+ connect \$9 $and$libresoc.v:185262$11918_Y
+ connect \$11 $or$libresoc.v:185263$11919_Y
+ connect \$13 $not$libresoc.v:185264$11920_Y
+ connect \$15 $or$libresoc.v:185265$11921_Y
+ connect \$1 $not$libresoc.v:185266$11922_Y
+ connect \$3 $and$libresoc.v:185267$11923_Y
+ connect \$5 $or$libresoc.v:185268$11924_Y
+ connect \$7 $not$libresoc.v:185269$11925_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186344.1-186402.10"
+attribute \src "libresoc.v:185288.1-185346.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l"
attribute \generator "nMigen"
module \rok_l$123
- attribute \src "libresoc.v:186345.7-186345.20"
+ attribute \src "libresoc.v:185289.7-185289.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186390.3-186398.6"
- wire $0\q_int$next[0:0]$12130
- attribute \src "libresoc.v:186388.3-186389.27"
+ attribute \src "libresoc.v:185334.3-185342.6"
+ wire $0\q_int$next[0:0]$11942
+ attribute \src "libresoc.v:185332.3-185333.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186390.3-186398.6"
- wire $1\q_int$next[0:0]$12131
- attribute \src "libresoc.v:186367.7-186367.19"
+ attribute \src "libresoc.v:185334.3-185342.6"
+ wire $1\q_int$next[0:0]$11943
+ attribute \src "libresoc.v:185311.7-185311.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186380.17-186380.96"
- wire $and$libresoc.v:186380$12120_Y
- attribute \src "libresoc.v:186385.17-186385.96"
- wire $and$libresoc.v:186385$12125_Y
- attribute \src "libresoc.v:186382.18-186382.94"
- wire $not$libresoc.v:186382$12122_Y
- attribute \src "libresoc.v:186384.17-186384.93"
- wire $not$libresoc.v:186384$12124_Y
- attribute \src "libresoc.v:186387.17-186387.93"
- wire $not$libresoc.v:186387$12127_Y
- attribute \src "libresoc.v:186381.18-186381.99"
- wire $or$libresoc.v:186381$12121_Y
- attribute \src "libresoc.v:186383.18-186383.100"
- wire $or$libresoc.v:186383$12123_Y
- attribute \src "libresoc.v:186386.17-186386.98"
- wire $or$libresoc.v:186386$12126_Y
+ attribute \src "libresoc.v:185324.17-185324.96"
+ wire $and$libresoc.v:185324$11932_Y
+ attribute \src "libresoc.v:185329.17-185329.96"
+ wire $and$libresoc.v:185329$11937_Y
+ attribute \src "libresoc.v:185326.18-185326.94"
+ wire $not$libresoc.v:185326$11934_Y
+ attribute \src "libresoc.v:185328.17-185328.93"
+ wire $not$libresoc.v:185328$11936_Y
+ attribute \src "libresoc.v:185331.17-185331.93"
+ wire $not$libresoc.v:185331$11939_Y
+ attribute \src "libresoc.v:185325.18-185325.99"
+ wire $or$libresoc.v:185325$11933_Y
+ attribute \src "libresoc.v:185327.18-185327.100"
+ wire $or$libresoc.v:185327$11935_Y
+ attribute \src "libresoc.v:185330.17-185330.98"
+ wire $or$libresoc.v:185330$11938_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186345.7-186345.15"
+ attribute \src "libresoc.v:185289.7-185289.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186380$12120
+ cell $and $and$libresoc.v:185324$11932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186380$12120_Y
+ connect \Y $and$libresoc.v:185324$11932_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186385$12125
+ cell $and $and$libresoc.v:185329$11937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186385$12125_Y
+ connect \Y $and$libresoc.v:185329$11937_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186382$12122
+ cell $not $not$libresoc.v:185326$11934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186382$12122_Y
+ connect \Y $not$libresoc.v:185326$11934_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186384$12124
+ cell $not $not$libresoc.v:185328$11936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186384$12124_Y
+ connect \Y $not$libresoc.v:185328$11936_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186387$12127
+ cell $not $not$libresoc.v:185331$11939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186387$12127_Y
+ connect \Y $not$libresoc.v:185331$11939_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186381$12121
+ cell $or $or$libresoc.v:185325$11933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186381$12121_Y
+ connect \Y $or$libresoc.v:185325$11933_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186383$12123
+ cell $or $or$libresoc.v:185327$11935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186383$12123_Y
+ connect \Y $or$libresoc.v:185327$11935_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186386$12126
+ cell $or $or$libresoc.v:185330$11938
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186386$12126_Y
+ connect \Y $or$libresoc.v:185330$11938_Y
end
- attribute \src "libresoc.v:186345.7-186345.20"
- process $proc$libresoc.v:186345$12132
+ attribute \src "libresoc.v:185289.7-185289.20"
+ process $proc$libresoc.v:185289$11944
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186367.7-186367.19"
- process $proc$libresoc.v:186367$12133
+ attribute \src "libresoc.v:185311.7-185311.19"
+ process $proc$libresoc.v:185311$11945
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186388.3-186389.27"
- process $proc$libresoc.v:186388$12128
+ attribute \src "libresoc.v:185332.3-185333.27"
+ process $proc$libresoc.v:185332$11940
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186390.3-186398.6"
- process $proc$libresoc.v:186390$12129
+ attribute \src "libresoc.v:185334.3-185342.6"
+ process $proc$libresoc.v:185334$11941
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12130 $1\q_int$next[0:0]$12131
- attribute \src "libresoc.v:186391.5-186391.29"
+ assign $0\q_int$next[0:0]$11942 $1\q_int$next[0:0]$11943
+ attribute \src "libresoc.v:185335.5-185335.29"
switch \initial
- attribute \src "libresoc.v:186391.9-186391.17"
+ attribute \src "libresoc.v:185335.9-185335.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12131 1'0
+ assign $1\q_int$next[0:0]$11943 1'0
case
- assign $1\q_int$next[0:0]$12131 \$5
+ assign $1\q_int$next[0:0]$11943 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12130
+ update \q_int$next $0\q_int$next[0:0]$11942
end
- connect \$9 $and$libresoc.v:186380$12120_Y
- connect \$11 $or$libresoc.v:186381$12121_Y
- connect \$13 $not$libresoc.v:186382$12122_Y
- connect \$15 $or$libresoc.v:186383$12123_Y
- connect \$1 $not$libresoc.v:186384$12124_Y
- connect \$3 $and$libresoc.v:186385$12125_Y
- connect \$5 $or$libresoc.v:186386$12126_Y
- connect \$7 $not$libresoc.v:186387$12127_Y
+ connect \$9 $and$libresoc.v:185324$11932_Y
+ connect \$11 $or$libresoc.v:185325$11933_Y
+ connect \$13 $not$libresoc.v:185326$11934_Y
+ connect \$15 $or$libresoc.v:185327$11935_Y
+ connect \$1 $not$libresoc.v:185328$11936_Y
+ connect \$3 $and$libresoc.v:185329$11937_Y
+ connect \$5 $or$libresoc.v:185330$11938_Y
+ connect \$7 $not$libresoc.v:185331$11939_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186406.1-186464.10"
+attribute \src "libresoc.v:185350.1-185408.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l"
attribute \generator "nMigen"
module \rok_l$14
- attribute \src "libresoc.v:186407.7-186407.20"
+ attribute \src "libresoc.v:185351.7-185351.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186452.3-186460.6"
- wire $0\q_int$next[0:0]$12144
- attribute \src "libresoc.v:186450.3-186451.27"
+ attribute \src "libresoc.v:185396.3-185404.6"
+ wire $0\q_int$next[0:0]$11956
+ attribute \src "libresoc.v:185394.3-185395.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186452.3-186460.6"
- wire $1\q_int$next[0:0]$12145
- attribute \src "libresoc.v:186429.7-186429.19"
+ attribute \src "libresoc.v:185396.3-185404.6"
+ wire $1\q_int$next[0:0]$11957
+ attribute \src "libresoc.v:185373.7-185373.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186442.17-186442.96"
- wire $and$libresoc.v:186442$12134_Y
- attribute \src "libresoc.v:186447.17-186447.96"
- wire $and$libresoc.v:186447$12139_Y
- attribute \src "libresoc.v:186444.18-186444.94"
- wire $not$libresoc.v:186444$12136_Y
- attribute \src "libresoc.v:186446.17-186446.93"
- wire $not$libresoc.v:186446$12138_Y
- attribute \src "libresoc.v:186449.17-186449.93"
- wire $not$libresoc.v:186449$12141_Y
- attribute \src "libresoc.v:186443.18-186443.99"
- wire $or$libresoc.v:186443$12135_Y
- attribute \src "libresoc.v:186445.18-186445.100"
- wire $or$libresoc.v:186445$12137_Y
- attribute \src "libresoc.v:186448.17-186448.98"
- wire $or$libresoc.v:186448$12140_Y
+ attribute \src "libresoc.v:185386.17-185386.96"
+ wire $and$libresoc.v:185386$11946_Y
+ attribute \src "libresoc.v:185391.17-185391.96"
+ wire $and$libresoc.v:185391$11951_Y
+ attribute \src "libresoc.v:185388.18-185388.94"
+ wire $not$libresoc.v:185388$11948_Y
+ attribute \src "libresoc.v:185390.17-185390.93"
+ wire $not$libresoc.v:185390$11950_Y
+ attribute \src "libresoc.v:185393.17-185393.93"
+ wire $not$libresoc.v:185393$11953_Y
+ attribute \src "libresoc.v:185387.18-185387.99"
+ wire $or$libresoc.v:185387$11947_Y
+ attribute \src "libresoc.v:185389.18-185389.100"
+ wire $or$libresoc.v:185389$11949_Y
+ attribute \src "libresoc.v:185392.17-185392.98"
+ wire $or$libresoc.v:185392$11952_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186407.7-186407.15"
+ attribute \src "libresoc.v:185351.7-185351.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186442$12134
+ cell $and $and$libresoc.v:185386$11946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186442$12134_Y
+ connect \Y $and$libresoc.v:185386$11946_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186447$12139
+ cell $and $and$libresoc.v:185391$11951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186447$12139_Y
+ connect \Y $and$libresoc.v:185391$11951_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186444$12136
+ cell $not $not$libresoc.v:185388$11948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186444$12136_Y
+ connect \Y $not$libresoc.v:185388$11948_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186446$12138
+ cell $not $not$libresoc.v:185390$11950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186446$12138_Y
+ connect \Y $not$libresoc.v:185390$11950_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186449$12141
+ cell $not $not$libresoc.v:185393$11953
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186449$12141_Y
+ connect \Y $not$libresoc.v:185393$11953_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186443$12135
+ cell $or $or$libresoc.v:185387$11947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186443$12135_Y
+ connect \Y $or$libresoc.v:185387$11947_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186445$12137
+ cell $or $or$libresoc.v:185389$11949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186445$12137_Y
+ connect \Y $or$libresoc.v:185389$11949_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186448$12140
+ cell $or $or$libresoc.v:185392$11952
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186448$12140_Y
+ connect \Y $or$libresoc.v:185392$11952_Y
end
- attribute \src "libresoc.v:186407.7-186407.20"
- process $proc$libresoc.v:186407$12146
+ attribute \src "libresoc.v:185351.7-185351.20"
+ process $proc$libresoc.v:185351$11958
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186429.7-186429.19"
- process $proc$libresoc.v:186429$12147
+ attribute \src "libresoc.v:185373.7-185373.19"
+ process $proc$libresoc.v:185373$11959
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186450.3-186451.27"
- process $proc$libresoc.v:186450$12142
+ attribute \src "libresoc.v:185394.3-185395.27"
+ process $proc$libresoc.v:185394$11954
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186452.3-186460.6"
- process $proc$libresoc.v:186452$12143
+ attribute \src "libresoc.v:185396.3-185404.6"
+ process $proc$libresoc.v:185396$11955
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12144 $1\q_int$next[0:0]$12145
- attribute \src "libresoc.v:186453.5-186453.29"
+ assign $0\q_int$next[0:0]$11956 $1\q_int$next[0:0]$11957
+ attribute \src "libresoc.v:185397.5-185397.29"
switch \initial
- attribute \src "libresoc.v:186453.9-186453.17"
+ attribute \src "libresoc.v:185397.9-185397.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12145 1'0
+ assign $1\q_int$next[0:0]$11957 1'0
case
- assign $1\q_int$next[0:0]$12145 \$5
+ assign $1\q_int$next[0:0]$11957 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12144
+ update \q_int$next $0\q_int$next[0:0]$11956
end
- connect \$9 $and$libresoc.v:186442$12134_Y
- connect \$11 $or$libresoc.v:186443$12135_Y
- connect \$13 $not$libresoc.v:186444$12136_Y
- connect \$15 $or$libresoc.v:186445$12137_Y
- connect \$1 $not$libresoc.v:186446$12138_Y
- connect \$3 $and$libresoc.v:186447$12139_Y
- connect \$5 $or$libresoc.v:186448$12140_Y
- connect \$7 $not$libresoc.v:186449$12141_Y
+ connect \$9 $and$libresoc.v:185386$11946_Y
+ connect \$11 $or$libresoc.v:185387$11947_Y
+ connect \$13 $not$libresoc.v:185388$11948_Y
+ connect \$15 $or$libresoc.v:185389$11949_Y
+ connect \$1 $not$libresoc.v:185390$11950_Y
+ connect \$3 $and$libresoc.v:185391$11951_Y
+ connect \$5 $or$libresoc.v:185392$11952_Y
+ connect \$7 $not$libresoc.v:185393$11953_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186468.1-186526.10"
+attribute \src "libresoc.v:185412.1-185470.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l"
attribute \generator "nMigen"
module \rok_l$27
- attribute \src "libresoc.v:186469.7-186469.20"
+ attribute \src "libresoc.v:185413.7-185413.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186514.3-186522.6"
- wire $0\q_int$next[0:0]$12158
- attribute \src "libresoc.v:186512.3-186513.27"
+ attribute \src "libresoc.v:185458.3-185466.6"
+ wire $0\q_int$next[0:0]$11970
+ attribute \src "libresoc.v:185456.3-185457.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186514.3-186522.6"
- wire $1\q_int$next[0:0]$12159
- attribute \src "libresoc.v:186491.7-186491.19"
+ attribute \src "libresoc.v:185458.3-185466.6"
+ wire $1\q_int$next[0:0]$11971
+ attribute \src "libresoc.v:185435.7-185435.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186504.17-186504.96"
- wire $and$libresoc.v:186504$12148_Y
- attribute \src "libresoc.v:186509.17-186509.96"
- wire $and$libresoc.v:186509$12153_Y
- attribute \src "libresoc.v:186506.18-186506.94"
- wire $not$libresoc.v:186506$12150_Y
- attribute \src "libresoc.v:186508.17-186508.93"
- wire $not$libresoc.v:186508$12152_Y
- attribute \src "libresoc.v:186511.17-186511.93"
- wire $not$libresoc.v:186511$12155_Y
- attribute \src "libresoc.v:186505.18-186505.99"
- wire $or$libresoc.v:186505$12149_Y
- attribute \src "libresoc.v:186507.18-186507.100"
- wire $or$libresoc.v:186507$12151_Y
- attribute \src "libresoc.v:186510.17-186510.98"
- wire $or$libresoc.v:186510$12154_Y
+ attribute \src "libresoc.v:185448.17-185448.96"
+ wire $and$libresoc.v:185448$11960_Y
+ attribute \src "libresoc.v:185453.17-185453.96"
+ wire $and$libresoc.v:185453$11965_Y
+ attribute \src "libresoc.v:185450.18-185450.94"
+ wire $not$libresoc.v:185450$11962_Y
+ attribute \src "libresoc.v:185452.17-185452.93"
+ wire $not$libresoc.v:185452$11964_Y
+ attribute \src "libresoc.v:185455.17-185455.93"
+ wire $not$libresoc.v:185455$11967_Y
+ attribute \src "libresoc.v:185449.18-185449.99"
+ wire $or$libresoc.v:185449$11961_Y
+ attribute \src "libresoc.v:185451.18-185451.100"
+ wire $or$libresoc.v:185451$11963_Y
+ attribute \src "libresoc.v:185454.17-185454.98"
+ wire $or$libresoc.v:185454$11966_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186469.7-186469.15"
+ attribute \src "libresoc.v:185413.7-185413.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186504$12148
+ cell $and $and$libresoc.v:185448$11960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186504$12148_Y
+ connect \Y $and$libresoc.v:185448$11960_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186509$12153
+ cell $and $and$libresoc.v:185453$11965
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186509$12153_Y
+ connect \Y $and$libresoc.v:185453$11965_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186506$12150
+ cell $not $not$libresoc.v:185450$11962
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186506$12150_Y
+ connect \Y $not$libresoc.v:185450$11962_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186508$12152
+ cell $not $not$libresoc.v:185452$11964
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186508$12152_Y
+ connect \Y $not$libresoc.v:185452$11964_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186511$12155
+ cell $not $not$libresoc.v:185455$11967
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186511$12155_Y
+ connect \Y $not$libresoc.v:185455$11967_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186505$12149
+ cell $or $or$libresoc.v:185449$11961
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186505$12149_Y
+ connect \Y $or$libresoc.v:185449$11961_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186507$12151
+ cell $or $or$libresoc.v:185451$11963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186507$12151_Y
+ connect \Y $or$libresoc.v:185451$11963_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186510$12154
+ cell $or $or$libresoc.v:185454$11966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186510$12154_Y
+ connect \Y $or$libresoc.v:185454$11966_Y
end
- attribute \src "libresoc.v:186469.7-186469.20"
- process $proc$libresoc.v:186469$12160
+ attribute \src "libresoc.v:185413.7-185413.20"
+ process $proc$libresoc.v:185413$11972
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186491.7-186491.19"
- process $proc$libresoc.v:186491$12161
+ attribute \src "libresoc.v:185435.7-185435.19"
+ process $proc$libresoc.v:185435$11973
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186512.3-186513.27"
- process $proc$libresoc.v:186512$12156
+ attribute \src "libresoc.v:185456.3-185457.27"
+ process $proc$libresoc.v:185456$11968
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186514.3-186522.6"
- process $proc$libresoc.v:186514$12157
+ attribute \src "libresoc.v:185458.3-185466.6"
+ process $proc$libresoc.v:185458$11969
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12158 $1\q_int$next[0:0]$12159
- attribute \src "libresoc.v:186515.5-186515.29"
+ assign $0\q_int$next[0:0]$11970 $1\q_int$next[0:0]$11971
+ attribute \src "libresoc.v:185459.5-185459.29"
switch \initial
- attribute \src "libresoc.v:186515.9-186515.17"
+ attribute \src "libresoc.v:185459.9-185459.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12159 1'0
+ assign $1\q_int$next[0:0]$11971 1'0
case
- assign $1\q_int$next[0:0]$12159 \$5
+ assign $1\q_int$next[0:0]$11971 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12158
+ update \q_int$next $0\q_int$next[0:0]$11970
end
- connect \$9 $and$libresoc.v:186504$12148_Y
- connect \$11 $or$libresoc.v:186505$12149_Y
- connect \$13 $not$libresoc.v:186506$12150_Y
- connect \$15 $or$libresoc.v:186507$12151_Y
- connect \$1 $not$libresoc.v:186508$12152_Y
- connect \$3 $and$libresoc.v:186509$12153_Y
- connect \$5 $or$libresoc.v:186510$12154_Y
- connect \$7 $not$libresoc.v:186511$12155_Y
+ connect \$9 $and$libresoc.v:185448$11960_Y
+ connect \$11 $or$libresoc.v:185449$11961_Y
+ connect \$13 $not$libresoc.v:185450$11962_Y
+ connect \$15 $or$libresoc.v:185451$11963_Y
+ connect \$1 $not$libresoc.v:185452$11964_Y
+ connect \$3 $and$libresoc.v:185453$11965_Y
+ connect \$5 $or$libresoc.v:185454$11966_Y
+ connect \$7 $not$libresoc.v:185455$11967_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186530.1-186588.10"
+attribute \src "libresoc.v:185474.1-185532.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l"
attribute \generator "nMigen"
module \rok_l$43
- attribute \src "libresoc.v:186531.7-186531.20"
+ attribute \src "libresoc.v:185475.7-185475.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186576.3-186584.6"
- wire $0\q_int$next[0:0]$12172
- attribute \src "libresoc.v:186574.3-186575.27"
+ attribute \src "libresoc.v:185520.3-185528.6"
+ wire $0\q_int$next[0:0]$11984
+ attribute \src "libresoc.v:185518.3-185519.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186576.3-186584.6"
- wire $1\q_int$next[0:0]$12173
- attribute \src "libresoc.v:186553.7-186553.19"
+ attribute \src "libresoc.v:185520.3-185528.6"
+ wire $1\q_int$next[0:0]$11985
+ attribute \src "libresoc.v:185497.7-185497.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186566.17-186566.96"
- wire $and$libresoc.v:186566$12162_Y
- attribute \src "libresoc.v:186571.17-186571.96"
- wire $and$libresoc.v:186571$12167_Y
- attribute \src "libresoc.v:186568.18-186568.94"
- wire $not$libresoc.v:186568$12164_Y
- attribute \src "libresoc.v:186570.17-186570.93"
- wire $not$libresoc.v:186570$12166_Y
- attribute \src "libresoc.v:186573.17-186573.93"
- wire $not$libresoc.v:186573$12169_Y
- attribute \src "libresoc.v:186567.18-186567.99"
- wire $or$libresoc.v:186567$12163_Y
- attribute \src "libresoc.v:186569.18-186569.100"
- wire $or$libresoc.v:186569$12165_Y
- attribute \src "libresoc.v:186572.17-186572.98"
- wire $or$libresoc.v:186572$12168_Y
+ attribute \src "libresoc.v:185510.17-185510.96"
+ wire $and$libresoc.v:185510$11974_Y
+ attribute \src "libresoc.v:185515.17-185515.96"
+ wire $and$libresoc.v:185515$11979_Y
+ attribute \src "libresoc.v:185512.18-185512.94"
+ wire $not$libresoc.v:185512$11976_Y
+ attribute \src "libresoc.v:185514.17-185514.93"
+ wire $not$libresoc.v:185514$11978_Y
+ attribute \src "libresoc.v:185517.17-185517.93"
+ wire $not$libresoc.v:185517$11981_Y
+ attribute \src "libresoc.v:185511.18-185511.99"
+ wire $or$libresoc.v:185511$11975_Y
+ attribute \src "libresoc.v:185513.18-185513.100"
+ wire $or$libresoc.v:185513$11977_Y
+ attribute \src "libresoc.v:185516.17-185516.98"
+ wire $or$libresoc.v:185516$11980_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186531.7-186531.15"
+ attribute \src "libresoc.v:185475.7-185475.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186566$12162
+ cell $and $and$libresoc.v:185510$11974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186566$12162_Y
+ connect \Y $and$libresoc.v:185510$11974_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186571$12167
+ cell $and $and$libresoc.v:185515$11979
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186571$12167_Y
+ connect \Y $and$libresoc.v:185515$11979_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186568$12164
+ cell $not $not$libresoc.v:185512$11976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186568$12164_Y
+ connect \Y $not$libresoc.v:185512$11976_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186570$12166
+ cell $not $not$libresoc.v:185514$11978
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186570$12166_Y
+ connect \Y $not$libresoc.v:185514$11978_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186573$12169
+ cell $not $not$libresoc.v:185517$11981
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186573$12169_Y
+ connect \Y $not$libresoc.v:185517$11981_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186567$12163
+ cell $or $or$libresoc.v:185511$11975
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186567$12163_Y
+ connect \Y $or$libresoc.v:185511$11975_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186569$12165
+ cell $or $or$libresoc.v:185513$11977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186569$12165_Y
+ connect \Y $or$libresoc.v:185513$11977_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186572$12168
+ cell $or $or$libresoc.v:185516$11980
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186572$12168_Y
+ connect \Y $or$libresoc.v:185516$11980_Y
end
- attribute \src "libresoc.v:186531.7-186531.20"
- process $proc$libresoc.v:186531$12174
+ attribute \src "libresoc.v:185475.7-185475.20"
+ process $proc$libresoc.v:185475$11986
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186553.7-186553.19"
- process $proc$libresoc.v:186553$12175
+ attribute \src "libresoc.v:185497.7-185497.19"
+ process $proc$libresoc.v:185497$11987
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186574.3-186575.27"
- process $proc$libresoc.v:186574$12170
+ attribute \src "libresoc.v:185518.3-185519.27"
+ process $proc$libresoc.v:185518$11982
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186576.3-186584.6"
- process $proc$libresoc.v:186576$12171
+ attribute \src "libresoc.v:185520.3-185528.6"
+ process $proc$libresoc.v:185520$11983
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12172 $1\q_int$next[0:0]$12173
- attribute \src "libresoc.v:186577.5-186577.29"
+ assign $0\q_int$next[0:0]$11984 $1\q_int$next[0:0]$11985
+ attribute \src "libresoc.v:185521.5-185521.29"
switch \initial
- attribute \src "libresoc.v:186577.9-186577.17"
+ attribute \src "libresoc.v:185521.9-185521.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12173 1'0
+ assign $1\q_int$next[0:0]$11985 1'0
case
- assign $1\q_int$next[0:0]$12173 \$5
+ assign $1\q_int$next[0:0]$11985 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12172
+ update \q_int$next $0\q_int$next[0:0]$11984
end
- connect \$9 $and$libresoc.v:186566$12162_Y
- connect \$11 $or$libresoc.v:186567$12163_Y
- connect \$13 $not$libresoc.v:186568$12164_Y
- connect \$15 $or$libresoc.v:186569$12165_Y
- connect \$1 $not$libresoc.v:186570$12166_Y
- connect \$3 $and$libresoc.v:186571$12167_Y
- connect \$5 $or$libresoc.v:186572$12168_Y
- connect \$7 $not$libresoc.v:186573$12169_Y
+ connect \$9 $and$libresoc.v:185510$11974_Y
+ connect \$11 $or$libresoc.v:185511$11975_Y
+ connect \$13 $not$libresoc.v:185512$11976_Y
+ connect \$15 $or$libresoc.v:185513$11977_Y
+ connect \$1 $not$libresoc.v:185514$11978_Y
+ connect \$3 $and$libresoc.v:185515$11979_Y
+ connect \$5 $or$libresoc.v:185516$11980_Y
+ connect \$7 $not$libresoc.v:185517$11981_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186592.1-186650.10"
+attribute \src "libresoc.v:185536.1-185594.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l"
attribute \generator "nMigen"
module \rok_l$59
- attribute \src "libresoc.v:186593.7-186593.20"
+ attribute \src "libresoc.v:185537.7-185537.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186638.3-186646.6"
- wire $0\q_int$next[0:0]$12186
- attribute \src "libresoc.v:186636.3-186637.27"
+ attribute \src "libresoc.v:185582.3-185590.6"
+ wire $0\q_int$next[0:0]$11998
+ attribute \src "libresoc.v:185580.3-185581.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186638.3-186646.6"
- wire $1\q_int$next[0:0]$12187
- attribute \src "libresoc.v:186615.7-186615.19"
+ attribute \src "libresoc.v:185582.3-185590.6"
+ wire $1\q_int$next[0:0]$11999
+ attribute \src "libresoc.v:185559.7-185559.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186628.17-186628.96"
- wire $and$libresoc.v:186628$12176_Y
- attribute \src "libresoc.v:186633.17-186633.96"
- wire $and$libresoc.v:186633$12181_Y
- attribute \src "libresoc.v:186630.18-186630.94"
- wire $not$libresoc.v:186630$12178_Y
- attribute \src "libresoc.v:186632.17-186632.93"
- wire $not$libresoc.v:186632$12180_Y
- attribute \src "libresoc.v:186635.17-186635.93"
- wire $not$libresoc.v:186635$12183_Y
- attribute \src "libresoc.v:186629.18-186629.99"
- wire $or$libresoc.v:186629$12177_Y
- attribute \src "libresoc.v:186631.18-186631.100"
- wire $or$libresoc.v:186631$12179_Y
- attribute \src "libresoc.v:186634.17-186634.98"
- wire $or$libresoc.v:186634$12182_Y
+ attribute \src "libresoc.v:185572.17-185572.96"
+ wire $and$libresoc.v:185572$11988_Y
+ attribute \src "libresoc.v:185577.17-185577.96"
+ wire $and$libresoc.v:185577$11993_Y
+ attribute \src "libresoc.v:185574.18-185574.94"
+ wire $not$libresoc.v:185574$11990_Y
+ attribute \src "libresoc.v:185576.17-185576.93"
+ wire $not$libresoc.v:185576$11992_Y
+ attribute \src "libresoc.v:185579.17-185579.93"
+ wire $not$libresoc.v:185579$11995_Y
+ attribute \src "libresoc.v:185573.18-185573.99"
+ wire $or$libresoc.v:185573$11989_Y
+ attribute \src "libresoc.v:185575.18-185575.100"
+ wire $or$libresoc.v:185575$11991_Y
+ attribute \src "libresoc.v:185578.17-185578.98"
+ wire $or$libresoc.v:185578$11994_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186593.7-186593.15"
+ attribute \src "libresoc.v:185537.7-185537.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186628$12176
+ cell $and $and$libresoc.v:185572$11988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186628$12176_Y
+ connect \Y $and$libresoc.v:185572$11988_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186633$12181
+ cell $and $and$libresoc.v:185577$11993
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186633$12181_Y
+ connect \Y $and$libresoc.v:185577$11993_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186630$12178
+ cell $not $not$libresoc.v:185574$11990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186630$12178_Y
+ connect \Y $not$libresoc.v:185574$11990_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186632$12180
+ cell $not $not$libresoc.v:185576$11992
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186632$12180_Y
+ connect \Y $not$libresoc.v:185576$11992_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186635$12183
+ cell $not $not$libresoc.v:185579$11995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186635$12183_Y
+ connect \Y $not$libresoc.v:185579$11995_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186629$12177
+ cell $or $or$libresoc.v:185573$11989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186629$12177_Y
+ connect \Y $or$libresoc.v:185573$11989_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186631$12179
+ cell $or $or$libresoc.v:185575$11991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186631$12179_Y
+ connect \Y $or$libresoc.v:185575$11991_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186634$12182
+ cell $or $or$libresoc.v:185578$11994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186634$12182_Y
+ connect \Y $or$libresoc.v:185578$11994_Y
end
- attribute \src "libresoc.v:186593.7-186593.20"
- process $proc$libresoc.v:186593$12188
+ attribute \src "libresoc.v:185537.7-185537.20"
+ process $proc$libresoc.v:185537$12000
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186615.7-186615.19"
- process $proc$libresoc.v:186615$12189
+ attribute \src "libresoc.v:185559.7-185559.19"
+ process $proc$libresoc.v:185559$12001
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186636.3-186637.27"
- process $proc$libresoc.v:186636$12184
+ attribute \src "libresoc.v:185580.3-185581.27"
+ process $proc$libresoc.v:185580$11996
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186638.3-186646.6"
- process $proc$libresoc.v:186638$12185
+ attribute \src "libresoc.v:185582.3-185590.6"
+ process $proc$libresoc.v:185582$11997
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12186 $1\q_int$next[0:0]$12187
- attribute \src "libresoc.v:186639.5-186639.29"
+ assign $0\q_int$next[0:0]$11998 $1\q_int$next[0:0]$11999
+ attribute \src "libresoc.v:185583.5-185583.29"
switch \initial
- attribute \src "libresoc.v:186639.9-186639.17"
+ attribute \src "libresoc.v:185583.9-185583.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12187 1'0
+ assign $1\q_int$next[0:0]$11999 1'0
case
- assign $1\q_int$next[0:0]$12187 \$5
+ assign $1\q_int$next[0:0]$11999 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12186
+ update \q_int$next $0\q_int$next[0:0]$11998
end
- connect \$9 $and$libresoc.v:186628$12176_Y
- connect \$11 $or$libresoc.v:186629$12177_Y
- connect \$13 $not$libresoc.v:186630$12178_Y
- connect \$15 $or$libresoc.v:186631$12179_Y
- connect \$1 $not$libresoc.v:186632$12180_Y
- connect \$3 $and$libresoc.v:186633$12181_Y
- connect \$5 $or$libresoc.v:186634$12182_Y
- connect \$7 $not$libresoc.v:186635$12183_Y
+ connect \$9 $and$libresoc.v:185572$11988_Y
+ connect \$11 $or$libresoc.v:185573$11989_Y
+ connect \$13 $not$libresoc.v:185574$11990_Y
+ connect \$15 $or$libresoc.v:185575$11991_Y
+ connect \$1 $not$libresoc.v:185576$11992_Y
+ connect \$3 $and$libresoc.v:185577$11993_Y
+ connect \$5 $or$libresoc.v:185578$11994_Y
+ connect \$7 $not$libresoc.v:185579$11995_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186654.1-186712.10"
+attribute \src "libresoc.v:185598.1-185656.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l"
attribute \generator "nMigen"
module \rok_l$71
- attribute \src "libresoc.v:186655.7-186655.20"
+ attribute \src "libresoc.v:185599.7-185599.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186700.3-186708.6"
- wire $0\q_int$next[0:0]$12200
- attribute \src "libresoc.v:186698.3-186699.27"
+ attribute \src "libresoc.v:185644.3-185652.6"
+ wire $0\q_int$next[0:0]$12012
+ attribute \src "libresoc.v:185642.3-185643.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186700.3-186708.6"
- wire $1\q_int$next[0:0]$12201
- attribute \src "libresoc.v:186677.7-186677.19"
+ attribute \src "libresoc.v:185644.3-185652.6"
+ wire $1\q_int$next[0:0]$12013
+ attribute \src "libresoc.v:185621.7-185621.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186690.17-186690.96"
- wire $and$libresoc.v:186690$12190_Y
- attribute \src "libresoc.v:186695.17-186695.96"
- wire $and$libresoc.v:186695$12195_Y
- attribute \src "libresoc.v:186692.18-186692.94"
- wire $not$libresoc.v:186692$12192_Y
- attribute \src "libresoc.v:186694.17-186694.93"
- wire $not$libresoc.v:186694$12194_Y
- attribute \src "libresoc.v:186697.17-186697.93"
- wire $not$libresoc.v:186697$12197_Y
- attribute \src "libresoc.v:186691.18-186691.99"
- wire $or$libresoc.v:186691$12191_Y
- attribute \src "libresoc.v:186693.18-186693.100"
- wire $or$libresoc.v:186693$12193_Y
- attribute \src "libresoc.v:186696.17-186696.98"
- wire $or$libresoc.v:186696$12196_Y
+ attribute \src "libresoc.v:185634.17-185634.96"
+ wire $and$libresoc.v:185634$12002_Y
+ attribute \src "libresoc.v:185639.17-185639.96"
+ wire $and$libresoc.v:185639$12007_Y
+ attribute \src "libresoc.v:185636.18-185636.94"
+ wire $not$libresoc.v:185636$12004_Y
+ attribute \src "libresoc.v:185638.17-185638.93"
+ wire $not$libresoc.v:185638$12006_Y
+ attribute \src "libresoc.v:185641.17-185641.93"
+ wire $not$libresoc.v:185641$12009_Y
+ attribute \src "libresoc.v:185635.18-185635.99"
+ wire $or$libresoc.v:185635$12003_Y
+ attribute \src "libresoc.v:185637.18-185637.100"
+ wire $or$libresoc.v:185637$12005_Y
+ attribute \src "libresoc.v:185640.17-185640.98"
+ wire $or$libresoc.v:185640$12008_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186655.7-186655.15"
+ attribute \src "libresoc.v:185599.7-185599.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186690$12190
+ cell $and $and$libresoc.v:185634$12002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186690$12190_Y
+ connect \Y $and$libresoc.v:185634$12002_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186695$12195
+ cell $and $and$libresoc.v:185639$12007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186695$12195_Y
+ connect \Y $and$libresoc.v:185639$12007_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186692$12192
+ cell $not $not$libresoc.v:185636$12004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186692$12192_Y
+ connect \Y $not$libresoc.v:185636$12004_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186694$12194
+ cell $not $not$libresoc.v:185638$12006
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186694$12194_Y
+ connect \Y $not$libresoc.v:185638$12006_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186697$12197
+ cell $not $not$libresoc.v:185641$12009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186697$12197_Y
+ connect \Y $not$libresoc.v:185641$12009_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186691$12191
+ cell $or $or$libresoc.v:185635$12003
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186691$12191_Y
+ connect \Y $or$libresoc.v:185635$12003_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186693$12193
+ cell $or $or$libresoc.v:185637$12005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186693$12193_Y
+ connect \Y $or$libresoc.v:185637$12005_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186696$12196
+ cell $or $or$libresoc.v:185640$12008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186696$12196_Y
+ connect \Y $or$libresoc.v:185640$12008_Y
end
- attribute \src "libresoc.v:186655.7-186655.20"
- process $proc$libresoc.v:186655$12202
+ attribute \src "libresoc.v:185599.7-185599.20"
+ process $proc$libresoc.v:185599$12014
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186677.7-186677.19"
- process $proc$libresoc.v:186677$12203
+ attribute \src "libresoc.v:185621.7-185621.19"
+ process $proc$libresoc.v:185621$12015
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186698.3-186699.27"
- process $proc$libresoc.v:186698$12198
+ attribute \src "libresoc.v:185642.3-185643.27"
+ process $proc$libresoc.v:185642$12010
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186700.3-186708.6"
- process $proc$libresoc.v:186700$12199
+ attribute \src "libresoc.v:185644.3-185652.6"
+ process $proc$libresoc.v:185644$12011
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12200 $1\q_int$next[0:0]$12201
- attribute \src "libresoc.v:186701.5-186701.29"
+ assign $0\q_int$next[0:0]$12012 $1\q_int$next[0:0]$12013
+ attribute \src "libresoc.v:185645.5-185645.29"
switch \initial
- attribute \src "libresoc.v:186701.9-186701.17"
+ attribute \src "libresoc.v:185645.9-185645.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12201 1'0
+ assign $1\q_int$next[0:0]$12013 1'0
case
- assign $1\q_int$next[0:0]$12201 \$5
+ assign $1\q_int$next[0:0]$12013 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12200
+ update \q_int$next $0\q_int$next[0:0]$12012
end
- connect \$9 $and$libresoc.v:186690$12190_Y
- connect \$11 $or$libresoc.v:186691$12191_Y
- connect \$13 $not$libresoc.v:186692$12192_Y
- connect \$15 $or$libresoc.v:186693$12193_Y
- connect \$1 $not$libresoc.v:186694$12194_Y
- connect \$3 $and$libresoc.v:186695$12195_Y
- connect \$5 $or$libresoc.v:186696$12196_Y
- connect \$7 $not$libresoc.v:186697$12197_Y
+ connect \$9 $and$libresoc.v:185634$12002_Y
+ connect \$11 $or$libresoc.v:185635$12003_Y
+ connect \$13 $not$libresoc.v:185636$12004_Y
+ connect \$15 $or$libresoc.v:185637$12005_Y
+ connect \$1 $not$libresoc.v:185638$12006_Y
+ connect \$3 $and$libresoc.v:185639$12007_Y
+ connect \$5 $or$libresoc.v:185640$12008_Y
+ connect \$7 $not$libresoc.v:185641$12009_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186716.1-186774.10"
+attribute \src "libresoc.v:185660.1-185718.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l"
attribute \generator "nMigen"
module \rok_l$88
- attribute \src "libresoc.v:186717.7-186717.20"
+ attribute \src "libresoc.v:185661.7-185661.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186762.3-186770.6"
- wire $0\q_int$next[0:0]$12214
- attribute \src "libresoc.v:186760.3-186761.27"
+ attribute \src "libresoc.v:185706.3-185714.6"
+ wire $0\q_int$next[0:0]$12026
+ attribute \src "libresoc.v:185704.3-185705.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:186762.3-186770.6"
- wire $1\q_int$next[0:0]$12215
- attribute \src "libresoc.v:186739.7-186739.19"
+ attribute \src "libresoc.v:185706.3-185714.6"
+ wire $1\q_int$next[0:0]$12027
+ attribute \src "libresoc.v:185683.7-185683.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:186752.17-186752.96"
- wire $and$libresoc.v:186752$12204_Y
- attribute \src "libresoc.v:186757.17-186757.96"
- wire $and$libresoc.v:186757$12209_Y
- attribute \src "libresoc.v:186754.18-186754.94"
- wire $not$libresoc.v:186754$12206_Y
- attribute \src "libresoc.v:186756.17-186756.93"
- wire $not$libresoc.v:186756$12208_Y
- attribute \src "libresoc.v:186759.17-186759.93"
- wire $not$libresoc.v:186759$12211_Y
- attribute \src "libresoc.v:186753.18-186753.99"
- wire $or$libresoc.v:186753$12205_Y
- attribute \src "libresoc.v:186755.18-186755.100"
- wire $or$libresoc.v:186755$12207_Y
- attribute \src "libresoc.v:186758.17-186758.98"
- wire $or$libresoc.v:186758$12210_Y
+ attribute \src "libresoc.v:185696.17-185696.96"
+ wire $and$libresoc.v:185696$12016_Y
+ attribute \src "libresoc.v:185701.17-185701.96"
+ wire $and$libresoc.v:185701$12021_Y
+ attribute \src "libresoc.v:185698.18-185698.94"
+ wire $not$libresoc.v:185698$12018_Y
+ attribute \src "libresoc.v:185700.17-185700.93"
+ wire $not$libresoc.v:185700$12020_Y
+ attribute \src "libresoc.v:185703.17-185703.93"
+ wire $not$libresoc.v:185703$12023_Y
+ attribute \src "libresoc.v:185697.18-185697.99"
+ wire $or$libresoc.v:185697$12017_Y
+ attribute \src "libresoc.v:185699.18-185699.100"
+ wire $or$libresoc.v:185699$12019_Y
+ attribute \src "libresoc.v:185702.17-185702.98"
+ wire $or$libresoc.v:185702$12022_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:186717.7-186717.15"
+ attribute \src "libresoc.v:185661.7-185661.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:186752$12204
+ cell $and $and$libresoc.v:185696$12016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:186752$12204_Y
+ connect \Y $and$libresoc.v:185696$12016_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:186757$12209
+ cell $and $and$libresoc.v:185701$12021
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:186757$12209_Y
+ connect \Y $and$libresoc.v:185701$12021_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:186754$12206
+ cell $not $not$libresoc.v:185698$12018
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:186754$12206_Y
+ connect \Y $not$libresoc.v:185698$12018_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:186756$12208
+ cell $not $not$libresoc.v:185700$12020
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186756$12208_Y
+ connect \Y $not$libresoc.v:185700$12020_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:186759$12211
+ cell $not $not$libresoc.v:185703$12023
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:186759$12211_Y
+ connect \Y $not$libresoc.v:185703$12023_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:186753$12205
+ cell $or $or$libresoc.v:185697$12017
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:186753$12205_Y
+ connect \Y $or$libresoc.v:185697$12017_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:186755$12207
+ cell $or $or$libresoc.v:185699$12019
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:186755$12207_Y
+ connect \Y $or$libresoc.v:185699$12019_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:186758$12210
+ cell $or $or$libresoc.v:185702$12022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:186758$12210_Y
+ connect \Y $or$libresoc.v:185702$12022_Y
end
- attribute \src "libresoc.v:186717.7-186717.20"
- process $proc$libresoc.v:186717$12216
+ attribute \src "libresoc.v:185661.7-185661.20"
+ process $proc$libresoc.v:185661$12028
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186739.7-186739.19"
- process $proc$libresoc.v:186739$12217
+ attribute \src "libresoc.v:185683.7-185683.19"
+ process $proc$libresoc.v:185683$12029
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:186760.3-186761.27"
- process $proc$libresoc.v:186760$12212
+ attribute \src "libresoc.v:185704.3-185705.27"
+ process $proc$libresoc.v:185704$12024
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:186762.3-186770.6"
- process $proc$libresoc.v:186762$12213
+ attribute \src "libresoc.v:185706.3-185714.6"
+ process $proc$libresoc.v:185706$12025
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12214 $1\q_int$next[0:0]$12215
- attribute \src "libresoc.v:186763.5-186763.29"
+ assign $0\q_int$next[0:0]$12026 $1\q_int$next[0:0]$12027
+ attribute \src "libresoc.v:185707.5-185707.29"
switch \initial
- attribute \src "libresoc.v:186763.9-186763.17"
+ attribute \src "libresoc.v:185707.9-185707.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12215 1'0
+ assign $1\q_int$next[0:0]$12027 1'0
case
- assign $1\q_int$next[0:0]$12215 \$5
+ assign $1\q_int$next[0:0]$12027 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12214
+ update \q_int$next $0\q_int$next[0:0]$12026
end
- connect \$9 $and$libresoc.v:186752$12204_Y
- connect \$11 $or$libresoc.v:186753$12205_Y
- connect \$13 $not$libresoc.v:186754$12206_Y
- connect \$15 $or$libresoc.v:186755$12207_Y
- connect \$1 $not$libresoc.v:186756$12208_Y
- connect \$3 $and$libresoc.v:186757$12209_Y
- connect \$5 $or$libresoc.v:186758$12210_Y
- connect \$7 $not$libresoc.v:186759$12211_Y
+ connect \$9 $and$libresoc.v:185696$12016_Y
+ connect \$11 $or$libresoc.v:185697$12017_Y
+ connect \$13 $not$libresoc.v:185698$12018_Y
+ connect \$15 $or$libresoc.v:185699$12019_Y
+ connect \$1 $not$libresoc.v:185700$12020_Y
+ connect \$3 $and$libresoc.v:185701$12021_Y
+ connect \$5 $or$libresoc.v:185702$12022_Y
+ connect \$7 $not$libresoc.v:185703$12023_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:186778.1-187138.10"
+attribute \src "libresoc.v:185722.1-186082.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator"
attribute \generator "nMigen"
module \rotator
- attribute \src "libresoc.v:187047.3-187065.6"
+ attribute \src "libresoc.v:185991.3-186009.6"
wire $0\carry_out_o[0:0]
- attribute \src "libresoc.v:186979.3-186993.6"
+ attribute \src "libresoc.v:185923.3-185937.6"
wire width 32 $0\hi32[31:0]
- attribute \src "libresoc.v:186779.7-186779.20"
+ attribute \src "libresoc.v:185723.7-185723.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187078.3-187111.6"
- wire width 7 $0\mb$8[6:0]$12265
- attribute \src "libresoc.v:187112.3-187126.6"
- wire width 7 $0\me$13[6:0]$12270
- attribute \src "libresoc.v:187004.3-187015.6"
+ attribute \src "libresoc.v:186022.3-186055.6"
+ wire width 7 $0\mb$8[6:0]$12077
+ attribute \src "libresoc.v:186056.3-186070.6"
+ wire width 7 $0\me$13[6:0]$12082
+ attribute \src "libresoc.v:185948.3-185959.6"
wire width 64 $0\mr[63:0]
- attribute \src "libresoc.v:187016.3-187027.6"
+ attribute \src "libresoc.v:185960.3-185971.6"
wire width 2 $0\output_mode[1:0]
- attribute \src "libresoc.v:187028.3-187046.6"
+ attribute \src "libresoc.v:185972.3-185990.6"
wire width 64 $0\result_o[63:0]
- attribute \src "libresoc.v:186994.3-187003.6"
+ attribute \src "libresoc.v:185938.3-185947.6"
wire width 7 $0\right_mask_shift[6:0]
- attribute \src "libresoc.v:187066.3-187077.6"
+ attribute \src "libresoc.v:186010.3-186021.6"
wire width 6 $0\rot_count[5:0]
- attribute \src "libresoc.v:187047.3-187065.6"
+ attribute \src "libresoc.v:185991.3-186009.6"
wire $1\carry_out_o[0:0]
- attribute \src "libresoc.v:186979.3-186993.6"
+ attribute \src "libresoc.v:185923.3-185937.6"
wire width 32 $1\hi32[31:0]
- attribute \src "libresoc.v:187078.3-187111.6"
- wire width 7 $1\mb$8[6:0]$12266
- attribute \src "libresoc.v:187112.3-187126.6"
- wire width 7 $1\me$13[6:0]$12271
- attribute \src "libresoc.v:187004.3-187015.6"
+ attribute \src "libresoc.v:186022.3-186055.6"
+ wire width 7 $1\mb$8[6:0]$12078
+ attribute \src "libresoc.v:186056.3-186070.6"
+ wire width 7 $1\me$13[6:0]$12083
+ attribute \src "libresoc.v:185948.3-185959.6"
wire width 64 $1\mr[63:0]
- attribute \src "libresoc.v:187016.3-187027.6"
+ attribute \src "libresoc.v:185960.3-185971.6"
wire width 2 $1\output_mode[1:0]
- attribute \src "libresoc.v:187028.3-187046.6"
+ attribute \src "libresoc.v:185972.3-185990.6"
wire width 64 $1\result_o[63:0]
- attribute \src "libresoc.v:186994.3-187003.6"
+ attribute \src "libresoc.v:185938.3-185947.6"
wire width 7 $1\right_mask_shift[6:0]
- attribute \src "libresoc.v:187066.3-187077.6"
+ attribute \src "libresoc.v:186010.3-186021.6"
wire width 6 $1\rot_count[5:0]
- attribute \src "libresoc.v:187078.3-187111.6"
- wire width 2 $2\mb$8[6:5]$12267
- attribute \src "libresoc.v:187078.3-187111.6"
- wire width 2 $3\mb$8[6:5]$12268
- attribute \src "libresoc.v:186930.18-186930.118"
- wire $and$libresoc.v:186930$12221_Y
- attribute \src "libresoc.v:186932.18-186932.114"
- wire $and$libresoc.v:186932$12223_Y
- attribute \src "libresoc.v:186941.18-186941.113"
- wire $and$libresoc.v:186941$12232_Y
- attribute \src "libresoc.v:186943.18-186943.114"
- wire $and$libresoc.v:186943$12234_Y
- attribute \src "libresoc.v:186945.18-186945.114"
- wire $and$libresoc.v:186945$12236_Y
- attribute \src "libresoc.v:186946.18-186946.103"
- wire width 64 $and$libresoc.v:186946$12237_Y
- attribute \src "libresoc.v:186947.18-186947.106"
- wire width 64 $and$libresoc.v:186947$12238_Y
- attribute \src "libresoc.v:186949.18-186949.103"
- wire width 64 $and$libresoc.v:186949$12240_Y
- attribute \src "libresoc.v:186951.18-186951.105"
- wire width 64 $and$libresoc.v:186951$12242_Y
- attribute \src "libresoc.v:186954.18-186954.106"
- wire width 64 $and$libresoc.v:186954$12245_Y
- attribute \src "libresoc.v:186957.18-186957.105"
- wire width 64 $and$libresoc.v:186957$12248_Y
- attribute \src "libresoc.v:186959.17-186959.109"
- wire $and$libresoc.v:186959$12250_Y
- attribute \src "libresoc.v:186960.18-186960.104"
- wire width 64 $and$libresoc.v:186960$12251_Y
- attribute \src "libresoc.v:186964.18-186964.105"
- wire width 64 $and$libresoc.v:186964$12255_Y
- attribute \src "libresoc.v:186928.17-186928.98"
- wire width 7 $extend$libresoc.v:186928$12218_Y
- attribute \src "libresoc.v:186944.18-186944.122"
- wire $gt$libresoc.v:186944$12235_Y
- attribute \src "libresoc.v:186934.18-186934.111"
- wire $le$libresoc.v:186934$12225_Y
- attribute \src "libresoc.v:186936.18-186936.111"
- wire $le$libresoc.v:186936$12227_Y
- attribute \src "libresoc.v:186937.17-186937.117"
- wire width 7 signed $neg$libresoc.v:186937$12228_Y
- attribute \src "libresoc.v:186929.18-186929.103"
- wire $not$libresoc.v:186929$12220_Y
- attribute \src "libresoc.v:186931.18-186931.108"
- wire $not$libresoc.v:186931$12222_Y
- attribute \src "libresoc.v:186933.18-186933.105"
- wire width 6 $not$libresoc.v:186933$12224_Y
- attribute \src "libresoc.v:186939.18-186939.112"
- wire width 64 $not$libresoc.v:186939$12230_Y
- attribute \src "libresoc.v:186940.18-186940.109"
- wire $not$libresoc.v:186940$12231_Y
- attribute \src "libresoc.v:186948.17-186948.105"
- wire $not$libresoc.v:186948$12239_Y
- attribute \src "libresoc.v:186950.18-186950.102"
- wire width 64 $not$libresoc.v:186950$12241_Y
- attribute \src "libresoc.v:186956.18-186956.102"
- wire width 64 $not$libresoc.v:186956$12247_Y
- attribute \src "libresoc.v:186961.18-186961.100"
- wire width 64 $not$libresoc.v:186961$12252_Y
- attribute \src "libresoc.v:186963.18-186963.100"
- wire width 64 $not$libresoc.v:186963$12254_Y
- attribute \src "libresoc.v:186942.18-186942.115"
- wire $or$libresoc.v:186942$12233_Y
- attribute \src "libresoc.v:186952.18-186952.108"
- wire width 64 $or$libresoc.v:186952$12243_Y
- attribute \src "libresoc.v:186953.18-186953.103"
- wire width 64 $or$libresoc.v:186953$12244_Y
- attribute \src "libresoc.v:186955.18-186955.103"
- wire width 64 $or$libresoc.v:186955$12246_Y
- attribute \src "libresoc.v:186958.18-186958.108"
- wire width 64 $or$libresoc.v:186958$12249_Y
- attribute \src "libresoc.v:186962.18-186962.106"
- wire width 64 $or$libresoc.v:186962$12253_Y
- attribute \src "libresoc.v:186928.17-186928.98"
- wire width 7 $pos$libresoc.v:186928$12219_Y
- attribute \src "libresoc.v:186965.18-186965.102"
- wire $reduce_or$libresoc.v:186965$12256_Y
- attribute \src "libresoc.v:186935.18-186935.109"
- wire width 8 $sub$libresoc.v:186935$12226_Y
- attribute \src "libresoc.v:186938.18-186938.110"
- wire width 8 $sub$libresoc.v:186938$12229_Y
+ attribute \src "libresoc.v:186022.3-186055.6"
+ wire width 2 $2\mb$8[6:5]$12079
+ attribute \src "libresoc.v:186022.3-186055.6"
+ wire width 2 $3\mb$8[6:5]$12080
+ attribute \src "libresoc.v:185874.18-185874.118"
+ wire $and$libresoc.v:185874$12033_Y
+ attribute \src "libresoc.v:185876.18-185876.114"
+ wire $and$libresoc.v:185876$12035_Y
+ attribute \src "libresoc.v:185885.18-185885.113"
+ wire $and$libresoc.v:185885$12044_Y
+ attribute \src "libresoc.v:185887.18-185887.114"
+ wire $and$libresoc.v:185887$12046_Y
+ attribute \src "libresoc.v:185889.18-185889.114"
+ wire $and$libresoc.v:185889$12048_Y
+ attribute \src "libresoc.v:185890.18-185890.103"
+ wire width 64 $and$libresoc.v:185890$12049_Y
+ attribute \src "libresoc.v:185891.18-185891.106"
+ wire width 64 $and$libresoc.v:185891$12050_Y
+ attribute \src "libresoc.v:185893.18-185893.103"
+ wire width 64 $and$libresoc.v:185893$12052_Y
+ attribute \src "libresoc.v:185895.18-185895.105"
+ wire width 64 $and$libresoc.v:185895$12054_Y
+ attribute \src "libresoc.v:185898.18-185898.106"
+ wire width 64 $and$libresoc.v:185898$12057_Y
+ attribute \src "libresoc.v:185901.18-185901.105"
+ wire width 64 $and$libresoc.v:185901$12060_Y
+ attribute \src "libresoc.v:185903.17-185903.109"
+ wire $and$libresoc.v:185903$12062_Y
+ attribute \src "libresoc.v:185904.18-185904.104"
+ wire width 64 $and$libresoc.v:185904$12063_Y
+ attribute \src "libresoc.v:185908.18-185908.105"
+ wire width 64 $and$libresoc.v:185908$12067_Y
+ attribute \src "libresoc.v:185872.17-185872.98"
+ wire width 7 $extend$libresoc.v:185872$12030_Y
+ attribute \src "libresoc.v:185888.18-185888.122"
+ wire $gt$libresoc.v:185888$12047_Y
+ attribute \src "libresoc.v:185878.18-185878.111"
+ wire $le$libresoc.v:185878$12037_Y
+ attribute \src "libresoc.v:185880.18-185880.111"
+ wire $le$libresoc.v:185880$12039_Y
+ attribute \src "libresoc.v:185881.17-185881.117"
+ wire width 7 signed $neg$libresoc.v:185881$12040_Y
+ attribute \src "libresoc.v:185873.18-185873.103"
+ wire $not$libresoc.v:185873$12032_Y
+ attribute \src "libresoc.v:185875.18-185875.108"
+ wire $not$libresoc.v:185875$12034_Y
+ attribute \src "libresoc.v:185877.18-185877.105"
+ wire width 6 $not$libresoc.v:185877$12036_Y
+ attribute \src "libresoc.v:185883.18-185883.112"
+ wire width 64 $not$libresoc.v:185883$12042_Y
+ attribute \src "libresoc.v:185884.18-185884.109"
+ wire $not$libresoc.v:185884$12043_Y
+ attribute \src "libresoc.v:185892.17-185892.105"
+ wire $not$libresoc.v:185892$12051_Y
+ attribute \src "libresoc.v:185894.18-185894.102"
+ wire width 64 $not$libresoc.v:185894$12053_Y
+ attribute \src "libresoc.v:185900.18-185900.102"
+ wire width 64 $not$libresoc.v:185900$12059_Y
+ attribute \src "libresoc.v:185905.18-185905.100"
+ wire width 64 $not$libresoc.v:185905$12064_Y
+ attribute \src "libresoc.v:185907.18-185907.100"
+ wire width 64 $not$libresoc.v:185907$12066_Y
+ attribute \src "libresoc.v:185886.18-185886.115"
+ wire $or$libresoc.v:185886$12045_Y
+ attribute \src "libresoc.v:185896.18-185896.108"
+ wire width 64 $or$libresoc.v:185896$12055_Y
+ attribute \src "libresoc.v:185897.18-185897.103"
+ wire width 64 $or$libresoc.v:185897$12056_Y
+ attribute \src "libresoc.v:185899.18-185899.103"
+ wire width 64 $or$libresoc.v:185899$12058_Y
+ attribute \src "libresoc.v:185902.18-185902.108"
+ wire width 64 $or$libresoc.v:185902$12061_Y
+ attribute \src "libresoc.v:185906.18-185906.106"
+ wire width 64 $or$libresoc.v:185906$12065_Y
+ attribute \src "libresoc.v:185872.17-185872.98"
+ wire width 7 $pos$libresoc.v:185872$12031_Y
+ attribute \src "libresoc.v:185909.18-185909.102"
+ wire $reduce_or$libresoc.v:185909$12068_Y
+ attribute \src "libresoc.v:185879.18-185879.109"
+ wire width 8 $sub$libresoc.v:185879$12038_Y
+ attribute \src "libresoc.v:185882.18-185882.110"
+ wire width 8 $sub$libresoc.v:185882$12041_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99"
wire width 7 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
wire input 10 \clear_right
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81"
wire width 32 \hi32
- attribute \src "libresoc.v:186779.7-186779.15"
+ attribute \src "libresoc.v:185723.7-185723.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
wire input 6 \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
wire input 11 \sign_ext_rs
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
- cell $and $and$libresoc.v:186930$12221
+ cell $and $and$libresoc.v:185874$12033
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \is_32bit
- connect \Y $and$libresoc.v:186930$12221_Y
+ connect \Y $and$libresoc.v:185874$12033_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
- cell $and $and$libresoc.v:186932$12223
+ cell $and $and$libresoc.v:185876$12035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \$16
- connect \Y $and$libresoc.v:186932$12223_Y
+ connect \Y $and$libresoc.v:185876$12035_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $and $and$libresoc.v:186941$12232
+ cell $and $and$libresoc.v:185885$12044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_left
connect \B \$34
- connect \Y $and$libresoc.v:186941$12232_Y
+ connect \Y $and$libresoc.v:185885$12044_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
- cell $and $and$libresoc.v:186943$12234
+ cell $and $and$libresoc.v:185887$12046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \arith
connect \B \repl32 [63]
- connect \Y $and$libresoc.v:186943$12234_Y
+ connect \Y $and$libresoc.v:185887$12046_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
- cell $and $and$libresoc.v:186945$12236
+ cell $and $and$libresoc.v:185889$12048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \$42
- connect \Y $and$libresoc.v:186945$12236_Y
+ connect \Y $and$libresoc.v:185889$12048_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:186946$12237
+ cell $and $and$libresoc.v:185890$12049
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $and$libresoc.v:186946$12237_Y
+ connect \Y $and$libresoc.v:185890$12049_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:186947$12238
+ cell $and $and$libresoc.v:185891$12050
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$46
- connect \Y $and$libresoc.v:186947$12238_Y
+ connect \Y $and$libresoc.v:185891$12050_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:186949$12240
+ cell $and $and$libresoc.v:185893$12052
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $and$libresoc.v:186949$12240_Y
+ connect \Y $and$libresoc.v:185893$12052_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:186951$12242
+ cell $and $and$libresoc.v:185895$12054
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \$50
- connect \Y $and$libresoc.v:186951$12242_Y
+ connect \Y $and$libresoc.v:185895$12054_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $and $and$libresoc.v:186954$12245
+ cell $and $and$libresoc.v:185898$12057
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$58
- connect \Y $and$libresoc.v:186954$12245_Y
+ connect \Y $and$libresoc.v:185898$12057_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $and $and$libresoc.v:186957$12248
+ cell $and $and$libresoc.v:185901$12060
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \$62
- connect \Y $and$libresoc.v:186957$12248_Y
+ connect \Y $and$libresoc.v:185901$12060_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- cell $and $and$libresoc.v:186959$12250
+ cell $and $and$libresoc.v:185903$12062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift [6]
connect \B \$4
- connect \Y $and$libresoc.v:186959$12250_Y
+ connect \Y $and$libresoc.v:185903$12062_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174"
- cell $and $and$libresoc.v:186960$12251
+ cell $and $and$libresoc.v:185904$12063
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \mr
- connect \Y $and$libresoc.v:186960$12251_Y
+ connect \Y $and$libresoc.v:185904$12063_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $and $and$libresoc.v:186964$12255
+ cell $and $and$libresoc.v:185908$12067
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rs
connect \B \$77
- connect \Y $and$libresoc.v:186964$12255_Y
+ connect \Y $and$libresoc.v:185908$12067_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- cell $pos $extend$libresoc.v:186928$12218
+ cell $pos $extend$libresoc.v:185872$12030
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \mb
- connect \Y $extend$libresoc.v:186928$12218_Y
+ connect \Y $extend$libresoc.v:185872$12030_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
- cell $gt $gt$libresoc.v:186944$12235
+ cell $gt $gt$libresoc.v:185888$12047
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8 [5:0]
connect \B \me$13 [5:0]
- connect \Y $gt$libresoc.v:186944$12235_Y
+ connect \Y $gt$libresoc.v:185888$12047_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- cell $le $le$libresoc.v:186934$12225
+ cell $le $le$libresoc.v:185878$12037
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8
connect \B 7'1000000
- connect \Y $le$libresoc.v:186934$12225_Y
+ connect \Y $le$libresoc.v:185878$12037_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- cell $le $le$libresoc.v:186936$12227
+ cell $le $le$libresoc.v:185880$12039
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8
connect \B 7'1000000
- connect \Y $le$libresoc.v:186936$12227_Y
+ connect \Y $le$libresoc.v:185880$12039_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99"
- cell $neg $neg$libresoc.v:186937$12228
+ cell $neg $neg$libresoc.v:185881$12040
parameter \A_SIGNED 1
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
connect \A { \shift_signed [5] \shift_signed }
- connect \Y $neg$libresoc.v:186937$12228_Y
+ connect \Y $neg$libresoc.v:185881$12040_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- cell $not $not$libresoc.v:186929$12220
+ cell $not $not$libresoc.v:185873$12032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sh [5]
- connect \Y $not$libresoc.v:186929$12220_Y
+ connect \Y $not$libresoc.v:185873$12032_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
- cell $not $not$libresoc.v:186931$12222
+ cell $not $not$libresoc.v:185875$12034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \clear_left
- connect \Y $not$libresoc.v:186931$12222_Y
+ connect \Y $not$libresoc.v:185875$12034_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139"
- cell $not $not$libresoc.v:186933$12224
+ cell $not $not$libresoc.v:185877$12036
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \sh [5:0]
- connect \Y $not$libresoc.v:186933$12224_Y
+ connect \Y $not$libresoc.v:185877$12036_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
- cell $not $not$libresoc.v:186939$12230
+ cell $not $not$libresoc.v:185883$12042
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \left_mask_mask
- connect \Y $not$libresoc.v:186939$12230_Y
+ connect \Y $not$libresoc.v:185883$12042_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $not $not$libresoc.v:186940$12231
+ cell $not $not$libresoc.v:185884$12043
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \clear_right
- connect \Y $not$libresoc.v:186940$12231_Y
+ connect \Y $not$libresoc.v:185884$12043_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- cell $not $not$libresoc.v:186948$12239
+ cell $not $not$libresoc.v:185892$12051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_32bit
- connect \Y $not$libresoc.v:186948$12239_Y
+ connect \Y $not$libresoc.v:185892$12051_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $not $not$libresoc.v:186950$12241
+ cell $not $not$libresoc.v:185894$12053
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \$51
- connect \Y $not$libresoc.v:186950$12241_Y
+ connect \Y $not$libresoc.v:185894$12053_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $not $not$libresoc.v:186956$12247
+ cell $not $not$libresoc.v:185900$12059
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \$63
- connect \Y $not$libresoc.v:186956$12247_Y
+ connect \Y $not$libresoc.v:185900$12059_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176"
- cell $not $not$libresoc.v:186961$12252
+ cell $not $not$libresoc.v:185905$12064
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \mr
- connect \Y $not$libresoc.v:186961$12252_Y
+ connect \Y $not$libresoc.v:185905$12064_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $not $not$libresoc.v:186963$12254
+ cell $not $not$libresoc.v:185907$12066
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ml
- connect \Y $not$libresoc.v:186963$12254_Y
+ connect \Y $not$libresoc.v:185907$12066_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $or $or$libresoc.v:186942$12233
+ cell $or $or$libresoc.v:185886$12045
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \right_shift
- connect \Y $or$libresoc.v:186942$12233_Y
+ connect \Y $or$libresoc.v:185886$12045_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $or $or$libresoc.v:186952$12243
+ cell $or $or$libresoc.v:185896$12055
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \$48
connect \B \$54
- connect \Y $or$libresoc.v:186952$12243_Y
+ connect \Y $or$libresoc.v:185896$12055_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:186953$12244
+ cell $or $or$libresoc.v:185897$12056
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $or$libresoc.v:186953$12244_Y
+ connect \Y $or$libresoc.v:185897$12056_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:186955$12246
+ cell $or $or$libresoc.v:185899$12058
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $or$libresoc.v:186955$12246_Y
+ connect \Y $or$libresoc.v:185899$12058_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:186958$12249
+ cell $or $or$libresoc.v:185902$12061
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \$60
connect \B \$66
- connect \Y $or$libresoc.v:186958$12249_Y
+ connect \Y $or$libresoc.v:185902$12061_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176"
- cell $or $or$libresoc.v:186962$12253
+ cell $or $or$libresoc.v:185906$12065
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$72
- connect \Y $or$libresoc.v:186962$12253_Y
+ connect \Y $or$libresoc.v:185906$12065_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- cell $pos $pos$libresoc.v:186928$12219
+ cell $pos $pos$libresoc.v:185872$12031
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:186928$12218_Y
- connect \Y $pos$libresoc.v:186928$12219_Y
+ connect \A $extend$libresoc.v:185872$12030_Y
+ connect \Y $pos$libresoc.v:185872$12031_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $reduce_or $reduce_or$libresoc.v:186965$12256
+ cell $reduce_or $reduce_or$libresoc.v:185909$12068
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \$79
- connect \Y $reduce_or$libresoc.v:186965$12256_Y
+ connect \Y $reduce_or$libresoc.v:185909$12068_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
- cell $sub $sub$libresoc.v:186935$12226
+ cell $sub $sub$libresoc.v:185879$12038
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 7'1000000
connect \B \mb$8
- connect \Y $sub$libresoc.v:186935$12226_Y
+ connect \Y $sub$libresoc.v:185879$12038_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $sub $sub$libresoc.v:186938$12229
+ cell $sub $sub$libresoc.v:185882$12041
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 6'111111
connect \B \me$13
- connect \Y $sub$libresoc.v:186938$12229_Y
+ connect \Y $sub$libresoc.v:185882$12041_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186966.13-186969.4"
+ attribute \src "libresoc.v:185910.13-185913.4"
cell \left_mask \left_mask
connect \mask \left_mask_mask
connect \shift \left_mask_shift
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186970.14-186973.4"
+ attribute \src "libresoc.v:185914.14-185917.4"
cell \right_mask \right_mask
connect \mask \right_mask_mask
connect \shift \right_mask_shift
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186974.8-186978.4"
+ attribute \src "libresoc.v:185918.8-185922.4"
cell \rotl \rotl
connect \a \rotl_a
connect \b \rotl_b
connect \o \rotl_o
end
- attribute \src "libresoc.v:186779.7-186779.20"
- process $proc$libresoc.v:186779$12272
+ attribute \src "libresoc.v:185723.7-185723.20"
+ process $proc$libresoc.v:185723$12084
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186979.3-186993.6"
- process $proc$libresoc.v:186979$12257
+ attribute \src "libresoc.v:185923.3-185937.6"
+ process $proc$libresoc.v:185923$12069
assign { } { }
assign $0\hi32[31:0] $1\hi32[31:0]
- attribute \src "libresoc.v:186980.5-186980.29"
+ attribute \src "libresoc.v:185924.5-185924.29"
switch \initial
- attribute \src "libresoc.v:186980.9-186980.17"
+ attribute \src "libresoc.v:185924.9-185924.17"
case 1'1
case
end
sync always
update \hi32 $0\hi32[31:0]
end
- attribute \src "libresoc.v:186994.3-187003.6"
- process $proc$libresoc.v:186994$12258
+ attribute \src "libresoc.v:185938.3-185947.6"
+ process $proc$libresoc.v:185938$12070
assign { } { }
assign { } { }
assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0]
- attribute \src "libresoc.v:186995.5-186995.29"
+ attribute \src "libresoc.v:185939.5-185939.29"
switch \initial
- attribute \src "libresoc.v:186995.9-186995.17"
+ attribute \src "libresoc.v:185939.9-185939.17"
case 1'1
case
end
sync always
update \right_mask_shift $0\right_mask_shift[6:0]
end
- attribute \src "libresoc.v:187004.3-187015.6"
- process $proc$libresoc.v:187004$12259
+ attribute \src "libresoc.v:185948.3-185959.6"
+ process $proc$libresoc.v:185948$12071
assign { } { }
assign $0\mr[63:0] $1\mr[63:0]
- attribute \src "libresoc.v:187005.5-187005.29"
+ attribute \src "libresoc.v:185949.5-185949.29"
switch \initial
- attribute \src "libresoc.v:187005.9-187005.17"
+ attribute \src "libresoc.v:185949.9-185949.17"
case 1'1
case
end
sync always
update \mr $0\mr[63:0]
end
- attribute \src "libresoc.v:187016.3-187027.6"
- process $proc$libresoc.v:187016$12260
+ attribute \src "libresoc.v:185960.3-185971.6"
+ process $proc$libresoc.v:185960$12072
assign { } { }
assign $0\output_mode[1:0] $1\output_mode[1:0]
- attribute \src "libresoc.v:187017.5-187017.29"
+ attribute \src "libresoc.v:185961.5-185961.29"
switch \initial
- attribute \src "libresoc.v:187017.9-187017.17"
+ attribute \src "libresoc.v:185961.9-185961.17"
case 1'1
case
end
sync always
update \output_mode $0\output_mode[1:0]
end
- attribute \src "libresoc.v:187028.3-187046.6"
- process $proc$libresoc.v:187028$12261
+ attribute \src "libresoc.v:185972.3-185990.6"
+ process $proc$libresoc.v:185972$12073
assign { } { }
assign { } { }
assign $0\result_o[63:0] $1\result_o[63:0]
- attribute \src "libresoc.v:187029.5-187029.29"
+ attribute \src "libresoc.v:185973.5-185973.29"
switch \initial
- attribute \src "libresoc.v:187029.9-187029.17"
+ attribute \src "libresoc.v:185973.9-185973.17"
case 1'1
case
end
sync always
update \result_o $0\result_o[63:0]
end
- attribute \src "libresoc.v:187047.3-187065.6"
- process $proc$libresoc.v:187047$12262
+ attribute \src "libresoc.v:185991.3-186009.6"
+ process $proc$libresoc.v:185991$12074
assign { } { }
assign { } { }
assign $0\carry_out_o[0:0] $1\carry_out_o[0:0]
- attribute \src "libresoc.v:187048.5-187048.29"
+ attribute \src "libresoc.v:185992.5-185992.29"
switch \initial
- attribute \src "libresoc.v:187048.9-187048.17"
+ attribute \src "libresoc.v:185992.9-185992.17"
case 1'1
case
end
sync always
update \carry_out_o $0\carry_out_o[0:0]
end
- attribute \src "libresoc.v:187066.3-187077.6"
- process $proc$libresoc.v:187066$12263
+ attribute \src "libresoc.v:186010.3-186021.6"
+ process $proc$libresoc.v:186010$12075
assign { } { }
assign $0\rot_count[5:0] $1\rot_count[5:0]
- attribute \src "libresoc.v:187067.5-187067.29"
+ attribute \src "libresoc.v:186011.5-186011.29"
switch \initial
- attribute \src "libresoc.v:187067.9-187067.17"
+ attribute \src "libresoc.v:186011.9-186011.17"
case 1'1
case
end
sync always
update \rot_count $0\rot_count[5:0]
end
- attribute \src "libresoc.v:187078.3-187111.6"
- process $proc$libresoc.v:187078$12264
+ attribute \src "libresoc.v:186022.3-186055.6"
+ process $proc$libresoc.v:186022$12076
assign { } { }
- assign $0\mb$8[6:0]$12265 $1\mb$8[6:0]$12266
- attribute \src "libresoc.v:187079.5-187079.29"
+ assign $0\mb$8[6:0]$12077 $1\mb$8[6:0]$12078
+ attribute \src "libresoc.v:186023.5-186023.29"
switch \initial
- attribute \src "libresoc.v:187079.9-187079.17"
+ attribute \src "libresoc.v:186023.9-186023.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\mb$8[6:0]$12266 [4:0] \$9 [4:0]
- assign $1\mb$8[6:0]$12266 [6:5] $2\mb$8[6:5]$12267
+ assign $1\mb$8[6:0]$12078 [4:0] \$9 [4:0]
+ assign $1\mb$8[6:0]$12078 [6:5] $2\mb$8[6:5]$12079
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
switch \is_32bit
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\mb$8[6:5]$12267 2'01
+ assign $2\mb$8[6:5]$12079 2'01
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\mb$8[6:5]$12267 { 1'0 \mb_extra }
+ assign $2\mb$8[6:5]$12079 { 1'0 \mb_extra }
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\mb$8[6:0]$12266 [4:0] \sh [4:0]
- assign $1\mb$8[6:0]$12266 [6:5] $3\mb$8[6:5]$12268
+ assign $1\mb$8[6:0]$12078 [4:0] \sh [4:0]
+ assign $1\mb$8[6:0]$12078 [6:5] $3\mb$8[6:5]$12080
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
switch \is_32bit
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\mb$8[6:5]$12268 { \sh [5] \$11 }
+ assign $3\mb$8[6:5]$12080 { \sh [5] \$11 }
case
- assign $3\mb$8[6:5]$12268 \sh [6:5]
+ assign $3\mb$8[6:5]$12080 \sh [6:5]
end
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\mb$8[6:0]$12266 { 1'0 \is_32bit 5'00000 }
+ assign $1\mb$8[6:0]$12078 { 1'0 \is_32bit 5'00000 }
end
sync always
- update \mb$8 $0\mb$8[6:0]$12265
+ update \mb$8 $0\mb$8[6:0]$12077
end
- attribute \src "libresoc.v:187112.3-187126.6"
- process $proc$libresoc.v:187112$12269
+ attribute \src "libresoc.v:186056.3-186070.6"
+ process $proc$libresoc.v:186056$12081
assign { } { }
- assign $0\me$13[6:0]$12270 $1\me$13[6:0]$12271
- attribute \src "libresoc.v:187113.5-187113.29"
+ assign $0\me$13[6:0]$12082 $1\me$13[6:0]$12083
+ attribute \src "libresoc.v:186057.5-186057.29"
switch \initial
- attribute \src "libresoc.v:187113.9-187113.17"
+ attribute \src "libresoc.v:186057.9-186057.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\me$13[6:0]$12271 { 2'01 \me }
+ assign $1\me$13[6:0]$12083 { 2'01 \me }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\me$13[6:0]$12271 { 1'0 \mb_extra \mb }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\me$13[6:0]$12271 { \sh [6] \$20 }
- end
- sync always
- update \me$13 $0\me$13[6:0]$12270
- end
- connect \$9 $pos$libresoc.v:186928$12219_Y
- connect \$11 $not$libresoc.v:186929$12220_Y
- connect \$14 $and$libresoc.v:186930$12221_Y
- connect \$16 $not$libresoc.v:186931$12222_Y
- connect \$18 $and$libresoc.v:186932$12223_Y
- connect \$20 $not$libresoc.v:186933$12224_Y
- connect \$22 $le$libresoc.v:186934$12225_Y
- connect \$25 $sub$libresoc.v:186935$12226_Y
- connect \$27 $le$libresoc.v:186936$12227_Y
- connect \$2 $neg$libresoc.v:186937$12228_Y
- connect \$30 $sub$libresoc.v:186938$12229_Y
- connect \$32 $not$libresoc.v:186939$12230_Y
- connect \$34 $not$libresoc.v:186940$12231_Y
- connect \$36 $and$libresoc.v:186941$12232_Y
- connect \$38 $or$libresoc.v:186942$12233_Y
- connect \$40 $and$libresoc.v:186943$12234_Y
- connect \$42 $gt$libresoc.v:186944$12235_Y
- connect \$44 $and$libresoc.v:186945$12236_Y
- connect \$46 $and$libresoc.v:186946$12237_Y
- connect \$48 $and$libresoc.v:186947$12238_Y
- connect \$4 $not$libresoc.v:186948$12239_Y
- connect \$51 $and$libresoc.v:186949$12240_Y
- connect \$50 $not$libresoc.v:186950$12241_Y
- connect \$54 $and$libresoc.v:186951$12242_Y
- connect \$56 $or$libresoc.v:186952$12243_Y
- connect \$58 $or$libresoc.v:186953$12244_Y
- connect \$60 $and$libresoc.v:186954$12245_Y
- connect \$63 $or$libresoc.v:186955$12246_Y
- connect \$62 $not$libresoc.v:186956$12247_Y
- connect \$66 $and$libresoc.v:186957$12248_Y
- connect \$68 $or$libresoc.v:186958$12249_Y
- connect \$6 $and$libresoc.v:186959$12250_Y
- connect \$70 $and$libresoc.v:186960$12251_Y
- connect \$72 $not$libresoc.v:186961$12252_Y
- connect \$74 $or$libresoc.v:186962$12253_Y
- connect \$77 $not$libresoc.v:186963$12254_Y
- connect \$79 $and$libresoc.v:186964$12255_Y
- connect \$76 $reduce_or$libresoc.v:186965$12256_Y
+ assign $1\me$13[6:0]$12083 { 1'0 \mb_extra \mb }
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $1\me$13[6:0]$12083 { \sh [6] \$20 }
+ end
+ sync always
+ update \me$13 $0\me$13[6:0]$12082
+ end
+ connect \$9 $pos$libresoc.v:185872$12031_Y
+ connect \$11 $not$libresoc.v:185873$12032_Y
+ connect \$14 $and$libresoc.v:185874$12033_Y
+ connect \$16 $not$libresoc.v:185875$12034_Y
+ connect \$18 $and$libresoc.v:185876$12035_Y
+ connect \$20 $not$libresoc.v:185877$12036_Y
+ connect \$22 $le$libresoc.v:185878$12037_Y
+ connect \$25 $sub$libresoc.v:185879$12038_Y
+ connect \$27 $le$libresoc.v:185880$12039_Y
+ connect \$2 $neg$libresoc.v:185881$12040_Y
+ connect \$30 $sub$libresoc.v:185882$12041_Y
+ connect \$32 $not$libresoc.v:185883$12042_Y
+ connect \$34 $not$libresoc.v:185884$12043_Y
+ connect \$36 $and$libresoc.v:185885$12044_Y
+ connect \$38 $or$libresoc.v:185886$12045_Y
+ connect \$40 $and$libresoc.v:185887$12046_Y
+ connect \$42 $gt$libresoc.v:185888$12047_Y
+ connect \$44 $and$libresoc.v:185889$12048_Y
+ connect \$46 $and$libresoc.v:185890$12049_Y
+ connect \$48 $and$libresoc.v:185891$12050_Y
+ connect \$4 $not$libresoc.v:185892$12051_Y
+ connect \$51 $and$libresoc.v:185893$12052_Y
+ connect \$50 $not$libresoc.v:185894$12053_Y
+ connect \$54 $and$libresoc.v:185895$12054_Y
+ connect \$56 $or$libresoc.v:185896$12055_Y
+ connect \$58 $or$libresoc.v:185897$12056_Y
+ connect \$60 $and$libresoc.v:185898$12057_Y
+ connect \$63 $or$libresoc.v:185899$12058_Y
+ connect \$62 $not$libresoc.v:185900$12059_Y
+ connect \$66 $and$libresoc.v:185901$12060_Y
+ connect \$68 $or$libresoc.v:185902$12061_Y
+ connect \$6 $and$libresoc.v:185903$12062_Y
+ connect \$70 $and$libresoc.v:185904$12063_Y
+ connect \$72 $not$libresoc.v:185905$12064_Y
+ connect \$74 $or$libresoc.v:185906$12065_Y
+ connect \$77 $not$libresoc.v:185907$12066_Y
+ connect \$79 $and$libresoc.v:185908$12067_Y
+ connect \$76 $reduce_or$libresoc.v:185909$12068_Y
connect \$1 \$2
connect \$24 \$25
connect \$29 \$30
connect \shift_signed \shift [5:0]
connect \repl32 { \hi32 \rs [31:0] }
end
-attribute \src "libresoc.v:187142.1-187156.10"
+attribute \src "libresoc.v:186086.1-186100.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl"
attribute \generator "nMigen"
module \rotl
- attribute \src "libresoc.v:187154.17-187154.32"
- wire width 128 $shr$libresoc.v:187154$12274_Y
- attribute \src "libresoc.v:187153.17-187153.100"
- wire width 8 $sub$libresoc.v:187153$12273_Y
+ attribute \src "libresoc.v:186098.17-186098.32"
+ wire width 128 $shr$libresoc.v:186098$12086_Y
+ attribute \src "libresoc.v:186097.17-186097.100"
+ wire width 8 $sub$libresoc.v:186097$12085_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
wire width 6 input 1 \b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
wire width 64 output 2 \o
- attribute \src "libresoc.v:187154.17-187154.32"
- cell $shr $shr$libresoc.v:187154$12274
+ attribute \src "libresoc.v:186098.17-186098.32"
+ cell $shr $shr$libresoc.v:186098$12086
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \B_SIGNED 0
parameter \Y_WIDTH 128
connect \A { \a \a }
connect \B \$2
- connect \Y $shr$libresoc.v:187154$12274_Y
+ connect \Y $shr$libresoc.v:186098$12086_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
- cell $sub $sub$libresoc.v:187153$12273
+ cell $sub $sub$libresoc.v:186097$12085
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 7'1000000
connect \B \b
- connect \Y $sub$libresoc.v:187153$12273_Y
+ connect \Y $sub$libresoc.v:186097$12085_Y
end
- connect \$2 $sub$libresoc.v:187153$12273_Y
- connect \$1 $shr$libresoc.v:187154$12274_Y [63:0]
+ connect \$2 $sub$libresoc.v:186097$12085_Y
+ connect \$1 $shr$libresoc.v:186098$12086_Y [63:0]
connect \o \$1
end
-attribute \src "libresoc.v:187160.1-187218.10"
+attribute \src "libresoc.v:186104.1-186162.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l"
attribute \generator "nMigen"
module \rst_l
- attribute \src "libresoc.v:187161.7-187161.20"
+ attribute \src "libresoc.v:186105.7-186105.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187206.3-187214.6"
- wire $0\q_int$next[0:0]$12285
- attribute \src "libresoc.v:187204.3-187205.27"
+ attribute \src "libresoc.v:186150.3-186158.6"
+ wire $0\q_int$next[0:0]$12097
+ attribute \src "libresoc.v:186148.3-186149.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187206.3-187214.6"
- wire $1\q_int$next[0:0]$12286
- attribute \src "libresoc.v:187183.7-187183.19"
+ attribute \src "libresoc.v:186150.3-186158.6"
+ wire $1\q_int$next[0:0]$12098
+ attribute \src "libresoc.v:186127.7-186127.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187196.17-187196.96"
- wire $and$libresoc.v:187196$12275_Y
- attribute \src "libresoc.v:187201.17-187201.96"
- wire $and$libresoc.v:187201$12280_Y
- attribute \src "libresoc.v:187198.18-187198.93"
- wire $not$libresoc.v:187198$12277_Y
- attribute \src "libresoc.v:187200.17-187200.92"
- wire $not$libresoc.v:187200$12279_Y
- attribute \src "libresoc.v:187203.17-187203.92"
- wire $not$libresoc.v:187203$12282_Y
- attribute \src "libresoc.v:187197.18-187197.98"
- wire $or$libresoc.v:187197$12276_Y
- attribute \src "libresoc.v:187199.18-187199.99"
- wire $or$libresoc.v:187199$12278_Y
- attribute \src "libresoc.v:187202.17-187202.97"
- wire $or$libresoc.v:187202$12281_Y
+ attribute \src "libresoc.v:186140.17-186140.96"
+ wire $and$libresoc.v:186140$12087_Y
+ attribute \src "libresoc.v:186145.17-186145.96"
+ wire $and$libresoc.v:186145$12092_Y
+ attribute \src "libresoc.v:186142.18-186142.93"
+ wire $not$libresoc.v:186142$12089_Y
+ attribute \src "libresoc.v:186144.17-186144.92"
+ wire $not$libresoc.v:186144$12091_Y
+ attribute \src "libresoc.v:186147.17-186147.92"
+ wire $not$libresoc.v:186147$12094_Y
+ attribute \src "libresoc.v:186141.18-186141.98"
+ wire $or$libresoc.v:186141$12088_Y
+ attribute \src "libresoc.v:186143.18-186143.99"
+ wire $or$libresoc.v:186143$12090_Y
+ attribute \src "libresoc.v:186146.17-186146.97"
+ wire $or$libresoc.v:186146$12093_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187161.7-187161.15"
+ attribute \src "libresoc.v:186105.7-186105.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187196$12275
+ cell $and $and$libresoc.v:186140$12087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187196$12275_Y
+ connect \Y $and$libresoc.v:186140$12087_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187201$12280
+ cell $and $and$libresoc.v:186145$12092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187201$12280_Y
+ connect \Y $and$libresoc.v:186145$12092_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187198$12277
+ cell $not $not$libresoc.v:186142$12089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187198$12277_Y
+ connect \Y $not$libresoc.v:186142$12089_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187200$12279
+ cell $not $not$libresoc.v:186144$12091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187200$12279_Y
+ connect \Y $not$libresoc.v:186144$12091_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187203$12282
+ cell $not $not$libresoc.v:186147$12094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187203$12282_Y
+ connect \Y $not$libresoc.v:186147$12094_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187197$12276
+ cell $or $or$libresoc.v:186141$12088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187197$12276_Y
+ connect \Y $or$libresoc.v:186141$12088_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187199$12278
+ cell $or $or$libresoc.v:186143$12090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187199$12278_Y
+ connect \Y $or$libresoc.v:186143$12090_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187202$12281
+ cell $or $or$libresoc.v:186146$12093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187202$12281_Y
+ connect \Y $or$libresoc.v:186146$12093_Y
end
- attribute \src "libresoc.v:187161.7-187161.20"
- process $proc$libresoc.v:187161$12287
+ attribute \src "libresoc.v:186105.7-186105.20"
+ process $proc$libresoc.v:186105$12099
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187183.7-187183.19"
- process $proc$libresoc.v:187183$12288
+ attribute \src "libresoc.v:186127.7-186127.19"
+ process $proc$libresoc.v:186127$12100
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187204.3-187205.27"
- process $proc$libresoc.v:187204$12283
+ attribute \src "libresoc.v:186148.3-186149.27"
+ process $proc$libresoc.v:186148$12095
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187206.3-187214.6"
- process $proc$libresoc.v:187206$12284
+ attribute \src "libresoc.v:186150.3-186158.6"
+ process $proc$libresoc.v:186150$12096
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12285 $1\q_int$next[0:0]$12286
- attribute \src "libresoc.v:187207.5-187207.29"
+ assign $0\q_int$next[0:0]$12097 $1\q_int$next[0:0]$12098
+ attribute \src "libresoc.v:186151.5-186151.29"
switch \initial
- attribute \src "libresoc.v:187207.9-187207.17"
+ attribute \src "libresoc.v:186151.9-186151.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12286 1'0
+ assign $1\q_int$next[0:0]$12098 1'0
case
- assign $1\q_int$next[0:0]$12286 \$5
+ assign $1\q_int$next[0:0]$12098 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12285
+ update \q_int$next $0\q_int$next[0:0]$12097
end
- connect \$9 $and$libresoc.v:187196$12275_Y
- connect \$11 $or$libresoc.v:187197$12276_Y
- connect \$13 $not$libresoc.v:187198$12277_Y
- connect \$15 $or$libresoc.v:187199$12278_Y
- connect \$1 $not$libresoc.v:187200$12279_Y
- connect \$3 $and$libresoc.v:187201$12280_Y
- connect \$5 $or$libresoc.v:187202$12281_Y
- connect \$7 $not$libresoc.v:187203$12282_Y
+ connect \$9 $and$libresoc.v:186140$12087_Y
+ connect \$11 $or$libresoc.v:186141$12088_Y
+ connect \$13 $not$libresoc.v:186142$12089_Y
+ connect \$15 $or$libresoc.v:186143$12090_Y
+ connect \$1 $not$libresoc.v:186144$12091_Y
+ connect \$3 $and$libresoc.v:186145$12092_Y
+ connect \$5 $or$libresoc.v:186146$12093_Y
+ connect \$7 $not$libresoc.v:186147$12094_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187222.1-187280.10"
+attribute \src "libresoc.v:186166.1-186224.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l"
attribute \generator "nMigen"
module \rst_l$104
- attribute \src "libresoc.v:187223.7-187223.20"
+ attribute \src "libresoc.v:186167.7-186167.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187268.3-187276.6"
- wire $0\q_int$next[0:0]$12299
- attribute \src "libresoc.v:187266.3-187267.27"
+ attribute \src "libresoc.v:186212.3-186220.6"
+ wire $0\q_int$next[0:0]$12111
+ attribute \src "libresoc.v:186210.3-186211.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187268.3-187276.6"
- wire $1\q_int$next[0:0]$12300
- attribute \src "libresoc.v:187245.7-187245.19"
+ attribute \src "libresoc.v:186212.3-186220.6"
+ wire $1\q_int$next[0:0]$12112
+ attribute \src "libresoc.v:186189.7-186189.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187258.17-187258.96"
- wire $and$libresoc.v:187258$12289_Y
- attribute \src "libresoc.v:187263.17-187263.96"
- wire $and$libresoc.v:187263$12294_Y
- attribute \src "libresoc.v:187260.18-187260.93"
- wire $not$libresoc.v:187260$12291_Y
- attribute \src "libresoc.v:187262.17-187262.92"
- wire $not$libresoc.v:187262$12293_Y
- attribute \src "libresoc.v:187265.17-187265.92"
- wire $not$libresoc.v:187265$12296_Y
- attribute \src "libresoc.v:187259.18-187259.98"
- wire $or$libresoc.v:187259$12290_Y
- attribute \src "libresoc.v:187261.18-187261.99"
- wire $or$libresoc.v:187261$12292_Y
- attribute \src "libresoc.v:187264.17-187264.97"
- wire $or$libresoc.v:187264$12295_Y
+ attribute \src "libresoc.v:186202.17-186202.96"
+ wire $and$libresoc.v:186202$12101_Y
+ attribute \src "libresoc.v:186207.17-186207.96"
+ wire $and$libresoc.v:186207$12106_Y
+ attribute \src "libresoc.v:186204.18-186204.93"
+ wire $not$libresoc.v:186204$12103_Y
+ attribute \src "libresoc.v:186206.17-186206.92"
+ wire $not$libresoc.v:186206$12105_Y
+ attribute \src "libresoc.v:186209.17-186209.92"
+ wire $not$libresoc.v:186209$12108_Y
+ attribute \src "libresoc.v:186203.18-186203.98"
+ wire $or$libresoc.v:186203$12102_Y
+ attribute \src "libresoc.v:186205.18-186205.99"
+ wire $or$libresoc.v:186205$12104_Y
+ attribute \src "libresoc.v:186208.17-186208.97"
+ wire $or$libresoc.v:186208$12107_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187223.7-187223.15"
+ attribute \src "libresoc.v:186167.7-186167.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187258$12289
+ cell $and $and$libresoc.v:186202$12101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187258$12289_Y
+ connect \Y $and$libresoc.v:186202$12101_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187263$12294
+ cell $and $and$libresoc.v:186207$12106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187263$12294_Y
+ connect \Y $and$libresoc.v:186207$12106_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187260$12291
+ cell $not $not$libresoc.v:186204$12103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187260$12291_Y
+ connect \Y $not$libresoc.v:186204$12103_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187262$12293
+ cell $not $not$libresoc.v:186206$12105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187262$12293_Y
+ connect \Y $not$libresoc.v:186206$12105_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187265$12296
+ cell $not $not$libresoc.v:186209$12108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187265$12296_Y
+ connect \Y $not$libresoc.v:186209$12108_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187259$12290
+ cell $or $or$libresoc.v:186203$12102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187259$12290_Y
+ connect \Y $or$libresoc.v:186203$12102_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187261$12292
+ cell $or $or$libresoc.v:186205$12104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187261$12292_Y
+ connect \Y $or$libresoc.v:186205$12104_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187264$12295
+ cell $or $or$libresoc.v:186208$12107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187264$12295_Y
+ connect \Y $or$libresoc.v:186208$12107_Y
end
- attribute \src "libresoc.v:187223.7-187223.20"
- process $proc$libresoc.v:187223$12301
+ attribute \src "libresoc.v:186167.7-186167.20"
+ process $proc$libresoc.v:186167$12113
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187245.7-187245.19"
- process $proc$libresoc.v:187245$12302
+ attribute \src "libresoc.v:186189.7-186189.19"
+ process $proc$libresoc.v:186189$12114
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187266.3-187267.27"
- process $proc$libresoc.v:187266$12297
+ attribute \src "libresoc.v:186210.3-186211.27"
+ process $proc$libresoc.v:186210$12109
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187268.3-187276.6"
- process $proc$libresoc.v:187268$12298
+ attribute \src "libresoc.v:186212.3-186220.6"
+ process $proc$libresoc.v:186212$12110
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12299 $1\q_int$next[0:0]$12300
- attribute \src "libresoc.v:187269.5-187269.29"
+ assign $0\q_int$next[0:0]$12111 $1\q_int$next[0:0]$12112
+ attribute \src "libresoc.v:186213.5-186213.29"
switch \initial
- attribute \src "libresoc.v:187269.9-187269.17"
+ attribute \src "libresoc.v:186213.9-186213.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12300 1'0
+ assign $1\q_int$next[0:0]$12112 1'0
case
- assign $1\q_int$next[0:0]$12300 \$5
+ assign $1\q_int$next[0:0]$12112 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12299
+ update \q_int$next $0\q_int$next[0:0]$12111
end
- connect \$9 $and$libresoc.v:187258$12289_Y
- connect \$11 $or$libresoc.v:187259$12290_Y
- connect \$13 $not$libresoc.v:187260$12291_Y
- connect \$15 $or$libresoc.v:187261$12292_Y
- connect \$1 $not$libresoc.v:187262$12293_Y
- connect \$3 $and$libresoc.v:187263$12294_Y
- connect \$5 $or$libresoc.v:187264$12295_Y
- connect \$7 $not$libresoc.v:187265$12296_Y
+ connect \$9 $and$libresoc.v:186202$12101_Y
+ connect \$11 $or$libresoc.v:186203$12102_Y
+ connect \$13 $not$libresoc.v:186204$12103_Y
+ connect \$15 $or$libresoc.v:186205$12104_Y
+ connect \$1 $not$libresoc.v:186206$12105_Y
+ connect \$3 $and$libresoc.v:186207$12106_Y
+ connect \$5 $or$libresoc.v:186208$12107_Y
+ connect \$7 $not$libresoc.v:186209$12108_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187284.1-187342.10"
+attribute \src "libresoc.v:186228.1-186286.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l"
attribute \generator "nMigen"
module \rst_l$122
- attribute \src "libresoc.v:187285.7-187285.20"
+ attribute \src "libresoc.v:186229.7-186229.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187330.3-187338.6"
- wire $0\q_int$next[0:0]$12313
- attribute \src "libresoc.v:187328.3-187329.27"
+ attribute \src "libresoc.v:186274.3-186282.6"
+ wire $0\q_int$next[0:0]$12125
+ attribute \src "libresoc.v:186272.3-186273.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187330.3-187338.6"
- wire $1\q_int$next[0:0]$12314
- attribute \src "libresoc.v:187307.7-187307.19"
+ attribute \src "libresoc.v:186274.3-186282.6"
+ wire $1\q_int$next[0:0]$12126
+ attribute \src "libresoc.v:186251.7-186251.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187320.17-187320.96"
- wire $and$libresoc.v:187320$12303_Y
- attribute \src "libresoc.v:187325.17-187325.96"
- wire $and$libresoc.v:187325$12308_Y
- attribute \src "libresoc.v:187322.18-187322.93"
- wire $not$libresoc.v:187322$12305_Y
- attribute \src "libresoc.v:187324.17-187324.92"
- wire $not$libresoc.v:187324$12307_Y
- attribute \src "libresoc.v:187327.17-187327.92"
- wire $not$libresoc.v:187327$12310_Y
- attribute \src "libresoc.v:187321.18-187321.98"
- wire $or$libresoc.v:187321$12304_Y
- attribute \src "libresoc.v:187323.18-187323.99"
- wire $or$libresoc.v:187323$12306_Y
- attribute \src "libresoc.v:187326.17-187326.97"
- wire $or$libresoc.v:187326$12309_Y
+ attribute \src "libresoc.v:186264.17-186264.96"
+ wire $and$libresoc.v:186264$12115_Y
+ attribute \src "libresoc.v:186269.17-186269.96"
+ wire $and$libresoc.v:186269$12120_Y
+ attribute \src "libresoc.v:186266.18-186266.93"
+ wire $not$libresoc.v:186266$12117_Y
+ attribute \src "libresoc.v:186268.17-186268.92"
+ wire $not$libresoc.v:186268$12119_Y
+ attribute \src "libresoc.v:186271.17-186271.92"
+ wire $not$libresoc.v:186271$12122_Y
+ attribute \src "libresoc.v:186265.18-186265.98"
+ wire $or$libresoc.v:186265$12116_Y
+ attribute \src "libresoc.v:186267.18-186267.99"
+ wire $or$libresoc.v:186267$12118_Y
+ attribute \src "libresoc.v:186270.17-186270.97"
+ wire $or$libresoc.v:186270$12121_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187285.7-187285.15"
+ attribute \src "libresoc.v:186229.7-186229.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187320$12303
+ cell $and $and$libresoc.v:186264$12115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187320$12303_Y
+ connect \Y $and$libresoc.v:186264$12115_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187325$12308
+ cell $and $and$libresoc.v:186269$12120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187325$12308_Y
+ connect \Y $and$libresoc.v:186269$12120_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187322$12305
+ cell $not $not$libresoc.v:186266$12117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187322$12305_Y
+ connect \Y $not$libresoc.v:186266$12117_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187324$12307
+ cell $not $not$libresoc.v:186268$12119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187324$12307_Y
+ connect \Y $not$libresoc.v:186268$12119_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187327$12310
+ cell $not $not$libresoc.v:186271$12122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187327$12310_Y
+ connect \Y $not$libresoc.v:186271$12122_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187321$12304
+ cell $or $or$libresoc.v:186265$12116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187321$12304_Y
+ connect \Y $or$libresoc.v:186265$12116_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187323$12306
+ cell $or $or$libresoc.v:186267$12118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187323$12306_Y
+ connect \Y $or$libresoc.v:186267$12118_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187326$12309
+ cell $or $or$libresoc.v:186270$12121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187326$12309_Y
+ connect \Y $or$libresoc.v:186270$12121_Y
end
- attribute \src "libresoc.v:187285.7-187285.20"
- process $proc$libresoc.v:187285$12315
+ attribute \src "libresoc.v:186229.7-186229.20"
+ process $proc$libresoc.v:186229$12127
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187307.7-187307.19"
- process $proc$libresoc.v:187307$12316
+ attribute \src "libresoc.v:186251.7-186251.19"
+ process $proc$libresoc.v:186251$12128
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187328.3-187329.27"
- process $proc$libresoc.v:187328$12311
+ attribute \src "libresoc.v:186272.3-186273.27"
+ process $proc$libresoc.v:186272$12123
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187330.3-187338.6"
- process $proc$libresoc.v:187330$12312
+ attribute \src "libresoc.v:186274.3-186282.6"
+ process $proc$libresoc.v:186274$12124
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12313 $1\q_int$next[0:0]$12314
- attribute \src "libresoc.v:187331.5-187331.29"
+ assign $0\q_int$next[0:0]$12125 $1\q_int$next[0:0]$12126
+ attribute \src "libresoc.v:186275.5-186275.29"
switch \initial
- attribute \src "libresoc.v:187331.9-187331.17"
+ attribute \src "libresoc.v:186275.9-186275.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12314 1'0
+ assign $1\q_int$next[0:0]$12126 1'0
case
- assign $1\q_int$next[0:0]$12314 \$5
+ assign $1\q_int$next[0:0]$12126 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12313
+ update \q_int$next $0\q_int$next[0:0]$12125
end
- connect \$9 $and$libresoc.v:187320$12303_Y
- connect \$11 $or$libresoc.v:187321$12304_Y
- connect \$13 $not$libresoc.v:187322$12305_Y
- connect \$15 $or$libresoc.v:187323$12306_Y
- connect \$1 $not$libresoc.v:187324$12307_Y
- connect \$3 $and$libresoc.v:187325$12308_Y
- connect \$5 $or$libresoc.v:187326$12309_Y
- connect \$7 $not$libresoc.v:187327$12310_Y
+ connect \$9 $and$libresoc.v:186264$12115_Y
+ connect \$11 $or$libresoc.v:186265$12116_Y
+ connect \$13 $not$libresoc.v:186266$12117_Y
+ connect \$15 $or$libresoc.v:186267$12118_Y
+ connect \$1 $not$libresoc.v:186268$12119_Y
+ connect \$3 $and$libresoc.v:186269$12120_Y
+ connect \$5 $or$libresoc.v:186270$12121_Y
+ connect \$7 $not$libresoc.v:186271$12122_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187346.1-187404.10"
+attribute \src "libresoc.v:186290.1-186348.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l"
attribute \generator "nMigen"
module \rst_l$129
- attribute \src "libresoc.v:187347.7-187347.20"
+ attribute \src "libresoc.v:186291.7-186291.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187392.3-187400.6"
- wire $0\q_int$next[0:0]$12327
- attribute \src "libresoc.v:187390.3-187391.27"
+ attribute \src "libresoc.v:186336.3-186344.6"
+ wire $0\q_int$next[0:0]$12139
+ attribute \src "libresoc.v:186334.3-186335.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187392.3-187400.6"
- wire $1\q_int$next[0:0]$12328
- attribute \src "libresoc.v:187369.7-187369.19"
+ attribute \src "libresoc.v:186336.3-186344.6"
+ wire $1\q_int$next[0:0]$12140
+ attribute \src "libresoc.v:186313.7-186313.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187382.17-187382.96"
- wire $and$libresoc.v:187382$12317_Y
- attribute \src "libresoc.v:187387.17-187387.96"
- wire $and$libresoc.v:187387$12322_Y
- attribute \src "libresoc.v:187384.18-187384.93"
- wire $not$libresoc.v:187384$12319_Y
- attribute \src "libresoc.v:187386.17-187386.92"
- wire $not$libresoc.v:187386$12321_Y
- attribute \src "libresoc.v:187389.17-187389.92"
- wire $not$libresoc.v:187389$12324_Y
- attribute \src "libresoc.v:187383.18-187383.98"
- wire $or$libresoc.v:187383$12318_Y
- attribute \src "libresoc.v:187385.18-187385.99"
- wire $or$libresoc.v:187385$12320_Y
- attribute \src "libresoc.v:187388.17-187388.97"
- wire $or$libresoc.v:187388$12323_Y
+ attribute \src "libresoc.v:186326.17-186326.96"
+ wire $and$libresoc.v:186326$12129_Y
+ attribute \src "libresoc.v:186331.17-186331.96"
+ wire $and$libresoc.v:186331$12134_Y
+ attribute \src "libresoc.v:186328.18-186328.93"
+ wire $not$libresoc.v:186328$12131_Y
+ attribute \src "libresoc.v:186330.17-186330.92"
+ wire $not$libresoc.v:186330$12133_Y
+ attribute \src "libresoc.v:186333.17-186333.92"
+ wire $not$libresoc.v:186333$12136_Y
+ attribute \src "libresoc.v:186327.18-186327.98"
+ wire $or$libresoc.v:186327$12130_Y
+ attribute \src "libresoc.v:186329.18-186329.99"
+ wire $or$libresoc.v:186329$12132_Y
+ attribute \src "libresoc.v:186332.17-186332.97"
+ wire $or$libresoc.v:186332$12135_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187347.7-187347.15"
+ attribute \src "libresoc.v:186291.7-186291.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187382$12317
+ cell $and $and$libresoc.v:186326$12129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187382$12317_Y
+ connect \Y $and$libresoc.v:186326$12129_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187387$12322
+ cell $and $and$libresoc.v:186331$12134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187387$12322_Y
+ connect \Y $and$libresoc.v:186331$12134_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187384$12319
+ cell $not $not$libresoc.v:186328$12131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187384$12319_Y
+ connect \Y $not$libresoc.v:186328$12131_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187386$12321
+ cell $not $not$libresoc.v:186330$12133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187386$12321_Y
+ connect \Y $not$libresoc.v:186330$12133_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187389$12324
+ cell $not $not$libresoc.v:186333$12136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187389$12324_Y
+ connect \Y $not$libresoc.v:186333$12136_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187383$12318
+ cell $or $or$libresoc.v:186327$12130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187383$12318_Y
+ connect \Y $or$libresoc.v:186327$12130_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187385$12320
+ cell $or $or$libresoc.v:186329$12132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187385$12320_Y
+ connect \Y $or$libresoc.v:186329$12132_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187388$12323
+ cell $or $or$libresoc.v:186332$12135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187388$12323_Y
+ connect \Y $or$libresoc.v:186332$12135_Y
end
- attribute \src "libresoc.v:187347.7-187347.20"
- process $proc$libresoc.v:187347$12329
+ attribute \src "libresoc.v:186291.7-186291.20"
+ process $proc$libresoc.v:186291$12141
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187369.7-187369.19"
- process $proc$libresoc.v:187369$12330
+ attribute \src "libresoc.v:186313.7-186313.19"
+ process $proc$libresoc.v:186313$12142
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187390.3-187391.27"
- process $proc$libresoc.v:187390$12325
+ attribute \src "libresoc.v:186334.3-186335.27"
+ process $proc$libresoc.v:186334$12137
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187392.3-187400.6"
- process $proc$libresoc.v:187392$12326
+ attribute \src "libresoc.v:186336.3-186344.6"
+ process $proc$libresoc.v:186336$12138
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12327 $1\q_int$next[0:0]$12328
- attribute \src "libresoc.v:187393.5-187393.29"
+ assign $0\q_int$next[0:0]$12139 $1\q_int$next[0:0]$12140
+ attribute \src "libresoc.v:186337.5-186337.29"
switch \initial
- attribute \src "libresoc.v:187393.9-187393.17"
+ attribute \src "libresoc.v:186337.9-186337.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12328 1'0
+ assign $1\q_int$next[0:0]$12140 1'0
case
- assign $1\q_int$next[0:0]$12328 \$5
+ assign $1\q_int$next[0:0]$12140 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12327
+ update \q_int$next $0\q_int$next[0:0]$12139
end
- connect \$9 $and$libresoc.v:187382$12317_Y
- connect \$11 $or$libresoc.v:187383$12318_Y
- connect \$13 $not$libresoc.v:187384$12319_Y
- connect \$15 $or$libresoc.v:187385$12320_Y
- connect \$1 $not$libresoc.v:187386$12321_Y
- connect \$3 $and$libresoc.v:187387$12322_Y
- connect \$5 $or$libresoc.v:187388$12323_Y
- connect \$7 $not$libresoc.v:187389$12324_Y
+ connect \$9 $and$libresoc.v:186326$12129_Y
+ connect \$11 $or$libresoc.v:186327$12130_Y
+ connect \$13 $not$libresoc.v:186328$12131_Y
+ connect \$15 $or$libresoc.v:186329$12132_Y
+ connect \$1 $not$libresoc.v:186330$12133_Y
+ connect \$3 $and$libresoc.v:186331$12134_Y
+ connect \$5 $or$libresoc.v:186332$12135_Y
+ connect \$7 $not$libresoc.v:186333$12136_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187408.1-187466.10"
+attribute \src "libresoc.v:186352.1-186410.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l"
attribute \generator "nMigen"
module \rst_l$13
- attribute \src "libresoc.v:187409.7-187409.20"
+ attribute \src "libresoc.v:186353.7-186353.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187454.3-187462.6"
- wire $0\q_int$next[0:0]$12341
- attribute \src "libresoc.v:187452.3-187453.27"
+ attribute \src "libresoc.v:186398.3-186406.6"
+ wire $0\q_int$next[0:0]$12153
+ attribute \src "libresoc.v:186396.3-186397.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187454.3-187462.6"
- wire $1\q_int$next[0:0]$12342
- attribute \src "libresoc.v:187431.7-187431.19"
+ attribute \src "libresoc.v:186398.3-186406.6"
+ wire $1\q_int$next[0:0]$12154
+ attribute \src "libresoc.v:186375.7-186375.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187444.17-187444.96"
- wire $and$libresoc.v:187444$12331_Y
- attribute \src "libresoc.v:187449.17-187449.96"
- wire $and$libresoc.v:187449$12336_Y
- attribute \src "libresoc.v:187446.18-187446.93"
- wire $not$libresoc.v:187446$12333_Y
- attribute \src "libresoc.v:187448.17-187448.92"
- wire $not$libresoc.v:187448$12335_Y
- attribute \src "libresoc.v:187451.17-187451.92"
- wire $not$libresoc.v:187451$12338_Y
- attribute \src "libresoc.v:187445.18-187445.98"
- wire $or$libresoc.v:187445$12332_Y
- attribute \src "libresoc.v:187447.18-187447.99"
- wire $or$libresoc.v:187447$12334_Y
- attribute \src "libresoc.v:187450.17-187450.97"
- wire $or$libresoc.v:187450$12337_Y
+ attribute \src "libresoc.v:186388.17-186388.96"
+ wire $and$libresoc.v:186388$12143_Y
+ attribute \src "libresoc.v:186393.17-186393.96"
+ wire $and$libresoc.v:186393$12148_Y
+ attribute \src "libresoc.v:186390.18-186390.93"
+ wire $not$libresoc.v:186390$12145_Y
+ attribute \src "libresoc.v:186392.17-186392.92"
+ wire $not$libresoc.v:186392$12147_Y
+ attribute \src "libresoc.v:186395.17-186395.92"
+ wire $not$libresoc.v:186395$12150_Y
+ attribute \src "libresoc.v:186389.18-186389.98"
+ wire $or$libresoc.v:186389$12144_Y
+ attribute \src "libresoc.v:186391.18-186391.99"
+ wire $or$libresoc.v:186391$12146_Y
+ attribute \src "libresoc.v:186394.17-186394.97"
+ wire $or$libresoc.v:186394$12149_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187409.7-187409.15"
+ attribute \src "libresoc.v:186353.7-186353.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187444$12331
+ cell $and $and$libresoc.v:186388$12143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187444$12331_Y
+ connect \Y $and$libresoc.v:186388$12143_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187449$12336
+ cell $and $and$libresoc.v:186393$12148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187449$12336_Y
+ connect \Y $and$libresoc.v:186393$12148_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187446$12333
+ cell $not $not$libresoc.v:186390$12145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187446$12333_Y
+ connect \Y $not$libresoc.v:186390$12145_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187448$12335
+ cell $not $not$libresoc.v:186392$12147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187448$12335_Y
+ connect \Y $not$libresoc.v:186392$12147_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187451$12338
+ cell $not $not$libresoc.v:186395$12150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187451$12338_Y
+ connect \Y $not$libresoc.v:186395$12150_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187445$12332
+ cell $or $or$libresoc.v:186389$12144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187445$12332_Y
+ connect \Y $or$libresoc.v:186389$12144_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187447$12334
+ cell $or $or$libresoc.v:186391$12146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187447$12334_Y
+ connect \Y $or$libresoc.v:186391$12146_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187450$12337
+ cell $or $or$libresoc.v:186394$12149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187450$12337_Y
+ connect \Y $or$libresoc.v:186394$12149_Y
end
- attribute \src "libresoc.v:187409.7-187409.20"
- process $proc$libresoc.v:187409$12343
+ attribute \src "libresoc.v:186353.7-186353.20"
+ process $proc$libresoc.v:186353$12155
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187431.7-187431.19"
- process $proc$libresoc.v:187431$12344
+ attribute \src "libresoc.v:186375.7-186375.19"
+ process $proc$libresoc.v:186375$12156
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187452.3-187453.27"
- process $proc$libresoc.v:187452$12339
+ attribute \src "libresoc.v:186396.3-186397.27"
+ process $proc$libresoc.v:186396$12151
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187454.3-187462.6"
- process $proc$libresoc.v:187454$12340
+ attribute \src "libresoc.v:186398.3-186406.6"
+ process $proc$libresoc.v:186398$12152
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12341 $1\q_int$next[0:0]$12342
- attribute \src "libresoc.v:187455.5-187455.29"
+ assign $0\q_int$next[0:0]$12153 $1\q_int$next[0:0]$12154
+ attribute \src "libresoc.v:186399.5-186399.29"
switch \initial
- attribute \src "libresoc.v:187455.9-187455.17"
+ attribute \src "libresoc.v:186399.9-186399.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12342 1'0
+ assign $1\q_int$next[0:0]$12154 1'0
case
- assign $1\q_int$next[0:0]$12342 \$5
+ assign $1\q_int$next[0:0]$12154 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12341
+ update \q_int$next $0\q_int$next[0:0]$12153
end
- connect \$9 $and$libresoc.v:187444$12331_Y
- connect \$11 $or$libresoc.v:187445$12332_Y
- connect \$13 $not$libresoc.v:187446$12333_Y
- connect \$15 $or$libresoc.v:187447$12334_Y
- connect \$1 $not$libresoc.v:187448$12335_Y
- connect \$3 $and$libresoc.v:187449$12336_Y
- connect \$5 $or$libresoc.v:187450$12337_Y
- connect \$7 $not$libresoc.v:187451$12338_Y
+ connect \$9 $and$libresoc.v:186388$12143_Y
+ connect \$11 $or$libresoc.v:186389$12144_Y
+ connect \$13 $not$libresoc.v:186390$12145_Y
+ connect \$15 $or$libresoc.v:186391$12146_Y
+ connect \$1 $not$libresoc.v:186392$12147_Y
+ connect \$3 $and$libresoc.v:186393$12148_Y
+ connect \$5 $or$libresoc.v:186394$12149_Y
+ connect \$7 $not$libresoc.v:186395$12150_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187470.1-187528.10"
+attribute \src "libresoc.v:186414.1-186472.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l"
attribute \generator "nMigen"
module \rst_l$26
- attribute \src "libresoc.v:187471.7-187471.20"
+ attribute \src "libresoc.v:186415.7-186415.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187516.3-187524.6"
- wire $0\q_int$next[0:0]$12355
- attribute \src "libresoc.v:187514.3-187515.27"
+ attribute \src "libresoc.v:186460.3-186468.6"
+ wire $0\q_int$next[0:0]$12167
+ attribute \src "libresoc.v:186458.3-186459.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187516.3-187524.6"
- wire $1\q_int$next[0:0]$12356
- attribute \src "libresoc.v:187493.7-187493.19"
+ attribute \src "libresoc.v:186460.3-186468.6"
+ wire $1\q_int$next[0:0]$12168
+ attribute \src "libresoc.v:186437.7-186437.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187506.17-187506.96"
- wire $and$libresoc.v:187506$12345_Y
- attribute \src "libresoc.v:187511.17-187511.96"
- wire $and$libresoc.v:187511$12350_Y
- attribute \src "libresoc.v:187508.18-187508.93"
- wire $not$libresoc.v:187508$12347_Y
- attribute \src "libresoc.v:187510.17-187510.92"
- wire $not$libresoc.v:187510$12349_Y
- attribute \src "libresoc.v:187513.17-187513.92"
- wire $not$libresoc.v:187513$12352_Y
- attribute \src "libresoc.v:187507.18-187507.98"
- wire $or$libresoc.v:187507$12346_Y
- attribute \src "libresoc.v:187509.18-187509.99"
- wire $or$libresoc.v:187509$12348_Y
- attribute \src "libresoc.v:187512.17-187512.97"
- wire $or$libresoc.v:187512$12351_Y
+ attribute \src "libresoc.v:186450.17-186450.96"
+ wire $and$libresoc.v:186450$12157_Y
+ attribute \src "libresoc.v:186455.17-186455.96"
+ wire $and$libresoc.v:186455$12162_Y
+ attribute \src "libresoc.v:186452.18-186452.93"
+ wire $not$libresoc.v:186452$12159_Y
+ attribute \src "libresoc.v:186454.17-186454.92"
+ wire $not$libresoc.v:186454$12161_Y
+ attribute \src "libresoc.v:186457.17-186457.92"
+ wire $not$libresoc.v:186457$12164_Y
+ attribute \src "libresoc.v:186451.18-186451.98"
+ wire $or$libresoc.v:186451$12158_Y
+ attribute \src "libresoc.v:186453.18-186453.99"
+ wire $or$libresoc.v:186453$12160_Y
+ attribute \src "libresoc.v:186456.17-186456.97"
+ wire $or$libresoc.v:186456$12163_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187471.7-187471.15"
+ attribute \src "libresoc.v:186415.7-186415.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187506$12345
+ cell $and $and$libresoc.v:186450$12157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187506$12345_Y
+ connect \Y $and$libresoc.v:186450$12157_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187511$12350
+ cell $and $and$libresoc.v:186455$12162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187511$12350_Y
+ connect \Y $and$libresoc.v:186455$12162_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187508$12347
+ cell $not $not$libresoc.v:186452$12159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187508$12347_Y
+ connect \Y $not$libresoc.v:186452$12159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187510$12349
+ cell $not $not$libresoc.v:186454$12161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187510$12349_Y
+ connect \Y $not$libresoc.v:186454$12161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187513$12352
+ cell $not $not$libresoc.v:186457$12164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187513$12352_Y
+ connect \Y $not$libresoc.v:186457$12164_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187507$12346
+ cell $or $or$libresoc.v:186451$12158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187507$12346_Y
+ connect \Y $or$libresoc.v:186451$12158_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187509$12348
+ cell $or $or$libresoc.v:186453$12160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187509$12348_Y
+ connect \Y $or$libresoc.v:186453$12160_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187512$12351
+ cell $or $or$libresoc.v:186456$12163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187512$12351_Y
+ connect \Y $or$libresoc.v:186456$12163_Y
end
- attribute \src "libresoc.v:187471.7-187471.20"
- process $proc$libresoc.v:187471$12357
+ attribute \src "libresoc.v:186415.7-186415.20"
+ process $proc$libresoc.v:186415$12169
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187493.7-187493.19"
- process $proc$libresoc.v:187493$12358
+ attribute \src "libresoc.v:186437.7-186437.19"
+ process $proc$libresoc.v:186437$12170
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187514.3-187515.27"
- process $proc$libresoc.v:187514$12353
+ attribute \src "libresoc.v:186458.3-186459.27"
+ process $proc$libresoc.v:186458$12165
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187516.3-187524.6"
- process $proc$libresoc.v:187516$12354
+ attribute \src "libresoc.v:186460.3-186468.6"
+ process $proc$libresoc.v:186460$12166
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12355 $1\q_int$next[0:0]$12356
- attribute \src "libresoc.v:187517.5-187517.29"
+ assign $0\q_int$next[0:0]$12167 $1\q_int$next[0:0]$12168
+ attribute \src "libresoc.v:186461.5-186461.29"
switch \initial
- attribute \src "libresoc.v:187517.9-187517.17"
+ attribute \src "libresoc.v:186461.9-186461.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12356 1'0
+ assign $1\q_int$next[0:0]$12168 1'0
case
- assign $1\q_int$next[0:0]$12356 \$5
+ assign $1\q_int$next[0:0]$12168 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12355
+ update \q_int$next $0\q_int$next[0:0]$12167
end
- connect \$9 $and$libresoc.v:187506$12345_Y
- connect \$11 $or$libresoc.v:187507$12346_Y
- connect \$13 $not$libresoc.v:187508$12347_Y
- connect \$15 $or$libresoc.v:187509$12348_Y
- connect \$1 $not$libresoc.v:187510$12349_Y
- connect \$3 $and$libresoc.v:187511$12350_Y
- connect \$5 $or$libresoc.v:187512$12351_Y
- connect \$7 $not$libresoc.v:187513$12352_Y
+ connect \$9 $and$libresoc.v:186450$12157_Y
+ connect \$11 $or$libresoc.v:186451$12158_Y
+ connect \$13 $not$libresoc.v:186452$12159_Y
+ connect \$15 $or$libresoc.v:186453$12160_Y
+ connect \$1 $not$libresoc.v:186454$12161_Y
+ connect \$3 $and$libresoc.v:186455$12162_Y
+ connect \$5 $or$libresoc.v:186456$12163_Y
+ connect \$7 $not$libresoc.v:186457$12164_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187532.1-187590.10"
+attribute \src "libresoc.v:186476.1-186534.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l"
attribute \generator "nMigen"
module \rst_l$42
- attribute \src "libresoc.v:187533.7-187533.20"
+ attribute \src "libresoc.v:186477.7-186477.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187578.3-187586.6"
- wire $0\q_int$next[0:0]$12369
- attribute \src "libresoc.v:187576.3-187577.27"
+ attribute \src "libresoc.v:186522.3-186530.6"
+ wire $0\q_int$next[0:0]$12181
+ attribute \src "libresoc.v:186520.3-186521.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187578.3-187586.6"
- wire $1\q_int$next[0:0]$12370
- attribute \src "libresoc.v:187555.7-187555.19"
+ attribute \src "libresoc.v:186522.3-186530.6"
+ wire $1\q_int$next[0:0]$12182
+ attribute \src "libresoc.v:186499.7-186499.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187568.17-187568.96"
- wire $and$libresoc.v:187568$12359_Y
- attribute \src "libresoc.v:187573.17-187573.96"
- wire $and$libresoc.v:187573$12364_Y
- attribute \src "libresoc.v:187570.18-187570.93"
- wire $not$libresoc.v:187570$12361_Y
- attribute \src "libresoc.v:187572.17-187572.92"
- wire $not$libresoc.v:187572$12363_Y
- attribute \src "libresoc.v:187575.17-187575.92"
- wire $not$libresoc.v:187575$12366_Y
- attribute \src "libresoc.v:187569.18-187569.98"
- wire $or$libresoc.v:187569$12360_Y
- attribute \src "libresoc.v:187571.18-187571.99"
- wire $or$libresoc.v:187571$12362_Y
- attribute \src "libresoc.v:187574.17-187574.97"
- wire $or$libresoc.v:187574$12365_Y
+ attribute \src "libresoc.v:186512.17-186512.96"
+ wire $and$libresoc.v:186512$12171_Y
+ attribute \src "libresoc.v:186517.17-186517.96"
+ wire $and$libresoc.v:186517$12176_Y
+ attribute \src "libresoc.v:186514.18-186514.93"
+ wire $not$libresoc.v:186514$12173_Y
+ attribute \src "libresoc.v:186516.17-186516.92"
+ wire $not$libresoc.v:186516$12175_Y
+ attribute \src "libresoc.v:186519.17-186519.92"
+ wire $not$libresoc.v:186519$12178_Y
+ attribute \src "libresoc.v:186513.18-186513.98"
+ wire $or$libresoc.v:186513$12172_Y
+ attribute \src "libresoc.v:186515.18-186515.99"
+ wire $or$libresoc.v:186515$12174_Y
+ attribute \src "libresoc.v:186518.17-186518.97"
+ wire $or$libresoc.v:186518$12177_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187533.7-187533.15"
+ attribute \src "libresoc.v:186477.7-186477.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187568$12359
+ cell $and $and$libresoc.v:186512$12171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187568$12359_Y
+ connect \Y $and$libresoc.v:186512$12171_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187573$12364
+ cell $and $and$libresoc.v:186517$12176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187573$12364_Y
+ connect \Y $and$libresoc.v:186517$12176_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187570$12361
+ cell $not $not$libresoc.v:186514$12173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187570$12361_Y
+ connect \Y $not$libresoc.v:186514$12173_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187572$12363
+ cell $not $not$libresoc.v:186516$12175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187572$12363_Y
+ connect \Y $not$libresoc.v:186516$12175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187575$12366
+ cell $not $not$libresoc.v:186519$12178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187575$12366_Y
+ connect \Y $not$libresoc.v:186519$12178_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187569$12360
+ cell $or $or$libresoc.v:186513$12172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187569$12360_Y
+ connect \Y $or$libresoc.v:186513$12172_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187571$12362
+ cell $or $or$libresoc.v:186515$12174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187571$12362_Y
+ connect \Y $or$libresoc.v:186515$12174_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187574$12365
+ cell $or $or$libresoc.v:186518$12177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187574$12365_Y
+ connect \Y $or$libresoc.v:186518$12177_Y
end
- attribute \src "libresoc.v:187533.7-187533.20"
- process $proc$libresoc.v:187533$12371
+ attribute \src "libresoc.v:186477.7-186477.20"
+ process $proc$libresoc.v:186477$12183
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187555.7-187555.19"
- process $proc$libresoc.v:187555$12372
+ attribute \src "libresoc.v:186499.7-186499.19"
+ process $proc$libresoc.v:186499$12184
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187576.3-187577.27"
- process $proc$libresoc.v:187576$12367
+ attribute \src "libresoc.v:186520.3-186521.27"
+ process $proc$libresoc.v:186520$12179
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187578.3-187586.6"
- process $proc$libresoc.v:187578$12368
+ attribute \src "libresoc.v:186522.3-186530.6"
+ process $proc$libresoc.v:186522$12180
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12369 $1\q_int$next[0:0]$12370
- attribute \src "libresoc.v:187579.5-187579.29"
+ assign $0\q_int$next[0:0]$12181 $1\q_int$next[0:0]$12182
+ attribute \src "libresoc.v:186523.5-186523.29"
switch \initial
- attribute \src "libresoc.v:187579.9-187579.17"
+ attribute \src "libresoc.v:186523.9-186523.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12370 1'0
+ assign $1\q_int$next[0:0]$12182 1'0
case
- assign $1\q_int$next[0:0]$12370 \$5
+ assign $1\q_int$next[0:0]$12182 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12369
+ update \q_int$next $0\q_int$next[0:0]$12181
end
- connect \$9 $and$libresoc.v:187568$12359_Y
- connect \$11 $or$libresoc.v:187569$12360_Y
- connect \$13 $not$libresoc.v:187570$12361_Y
- connect \$15 $or$libresoc.v:187571$12362_Y
- connect \$1 $not$libresoc.v:187572$12363_Y
- connect \$3 $and$libresoc.v:187573$12364_Y
- connect \$5 $or$libresoc.v:187574$12365_Y
- connect \$7 $not$libresoc.v:187575$12366_Y
+ connect \$9 $and$libresoc.v:186512$12171_Y
+ connect \$11 $or$libresoc.v:186513$12172_Y
+ connect \$13 $not$libresoc.v:186514$12173_Y
+ connect \$15 $or$libresoc.v:186515$12174_Y
+ connect \$1 $not$libresoc.v:186516$12175_Y
+ connect \$3 $and$libresoc.v:186517$12176_Y
+ connect \$5 $or$libresoc.v:186518$12177_Y
+ connect \$7 $not$libresoc.v:186519$12178_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187594.1-187652.10"
+attribute \src "libresoc.v:186538.1-186596.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l"
attribute \generator "nMigen"
module \rst_l$58
- attribute \src "libresoc.v:187595.7-187595.20"
+ attribute \src "libresoc.v:186539.7-186539.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187640.3-187648.6"
- wire $0\q_int$next[0:0]$12383
- attribute \src "libresoc.v:187638.3-187639.27"
+ attribute \src "libresoc.v:186584.3-186592.6"
+ wire $0\q_int$next[0:0]$12195
+ attribute \src "libresoc.v:186582.3-186583.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187640.3-187648.6"
- wire $1\q_int$next[0:0]$12384
- attribute \src "libresoc.v:187617.7-187617.19"
+ attribute \src "libresoc.v:186584.3-186592.6"
+ wire $1\q_int$next[0:0]$12196
+ attribute \src "libresoc.v:186561.7-186561.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187630.17-187630.96"
- wire $and$libresoc.v:187630$12373_Y
- attribute \src "libresoc.v:187635.17-187635.96"
- wire $and$libresoc.v:187635$12378_Y
- attribute \src "libresoc.v:187632.18-187632.93"
- wire $not$libresoc.v:187632$12375_Y
- attribute \src "libresoc.v:187634.17-187634.92"
- wire $not$libresoc.v:187634$12377_Y
- attribute \src "libresoc.v:187637.17-187637.92"
- wire $not$libresoc.v:187637$12380_Y
- attribute \src "libresoc.v:187631.18-187631.98"
- wire $or$libresoc.v:187631$12374_Y
- attribute \src "libresoc.v:187633.18-187633.99"
- wire $or$libresoc.v:187633$12376_Y
- attribute \src "libresoc.v:187636.17-187636.97"
- wire $or$libresoc.v:187636$12379_Y
+ attribute \src "libresoc.v:186574.17-186574.96"
+ wire $and$libresoc.v:186574$12185_Y
+ attribute \src "libresoc.v:186579.17-186579.96"
+ wire $and$libresoc.v:186579$12190_Y
+ attribute \src "libresoc.v:186576.18-186576.93"
+ wire $not$libresoc.v:186576$12187_Y
+ attribute \src "libresoc.v:186578.17-186578.92"
+ wire $not$libresoc.v:186578$12189_Y
+ attribute \src "libresoc.v:186581.17-186581.92"
+ wire $not$libresoc.v:186581$12192_Y
+ attribute \src "libresoc.v:186575.18-186575.98"
+ wire $or$libresoc.v:186575$12186_Y
+ attribute \src "libresoc.v:186577.18-186577.99"
+ wire $or$libresoc.v:186577$12188_Y
+ attribute \src "libresoc.v:186580.17-186580.97"
+ wire $or$libresoc.v:186580$12191_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187595.7-187595.15"
+ attribute \src "libresoc.v:186539.7-186539.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187630$12373
+ cell $and $and$libresoc.v:186574$12185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187630$12373_Y
+ connect \Y $and$libresoc.v:186574$12185_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187635$12378
+ cell $and $and$libresoc.v:186579$12190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187635$12378_Y
+ connect \Y $and$libresoc.v:186579$12190_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187632$12375
+ cell $not $not$libresoc.v:186576$12187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187632$12375_Y
+ connect \Y $not$libresoc.v:186576$12187_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187634$12377
+ cell $not $not$libresoc.v:186578$12189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187634$12377_Y
+ connect \Y $not$libresoc.v:186578$12189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187637$12380
+ cell $not $not$libresoc.v:186581$12192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187637$12380_Y
+ connect \Y $not$libresoc.v:186581$12192_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187631$12374
+ cell $or $or$libresoc.v:186575$12186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187631$12374_Y
+ connect \Y $or$libresoc.v:186575$12186_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187633$12376
+ cell $or $or$libresoc.v:186577$12188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187633$12376_Y
+ connect \Y $or$libresoc.v:186577$12188_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187636$12379
+ cell $or $or$libresoc.v:186580$12191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187636$12379_Y
+ connect \Y $or$libresoc.v:186580$12191_Y
end
- attribute \src "libresoc.v:187595.7-187595.20"
- process $proc$libresoc.v:187595$12385
+ attribute \src "libresoc.v:186539.7-186539.20"
+ process $proc$libresoc.v:186539$12197
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187617.7-187617.19"
- process $proc$libresoc.v:187617$12386
+ attribute \src "libresoc.v:186561.7-186561.19"
+ process $proc$libresoc.v:186561$12198
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187638.3-187639.27"
- process $proc$libresoc.v:187638$12381
+ attribute \src "libresoc.v:186582.3-186583.27"
+ process $proc$libresoc.v:186582$12193
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187640.3-187648.6"
- process $proc$libresoc.v:187640$12382
+ attribute \src "libresoc.v:186584.3-186592.6"
+ process $proc$libresoc.v:186584$12194
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12383 $1\q_int$next[0:0]$12384
- attribute \src "libresoc.v:187641.5-187641.29"
+ assign $0\q_int$next[0:0]$12195 $1\q_int$next[0:0]$12196
+ attribute \src "libresoc.v:186585.5-186585.29"
switch \initial
- attribute \src "libresoc.v:187641.9-187641.17"
+ attribute \src "libresoc.v:186585.9-186585.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12384 1'0
+ assign $1\q_int$next[0:0]$12196 1'0
case
- assign $1\q_int$next[0:0]$12384 \$5
+ assign $1\q_int$next[0:0]$12196 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12383
+ update \q_int$next $0\q_int$next[0:0]$12195
end
- connect \$9 $and$libresoc.v:187630$12373_Y
- connect \$11 $or$libresoc.v:187631$12374_Y
- connect \$13 $not$libresoc.v:187632$12375_Y
- connect \$15 $or$libresoc.v:187633$12376_Y
- connect \$1 $not$libresoc.v:187634$12377_Y
- connect \$3 $and$libresoc.v:187635$12378_Y
- connect \$5 $or$libresoc.v:187636$12379_Y
- connect \$7 $not$libresoc.v:187637$12380_Y
+ connect \$9 $and$libresoc.v:186574$12185_Y
+ connect \$11 $or$libresoc.v:186575$12186_Y
+ connect \$13 $not$libresoc.v:186576$12187_Y
+ connect \$15 $or$libresoc.v:186577$12188_Y
+ connect \$1 $not$libresoc.v:186578$12189_Y
+ connect \$3 $and$libresoc.v:186579$12190_Y
+ connect \$5 $or$libresoc.v:186580$12191_Y
+ connect \$7 $not$libresoc.v:186581$12192_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187656.1-187714.10"
+attribute \src "libresoc.v:186600.1-186658.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l"
attribute \generator "nMigen"
module \rst_l$70
- attribute \src "libresoc.v:187657.7-187657.20"
+ attribute \src "libresoc.v:186601.7-186601.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187702.3-187710.6"
- wire $0\q_int$next[0:0]$12397
- attribute \src "libresoc.v:187700.3-187701.27"
+ attribute \src "libresoc.v:186646.3-186654.6"
+ wire $0\q_int$next[0:0]$12209
+ attribute \src "libresoc.v:186644.3-186645.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187702.3-187710.6"
- wire $1\q_int$next[0:0]$12398
- attribute \src "libresoc.v:187679.7-187679.19"
+ attribute \src "libresoc.v:186646.3-186654.6"
+ wire $1\q_int$next[0:0]$12210
+ attribute \src "libresoc.v:186623.7-186623.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187692.17-187692.96"
- wire $and$libresoc.v:187692$12387_Y
- attribute \src "libresoc.v:187697.17-187697.96"
- wire $and$libresoc.v:187697$12392_Y
- attribute \src "libresoc.v:187694.18-187694.93"
- wire $not$libresoc.v:187694$12389_Y
- attribute \src "libresoc.v:187696.17-187696.92"
- wire $not$libresoc.v:187696$12391_Y
- attribute \src "libresoc.v:187699.17-187699.92"
- wire $not$libresoc.v:187699$12394_Y
- attribute \src "libresoc.v:187693.18-187693.98"
- wire $or$libresoc.v:187693$12388_Y
- attribute \src "libresoc.v:187695.18-187695.99"
- wire $or$libresoc.v:187695$12390_Y
- attribute \src "libresoc.v:187698.17-187698.97"
- wire $or$libresoc.v:187698$12393_Y
+ attribute \src "libresoc.v:186636.17-186636.96"
+ wire $and$libresoc.v:186636$12199_Y
+ attribute \src "libresoc.v:186641.17-186641.96"
+ wire $and$libresoc.v:186641$12204_Y
+ attribute \src "libresoc.v:186638.18-186638.93"
+ wire $not$libresoc.v:186638$12201_Y
+ attribute \src "libresoc.v:186640.17-186640.92"
+ wire $not$libresoc.v:186640$12203_Y
+ attribute \src "libresoc.v:186643.17-186643.92"
+ wire $not$libresoc.v:186643$12206_Y
+ attribute \src "libresoc.v:186637.18-186637.98"
+ wire $or$libresoc.v:186637$12200_Y
+ attribute \src "libresoc.v:186639.18-186639.99"
+ wire $or$libresoc.v:186639$12202_Y
+ attribute \src "libresoc.v:186642.17-186642.97"
+ wire $or$libresoc.v:186642$12205_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187657.7-187657.15"
+ attribute \src "libresoc.v:186601.7-186601.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187692$12387
+ cell $and $and$libresoc.v:186636$12199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187692$12387_Y
+ connect \Y $and$libresoc.v:186636$12199_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187697$12392
+ cell $and $and$libresoc.v:186641$12204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187697$12392_Y
+ connect \Y $and$libresoc.v:186641$12204_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187694$12389
+ cell $not $not$libresoc.v:186638$12201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187694$12389_Y
+ connect \Y $not$libresoc.v:186638$12201_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187696$12391
+ cell $not $not$libresoc.v:186640$12203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187696$12391_Y
+ connect \Y $not$libresoc.v:186640$12203_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187699$12394
+ cell $not $not$libresoc.v:186643$12206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187699$12394_Y
+ connect \Y $not$libresoc.v:186643$12206_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187693$12388
+ cell $or $or$libresoc.v:186637$12200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187693$12388_Y
+ connect \Y $or$libresoc.v:186637$12200_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187695$12390
+ cell $or $or$libresoc.v:186639$12202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187695$12390_Y
+ connect \Y $or$libresoc.v:186639$12202_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187698$12393
+ cell $or $or$libresoc.v:186642$12205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187698$12393_Y
+ connect \Y $or$libresoc.v:186642$12205_Y
end
- attribute \src "libresoc.v:187657.7-187657.20"
- process $proc$libresoc.v:187657$12399
+ attribute \src "libresoc.v:186601.7-186601.20"
+ process $proc$libresoc.v:186601$12211
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187679.7-187679.19"
- process $proc$libresoc.v:187679$12400
+ attribute \src "libresoc.v:186623.7-186623.19"
+ process $proc$libresoc.v:186623$12212
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187700.3-187701.27"
- process $proc$libresoc.v:187700$12395
+ attribute \src "libresoc.v:186644.3-186645.27"
+ process $proc$libresoc.v:186644$12207
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187702.3-187710.6"
- process $proc$libresoc.v:187702$12396
+ attribute \src "libresoc.v:186646.3-186654.6"
+ process $proc$libresoc.v:186646$12208
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12397 $1\q_int$next[0:0]$12398
- attribute \src "libresoc.v:187703.5-187703.29"
+ assign $0\q_int$next[0:0]$12209 $1\q_int$next[0:0]$12210
+ attribute \src "libresoc.v:186647.5-186647.29"
switch \initial
- attribute \src "libresoc.v:187703.9-187703.17"
+ attribute \src "libresoc.v:186647.9-186647.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12398 1'0
+ assign $1\q_int$next[0:0]$12210 1'0
case
- assign $1\q_int$next[0:0]$12398 \$5
+ assign $1\q_int$next[0:0]$12210 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12397
+ update \q_int$next $0\q_int$next[0:0]$12209
end
- connect \$9 $and$libresoc.v:187692$12387_Y
- connect \$11 $or$libresoc.v:187693$12388_Y
- connect \$13 $not$libresoc.v:187694$12389_Y
- connect \$15 $or$libresoc.v:187695$12390_Y
- connect \$1 $not$libresoc.v:187696$12391_Y
- connect \$3 $and$libresoc.v:187697$12392_Y
- connect \$5 $or$libresoc.v:187698$12393_Y
- connect \$7 $not$libresoc.v:187699$12394_Y
+ connect \$9 $and$libresoc.v:186636$12199_Y
+ connect \$11 $or$libresoc.v:186637$12200_Y
+ connect \$13 $not$libresoc.v:186638$12201_Y
+ connect \$15 $or$libresoc.v:186639$12202_Y
+ connect \$1 $not$libresoc.v:186640$12203_Y
+ connect \$3 $and$libresoc.v:186641$12204_Y
+ connect \$5 $or$libresoc.v:186642$12205_Y
+ connect \$7 $not$libresoc.v:186643$12206_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187718.1-187776.10"
+attribute \src "libresoc.v:186662.1-186720.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l"
attribute \generator "nMigen"
module \rst_l$87
- attribute \src "libresoc.v:187719.7-187719.20"
+ attribute \src "libresoc.v:186663.7-186663.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187764.3-187772.6"
- wire $0\q_int$next[0:0]$12411
- attribute \src "libresoc.v:187762.3-187763.27"
+ attribute \src "libresoc.v:186708.3-186716.6"
+ wire $0\q_int$next[0:0]$12223
+ attribute \src "libresoc.v:186706.3-186707.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:187764.3-187772.6"
- wire $1\q_int$next[0:0]$12412
- attribute \src "libresoc.v:187741.7-187741.19"
+ attribute \src "libresoc.v:186708.3-186716.6"
+ wire $1\q_int$next[0:0]$12224
+ attribute \src "libresoc.v:186685.7-186685.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:187754.17-187754.96"
- wire $and$libresoc.v:187754$12401_Y
- attribute \src "libresoc.v:187759.17-187759.96"
- wire $and$libresoc.v:187759$12406_Y
- attribute \src "libresoc.v:187756.18-187756.93"
- wire $not$libresoc.v:187756$12403_Y
- attribute \src "libresoc.v:187758.17-187758.92"
- wire $not$libresoc.v:187758$12405_Y
- attribute \src "libresoc.v:187761.17-187761.92"
- wire $not$libresoc.v:187761$12408_Y
- attribute \src "libresoc.v:187755.18-187755.98"
- wire $or$libresoc.v:187755$12402_Y
- attribute \src "libresoc.v:187757.18-187757.99"
- wire $or$libresoc.v:187757$12404_Y
- attribute \src "libresoc.v:187760.17-187760.97"
- wire $or$libresoc.v:187760$12407_Y
+ attribute \src "libresoc.v:186698.17-186698.96"
+ wire $and$libresoc.v:186698$12213_Y
+ attribute \src "libresoc.v:186703.17-186703.96"
+ wire $and$libresoc.v:186703$12218_Y
+ attribute \src "libresoc.v:186700.18-186700.93"
+ wire $not$libresoc.v:186700$12215_Y
+ attribute \src "libresoc.v:186702.17-186702.92"
+ wire $not$libresoc.v:186702$12217_Y
+ attribute \src "libresoc.v:186705.17-186705.92"
+ wire $not$libresoc.v:186705$12220_Y
+ attribute \src "libresoc.v:186699.18-186699.98"
+ wire $or$libresoc.v:186699$12214_Y
+ attribute \src "libresoc.v:186701.18-186701.99"
+ wire $or$libresoc.v:186701$12216_Y
+ attribute \src "libresoc.v:186704.17-186704.97"
+ wire $or$libresoc.v:186704$12219_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:187719.7-187719.15"
+ attribute \src "libresoc.v:186663.7-186663.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:187754$12401
+ cell $and $and$libresoc.v:186698$12213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:187754$12401_Y
+ connect \Y $and$libresoc.v:186698$12213_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:187759$12406
+ cell $and $and$libresoc.v:186703$12218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:187759$12406_Y
+ connect \Y $and$libresoc.v:186703$12218_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:187756$12403
+ cell $not $not$libresoc.v:186700$12215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:187756$12403_Y
+ connect \Y $not$libresoc.v:186700$12215_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:187758$12405
+ cell $not $not$libresoc.v:186702$12217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187758$12405_Y
+ connect \Y $not$libresoc.v:186702$12217_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:187761$12408
+ cell $not $not$libresoc.v:186705$12220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:187761$12408_Y
+ connect \Y $not$libresoc.v:186705$12220_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:187755$12402
+ cell $or $or$libresoc.v:186699$12214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:187755$12402_Y
+ connect \Y $or$libresoc.v:186699$12214_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:187757$12404
+ cell $or $or$libresoc.v:186701$12216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:187757$12404_Y
+ connect \Y $or$libresoc.v:186701$12216_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:187760$12407
+ cell $or $or$libresoc.v:186704$12219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:187760$12407_Y
+ connect \Y $or$libresoc.v:186704$12219_Y
end
- attribute \src "libresoc.v:187719.7-187719.20"
- process $proc$libresoc.v:187719$12413
+ attribute \src "libresoc.v:186663.7-186663.20"
+ process $proc$libresoc.v:186663$12225
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187741.7-187741.19"
- process $proc$libresoc.v:187741$12414
+ attribute \src "libresoc.v:186685.7-186685.19"
+ process $proc$libresoc.v:186685$12226
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:187762.3-187763.27"
- process $proc$libresoc.v:187762$12409
+ attribute \src "libresoc.v:186706.3-186707.27"
+ process $proc$libresoc.v:186706$12221
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:187764.3-187772.6"
- process $proc$libresoc.v:187764$12410
+ attribute \src "libresoc.v:186708.3-186716.6"
+ process $proc$libresoc.v:186708$12222
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12411 $1\q_int$next[0:0]$12412
- attribute \src "libresoc.v:187765.5-187765.29"
+ assign $0\q_int$next[0:0]$12223 $1\q_int$next[0:0]$12224
+ attribute \src "libresoc.v:186709.5-186709.29"
switch \initial
- attribute \src "libresoc.v:187765.9-187765.17"
+ attribute \src "libresoc.v:186709.9-186709.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12412 1'0
+ assign $1\q_int$next[0:0]$12224 1'0
case
- assign $1\q_int$next[0:0]$12412 \$5
+ assign $1\q_int$next[0:0]$12224 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12411
+ update \q_int$next $0\q_int$next[0:0]$12223
end
- connect \$9 $and$libresoc.v:187754$12401_Y
- connect \$11 $or$libresoc.v:187755$12402_Y
- connect \$13 $not$libresoc.v:187756$12403_Y
- connect \$15 $or$libresoc.v:187757$12404_Y
- connect \$1 $not$libresoc.v:187758$12405_Y
- connect \$3 $and$libresoc.v:187759$12406_Y
- connect \$5 $or$libresoc.v:187760$12407_Y
- connect \$7 $not$libresoc.v:187761$12408_Y
+ connect \$9 $and$libresoc.v:186698$12213_Y
+ connect \$11 $or$libresoc.v:186699$12214_Y
+ connect \$13 $not$libresoc.v:186700$12215_Y
+ connect \$15 $or$libresoc.v:186701$12216_Y
+ connect \$1 $not$libresoc.v:186702$12217_Y
+ connect \$3 $and$libresoc.v:186703$12218_Y
+ connect \$5 $or$libresoc.v:186704$12219_Y
+ connect \$7 $not$libresoc.v:186705$12220_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:187780.1-188189.10"
+attribute \src "libresoc.v:186724.1-187133.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage"
attribute \generator "nMigen"
module \setup_stage
- attribute \src "libresoc.v:188147.3-188172.6"
+ attribute \src "libresoc.v:187091.3-187116.6"
wire width 128 $0\dividend[127:0]
- attribute \src "libresoc.v:187781.7-187781.20"
+ attribute \src "libresoc.v:186725.7-186725.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:188147.3-188172.6"
+ attribute \src "libresoc.v:187091.3-187116.6"
wire width 128 $1\dividend[127:0]
- attribute \src "libresoc.v:188147.3-188172.6"
+ attribute \src "libresoc.v:187091.3-187116.6"
wire width 128 $2\dividend[127:0]
- attribute \src "libresoc.v:188126.18-188126.122"
- wire $and$libresoc.v:188126$12416_Y
- attribute \src "libresoc.v:188128.18-188128.122"
- wire $and$libresoc.v:188128$12418_Y
- attribute \src "libresoc.v:188137.18-188137.105"
- wire $and$libresoc.v:188137$12431_Y
- attribute \src "libresoc.v:188140.18-188140.105"
- wire $and$libresoc.v:188140$12434_Y
- attribute \src "libresoc.v:188136.18-188136.123"
- wire $eq$libresoc.v:188136$12430_Y
- attribute \src "libresoc.v:188139.18-188139.123"
- wire $eq$libresoc.v:188139$12433_Y
- attribute \src "libresoc.v:188142.18-188142.117"
- wire $eq$libresoc.v:188142$12436_Y
- attribute \src "libresoc.v:188129.18-188129.97"
- wire width 65 $extend$libresoc.v:188129$12419_Y
- attribute \src "libresoc.v:188130.18-188130.91"
- wire width 65 $extend$libresoc.v:188130$12421_Y
- attribute \src "libresoc.v:188132.18-188132.97"
- wire width 65 $extend$libresoc.v:188132$12424_Y
- attribute \src "libresoc.v:188133.18-188133.91"
- wire width 65 $extend$libresoc.v:188133$12426_Y
- attribute \src "libresoc.v:188145.18-188145.99"
- wire width 128 $extend$libresoc.v:188145$12439_Y
- attribute \src "libresoc.v:188135.18-188135.112"
- wire $ge$libresoc.v:188135$12429_Y
- attribute \src "libresoc.v:188138.18-188138.124"
- wire $ge$libresoc.v:188138$12432_Y
- attribute \src "libresoc.v:188129.18-188129.97"
- wire width 65 $neg$libresoc.v:188129$12420_Y
- attribute \src "libresoc.v:188132.18-188132.97"
- wire width 65 $neg$libresoc.v:188132$12425_Y
- attribute \src "libresoc.v:188130.18-188130.91"
- wire width 65 $pos$libresoc.v:188130$12422_Y
- attribute \src "libresoc.v:188133.18-188133.91"
- wire width 65 $pos$libresoc.v:188133$12427_Y
- attribute \src "libresoc.v:188145.18-188145.99"
- wire width 128 $pos$libresoc.v:188145$12440_Y
- attribute \src "libresoc.v:188144.18-188144.117"
- wire width 95 $sshl$libresoc.v:188144$12438_Y
- attribute \src "libresoc.v:188146.18-188146.111"
- wire width 191 $sshl$libresoc.v:188146$12441_Y
- attribute \src "libresoc.v:188125.18-188125.131"
- wire $ternary$libresoc.v:188125$12415_Y
- attribute \src "libresoc.v:188127.18-188127.131"
- wire $ternary$libresoc.v:188127$12417_Y
- attribute \src "libresoc.v:188131.18-188131.119"
- wire width 65 $ternary$libresoc.v:188131$12423_Y
- attribute \src "libresoc.v:188134.18-188134.120"
- wire width 65 $ternary$libresoc.v:188134$12428_Y
- attribute \src "libresoc.v:188141.18-188141.130"
- wire width 32 $ternary$libresoc.v:188141$12435_Y
- attribute \src "libresoc.v:188143.18-188143.131"
- wire width 32 $ternary$libresoc.v:188143$12437_Y
+ attribute \src "libresoc.v:187070.18-187070.122"
+ wire $and$libresoc.v:187070$12228_Y
+ attribute \src "libresoc.v:187072.18-187072.122"
+ wire $and$libresoc.v:187072$12230_Y
+ attribute \src "libresoc.v:187081.18-187081.105"
+ wire $and$libresoc.v:187081$12243_Y
+ attribute \src "libresoc.v:187084.18-187084.105"
+ wire $and$libresoc.v:187084$12246_Y
+ attribute \src "libresoc.v:187080.18-187080.123"
+ wire $eq$libresoc.v:187080$12242_Y
+ attribute \src "libresoc.v:187083.18-187083.123"
+ wire $eq$libresoc.v:187083$12245_Y
+ attribute \src "libresoc.v:187086.18-187086.117"
+ wire $eq$libresoc.v:187086$12248_Y
+ attribute \src "libresoc.v:187073.18-187073.97"
+ wire width 65 $extend$libresoc.v:187073$12231_Y
+ attribute \src "libresoc.v:187074.18-187074.91"
+ wire width 65 $extend$libresoc.v:187074$12233_Y
+ attribute \src "libresoc.v:187076.18-187076.97"
+ wire width 65 $extend$libresoc.v:187076$12236_Y
+ attribute \src "libresoc.v:187077.18-187077.91"
+ wire width 65 $extend$libresoc.v:187077$12238_Y
+ attribute \src "libresoc.v:187089.18-187089.99"
+ wire width 128 $extend$libresoc.v:187089$12251_Y
+ attribute \src "libresoc.v:187079.18-187079.112"
+ wire $ge$libresoc.v:187079$12241_Y
+ attribute \src "libresoc.v:187082.18-187082.124"
+ wire $ge$libresoc.v:187082$12244_Y
+ attribute \src "libresoc.v:187073.18-187073.97"
+ wire width 65 $neg$libresoc.v:187073$12232_Y
+ attribute \src "libresoc.v:187076.18-187076.97"
+ wire width 65 $neg$libresoc.v:187076$12237_Y
+ attribute \src "libresoc.v:187074.18-187074.91"
+ wire width 65 $pos$libresoc.v:187074$12234_Y
+ attribute \src "libresoc.v:187077.18-187077.91"
+ wire width 65 $pos$libresoc.v:187077$12239_Y
+ attribute \src "libresoc.v:187089.18-187089.99"
+ wire width 128 $pos$libresoc.v:187089$12252_Y
+ attribute \src "libresoc.v:187088.18-187088.117"
+ wire width 95 $sshl$libresoc.v:187088$12250_Y
+ attribute \src "libresoc.v:187090.18-187090.111"
+ wire width 191 $sshl$libresoc.v:187090$12253_Y
+ attribute \src "libresoc.v:187069.18-187069.131"
+ wire $ternary$libresoc.v:187069$12227_Y
+ attribute \src "libresoc.v:187071.18-187071.131"
+ wire $ternary$libresoc.v:187071$12229_Y
+ attribute \src "libresoc.v:187075.18-187075.119"
+ wire width 65 $ternary$libresoc.v:187075$12235_Y
+ attribute \src "libresoc.v:187078.18-187078.120"
+ wire width 65 $ternary$libresoc.v:187078$12240_Y
+ attribute \src "libresoc.v:187085.18-187085.130"
+ wire width 32 $ternary$libresoc.v:187085$12247_Y
+ attribute \src "libresoc.v:187087.18-187087.131"
+ wire width 32 $ternary$libresoc.v:187087$12249_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
wire \$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
wire output 42 \divisor_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
wire width 64 output 48 \divisor_radicand
- attribute \src "libresoc.v:187781.7-187781.15"
+ attribute \src "libresoc.v:186725.7-186725.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 41 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
- cell $and $and$libresoc.v:188126$12416
+ cell $and $and$libresoc.v:187070$12228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$21
connect \B \logical_op__is_signed
- connect \Y $and$libresoc.v:188126$12416_Y
+ connect \Y $and$libresoc.v:187070$12228_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
- cell $and $and$libresoc.v:188128$12418
+ cell $and $and$libresoc.v:187072$12230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$25
connect \B \logical_op__is_signed
- connect \Y $and$libresoc.v:188128$12418_Y
+ connect \Y $and$libresoc.v:187072$12230_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
- cell $and $and$libresoc.v:188137$12431
+ cell $and $and$libresoc.v:187081$12243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \$45
- connect \Y $and$libresoc.v:188137$12431_Y
+ connect \Y $and$libresoc.v:187081$12243_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
- cell $and $and$libresoc.v:188140$12434
+ cell $and $and$libresoc.v:187084$12246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \$51
- connect \Y $and$libresoc.v:188140$12434_Y
+ connect \Y $and$libresoc.v:187084$12246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
- cell $eq $eq$libresoc.v:188136$12430
+ cell $eq $eq$libresoc.v:187080$12242
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0011110
- connect \Y $eq$libresoc.v:188136$12430_Y
+ connect \Y $eq$libresoc.v:187080$12242_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
- cell $eq $eq$libresoc.v:188139$12433
+ cell $eq $eq$libresoc.v:187083$12245
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0011110
- connect \Y $eq$libresoc.v:188139$12433_Y
+ connect \Y $eq$libresoc.v:187083$12245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67"
- cell $eq $eq$libresoc.v:188142$12436
+ cell $eq $eq$libresoc.v:187086$12248
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \divisor_radicand
connect \B 1'0
- connect \Y $eq$libresoc.v:188142$12436_Y
+ connect \Y $eq$libresoc.v:187086$12248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $pos $extend$libresoc.v:188129$12419
+ cell $pos $extend$libresoc.v:187073$12231
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:188129$12419_Y
+ connect \Y $extend$libresoc.v:187073$12231_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:188130$12421
+ cell $pos $extend$libresoc.v:187074$12233
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:188130$12421_Y
+ connect \Y $extend$libresoc.v:187074$12233_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $pos $extend$libresoc.v:188132$12424
+ cell $pos $extend$libresoc.v:187076$12236
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:188132$12424_Y
+ connect \Y $extend$libresoc.v:187076$12236_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:188133$12426
+ cell $pos $extend$libresoc.v:187077$12238
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:188133$12426_Y
+ connect \Y $extend$libresoc.v:187077$12238_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $pos $extend$libresoc.v:188145$12439
+ cell $pos $extend$libresoc.v:187089$12251
parameter \A_SIGNED 0
parameter \A_WIDTH 95
parameter \Y_WIDTH 128
connect \A \$62
- connect \Y $extend$libresoc.v:188145$12439_Y
+ connect \Y $extend$libresoc.v:187089$12251_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57"
- cell $ge $ge$libresoc.v:188135$12429
+ cell $ge $ge$libresoc.v:187079$12241
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \abs_dend
connect \B \abs_dor
- connect \Y $ge$libresoc.v:188135$12429_Y
+ connect \Y $ge$libresoc.v:187079$12241_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60"
- cell $ge $ge$libresoc.v:188138$12432
+ cell $ge $ge$libresoc.v:187082$12244
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \abs_dend [31:0]
connect \B \abs_dor [31:0]
- connect \Y $ge$libresoc.v:188138$12432_Y
+ connect \Y $ge$libresoc.v:187082$12244_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $neg $neg$libresoc.v:188129$12420
+ cell $neg $neg$libresoc.v:187073$12232
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:188129$12419_Y
- connect \Y $neg$libresoc.v:188129$12420_Y
+ connect \A $extend$libresoc.v:187073$12231_Y
+ connect \Y $neg$libresoc.v:187073$12232_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $neg $neg$libresoc.v:188132$12425
+ cell $neg $neg$libresoc.v:187076$12237
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:188132$12424_Y
- connect \Y $neg$libresoc.v:188132$12425_Y
+ connect \A $extend$libresoc.v:187076$12236_Y
+ connect \Y $neg$libresoc.v:187076$12237_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:188130$12422
+ cell $pos $pos$libresoc.v:187074$12234
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:188130$12421_Y
- connect \Y $pos$libresoc.v:188130$12422_Y
+ connect \A $extend$libresoc.v:187074$12233_Y
+ connect \Y $pos$libresoc.v:187074$12234_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:188133$12427
+ cell $pos $pos$libresoc.v:187077$12239
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:188133$12426_Y
- connect \Y $pos$libresoc.v:188133$12427_Y
+ connect \A $extend$libresoc.v:187077$12238_Y
+ connect \Y $pos$libresoc.v:187077$12239_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $pos $pos$libresoc.v:188145$12440
+ cell $pos $pos$libresoc.v:187089$12252
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \Y_WIDTH 128
- connect \A $extend$libresoc.v:188145$12439_Y
- connect \Y $pos$libresoc.v:188145$12440_Y
+ connect \A $extend$libresoc.v:187089$12251_Y
+ connect \Y $pos$libresoc.v:187089$12252_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $sshl $sshl$libresoc.v:188144$12438
+ cell $sshl $sshl$libresoc.v:187088$12250
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 95
connect \A \abs_dend [31:0]
connect \B 6'100000
- connect \Y $sshl$libresoc.v:188144$12438_Y
+ connect \Y $sshl$libresoc.v:187088$12250_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81"
- cell $sshl $sshl$libresoc.v:188146$12441
+ cell $sshl $sshl$libresoc.v:187090$12253
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 191
connect \A \abs_dend
connect \B 7'1000000
- connect \Y $sshl$libresoc.v:188146$12441_Y
+ connect \Y $sshl$libresoc.v:187090$12253_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
- cell $mux $ternary$libresoc.v:188125$12415
+ cell $mux $ternary$libresoc.v:187069$12227
parameter \WIDTH 1
connect \A \ra [63]
connect \B \ra [31]
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:188125$12415_Y
+ connect \Y $ternary$libresoc.v:187069$12227_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
- cell $mux $ternary$libresoc.v:188127$12417
+ cell $mux $ternary$libresoc.v:187071$12229
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:188127$12417_Y
+ connect \Y $ternary$libresoc.v:187071$12229_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $mux $ternary$libresoc.v:188131$12423
+ cell $mux $ternary$libresoc.v:187075$12235
parameter \WIDTH 65
connect \A \$32
connect \B \$30
connect \S \divisor_neg
- connect \Y $ternary$libresoc.v:188131$12423_Y
+ connect \Y $ternary$libresoc.v:187075$12235_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $mux $ternary$libresoc.v:188134$12428
+ cell $mux $ternary$libresoc.v:187078$12240
parameter \WIDTH 65
connect \A \$39
connect \B \$37
connect \S \dividend_neg
- connect \Y $ternary$libresoc.v:188134$12428_Y
+ connect \Y $ternary$libresoc.v:187078$12240_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:188141$12435
+ cell $mux $ternary$libresoc.v:187085$12247
parameter \WIDTH 32
connect \A \abs_dor [63:32]
connect \B 0
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:188141$12435_Y
+ connect \Y $ternary$libresoc.v:187085$12247_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:188143$12437
+ cell $mux $ternary$libresoc.v:187087$12249
parameter \WIDTH 32
connect \A \abs_dend [63:32]
connect \B 0
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:188143$12437_Y
+ connect \Y $ternary$libresoc.v:187087$12249_Y
end
- attribute \src "libresoc.v:187781.7-187781.20"
- process $proc$libresoc.v:187781$12443
+ attribute \src "libresoc.v:186725.7-186725.20"
+ process $proc$libresoc.v:186725$12255
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:188147.3-188172.6"
- process $proc$libresoc.v:188147$12442
+ attribute \src "libresoc.v:187091.3-187116.6"
+ process $proc$libresoc.v:187091$12254
assign { } { }
assign { } { }
assign $0\dividend[127:0] $1\dividend[127:0]
- attribute \src "libresoc.v:188148.5-188148.29"
+ attribute \src "libresoc.v:187092.5-187092.29"
switch \initial
- attribute \src "libresoc.v:188148.9-188148.17"
+ attribute \src "libresoc.v:187092.9-187092.17"
case 1'1
case
end
sync always
update \dividend $0\dividend[127:0]
end
- connect \$21 $ternary$libresoc.v:188125$12415_Y
- connect \$23 $and$libresoc.v:188126$12416_Y
- connect \$25 $ternary$libresoc.v:188127$12417_Y
- connect \$27 $and$libresoc.v:188128$12418_Y
- connect \$30 $neg$libresoc.v:188129$12420_Y
- connect \$32 $pos$libresoc.v:188130$12422_Y
- connect \$34 $ternary$libresoc.v:188131$12423_Y
- connect \$37 $neg$libresoc.v:188132$12425_Y
- connect \$39 $pos$libresoc.v:188133$12427_Y
- connect \$41 $ternary$libresoc.v:188134$12428_Y
- connect \$43 $ge$libresoc.v:188135$12429_Y
- connect \$45 $eq$libresoc.v:188136$12430_Y
- connect \$47 $and$libresoc.v:188137$12431_Y
- connect \$49 $ge$libresoc.v:188138$12432_Y
- connect \$51 $eq$libresoc.v:188139$12433_Y
- connect \$53 $and$libresoc.v:188140$12434_Y
- connect \$55 $ternary$libresoc.v:188141$12435_Y
- connect \$57 $eq$libresoc.v:188142$12436_Y
- connect \$59 $ternary$libresoc.v:188143$12437_Y
- connect \$62 $sshl$libresoc.v:188144$12438_Y
- connect \$61 $pos$libresoc.v:188145$12440_Y
- connect \$66 $sshl$libresoc.v:188146$12441_Y
+ connect \$21 $ternary$libresoc.v:187069$12227_Y
+ connect \$23 $and$libresoc.v:187070$12228_Y
+ connect \$25 $ternary$libresoc.v:187071$12229_Y
+ connect \$27 $and$libresoc.v:187072$12230_Y
+ connect \$30 $neg$libresoc.v:187073$12232_Y
+ connect \$32 $pos$libresoc.v:187074$12234_Y
+ connect \$34 $ternary$libresoc.v:187075$12235_Y
+ connect \$37 $neg$libresoc.v:187076$12237_Y
+ connect \$39 $pos$libresoc.v:187077$12239_Y
+ connect \$41 $ternary$libresoc.v:187078$12240_Y
+ connect \$43 $ge$libresoc.v:187079$12241_Y
+ connect \$45 $eq$libresoc.v:187080$12242_Y
+ connect \$47 $and$libresoc.v:187081$12243_Y
+ connect \$49 $ge$libresoc.v:187082$12244_Y
+ connect \$51 $eq$libresoc.v:187083$12245_Y
+ connect \$53 $and$libresoc.v:187084$12246_Y
+ connect \$55 $ternary$libresoc.v:187085$12247_Y
+ connect \$57 $eq$libresoc.v:187086$12248_Y
+ connect \$59 $ternary$libresoc.v:187087$12249_Y
+ connect \$62 $sshl$libresoc.v:187088$12250_Y
+ connect \$61 $pos$libresoc.v:187089$12252_Y
+ connect \$66 $sshl$libresoc.v:187090$12253_Y
connect \$29 \$34
connect \$36 \$41
connect \$65 \$66
connect \dividend_neg \$23
connect \operation 2'01
end
-attribute \src "libresoc.v:188193.1-189400.10"
+attribute \src "libresoc.v:187137.1-188344.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0"
attribute \generator "nMigen"
module \shiftrot0
- attribute \src "libresoc.v:188971.3-188972.25"
+ attribute \src "libresoc.v:187915.3-187916.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:188969.3-188970.46"
+ attribute \src "libresoc.v:187913.3-187914.46"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:189320.3-189328.6"
- wire $0\alu_l_r_alu$next[0:0]$12661
- attribute \src "libresoc.v:188887.3-188888.39"
+ attribute \src "libresoc.v:188264.3-188272.6"
+ wire $0\alu_l_r_alu$next[0:0]$12473
+ attribute \src "libresoc.v:187831.3-187832.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578
- attribute \src "libresoc.v:188915.3-188916.75"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390
+ attribute \src "libresoc.v:187859.3-187860.75"
wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579
- attribute \src "libresoc.v:188917.3-188918.89"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391
+ attribute \src "libresoc.v:187861.3-187862.89"
wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580
- attribute \src "libresoc.v:188919.3-188920.85"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392
+ attribute \src "libresoc.v:187863.3-187864.85"
wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581
- attribute \src "libresoc.v:188933.3-188934.83"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393
+ attribute \src "libresoc.v:187877.3-187878.83"
wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582
- attribute \src "libresoc.v:188937.3-188938.77"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394
+ attribute \src "libresoc.v:187881.3-187882.77"
wire $0\alu_shift_rot0_sr_op__input_cr[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583
- attribute \src "libresoc.v:188945.3-188946.69"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395
+ attribute \src "libresoc.v:187889.3-187890.69"
wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584
- attribute \src "libresoc.v:188913.3-188914.79"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396
+ attribute \src "libresoc.v:187857.3-187858.79"
wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585
- attribute \src "libresoc.v:188931.3-188932.79"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397
+ attribute \src "libresoc.v:187875.3-187876.79"
wire $0\alu_shift_rot0_sr_op__invert_in[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586
- attribute \src "libresoc.v:188941.3-188942.77"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398
+ attribute \src "libresoc.v:187885.3-187886.77"
wire $0\alu_shift_rot0_sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587
- attribute \src "libresoc.v:188943.3-188944.79"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399
+ attribute \src "libresoc.v:187887.3-187888.79"
wire $0\alu_shift_rot0_sr_op__is_signed[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588
- attribute \src "libresoc.v:188925.3-188926.73"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400
+ attribute \src "libresoc.v:187869.3-187870.73"
wire $0\alu_shift_rot0_sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589
- attribute \src "libresoc.v:188927.3-188928.73"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401
+ attribute \src "libresoc.v:187871.3-187872.73"
wire $0\alu_shift_rot0_sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590
- attribute \src "libresoc.v:188935.3-188936.85"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402
+ attribute \src "libresoc.v:187879.3-187880.85"
wire $0\alu_shift_rot0_sr_op__output_carry[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591
- attribute \src "libresoc.v:188939.3-188940.79"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403
+ attribute \src "libresoc.v:187883.3-187884.79"
wire $0\alu_shift_rot0_sr_op__output_cr[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592
- attribute \src "libresoc.v:188923.3-188924.73"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404
+ attribute \src "libresoc.v:187867.3-187868.73"
wire $0\alu_shift_rot0_sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593
- attribute \src "libresoc.v:188921.3-188922.73"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405
+ attribute \src "libresoc.v:187865.3-187866.73"
wire $0\alu_shift_rot0_sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594
- attribute \src "libresoc.v:188929.3-188930.79"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406
+ attribute \src "libresoc.v:187873.3-187874.79"
wire $0\alu_shift_rot0_sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:189311.3-189319.6"
- wire $0\alui_l_r_alui$next[0:0]$12658
- attribute \src "libresoc.v:188889.3-188890.43"
+ attribute \src "libresoc.v:188255.3-188263.6"
+ wire $0\alui_l_r_alui$next[0:0]$12470
+ attribute \src "libresoc.v:187833.3-187834.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:189195.3-189216.6"
- wire width 64 $0\data_r0__o$next[63:0]$12619
- attribute \src "libresoc.v:188909.3-188910.37"
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire width 64 $0\data_r0__o$next[63:0]$12431
+ attribute \src "libresoc.v:187853.3-187854.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:189195.3-189216.6"
- wire $0\data_r0__o_ok$next[0:0]$12620
- attribute \src "libresoc.v:188911.3-188912.43"
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire $0\data_r0__o_ok$next[0:0]$12432
+ attribute \src "libresoc.v:187855.3-187856.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:189217.3-189238.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$12627
- attribute \src "libresoc.v:188905.3-188906.43"
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$12439
+ attribute \src "libresoc.v:187849.3-187850.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:189217.3-189238.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$12628
- attribute \src "libresoc.v:188907.3-188908.49"
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$12440
+ attribute \src "libresoc.v:187851.3-187852.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:189239.3-189260.6"
- wire width 2 $0\data_r2__xer_ca$next[1:0]$12635
- attribute \src "libresoc.v:188901.3-188902.47"
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire width 2 $0\data_r2__xer_ca$next[1:0]$12447
+ attribute \src "libresoc.v:187845.3-187846.47"
wire width 2 $0\data_r2__xer_ca[1:0]
- attribute \src "libresoc.v:189239.3-189260.6"
- wire $0\data_r2__xer_ca_ok$next[0:0]$12636
- attribute \src "libresoc.v:188903.3-188904.53"
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire $0\data_r2__xer_ca_ok$next[0:0]$12448
+ attribute \src "libresoc.v:187847.3-187848.53"
wire $0\data_r2__xer_ca_ok[0:0]
- attribute \src "libresoc.v:189329.3-189338.6"
+ attribute \src "libresoc.v:188273.3-188282.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:189339.3-189348.6"
+ attribute \src "libresoc.v:188283.3-188292.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:189349.3-189358.6"
+ attribute \src "libresoc.v:188293.3-188302.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:188194.7-188194.20"
+ attribute \src "libresoc.v:187138.7-187138.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:189112.3-189120.6"
- wire $0\opc_l_r_opc$next[0:0]$12563
- attribute \src "libresoc.v:188955.3-188956.39"
+ attribute \src "libresoc.v:188056.3-188064.6"
+ wire $0\opc_l_r_opc$next[0:0]$12375
+ attribute \src "libresoc.v:187899.3-187900.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:189103.3-189111.6"
- wire $0\opc_l_s_opc$next[0:0]$12560
- attribute \src "libresoc.v:188957.3-188958.39"
+ attribute \src "libresoc.v:188047.3-188055.6"
+ wire $0\opc_l_s_opc$next[0:0]$12372
+ attribute \src "libresoc.v:187901.3-187902.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:189359.3-189367.6"
- wire width 3 $0\prev_wr_go$next[2:0]$12667
- attribute \src "libresoc.v:188967.3-188968.37"
+ attribute \src "libresoc.v:188303.3-188311.6"
+ wire width 3 $0\prev_wr_go$next[2:0]$12479
+ attribute \src "libresoc.v:187911.3-187912.37"
wire width 3 $0\prev_wr_go[2:0]
- attribute \src "libresoc.v:189057.3-189066.6"
+ attribute \src "libresoc.v:188001.3-188010.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:189148.3-189156.6"
- wire width 3 $0\req_l_r_req$next[2:0]$12575
- attribute \src "libresoc.v:188947.3-188948.39"
+ attribute \src "libresoc.v:188092.3-188100.6"
+ wire width 3 $0\req_l_r_req$next[2:0]$12387
+ attribute \src "libresoc.v:187891.3-187892.39"
wire width 3 $0\req_l_r_req[2:0]
- attribute \src "libresoc.v:189139.3-189147.6"
- wire width 3 $0\req_l_s_req$next[2:0]$12572
- attribute \src "libresoc.v:188949.3-188950.39"
+ attribute \src "libresoc.v:188083.3-188091.6"
+ wire width 3 $0\req_l_s_req$next[2:0]$12384
+ attribute \src "libresoc.v:187893.3-187894.39"
wire width 3 $0\req_l_s_req[2:0]
- attribute \src "libresoc.v:189076.3-189084.6"
- wire $0\rok_l_r_rdok$next[0:0]$12551
- attribute \src "libresoc.v:188963.3-188964.41"
+ attribute \src "libresoc.v:188020.3-188028.6"
+ wire $0\rok_l_r_rdok$next[0:0]$12363
+ attribute \src "libresoc.v:187907.3-187908.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:189067.3-189075.6"
- wire $0\rok_l_s_rdok$next[0:0]$12548
- attribute \src "libresoc.v:188965.3-188966.41"
+ attribute \src "libresoc.v:188011.3-188019.6"
+ wire $0\rok_l_s_rdok$next[0:0]$12360
+ attribute \src "libresoc.v:187909.3-187910.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:189094.3-189102.6"
- wire $0\rst_l_r_rst$next[0:0]$12557
- attribute \src "libresoc.v:188959.3-188960.39"
+ attribute \src "libresoc.v:188038.3-188046.6"
+ wire $0\rst_l_r_rst$next[0:0]$12369
+ attribute \src "libresoc.v:187903.3-187904.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:189085.3-189093.6"
- wire $0\rst_l_s_rst$next[0:0]$12554
- attribute \src "libresoc.v:188961.3-188962.39"
+ attribute \src "libresoc.v:188029.3-188037.6"
+ wire $0\rst_l_s_rst$next[0:0]$12366
+ attribute \src "libresoc.v:187905.3-187906.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:189130.3-189138.6"
- wire width 5 $0\src_l_r_src$next[4:0]$12569
- attribute \src "libresoc.v:188951.3-188952.39"
+ attribute \src "libresoc.v:188074.3-188082.6"
+ wire width 5 $0\src_l_r_src$next[4:0]$12381
+ attribute \src "libresoc.v:187895.3-187896.39"
wire width 5 $0\src_l_r_src[4:0]
- attribute \src "libresoc.v:189121.3-189129.6"
- wire width 5 $0\src_l_s_src$next[4:0]$12566
- attribute \src "libresoc.v:188953.3-188954.39"
+ attribute \src "libresoc.v:188065.3-188073.6"
+ wire width 5 $0\src_l_s_src$next[4:0]$12378
+ attribute \src "libresoc.v:187897.3-187898.39"
wire width 5 $0\src_l_s_src[4:0]
- attribute \src "libresoc.v:189261.3-189270.6"
- wire width 64 $0\src_r0$next[63:0]$12643
- attribute \src "libresoc.v:188899.3-188900.29"
+ attribute \src "libresoc.v:188205.3-188214.6"
+ wire width 64 $0\src_r0$next[63:0]$12455
+ attribute \src "libresoc.v:187843.3-187844.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:189271.3-189280.6"
- wire width 64 $0\src_r1$next[63:0]$12646
- attribute \src "libresoc.v:188897.3-188898.29"
+ attribute \src "libresoc.v:188215.3-188224.6"
+ wire width 64 $0\src_r1$next[63:0]$12458
+ attribute \src "libresoc.v:187841.3-187842.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:189281.3-189290.6"
- wire width 64 $0\src_r2$next[63:0]$12649
- attribute \src "libresoc.v:188895.3-188896.29"
+ attribute \src "libresoc.v:188225.3-188234.6"
+ wire width 64 $0\src_r2$next[63:0]$12461
+ attribute \src "libresoc.v:187839.3-187840.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:189291.3-189300.6"
- wire $0\src_r3$next[0:0]$12652
- attribute \src "libresoc.v:188893.3-188894.29"
+ attribute \src "libresoc.v:188235.3-188244.6"
+ wire $0\src_r3$next[0:0]$12464
+ attribute \src "libresoc.v:187837.3-187838.29"
wire $0\src_r3[0:0]
- attribute \src "libresoc.v:189301.3-189310.6"
- wire width 2 $0\src_r4$next[1:0]$12655
- attribute \src "libresoc.v:188891.3-188892.29"
+ attribute \src "libresoc.v:188245.3-188254.6"
+ wire width 2 $0\src_r4$next[1:0]$12467
+ attribute \src "libresoc.v:187835.3-187836.29"
wire width 2 $0\src_r4[1:0]
- attribute \src "libresoc.v:188316.7-188316.24"
+ attribute \src "libresoc.v:187260.7-187260.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:188326.7-188326.26"
+ attribute \src "libresoc.v:187270.7-187270.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:189320.3-189328.6"
- wire $1\alu_l_r_alu$next[0:0]$12662
- attribute \src "libresoc.v:188334.7-188334.25"
+ attribute \src "libresoc.v:188264.3-188272.6"
+ wire $1\alu_l_r_alu$next[0:0]$12474
+ attribute \src "libresoc.v:187278.7-187278.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595
- attribute \src "libresoc.v:188377.14-188377.54"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407
+ attribute \src "libresoc.v:187321.14-187321.54"
wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596
- attribute \src "libresoc.v:188381.14-188381.73"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408
+ attribute \src "libresoc.v:187325.14-187325.73"
wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597
- attribute \src "libresoc.v:188385.7-188385.48"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409
+ attribute \src "libresoc.v:187329.7-187329.48"
wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598
- attribute \src "libresoc.v:188393.13-188393.53"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410
+ attribute \src "libresoc.v:187337.13-187337.53"
wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599
- attribute \src "libresoc.v:188397.7-188397.44"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411
+ attribute \src "libresoc.v:187341.7-187341.44"
wire $1\alu_shift_rot0_sr_op__input_cr[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600
- attribute \src "libresoc.v:188401.14-188401.48"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412
+ attribute \src "libresoc.v:187345.14-187345.48"
wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601
- attribute \src "libresoc.v:188480.13-188480.52"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413
+ attribute \src "libresoc.v:187424.13-187424.52"
wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602
- attribute \src "libresoc.v:188484.7-188484.45"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414
+ attribute \src "libresoc.v:187428.7-187428.45"
wire $1\alu_shift_rot0_sr_op__invert_in[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603
- attribute \src "libresoc.v:188488.7-188488.44"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415
+ attribute \src "libresoc.v:187432.7-187432.44"
wire $1\alu_shift_rot0_sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604
- attribute \src "libresoc.v:188492.7-188492.45"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416
+ attribute \src "libresoc.v:187436.7-187436.45"
wire $1\alu_shift_rot0_sr_op__is_signed[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605
- attribute \src "libresoc.v:188496.7-188496.42"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417
+ attribute \src "libresoc.v:187440.7-187440.42"
wire $1\alu_shift_rot0_sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606
- attribute \src "libresoc.v:188500.7-188500.42"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418
+ attribute \src "libresoc.v:187444.7-187444.42"
wire $1\alu_shift_rot0_sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607
- attribute \src "libresoc.v:188504.7-188504.48"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419
+ attribute \src "libresoc.v:187448.7-187448.48"
wire $1\alu_shift_rot0_sr_op__output_carry[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608
- attribute \src "libresoc.v:188508.7-188508.45"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420
+ attribute \src "libresoc.v:187452.7-187452.45"
wire $1\alu_shift_rot0_sr_op__output_cr[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609
- attribute \src "libresoc.v:188512.7-188512.42"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421
+ attribute \src "libresoc.v:187456.7-187456.42"
wire $1\alu_shift_rot0_sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610
- attribute \src "libresoc.v:188516.7-188516.42"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422
+ attribute \src "libresoc.v:187460.7-187460.42"
wire $1\alu_shift_rot0_sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611
- attribute \src "libresoc.v:188520.7-188520.45"
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423
+ attribute \src "libresoc.v:187464.7-187464.45"
wire $1\alu_shift_rot0_sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:189311.3-189319.6"
- wire $1\alui_l_r_alui$next[0:0]$12659
- attribute \src "libresoc.v:188532.7-188532.27"
+ attribute \src "libresoc.v:188255.3-188263.6"
+ wire $1\alui_l_r_alui$next[0:0]$12471
+ attribute \src "libresoc.v:187476.7-187476.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:189195.3-189216.6"
- wire width 64 $1\data_r0__o$next[63:0]$12621
- attribute \src "libresoc.v:188566.14-188566.47"
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire width 64 $1\data_r0__o$next[63:0]$12433
+ attribute \src "libresoc.v:187510.14-187510.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:189195.3-189216.6"
- wire $1\data_r0__o_ok$next[0:0]$12622
- attribute \src "libresoc.v:188570.7-188570.27"
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire $1\data_r0__o_ok$next[0:0]$12434
+ attribute \src "libresoc.v:187514.7-187514.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:189217.3-189238.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$12629
- attribute \src "libresoc.v:188574.13-188574.33"
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$12441
+ attribute \src "libresoc.v:187518.13-187518.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:189217.3-189238.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$12630
- attribute \src "libresoc.v:188578.7-188578.30"
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$12442
+ attribute \src "libresoc.v:187522.7-187522.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:189239.3-189260.6"
- wire width 2 $1\data_r2__xer_ca$next[1:0]$12637
- attribute \src "libresoc.v:188582.13-188582.35"
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire width 2 $1\data_r2__xer_ca$next[1:0]$12449
+ attribute \src "libresoc.v:187526.13-187526.35"
wire width 2 $1\data_r2__xer_ca[1:0]
- attribute \src "libresoc.v:189239.3-189260.6"
- wire $1\data_r2__xer_ca_ok$next[0:0]$12638
- attribute \src "libresoc.v:188586.7-188586.32"
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire $1\data_r2__xer_ca_ok$next[0:0]$12450
+ attribute \src "libresoc.v:187530.7-187530.32"
wire $1\data_r2__xer_ca_ok[0:0]
- attribute \src "libresoc.v:189329.3-189338.6"
+ attribute \src "libresoc.v:188273.3-188282.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:189339.3-189348.6"
+ attribute \src "libresoc.v:188283.3-188292.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:189349.3-189358.6"
+ attribute \src "libresoc.v:188293.3-188302.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:189112.3-189120.6"
- wire $1\opc_l_r_opc$next[0:0]$12564
- attribute \src "libresoc.v:188603.7-188603.25"
+ attribute \src "libresoc.v:188056.3-188064.6"
+ wire $1\opc_l_r_opc$next[0:0]$12376
+ attribute \src "libresoc.v:187547.7-187547.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:189103.3-189111.6"
- wire $1\opc_l_s_opc$next[0:0]$12561
- attribute \src "libresoc.v:188607.7-188607.25"
+ attribute \src "libresoc.v:188047.3-188055.6"
+ wire $1\opc_l_s_opc$next[0:0]$12373
+ attribute \src "libresoc.v:187551.7-187551.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:189359.3-189367.6"
- wire width 3 $1\prev_wr_go$next[2:0]$12668
- attribute \src "libresoc.v:188739.13-188739.30"
+ attribute \src "libresoc.v:188303.3-188311.6"
+ wire width 3 $1\prev_wr_go$next[2:0]$12480
+ attribute \src "libresoc.v:187683.13-187683.30"
wire width 3 $1\prev_wr_go[2:0]
- attribute \src "libresoc.v:189057.3-189066.6"
+ attribute \src "libresoc.v:188001.3-188010.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:189148.3-189156.6"
- wire width 3 $1\req_l_r_req$next[2:0]$12576
- attribute \src "libresoc.v:188747.13-188747.31"
+ attribute \src "libresoc.v:188092.3-188100.6"
+ wire width 3 $1\req_l_r_req$next[2:0]$12388
+ attribute \src "libresoc.v:187691.13-187691.31"
wire width 3 $1\req_l_r_req[2:0]
- attribute \src "libresoc.v:189139.3-189147.6"
- wire width 3 $1\req_l_s_req$next[2:0]$12573
- attribute \src "libresoc.v:188751.13-188751.31"
+ attribute \src "libresoc.v:188083.3-188091.6"
+ wire width 3 $1\req_l_s_req$next[2:0]$12385
+ attribute \src "libresoc.v:187695.13-187695.31"
wire width 3 $1\req_l_s_req[2:0]
- attribute \src "libresoc.v:189076.3-189084.6"
- wire $1\rok_l_r_rdok$next[0:0]$12552
- attribute \src "libresoc.v:188763.7-188763.26"
+ attribute \src "libresoc.v:188020.3-188028.6"
+ wire $1\rok_l_r_rdok$next[0:0]$12364
+ attribute \src "libresoc.v:187707.7-187707.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:189067.3-189075.6"
- wire $1\rok_l_s_rdok$next[0:0]$12549
- attribute \src "libresoc.v:188767.7-188767.26"
+ attribute \src "libresoc.v:188011.3-188019.6"
+ wire $1\rok_l_s_rdok$next[0:0]$12361
+ attribute \src "libresoc.v:187711.7-187711.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:189094.3-189102.6"
- wire $1\rst_l_r_rst$next[0:0]$12558
- attribute \src "libresoc.v:188771.7-188771.25"
+ attribute \src "libresoc.v:188038.3-188046.6"
+ wire $1\rst_l_r_rst$next[0:0]$12370
+ attribute \src "libresoc.v:187715.7-187715.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:189085.3-189093.6"
- wire $1\rst_l_s_rst$next[0:0]$12555
- attribute \src "libresoc.v:188775.7-188775.25"
+ attribute \src "libresoc.v:188029.3-188037.6"
+ wire $1\rst_l_s_rst$next[0:0]$12367
+ attribute \src "libresoc.v:187719.7-187719.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:189130.3-189138.6"
- wire width 5 $1\src_l_r_src$next[4:0]$12570
- attribute \src "libresoc.v:188793.13-188793.32"
+ attribute \src "libresoc.v:188074.3-188082.6"
+ wire width 5 $1\src_l_r_src$next[4:0]$12382
+ attribute \src "libresoc.v:187737.13-187737.32"
wire width 5 $1\src_l_r_src[4:0]
- attribute \src "libresoc.v:189121.3-189129.6"
- wire width 5 $1\src_l_s_src$next[4:0]$12567
- attribute \src "libresoc.v:188797.13-188797.32"
+ attribute \src "libresoc.v:188065.3-188073.6"
+ wire width 5 $1\src_l_s_src$next[4:0]$12379
+ attribute \src "libresoc.v:187741.13-187741.32"
wire width 5 $1\src_l_s_src[4:0]
- attribute \src "libresoc.v:189261.3-189270.6"
- wire width 64 $1\src_r0$next[63:0]$12644
- attribute \src "libresoc.v:188803.14-188803.43"
+ attribute \src "libresoc.v:188205.3-188214.6"
+ wire width 64 $1\src_r0$next[63:0]$12456
+ attribute \src "libresoc.v:187747.14-187747.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:189271.3-189280.6"
- wire width 64 $1\src_r1$next[63:0]$12647
- attribute \src "libresoc.v:188807.14-188807.43"
+ attribute \src "libresoc.v:188215.3-188224.6"
+ wire width 64 $1\src_r1$next[63:0]$12459
+ attribute \src "libresoc.v:187751.14-187751.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:189281.3-189290.6"
- wire width 64 $1\src_r2$next[63:0]$12650
- attribute \src "libresoc.v:188811.14-188811.43"
+ attribute \src "libresoc.v:188225.3-188234.6"
+ wire width 64 $1\src_r2$next[63:0]$12462
+ attribute \src "libresoc.v:187755.14-187755.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:189291.3-189300.6"
- wire $1\src_r3$next[0:0]$12653
- attribute \src "libresoc.v:188815.7-188815.20"
+ attribute \src "libresoc.v:188235.3-188244.6"
+ wire $1\src_r3$next[0:0]$12465
+ attribute \src "libresoc.v:187759.7-187759.20"
wire $1\src_r3[0:0]
- attribute \src "libresoc.v:189301.3-189310.6"
- wire width 2 $1\src_r4$next[1:0]$12656
- attribute \src "libresoc.v:188819.13-188819.26"
+ attribute \src "libresoc.v:188245.3-188254.6"
+ wire width 2 $1\src_r4$next[1:0]$12468
+ attribute \src "libresoc.v:187763.13-187763.26"
wire width 2 $1\src_r4[1:0]
- attribute \src "libresoc.v:189157.3-189194.6"
- wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616
- attribute \src "libresoc.v:189157.3-189194.6"
- wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617
- attribute \src "libresoc.v:189195.3-189216.6"
- wire width 64 $2\data_r0__o$next[63:0]$12623
- attribute \src "libresoc.v:189195.3-189216.6"
- wire $2\data_r0__o_ok$next[0:0]$12624
- attribute \src "libresoc.v:189217.3-189238.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$12631
- attribute \src "libresoc.v:189217.3-189238.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$12632
- attribute \src "libresoc.v:189239.3-189260.6"
- wire width 2 $2\data_r2__xer_ca$next[1:0]$12639
- attribute \src "libresoc.v:189239.3-189260.6"
- wire $2\data_r2__xer_ca_ok$next[0:0]$12640
- attribute \src "libresoc.v:189195.3-189216.6"
- wire $3\data_r0__o_ok$next[0:0]$12625
- attribute \src "libresoc.v:189217.3-189238.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$12633
- attribute \src "libresoc.v:189239.3-189260.6"
- wire $3\data_r2__xer_ca_ok$next[0:0]$12641
- attribute \src "libresoc.v:188829.19-188829.114"
- wire width 5 $and$libresoc.v:188829$12445_Y
- attribute \src "libresoc.v:188830.19-188830.125"
- wire $and$libresoc.v:188830$12446_Y
- attribute \src "libresoc.v:188831.19-188831.125"
- wire $and$libresoc.v:188831$12447_Y
- attribute \src "libresoc.v:188832.19-188832.125"
- wire $and$libresoc.v:188832$12448_Y
- attribute \src "libresoc.v:188833.18-188833.110"
- wire $and$libresoc.v:188833$12449_Y
- attribute \src "libresoc.v:188834.19-188834.141"
- wire width 3 $and$libresoc.v:188834$12450_Y
- attribute \src "libresoc.v:188835.19-188835.121"
- wire width 3 $and$libresoc.v:188835$12451_Y
- attribute \src "libresoc.v:188836.19-188836.127"
- wire $and$libresoc.v:188836$12452_Y
- attribute \src "libresoc.v:188837.19-188837.127"
- wire $and$libresoc.v:188837$12453_Y
- attribute \src "libresoc.v:188838.19-188838.127"
- wire $and$libresoc.v:188838$12454_Y
- attribute \src "libresoc.v:188840.18-188840.98"
- wire $and$libresoc.v:188840$12456_Y
- attribute \src "libresoc.v:188842.18-188842.100"
- wire $and$libresoc.v:188842$12458_Y
- attribute \src "libresoc.v:188843.18-188843.149"
- wire width 3 $and$libresoc.v:188843$12459_Y
- attribute \src "libresoc.v:188845.18-188845.119"
- wire width 3 $and$libresoc.v:188845$12461_Y
- attribute \src "libresoc.v:188848.17-188848.123"
- wire $and$libresoc.v:188848$12464_Y
- attribute \src "libresoc.v:188849.18-188849.116"
- wire $and$libresoc.v:188849$12465_Y
- attribute \src "libresoc.v:188854.18-188854.113"
- wire $and$libresoc.v:188854$12470_Y
- attribute \src "libresoc.v:188855.18-188855.125"
- wire width 3 $and$libresoc.v:188855$12471_Y
- attribute \src "libresoc.v:188857.18-188857.112"
- wire $and$libresoc.v:188857$12473_Y
- attribute \src "libresoc.v:188859.18-188859.132"
- wire $and$libresoc.v:188859$12475_Y
- attribute \src "libresoc.v:188860.18-188860.132"
- wire $and$libresoc.v:188860$12476_Y
- attribute \src "libresoc.v:188861.18-188861.117"
- wire $and$libresoc.v:188861$12477_Y
- attribute \src "libresoc.v:188867.18-188867.136"
- wire $and$libresoc.v:188867$12483_Y
- attribute \src "libresoc.v:188868.18-188868.124"
- wire width 3 $and$libresoc.v:188868$12484_Y
- attribute \src "libresoc.v:188870.18-188870.116"
- wire $and$libresoc.v:188870$12486_Y
- attribute \src "libresoc.v:188871.18-188871.119"
- wire $and$libresoc.v:188871$12487_Y
- attribute \src "libresoc.v:188872.18-188872.121"
- wire $and$libresoc.v:188872$12488_Y
- attribute \src "libresoc.v:188882.18-188882.140"
- wire $and$libresoc.v:188882$12498_Y
- attribute \src "libresoc.v:188883.18-188883.138"
- wire $and$libresoc.v:188883$12499_Y
- attribute \src "libresoc.v:188884.18-188884.171"
- wire width 5 $and$libresoc.v:188884$12500_Y
- attribute \src "libresoc.v:188886.18-188886.129"
- wire width 5 $and$libresoc.v:188886$12502_Y
- attribute \src "libresoc.v:188856.18-188856.113"
- wire $eq$libresoc.v:188856$12472_Y
- attribute \src "libresoc.v:188858.18-188858.119"
- wire $eq$libresoc.v:188858$12474_Y
- attribute \src "libresoc.v:188828.19-188828.115"
- wire width 5 $not$libresoc.v:188828$12444_Y
- attribute \src "libresoc.v:188839.18-188839.97"
- wire $not$libresoc.v:188839$12455_Y
- attribute \src "libresoc.v:188841.18-188841.99"
- wire $not$libresoc.v:188841$12457_Y
- attribute \src "libresoc.v:188844.18-188844.113"
- wire width 3 $not$libresoc.v:188844$12460_Y
- attribute \src "libresoc.v:188847.18-188847.106"
- wire $not$libresoc.v:188847$12463_Y
- attribute \src "libresoc.v:188853.18-188853.126"
- wire $not$libresoc.v:188853$12469_Y
- attribute \src "libresoc.v:188864.17-188864.113"
- wire width 5 $not$libresoc.v:188864$12480_Y
- attribute \src "libresoc.v:188885.18-188885.136"
- wire $not$libresoc.v:188885$12501_Y
- attribute \src "libresoc.v:188852.18-188852.112"
- wire $or$libresoc.v:188852$12468_Y
- attribute \src "libresoc.v:188862.18-188862.122"
- wire $or$libresoc.v:188862$12478_Y
- attribute \src "libresoc.v:188863.18-188863.124"
- wire $or$libresoc.v:188863$12479_Y
- attribute \src "libresoc.v:188865.18-188865.155"
- wire width 3 $or$libresoc.v:188865$12481_Y
- attribute \src "libresoc.v:188866.18-188866.181"
- wire width 5 $or$libresoc.v:188866$12482_Y
- attribute \src "libresoc.v:188869.18-188869.120"
- wire width 3 $or$libresoc.v:188869$12485_Y
- attribute \src "libresoc.v:188875.17-188875.117"
- wire width 5 $or$libresoc.v:188875$12491_Y
- attribute \src "libresoc.v:188881.17-188881.104"
- wire $reduce_and$libresoc.v:188881$12497_Y
- attribute \src "libresoc.v:188846.18-188846.106"
- wire $reduce_or$libresoc.v:188846$12462_Y
- attribute \src "libresoc.v:188850.18-188850.113"
- wire $reduce_or$libresoc.v:188850$12466_Y
- attribute \src "libresoc.v:188851.18-188851.112"
- wire $reduce_or$libresoc.v:188851$12467_Y
- attribute \src "libresoc.v:188873.18-188873.165"
- wire $ternary$libresoc.v:188873$12489_Y
- attribute \src "libresoc.v:188874.18-188874.182"
- wire width 64 $ternary$libresoc.v:188874$12490_Y
- attribute \src "libresoc.v:188876.18-188876.118"
- wire width 64 $ternary$libresoc.v:188876$12492_Y
- attribute \src "libresoc.v:188877.18-188877.115"
- wire width 64 $ternary$libresoc.v:188877$12493_Y
- attribute \src "libresoc.v:188878.18-188878.118"
- wire width 64 $ternary$libresoc.v:188878$12494_Y
- attribute \src "libresoc.v:188879.18-188879.118"
- wire $ternary$libresoc.v:188879$12495_Y
- attribute \src "libresoc.v:188880.18-188880.118"
- wire width 2 $ternary$libresoc.v:188880$12496_Y
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428
+ attribute \src "libresoc.v:188101.3-188138.6"
+ wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire width 64 $2\data_r0__o$next[63:0]$12435
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire $2\data_r0__o_ok$next[0:0]$12436
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$12443
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$12444
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire width 2 $2\data_r2__xer_ca$next[1:0]$12451
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire $2\data_r2__xer_ca_ok$next[0:0]$12452
+ attribute \src "libresoc.v:188139.3-188160.6"
+ wire $3\data_r0__o_ok$next[0:0]$12437
+ attribute \src "libresoc.v:188161.3-188182.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$12445
+ attribute \src "libresoc.v:188183.3-188204.6"
+ wire $3\data_r2__xer_ca_ok$next[0:0]$12453
+ attribute \src "libresoc.v:187773.19-187773.114"
+ wire width 5 $and$libresoc.v:187773$12257_Y
+ attribute \src "libresoc.v:187774.19-187774.125"
+ wire $and$libresoc.v:187774$12258_Y
+ attribute \src "libresoc.v:187775.19-187775.125"
+ wire $and$libresoc.v:187775$12259_Y
+ attribute \src "libresoc.v:187776.19-187776.125"
+ wire $and$libresoc.v:187776$12260_Y
+ attribute \src "libresoc.v:187777.18-187777.110"
+ wire $and$libresoc.v:187777$12261_Y
+ attribute \src "libresoc.v:187778.19-187778.141"
+ wire width 3 $and$libresoc.v:187778$12262_Y
+ attribute \src "libresoc.v:187779.19-187779.121"
+ wire width 3 $and$libresoc.v:187779$12263_Y
+ attribute \src "libresoc.v:187780.19-187780.127"
+ wire $and$libresoc.v:187780$12264_Y
+ attribute \src "libresoc.v:187781.19-187781.127"
+ wire $and$libresoc.v:187781$12265_Y
+ attribute \src "libresoc.v:187782.19-187782.127"
+ wire $and$libresoc.v:187782$12266_Y
+ attribute \src "libresoc.v:187784.18-187784.98"
+ wire $and$libresoc.v:187784$12268_Y
+ attribute \src "libresoc.v:187786.18-187786.100"
+ wire $and$libresoc.v:187786$12270_Y
+ attribute \src "libresoc.v:187787.18-187787.149"
+ wire width 3 $and$libresoc.v:187787$12271_Y
+ attribute \src "libresoc.v:187789.18-187789.119"
+ wire width 3 $and$libresoc.v:187789$12273_Y
+ attribute \src "libresoc.v:187792.17-187792.123"
+ wire $and$libresoc.v:187792$12276_Y
+ attribute \src "libresoc.v:187793.18-187793.116"
+ wire $and$libresoc.v:187793$12277_Y
+ attribute \src "libresoc.v:187798.18-187798.113"
+ wire $and$libresoc.v:187798$12282_Y
+ attribute \src "libresoc.v:187799.18-187799.125"
+ wire width 3 $and$libresoc.v:187799$12283_Y
+ attribute \src "libresoc.v:187801.18-187801.112"
+ wire $and$libresoc.v:187801$12285_Y
+ attribute \src "libresoc.v:187803.18-187803.132"
+ wire $and$libresoc.v:187803$12287_Y
+ attribute \src "libresoc.v:187804.18-187804.132"
+ wire $and$libresoc.v:187804$12288_Y
+ attribute \src "libresoc.v:187805.18-187805.117"
+ wire $and$libresoc.v:187805$12289_Y
+ attribute \src "libresoc.v:187811.18-187811.136"
+ wire $and$libresoc.v:187811$12295_Y
+ attribute \src "libresoc.v:187812.18-187812.124"
+ wire width 3 $and$libresoc.v:187812$12296_Y
+ attribute \src "libresoc.v:187814.18-187814.116"
+ wire $and$libresoc.v:187814$12298_Y
+ attribute \src "libresoc.v:187815.18-187815.119"
+ wire $and$libresoc.v:187815$12299_Y
+ attribute \src "libresoc.v:187816.18-187816.121"
+ wire $and$libresoc.v:187816$12300_Y
+ attribute \src "libresoc.v:187826.18-187826.140"
+ wire $and$libresoc.v:187826$12310_Y
+ attribute \src "libresoc.v:187827.18-187827.138"
+ wire $and$libresoc.v:187827$12311_Y
+ attribute \src "libresoc.v:187828.18-187828.171"
+ wire width 5 $and$libresoc.v:187828$12312_Y
+ attribute \src "libresoc.v:187830.18-187830.129"
+ wire width 5 $and$libresoc.v:187830$12314_Y
+ attribute \src "libresoc.v:187800.18-187800.113"
+ wire $eq$libresoc.v:187800$12284_Y
+ attribute \src "libresoc.v:187802.18-187802.119"
+ wire $eq$libresoc.v:187802$12286_Y
+ attribute \src "libresoc.v:187772.19-187772.115"
+ wire width 5 $not$libresoc.v:187772$12256_Y
+ attribute \src "libresoc.v:187783.18-187783.97"
+ wire $not$libresoc.v:187783$12267_Y
+ attribute \src "libresoc.v:187785.18-187785.99"
+ wire $not$libresoc.v:187785$12269_Y
+ attribute \src "libresoc.v:187788.18-187788.113"
+ wire width 3 $not$libresoc.v:187788$12272_Y
+ attribute \src "libresoc.v:187791.18-187791.106"
+ wire $not$libresoc.v:187791$12275_Y
+ attribute \src "libresoc.v:187797.18-187797.126"
+ wire $not$libresoc.v:187797$12281_Y
+ attribute \src "libresoc.v:187808.17-187808.113"
+ wire width 5 $not$libresoc.v:187808$12292_Y
+ attribute \src "libresoc.v:187829.18-187829.136"
+ wire $not$libresoc.v:187829$12313_Y
+ attribute \src "libresoc.v:187796.18-187796.112"
+ wire $or$libresoc.v:187796$12280_Y
+ attribute \src "libresoc.v:187806.18-187806.122"
+ wire $or$libresoc.v:187806$12290_Y
+ attribute \src "libresoc.v:187807.18-187807.124"
+ wire $or$libresoc.v:187807$12291_Y
+ attribute \src "libresoc.v:187809.18-187809.155"
+ wire width 3 $or$libresoc.v:187809$12293_Y
+ attribute \src "libresoc.v:187810.18-187810.181"
+ wire width 5 $or$libresoc.v:187810$12294_Y
+ attribute \src "libresoc.v:187813.18-187813.120"
+ wire width 3 $or$libresoc.v:187813$12297_Y
+ attribute \src "libresoc.v:187819.17-187819.117"
+ wire width 5 $or$libresoc.v:187819$12303_Y
+ attribute \src "libresoc.v:187825.17-187825.104"
+ wire $reduce_and$libresoc.v:187825$12309_Y
+ attribute \src "libresoc.v:187790.18-187790.106"
+ wire $reduce_or$libresoc.v:187790$12274_Y
+ attribute \src "libresoc.v:187794.18-187794.113"
+ wire $reduce_or$libresoc.v:187794$12278_Y
+ attribute \src "libresoc.v:187795.18-187795.112"
+ wire $reduce_or$libresoc.v:187795$12279_Y
+ attribute \src "libresoc.v:187817.18-187817.165"
+ wire $ternary$libresoc.v:187817$12301_Y
+ attribute \src "libresoc.v:187818.18-187818.182"
+ wire width 64 $ternary$libresoc.v:187818$12302_Y
+ attribute \src "libresoc.v:187820.18-187820.118"
+ wire width 64 $ternary$libresoc.v:187820$12304_Y
+ attribute \src "libresoc.v:187821.18-187821.115"
+ wire width 64 $ternary$libresoc.v:187821$12305_Y
+ attribute \src "libresoc.v:187822.18-187822.118"
+ wire width 64 $ternary$libresoc.v:187822$12306_Y
+ attribute \src "libresoc.v:187823.18-187823.118"
+ wire $ternary$libresoc.v:187823$12307_Y
+ attribute \src "libresoc.v:187824.18-187824.118"
+ wire width 2 $ternary$libresoc.v:187824$12308_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 37 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 33 \cr_a_ok
wire width 4 output 34 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 2 output 36 \dest3_o
- attribute \src "libresoc.v:188194.7-188194.15"
+ attribute \src "libresoc.v:187138.7-187138.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 24 \src1_i
+ wire width 64 input 26 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 25 \src2_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 26 \src3_i
+ wire width 64 input 25 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire input 27 \src4_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 35 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:188829$12445
+ cell $and $and$libresoc.v:187773$12257
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$98
connect \B \$100
- connect \Y $and$libresoc.v:188829$12445_Y
+ connect \Y $and$libresoc.v:187773$12257_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:188830$12446
+ cell $and $and$libresoc.v:187774$12258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:188830$12446_Y
+ connect \Y $and$libresoc.v:187774$12258_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:188831$12447
+ cell $and $and$libresoc.v:187775$12259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:188831$12447_Y
+ connect \Y $and$libresoc.v:187775$12259_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:188832$12448
+ cell $and $and$libresoc.v:187776$12260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:188832$12448_Y
+ connect \Y $and$libresoc.v:187776$12260_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:188833$12449
+ cell $and $and$libresoc.v:187777$12261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:188833$12449_Y
+ connect \Y $and$libresoc.v:187777$12261_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:188834$12450
+ cell $and $and$libresoc.v:187778$12262
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B { \$104 \$106 \$108 }
- connect \Y $and$libresoc.v:188834$12450_Y
+ connect \Y $and$libresoc.v:187778$12262_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:188835$12451
+ cell $and $and$libresoc.v:187779$12263
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$110
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:188835$12451_Y
+ connect \Y $and$libresoc.v:187779$12263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:188836$12452
+ cell $and $and$libresoc.v:187780$12264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188836$12452_Y
+ connect \Y $and$libresoc.v:187780$12264_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:188837$12453
+ cell $and $and$libresoc.v:187781$12265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188837$12453_Y
+ connect \Y $and$libresoc.v:187781$12265_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:188838$12454
+ cell $and $and$libresoc.v:187782$12266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188838$12454_Y
+ connect \Y $and$libresoc.v:187782$12266_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:188840$12456
+ cell $and $and$libresoc.v:187784$12268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:188840$12456_Y
+ connect \Y $and$libresoc.v:187784$12268_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:188842$12458
+ cell $and $and$libresoc.v:187786$12270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:188842$12458_Y
+ connect \Y $and$libresoc.v:187786$12270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:188843$12459
+ cell $and $and$libresoc.v:187787$12271
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:188843$12459_Y
+ connect \Y $and$libresoc.v:187787$12271_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:188845$12461
+ cell $and $and$libresoc.v:187789$12273
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:188845$12461_Y
+ connect \Y $and$libresoc.v:187789$12273_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:188848$12464
+ cell $and $and$libresoc.v:187792$12276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:188848$12464_Y
+ connect \Y $and$libresoc.v:187792$12276_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:188849$12465
+ cell $and $and$libresoc.v:187793$12277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:188849$12465_Y
+ connect \Y $and$libresoc.v:187793$12277_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:188854$12470
+ cell $and $and$libresoc.v:187798$12282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:188854$12470_Y
+ connect \Y $and$libresoc.v:187798$12282_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:188855$12471
+ cell $and $and$libresoc.v:187799$12283
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:188855$12471_Y
+ connect \Y $and$libresoc.v:187799$12283_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:188857$12473
+ cell $and $and$libresoc.v:187801$12285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:188857$12473_Y
+ connect \Y $and$libresoc.v:187801$12285_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:188859$12475
+ cell $and $and$libresoc.v:187803$12287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_shift_rot0_n_ready_i
- connect \Y $and$libresoc.v:188859$12475_Y
+ connect \Y $and$libresoc.v:187803$12287_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:188860$12476
+ cell $and $and$libresoc.v:187804$12288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_shift_rot0_n_valid_o
- connect \Y $and$libresoc.v:188860$12476_Y
+ connect \Y $and$libresoc.v:187804$12288_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:188861$12477
+ cell $and $and$libresoc.v:187805$12289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188861$12477_Y
+ connect \Y $and$libresoc.v:187805$12289_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:188867$12483
+ cell $and $and$libresoc.v:187811$12295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188867$12483_Y
+ connect \Y $and$libresoc.v:187811$12295_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:188868$12484
+ cell $and $and$libresoc.v:187812$12296
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:188868$12484_Y
+ connect \Y $and$libresoc.v:187812$12296_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:188870$12486
+ cell $and $and$libresoc.v:187814$12298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188870$12486_Y
+ connect \Y $and$libresoc.v:187814$12298_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:188871$12487
+ cell $and $and$libresoc.v:187815$12299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188871$12487_Y
+ connect \Y $and$libresoc.v:187815$12299_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:188872$12488
+ cell $and $and$libresoc.v:187816$12300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ca_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:188872$12488_Y
+ connect \Y $and$libresoc.v:187816$12300_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:188882$12498
+ cell $and $and$libresoc.v:187826$12310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:188882$12498_Y
+ connect \Y $and$libresoc.v:187826$12310_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:188883$12499
+ cell $and $and$libresoc.v:187827$12311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:188883$12499_Y
+ connect \Y $and$libresoc.v:187827$12311_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:188884$12500
+ cell $and $and$libresoc.v:187828$12312
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:188884$12500_Y
+ connect \Y $and$libresoc.v:187828$12312_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:188886$12502
+ cell $and $and$libresoc.v:187830$12314
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$94
connect \B { 3'111 \$96 1'1 }
- connect \Y $and$libresoc.v:188886$12502_Y
+ connect \Y $and$libresoc.v:187830$12314_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:188856$12472
+ cell $eq $eq$libresoc.v:187800$12284
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:188856$12472_Y
+ connect \Y $eq$libresoc.v:187800$12284_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:188858$12474
+ cell $eq $eq$libresoc.v:187802$12286
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:188858$12474_Y
+ connect \Y $eq$libresoc.v:187802$12286_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:188828$12444
+ cell $not $not$libresoc.v:187772$12256
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:188828$12444_Y
+ connect \Y $not$libresoc.v:187772$12256_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:188839$12455
+ cell $not $not$libresoc.v:187783$12267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:188839$12455_Y
+ connect \Y $not$libresoc.v:187783$12267_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:188841$12457
+ cell $not $not$libresoc.v:187785$12269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:188841$12457_Y
+ connect \Y $not$libresoc.v:187785$12269_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:188844$12460
+ cell $not $not$libresoc.v:187788$12272
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:188844$12460_Y
+ connect \Y $not$libresoc.v:187788$12272_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:188847$12463
+ cell $not $not$libresoc.v:187791$12275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:188847$12463_Y
+ connect \Y $not$libresoc.v:187791$12275_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:188853$12469
+ cell $not $not$libresoc.v:187797$12281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_ready_i
- connect \Y $not$libresoc.v:188853$12469_Y
+ connect \Y $not$libresoc.v:187797$12281_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:188864$12480
+ cell $not $not$libresoc.v:187808$12292
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:188864$12480_Y
+ connect \Y $not$libresoc.v:187808$12292_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:188885$12501
+ cell $not $not$libresoc.v:187829$12313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $not$libresoc.v:188885$12501_Y
+ connect \Y $not$libresoc.v:187829$12313_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:188852$12468
+ cell $or $or$libresoc.v:187796$12280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:188852$12468_Y
+ connect \Y $or$libresoc.v:187796$12280_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:188862$12478
+ cell $or $or$libresoc.v:187806$12290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:188862$12478_Y
+ connect \Y $or$libresoc.v:187806$12290_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:188863$12479
+ cell $or $or$libresoc.v:187807$12291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:188863$12479_Y
+ connect \Y $or$libresoc.v:187807$12291_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:188865$12481
+ cell $or $or$libresoc.v:187809$12293
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:188865$12481_Y
+ connect \Y $or$libresoc.v:187809$12293_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:188866$12482
+ cell $or $or$libresoc.v:187810$12294
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:188866$12482_Y
+ connect \Y $or$libresoc.v:187810$12294_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:188869$12485
+ cell $or $or$libresoc.v:187813$12297
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:188869$12485_Y
+ connect \Y $or$libresoc.v:187813$12297_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:188875$12491
+ cell $or $or$libresoc.v:187819$12303
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:188875$12491_Y
+ connect \Y $or$libresoc.v:187819$12303_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:188881$12497
+ cell $reduce_and $reduce_and$libresoc.v:187825$12309
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:188881$12497_Y
+ connect \Y $reduce_and$libresoc.v:187825$12309_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:188846$12462
+ cell $reduce_or $reduce_or$libresoc.v:187790$12274
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:188846$12462_Y
+ connect \Y $reduce_or$libresoc.v:187790$12274_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:188850$12466
+ cell $reduce_or $reduce_or$libresoc.v:187794$12278
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:188850$12466_Y
+ connect \Y $reduce_or$libresoc.v:187794$12278_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:188851$12467
+ cell $reduce_or $reduce_or$libresoc.v:187795$12279
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:188851$12467_Y
+ connect \Y $reduce_or$libresoc.v:187795$12279_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:188873$12489
+ cell $mux $ternary$libresoc.v:187817$12301
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $ternary$libresoc.v:188873$12489_Y
+ connect \Y $ternary$libresoc.v:187817$12301_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:188874$12490
+ cell $mux $ternary$libresoc.v:187818$12302
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_shift_rot0_sr_op__imm_data__data
connect \S \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $ternary$libresoc.v:188874$12490_Y
+ connect \Y $ternary$libresoc.v:187818$12302_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:188876$12492
+ cell $mux $ternary$libresoc.v:187820$12304
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:188876$12492_Y
+ connect \Y $ternary$libresoc.v:187820$12304_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:188877$12493
+ cell $mux $ternary$libresoc.v:187821$12305
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:188877$12493_Y
+ connect \Y $ternary$libresoc.v:187821$12305_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:188878$12494
+ cell $mux $ternary$libresoc.v:187822$12306
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:188878$12494_Y
+ connect \Y $ternary$libresoc.v:187822$12306_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:188879$12495
+ cell $mux $ternary$libresoc.v:187823$12307
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:188879$12495_Y
+ connect \Y $ternary$libresoc.v:187823$12307_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:188880$12496
+ cell $mux $ternary$libresoc.v:187824$12308
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:188880$12496_Y
+ connect \Y $ternary$libresoc.v:187824$12308_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:188973.15-188979.4"
+ attribute \src "libresoc.v:187917.15-187923.4"
cell \alu_l$125 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:188980.18-189015.4"
+ attribute \src "libresoc.v:187924.18-187959.4"
cell \alu_shift_rot0 \alu_shift_rot0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so \alu_shift_rot0_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189016.16-189022.4"
+ attribute \src "libresoc.v:187960.16-187966.4"
cell \alui_l$124 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189023.15-189029.4"
+ attribute \src "libresoc.v:187967.15-187973.4"
cell \opc_l$120 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189030.15-189036.4"
+ attribute \src "libresoc.v:187974.15-187980.4"
cell \req_l$121 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189037.15-189043.4"
+ attribute \src "libresoc.v:187981.15-187987.4"
cell \rok_l$123 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189044.15-189049.4"
+ attribute \src "libresoc.v:187988.15-187993.4"
cell \rst_l$122 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189050.15-189056.4"
+ attribute \src "libresoc.v:187994.15-188000.4"
cell \src_l$119 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:188194.7-188194.20"
- process $proc$libresoc.v:188194$12669
+ attribute \src "libresoc.v:187138.7-187138.20"
+ process $proc$libresoc.v:187138$12481
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:188316.7-188316.24"
- process $proc$libresoc.v:188316$12670
+ attribute \src "libresoc.v:187260.7-187260.24"
+ process $proc$libresoc.v:187260$12482
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:188326.7-188326.26"
- process $proc$libresoc.v:188326$12671
+ attribute \src "libresoc.v:187270.7-187270.26"
+ process $proc$libresoc.v:187270$12483
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:188334.7-188334.25"
- process $proc$libresoc.v:188334$12672
+ attribute \src "libresoc.v:187278.7-187278.25"
+ process $proc$libresoc.v:187278$12484
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:188377.14-188377.54"
- process $proc$libresoc.v:188377$12673
+ attribute \src "libresoc.v:187321.14-187321.54"
+ process $proc$libresoc.v:187321$12485
assign { } { }
assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:188381.14-188381.73"
- process $proc$libresoc.v:188381$12674
+ attribute \src "libresoc.v:187325.14-187325.73"
+ process $proc$libresoc.v:187325$12486
assign { } { }
assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:188385.7-188385.48"
- process $proc$libresoc.v:188385$12675
+ attribute \src "libresoc.v:187329.7-187329.48"
+ process $proc$libresoc.v:187329$12487
assign { } { }
assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:188393.13-188393.53"
- process $proc$libresoc.v:188393$12676
+ attribute \src "libresoc.v:187337.13-187337.53"
+ process $proc$libresoc.v:187337$12488
assign { } { }
assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:188397.7-188397.44"
- process $proc$libresoc.v:188397$12677
+ attribute \src "libresoc.v:187341.7-187341.44"
+ process $proc$libresoc.v:187341$12489
assign { } { }
assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:188401.14-188401.48"
- process $proc$libresoc.v:188401$12678
+ attribute \src "libresoc.v:187345.14-187345.48"
+ process $proc$libresoc.v:187345$12490
assign { } { }
assign $1\alu_shift_rot0_sr_op__insn[31:0] 0
sync always
sync init
update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0]
end
- attribute \src "libresoc.v:188480.13-188480.52"
- process $proc$libresoc.v:188480$12679
+ attribute \src "libresoc.v:187424.13-187424.52"
+ process $proc$libresoc.v:187424$12491
assign { } { }
assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:188484.7-188484.45"
- process $proc$libresoc.v:188484$12680
+ attribute \src "libresoc.v:187428.7-187428.45"
+ process $proc$libresoc.v:187428$12492
assign { } { }
assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:188488.7-188488.44"
- process $proc$libresoc.v:188488$12681
+ attribute \src "libresoc.v:187432.7-187432.44"
+ process $proc$libresoc.v:187432$12493
assign { } { }
assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:188492.7-188492.45"
- process $proc$libresoc.v:188492$12682
+ attribute \src "libresoc.v:187436.7-187436.45"
+ process $proc$libresoc.v:187436$12494
assign { } { }
assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:188496.7-188496.42"
- process $proc$libresoc.v:188496$12683
+ attribute \src "libresoc.v:187440.7-187440.42"
+ process $proc$libresoc.v:187440$12495
assign { } { }
assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:188500.7-188500.42"
- process $proc$libresoc.v:188500$12684
+ attribute \src "libresoc.v:187444.7-187444.42"
+ process $proc$libresoc.v:187444$12496
assign { } { }
assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:188504.7-188504.48"
- process $proc$libresoc.v:188504$12685
+ attribute \src "libresoc.v:187448.7-187448.48"
+ process $proc$libresoc.v:187448$12497
assign { } { }
assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:188508.7-188508.45"
- process $proc$libresoc.v:188508$12686
+ attribute \src "libresoc.v:187452.7-187452.45"
+ process $proc$libresoc.v:187452$12498
assign { } { }
assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:188512.7-188512.42"
- process $proc$libresoc.v:188512$12687
+ attribute \src "libresoc.v:187456.7-187456.42"
+ process $proc$libresoc.v:187456$12499
assign { } { }
assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:188516.7-188516.42"
- process $proc$libresoc.v:188516$12688
+ attribute \src "libresoc.v:187460.7-187460.42"
+ process $proc$libresoc.v:187460$12500
assign { } { }
assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:188520.7-188520.45"
- process $proc$libresoc.v:188520$12689
+ attribute \src "libresoc.v:187464.7-187464.45"
+ process $proc$libresoc.v:187464$12501
assign { } { }
assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:188532.7-188532.27"
- process $proc$libresoc.v:188532$12690
+ attribute \src "libresoc.v:187476.7-187476.27"
+ process $proc$libresoc.v:187476$12502
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:188566.14-188566.47"
- process $proc$libresoc.v:188566$12691
+ attribute \src "libresoc.v:187510.14-187510.47"
+ process $proc$libresoc.v:187510$12503
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:188570.7-188570.27"
- process $proc$libresoc.v:188570$12692
+ attribute \src "libresoc.v:187514.7-187514.27"
+ process $proc$libresoc.v:187514$12504
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:188574.13-188574.33"
- process $proc$libresoc.v:188574$12693
+ attribute \src "libresoc.v:187518.13-187518.33"
+ process $proc$libresoc.v:187518$12505
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:188578.7-188578.30"
- process $proc$libresoc.v:188578$12694
+ attribute \src "libresoc.v:187522.7-187522.30"
+ process $proc$libresoc.v:187522$12506
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:188582.13-188582.35"
- process $proc$libresoc.v:188582$12695
+ attribute \src "libresoc.v:187526.13-187526.35"
+ process $proc$libresoc.v:187526$12507
assign { } { }
assign $1\data_r2__xer_ca[1:0] 2'00
sync always
sync init
update \data_r2__xer_ca $1\data_r2__xer_ca[1:0]
end
- attribute \src "libresoc.v:188586.7-188586.32"
- process $proc$libresoc.v:188586$12696
+ attribute \src "libresoc.v:187530.7-187530.32"
+ process $proc$libresoc.v:187530$12508
assign { } { }
assign $1\data_r2__xer_ca_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:188603.7-188603.25"
- process $proc$libresoc.v:188603$12697
+ attribute \src "libresoc.v:187547.7-187547.25"
+ process $proc$libresoc.v:187547$12509
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:188607.7-188607.25"
- process $proc$libresoc.v:188607$12698
+ attribute \src "libresoc.v:187551.7-187551.25"
+ process $proc$libresoc.v:187551$12510
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:188739.13-188739.30"
- process $proc$libresoc.v:188739$12699
+ attribute \src "libresoc.v:187683.13-187683.30"
+ process $proc$libresoc.v:187683$12511
assign { } { }
assign $1\prev_wr_go[2:0] 3'000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:188747.13-188747.31"
- process $proc$libresoc.v:188747$12700
+ attribute \src "libresoc.v:187691.13-187691.31"
+ process $proc$libresoc.v:187691$12512
assign { } { }
assign $1\req_l_r_req[2:0] 3'111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:188751.13-188751.31"
- process $proc$libresoc.v:188751$12701
+ attribute \src "libresoc.v:187695.13-187695.31"
+ process $proc$libresoc.v:187695$12513
assign { } { }
assign $1\req_l_s_req[2:0] 3'000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:188763.7-188763.26"
- process $proc$libresoc.v:188763$12702
+ attribute \src "libresoc.v:187707.7-187707.26"
+ process $proc$libresoc.v:187707$12514
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:188767.7-188767.26"
- process $proc$libresoc.v:188767$12703
+ attribute \src "libresoc.v:187711.7-187711.26"
+ process $proc$libresoc.v:187711$12515
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:188771.7-188771.25"
- process $proc$libresoc.v:188771$12704
+ attribute \src "libresoc.v:187715.7-187715.25"
+ process $proc$libresoc.v:187715$12516
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:188775.7-188775.25"
- process $proc$libresoc.v:188775$12705
+ attribute \src "libresoc.v:187719.7-187719.25"
+ process $proc$libresoc.v:187719$12517
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:188793.13-188793.32"
- process $proc$libresoc.v:188793$12706
+ attribute \src "libresoc.v:187737.13-187737.32"
+ process $proc$libresoc.v:187737$12518
assign { } { }
assign $1\src_l_r_src[4:0] 5'11111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[4:0]
end
- attribute \src "libresoc.v:188797.13-188797.32"
- process $proc$libresoc.v:188797$12707
+ attribute \src "libresoc.v:187741.13-187741.32"
+ process $proc$libresoc.v:187741$12519
assign { } { }
assign $1\src_l_s_src[4:0] 5'00000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[4:0]
end
- attribute \src "libresoc.v:188803.14-188803.43"
- process $proc$libresoc.v:188803$12708
+ attribute \src "libresoc.v:187747.14-187747.43"
+ process $proc$libresoc.v:187747$12520
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:188807.14-188807.43"
- process $proc$libresoc.v:188807$12709
+ attribute \src "libresoc.v:187751.14-187751.43"
+ process $proc$libresoc.v:187751$12521
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:188811.14-188811.43"
- process $proc$libresoc.v:188811$12710
+ attribute \src "libresoc.v:187755.14-187755.43"
+ process $proc$libresoc.v:187755$12522
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:188815.7-188815.20"
- process $proc$libresoc.v:188815$12711
+ attribute \src "libresoc.v:187759.7-187759.20"
+ process $proc$libresoc.v:187759$12523
assign { } { }
assign $1\src_r3[0:0] 1'0
sync always
sync init
update \src_r3 $1\src_r3[0:0]
end
- attribute \src "libresoc.v:188819.13-188819.26"
- process $proc$libresoc.v:188819$12712
+ attribute \src "libresoc.v:187763.13-187763.26"
+ process $proc$libresoc.v:187763$12524
assign { } { }
assign $1\src_r4[1:0] 2'00
sync always
sync init
update \src_r4 $1\src_r4[1:0]
end
- attribute \src "libresoc.v:188887.3-188888.39"
- process $proc$libresoc.v:188887$12503
+ attribute \src "libresoc.v:187831.3-187832.39"
+ process $proc$libresoc.v:187831$12315
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:188889.3-188890.43"
- process $proc$libresoc.v:188889$12504
+ attribute \src "libresoc.v:187833.3-187834.43"
+ process $proc$libresoc.v:187833$12316
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:188891.3-188892.29"
- process $proc$libresoc.v:188891$12505
+ attribute \src "libresoc.v:187835.3-187836.29"
+ process $proc$libresoc.v:187835$12317
assign { } { }
assign $0\src_r4[1:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[1:0]
end
- attribute \src "libresoc.v:188893.3-188894.29"
- process $proc$libresoc.v:188893$12506
+ attribute \src "libresoc.v:187837.3-187838.29"
+ process $proc$libresoc.v:187837$12318
assign { } { }
assign $0\src_r3[0:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[0:0]
end
- attribute \src "libresoc.v:188895.3-188896.29"
- process $proc$libresoc.v:188895$12507
+ attribute \src "libresoc.v:187839.3-187840.29"
+ process $proc$libresoc.v:187839$12319
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:188897.3-188898.29"
- process $proc$libresoc.v:188897$12508
+ attribute \src "libresoc.v:187841.3-187842.29"
+ process $proc$libresoc.v:187841$12320
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:188899.3-188900.29"
- process $proc$libresoc.v:188899$12509
+ attribute \src "libresoc.v:187843.3-187844.29"
+ process $proc$libresoc.v:187843$12321
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:188901.3-188902.47"
- process $proc$libresoc.v:188901$12510
+ attribute \src "libresoc.v:187845.3-187846.47"
+ process $proc$libresoc.v:187845$12322
assign { } { }
assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next
sync posedge \coresync_clk
update \data_r2__xer_ca $0\data_r2__xer_ca[1:0]
end
- attribute \src "libresoc.v:188903.3-188904.53"
- process $proc$libresoc.v:188903$12511
+ attribute \src "libresoc.v:187847.3-187848.53"
+ process $proc$libresoc.v:187847$12323
assign { } { }
assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:188905.3-188906.43"
- process $proc$libresoc.v:188905$12512
+ attribute \src "libresoc.v:187849.3-187850.43"
+ process $proc$libresoc.v:187849$12324
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:188907.3-188908.49"
- process $proc$libresoc.v:188907$12513
+ attribute \src "libresoc.v:187851.3-187852.49"
+ process $proc$libresoc.v:187851$12325
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:188909.3-188910.37"
- process $proc$libresoc.v:188909$12514
+ attribute \src "libresoc.v:187853.3-187854.37"
+ process $proc$libresoc.v:187853$12326
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:188911.3-188912.43"
- process $proc$libresoc.v:188911$12515
+ attribute \src "libresoc.v:187855.3-187856.43"
+ process $proc$libresoc.v:187855$12327
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:188913.3-188914.79"
- process $proc$libresoc.v:188913$12516
+ attribute \src "libresoc.v:187857.3-187858.79"
+ process $proc$libresoc.v:187857$12328
assign { } { }
assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:188915.3-188916.75"
- process $proc$libresoc.v:188915$12517
+ attribute \src "libresoc.v:187859.3-187860.75"
+ process $proc$libresoc.v:187859$12329
assign { } { }
assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:188917.3-188918.89"
- process $proc$libresoc.v:188917$12518
+ attribute \src "libresoc.v:187861.3-187862.89"
+ process $proc$libresoc.v:187861$12330
assign { } { }
assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:188919.3-188920.85"
- process $proc$libresoc.v:188919$12519
+ attribute \src "libresoc.v:187863.3-187864.85"
+ process $proc$libresoc.v:187863$12331
assign { } { }
assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:188921.3-188922.73"
- process $proc$libresoc.v:188921$12520
+ attribute \src "libresoc.v:187865.3-187866.73"
+ process $proc$libresoc.v:187865$12332
assign { } { }
assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:188923.3-188924.73"
- process $proc$libresoc.v:188923$12521
+ attribute \src "libresoc.v:187867.3-187868.73"
+ process $proc$libresoc.v:187867$12333
assign { } { }
assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:188925.3-188926.73"
- process $proc$libresoc.v:188925$12522
+ attribute \src "libresoc.v:187869.3-187870.73"
+ process $proc$libresoc.v:187869$12334
assign { } { }
assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:188927.3-188928.73"
- process $proc$libresoc.v:188927$12523
+ attribute \src "libresoc.v:187871.3-187872.73"
+ process $proc$libresoc.v:187871$12335
assign { } { }
assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:188929.3-188930.79"
- process $proc$libresoc.v:188929$12524
+ attribute \src "libresoc.v:187873.3-187874.79"
+ process $proc$libresoc.v:187873$12336
assign { } { }
assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:188931.3-188932.79"
- process $proc$libresoc.v:188931$12525
+ attribute \src "libresoc.v:187875.3-187876.79"
+ process $proc$libresoc.v:187875$12337
assign { } { }
assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:188933.3-188934.83"
- process $proc$libresoc.v:188933$12526
+ attribute \src "libresoc.v:187877.3-187878.83"
+ process $proc$libresoc.v:187877$12338
assign { } { }
assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:188935.3-188936.85"
- process $proc$libresoc.v:188935$12527
+ attribute \src "libresoc.v:187879.3-187880.85"
+ process $proc$libresoc.v:187879$12339
assign { } { }
assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:188937.3-188938.77"
- process $proc$libresoc.v:188937$12528
+ attribute \src "libresoc.v:187881.3-187882.77"
+ process $proc$libresoc.v:187881$12340
assign { } { }
assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:188939.3-188940.79"
- process $proc$libresoc.v:188939$12529
+ attribute \src "libresoc.v:187883.3-187884.79"
+ process $proc$libresoc.v:187883$12341
assign { } { }
assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:188941.3-188942.77"
- process $proc$libresoc.v:188941$12530
+ attribute \src "libresoc.v:187885.3-187886.77"
+ process $proc$libresoc.v:187885$12342
assign { } { }
assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:188943.3-188944.79"
- process $proc$libresoc.v:188943$12531
+ attribute \src "libresoc.v:187887.3-187888.79"
+ process $proc$libresoc.v:187887$12343
assign { } { }
assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:188945.3-188946.69"
- process $proc$libresoc.v:188945$12532
+ attribute \src "libresoc.v:187889.3-187890.69"
+ process $proc$libresoc.v:187889$12344
assign { } { }
assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0]
end
- attribute \src "libresoc.v:188947.3-188948.39"
- process $proc$libresoc.v:188947$12533
+ attribute \src "libresoc.v:187891.3-187892.39"
+ process $proc$libresoc.v:187891$12345
assign { } { }
assign $0\req_l_r_req[2:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:188949.3-188950.39"
- process $proc$libresoc.v:188949$12534
+ attribute \src "libresoc.v:187893.3-187894.39"
+ process $proc$libresoc.v:187893$12346
assign { } { }
assign $0\req_l_s_req[2:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:188951.3-188952.39"
- process $proc$libresoc.v:188951$12535
+ attribute \src "libresoc.v:187895.3-187896.39"
+ process $proc$libresoc.v:187895$12347
assign { } { }
assign $0\src_l_r_src[4:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[4:0]
end
- attribute \src "libresoc.v:188953.3-188954.39"
- process $proc$libresoc.v:188953$12536
+ attribute \src "libresoc.v:187897.3-187898.39"
+ process $proc$libresoc.v:187897$12348
assign { } { }
assign $0\src_l_s_src[4:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[4:0]
end
- attribute \src "libresoc.v:188955.3-188956.39"
- process $proc$libresoc.v:188955$12537
+ attribute \src "libresoc.v:187899.3-187900.39"
+ process $proc$libresoc.v:187899$12349
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:188957.3-188958.39"
- process $proc$libresoc.v:188957$12538
+ attribute \src "libresoc.v:187901.3-187902.39"
+ process $proc$libresoc.v:187901$12350
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:188959.3-188960.39"
- process $proc$libresoc.v:188959$12539
+ attribute \src "libresoc.v:187903.3-187904.39"
+ process $proc$libresoc.v:187903$12351
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:188961.3-188962.39"
- process $proc$libresoc.v:188961$12540
+ attribute \src "libresoc.v:187905.3-187906.39"
+ process $proc$libresoc.v:187905$12352
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:188963.3-188964.41"
- process $proc$libresoc.v:188963$12541
+ attribute \src "libresoc.v:187907.3-187908.41"
+ process $proc$libresoc.v:187907$12353
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:188965.3-188966.41"
- process $proc$libresoc.v:188965$12542
+ attribute \src "libresoc.v:187909.3-187910.41"
+ process $proc$libresoc.v:187909$12354
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:188967.3-188968.37"
- process $proc$libresoc.v:188967$12543
+ attribute \src "libresoc.v:187911.3-187912.37"
+ process $proc$libresoc.v:187911$12355
assign { } { }
assign $0\prev_wr_go[2:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:188969.3-188970.46"
- process $proc$libresoc.v:188969$12544
+ attribute \src "libresoc.v:187913.3-187914.46"
+ process $proc$libresoc.v:187913$12356
assign { } { }
assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:188971.3-188972.25"
- process $proc$libresoc.v:188971$12545
+ attribute \src "libresoc.v:187915.3-187916.25"
+ process $proc$libresoc.v:187915$12357
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:189057.3-189066.6"
- process $proc$libresoc.v:189057$12546
+ attribute \src "libresoc.v:188001.3-188010.6"
+ process $proc$libresoc.v:188001$12358
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:189058.5-189058.29"
+ attribute \src "libresoc.v:188002.5-188002.29"
switch \initial
- attribute \src "libresoc.v:189058.9-189058.17"
+ attribute \src "libresoc.v:188002.9-188002.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:189067.3-189075.6"
- process $proc$libresoc.v:189067$12547
+ attribute \src "libresoc.v:188011.3-188019.6"
+ process $proc$libresoc.v:188011$12359
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$12548 $1\rok_l_s_rdok$next[0:0]$12549
- attribute \src "libresoc.v:189068.5-189068.29"
+ assign $0\rok_l_s_rdok$next[0:0]$12360 $1\rok_l_s_rdok$next[0:0]$12361
+ attribute \src "libresoc.v:188012.5-188012.29"
switch \initial
- attribute \src "libresoc.v:189068.9-189068.17"
+ attribute \src "libresoc.v:188012.9-188012.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$12549 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$12361 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$12549 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$12361 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12548
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12360
end
- attribute \src "libresoc.v:189076.3-189084.6"
- process $proc$libresoc.v:189076$12550
+ attribute \src "libresoc.v:188020.3-188028.6"
+ process $proc$libresoc.v:188020$12362
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$12551 $1\rok_l_r_rdok$next[0:0]$12552
- attribute \src "libresoc.v:189077.5-189077.29"
+ assign $0\rok_l_r_rdok$next[0:0]$12363 $1\rok_l_r_rdok$next[0:0]$12364
+ attribute \src "libresoc.v:188021.5-188021.29"
switch \initial
- attribute \src "libresoc.v:189077.9-189077.17"
+ attribute \src "libresoc.v:188021.9-188021.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$12552 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$12364 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$12552 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$12364 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12551
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12363
end
- attribute \src "libresoc.v:189085.3-189093.6"
- process $proc$libresoc.v:189085$12553
+ attribute \src "libresoc.v:188029.3-188037.6"
+ process $proc$libresoc.v:188029$12365
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$12554 $1\rst_l_s_rst$next[0:0]$12555
- attribute \src "libresoc.v:189086.5-189086.29"
+ assign $0\rst_l_s_rst$next[0:0]$12366 $1\rst_l_s_rst$next[0:0]$12367
+ attribute \src "libresoc.v:188030.5-188030.29"
switch \initial
- attribute \src "libresoc.v:189086.9-189086.17"
+ attribute \src "libresoc.v:188030.9-188030.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$12555 1'0
+ assign $1\rst_l_s_rst$next[0:0]$12367 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$12555 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$12367 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12554
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12366
end
- attribute \src "libresoc.v:189094.3-189102.6"
- process $proc$libresoc.v:189094$12556
+ attribute \src "libresoc.v:188038.3-188046.6"
+ process $proc$libresoc.v:188038$12368
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$12557 $1\rst_l_r_rst$next[0:0]$12558
- attribute \src "libresoc.v:189095.5-189095.29"
+ assign $0\rst_l_r_rst$next[0:0]$12369 $1\rst_l_r_rst$next[0:0]$12370
+ attribute \src "libresoc.v:188039.5-188039.29"
switch \initial
- attribute \src "libresoc.v:189095.9-189095.17"
+ attribute \src "libresoc.v:188039.9-188039.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$12558 1'1
+ assign $1\rst_l_r_rst$next[0:0]$12370 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$12558 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$12370 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12557
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12369
end
- attribute \src "libresoc.v:189103.3-189111.6"
- process $proc$libresoc.v:189103$12559
+ attribute \src "libresoc.v:188047.3-188055.6"
+ process $proc$libresoc.v:188047$12371
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$12560 $1\opc_l_s_opc$next[0:0]$12561
- attribute \src "libresoc.v:189104.5-189104.29"
+ assign $0\opc_l_s_opc$next[0:0]$12372 $1\opc_l_s_opc$next[0:0]$12373
+ attribute \src "libresoc.v:188048.5-188048.29"
switch \initial
- attribute \src "libresoc.v:189104.9-189104.17"
+ attribute \src "libresoc.v:188048.9-188048.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$12561 1'0
+ assign $1\opc_l_s_opc$next[0:0]$12373 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$12561 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$12373 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12560
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12372
end
- attribute \src "libresoc.v:189112.3-189120.6"
- process $proc$libresoc.v:189112$12562
+ attribute \src "libresoc.v:188056.3-188064.6"
+ process $proc$libresoc.v:188056$12374
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$12563 $1\opc_l_r_opc$next[0:0]$12564
- attribute \src "libresoc.v:189113.5-189113.29"
+ assign $0\opc_l_r_opc$next[0:0]$12375 $1\opc_l_r_opc$next[0:0]$12376
+ attribute \src "libresoc.v:188057.5-188057.29"
switch \initial
- attribute \src "libresoc.v:189113.9-189113.17"
+ attribute \src "libresoc.v:188057.9-188057.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$12564 1'1
+ assign $1\opc_l_r_opc$next[0:0]$12376 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$12564 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$12376 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12563
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12375
end
- attribute \src "libresoc.v:189121.3-189129.6"
- process $proc$libresoc.v:189121$12565
+ attribute \src "libresoc.v:188065.3-188073.6"
+ process $proc$libresoc.v:188065$12377
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[4:0]$12566 $1\src_l_s_src$next[4:0]$12567
- attribute \src "libresoc.v:189122.5-189122.29"
+ assign $0\src_l_s_src$next[4:0]$12378 $1\src_l_s_src$next[4:0]$12379
+ attribute \src "libresoc.v:188066.5-188066.29"
switch \initial
- attribute \src "libresoc.v:189122.9-189122.17"
+ attribute \src "libresoc.v:188066.9-188066.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[4:0]$12567 5'00000
+ assign $1\src_l_s_src$next[4:0]$12379 5'00000
case
- assign $1\src_l_s_src$next[4:0]$12567 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[4:0]$12379 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12566
+ update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12378
end
- attribute \src "libresoc.v:189130.3-189138.6"
- process $proc$libresoc.v:189130$12568
+ attribute \src "libresoc.v:188074.3-188082.6"
+ process $proc$libresoc.v:188074$12380
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[4:0]$12569 $1\src_l_r_src$next[4:0]$12570
- attribute \src "libresoc.v:189131.5-189131.29"
+ assign $0\src_l_r_src$next[4:0]$12381 $1\src_l_r_src$next[4:0]$12382
+ attribute \src "libresoc.v:188075.5-188075.29"
switch \initial
- attribute \src "libresoc.v:189131.9-189131.17"
+ attribute \src "libresoc.v:188075.9-188075.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[4:0]$12570 5'11111
+ assign $1\src_l_r_src$next[4:0]$12382 5'11111
case
- assign $1\src_l_r_src$next[4:0]$12570 \reset_r
+ assign $1\src_l_r_src$next[4:0]$12382 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12569
+ update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12381
end
- attribute \src "libresoc.v:189139.3-189147.6"
- process $proc$libresoc.v:189139$12571
+ attribute \src "libresoc.v:188083.3-188091.6"
+ process $proc$libresoc.v:188083$12383
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[2:0]$12572 $1\req_l_s_req$next[2:0]$12573
- attribute \src "libresoc.v:189140.5-189140.29"
+ assign $0\req_l_s_req$next[2:0]$12384 $1\req_l_s_req$next[2:0]$12385
+ attribute \src "libresoc.v:188084.5-188084.29"
switch \initial
- attribute \src "libresoc.v:189140.9-189140.17"
+ attribute \src "libresoc.v:188084.9-188084.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[2:0]$12573 3'000
+ assign $1\req_l_s_req$next[2:0]$12385 3'000
case
- assign $1\req_l_s_req$next[2:0]$12573 \$66
+ assign $1\req_l_s_req$next[2:0]$12385 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12572
+ update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12384
end
- attribute \src "libresoc.v:189148.3-189156.6"
- process $proc$libresoc.v:189148$12574
+ attribute \src "libresoc.v:188092.3-188100.6"
+ process $proc$libresoc.v:188092$12386
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[2:0]$12575 $1\req_l_r_req$next[2:0]$12576
- attribute \src "libresoc.v:189149.5-189149.29"
+ assign $0\req_l_r_req$next[2:0]$12387 $1\req_l_r_req$next[2:0]$12388
+ attribute \src "libresoc.v:188093.5-188093.29"
switch \initial
- attribute \src "libresoc.v:189149.9-189149.17"
+ attribute \src "libresoc.v:188093.9-188093.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[2:0]$12576 3'111
+ assign $1\req_l_r_req$next[2:0]$12388 3'111
case
- assign $1\req_l_r_req$next[2:0]$12576 \$68
+ assign $1\req_l_r_req$next[2:0]$12388 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12575
+ update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12387
end
- attribute \src "libresoc.v:189157.3-189194.6"
- process $proc$libresoc.v:189157$12577
+ attribute \src "libresoc.v:188101.3-188138.6"
+ process $proc$libresoc.v:188101$12389
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595
+ assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598
- assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599
- assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600
- assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601
- assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602
- assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603
- assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604
+ assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410
+ assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411
+ assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412
+ assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413
+ assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414
+ assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415
+ assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607
- assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608
+ assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419
+ assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611
- assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612
- assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613
- assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614
- assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615
- assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616
- assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617
- attribute \src "libresoc.v:189158.5-189158.29"
+ assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423
+ assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424
+ assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425
+ assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426
+ assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427
+ assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428
+ assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429
+ attribute \src "libresoc.v:188102.5-188102.29"
switch \initial
- attribute \src "libresoc.v:189158.9-189158.17"
+ attribute \src "libresoc.v:188102.9-188102.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
+ assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
case
- assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 \alu_shift_rot0_sr_op__fn_unit
- assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 \alu_shift_rot0_sr_op__imm_data__data
- assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 \alu_shift_rot0_sr_op__imm_data__ok
- assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 \alu_shift_rot0_sr_op__input_carry
- assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 \alu_shift_rot0_sr_op__input_cr
- assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 \alu_shift_rot0_sr_op__insn
- assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 \alu_shift_rot0_sr_op__insn_type
- assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 \alu_shift_rot0_sr_op__invert_in
- assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 \alu_shift_rot0_sr_op__is_32bit
- assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 \alu_shift_rot0_sr_op__is_signed
- assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 \alu_shift_rot0_sr_op__oe__oe
- assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 \alu_shift_rot0_sr_op__oe__ok
- assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 \alu_shift_rot0_sr_op__output_carry
- assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 \alu_shift_rot0_sr_op__output_cr
- assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 \alu_shift_rot0_sr_op__rc__ok
- assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 \alu_shift_rot0_sr_op__rc__rc
- assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 \alu_shift_rot0_sr_op__write_cr0
+ assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 \alu_shift_rot0_sr_op__fn_unit
+ assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 \alu_shift_rot0_sr_op__imm_data__data
+ assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 \alu_shift_rot0_sr_op__imm_data__ok
+ assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 \alu_shift_rot0_sr_op__input_carry
+ assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 \alu_shift_rot0_sr_op__input_cr
+ assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 \alu_shift_rot0_sr_op__insn
+ assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 \alu_shift_rot0_sr_op__insn_type
+ assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 \alu_shift_rot0_sr_op__invert_in
+ assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 \alu_shift_rot0_sr_op__is_32bit
+ assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 \alu_shift_rot0_sr_op__is_signed
+ assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 \alu_shift_rot0_sr_op__oe__oe
+ assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 \alu_shift_rot0_sr_op__oe__ok
+ assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 \alu_shift_rot0_sr_op__output_carry
+ assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 \alu_shift_rot0_sr_op__output_cr
+ assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 \alu_shift_rot0_sr_op__rc__ok
+ assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 \alu_shift_rot0_sr_op__rc__rc
+ assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 \alu_shift_rot0_sr_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 1'0
- assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 1'0
- assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 1'0
- assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 1'0
- assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 1'0
+ assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 1'0
+ assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 1'0
+ assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 1'0
+ assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 1'0
+ assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 1'0
case
- assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596
- assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597
- assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605
- assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606
- assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609
- assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610
+ assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408
+ assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409
+ assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417
+ assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418
+ assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421
+ assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422
end
sync always
- update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578
- update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579
- update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580
- update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581
- update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582
- update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583
- update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584
- update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585
- update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586
- update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587
- update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588
- update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589
- update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590
- update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591
- update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592
- update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593
- update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594
+ update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390
+ update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391
+ update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392
+ update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393
+ update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394
+ update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395
+ update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396
+ update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397
+ update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398
+ update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399
+ update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400
+ update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401
+ update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402
+ update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403
+ update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404
+ update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405
+ update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406
end
- attribute \src "libresoc.v:189195.3-189216.6"
- process $proc$libresoc.v:189195$12618
+ attribute \src "libresoc.v:188139.3-188160.6"
+ process $proc$libresoc.v:188139$12430
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$12619 $2\data_r0__o$next[63:0]$12623
+ assign $0\data_r0__o$next[63:0]$12431 $2\data_r0__o$next[63:0]$12435
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$12620 $3\data_r0__o_ok$next[0:0]$12625
- attribute \src "libresoc.v:189196.5-189196.29"
+ assign $0\data_r0__o_ok$next[0:0]$12432 $3\data_r0__o_ok$next[0:0]$12437
+ attribute \src "libresoc.v:188140.5-188140.29"
switch \initial
- attribute \src "libresoc.v:189196.9-189196.17"
+ attribute \src "libresoc.v:188140.9-188140.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$12622 $1\data_r0__o$next[63:0]$12621 } { \o_ok \alu_shift_rot0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$12434 $1\data_r0__o$next[63:0]$12433 } { \o_ok \alu_shift_rot0_o }
case
- assign $1\data_r0__o$next[63:0]$12621 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$12622 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$12433 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$12434 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$12624 $2\data_r0__o$next[63:0]$12623 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$12436 $2\data_r0__o$next[63:0]$12435 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$12623 $1\data_r0__o$next[63:0]$12621
- assign $2\data_r0__o_ok$next[0:0]$12624 $1\data_r0__o_ok$next[0:0]$12622
+ assign $2\data_r0__o$next[63:0]$12435 $1\data_r0__o$next[63:0]$12433
+ assign $2\data_r0__o_ok$next[0:0]$12436 $1\data_r0__o_ok$next[0:0]$12434
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$12625 1'0
+ assign $3\data_r0__o_ok$next[0:0]$12437 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$12625 $2\data_r0__o_ok$next[0:0]$12624
+ assign $3\data_r0__o_ok$next[0:0]$12437 $2\data_r0__o_ok$next[0:0]$12436
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$12619
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12620
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$12431
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12432
end
- attribute \src "libresoc.v:189217.3-189238.6"
- process $proc$libresoc.v:189217$12626
+ attribute \src "libresoc.v:188161.3-188182.6"
+ process $proc$libresoc.v:188161$12438
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$12627 $2\data_r1__cr_a$next[3:0]$12631
+ assign $0\data_r1__cr_a$next[3:0]$12439 $2\data_r1__cr_a$next[3:0]$12443
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$12628 $3\data_r1__cr_a_ok$next[0:0]$12633
- attribute \src "libresoc.v:189218.5-189218.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$12440 $3\data_r1__cr_a_ok$next[0:0]$12445
+ attribute \src "libresoc.v:188162.5-188162.29"
switch \initial
- attribute \src "libresoc.v:189218.9-189218.17"
+ attribute \src "libresoc.v:188162.9-188162.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$12630 $1\data_r1__cr_a$next[3:0]$12629 } { \cr_a_ok \alu_shift_rot0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$12442 $1\data_r1__cr_a$next[3:0]$12441 } { \cr_a_ok \alu_shift_rot0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$12629 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$12630 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$12441 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$12442 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$12632 $2\data_r1__cr_a$next[3:0]$12631 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$12444 $2\data_r1__cr_a$next[3:0]$12443 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$12631 $1\data_r1__cr_a$next[3:0]$12629
- assign $2\data_r1__cr_a_ok$next[0:0]$12632 $1\data_r1__cr_a_ok$next[0:0]$12630
+ assign $2\data_r1__cr_a$next[3:0]$12443 $1\data_r1__cr_a$next[3:0]$12441
+ assign $2\data_r1__cr_a_ok$next[0:0]$12444 $1\data_r1__cr_a_ok$next[0:0]$12442
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$12633 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$12445 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$12633 $2\data_r1__cr_a_ok$next[0:0]$12632
+ assign $3\data_r1__cr_a_ok$next[0:0]$12445 $2\data_r1__cr_a_ok$next[0:0]$12444
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12627
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12628
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12439
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12440
end
- attribute \src "libresoc.v:189239.3-189260.6"
- process $proc$libresoc.v:189239$12634
+ attribute \src "libresoc.v:188183.3-188204.6"
+ process $proc$libresoc.v:188183$12446
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ca$next[1:0]$12635 $2\data_r2__xer_ca$next[1:0]$12639
+ assign $0\data_r2__xer_ca$next[1:0]$12447 $2\data_r2__xer_ca$next[1:0]$12451
assign { } { }
- assign $0\data_r2__xer_ca_ok$next[0:0]$12636 $3\data_r2__xer_ca_ok$next[0:0]$12641
- attribute \src "libresoc.v:189240.5-189240.29"
+ assign $0\data_r2__xer_ca_ok$next[0:0]$12448 $3\data_r2__xer_ca_ok$next[0:0]$12453
+ attribute \src "libresoc.v:188184.5-188184.29"
switch \initial
- attribute \src "libresoc.v:189240.9-189240.17"
+ attribute \src "libresoc.v:188184.9-188184.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ca_ok$next[0:0]$12638 $1\data_r2__xer_ca$next[1:0]$12637 } { \xer_ca_ok \alu_shift_rot0_xer_ca }
+ assign { $1\data_r2__xer_ca_ok$next[0:0]$12450 $1\data_r2__xer_ca$next[1:0]$12449 } { \xer_ca_ok \alu_shift_rot0_xer_ca }
case
- assign $1\data_r2__xer_ca$next[1:0]$12637 \data_r2__xer_ca
- assign $1\data_r2__xer_ca_ok$next[0:0]$12638 \data_r2__xer_ca_ok
+ assign $1\data_r2__xer_ca$next[1:0]$12449 \data_r2__xer_ca
+ assign $1\data_r2__xer_ca_ok$next[0:0]$12450 \data_r2__xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ca_ok$next[0:0]$12640 $2\data_r2__xer_ca$next[1:0]$12639 } 3'000
+ assign { $2\data_r2__xer_ca_ok$next[0:0]$12452 $2\data_r2__xer_ca$next[1:0]$12451 } 3'000
case
- assign $2\data_r2__xer_ca$next[1:0]$12639 $1\data_r2__xer_ca$next[1:0]$12637
- assign $2\data_r2__xer_ca_ok$next[0:0]$12640 $1\data_r2__xer_ca_ok$next[0:0]$12638
+ assign $2\data_r2__xer_ca$next[1:0]$12451 $1\data_r2__xer_ca$next[1:0]$12449
+ assign $2\data_r2__xer_ca_ok$next[0:0]$12452 $1\data_r2__xer_ca_ok$next[0:0]$12450
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ca_ok$next[0:0]$12641 1'0
+ assign $3\data_r2__xer_ca_ok$next[0:0]$12453 1'0
case
- assign $3\data_r2__xer_ca_ok$next[0:0]$12641 $2\data_r2__xer_ca_ok$next[0:0]$12640
+ assign $3\data_r2__xer_ca_ok$next[0:0]$12453 $2\data_r2__xer_ca_ok$next[0:0]$12452
end
sync always
- update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12635
- update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12636
+ update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12447
+ update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12448
end
- attribute \src "libresoc.v:189261.3-189270.6"
- process $proc$libresoc.v:189261$12642
+ attribute \src "libresoc.v:188205.3-188214.6"
+ process $proc$libresoc.v:188205$12454
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$12643 $1\src_r0$next[63:0]$12644
- attribute \src "libresoc.v:189262.5-189262.29"
+ assign $0\src_r0$next[63:0]$12455 $1\src_r0$next[63:0]$12456
+ attribute \src "libresoc.v:188206.5-188206.29"
switch \initial
- attribute \src "libresoc.v:189262.9-189262.17"
+ attribute \src "libresoc.v:188206.9-188206.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$12644 \src1_i
+ assign $1\src_r0$next[63:0]$12456 \src1_i
case
- assign $1\src_r0$next[63:0]$12644 \src_r0
+ assign $1\src_r0$next[63:0]$12456 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$12643
+ update \src_r0$next $0\src_r0$next[63:0]$12455
end
- attribute \src "libresoc.v:189271.3-189280.6"
- process $proc$libresoc.v:189271$12645
+ attribute \src "libresoc.v:188215.3-188224.6"
+ process $proc$libresoc.v:188215$12457
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$12646 $1\src_r1$next[63:0]$12647
- attribute \src "libresoc.v:189272.5-189272.29"
+ assign $0\src_r1$next[63:0]$12458 $1\src_r1$next[63:0]$12459
+ attribute \src "libresoc.v:188216.5-188216.29"
switch \initial
- attribute \src "libresoc.v:189272.9-189272.17"
+ attribute \src "libresoc.v:188216.9-188216.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$12647 \src_or_imm
+ assign $1\src_r1$next[63:0]$12459 \src_or_imm
case
- assign $1\src_r1$next[63:0]$12647 \src_r1
+ assign $1\src_r1$next[63:0]$12459 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$12646
+ update \src_r1$next $0\src_r1$next[63:0]$12458
end
- attribute \src "libresoc.v:189281.3-189290.6"
- process $proc$libresoc.v:189281$12648
+ attribute \src "libresoc.v:188225.3-188234.6"
+ process $proc$libresoc.v:188225$12460
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$12649 $1\src_r2$next[63:0]$12650
- attribute \src "libresoc.v:189282.5-189282.29"
+ assign $0\src_r2$next[63:0]$12461 $1\src_r2$next[63:0]$12462
+ attribute \src "libresoc.v:188226.5-188226.29"
switch \initial
- attribute \src "libresoc.v:189282.9-189282.17"
+ attribute \src "libresoc.v:188226.9-188226.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$12650 \src3_i
+ assign $1\src_r2$next[63:0]$12462 \src3_i
case
- assign $1\src_r2$next[63:0]$12650 \src_r2
+ assign $1\src_r2$next[63:0]$12462 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$12649
+ update \src_r2$next $0\src_r2$next[63:0]$12461
end
- attribute \src "libresoc.v:189291.3-189300.6"
- process $proc$libresoc.v:189291$12651
+ attribute \src "libresoc.v:188235.3-188244.6"
+ process $proc$libresoc.v:188235$12463
assign { } { }
assign { } { }
- assign $0\src_r3$next[0:0]$12652 $1\src_r3$next[0:0]$12653
- attribute \src "libresoc.v:189292.5-189292.29"
+ assign $0\src_r3$next[0:0]$12464 $1\src_r3$next[0:0]$12465
+ attribute \src "libresoc.v:188236.5-188236.29"
switch \initial
- attribute \src "libresoc.v:189292.9-189292.17"
+ attribute \src "libresoc.v:188236.9-188236.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[0:0]$12653 \src4_i
+ assign $1\src_r3$next[0:0]$12465 \src4_i
case
- assign $1\src_r3$next[0:0]$12653 \src_r3
+ assign $1\src_r3$next[0:0]$12465 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[0:0]$12652
+ update \src_r3$next $0\src_r3$next[0:0]$12464
end
- attribute \src "libresoc.v:189301.3-189310.6"
- process $proc$libresoc.v:189301$12654
+ attribute \src "libresoc.v:188245.3-188254.6"
+ process $proc$libresoc.v:188245$12466
assign { } { }
assign { } { }
- assign $0\src_r4$next[1:0]$12655 $1\src_r4$next[1:0]$12656
- attribute \src "libresoc.v:189302.5-189302.29"
+ assign $0\src_r4$next[1:0]$12467 $1\src_r4$next[1:0]$12468
+ attribute \src "libresoc.v:188246.5-188246.29"
switch \initial
- attribute \src "libresoc.v:189302.9-189302.17"
+ attribute \src "libresoc.v:188246.9-188246.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[1:0]$12656 \src5_i
+ assign $1\src_r4$next[1:0]$12468 \src5_i
case
- assign $1\src_r4$next[1:0]$12656 \src_r4
+ assign $1\src_r4$next[1:0]$12468 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[1:0]$12655
+ update \src_r4$next $0\src_r4$next[1:0]$12467
end
- attribute \src "libresoc.v:189311.3-189319.6"
- process $proc$libresoc.v:189311$12657
+ attribute \src "libresoc.v:188255.3-188263.6"
+ process $proc$libresoc.v:188255$12469
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$12658 $1\alui_l_r_alui$next[0:0]$12659
- attribute \src "libresoc.v:189312.5-189312.29"
+ assign $0\alui_l_r_alui$next[0:0]$12470 $1\alui_l_r_alui$next[0:0]$12471
+ attribute \src "libresoc.v:188256.5-188256.29"
switch \initial
- attribute \src "libresoc.v:189312.9-189312.17"
+ attribute \src "libresoc.v:188256.9-188256.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$12659 1'1
+ assign $1\alui_l_r_alui$next[0:0]$12471 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$12659 \$90
+ assign $1\alui_l_r_alui$next[0:0]$12471 \$90
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12658
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12470
end
- attribute \src "libresoc.v:189320.3-189328.6"
- process $proc$libresoc.v:189320$12660
+ attribute \src "libresoc.v:188264.3-188272.6"
+ process $proc$libresoc.v:188264$12472
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$12661 $1\alu_l_r_alu$next[0:0]$12662
- attribute \src "libresoc.v:189321.5-189321.29"
+ assign $0\alu_l_r_alu$next[0:0]$12473 $1\alu_l_r_alu$next[0:0]$12474
+ attribute \src "libresoc.v:188265.5-188265.29"
switch \initial
- attribute \src "libresoc.v:189321.9-189321.17"
+ attribute \src "libresoc.v:188265.9-188265.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$12662 1'1
+ assign $1\alu_l_r_alu$next[0:0]$12474 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$12662 \$92
+ assign $1\alu_l_r_alu$next[0:0]$12474 \$92
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12661
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12473
end
- attribute \src "libresoc.v:189329.3-189338.6"
- process $proc$libresoc.v:189329$12663
+ attribute \src "libresoc.v:188273.3-188282.6"
+ process $proc$libresoc.v:188273$12475
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:189330.5-189330.29"
+ attribute \src "libresoc.v:188274.5-188274.29"
switch \initial
- attribute \src "libresoc.v:189330.9-189330.17"
+ attribute \src "libresoc.v:188274.9-188274.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:189339.3-189348.6"
- process $proc$libresoc.v:189339$12664
+ attribute \src "libresoc.v:188283.3-188292.6"
+ process $proc$libresoc.v:188283$12476
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:189340.5-189340.29"
+ attribute \src "libresoc.v:188284.5-188284.29"
switch \initial
- attribute \src "libresoc.v:189340.9-189340.17"
+ attribute \src "libresoc.v:188284.9-188284.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:189349.3-189358.6"
- process $proc$libresoc.v:189349$12665
+ attribute \src "libresoc.v:188293.3-188302.6"
+ process $proc$libresoc.v:188293$12477
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:189350.5-189350.29"
+ attribute \src "libresoc.v:188294.5-188294.29"
switch \initial
- attribute \src "libresoc.v:189350.9-189350.17"
+ attribute \src "libresoc.v:188294.9-188294.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:189359.3-189367.6"
- process $proc$libresoc.v:189359$12666
+ attribute \src "libresoc.v:188303.3-188311.6"
+ process $proc$libresoc.v:188303$12478
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[2:0]$12667 $1\prev_wr_go$next[2:0]$12668
- attribute \src "libresoc.v:189360.5-189360.29"
+ assign $0\prev_wr_go$next[2:0]$12479 $1\prev_wr_go$next[2:0]$12480
+ attribute \src "libresoc.v:188304.5-188304.29"
switch \initial
- attribute \src "libresoc.v:189360.9-189360.17"
+ attribute \src "libresoc.v:188304.9-188304.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[2:0]$12668 3'000
- case
- assign $1\prev_wr_go$next[2:0]$12668 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12667
- end
- connect \$100 $not$libresoc.v:188828$12444_Y
- connect \$102 $and$libresoc.v:188829$12445_Y
- connect \$104 $and$libresoc.v:188830$12446_Y
- connect \$106 $and$libresoc.v:188831$12447_Y
- connect \$108 $and$libresoc.v:188832$12448_Y
- connect \$10 $and$libresoc.v:188833$12449_Y
- connect \$110 $and$libresoc.v:188834$12450_Y
- connect \$112 $and$libresoc.v:188835$12451_Y
- connect \$114 $and$libresoc.v:188836$12452_Y
- connect \$116 $and$libresoc.v:188837$12453_Y
- connect \$118 $and$libresoc.v:188838$12454_Y
- connect \$12 $not$libresoc.v:188839$12455_Y
- connect \$14 $and$libresoc.v:188840$12456_Y
- connect \$16 $not$libresoc.v:188841$12457_Y
- connect \$18 $and$libresoc.v:188842$12458_Y
- connect \$20 $and$libresoc.v:188843$12459_Y
- connect \$24 $not$libresoc.v:188844$12460_Y
- connect \$26 $and$libresoc.v:188845$12461_Y
- connect \$23 $reduce_or$libresoc.v:188846$12462_Y
- connect \$22 $not$libresoc.v:188847$12463_Y
- connect \$2 $and$libresoc.v:188848$12464_Y
- connect \$30 $and$libresoc.v:188849$12465_Y
- connect \$32 $reduce_or$libresoc.v:188850$12466_Y
- connect \$34 $reduce_or$libresoc.v:188851$12467_Y
- connect \$36 $or$libresoc.v:188852$12468_Y
- connect \$38 $not$libresoc.v:188853$12469_Y
- connect \$40 $and$libresoc.v:188854$12470_Y
- connect \$42 $and$libresoc.v:188855$12471_Y
- connect \$44 $eq$libresoc.v:188856$12472_Y
- connect \$46 $and$libresoc.v:188857$12473_Y
- connect \$48 $eq$libresoc.v:188858$12474_Y
- connect \$50 $and$libresoc.v:188859$12475_Y
- connect \$52 $and$libresoc.v:188860$12476_Y
- connect \$54 $and$libresoc.v:188861$12477_Y
- connect \$56 $or$libresoc.v:188862$12478_Y
- connect \$58 $or$libresoc.v:188863$12479_Y
- connect \$5 $not$libresoc.v:188864$12480_Y
- connect \$60 $or$libresoc.v:188865$12481_Y
- connect \$62 $or$libresoc.v:188866$12482_Y
- connect \$64 $and$libresoc.v:188867$12483_Y
- connect \$66 $and$libresoc.v:188868$12484_Y
- connect \$68 $or$libresoc.v:188869$12485_Y
- connect \$70 $and$libresoc.v:188870$12486_Y
- connect \$72 $and$libresoc.v:188871$12487_Y
- connect \$74 $and$libresoc.v:188872$12488_Y
- connect \$76 $ternary$libresoc.v:188873$12489_Y
- connect \$78 $ternary$libresoc.v:188874$12490_Y
- connect \$7 $or$libresoc.v:188875$12491_Y
- connect \$80 $ternary$libresoc.v:188876$12492_Y
- connect \$82 $ternary$libresoc.v:188877$12493_Y
- connect \$84 $ternary$libresoc.v:188878$12494_Y
- connect \$86 $ternary$libresoc.v:188879$12495_Y
- connect \$88 $ternary$libresoc.v:188880$12496_Y
- connect \$4 $reduce_and$libresoc.v:188881$12497_Y
- connect \$90 $and$libresoc.v:188882$12498_Y
- connect \$92 $and$libresoc.v:188883$12499_Y
- connect \$94 $and$libresoc.v:188884$12500_Y
- connect \$96 $not$libresoc.v:188885$12501_Y
- connect \$98 $and$libresoc.v:188886$12502_Y
+ assign $1\prev_wr_go$next[2:0]$12480 3'000
+ case
+ assign $1\prev_wr_go$next[2:0]$12480 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12479
+ end
+ connect \$100 $not$libresoc.v:187772$12256_Y
+ connect \$102 $and$libresoc.v:187773$12257_Y
+ connect \$104 $and$libresoc.v:187774$12258_Y
+ connect \$106 $and$libresoc.v:187775$12259_Y
+ connect \$108 $and$libresoc.v:187776$12260_Y
+ connect \$10 $and$libresoc.v:187777$12261_Y
+ connect \$110 $and$libresoc.v:187778$12262_Y
+ connect \$112 $and$libresoc.v:187779$12263_Y
+ connect \$114 $and$libresoc.v:187780$12264_Y
+ connect \$116 $and$libresoc.v:187781$12265_Y
+ connect \$118 $and$libresoc.v:187782$12266_Y
+ connect \$12 $not$libresoc.v:187783$12267_Y
+ connect \$14 $and$libresoc.v:187784$12268_Y
+ connect \$16 $not$libresoc.v:187785$12269_Y
+ connect \$18 $and$libresoc.v:187786$12270_Y
+ connect \$20 $and$libresoc.v:187787$12271_Y
+ connect \$24 $not$libresoc.v:187788$12272_Y
+ connect \$26 $and$libresoc.v:187789$12273_Y
+ connect \$23 $reduce_or$libresoc.v:187790$12274_Y
+ connect \$22 $not$libresoc.v:187791$12275_Y
+ connect \$2 $and$libresoc.v:187792$12276_Y
+ connect \$30 $and$libresoc.v:187793$12277_Y
+ connect \$32 $reduce_or$libresoc.v:187794$12278_Y
+ connect \$34 $reduce_or$libresoc.v:187795$12279_Y
+ connect \$36 $or$libresoc.v:187796$12280_Y
+ connect \$38 $not$libresoc.v:187797$12281_Y
+ connect \$40 $and$libresoc.v:187798$12282_Y
+ connect \$42 $and$libresoc.v:187799$12283_Y
+ connect \$44 $eq$libresoc.v:187800$12284_Y
+ connect \$46 $and$libresoc.v:187801$12285_Y
+ connect \$48 $eq$libresoc.v:187802$12286_Y
+ connect \$50 $and$libresoc.v:187803$12287_Y
+ connect \$52 $and$libresoc.v:187804$12288_Y
+ connect \$54 $and$libresoc.v:187805$12289_Y
+ connect \$56 $or$libresoc.v:187806$12290_Y
+ connect \$58 $or$libresoc.v:187807$12291_Y
+ connect \$5 $not$libresoc.v:187808$12292_Y
+ connect \$60 $or$libresoc.v:187809$12293_Y
+ connect \$62 $or$libresoc.v:187810$12294_Y
+ connect \$64 $and$libresoc.v:187811$12295_Y
+ connect \$66 $and$libresoc.v:187812$12296_Y
+ connect \$68 $or$libresoc.v:187813$12297_Y
+ connect \$70 $and$libresoc.v:187814$12298_Y
+ connect \$72 $and$libresoc.v:187815$12299_Y
+ connect \$74 $and$libresoc.v:187816$12300_Y
+ connect \$76 $ternary$libresoc.v:187817$12301_Y
+ connect \$78 $ternary$libresoc.v:187818$12302_Y
+ connect \$7 $or$libresoc.v:187819$12303_Y
+ connect \$80 $ternary$libresoc.v:187820$12304_Y
+ connect \$82 $ternary$libresoc.v:187821$12305_Y
+ connect \$84 $ternary$libresoc.v:187822$12306_Y
+ connect \$86 $ternary$libresoc.v:187823$12307_Y
+ connect \$88 $ternary$libresoc.v:187824$12308_Y
+ connect \$4 $reduce_and$libresoc.v:187825$12309_Y
+ connect \$90 $and$libresoc.v:187826$12310_Y
+ connect \$92 $and$libresoc.v:187827$12311_Y
+ connect \$94 $and$libresoc.v:187828$12312_Y
+ connect \$96 $not$libresoc.v:187829$12313_Y
+ connect \$98 $and$libresoc.v:187830$12314_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$112
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:189404.1-189584.10"
+attribute \src "libresoc.v:188348.1-188528.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.spr"
attribute \generator "nMigen"
module \spr
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 7 $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 64 $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 64 $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830
- attribute \src "libresoc.v:189554.3-189557.6"
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 7 $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642
+ attribute \src "libresoc.v:188498.3-188501.6"
wire width 7 $0\_0_[6:0]
- attribute \src "libresoc.v:189405.7-189405.20"
+ attribute \src "libresoc.v:188349.7-188349.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:189561.3-189569.6"
- wire $0\ren_delay$next[0:0]$12837
- attribute \src "libresoc.v:189559.3-189560.35"
+ attribute \src "libresoc.v:188505.3-188513.6"
+ wire $0\ren_delay$next[0:0]$12649
+ attribute \src "libresoc.v:188503.3-188504.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:189570.3-189579.6"
+ attribute \src "libresoc.v:188514.3-188523.6"
wire width 64 $0\spr1__data_o[63:0]
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 7 $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 64 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832
- attribute \src "libresoc.v:189554.3-189557.6"
- wire width 64 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833
- attribute \src "libresoc.v:189561.3-189569.6"
- wire $1\ren_delay$next[0:0]$12838
- attribute \src "libresoc.v:189421.7-189421.23"
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 7 $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644
+ attribute \src "libresoc.v:188498.3-188501.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645
+ attribute \src "libresoc.v:188505.3-188513.6"
+ wire $1\ren_delay$next[0:0]$12650
+ attribute \src "libresoc.v:188365.7-188365.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:189570.3-189579.6"
+ attribute \src "libresoc.v:188514.3-188523.6"
wire width 64 $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:189558.26-189558.32"
- wire width 64 $memrd$\memory$libresoc.v:189558$12834_DATA
+ attribute \src "libresoc.v:188502.26-188502.32"
+ wire width 64 $memrd$\memory$libresoc.v:188502$12646_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 7 $memwr$\memory$libresoc.v:189556$12826_ADDR
+ wire width 7 $memwr$\memory$libresoc.v:188500$12638_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:189556$12826_DATA
+ wire width 64 $memwr$\memory$libresoc.v:188500$12638_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:189556$12826_EN
- attribute \src "libresoc.v:189553.13-189553.16"
+ wire width 64 $memwr$\memory$libresoc.v:188500$12638_EN
+ attribute \src "libresoc.v:188497.13-188497.16"
wire width 7 \_0_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 8 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:189405.7-189405.15"
+ attribute \src "libresoc.v:188349.7-188349.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 7 \memory_r_addr
wire input 4 \spr1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 7 \spr1__wen
- attribute \src "libresoc.v:189437.14-189437.20"
+ attribute \src "libresoc.v:188381.14-188381.20"
memory width 64 size 113 \memory
- attribute \src "libresoc.v:189439.5-189439.37"
- cell $meminit $meminit$\memory$libresoc.v:189439$12840
+ attribute \src "libresoc.v:188383.5-188383.37"
+ cell $meminit $meminit$\memory$libresoc.v:188383$12652
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12840
+ parameter \PRIORITY 12652
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189440.5-189440.37"
- cell $meminit $meminit$\memory$libresoc.v:189440$12841
+ attribute \src "libresoc.v:188384.5-188384.37"
+ cell $meminit $meminit$\memory$libresoc.v:188384$12653
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12841
+ parameter \PRIORITY 12653
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189441.5-189441.37"
- cell $meminit $meminit$\memory$libresoc.v:189441$12842
+ attribute \src "libresoc.v:188385.5-188385.37"
+ cell $meminit $meminit$\memory$libresoc.v:188385$12654
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12842
+ parameter \PRIORITY 12654
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189442.5-189442.37"
- cell $meminit $meminit$\memory$libresoc.v:189442$12843
+ attribute \src "libresoc.v:188386.5-188386.37"
+ cell $meminit $meminit$\memory$libresoc.v:188386$12655
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12843
+ parameter \PRIORITY 12655
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189443.5-189443.37"
- cell $meminit $meminit$\memory$libresoc.v:189443$12844
+ attribute \src "libresoc.v:188387.5-188387.37"
+ cell $meminit $meminit$\memory$libresoc.v:188387$12656
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12844
+ parameter \PRIORITY 12656
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189444.5-189444.37"
- cell $meminit $meminit$\memory$libresoc.v:189444$12845
+ attribute \src "libresoc.v:188388.5-188388.37"
+ cell $meminit $meminit$\memory$libresoc.v:188388$12657
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12845
+ parameter \PRIORITY 12657
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189445.5-189445.37"
- cell $meminit $meminit$\memory$libresoc.v:189445$12846
+ attribute \src "libresoc.v:188389.5-188389.37"
+ cell $meminit $meminit$\memory$libresoc.v:188389$12658
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12846
+ parameter \PRIORITY 12658
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189446.5-189446.37"
- cell $meminit $meminit$\memory$libresoc.v:189446$12847
+ attribute \src "libresoc.v:188390.5-188390.37"
+ cell $meminit $meminit$\memory$libresoc.v:188390$12659
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12847
+ parameter \PRIORITY 12659
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189447.5-189447.37"
- cell $meminit $meminit$\memory$libresoc.v:189447$12848
+ attribute \src "libresoc.v:188391.5-188391.37"
+ cell $meminit $meminit$\memory$libresoc.v:188391$12660
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12848
+ parameter \PRIORITY 12660
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 8
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189448.5-189448.37"
- cell $meminit $meminit$\memory$libresoc.v:189448$12849
+ attribute \src "libresoc.v:188392.5-188392.37"
+ cell $meminit $meminit$\memory$libresoc.v:188392$12661
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12849
+ parameter \PRIORITY 12661
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 9
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189449.5-189449.38"
- cell $meminit $meminit$\memory$libresoc.v:189449$12850
+ attribute \src "libresoc.v:188393.5-188393.38"
+ cell $meminit $meminit$\memory$libresoc.v:188393$12662
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12850
+ parameter \PRIORITY 12662
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 10
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189450.5-189450.38"
- cell $meminit $meminit$\memory$libresoc.v:189450$12851
+ attribute \src "libresoc.v:188394.5-188394.38"
+ cell $meminit $meminit$\memory$libresoc.v:188394$12663
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12851
+ parameter \PRIORITY 12663
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 11
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189451.5-189451.38"
- cell $meminit $meminit$\memory$libresoc.v:189451$12852
+ attribute \src "libresoc.v:188395.5-188395.38"
+ cell $meminit $meminit$\memory$libresoc.v:188395$12664
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12852
+ parameter \PRIORITY 12664
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 12
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189452.5-189452.38"
- cell $meminit $meminit$\memory$libresoc.v:189452$12853
+ attribute \src "libresoc.v:188396.5-188396.38"
+ cell $meminit $meminit$\memory$libresoc.v:188396$12665
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12853
+ parameter \PRIORITY 12665
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 13
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189453.5-189453.38"
- cell $meminit $meminit$\memory$libresoc.v:189453$12854
+ attribute \src "libresoc.v:188397.5-188397.38"
+ cell $meminit $meminit$\memory$libresoc.v:188397$12666
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12854
+ parameter \PRIORITY 12666
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 14
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189454.5-189454.38"
- cell $meminit $meminit$\memory$libresoc.v:189454$12855
+ attribute \src "libresoc.v:188398.5-188398.38"
+ cell $meminit $meminit$\memory$libresoc.v:188398$12667
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12855
+ parameter \PRIORITY 12667
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 15
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189455.5-189455.38"
- cell $meminit $meminit$\memory$libresoc.v:189455$12856
+ attribute \src "libresoc.v:188399.5-188399.38"
+ cell $meminit $meminit$\memory$libresoc.v:188399$12668
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12856
+ parameter \PRIORITY 12668
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 16
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189456.5-189456.38"
- cell $meminit $meminit$\memory$libresoc.v:189456$12857
+ attribute \src "libresoc.v:188400.5-188400.38"
+ cell $meminit $meminit$\memory$libresoc.v:188400$12669
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12857
+ parameter \PRIORITY 12669
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 17
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189457.5-189457.38"
- cell $meminit $meminit$\memory$libresoc.v:189457$12858
+ attribute \src "libresoc.v:188401.5-188401.38"
+ cell $meminit $meminit$\memory$libresoc.v:188401$12670
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12858
+ parameter \PRIORITY 12670
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 18
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189458.5-189458.38"
- cell $meminit $meminit$\memory$libresoc.v:189458$12859
+ attribute \src "libresoc.v:188402.5-188402.38"
+ cell $meminit $meminit$\memory$libresoc.v:188402$12671
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12859
+ parameter \PRIORITY 12671
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 19
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189459.5-189459.38"
- cell $meminit $meminit$\memory$libresoc.v:189459$12860
+ attribute \src "libresoc.v:188403.5-188403.38"
+ cell $meminit $meminit$\memory$libresoc.v:188403$12672
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12860
+ parameter \PRIORITY 12672
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 20
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189460.5-189460.38"
- cell $meminit $meminit$\memory$libresoc.v:189460$12861
+ attribute \src "libresoc.v:188404.5-188404.38"
+ cell $meminit $meminit$\memory$libresoc.v:188404$12673
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12861
+ parameter \PRIORITY 12673
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 21
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189461.5-189461.38"
- cell $meminit $meminit$\memory$libresoc.v:189461$12862
+ attribute \src "libresoc.v:188405.5-188405.38"
+ cell $meminit $meminit$\memory$libresoc.v:188405$12674
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12862
+ parameter \PRIORITY 12674
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 22
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189462.5-189462.38"
- cell $meminit $meminit$\memory$libresoc.v:189462$12863
+ attribute \src "libresoc.v:188406.5-188406.38"
+ cell $meminit $meminit$\memory$libresoc.v:188406$12675
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12863
+ parameter \PRIORITY 12675
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 23
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189463.5-189463.38"
- cell $meminit $meminit$\memory$libresoc.v:189463$12864
+ attribute \src "libresoc.v:188407.5-188407.38"
+ cell $meminit $meminit$\memory$libresoc.v:188407$12676
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12864
+ parameter \PRIORITY 12676
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 24
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189464.5-189464.38"
- cell $meminit $meminit$\memory$libresoc.v:189464$12865
+ attribute \src "libresoc.v:188408.5-188408.38"
+ cell $meminit $meminit$\memory$libresoc.v:188408$12677
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12865
+ parameter \PRIORITY 12677
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 25
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189465.5-189465.38"
- cell $meminit $meminit$\memory$libresoc.v:189465$12866
+ attribute \src "libresoc.v:188409.5-188409.38"
+ cell $meminit $meminit$\memory$libresoc.v:188409$12678
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12866
+ parameter \PRIORITY 12678
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 26
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189466.5-189466.38"
- cell $meminit $meminit$\memory$libresoc.v:189466$12867
+ attribute \src "libresoc.v:188410.5-188410.38"
+ cell $meminit $meminit$\memory$libresoc.v:188410$12679
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12867
+ parameter \PRIORITY 12679
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 27
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189467.5-189467.38"
- cell $meminit $meminit$\memory$libresoc.v:189467$12868
+ attribute \src "libresoc.v:188411.5-188411.38"
+ cell $meminit $meminit$\memory$libresoc.v:188411$12680
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12868
+ parameter \PRIORITY 12680
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 28
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189468.5-189468.38"
- cell $meminit $meminit$\memory$libresoc.v:189468$12869
+ attribute \src "libresoc.v:188412.5-188412.38"
+ cell $meminit $meminit$\memory$libresoc.v:188412$12681
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12869
+ parameter \PRIORITY 12681
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 29
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189469.5-189469.38"
- cell $meminit $meminit$\memory$libresoc.v:189469$12870
+ attribute \src "libresoc.v:188413.5-188413.38"
+ cell $meminit $meminit$\memory$libresoc.v:188413$12682
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12870
+ parameter \PRIORITY 12682
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 30
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189470.5-189470.38"
- cell $meminit $meminit$\memory$libresoc.v:189470$12871
+ attribute \src "libresoc.v:188414.5-188414.38"
+ cell $meminit $meminit$\memory$libresoc.v:188414$12683
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12871
+ parameter \PRIORITY 12683
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 31
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189471.5-189471.38"
- cell $meminit $meminit$\memory$libresoc.v:189471$12872
+ attribute \src "libresoc.v:188415.5-188415.38"
+ cell $meminit $meminit$\memory$libresoc.v:188415$12684
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12872
+ parameter \PRIORITY 12684
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 32
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189472.5-189472.38"
- cell $meminit $meminit$\memory$libresoc.v:189472$12873
+ attribute \src "libresoc.v:188416.5-188416.38"
+ cell $meminit $meminit$\memory$libresoc.v:188416$12685
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12873
+ parameter \PRIORITY 12685
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 33
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189473.5-189473.38"
- cell $meminit $meminit$\memory$libresoc.v:189473$12874
+ attribute \src "libresoc.v:188417.5-188417.38"
+ cell $meminit $meminit$\memory$libresoc.v:188417$12686
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12874
+ parameter \PRIORITY 12686
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 34
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189474.5-189474.38"
- cell $meminit $meminit$\memory$libresoc.v:189474$12875
+ attribute \src "libresoc.v:188418.5-188418.38"
+ cell $meminit $meminit$\memory$libresoc.v:188418$12687
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12875
+ parameter \PRIORITY 12687
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 35
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189475.5-189475.38"
- cell $meminit $meminit$\memory$libresoc.v:189475$12876
+ attribute \src "libresoc.v:188419.5-188419.38"
+ cell $meminit $meminit$\memory$libresoc.v:188419$12688
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12876
+ parameter \PRIORITY 12688
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 36
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189476.5-189476.38"
- cell $meminit $meminit$\memory$libresoc.v:189476$12877
+ attribute \src "libresoc.v:188420.5-188420.38"
+ cell $meminit $meminit$\memory$libresoc.v:188420$12689
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12877
+ parameter \PRIORITY 12689
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 37
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189477.5-189477.38"
- cell $meminit $meminit$\memory$libresoc.v:189477$12878
+ attribute \src "libresoc.v:188421.5-188421.38"
+ cell $meminit $meminit$\memory$libresoc.v:188421$12690
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12878
+ parameter \PRIORITY 12690
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 38
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189478.5-189478.38"
- cell $meminit $meminit$\memory$libresoc.v:189478$12879
+ attribute \src "libresoc.v:188422.5-188422.38"
+ cell $meminit $meminit$\memory$libresoc.v:188422$12691
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12879
+ parameter \PRIORITY 12691
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 39
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189479.5-189479.38"
- cell $meminit $meminit$\memory$libresoc.v:189479$12880
+ attribute \src "libresoc.v:188423.5-188423.38"
+ cell $meminit $meminit$\memory$libresoc.v:188423$12692
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12880
+ parameter \PRIORITY 12692
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 40
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189480.5-189480.38"
- cell $meminit $meminit$\memory$libresoc.v:189480$12881
+ attribute \src "libresoc.v:188424.5-188424.38"
+ cell $meminit $meminit$\memory$libresoc.v:188424$12693
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12881
+ parameter \PRIORITY 12693
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 41
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189481.5-189481.38"
- cell $meminit $meminit$\memory$libresoc.v:189481$12882
+ attribute \src "libresoc.v:188425.5-188425.38"
+ cell $meminit $meminit$\memory$libresoc.v:188425$12694
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12882
+ parameter \PRIORITY 12694
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 42
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189482.5-189482.38"
- cell $meminit $meminit$\memory$libresoc.v:189482$12883
+ attribute \src "libresoc.v:188426.5-188426.38"
+ cell $meminit $meminit$\memory$libresoc.v:188426$12695
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12883
+ parameter \PRIORITY 12695
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 43
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189483.5-189483.38"
- cell $meminit $meminit$\memory$libresoc.v:189483$12884
+ attribute \src "libresoc.v:188427.5-188427.38"
+ cell $meminit $meminit$\memory$libresoc.v:188427$12696
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12884
+ parameter \PRIORITY 12696
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 44
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189484.5-189484.38"
- cell $meminit $meminit$\memory$libresoc.v:189484$12885
+ attribute \src "libresoc.v:188428.5-188428.38"
+ cell $meminit $meminit$\memory$libresoc.v:188428$12697
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12885
+ parameter \PRIORITY 12697
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 45
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189485.5-189485.38"
- cell $meminit $meminit$\memory$libresoc.v:189485$12886
+ attribute \src "libresoc.v:188429.5-188429.38"
+ cell $meminit $meminit$\memory$libresoc.v:188429$12698
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12886
+ parameter \PRIORITY 12698
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 46
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189486.5-189486.38"
- cell $meminit $meminit$\memory$libresoc.v:189486$12887
+ attribute \src "libresoc.v:188430.5-188430.38"
+ cell $meminit $meminit$\memory$libresoc.v:188430$12699
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12887
+ parameter \PRIORITY 12699
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 47
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189487.5-189487.38"
- cell $meminit $meminit$\memory$libresoc.v:189487$12888
+ attribute \src "libresoc.v:188431.5-188431.38"
+ cell $meminit $meminit$\memory$libresoc.v:188431$12700
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12888
+ parameter \PRIORITY 12700
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 48
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189488.5-189488.38"
- cell $meminit $meminit$\memory$libresoc.v:189488$12889
+ attribute \src "libresoc.v:188432.5-188432.38"
+ cell $meminit $meminit$\memory$libresoc.v:188432$12701
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12889
+ parameter \PRIORITY 12701
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 49
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189489.5-189489.38"
- cell $meminit $meminit$\memory$libresoc.v:189489$12890
+ attribute \src "libresoc.v:188433.5-188433.38"
+ cell $meminit $meminit$\memory$libresoc.v:188433$12702
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12890
+ parameter \PRIORITY 12702
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 50
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189490.5-189490.38"
- cell $meminit $meminit$\memory$libresoc.v:189490$12891
+ attribute \src "libresoc.v:188434.5-188434.38"
+ cell $meminit $meminit$\memory$libresoc.v:188434$12703
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12891
+ parameter \PRIORITY 12703
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 51
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189491.5-189491.38"
- cell $meminit $meminit$\memory$libresoc.v:189491$12892
+ attribute \src "libresoc.v:188435.5-188435.38"
+ cell $meminit $meminit$\memory$libresoc.v:188435$12704
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12892
+ parameter \PRIORITY 12704
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 52
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189492.5-189492.38"
- cell $meminit $meminit$\memory$libresoc.v:189492$12893
+ attribute \src "libresoc.v:188436.5-188436.38"
+ cell $meminit $meminit$\memory$libresoc.v:188436$12705
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12893
+ parameter \PRIORITY 12705
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 53
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189493.5-189493.38"
- cell $meminit $meminit$\memory$libresoc.v:189493$12894
+ attribute \src "libresoc.v:188437.5-188437.38"
+ cell $meminit $meminit$\memory$libresoc.v:188437$12706
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12894
+ parameter \PRIORITY 12706
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 54
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189494.5-189494.38"
- cell $meminit $meminit$\memory$libresoc.v:189494$12895
+ attribute \src "libresoc.v:188438.5-188438.38"
+ cell $meminit $meminit$\memory$libresoc.v:188438$12707
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12895
+ parameter \PRIORITY 12707
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 55
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189495.5-189495.38"
- cell $meminit $meminit$\memory$libresoc.v:189495$12896
+ attribute \src "libresoc.v:188439.5-188439.38"
+ cell $meminit $meminit$\memory$libresoc.v:188439$12708
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12896
+ parameter \PRIORITY 12708
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 56
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189496.5-189496.38"
- cell $meminit $meminit$\memory$libresoc.v:189496$12897
+ attribute \src "libresoc.v:188440.5-188440.38"
+ cell $meminit $meminit$\memory$libresoc.v:188440$12709
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12897
+ parameter \PRIORITY 12709
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 57
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189497.5-189497.38"
- cell $meminit $meminit$\memory$libresoc.v:189497$12898
+ attribute \src "libresoc.v:188441.5-188441.38"
+ cell $meminit $meminit$\memory$libresoc.v:188441$12710
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12898
+ parameter \PRIORITY 12710
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 58
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189498.5-189498.38"
- cell $meminit $meminit$\memory$libresoc.v:189498$12899
+ attribute \src "libresoc.v:188442.5-188442.38"
+ cell $meminit $meminit$\memory$libresoc.v:188442$12711
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12899
+ parameter \PRIORITY 12711
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 59
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189499.5-189499.38"
- cell $meminit $meminit$\memory$libresoc.v:189499$12900
+ attribute \src "libresoc.v:188443.5-188443.38"
+ cell $meminit $meminit$\memory$libresoc.v:188443$12712
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12900
+ parameter \PRIORITY 12712
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 60
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189500.5-189500.38"
- cell $meminit $meminit$\memory$libresoc.v:189500$12901
+ attribute \src "libresoc.v:188444.5-188444.38"
+ cell $meminit $meminit$\memory$libresoc.v:188444$12713
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12901
+ parameter \PRIORITY 12713
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 61
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189501.5-189501.38"
- cell $meminit $meminit$\memory$libresoc.v:189501$12902
+ attribute \src "libresoc.v:188445.5-188445.38"
+ cell $meminit $meminit$\memory$libresoc.v:188445$12714
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12902
+ parameter \PRIORITY 12714
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 62
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189502.5-189502.38"
- cell $meminit $meminit$\memory$libresoc.v:189502$12903
+ attribute \src "libresoc.v:188446.5-188446.38"
+ cell $meminit $meminit$\memory$libresoc.v:188446$12715
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12903
+ parameter \PRIORITY 12715
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 63
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189503.5-189503.38"
- cell $meminit $meminit$\memory$libresoc.v:189503$12904
+ attribute \src "libresoc.v:188447.5-188447.38"
+ cell $meminit $meminit$\memory$libresoc.v:188447$12716
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12904
+ parameter \PRIORITY 12716
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 64
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189504.5-189504.38"
- cell $meminit $meminit$\memory$libresoc.v:189504$12905
+ attribute \src "libresoc.v:188448.5-188448.38"
+ cell $meminit $meminit$\memory$libresoc.v:188448$12717
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12905
+ parameter \PRIORITY 12717
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 65
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189505.5-189505.38"
- cell $meminit $meminit$\memory$libresoc.v:189505$12906
+ attribute \src "libresoc.v:188449.5-188449.38"
+ cell $meminit $meminit$\memory$libresoc.v:188449$12718
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12906
+ parameter \PRIORITY 12718
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 66
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189506.5-189506.38"
- cell $meminit $meminit$\memory$libresoc.v:189506$12907
+ attribute \src "libresoc.v:188450.5-188450.38"
+ cell $meminit $meminit$\memory$libresoc.v:188450$12719
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12907
+ parameter \PRIORITY 12719
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 67
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189507.5-189507.38"
- cell $meminit $meminit$\memory$libresoc.v:189507$12908
+ attribute \src "libresoc.v:188451.5-188451.38"
+ cell $meminit $meminit$\memory$libresoc.v:188451$12720
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12908
+ parameter \PRIORITY 12720
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 68
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189508.5-189508.38"
- cell $meminit $meminit$\memory$libresoc.v:189508$12909
+ attribute \src "libresoc.v:188452.5-188452.38"
+ cell $meminit $meminit$\memory$libresoc.v:188452$12721
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12909
+ parameter \PRIORITY 12721
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 69
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189509.5-189509.38"
- cell $meminit $meminit$\memory$libresoc.v:189509$12910
+ attribute \src "libresoc.v:188453.5-188453.38"
+ cell $meminit $meminit$\memory$libresoc.v:188453$12722
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12910
+ parameter \PRIORITY 12722
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 70
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189510.5-189510.38"
- cell $meminit $meminit$\memory$libresoc.v:189510$12911
+ attribute \src "libresoc.v:188454.5-188454.38"
+ cell $meminit $meminit$\memory$libresoc.v:188454$12723
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12911
+ parameter \PRIORITY 12723
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 71
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189511.5-189511.38"
- cell $meminit $meminit$\memory$libresoc.v:189511$12912
+ attribute \src "libresoc.v:188455.5-188455.38"
+ cell $meminit $meminit$\memory$libresoc.v:188455$12724
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12912
+ parameter \PRIORITY 12724
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 72
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189512.5-189512.38"
- cell $meminit $meminit$\memory$libresoc.v:189512$12913
+ attribute \src "libresoc.v:188456.5-188456.38"
+ cell $meminit $meminit$\memory$libresoc.v:188456$12725
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12913
+ parameter \PRIORITY 12725
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 73
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189513.5-189513.38"
- cell $meminit $meminit$\memory$libresoc.v:189513$12914
+ attribute \src "libresoc.v:188457.5-188457.38"
+ cell $meminit $meminit$\memory$libresoc.v:188457$12726
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12914
+ parameter \PRIORITY 12726
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 74
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189514.5-189514.38"
- cell $meminit $meminit$\memory$libresoc.v:189514$12915
+ attribute \src "libresoc.v:188458.5-188458.38"
+ cell $meminit $meminit$\memory$libresoc.v:188458$12727
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12915
+ parameter \PRIORITY 12727
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 75
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189515.5-189515.38"
- cell $meminit $meminit$\memory$libresoc.v:189515$12916
+ attribute \src "libresoc.v:188459.5-188459.38"
+ cell $meminit $meminit$\memory$libresoc.v:188459$12728
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12916
+ parameter \PRIORITY 12728
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 76
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189516.5-189516.38"
- cell $meminit $meminit$\memory$libresoc.v:189516$12917
+ attribute \src "libresoc.v:188460.5-188460.38"
+ cell $meminit $meminit$\memory$libresoc.v:188460$12729
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12917
+ parameter \PRIORITY 12729
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 77
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189517.5-189517.38"
- cell $meminit $meminit$\memory$libresoc.v:189517$12918
+ attribute \src "libresoc.v:188461.5-188461.38"
+ cell $meminit $meminit$\memory$libresoc.v:188461$12730
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12918
+ parameter \PRIORITY 12730
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 78
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189518.5-189518.38"
- cell $meminit $meminit$\memory$libresoc.v:189518$12919
+ attribute \src "libresoc.v:188462.5-188462.38"
+ cell $meminit $meminit$\memory$libresoc.v:188462$12731
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12919
+ parameter \PRIORITY 12731
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 79
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189519.5-189519.38"
- cell $meminit $meminit$\memory$libresoc.v:189519$12920
+ attribute \src "libresoc.v:188463.5-188463.38"
+ cell $meminit $meminit$\memory$libresoc.v:188463$12732
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12920
+ parameter \PRIORITY 12732
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 80
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189520.5-189520.38"
- cell $meminit $meminit$\memory$libresoc.v:189520$12921
+ attribute \src "libresoc.v:188464.5-188464.38"
+ cell $meminit $meminit$\memory$libresoc.v:188464$12733
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12921
+ parameter \PRIORITY 12733
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 81
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189521.5-189521.38"
- cell $meminit $meminit$\memory$libresoc.v:189521$12922
+ attribute \src "libresoc.v:188465.5-188465.38"
+ cell $meminit $meminit$\memory$libresoc.v:188465$12734
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12922
+ parameter \PRIORITY 12734
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 82
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189522.5-189522.38"
- cell $meminit $meminit$\memory$libresoc.v:189522$12923
+ attribute \src "libresoc.v:188466.5-188466.38"
+ cell $meminit $meminit$\memory$libresoc.v:188466$12735
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12923
+ parameter \PRIORITY 12735
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 83
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189523.5-189523.38"
- cell $meminit $meminit$\memory$libresoc.v:189523$12924
+ attribute \src "libresoc.v:188467.5-188467.38"
+ cell $meminit $meminit$\memory$libresoc.v:188467$12736
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12924
+ parameter \PRIORITY 12736
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 84
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189524.5-189524.38"
- cell $meminit $meminit$\memory$libresoc.v:189524$12925
+ attribute \src "libresoc.v:188468.5-188468.38"
+ cell $meminit $meminit$\memory$libresoc.v:188468$12737
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12925
+ parameter \PRIORITY 12737
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 85
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189525.5-189525.38"
- cell $meminit $meminit$\memory$libresoc.v:189525$12926
+ attribute \src "libresoc.v:188469.5-188469.38"
+ cell $meminit $meminit$\memory$libresoc.v:188469$12738
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12926
+ parameter \PRIORITY 12738
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 86
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189526.5-189526.38"
- cell $meminit $meminit$\memory$libresoc.v:189526$12927
+ attribute \src "libresoc.v:188470.5-188470.38"
+ cell $meminit $meminit$\memory$libresoc.v:188470$12739
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12927
+ parameter \PRIORITY 12739
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 87
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189527.5-189527.38"
- cell $meminit $meminit$\memory$libresoc.v:189527$12928
+ attribute \src "libresoc.v:188471.5-188471.38"
+ cell $meminit $meminit$\memory$libresoc.v:188471$12740
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12928
+ parameter \PRIORITY 12740
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 88
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189528.5-189528.38"
- cell $meminit $meminit$\memory$libresoc.v:189528$12929
+ attribute \src "libresoc.v:188472.5-188472.38"
+ cell $meminit $meminit$\memory$libresoc.v:188472$12741
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12929
+ parameter \PRIORITY 12741
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 89
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189529.5-189529.38"
- cell $meminit $meminit$\memory$libresoc.v:189529$12930
+ attribute \src "libresoc.v:188473.5-188473.38"
+ cell $meminit $meminit$\memory$libresoc.v:188473$12742
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12930
+ parameter \PRIORITY 12742
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 90
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189530.5-189530.38"
- cell $meminit $meminit$\memory$libresoc.v:189530$12931
+ attribute \src "libresoc.v:188474.5-188474.38"
+ cell $meminit $meminit$\memory$libresoc.v:188474$12743
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12931
+ parameter \PRIORITY 12743
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 91
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189531.5-189531.38"
- cell $meminit $meminit$\memory$libresoc.v:189531$12932
+ attribute \src "libresoc.v:188475.5-188475.38"
+ cell $meminit $meminit$\memory$libresoc.v:188475$12744
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12932
+ parameter \PRIORITY 12744
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 92
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189532.5-189532.38"
- cell $meminit $meminit$\memory$libresoc.v:189532$12933
+ attribute \src "libresoc.v:188476.5-188476.38"
+ cell $meminit $meminit$\memory$libresoc.v:188476$12745
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12933
+ parameter \PRIORITY 12745
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 93
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189533.5-189533.38"
- cell $meminit $meminit$\memory$libresoc.v:189533$12934
+ attribute \src "libresoc.v:188477.5-188477.38"
+ cell $meminit $meminit$\memory$libresoc.v:188477$12746
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12934
+ parameter \PRIORITY 12746
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 94
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189534.5-189534.38"
- cell $meminit $meminit$\memory$libresoc.v:189534$12935
+ attribute \src "libresoc.v:188478.5-188478.38"
+ cell $meminit $meminit$\memory$libresoc.v:188478$12747
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12935
+ parameter \PRIORITY 12747
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 95
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189535.5-189535.38"
- cell $meminit $meminit$\memory$libresoc.v:189535$12936
+ attribute \src "libresoc.v:188479.5-188479.38"
+ cell $meminit $meminit$\memory$libresoc.v:188479$12748
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12936
+ parameter \PRIORITY 12748
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 96
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189536.5-189536.38"
- cell $meminit $meminit$\memory$libresoc.v:189536$12937
+ attribute \src "libresoc.v:188480.5-188480.38"
+ cell $meminit $meminit$\memory$libresoc.v:188480$12749
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12937
+ parameter \PRIORITY 12749
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 97
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189537.5-189537.38"
- cell $meminit $meminit$\memory$libresoc.v:189537$12938
+ attribute \src "libresoc.v:188481.5-188481.38"
+ cell $meminit $meminit$\memory$libresoc.v:188481$12750
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12938
+ parameter \PRIORITY 12750
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 98
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189538.5-189538.38"
- cell $meminit $meminit$\memory$libresoc.v:189538$12939
+ attribute \src "libresoc.v:188482.5-188482.38"
+ cell $meminit $meminit$\memory$libresoc.v:188482$12751
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12939
+ parameter \PRIORITY 12751
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 99
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189539.5-189539.39"
- cell $meminit $meminit$\memory$libresoc.v:189539$12940
+ attribute \src "libresoc.v:188483.5-188483.39"
+ cell $meminit $meminit$\memory$libresoc.v:188483$12752
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12940
+ parameter \PRIORITY 12752
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 100
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189540.5-189540.39"
- cell $meminit $meminit$\memory$libresoc.v:189540$12941
+ attribute \src "libresoc.v:188484.5-188484.39"
+ cell $meminit $meminit$\memory$libresoc.v:188484$12753
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12941
+ parameter \PRIORITY 12753
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 101
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189541.5-189541.39"
- cell $meminit $meminit$\memory$libresoc.v:189541$12942
+ attribute \src "libresoc.v:188485.5-188485.39"
+ cell $meminit $meminit$\memory$libresoc.v:188485$12754
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12942
+ parameter \PRIORITY 12754
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 102
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189542.5-189542.39"
- cell $meminit $meminit$\memory$libresoc.v:189542$12943
+ attribute \src "libresoc.v:188486.5-188486.39"
+ cell $meminit $meminit$\memory$libresoc.v:188486$12755
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12943
+ parameter \PRIORITY 12755
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 103
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189543.5-189543.39"
- cell $meminit $meminit$\memory$libresoc.v:189543$12944
+ attribute \src "libresoc.v:188487.5-188487.39"
+ cell $meminit $meminit$\memory$libresoc.v:188487$12756
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12944
+ parameter \PRIORITY 12756
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 104
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189544.5-189544.39"
- cell $meminit $meminit$\memory$libresoc.v:189544$12945
+ attribute \src "libresoc.v:188488.5-188488.39"
+ cell $meminit $meminit$\memory$libresoc.v:188488$12757
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12945
+ parameter \PRIORITY 12757
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 105
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189545.5-189545.39"
- cell $meminit $meminit$\memory$libresoc.v:189545$12946
+ attribute \src "libresoc.v:188489.5-188489.39"
+ cell $meminit $meminit$\memory$libresoc.v:188489$12758
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12946
+ parameter \PRIORITY 12758
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 106
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189546.5-189546.39"
- cell $meminit $meminit$\memory$libresoc.v:189546$12947
+ attribute \src "libresoc.v:188490.5-188490.39"
+ cell $meminit $meminit$\memory$libresoc.v:188490$12759
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12947
+ parameter \PRIORITY 12759
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 107
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189547.5-189547.39"
- cell $meminit $meminit$\memory$libresoc.v:189547$12948
+ attribute \src "libresoc.v:188491.5-188491.39"
+ cell $meminit $meminit$\memory$libresoc.v:188491$12760
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12948
+ parameter \PRIORITY 12760
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 108
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189548.5-189548.39"
- cell $meminit $meminit$\memory$libresoc.v:189548$12949
+ attribute \src "libresoc.v:188492.5-188492.39"
+ cell $meminit $meminit$\memory$libresoc.v:188492$12761
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12949
+ parameter \PRIORITY 12761
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 109
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189549.5-189549.39"
- cell $meminit $meminit$\memory$libresoc.v:189549$12950
+ attribute \src "libresoc.v:188493.5-188493.39"
+ cell $meminit $meminit$\memory$libresoc.v:188493$12762
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12950
+ parameter \PRIORITY 12762
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 110
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189550.5-189550.39"
- cell $meminit $meminit$\memory$libresoc.v:189550$12951
+ attribute \src "libresoc.v:188494.5-188494.39"
+ cell $meminit $meminit$\memory$libresoc.v:188494$12763
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12951
+ parameter \PRIORITY 12763
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 111
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189551.5-189551.39"
- cell $meminit $meminit$\memory$libresoc.v:189551$12952
+ attribute \src "libresoc.v:188495.5-188495.39"
+ cell $meminit $meminit$\memory$libresoc.v:188495$12764
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12952
+ parameter \PRIORITY 12764
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 112
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:189558.26-189558.32"
- cell $memrd $memrd$\memory$libresoc.v:189558$12834
+ attribute \src "libresoc.v:188502.26-188502.32"
+ cell $memrd $memrd$\memory$libresoc.v:188502$12646
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:189558$12834_DATA
+ connect \DATA $memrd$\memory$libresoc.v:188502$12646_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$12955
+ process $proc$libresoc.v:0$12767
sync always
sync init
end
- attribute \src "libresoc.v:189405.7-189405.20"
- process $proc$libresoc.v:189405$12953
+ attribute \src "libresoc.v:188349.7-188349.20"
+ process $proc$libresoc.v:188349$12765
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:189421.7-189421.23"
- process $proc$libresoc.v:189421$12954
+ attribute \src "libresoc.v:188365.7-188365.23"
+ process $proc$libresoc.v:188365$12766
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:189554.3-189557.6"
- process $proc$libresoc.v:189554$12827
+ attribute \src "libresoc.v:188498.3-188501.6"
+ process $proc$libresoc.v:188498$12639
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\_0_[6:0] \memory_r_addr
- assign $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828 $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831
- assign $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832
- assign $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833
- attribute \src "libresoc.v:189556.5-189556.61"
+ assign $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640 $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643
+ assign $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644
+ assign $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645
+ attribute \src "libresoc.v:188500.5-188500.61"
switch \memory_w_en
- attribute \src "libresoc.v:189556.9-189556.20"
+ attribute \src "libresoc.v:188500.9-188500.20"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 \memory_w_addr
- assign $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 \memory_w_data
- assign $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 \memory_w_addr
+ assign $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 \memory_w_data
+ assign $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 64'1111111111111111111111111111111111111111111111111111111111111111
case
- assign $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 7'xxxxxxx
- assign $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 7'xxxxxxx
+ assign $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \coresync_clk
update \_0_ $0\_0_[6:0]
- update $memwr$\memory$libresoc.v:189556$12826_ADDR $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828
- update $memwr$\memory$libresoc.v:189556$12826_DATA $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829
- update $memwr$\memory$libresoc.v:189556$12826_EN $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830
- attribute \src "libresoc.v:189556.22-189556.60"
- memwr \memory $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 0'
+ update $memwr$\memory$libresoc.v:188500$12638_ADDR $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640
+ update $memwr$\memory$libresoc.v:188500$12638_DATA $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641
+ update $memwr$\memory$libresoc.v:188500$12638_EN $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642
+ attribute \src "libresoc.v:188500.22-188500.60"
+ memwr \memory $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 0'
end
- attribute \src "libresoc.v:189559.3-189560.35"
- process $proc$libresoc.v:189559$12835
+ attribute \src "libresoc.v:188503.3-188504.35"
+ process $proc$libresoc.v:188503$12647
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:189561.3-189569.6"
- process $proc$libresoc.v:189561$12836
+ attribute \src "libresoc.v:188505.3-188513.6"
+ process $proc$libresoc.v:188505$12648
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$12837 $1\ren_delay$next[0:0]$12838
- attribute \src "libresoc.v:189562.5-189562.29"
+ assign $0\ren_delay$next[0:0]$12649 $1\ren_delay$next[0:0]$12650
+ attribute \src "libresoc.v:188506.5-188506.29"
switch \initial
- attribute \src "libresoc.v:189562.9-189562.17"
+ attribute \src "libresoc.v:188506.9-188506.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$12838 1'0
+ assign $1\ren_delay$next[0:0]$12650 1'0
case
- assign $1\ren_delay$next[0:0]$12838 \spr1__ren
+ assign $1\ren_delay$next[0:0]$12650 \spr1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$12837
+ update \ren_delay$next $0\ren_delay$next[0:0]$12649
end
- attribute \src "libresoc.v:189570.3-189579.6"
- process $proc$libresoc.v:189570$12839
+ attribute \src "libresoc.v:188514.3-188523.6"
+ process $proc$libresoc.v:188514$12651
assign { } { }
assign { } { }
assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:189571.5-189571.29"
+ attribute \src "libresoc.v:188515.5-188515.29"
switch \initial
- attribute \src "libresoc.v:189571.9-189571.17"
+ attribute \src "libresoc.v:188515.9-188515.17"
case 1'1
case
end
sync always
update \spr1__data_o $0\spr1__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:189558$12834_DATA
+ connect \memory_r_data $memrd$\memory$libresoc.v:188502$12646_DATA
connect \memory_w_data \spr1__data_i
connect \memory_w_en \spr1__wen
connect \memory_w_addr \spr1__addr$1
connect \memory_r_addr \spr1__addr
end
-attribute \src "libresoc.v:189588.1-190841.10"
+attribute \src "libresoc.v:188532.1-189785.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0"
attribute \generator "nMigen"
module \spr0
- attribute \src "libresoc.v:190338.3-190339.25"
+ attribute \src "libresoc.v:189282.3-189283.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:190336.3-190337.40"
+ attribute \src "libresoc.v:189280.3-189281.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:190732.3-190740.6"
- wire $0\alu_l_r_alu$next[0:0]$13169
- attribute \src "libresoc.v:190266.3-190267.39"
+ attribute \src "libresoc.v:189676.3-189684.6"
+ wire $0\alu_l_r_alu$next[0:0]$12981
+ attribute \src "libresoc.v:189210.3-189211.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091
- attribute \src "libresoc.v:190308.3-190309.65"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903
+ attribute \src "libresoc.v:189252.3-189253.65"
wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13092
- attribute \src "libresoc.v:190310.3-190311.59"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12904
+ attribute \src "libresoc.v:189254.3-189255.59"
wire width 32 $0\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13093
- attribute \src "libresoc.v:190306.3-190307.69"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12905
+ attribute \src "libresoc.v:189250.3-189251.69"
wire width 7 $0\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094
- attribute \src "libresoc.v:190312.3-190313.67"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906
+ attribute \src "libresoc.v:189256.3-189257.67"
wire $0\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:190723.3-190731.6"
- wire $0\alui_l_r_alui$next[0:0]$13166
- attribute \src "libresoc.v:190268.3-190269.43"
+ attribute \src "libresoc.v:189667.3-189675.6"
+ wire $0\alui_l_r_alui$next[0:0]$12978
+ attribute \src "libresoc.v:189212.3-189213.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:190531.3-190552.6"
- wire width 64 $0\data_r0__o$next[63:0]$13100
- attribute \src "libresoc.v:190302.3-190303.37"
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire width 64 $0\data_r0__o$next[63:0]$12912
+ attribute \src "libresoc.v:189246.3-189247.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:190531.3-190552.6"
- wire $0\data_r0__o_ok$next[0:0]$13101
- attribute \src "libresoc.v:190304.3-190305.43"
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire $0\data_r0__o_ok$next[0:0]$12913
+ attribute \src "libresoc.v:189248.3-189249.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:190553.3-190574.6"
- wire width 64 $0\data_r1__spr1$next[63:0]$13108
- attribute \src "libresoc.v:190298.3-190299.43"
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire width 64 $0\data_r1__spr1$next[63:0]$12920
+ attribute \src "libresoc.v:189242.3-189243.43"
wire width 64 $0\data_r1__spr1[63:0]
- attribute \src "libresoc.v:190553.3-190574.6"
- wire $0\data_r1__spr1_ok$next[0:0]$13109
- attribute \src "libresoc.v:190300.3-190301.49"
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire $0\data_r1__spr1_ok$next[0:0]$12921
+ attribute \src "libresoc.v:189244.3-189245.49"
wire $0\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:190575.3-190596.6"
- wire width 64 $0\data_r2__fast1$next[63:0]$13116
- attribute \src "libresoc.v:190294.3-190295.45"
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire width 64 $0\data_r2__fast1$next[63:0]$12928
+ attribute \src "libresoc.v:189238.3-189239.45"
wire width 64 $0\data_r2__fast1[63:0]
- attribute \src "libresoc.v:190575.3-190596.6"
- wire $0\data_r2__fast1_ok$next[0:0]$13117
- attribute \src "libresoc.v:190296.3-190297.51"
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire $0\data_r2__fast1_ok$next[0:0]$12929
+ attribute \src "libresoc.v:189240.3-189241.51"
wire $0\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:190597.3-190618.6"
- wire $0\data_r3__xer_so$next[0:0]$13124
- attribute \src "libresoc.v:190290.3-190291.47"
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $0\data_r3__xer_so$next[0:0]$12936
+ attribute \src "libresoc.v:189234.3-189235.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:190597.3-190618.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$13125
- attribute \src "libresoc.v:190292.3-190293.53"
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$12937
+ attribute \src "libresoc.v:189236.3-189237.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:190619.3-190640.6"
- wire width 2 $0\data_r4__xer_ov$next[1:0]$13132
- attribute \src "libresoc.v:190286.3-190287.47"
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire width 2 $0\data_r4__xer_ov$next[1:0]$12944
+ attribute \src "libresoc.v:189230.3-189231.47"
wire width 2 $0\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:190619.3-190640.6"
- wire $0\data_r4__xer_ov_ok$next[0:0]$13133
- attribute \src "libresoc.v:190288.3-190289.53"
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire $0\data_r4__xer_ov_ok$next[0:0]$12945
+ attribute \src "libresoc.v:189232.3-189233.53"
wire $0\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:190641.3-190662.6"
- wire width 2 $0\data_r5__xer_ca$next[1:0]$13140
- attribute \src "libresoc.v:190282.3-190283.47"
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire width 2 $0\data_r5__xer_ca$next[1:0]$12952
+ attribute \src "libresoc.v:189226.3-189227.47"
wire width 2 $0\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:190641.3-190662.6"
- wire $0\data_r5__xer_ca_ok$next[0:0]$13141
- attribute \src "libresoc.v:190284.3-190285.53"
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire $0\data_r5__xer_ca_ok$next[0:0]$12953
+ attribute \src "libresoc.v:189228.3-189229.53"
wire $0\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:190741.3-190750.6"
+ attribute \src "libresoc.v:189685.3-189694.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:190751.3-190760.6"
+ attribute \src "libresoc.v:189695.3-189704.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:190761.3-190770.6"
+ attribute \src "libresoc.v:189705.3-189714.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:190771.3-190780.6"
+ attribute \src "libresoc.v:189715.3-189724.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:190781.3-190790.6"
+ attribute \src "libresoc.v:189725.3-189734.6"
wire width 2 $0\dest5_o[1:0]
- attribute \src "libresoc.v:190791.3-190800.6"
+ attribute \src "libresoc.v:189735.3-189744.6"
wire width 2 $0\dest6_o[1:0]
- attribute \src "libresoc.v:189589.7-189589.20"
+ attribute \src "libresoc.v:188533.7-188533.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190473.3-190481.6"
- wire $0\opc_l_r_opc$next[0:0]$13076
- attribute \src "libresoc.v:190322.3-190323.39"
+ attribute \src "libresoc.v:189417.3-189425.6"
+ wire $0\opc_l_r_opc$next[0:0]$12888
+ attribute \src "libresoc.v:189266.3-189267.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:190464.3-190472.6"
- wire $0\opc_l_s_opc$next[0:0]$13073
- attribute \src "libresoc.v:190324.3-190325.39"
+ attribute \src "libresoc.v:189408.3-189416.6"
+ wire $0\opc_l_s_opc$next[0:0]$12885
+ attribute \src "libresoc.v:189268.3-189269.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:190801.3-190809.6"
- wire width 6 $0\prev_wr_go$next[5:0]$13178
- attribute \src "libresoc.v:190334.3-190335.37"
+ attribute \src "libresoc.v:189745.3-189753.6"
+ wire width 6 $0\prev_wr_go$next[5:0]$12990
+ attribute \src "libresoc.v:189278.3-189279.37"
wire width 6 $0\prev_wr_go[5:0]
- attribute \src "libresoc.v:190418.3-190427.6"
+ attribute \src "libresoc.v:189362.3-189371.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:190509.3-190517.6"
- wire width 6 $0\req_l_r_req$next[5:0]$13088
- attribute \src "libresoc.v:190314.3-190315.39"
+ attribute \src "libresoc.v:189453.3-189461.6"
+ wire width 6 $0\req_l_r_req$next[5:0]$12900
+ attribute \src "libresoc.v:189258.3-189259.39"
wire width 6 $0\req_l_r_req[5:0]
- attribute \src "libresoc.v:190500.3-190508.6"
- wire width 6 $0\req_l_s_req$next[5:0]$13085
- attribute \src "libresoc.v:190316.3-190317.39"
+ attribute \src "libresoc.v:189444.3-189452.6"
+ wire width 6 $0\req_l_s_req$next[5:0]$12897
+ attribute \src "libresoc.v:189260.3-189261.39"
wire width 6 $0\req_l_s_req[5:0]
- attribute \src "libresoc.v:190437.3-190445.6"
- wire $0\rok_l_r_rdok$next[0:0]$13064
- attribute \src "libresoc.v:190330.3-190331.41"
+ attribute \src "libresoc.v:189381.3-189389.6"
+ wire $0\rok_l_r_rdok$next[0:0]$12876
+ attribute \src "libresoc.v:189274.3-189275.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:190428.3-190436.6"
- wire $0\rok_l_s_rdok$next[0:0]$13061
- attribute \src "libresoc.v:190332.3-190333.41"
+ attribute \src "libresoc.v:189372.3-189380.6"
+ wire $0\rok_l_s_rdok$next[0:0]$12873
+ attribute \src "libresoc.v:189276.3-189277.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:190455.3-190463.6"
- wire $0\rst_l_r_rst$next[0:0]$13070
- attribute \src "libresoc.v:190326.3-190327.39"
+ attribute \src "libresoc.v:189399.3-189407.6"
+ wire $0\rst_l_r_rst$next[0:0]$12882
+ attribute \src "libresoc.v:189270.3-189271.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:190446.3-190454.6"
- wire $0\rst_l_s_rst$next[0:0]$13067
- attribute \src "libresoc.v:190328.3-190329.39"
+ attribute \src "libresoc.v:189390.3-189398.6"
+ wire $0\rst_l_s_rst$next[0:0]$12879
+ attribute \src "libresoc.v:189272.3-189273.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:190491.3-190499.6"
- wire width 6 $0\src_l_r_src$next[5:0]$13082
- attribute \src "libresoc.v:190318.3-190319.39"
+ attribute \src "libresoc.v:189435.3-189443.6"
+ wire width 6 $0\src_l_r_src$next[5:0]$12894
+ attribute \src "libresoc.v:189262.3-189263.39"
wire width 6 $0\src_l_r_src[5:0]
- attribute \src "libresoc.v:190482.3-190490.6"
- wire width 6 $0\src_l_s_src$next[5:0]$13079
- attribute \src "libresoc.v:190320.3-190321.39"
+ attribute \src "libresoc.v:189426.3-189434.6"
+ wire width 6 $0\src_l_s_src$next[5:0]$12891
+ attribute \src "libresoc.v:189264.3-189265.39"
wire width 6 $0\src_l_s_src[5:0]
- attribute \src "libresoc.v:190663.3-190672.6"
- wire width 64 $0\src_r0$next[63:0]$13148
- attribute \src "libresoc.v:190280.3-190281.29"
+ attribute \src "libresoc.v:189607.3-189616.6"
+ wire width 64 $0\src_r0$next[63:0]$12960
+ attribute \src "libresoc.v:189224.3-189225.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:190673.3-190682.6"
- wire width 64 $0\src_r1$next[63:0]$13151
- attribute \src "libresoc.v:190278.3-190279.29"
+ attribute \src "libresoc.v:189617.3-189626.6"
+ wire width 64 $0\src_r1$next[63:0]$12963
+ attribute \src "libresoc.v:189222.3-189223.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:190683.3-190692.6"
- wire width 64 $0\src_r2$next[63:0]$13154
- attribute \src "libresoc.v:190276.3-190277.29"
+ attribute \src "libresoc.v:189627.3-189636.6"
+ wire width 64 $0\src_r2$next[63:0]$12966
+ attribute \src "libresoc.v:189220.3-189221.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:190693.3-190702.6"
- wire $0\src_r3$next[0:0]$13157
- attribute \src "libresoc.v:190274.3-190275.29"
+ attribute \src "libresoc.v:189637.3-189646.6"
+ wire $0\src_r3$next[0:0]$12969
+ attribute \src "libresoc.v:189218.3-189219.29"
wire $0\src_r3[0:0]
- attribute \src "libresoc.v:190703.3-190712.6"
- wire width 2 $0\src_r4$next[1:0]$13160
- attribute \src "libresoc.v:190272.3-190273.29"
+ attribute \src "libresoc.v:189647.3-189656.6"
+ wire width 2 $0\src_r4$next[1:0]$12972
+ attribute \src "libresoc.v:189216.3-189217.29"
wire width 2 $0\src_r4[1:0]
- attribute \src "libresoc.v:190713.3-190722.6"
- wire width 2 $0\src_r5$next[1:0]$13163
- attribute \src "libresoc.v:190270.3-190271.29"
+ attribute \src "libresoc.v:189657.3-189666.6"
+ wire width 2 $0\src_r5$next[1:0]$12975
+ attribute \src "libresoc.v:189214.3-189215.29"
wire width 2 $0\src_r5[1:0]
- attribute \src "libresoc.v:189725.7-189725.24"
+ attribute \src "libresoc.v:188669.7-188669.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:189735.7-189735.26"
+ attribute \src "libresoc.v:188679.7-188679.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:190732.3-190740.6"
- wire $1\alu_l_r_alu$next[0:0]$13170
- attribute \src "libresoc.v:189743.7-189743.25"
+ attribute \src "libresoc.v:189676.3-189684.6"
+ wire $1\alu_l_r_alu$next[0:0]$12982
+ attribute \src "libresoc.v:188687.7-188687.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095
- attribute \src "libresoc.v:189788.14-189788.49"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907
+ attribute \src "libresoc.v:188732.14-188732.49"
wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13096
- attribute \src "libresoc.v:189792.14-189792.43"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12908
+ attribute \src "libresoc.v:188736.14-188736.43"
wire width 32 $1\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097
- attribute \src "libresoc.v:189871.13-189871.47"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909
+ attribute \src "libresoc.v:188815.13-188815.47"
wire width 7 $1\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:190518.3-190530.6"
- wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098
- attribute \src "libresoc.v:189875.7-189875.39"
+ attribute \src "libresoc.v:189462.3-189474.6"
+ wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910
+ attribute \src "libresoc.v:188819.7-188819.39"
wire $1\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:190723.3-190731.6"
- wire $1\alui_l_r_alui$next[0:0]$13167
- attribute \src "libresoc.v:189893.7-189893.27"
+ attribute \src "libresoc.v:189667.3-189675.6"
+ wire $1\alui_l_r_alui$next[0:0]$12979
+ attribute \src "libresoc.v:188837.7-188837.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:190531.3-190552.6"
- wire width 64 $1\data_r0__o$next[63:0]$13102
- attribute \src "libresoc.v:189925.14-189925.47"
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire width 64 $1\data_r0__o$next[63:0]$12914
+ attribute \src "libresoc.v:188869.14-188869.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:190531.3-190552.6"
- wire $1\data_r0__o_ok$next[0:0]$13103
- attribute \src "libresoc.v:189929.7-189929.27"
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire $1\data_r0__o_ok$next[0:0]$12915
+ attribute \src "libresoc.v:188873.7-188873.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:190553.3-190574.6"
- wire width 64 $1\data_r1__spr1$next[63:0]$13110
- attribute \src "libresoc.v:189933.14-189933.50"
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire width 64 $1\data_r1__spr1$next[63:0]$12922
+ attribute \src "libresoc.v:188877.14-188877.50"
wire width 64 $1\data_r1__spr1[63:0]
- attribute \src "libresoc.v:190553.3-190574.6"
- wire $1\data_r1__spr1_ok$next[0:0]$13111
- attribute \src "libresoc.v:189937.7-189937.30"
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire $1\data_r1__spr1_ok$next[0:0]$12923
+ attribute \src "libresoc.v:188881.7-188881.30"
wire $1\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:190575.3-190596.6"
- wire width 64 $1\data_r2__fast1$next[63:0]$13118
- attribute \src "libresoc.v:189941.14-189941.51"
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire width 64 $1\data_r2__fast1$next[63:0]$12930
+ attribute \src "libresoc.v:188885.14-188885.51"
wire width 64 $1\data_r2__fast1[63:0]
- attribute \src "libresoc.v:190575.3-190596.6"
- wire $1\data_r2__fast1_ok$next[0:0]$13119
- attribute \src "libresoc.v:189945.7-189945.31"
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire $1\data_r2__fast1_ok$next[0:0]$12931
+ attribute \src "libresoc.v:188889.7-188889.31"
wire $1\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:190597.3-190618.6"
- wire $1\data_r3__xer_so$next[0:0]$13126
- attribute \src "libresoc.v:189949.7-189949.29"
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $1\data_r3__xer_so$next[0:0]$12938
+ attribute \src "libresoc.v:188893.7-188893.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:190597.3-190618.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$13127
- attribute \src "libresoc.v:189953.7-189953.32"
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$12939
+ attribute \src "libresoc.v:188897.7-188897.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:190619.3-190640.6"
- wire width 2 $1\data_r4__xer_ov$next[1:0]$13134
- attribute \src "libresoc.v:189957.13-189957.35"
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire width 2 $1\data_r4__xer_ov$next[1:0]$12946
+ attribute \src "libresoc.v:188901.13-188901.35"
wire width 2 $1\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:190619.3-190640.6"
- wire $1\data_r4__xer_ov_ok$next[0:0]$13135
- attribute \src "libresoc.v:189961.7-189961.32"
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire $1\data_r4__xer_ov_ok$next[0:0]$12947
+ attribute \src "libresoc.v:188905.7-188905.32"
wire $1\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:190641.3-190662.6"
- wire width 2 $1\data_r5__xer_ca$next[1:0]$13142
- attribute \src "libresoc.v:189965.13-189965.35"
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire width 2 $1\data_r5__xer_ca$next[1:0]$12954
+ attribute \src "libresoc.v:188909.13-188909.35"
wire width 2 $1\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:190641.3-190662.6"
- wire $1\data_r5__xer_ca_ok$next[0:0]$13143
- attribute \src "libresoc.v:189969.7-189969.32"
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire $1\data_r5__xer_ca_ok$next[0:0]$12955
+ attribute \src "libresoc.v:188913.7-188913.32"
wire $1\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:190741.3-190750.6"
+ attribute \src "libresoc.v:189685.3-189694.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:190751.3-190760.6"
+ attribute \src "libresoc.v:189695.3-189704.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:190761.3-190770.6"
+ attribute \src "libresoc.v:189705.3-189714.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:190771.3-190780.6"
+ attribute \src "libresoc.v:189715.3-189724.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:190781.3-190790.6"
+ attribute \src "libresoc.v:189725.3-189734.6"
wire width 2 $1\dest5_o[1:0]
- attribute \src "libresoc.v:190791.3-190800.6"
+ attribute \src "libresoc.v:189735.3-189744.6"
wire width 2 $1\dest6_o[1:0]
- attribute \src "libresoc.v:190473.3-190481.6"
- wire $1\opc_l_r_opc$next[0:0]$13077
- attribute \src "libresoc.v:189997.7-189997.25"
+ attribute \src "libresoc.v:189417.3-189425.6"
+ wire $1\opc_l_r_opc$next[0:0]$12889
+ attribute \src "libresoc.v:188941.7-188941.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:190464.3-190472.6"
- wire $1\opc_l_s_opc$next[0:0]$13074
- attribute \src "libresoc.v:190001.7-190001.25"
+ attribute \src "libresoc.v:189408.3-189416.6"
+ wire $1\opc_l_s_opc$next[0:0]$12886
+ attribute \src "libresoc.v:188945.7-188945.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:190801.3-190809.6"
- wire width 6 $1\prev_wr_go$next[5:0]$13179
- attribute \src "libresoc.v:190103.13-190103.31"
+ attribute \src "libresoc.v:189745.3-189753.6"
+ wire width 6 $1\prev_wr_go$next[5:0]$12991
+ attribute \src "libresoc.v:189047.13-189047.31"
wire width 6 $1\prev_wr_go[5:0]
- attribute \src "libresoc.v:190418.3-190427.6"
+ attribute \src "libresoc.v:189362.3-189371.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:190509.3-190517.6"
- wire width 6 $1\req_l_r_req$next[5:0]$13089
- attribute \src "libresoc.v:190111.13-190111.32"
+ attribute \src "libresoc.v:189453.3-189461.6"
+ wire width 6 $1\req_l_r_req$next[5:0]$12901
+ attribute \src "libresoc.v:189055.13-189055.32"
wire width 6 $1\req_l_r_req[5:0]
- attribute \src "libresoc.v:190500.3-190508.6"
- wire width 6 $1\req_l_s_req$next[5:0]$13086
- attribute \src "libresoc.v:190115.13-190115.32"
+ attribute \src "libresoc.v:189444.3-189452.6"
+ wire width 6 $1\req_l_s_req$next[5:0]$12898
+ attribute \src "libresoc.v:189059.13-189059.32"
wire width 6 $1\req_l_s_req[5:0]
- attribute \src "libresoc.v:190437.3-190445.6"
- wire $1\rok_l_r_rdok$next[0:0]$13065
- attribute \src "libresoc.v:190127.7-190127.26"
+ attribute \src "libresoc.v:189381.3-189389.6"
+ wire $1\rok_l_r_rdok$next[0:0]$12877
+ attribute \src "libresoc.v:189071.7-189071.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:190428.3-190436.6"
- wire $1\rok_l_s_rdok$next[0:0]$13062
- attribute \src "libresoc.v:190131.7-190131.26"
+ attribute \src "libresoc.v:189372.3-189380.6"
+ wire $1\rok_l_s_rdok$next[0:0]$12874
+ attribute \src "libresoc.v:189075.7-189075.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:190455.3-190463.6"
- wire $1\rst_l_r_rst$next[0:0]$13071
- attribute \src "libresoc.v:190135.7-190135.25"
+ attribute \src "libresoc.v:189399.3-189407.6"
+ wire $1\rst_l_r_rst$next[0:0]$12883
+ attribute \src "libresoc.v:189079.7-189079.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:190446.3-190454.6"
- wire $1\rst_l_s_rst$next[0:0]$13068
- attribute \src "libresoc.v:190139.7-190139.25"
+ attribute \src "libresoc.v:189390.3-189398.6"
+ wire $1\rst_l_s_rst$next[0:0]$12880
+ attribute \src "libresoc.v:189083.7-189083.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:190491.3-190499.6"
- wire width 6 $1\src_l_r_src$next[5:0]$13083
- attribute \src "libresoc.v:190161.13-190161.32"
+ attribute \src "libresoc.v:189435.3-189443.6"
+ wire width 6 $1\src_l_r_src$next[5:0]$12895
+ attribute \src "libresoc.v:189105.13-189105.32"
wire width 6 $1\src_l_r_src[5:0]
- attribute \src "libresoc.v:190482.3-190490.6"
- wire width 6 $1\src_l_s_src$next[5:0]$13080
- attribute \src "libresoc.v:190165.13-190165.32"
+ attribute \src "libresoc.v:189426.3-189434.6"
+ wire width 6 $1\src_l_s_src$next[5:0]$12892
+ attribute \src "libresoc.v:189109.13-189109.32"
wire width 6 $1\src_l_s_src[5:0]
- attribute \src "libresoc.v:190663.3-190672.6"
- wire width 64 $1\src_r0$next[63:0]$13149
- attribute \src "libresoc.v:190169.14-190169.43"
+ attribute \src "libresoc.v:189607.3-189616.6"
+ wire width 64 $1\src_r0$next[63:0]$12961
+ attribute \src "libresoc.v:189113.14-189113.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:190673.3-190682.6"
- wire width 64 $1\src_r1$next[63:0]$13152
- attribute \src "libresoc.v:190173.14-190173.43"
+ attribute \src "libresoc.v:189617.3-189626.6"
+ wire width 64 $1\src_r1$next[63:0]$12964
+ attribute \src "libresoc.v:189117.14-189117.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:190683.3-190692.6"
- wire width 64 $1\src_r2$next[63:0]$13155
- attribute \src "libresoc.v:190177.14-190177.43"
+ attribute \src "libresoc.v:189627.3-189636.6"
+ wire width 64 $1\src_r2$next[63:0]$12967
+ attribute \src "libresoc.v:189121.14-189121.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:190693.3-190702.6"
- wire $1\src_r3$next[0:0]$13158
- attribute \src "libresoc.v:190181.7-190181.20"
+ attribute \src "libresoc.v:189637.3-189646.6"
+ wire $1\src_r3$next[0:0]$12970
+ attribute \src "libresoc.v:189125.7-189125.20"
wire $1\src_r3[0:0]
- attribute \src "libresoc.v:190703.3-190712.6"
- wire width 2 $1\src_r4$next[1:0]$13161
- attribute \src "libresoc.v:190185.13-190185.26"
+ attribute \src "libresoc.v:189647.3-189656.6"
+ wire width 2 $1\src_r4$next[1:0]$12973
+ attribute \src "libresoc.v:189129.13-189129.26"
wire width 2 $1\src_r4[1:0]
- attribute \src "libresoc.v:190713.3-190722.6"
- wire width 2 $1\src_r5$next[1:0]$13164
- attribute \src "libresoc.v:190189.13-190189.26"
+ attribute \src "libresoc.v:189657.3-189666.6"
+ wire width 2 $1\src_r5$next[1:0]$12976
+ attribute \src "libresoc.v:189133.13-189133.26"
wire width 2 $1\src_r5[1:0]
- attribute \src "libresoc.v:190531.3-190552.6"
- wire width 64 $2\data_r0__o$next[63:0]$13104
- attribute \src "libresoc.v:190531.3-190552.6"
- wire $2\data_r0__o_ok$next[0:0]$13105
- attribute \src "libresoc.v:190553.3-190574.6"
- wire width 64 $2\data_r1__spr1$next[63:0]$13112
- attribute \src "libresoc.v:190553.3-190574.6"
- wire $2\data_r1__spr1_ok$next[0:0]$13113
- attribute \src "libresoc.v:190575.3-190596.6"
- wire width 64 $2\data_r2__fast1$next[63:0]$13120
- attribute \src "libresoc.v:190575.3-190596.6"
- wire $2\data_r2__fast1_ok$next[0:0]$13121
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- wire $2\data_r3__xer_so$next[0:0]$13128
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- wire $2\data_r3__xer_so_ok$next[0:0]$13129
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- wire width 2 $2\data_r4__xer_ov$next[1:0]$13136
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- wire $2\data_r4__xer_ov_ok$next[0:0]$13137
- attribute \src "libresoc.v:190641.3-190662.6"
- wire width 2 $2\data_r5__xer_ca$next[1:0]$13144
- attribute \src "libresoc.v:190641.3-190662.6"
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- wire $3\data_r0__o_ok$next[0:0]$13106
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- wire $3\data_r1__spr1_ok$next[0:0]$13114
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- wire $3\data_r3__xer_so_ok$next[0:0]$13130
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- wire width 6 $and$libresoc.v:190205$12961_Y
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- wire $and$libresoc.v:190207$12963_Y
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- wire $and$libresoc.v:190208$12964_Y
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- wire $and$libresoc.v:190209$12965_Y
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- wire width 6 $and$libresoc.v:190214$12970_Y
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- wire $and$libresoc.v:190215$12971_Y
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- wire $and$libresoc.v:190219$12975_Y
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- wire $and$libresoc.v:190220$12976_Y
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- wire $and$libresoc.v:190232$12988_Y
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- wire width 6 $and$libresoc.v:190238$12994_Y
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- wire $and$libresoc.v:190240$12996_Y
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- wire $and$libresoc.v:190242$12998_Y
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- wire $and$libresoc.v:190249$13005_Y
- attribute \src "libresoc.v:190250.17-190250.123"
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- wire $and$libresoc.v:190253$13009_Y
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- wire $and$libresoc.v:190254$13010_Y
- attribute \src "libresoc.v:190255.18-190255.120"
- wire $and$libresoc.v:190255$13011_Y
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- wire $and$libresoc.v:190257$13013_Y
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- wire $and$libresoc.v:190258$13014_Y
- attribute \src "libresoc.v:190265.18-190265.134"
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- wire $eq$libresoc.v:190239$12995_Y
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- wire $eq$libresoc.v:190241$12997_Y
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- wire width 6 $not$libresoc.v:190204$12960_Y
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- wire width 6 $not$libresoc.v:190228$12984_Y
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- wire $not$libresoc.v:190231$12987_Y
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- wire $not$libresoc.v:190236$12992_Y
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- wire width 6 $or$libresoc.v:190211$12967_Y
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- attribute \src "libresoc.v:190245.18-190245.122"
- wire $or$libresoc.v:190245$13001_Y
- attribute \src "libresoc.v:190246.18-190246.124"
- wire $or$libresoc.v:190246$13002_Y
- attribute \src "libresoc.v:190247.18-190247.194"
- wire width 6 $or$libresoc.v:190247$13003_Y
- attribute \src "libresoc.v:190248.18-190248.194"
- wire width 6 $or$libresoc.v:190248$13004_Y
- attribute \src "libresoc.v:190252.18-190252.120"
- wire width 6 $or$libresoc.v:190252$13008_Y
- attribute \src "libresoc.v:190217.17-190217.105"
- wire $reduce_and$libresoc.v:190217$12973_Y
- attribute \src "libresoc.v:190230.18-190230.106"
- wire $reduce_or$libresoc.v:190230$12986_Y
- attribute \src "libresoc.v:190233.18-190233.113"
- wire $reduce_or$libresoc.v:190233$12989_Y
- attribute \src "libresoc.v:190234.18-190234.112"
- wire $reduce_or$libresoc.v:190234$12990_Y
- attribute \src "libresoc.v:190259.18-190259.118"
- wire width 64 $ternary$libresoc.v:190259$13015_Y
- attribute \src "libresoc.v:190260.18-190260.118"
- wire width 64 $ternary$libresoc.v:190260$13016_Y
- attribute \src "libresoc.v:190261.18-190261.118"
- wire width 64 $ternary$libresoc.v:190261$13017_Y
- attribute \src "libresoc.v:190262.18-190262.118"
- wire $ternary$libresoc.v:190262$13018_Y
- attribute \src "libresoc.v:190263.18-190263.118"
- wire width 2 $ternary$libresoc.v:190263$13019_Y
- attribute \src "libresoc.v:190264.18-190264.118"
- wire width 2 $ternary$libresoc.v:190264$13020_Y
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire width 64 $2\data_r0__o$next[63:0]$12916
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire $2\data_r0__o_ok$next[0:0]$12917
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire width 64 $2\data_r1__spr1$next[63:0]$12924
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire $2\data_r1__spr1_ok$next[0:0]$12925
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire width 64 $2\data_r2__fast1$next[63:0]$12932
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire $2\data_r2__fast1_ok$next[0:0]$12933
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $2\data_r3__xer_so$next[0:0]$12940
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$12941
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire width 2 $2\data_r4__xer_ov$next[1:0]$12948
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire $2\data_r4__xer_ov_ok$next[0:0]$12949
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire width 2 $2\data_r5__xer_ca$next[1:0]$12956
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire $2\data_r5__xer_ca_ok$next[0:0]$12957
+ attribute \src "libresoc.v:189475.3-189496.6"
+ wire $3\data_r0__o_ok$next[0:0]$12918
+ attribute \src "libresoc.v:189497.3-189518.6"
+ wire $3\data_r1__spr1_ok$next[0:0]$12926
+ attribute \src "libresoc.v:189519.3-189540.6"
+ wire $3\data_r2__fast1_ok$next[0:0]$12934
+ attribute \src "libresoc.v:189541.3-189562.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$12942
+ attribute \src "libresoc.v:189563.3-189584.6"
+ wire $3\data_r4__xer_ov_ok$next[0:0]$12950
+ attribute \src "libresoc.v:189585.3-189606.6"
+ wire $3\data_r5__xer_ca_ok$next[0:0]$12958
+ attribute \src "libresoc.v:189145.19-189145.133"
+ wire $and$libresoc.v:189145$12769_Y
+ attribute \src "libresoc.v:189146.19-189146.183"
+ wire width 6 $and$libresoc.v:189146$12770_Y
+ attribute \src "libresoc.v:189147.19-189147.115"
+ wire width 6 $and$libresoc.v:189147$12771_Y
+ attribute \src "libresoc.v:189149.19-189149.115"
+ wire width 6 $and$libresoc.v:189149$12773_Y
+ attribute \src "libresoc.v:189150.19-189150.125"
+ wire $and$libresoc.v:189150$12774_Y
+ attribute \src "libresoc.v:189151.19-189151.125"
+ wire $and$libresoc.v:189151$12775_Y
+ attribute \src "libresoc.v:189152.19-189152.125"
+ wire $and$libresoc.v:189152$12776_Y
+ attribute \src "libresoc.v:189153.19-189153.125"
+ wire $and$libresoc.v:189153$12777_Y
+ attribute \src "libresoc.v:189154.19-189154.125"
+ wire $and$libresoc.v:189154$12778_Y
+ attribute \src "libresoc.v:189156.19-189156.125"
+ wire $and$libresoc.v:189156$12780_Y
+ attribute \src "libresoc.v:189157.19-189157.165"
+ wire width 6 $and$libresoc.v:189157$12781_Y
+ attribute \src "libresoc.v:189158.19-189158.121"
+ wire width 6 $and$libresoc.v:189158$12782_Y
+ attribute \src "libresoc.v:189159.19-189159.127"
+ wire $and$libresoc.v:189159$12783_Y
+ attribute \src "libresoc.v:189160.19-189160.127"
+ wire $and$libresoc.v:189160$12784_Y
+ attribute \src "libresoc.v:189162.19-189162.127"
+ wire $and$libresoc.v:189162$12786_Y
+ attribute \src "libresoc.v:189163.19-189163.127"
+ wire $and$libresoc.v:189163$12787_Y
+ attribute \src "libresoc.v:189164.19-189164.127"
+ wire $and$libresoc.v:189164$12788_Y
+ attribute \src "libresoc.v:189165.19-189165.127"
+ wire $and$libresoc.v:189165$12789_Y
+ attribute \src "libresoc.v:189166.18-189166.110"
+ wire $and$libresoc.v:189166$12790_Y
+ attribute \src "libresoc.v:189168.18-189168.98"
+ wire $and$libresoc.v:189168$12792_Y
+ attribute \src "libresoc.v:189170.18-189170.100"
+ wire $and$libresoc.v:189170$12794_Y
+ attribute \src "libresoc.v:189171.18-189171.182"
+ wire width 6 $and$libresoc.v:189171$12795_Y
+ attribute \src "libresoc.v:189173.18-189173.119"
+ wire width 6 $and$libresoc.v:189173$12797_Y
+ attribute \src "libresoc.v:189176.18-189176.116"
+ wire $and$libresoc.v:189176$12800_Y
+ attribute \src "libresoc.v:189181.18-189181.113"
+ wire $and$libresoc.v:189181$12805_Y
+ attribute \src "libresoc.v:189182.18-189182.125"
+ wire width 6 $and$libresoc.v:189182$12806_Y
+ attribute \src "libresoc.v:189184.18-189184.112"
+ wire $and$libresoc.v:189184$12808_Y
+ attribute \src "libresoc.v:189186.18-189186.126"
+ wire $and$libresoc.v:189186$12810_Y
+ attribute \src "libresoc.v:189187.18-189187.126"
+ wire $and$libresoc.v:189187$12811_Y
+ attribute \src "libresoc.v:189188.18-189188.117"
+ wire $and$libresoc.v:189188$12812_Y
+ attribute \src "libresoc.v:189193.18-189193.130"
+ wire $and$libresoc.v:189193$12817_Y
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+ wire $and$libresoc.v:189194$12818_Y
+ attribute \src "libresoc.v:189195.18-189195.124"
+ wire width 6 $and$libresoc.v:189195$12819_Y
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+ wire $and$libresoc.v:189197$12821_Y
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+ wire $and$libresoc.v:189198$12822_Y
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+ wire $and$libresoc.v:189199$12823_Y
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+ wire $and$libresoc.v:189200$12824_Y
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+ wire $and$libresoc.v:189201$12825_Y
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+ wire $and$libresoc.v:189202$12826_Y
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+ wire $and$libresoc.v:189209$12833_Y
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+ wire $eq$libresoc.v:189183$12807_Y
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+ wire $eq$libresoc.v:189185$12809_Y
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+ wire width 6 $not$libresoc.v:189148$12772_Y
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+ wire $not$libresoc.v:189167$12791_Y
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+ wire $not$libresoc.v:189169$12793_Y
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+ wire $not$libresoc.v:189175$12799_Y
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+ wire $not$libresoc.v:189180$12804_Y
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+ wire width 6 $or$libresoc.v:189192$12816_Y
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+ wire width 6 $or$libresoc.v:189196$12820_Y
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+ wire $reduce_and$libresoc.v:189161$12785_Y
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+ wire $reduce_or$libresoc.v:189174$12798_Y
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+ wire $reduce_or$libresoc.v:189177$12801_Y
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+ wire $reduce_or$libresoc.v:189178$12802_Y
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+ wire width 64 $ternary$libresoc.v:189203$12827_Y
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+ wire width 64 $ternary$libresoc.v:189204$12828_Y
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+ wire width 64 $ternary$libresoc.v:189205$12829_Y
+ attribute \src "libresoc.v:189206.18-189206.118"
+ wire $ternary$libresoc.v:189206$12830_Y
+ attribute \src "libresoc.v:189207.18-189207.118"
+ wire width 2 $ternary$libresoc.v:189207$12831_Y
+ attribute \src "libresoc.v:189208.18-189208.118"
+ wire width 2 $ternary$libresoc.v:189208$12832_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
wire \$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 7 \cu_busy_o
wire width 2 output 22 \dest6_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 27 \fast1_ok
- attribute \src "libresoc.v:189589.7-189589.15"
+ attribute \src "libresoc.v:188533.7-188533.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 17 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 25 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:190201$12957
+ cell $and $and$libresoc.v:189145$12769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:190201$12957_Y
+ connect \Y $and$libresoc.v:189145$12769_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:190202$12958
+ cell $and $and$libresoc.v:189146$12770
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:190202$12958_Y
+ connect \Y $and$libresoc.v:189146$12770_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:190203$12959
+ cell $and $and$libresoc.v:189147$12771
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$102
connect \B 6'111111
- connect \Y $and$libresoc.v:190203$12959_Y
+ connect \Y $and$libresoc.v:189147$12771_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:190205$12961
+ cell $and $and$libresoc.v:189149$12773
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$104
connect \B \$106
- connect \Y $and$libresoc.v:190205$12961_Y
+ connect \Y $and$libresoc.v:189149$12773_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190206$12962
+ cell $and $and$libresoc.v:189150$12774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190206$12962_Y
+ connect \Y $and$libresoc.v:189150$12774_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190207$12963
+ cell $and $and$libresoc.v:189151$12775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190207$12963_Y
+ connect \Y $and$libresoc.v:189151$12775_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190208$12964
+ cell $and $and$libresoc.v:189152$12776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190208$12964_Y
+ connect \Y $and$libresoc.v:189152$12776_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190209$12965
+ cell $and $and$libresoc.v:189153$12777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190209$12965_Y
+ connect \Y $and$libresoc.v:189153$12777_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190210$12966
+ cell $and $and$libresoc.v:189154$12778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190210$12966_Y
+ connect \Y $and$libresoc.v:189154$12778_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:190212$12968
+ cell $and $and$libresoc.v:189156$12780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:190212$12968_Y
+ connect \Y $and$libresoc.v:189156$12780_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:190213$12969
+ cell $and $and$libresoc.v:189157$12781
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B { \$110 \$112 \$114 \$116 \$118 \$120 }
- connect \Y $and$libresoc.v:190213$12969_Y
+ connect \Y $and$libresoc.v:189157$12781_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:190214$12970
+ cell $and $and$libresoc.v:189158$12782
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$122
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:190214$12970_Y
+ connect \Y $and$libresoc.v:189158$12782_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190215$12971
+ cell $and $and$libresoc.v:189159$12783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190215$12971_Y
+ connect \Y $and$libresoc.v:189159$12783_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190216$12972
+ cell $and $and$libresoc.v:189160$12784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190216$12972_Y
+ connect \Y $and$libresoc.v:189160$12784_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190218$12974
+ cell $and $and$libresoc.v:189162$12786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190218$12974_Y
+ connect \Y $and$libresoc.v:189162$12786_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190219$12975
+ cell $and $and$libresoc.v:189163$12787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190219$12975_Y
+ connect \Y $and$libresoc.v:189163$12787_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190220$12976
+ cell $and $and$libresoc.v:189164$12788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190220$12976_Y
+ connect \Y $and$libresoc.v:189164$12788_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:190221$12977
+ cell $and $and$libresoc.v:189165$12789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [5]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190221$12977_Y
+ connect \Y $and$libresoc.v:189165$12789_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:190222$12978
+ cell $and $and$libresoc.v:189166$12790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$6
connect \B \$8
- connect \Y $and$libresoc.v:190222$12978_Y
+ connect \Y $and$libresoc.v:189166$12790_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:190224$12980
+ cell $and $and$libresoc.v:189168$12792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$16
- connect \Y $and$libresoc.v:190224$12980_Y
+ connect \Y $and$libresoc.v:189168$12792_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:190226$12982
+ cell $and $and$libresoc.v:189170$12794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$20
- connect \Y $and$libresoc.v:190226$12982_Y
+ connect \Y $and$libresoc.v:189170$12794_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:190227$12983
+ cell $and $and$libresoc.v:189171$12795
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:190227$12983_Y
+ connect \Y $and$libresoc.v:189171$12795_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:190229$12985
+ cell $and $and$libresoc.v:189173$12797
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__rel_o
connect \B \$28
- connect \Y $and$libresoc.v:190229$12985_Y
+ connect \Y $and$libresoc.v:189173$12797_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:190232$12988
+ cell $and $and$libresoc.v:189176$12800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$26
- connect \Y $and$libresoc.v:190232$12988_Y
+ connect \Y $and$libresoc.v:189176$12800_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:190237$12993
+ cell $and $and$libresoc.v:189181$12805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$42
- connect \Y $and$libresoc.v:190237$12993_Y
+ connect \Y $and$libresoc.v:189181$12805_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:190238$12994
+ cell $and $and$libresoc.v:189182$12806
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:190238$12994_Y
+ connect \Y $and$libresoc.v:189182$12806_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:190240$12996
+ cell $and $and$libresoc.v:189184$12808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$48
- connect \Y $and$libresoc.v:190240$12996_Y
+ connect \Y $and$libresoc.v:189184$12808_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:190242$12998
+ cell $and $and$libresoc.v:189186$12810
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \alu_spr0_n_ready_i
- connect \Y $and$libresoc.v:190242$12998_Y
+ connect \Y $and$libresoc.v:189186$12810_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:190243$12999
+ cell $and $and$libresoc.v:189187$12811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$54
connect \B \alu_spr0_n_valid_o
- connect \Y $and$libresoc.v:190243$12999_Y
+ connect \Y $and$libresoc.v:189187$12811_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:190244$13000
+ cell $and $and$libresoc.v:189188$12812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$56
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190244$13000_Y
+ connect \Y $and$libresoc.v:189188$12812_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:190249$13005
+ cell $and $and$libresoc.v:189193$12817
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190249$13005_Y
+ connect \Y $and$libresoc.v:189193$12817_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:190250$13006
+ cell $and $and$libresoc.v:189194$12818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:190250$13006_Y
+ connect \Y $and$libresoc.v:189194$12818_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:190251$13007
+ cell $and $and$libresoc.v:189195$12819
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:190251$13007_Y
+ connect \Y $and$libresoc.v:189195$12819_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190253$13009
+ cell $and $and$libresoc.v:189197$12821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190253$13009_Y
+ connect \Y $and$libresoc.v:189197$12821_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190254$13010
+ cell $and $and$libresoc.v:189198$12822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190254$13010_Y
+ connect \Y $and$libresoc.v:189198$12822_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190255$13011
+ cell $and $and$libresoc.v:189199$12823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190255$13011_Y
+ connect \Y $and$libresoc.v:189199$12823_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190256$13012
+ cell $and $and$libresoc.v:189200$12824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190256$13012_Y
+ connect \Y $and$libresoc.v:189200$12824_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190257$13013
+ cell $and $and$libresoc.v:189201$12825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190257$13013_Y
+ connect \Y $and$libresoc.v:189201$12825_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:190258$13014
+ cell $and $and$libresoc.v:189202$12826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ca_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:190258$13014_Y
+ connect \Y $and$libresoc.v:189202$12826_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:190265$13021
+ cell $and $and$libresoc.v:189209$12833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:190265$13021_Y
+ connect \Y $and$libresoc.v:189209$12833_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:190239$12995
+ cell $eq $eq$libresoc.v:189183$12807
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$46
connect \B 1'0
- connect \Y $eq$libresoc.v:190239$12995_Y
+ connect \Y $eq$libresoc.v:189183$12807_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:190241$12997
+ cell $eq $eq$libresoc.v:189185$12809
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:190241$12997_Y
+ connect \Y $eq$libresoc.v:189185$12809_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:190200$12956
+ cell $not $not$libresoc.v:189144$12768
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:190200$12956_Y
+ connect \Y $not$libresoc.v:189144$12768_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:190204$12960
+ cell $not $not$libresoc.v:189148$12772
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:190204$12960_Y
+ connect \Y $not$libresoc.v:189148$12772_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:190223$12979
+ cell $not $not$libresoc.v:189167$12791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:190223$12979_Y
+ connect \Y $not$libresoc.v:189167$12791_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:190225$12981
+ cell $not $not$libresoc.v:189169$12793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:190225$12981_Y
+ connect \Y $not$libresoc.v:189169$12793_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:190228$12984
+ cell $not $not$libresoc.v:189172$12796
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:190228$12984_Y
+ connect \Y $not$libresoc.v:189172$12796_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:190231$12987
+ cell $not $not$libresoc.v:189175$12799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $not$libresoc.v:190231$12987_Y
+ connect \Y $not$libresoc.v:189175$12799_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:190236$12992
+ cell $not $not$libresoc.v:189180$12804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_ready_i
- connect \Y $not$libresoc.v:190236$12992_Y
+ connect \Y $not$libresoc.v:189180$12804_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:190211$12967
+ cell $or $or$libresoc.v:189155$12779
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:190211$12967_Y
+ connect \Y $or$libresoc.v:189155$12779_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:190235$12991
+ cell $or $or$libresoc.v:189179$12803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \$38
- connect \Y $or$libresoc.v:190235$12991_Y
+ connect \Y $or$libresoc.v:189179$12803_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:190245$13001
+ cell $or $or$libresoc.v:189189$12813
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:190245$13001_Y
+ connect \Y $or$libresoc.v:189189$12813_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:190246$13002
+ cell $or $or$libresoc.v:189190$12814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:190246$13002_Y
+ connect \Y $or$libresoc.v:189190$12814_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:190247$13003
+ cell $or $or$libresoc.v:189191$12815
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:190247$13003_Y
+ connect \Y $or$libresoc.v:189191$12815_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:190248$13004
+ cell $or $or$libresoc.v:189192$12816
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:190248$13004_Y
+ connect \Y $or$libresoc.v:189192$12816_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:190252$13008
+ cell $or $or$libresoc.v:189196$12820
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:190252$13008_Y
+ connect \Y $or$libresoc.v:189196$12820_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:190217$12973
+ cell $reduce_and $reduce_and$libresoc.v:189161$12785
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$11
- connect \Y $reduce_and$libresoc.v:190217$12973_Y
+ connect \Y $reduce_and$libresoc.v:189161$12785_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:190230$12986
+ cell $reduce_or $reduce_or$libresoc.v:189174$12798
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$30
- connect \Y $reduce_or$libresoc.v:190230$12986_Y
+ connect \Y $reduce_or$libresoc.v:189174$12798_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:190233$12989
+ cell $reduce_or $reduce_or$libresoc.v:189177$12801
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:190233$12989_Y
+ connect \Y $reduce_or$libresoc.v:189177$12801_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:190234$12990
+ cell $reduce_or $reduce_or$libresoc.v:189178$12802
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:190234$12990_Y
+ connect \Y $reduce_or$libresoc.v:189178$12802_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190259$13015
+ cell $mux $ternary$libresoc.v:189203$12827
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:190259$13015_Y
+ connect \Y $ternary$libresoc.v:189203$12827_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190260$13016
+ cell $mux $ternary$libresoc.v:189204$12828
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:190260$13016_Y
+ connect \Y $ternary$libresoc.v:189204$12828_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190261$13017
+ cell $mux $ternary$libresoc.v:189205$12829
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:190261$13017_Y
+ connect \Y $ternary$libresoc.v:189205$12829_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190262$13018
+ cell $mux $ternary$libresoc.v:189206$12830
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:190262$13018_Y
+ connect \Y $ternary$libresoc.v:189206$12830_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190263$13019
+ cell $mux $ternary$libresoc.v:189207$12831
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:190263$13019_Y
+ connect \Y $ternary$libresoc.v:189207$12831_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:190264$13020
+ cell $mux $ternary$libresoc.v:189208$12832
parameter \WIDTH 2
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $ternary$libresoc.v:190264$13020_Y
+ connect \Y $ternary$libresoc.v:189208$12832_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190340.14-190346.4"
+ attribute \src "libresoc.v:189284.14-189290.4"
cell \alu_l$73 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190347.12-190376.4"
+ attribute \src "libresoc.v:189291.12-189320.4"
cell \alu_spr0 \alu_spr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190377.15-190383.4"
+ attribute \src "libresoc.v:189321.15-189327.4"
cell \alui_l$72 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190384.14-190390.4"
+ attribute \src "libresoc.v:189328.14-189334.4"
cell \opc_l$68 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190391.14-190397.4"
+ attribute \src "libresoc.v:189335.14-189341.4"
cell \req_l$69 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190398.14-190404.4"
+ attribute \src "libresoc.v:189342.14-189348.4"
cell \rok_l$71 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190405.14-190410.4"
+ attribute \src "libresoc.v:189349.14-189354.4"
cell \rst_l$70 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:190411.14-190417.4"
+ attribute \src "libresoc.v:189355.14-189361.4"
cell \src_l$67 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:189589.7-189589.20"
- process $proc$libresoc.v:189589$13180
+ attribute \src "libresoc.v:188533.7-188533.20"
+ process $proc$libresoc.v:188533$12992
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:189725.7-189725.24"
- process $proc$libresoc.v:189725$13181
+ attribute \src "libresoc.v:188669.7-188669.24"
+ process $proc$libresoc.v:188669$12993
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:189735.7-189735.26"
- process $proc$libresoc.v:189735$13182
+ attribute \src "libresoc.v:188679.7-188679.26"
+ process $proc$libresoc.v:188679$12994
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:189743.7-189743.25"
- process $proc$libresoc.v:189743$13183
+ attribute \src "libresoc.v:188687.7-188687.25"
+ process $proc$libresoc.v:188687$12995
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:189788.14-189788.49"
- process $proc$libresoc.v:189788$13184
+ attribute \src "libresoc.v:188732.14-188732.49"
+ process $proc$libresoc.v:188732$12996
assign { } { }
assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:189792.14-189792.43"
- process $proc$libresoc.v:189792$13185
+ attribute \src "libresoc.v:188736.14-188736.43"
+ process $proc$libresoc.v:188736$12997
assign { } { }
assign $1\alu_spr0_spr_op__insn[31:0] 0
sync always
sync init
update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:189871.13-189871.47"
- process $proc$libresoc.v:189871$13186
+ attribute \src "libresoc.v:188815.13-188815.47"
+ process $proc$libresoc.v:188815$12998
assign { } { }
assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:189875.7-189875.39"
- process $proc$libresoc.v:189875$13187
+ attribute \src "libresoc.v:188819.7-188819.39"
+ process $proc$libresoc.v:188819$12999
assign { } { }
assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:189893.7-189893.27"
- process $proc$libresoc.v:189893$13188
+ attribute \src "libresoc.v:188837.7-188837.27"
+ process $proc$libresoc.v:188837$13000
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:189925.14-189925.47"
- process $proc$libresoc.v:189925$13189
+ attribute \src "libresoc.v:188869.14-188869.47"
+ process $proc$libresoc.v:188869$13001
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:189929.7-189929.27"
- process $proc$libresoc.v:189929$13190
+ attribute \src "libresoc.v:188873.7-188873.27"
+ process $proc$libresoc.v:188873$13002
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:189933.14-189933.50"
- process $proc$libresoc.v:189933$13191
+ attribute \src "libresoc.v:188877.14-188877.50"
+ process $proc$libresoc.v:188877$13003
assign { } { }
assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__spr1 $1\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:189937.7-189937.30"
- process $proc$libresoc.v:189937$13192
+ attribute \src "libresoc.v:188881.7-188881.30"
+ process $proc$libresoc.v:188881$13004
assign { } { }
assign $1\data_r1__spr1_ok[0:0] 1'0
sync always
sync init
update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:189941.14-189941.51"
- process $proc$libresoc.v:189941$13193
+ attribute \src "libresoc.v:188885.14-188885.51"
+ process $proc$libresoc.v:188885$13005
assign { } { }
assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast1 $1\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:189945.7-189945.31"
- process $proc$libresoc.v:189945$13194
+ attribute \src "libresoc.v:188889.7-188889.31"
+ process $proc$libresoc.v:188889$13006
assign { } { }
assign $1\data_r2__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:189949.7-189949.29"
- process $proc$libresoc.v:189949$13195
+ attribute \src "libresoc.v:188893.7-188893.29"
+ process $proc$libresoc.v:188893$13007
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:189953.7-189953.32"
- process $proc$libresoc.v:189953$13196
+ attribute \src "libresoc.v:188897.7-188897.32"
+ process $proc$libresoc.v:188897$13008
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:189957.13-189957.35"
- process $proc$libresoc.v:189957$13197
+ attribute \src "libresoc.v:188901.13-188901.35"
+ process $proc$libresoc.v:188901$13009
assign { } { }
assign $1\data_r4__xer_ov[1:0] 2'00
sync always
sync init
update \data_r4__xer_ov $1\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:189961.7-189961.32"
- process $proc$libresoc.v:189961$13198
+ attribute \src "libresoc.v:188905.7-188905.32"
+ process $proc$libresoc.v:188905$13010
assign { } { }
assign $1\data_r4__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:189965.13-189965.35"
- process $proc$libresoc.v:189965$13199
+ attribute \src "libresoc.v:188909.13-188909.35"
+ process $proc$libresoc.v:188909$13011
assign { } { }
assign $1\data_r5__xer_ca[1:0] 2'00
sync always
sync init
update \data_r5__xer_ca $1\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:189969.7-189969.32"
- process $proc$libresoc.v:189969$13200
+ attribute \src "libresoc.v:188913.7-188913.32"
+ process $proc$libresoc.v:188913$13012
assign { } { }
assign $1\data_r5__xer_ca_ok[0:0] 1'0
sync always
sync init
update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:189997.7-189997.25"
- process $proc$libresoc.v:189997$13201
+ attribute \src "libresoc.v:188941.7-188941.25"
+ process $proc$libresoc.v:188941$13013
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:190001.7-190001.25"
- process $proc$libresoc.v:190001$13202
+ attribute \src "libresoc.v:188945.7-188945.25"
+ process $proc$libresoc.v:188945$13014
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:190103.13-190103.31"
- process $proc$libresoc.v:190103$13203
+ attribute \src "libresoc.v:189047.13-189047.31"
+ process $proc$libresoc.v:189047$13015
assign { } { }
assign $1\prev_wr_go[5:0] 6'000000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:190111.13-190111.32"
- process $proc$libresoc.v:190111$13204
+ attribute \src "libresoc.v:189055.13-189055.32"
+ process $proc$libresoc.v:189055$13016
assign { } { }
assign $1\req_l_r_req[5:0] 6'111111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:190115.13-190115.32"
- process $proc$libresoc.v:190115$13205
+ attribute \src "libresoc.v:189059.13-189059.32"
+ process $proc$libresoc.v:189059$13017
assign { } { }
assign $1\req_l_s_req[5:0] 6'000000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:190127.7-190127.26"
- process $proc$libresoc.v:190127$13206
+ attribute \src "libresoc.v:189071.7-189071.26"
+ process $proc$libresoc.v:189071$13018
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:190131.7-190131.26"
- process $proc$libresoc.v:190131$13207
+ attribute \src "libresoc.v:189075.7-189075.26"
+ process $proc$libresoc.v:189075$13019
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:190135.7-190135.25"
- process $proc$libresoc.v:190135$13208
+ attribute \src "libresoc.v:189079.7-189079.25"
+ process $proc$libresoc.v:189079$13020
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:190139.7-190139.25"
- process $proc$libresoc.v:190139$13209
+ attribute \src "libresoc.v:189083.7-189083.25"
+ process $proc$libresoc.v:189083$13021
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:190161.13-190161.32"
- process $proc$libresoc.v:190161$13210
+ attribute \src "libresoc.v:189105.13-189105.32"
+ process $proc$libresoc.v:189105$13022
assign { } { }
assign $1\src_l_r_src[5:0] 6'111111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:190165.13-190165.32"
- process $proc$libresoc.v:190165$13211
+ attribute \src "libresoc.v:189109.13-189109.32"
+ process $proc$libresoc.v:189109$13023
assign { } { }
assign $1\src_l_s_src[5:0] 6'000000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:190169.14-190169.43"
- process $proc$libresoc.v:190169$13212
+ attribute \src "libresoc.v:189113.14-189113.43"
+ process $proc$libresoc.v:189113$13024
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:190173.14-190173.43"
- process $proc$libresoc.v:190173$13213
+ attribute \src "libresoc.v:189117.14-189117.43"
+ process $proc$libresoc.v:189117$13025
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:190177.14-190177.43"
- process $proc$libresoc.v:190177$13214
+ attribute \src "libresoc.v:189121.14-189121.43"
+ process $proc$libresoc.v:189121$13026
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:190181.7-190181.20"
- process $proc$libresoc.v:190181$13215
+ attribute \src "libresoc.v:189125.7-189125.20"
+ process $proc$libresoc.v:189125$13027
assign { } { }
assign $1\src_r3[0:0] 1'0
sync always
sync init
update \src_r3 $1\src_r3[0:0]
end
- attribute \src "libresoc.v:190185.13-190185.26"
- process $proc$libresoc.v:190185$13216
+ attribute \src "libresoc.v:189129.13-189129.26"
+ process $proc$libresoc.v:189129$13028
assign { } { }
assign $1\src_r4[1:0] 2'00
sync always
sync init
update \src_r4 $1\src_r4[1:0]
end
- attribute \src "libresoc.v:190189.13-190189.26"
- process $proc$libresoc.v:190189$13217
+ attribute \src "libresoc.v:189133.13-189133.26"
+ process $proc$libresoc.v:189133$13029
assign { } { }
assign $1\src_r5[1:0] 2'00
sync always
sync init
update \src_r5 $1\src_r5[1:0]
end
- attribute \src "libresoc.v:190266.3-190267.39"
- process $proc$libresoc.v:190266$13022
+ attribute \src "libresoc.v:189210.3-189211.39"
+ process $proc$libresoc.v:189210$12834
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:190268.3-190269.43"
- process $proc$libresoc.v:190268$13023
+ attribute \src "libresoc.v:189212.3-189213.43"
+ process $proc$libresoc.v:189212$12835
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:190270.3-190271.29"
- process $proc$libresoc.v:190270$13024
+ attribute \src "libresoc.v:189214.3-189215.29"
+ process $proc$libresoc.v:189214$12836
assign { } { }
assign $0\src_r5[1:0] \src_r5$next
sync posedge \coresync_clk
update \src_r5 $0\src_r5[1:0]
end
- attribute \src "libresoc.v:190272.3-190273.29"
- process $proc$libresoc.v:190272$13025
+ attribute \src "libresoc.v:189216.3-189217.29"
+ process $proc$libresoc.v:189216$12837
assign { } { }
assign $0\src_r4[1:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[1:0]
end
- attribute \src "libresoc.v:190274.3-190275.29"
- process $proc$libresoc.v:190274$13026
+ attribute \src "libresoc.v:189218.3-189219.29"
+ process $proc$libresoc.v:189218$12838
assign { } { }
assign $0\src_r3[0:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[0:0]
end
- attribute \src "libresoc.v:190276.3-190277.29"
- process $proc$libresoc.v:190276$13027
+ attribute \src "libresoc.v:189220.3-189221.29"
+ process $proc$libresoc.v:189220$12839
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:190278.3-190279.29"
- process $proc$libresoc.v:190278$13028
+ attribute \src "libresoc.v:189222.3-189223.29"
+ process $proc$libresoc.v:189222$12840
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:190280.3-190281.29"
- process $proc$libresoc.v:190280$13029
+ attribute \src "libresoc.v:189224.3-189225.29"
+ process $proc$libresoc.v:189224$12841
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:190282.3-190283.47"
- process $proc$libresoc.v:190282$13030
+ attribute \src "libresoc.v:189226.3-189227.47"
+ process $proc$libresoc.v:189226$12842
assign { } { }
assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next
sync posedge \coresync_clk
update \data_r5__xer_ca $0\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:190284.3-190285.53"
- process $proc$libresoc.v:190284$13031
+ attribute \src "libresoc.v:189228.3-189229.53"
+ process $proc$libresoc.v:189228$12843
assign { } { }
assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next
sync posedge \coresync_clk
update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:190286.3-190287.47"
- process $proc$libresoc.v:190286$13032
+ attribute \src "libresoc.v:189230.3-189231.47"
+ process $proc$libresoc.v:189230$12844
assign { } { }
assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next
sync posedge \coresync_clk
update \data_r4__xer_ov $0\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:190288.3-190289.53"
- process $proc$libresoc.v:190288$13033
+ attribute \src "libresoc.v:189232.3-189233.53"
+ process $proc$libresoc.v:189232$12845
assign { } { }
assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:190290.3-190291.47"
- process $proc$libresoc.v:190290$13034
+ attribute \src "libresoc.v:189234.3-189235.47"
+ process $proc$libresoc.v:189234$12846
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:190292.3-190293.53"
- process $proc$libresoc.v:190292$13035
+ attribute \src "libresoc.v:189236.3-189237.53"
+ process $proc$libresoc.v:189236$12847
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:190294.3-190295.45"
- process $proc$libresoc.v:190294$13036
+ attribute \src "libresoc.v:189238.3-189239.45"
+ process $proc$libresoc.v:189238$12848
assign { } { }
assign $0\data_r2__fast1[63:0] \data_r2__fast1$next
sync posedge \coresync_clk
update \data_r2__fast1 $0\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:190296.3-190297.51"
- process $proc$libresoc.v:190296$13037
+ attribute \src "libresoc.v:189240.3-189241.51"
+ process $proc$libresoc.v:189240$12849
assign { } { }
assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next
sync posedge \coresync_clk
update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:190298.3-190299.43"
- process $proc$libresoc.v:190298$13038
+ attribute \src "libresoc.v:189242.3-189243.43"
+ process $proc$libresoc.v:189242$12850
assign { } { }
assign $0\data_r1__spr1[63:0] \data_r1__spr1$next
sync posedge \coresync_clk
update \data_r1__spr1 $0\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:190300.3-190301.49"
- process $proc$libresoc.v:190300$13039
+ attribute \src "libresoc.v:189244.3-189245.49"
+ process $proc$libresoc.v:189244$12851
assign { } { }
assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next
sync posedge \coresync_clk
update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:190302.3-190303.37"
- process $proc$libresoc.v:190302$13040
+ attribute \src "libresoc.v:189246.3-189247.37"
+ process $proc$libresoc.v:189246$12852
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:190304.3-190305.43"
- process $proc$libresoc.v:190304$13041
+ attribute \src "libresoc.v:189248.3-189249.43"
+ process $proc$libresoc.v:189248$12853
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:190306.3-190307.69"
- process $proc$libresoc.v:190306$13042
+ attribute \src "libresoc.v:189250.3-189251.69"
+ process $proc$libresoc.v:189250$12854
assign { } { }
assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:190308.3-190309.65"
- process $proc$libresoc.v:190308$13043
+ attribute \src "libresoc.v:189252.3-189253.65"
+ process $proc$libresoc.v:189252$12855
assign { } { }
assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:190310.3-190311.59"
- process $proc$libresoc.v:190310$13044
+ attribute \src "libresoc.v:189254.3-189255.59"
+ process $proc$libresoc.v:189254$12856
assign { } { }
assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:190312.3-190313.67"
- process $proc$libresoc.v:190312$13045
+ attribute \src "libresoc.v:189256.3-189257.67"
+ process $proc$libresoc.v:189256$12857
assign { } { }
assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:190314.3-190315.39"
- process $proc$libresoc.v:190314$13046
+ attribute \src "libresoc.v:189258.3-189259.39"
+ process $proc$libresoc.v:189258$12858
assign { } { }
assign $0\req_l_r_req[5:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:190316.3-190317.39"
- process $proc$libresoc.v:190316$13047
+ attribute \src "libresoc.v:189260.3-189261.39"
+ process $proc$libresoc.v:189260$12859
assign { } { }
assign $0\req_l_s_req[5:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:190318.3-190319.39"
- process $proc$libresoc.v:190318$13048
+ attribute \src "libresoc.v:189262.3-189263.39"
+ process $proc$libresoc.v:189262$12860
assign { } { }
assign $0\src_l_r_src[5:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:190320.3-190321.39"
- process $proc$libresoc.v:190320$13049
+ attribute \src "libresoc.v:189264.3-189265.39"
+ process $proc$libresoc.v:189264$12861
assign { } { }
assign $0\src_l_s_src[5:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:190322.3-190323.39"
- process $proc$libresoc.v:190322$13050
+ attribute \src "libresoc.v:189266.3-189267.39"
+ process $proc$libresoc.v:189266$12862
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:190324.3-190325.39"
- process $proc$libresoc.v:190324$13051
+ attribute \src "libresoc.v:189268.3-189269.39"
+ process $proc$libresoc.v:189268$12863
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:190326.3-190327.39"
- process $proc$libresoc.v:190326$13052
+ attribute \src "libresoc.v:189270.3-189271.39"
+ process $proc$libresoc.v:189270$12864
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:190328.3-190329.39"
- process $proc$libresoc.v:190328$13053
+ attribute \src "libresoc.v:189272.3-189273.39"
+ process $proc$libresoc.v:189272$12865
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:190330.3-190331.41"
- process $proc$libresoc.v:190330$13054
+ attribute \src "libresoc.v:189274.3-189275.41"
+ process $proc$libresoc.v:189274$12866
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:190332.3-190333.41"
- process $proc$libresoc.v:190332$13055
+ attribute \src "libresoc.v:189276.3-189277.41"
+ process $proc$libresoc.v:189276$12867
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:190334.3-190335.37"
- process $proc$libresoc.v:190334$13056
+ attribute \src "libresoc.v:189278.3-189279.37"
+ process $proc$libresoc.v:189278$12868
assign { } { }
assign $0\prev_wr_go[5:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:190336.3-190337.40"
- process $proc$libresoc.v:190336$13057
+ attribute \src "libresoc.v:189280.3-189281.40"
+ process $proc$libresoc.v:189280$12869
assign { } { }
assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:190338.3-190339.25"
- process $proc$libresoc.v:190338$13058
+ attribute \src "libresoc.v:189282.3-189283.25"
+ process $proc$libresoc.v:189282$12870
assign { } { }
assign $0\all_rd_dly[0:0] \$14
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:190418.3-190427.6"
- process $proc$libresoc.v:190418$13059
+ attribute \src "libresoc.v:189362.3-189371.6"
+ process $proc$libresoc.v:189362$12871
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:190419.5-190419.29"
+ attribute \src "libresoc.v:189363.5-189363.29"
switch \initial
- attribute \src "libresoc.v:190419.9-190419.17"
+ attribute \src "libresoc.v:189363.9-189363.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:190428.3-190436.6"
- process $proc$libresoc.v:190428$13060
+ attribute \src "libresoc.v:189372.3-189380.6"
+ process $proc$libresoc.v:189372$12872
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$13061 $1\rok_l_s_rdok$next[0:0]$13062
- attribute \src "libresoc.v:190429.5-190429.29"
+ assign $0\rok_l_s_rdok$next[0:0]$12873 $1\rok_l_s_rdok$next[0:0]$12874
+ attribute \src "libresoc.v:189373.5-189373.29"
switch \initial
- attribute \src "libresoc.v:190429.9-190429.17"
+ attribute \src "libresoc.v:189373.9-189373.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$13062 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$12874 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$13062 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$12874 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13061
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12873
end
- attribute \src "libresoc.v:190437.3-190445.6"
- process $proc$libresoc.v:190437$13063
+ attribute \src "libresoc.v:189381.3-189389.6"
+ process $proc$libresoc.v:189381$12875
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$13064 $1\rok_l_r_rdok$next[0:0]$13065
- attribute \src "libresoc.v:190438.5-190438.29"
+ assign $0\rok_l_r_rdok$next[0:0]$12876 $1\rok_l_r_rdok$next[0:0]$12877
+ attribute \src "libresoc.v:189382.5-189382.29"
switch \initial
- attribute \src "libresoc.v:190438.9-190438.17"
+ attribute \src "libresoc.v:189382.9-189382.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$13065 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$12877 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$13065 \$68
+ assign $1\rok_l_r_rdok$next[0:0]$12877 \$68
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13064
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12876
end
- attribute \src "libresoc.v:190446.3-190454.6"
- process $proc$libresoc.v:190446$13066
+ attribute \src "libresoc.v:189390.3-189398.6"
+ process $proc$libresoc.v:189390$12878
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$13067 $1\rst_l_s_rst$next[0:0]$13068
- attribute \src "libresoc.v:190447.5-190447.29"
+ assign $0\rst_l_s_rst$next[0:0]$12879 $1\rst_l_s_rst$next[0:0]$12880
+ attribute \src "libresoc.v:189391.5-189391.29"
switch \initial
- attribute \src "libresoc.v:190447.9-190447.17"
+ attribute \src "libresoc.v:189391.9-189391.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$13068 1'0
+ assign $1\rst_l_s_rst$next[0:0]$12880 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$13068 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$12880 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13067
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12879
end
- attribute \src "libresoc.v:190455.3-190463.6"
- process $proc$libresoc.v:190455$13069
+ attribute \src "libresoc.v:189399.3-189407.6"
+ process $proc$libresoc.v:189399$12881
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$13070 $1\rst_l_r_rst$next[0:0]$13071
- attribute \src "libresoc.v:190456.5-190456.29"
+ assign $0\rst_l_r_rst$next[0:0]$12882 $1\rst_l_r_rst$next[0:0]$12883
+ attribute \src "libresoc.v:189400.5-189400.29"
switch \initial
- attribute \src "libresoc.v:190456.9-190456.17"
+ attribute \src "libresoc.v:189400.9-189400.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$13071 1'1
+ assign $1\rst_l_r_rst$next[0:0]$12883 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$13071 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$12883 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13070
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12882
end
- attribute \src "libresoc.v:190464.3-190472.6"
- process $proc$libresoc.v:190464$13072
+ attribute \src "libresoc.v:189408.3-189416.6"
+ process $proc$libresoc.v:189408$12884
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$13073 $1\opc_l_s_opc$next[0:0]$13074
- attribute \src "libresoc.v:190465.5-190465.29"
+ assign $0\opc_l_s_opc$next[0:0]$12885 $1\opc_l_s_opc$next[0:0]$12886
+ attribute \src "libresoc.v:189409.5-189409.29"
switch \initial
- attribute \src "libresoc.v:190465.9-190465.17"
+ attribute \src "libresoc.v:189409.9-189409.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$13074 1'0
+ assign $1\opc_l_s_opc$next[0:0]$12886 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$13074 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$12886 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13073
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12885
end
- attribute \src "libresoc.v:190473.3-190481.6"
- process $proc$libresoc.v:190473$13075
+ attribute \src "libresoc.v:189417.3-189425.6"
+ process $proc$libresoc.v:189417$12887
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$13076 $1\opc_l_r_opc$next[0:0]$13077
- attribute \src "libresoc.v:190474.5-190474.29"
+ assign $0\opc_l_r_opc$next[0:0]$12888 $1\opc_l_r_opc$next[0:0]$12889
+ attribute \src "libresoc.v:189418.5-189418.29"
switch \initial
- attribute \src "libresoc.v:190474.9-190474.17"
+ attribute \src "libresoc.v:189418.9-189418.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$13077 1'1
+ assign $1\opc_l_r_opc$next[0:0]$12889 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$13077 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$12889 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13076
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12888
end
- attribute \src "libresoc.v:190482.3-190490.6"
- process $proc$libresoc.v:190482$13078
+ attribute \src "libresoc.v:189426.3-189434.6"
+ process $proc$libresoc.v:189426$12890
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[5:0]$13079 $1\src_l_s_src$next[5:0]$13080
- attribute \src "libresoc.v:190483.5-190483.29"
+ assign $0\src_l_s_src$next[5:0]$12891 $1\src_l_s_src$next[5:0]$12892
+ attribute \src "libresoc.v:189427.5-189427.29"
switch \initial
- attribute \src "libresoc.v:190483.9-190483.17"
+ attribute \src "libresoc.v:189427.9-189427.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[5:0]$13080 6'000000
+ assign $1\src_l_s_src$next[5:0]$12892 6'000000
case
- assign $1\src_l_s_src$next[5:0]$13080 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[5:0]$12892 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13079
+ update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12891
end
- attribute \src "libresoc.v:190491.3-190499.6"
- process $proc$libresoc.v:190491$13081
+ attribute \src "libresoc.v:189435.3-189443.6"
+ process $proc$libresoc.v:189435$12893
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[5:0]$13082 $1\src_l_r_src$next[5:0]$13083
- attribute \src "libresoc.v:190492.5-190492.29"
+ assign $0\src_l_r_src$next[5:0]$12894 $1\src_l_r_src$next[5:0]$12895
+ attribute \src "libresoc.v:189436.5-189436.29"
switch \initial
- attribute \src "libresoc.v:190492.9-190492.17"
+ attribute \src "libresoc.v:189436.9-189436.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[5:0]$13083 6'111111
+ assign $1\src_l_r_src$next[5:0]$12895 6'111111
case
- assign $1\src_l_r_src$next[5:0]$13083 \reset_r
+ assign $1\src_l_r_src$next[5:0]$12895 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13082
+ update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12894
end
- attribute \src "libresoc.v:190500.3-190508.6"
- process $proc$libresoc.v:190500$13084
+ attribute \src "libresoc.v:189444.3-189452.6"
+ process $proc$libresoc.v:189444$12896
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[5:0]$13085 $1\req_l_s_req$next[5:0]$13086
- attribute \src "libresoc.v:190501.5-190501.29"
+ assign $0\req_l_s_req$next[5:0]$12897 $1\req_l_s_req$next[5:0]$12898
+ attribute \src "libresoc.v:189445.5-189445.29"
switch \initial
- attribute \src "libresoc.v:190501.9-190501.17"
+ attribute \src "libresoc.v:189445.9-189445.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[5:0]$13086 6'000000
+ assign $1\req_l_s_req$next[5:0]$12898 6'000000
case
- assign $1\req_l_s_req$next[5:0]$13086 \$70
+ assign $1\req_l_s_req$next[5:0]$12898 \$70
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13085
+ update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12897
end
- attribute \src "libresoc.v:190509.3-190517.6"
- process $proc$libresoc.v:190509$13087
+ attribute \src "libresoc.v:189453.3-189461.6"
+ process $proc$libresoc.v:189453$12899
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[5:0]$13088 $1\req_l_r_req$next[5:0]$13089
- attribute \src "libresoc.v:190510.5-190510.29"
+ assign $0\req_l_r_req$next[5:0]$12900 $1\req_l_r_req$next[5:0]$12901
+ attribute \src "libresoc.v:189454.5-189454.29"
switch \initial
- attribute \src "libresoc.v:190510.9-190510.17"
+ attribute \src "libresoc.v:189454.9-189454.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[5:0]$13089 6'111111
+ assign $1\req_l_r_req$next[5:0]$12901 6'111111
case
- assign $1\req_l_r_req$next[5:0]$13089 \$72
+ assign $1\req_l_r_req$next[5:0]$12901 \$72
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13088
+ update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12900
end
- attribute \src "libresoc.v:190518.3-190530.6"
- process $proc$libresoc.v:190518$13090
+ attribute \src "libresoc.v:189462.3-189474.6"
+ process $proc$libresoc.v:189462$12902
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095
- assign $0\alu_spr0_spr_op__insn$next[31:0]$13092 $1\alu_spr0_spr_op__insn$next[31:0]$13096
- assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13093 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097
- assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098
- attribute \src "libresoc.v:190519.5-190519.29"
+ assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907
+ assign $0\alu_spr0_spr_op__insn$next[31:0]$12904 $1\alu_spr0_spr_op__insn$next[31:0]$12908
+ assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12905 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909
+ assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910
+ attribute \src "libresoc.v:189463.5-189463.29"
switch \initial
- attribute \src "libresoc.v:190519.9-190519.17"
+ attribute \src "libresoc.v:189463.9-189463.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 $1\alu_spr0_spr_op__insn$next[31:0]$13096 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
+ assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910 $1\alu_spr0_spr_op__insn$next[31:0]$12908 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
case
- assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 \alu_spr0_spr_op__fn_unit
- assign $1\alu_spr0_spr_op__insn$next[31:0]$13096 \alu_spr0_spr_op__insn
- assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 \alu_spr0_spr_op__insn_type
- assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 \alu_spr0_spr_op__is_32bit
+ assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907 \alu_spr0_spr_op__fn_unit
+ assign $1\alu_spr0_spr_op__insn$next[31:0]$12908 \alu_spr0_spr_op__insn
+ assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12909 \alu_spr0_spr_op__insn_type
+ assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910 \alu_spr0_spr_op__is_32bit
end
sync always
- update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091
- update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13092
- update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13093
- update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094
+ update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903
+ update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12904
+ update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12905
+ update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906
end
- attribute \src "libresoc.v:190531.3-190552.6"
- process $proc$libresoc.v:190531$13099
+ attribute \src "libresoc.v:189475.3-189496.6"
+ process $proc$libresoc.v:189475$12911
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$13100 $2\data_r0__o$next[63:0]$13104
+ assign $0\data_r0__o$next[63:0]$12912 $2\data_r0__o$next[63:0]$12916
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$13101 $3\data_r0__o_ok$next[0:0]$13106
- attribute \src "libresoc.v:190532.5-190532.29"
+ assign $0\data_r0__o_ok$next[0:0]$12913 $3\data_r0__o_ok$next[0:0]$12918
+ attribute \src "libresoc.v:189476.5-189476.29"
switch \initial
- attribute \src "libresoc.v:190532.9-190532.17"
+ attribute \src "libresoc.v:189476.9-189476.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$13103 $1\data_r0__o$next[63:0]$13102 } { \o_ok \alu_spr0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$12915 $1\data_r0__o$next[63:0]$12914 } { \o_ok \alu_spr0_o }
case
- assign $1\data_r0__o$next[63:0]$13102 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$13103 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$12914 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$12915 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$13105 $2\data_r0__o$next[63:0]$13104 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$12917 $2\data_r0__o$next[63:0]$12916 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$13104 $1\data_r0__o$next[63:0]$13102
- assign $2\data_r0__o_ok$next[0:0]$13105 $1\data_r0__o_ok$next[0:0]$13103
+ assign $2\data_r0__o$next[63:0]$12916 $1\data_r0__o$next[63:0]$12914
+ assign $2\data_r0__o_ok$next[0:0]$12917 $1\data_r0__o_ok$next[0:0]$12915
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$13106 1'0
+ assign $3\data_r0__o_ok$next[0:0]$12918 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$13106 $2\data_r0__o_ok$next[0:0]$13105
+ assign $3\data_r0__o_ok$next[0:0]$12918 $2\data_r0__o_ok$next[0:0]$12917
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$13100
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13101
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$12912
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12913
end
- attribute \src "libresoc.v:190553.3-190574.6"
- process $proc$libresoc.v:190553$13107
+ attribute \src "libresoc.v:189497.3-189518.6"
+ process $proc$libresoc.v:189497$12919
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__spr1$next[63:0]$13108 $2\data_r1__spr1$next[63:0]$13112
+ assign $0\data_r1__spr1$next[63:0]$12920 $2\data_r1__spr1$next[63:0]$12924
assign { } { }
- assign $0\data_r1__spr1_ok$next[0:0]$13109 $3\data_r1__spr1_ok$next[0:0]$13114
- attribute \src "libresoc.v:190554.5-190554.29"
+ assign $0\data_r1__spr1_ok$next[0:0]$12921 $3\data_r1__spr1_ok$next[0:0]$12926
+ attribute \src "libresoc.v:189498.5-189498.29"
switch \initial
- attribute \src "libresoc.v:190554.9-190554.17"
+ attribute \src "libresoc.v:189498.9-189498.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__spr1_ok$next[0:0]$13111 $1\data_r1__spr1$next[63:0]$13110 } { \spr1_ok \alu_spr0_spr1 }
+ assign { $1\data_r1__spr1_ok$next[0:0]$12923 $1\data_r1__spr1$next[63:0]$12922 } { \spr1_ok \alu_spr0_spr1 }
case
- assign $1\data_r1__spr1$next[63:0]$13110 \data_r1__spr1
- assign $1\data_r1__spr1_ok$next[0:0]$13111 \data_r1__spr1_ok
+ assign $1\data_r1__spr1$next[63:0]$12922 \data_r1__spr1
+ assign $1\data_r1__spr1_ok$next[0:0]$12923 \data_r1__spr1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__spr1_ok$next[0:0]$13113 $2\data_r1__spr1$next[63:0]$13112 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__spr1_ok$next[0:0]$12925 $2\data_r1__spr1$next[63:0]$12924 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__spr1$next[63:0]$13112 $1\data_r1__spr1$next[63:0]$13110
- assign $2\data_r1__spr1_ok$next[0:0]$13113 $1\data_r1__spr1_ok$next[0:0]$13111
+ assign $2\data_r1__spr1$next[63:0]$12924 $1\data_r1__spr1$next[63:0]$12922
+ assign $2\data_r1__spr1_ok$next[0:0]$12925 $1\data_r1__spr1_ok$next[0:0]$12923
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__spr1_ok$next[0:0]$13114 1'0
+ assign $3\data_r1__spr1_ok$next[0:0]$12926 1'0
case
- assign $3\data_r1__spr1_ok$next[0:0]$13114 $2\data_r1__spr1_ok$next[0:0]$13113
+ assign $3\data_r1__spr1_ok$next[0:0]$12926 $2\data_r1__spr1_ok$next[0:0]$12925
end
sync always
- update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13108
- update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13109
+ update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12920
+ update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12921
end
- attribute \src "libresoc.v:190575.3-190596.6"
- process $proc$libresoc.v:190575$13115
+ attribute \src "libresoc.v:189519.3-189540.6"
+ process $proc$libresoc.v:189519$12927
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast1$next[63:0]$13116 $2\data_r2__fast1$next[63:0]$13120
+ assign $0\data_r2__fast1$next[63:0]$12928 $2\data_r2__fast1$next[63:0]$12932
assign { } { }
- assign $0\data_r2__fast1_ok$next[0:0]$13117 $3\data_r2__fast1_ok$next[0:0]$13122
- attribute \src "libresoc.v:190576.5-190576.29"
+ assign $0\data_r2__fast1_ok$next[0:0]$12929 $3\data_r2__fast1_ok$next[0:0]$12934
+ attribute \src "libresoc.v:189520.5-189520.29"
switch \initial
- attribute \src "libresoc.v:190576.9-190576.17"
+ attribute \src "libresoc.v:189520.9-189520.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast1_ok$next[0:0]$13119 $1\data_r2__fast1$next[63:0]$13118 } { \fast1_ok \alu_spr0_fast1 }
+ assign { $1\data_r2__fast1_ok$next[0:0]$12931 $1\data_r2__fast1$next[63:0]$12930 } { \fast1_ok \alu_spr0_fast1 }
case
- assign $1\data_r2__fast1$next[63:0]$13118 \data_r2__fast1
- assign $1\data_r2__fast1_ok$next[0:0]$13119 \data_r2__fast1_ok
+ assign $1\data_r2__fast1$next[63:0]$12930 \data_r2__fast1
+ assign $1\data_r2__fast1_ok$next[0:0]$12931 \data_r2__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast1_ok$next[0:0]$13121 $2\data_r2__fast1$next[63:0]$13120 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast1_ok$next[0:0]$12933 $2\data_r2__fast1$next[63:0]$12932 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast1$next[63:0]$13120 $1\data_r2__fast1$next[63:0]$13118
- assign $2\data_r2__fast1_ok$next[0:0]$13121 $1\data_r2__fast1_ok$next[0:0]$13119
+ assign $2\data_r2__fast1$next[63:0]$12932 $1\data_r2__fast1$next[63:0]$12930
+ assign $2\data_r2__fast1_ok$next[0:0]$12933 $1\data_r2__fast1_ok$next[0:0]$12931
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast1_ok$next[0:0]$13122 1'0
+ assign $3\data_r2__fast1_ok$next[0:0]$12934 1'0
case
- assign $3\data_r2__fast1_ok$next[0:0]$13122 $2\data_r2__fast1_ok$next[0:0]$13121
+ assign $3\data_r2__fast1_ok$next[0:0]$12934 $2\data_r2__fast1_ok$next[0:0]$12933
end
sync always
- update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13116
- update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13117
+ update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12928
+ update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12929
end
- attribute \src "libresoc.v:190597.3-190618.6"
- process $proc$libresoc.v:190597$13123
+ attribute \src "libresoc.v:189541.3-189562.6"
+ process $proc$libresoc.v:189541$12935
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$13124 $2\data_r3__xer_so$next[0:0]$13128
+ assign $0\data_r3__xer_so$next[0:0]$12936 $2\data_r3__xer_so$next[0:0]$12940
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$13125 $3\data_r3__xer_so_ok$next[0:0]$13130
- attribute \src "libresoc.v:190598.5-190598.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$12937 $3\data_r3__xer_so_ok$next[0:0]$12942
+ attribute \src "libresoc.v:189542.5-189542.29"
switch \initial
- attribute \src "libresoc.v:190598.9-190598.17"
+ attribute \src "libresoc.v:189542.9-189542.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$13127 $1\data_r3__xer_so$next[0:0]$13126 } { \xer_so_ok \alu_spr0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$12939 $1\data_r3__xer_so$next[0:0]$12938 } { \xer_so_ok \alu_spr0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$13126 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$13127 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$12938 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$12939 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$13129 $2\data_r3__xer_so$next[0:0]$13128 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$12941 $2\data_r3__xer_so$next[0:0]$12940 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$13128 $1\data_r3__xer_so$next[0:0]$13126
- assign $2\data_r3__xer_so_ok$next[0:0]$13129 $1\data_r3__xer_so_ok$next[0:0]$13127
+ assign $2\data_r3__xer_so$next[0:0]$12940 $1\data_r3__xer_so$next[0:0]$12938
+ assign $2\data_r3__xer_so_ok$next[0:0]$12941 $1\data_r3__xer_so_ok$next[0:0]$12939
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$13130 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$12942 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$13130 $2\data_r3__xer_so_ok$next[0:0]$13129
+ assign $3\data_r3__xer_so_ok$next[0:0]$12942 $2\data_r3__xer_so_ok$next[0:0]$12941
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13124
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13125
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12936
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12937
end
- attribute \src "libresoc.v:190619.3-190640.6"
- process $proc$libresoc.v:190619$13131
+ attribute \src "libresoc.v:189563.3-189584.6"
+ process $proc$libresoc.v:189563$12943
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__xer_ov$next[1:0]$13132 $2\data_r4__xer_ov$next[1:0]$13136
+ assign $0\data_r4__xer_ov$next[1:0]$12944 $2\data_r4__xer_ov$next[1:0]$12948
assign { } { }
- assign $0\data_r4__xer_ov_ok$next[0:0]$13133 $3\data_r4__xer_ov_ok$next[0:0]$13138
- attribute \src "libresoc.v:190620.5-190620.29"
+ assign $0\data_r4__xer_ov_ok$next[0:0]$12945 $3\data_r4__xer_ov_ok$next[0:0]$12950
+ attribute \src "libresoc.v:189564.5-189564.29"
switch \initial
- attribute \src "libresoc.v:190620.9-190620.17"
+ attribute \src "libresoc.v:189564.9-189564.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__xer_ov_ok$next[0:0]$13135 $1\data_r4__xer_ov$next[1:0]$13134 } { \xer_ov_ok \alu_spr0_xer_ov }
+ assign { $1\data_r4__xer_ov_ok$next[0:0]$12947 $1\data_r4__xer_ov$next[1:0]$12946 } { \xer_ov_ok \alu_spr0_xer_ov }
case
- assign $1\data_r4__xer_ov$next[1:0]$13134 \data_r4__xer_ov
- assign $1\data_r4__xer_ov_ok$next[0:0]$13135 \data_r4__xer_ov_ok
+ assign $1\data_r4__xer_ov$next[1:0]$12946 \data_r4__xer_ov
+ assign $1\data_r4__xer_ov_ok$next[0:0]$12947 \data_r4__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__xer_ov_ok$next[0:0]$13137 $2\data_r4__xer_ov$next[1:0]$13136 } 3'000
+ assign { $2\data_r4__xer_ov_ok$next[0:0]$12949 $2\data_r4__xer_ov$next[1:0]$12948 } 3'000
case
- assign $2\data_r4__xer_ov$next[1:0]$13136 $1\data_r4__xer_ov$next[1:0]$13134
- assign $2\data_r4__xer_ov_ok$next[0:0]$13137 $1\data_r4__xer_ov_ok$next[0:0]$13135
+ assign $2\data_r4__xer_ov$next[1:0]$12948 $1\data_r4__xer_ov$next[1:0]$12946
+ assign $2\data_r4__xer_ov_ok$next[0:0]$12949 $1\data_r4__xer_ov_ok$next[0:0]$12947
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__xer_ov_ok$next[0:0]$13138 1'0
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12950 1'0
case
- assign $3\data_r4__xer_ov_ok$next[0:0]$13138 $2\data_r4__xer_ov_ok$next[0:0]$13137
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12950 $2\data_r4__xer_ov_ok$next[0:0]$12949
end
sync always
- update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13132
- update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13133
+ update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12944
+ update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12945
end
- attribute \src "libresoc.v:190641.3-190662.6"
- process $proc$libresoc.v:190641$13139
+ attribute \src "libresoc.v:189585.3-189606.6"
+ process $proc$libresoc.v:189585$12951
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r5__xer_ca$next[1:0]$13140 $2\data_r5__xer_ca$next[1:0]$13144
+ assign $0\data_r5__xer_ca$next[1:0]$12952 $2\data_r5__xer_ca$next[1:0]$12956
assign { } { }
- assign $0\data_r5__xer_ca_ok$next[0:0]$13141 $3\data_r5__xer_ca_ok$next[0:0]$13146
- attribute \src "libresoc.v:190642.5-190642.29"
+ assign $0\data_r5__xer_ca_ok$next[0:0]$12953 $3\data_r5__xer_ca_ok$next[0:0]$12958
+ attribute \src "libresoc.v:189586.5-189586.29"
switch \initial
- attribute \src "libresoc.v:190642.9-190642.17"
+ attribute \src "libresoc.v:189586.9-189586.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r5__xer_ca_ok$next[0:0]$13143 $1\data_r5__xer_ca$next[1:0]$13142 } { \xer_ca_ok \alu_spr0_xer_ca }
+ assign { $1\data_r5__xer_ca_ok$next[0:0]$12955 $1\data_r5__xer_ca$next[1:0]$12954 } { \xer_ca_ok \alu_spr0_xer_ca }
case
- assign $1\data_r5__xer_ca$next[1:0]$13142 \data_r5__xer_ca
- assign $1\data_r5__xer_ca_ok$next[0:0]$13143 \data_r5__xer_ca_ok
+ assign $1\data_r5__xer_ca$next[1:0]$12954 \data_r5__xer_ca
+ assign $1\data_r5__xer_ca_ok$next[0:0]$12955 \data_r5__xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r5__xer_ca_ok$next[0:0]$13145 $2\data_r5__xer_ca$next[1:0]$13144 } 3'000
+ assign { $2\data_r5__xer_ca_ok$next[0:0]$12957 $2\data_r5__xer_ca$next[1:0]$12956 } 3'000
case
- assign $2\data_r5__xer_ca$next[1:0]$13144 $1\data_r5__xer_ca$next[1:0]$13142
- assign $2\data_r5__xer_ca_ok$next[0:0]$13145 $1\data_r5__xer_ca_ok$next[0:0]$13143
+ assign $2\data_r5__xer_ca$next[1:0]$12956 $1\data_r5__xer_ca$next[1:0]$12954
+ assign $2\data_r5__xer_ca_ok$next[0:0]$12957 $1\data_r5__xer_ca_ok$next[0:0]$12955
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r5__xer_ca_ok$next[0:0]$13146 1'0
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12958 1'0
case
- assign $3\data_r5__xer_ca_ok$next[0:0]$13146 $2\data_r5__xer_ca_ok$next[0:0]$13145
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12958 $2\data_r5__xer_ca_ok$next[0:0]$12957
end
sync always
- update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13140
- update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13141
+ update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12952
+ update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12953
end
- attribute \src "libresoc.v:190663.3-190672.6"
- process $proc$libresoc.v:190663$13147
+ attribute \src "libresoc.v:189607.3-189616.6"
+ process $proc$libresoc.v:189607$12959
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$13148 $1\src_r0$next[63:0]$13149
- attribute \src "libresoc.v:190664.5-190664.29"
+ assign $0\src_r0$next[63:0]$12960 $1\src_r0$next[63:0]$12961
+ attribute \src "libresoc.v:189608.5-189608.29"
switch \initial
- attribute \src "libresoc.v:190664.9-190664.17"
+ attribute \src "libresoc.v:189608.9-189608.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$13149 \src1_i
+ assign $1\src_r0$next[63:0]$12961 \src1_i
case
- assign $1\src_r0$next[63:0]$13149 \src_r0
+ assign $1\src_r0$next[63:0]$12961 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$13148
+ update \src_r0$next $0\src_r0$next[63:0]$12960
end
- attribute \src "libresoc.v:190673.3-190682.6"
- process $proc$libresoc.v:190673$13150
+ attribute \src "libresoc.v:189617.3-189626.6"
+ process $proc$libresoc.v:189617$12962
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$13151 $1\src_r1$next[63:0]$13152
- attribute \src "libresoc.v:190674.5-190674.29"
+ assign $0\src_r1$next[63:0]$12963 $1\src_r1$next[63:0]$12964
+ attribute \src "libresoc.v:189618.5-189618.29"
switch \initial
- attribute \src "libresoc.v:190674.9-190674.17"
+ attribute \src "libresoc.v:189618.9-189618.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$13152 \src2_i
+ assign $1\src_r1$next[63:0]$12964 \src2_i
case
- assign $1\src_r1$next[63:0]$13152 \src_r1
+ assign $1\src_r1$next[63:0]$12964 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$13151
+ update \src_r1$next $0\src_r1$next[63:0]$12963
end
- attribute \src "libresoc.v:190683.3-190692.6"
- process $proc$libresoc.v:190683$13153
+ attribute \src "libresoc.v:189627.3-189636.6"
+ process $proc$libresoc.v:189627$12965
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$13154 $1\src_r2$next[63:0]$13155
- attribute \src "libresoc.v:190684.5-190684.29"
+ assign $0\src_r2$next[63:0]$12966 $1\src_r2$next[63:0]$12967
+ attribute \src "libresoc.v:189628.5-189628.29"
switch \initial
- attribute \src "libresoc.v:190684.9-190684.17"
+ attribute \src "libresoc.v:189628.9-189628.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$13155 \src3_i
+ assign $1\src_r2$next[63:0]$12967 \src3_i
case
- assign $1\src_r2$next[63:0]$13155 \src_r2
+ assign $1\src_r2$next[63:0]$12967 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$13154
+ update \src_r2$next $0\src_r2$next[63:0]$12966
end
- attribute \src "libresoc.v:190693.3-190702.6"
- process $proc$libresoc.v:190693$13156
+ attribute \src "libresoc.v:189637.3-189646.6"
+ process $proc$libresoc.v:189637$12968
assign { } { }
assign { } { }
- assign $0\src_r3$next[0:0]$13157 $1\src_r3$next[0:0]$13158
- attribute \src "libresoc.v:190694.5-190694.29"
+ assign $0\src_r3$next[0:0]$12969 $1\src_r3$next[0:0]$12970
+ attribute \src "libresoc.v:189638.5-189638.29"
switch \initial
- attribute \src "libresoc.v:190694.9-190694.17"
+ attribute \src "libresoc.v:189638.9-189638.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[0:0]$13158 \src4_i
+ assign $1\src_r3$next[0:0]$12970 \src4_i
case
- assign $1\src_r3$next[0:0]$13158 \src_r3
+ assign $1\src_r3$next[0:0]$12970 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[0:0]$13157
+ update \src_r3$next $0\src_r3$next[0:0]$12969
end
- attribute \src "libresoc.v:190703.3-190712.6"
- process $proc$libresoc.v:190703$13159
+ attribute \src "libresoc.v:189647.3-189656.6"
+ process $proc$libresoc.v:189647$12971
assign { } { }
assign { } { }
- assign $0\src_r4$next[1:0]$13160 $1\src_r4$next[1:0]$13161
- attribute \src "libresoc.v:190704.5-190704.29"
+ assign $0\src_r4$next[1:0]$12972 $1\src_r4$next[1:0]$12973
+ attribute \src "libresoc.v:189648.5-189648.29"
switch \initial
- attribute \src "libresoc.v:190704.9-190704.17"
+ attribute \src "libresoc.v:189648.9-189648.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[1:0]$13161 \src5_i
+ assign $1\src_r4$next[1:0]$12973 \src5_i
case
- assign $1\src_r4$next[1:0]$13161 \src_r4
+ assign $1\src_r4$next[1:0]$12973 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[1:0]$13160
+ update \src_r4$next $0\src_r4$next[1:0]$12972
end
- attribute \src "libresoc.v:190713.3-190722.6"
- process $proc$libresoc.v:190713$13162
+ attribute \src "libresoc.v:189657.3-189666.6"
+ process $proc$libresoc.v:189657$12974
assign { } { }
assign { } { }
- assign $0\src_r5$next[1:0]$13163 $1\src_r5$next[1:0]$13164
- attribute \src "libresoc.v:190714.5-190714.29"
+ assign $0\src_r5$next[1:0]$12975 $1\src_r5$next[1:0]$12976
+ attribute \src "libresoc.v:189658.5-189658.29"
switch \initial
- attribute \src "libresoc.v:190714.9-190714.17"
+ attribute \src "libresoc.v:189658.9-189658.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r5$next[1:0]$13164 \src6_i
+ assign $1\src_r5$next[1:0]$12976 \src6_i
case
- assign $1\src_r5$next[1:0]$13164 \src_r5
+ assign $1\src_r5$next[1:0]$12976 \src_r5
end
sync always
- update \src_r5$next $0\src_r5$next[1:0]$13163
+ update \src_r5$next $0\src_r5$next[1:0]$12975
end
- attribute \src "libresoc.v:190723.3-190731.6"
- process $proc$libresoc.v:190723$13165
+ attribute \src "libresoc.v:189667.3-189675.6"
+ process $proc$libresoc.v:189667$12977
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$13166 $1\alui_l_r_alui$next[0:0]$13167
- attribute \src "libresoc.v:190724.5-190724.29"
+ assign $0\alui_l_r_alui$next[0:0]$12978 $1\alui_l_r_alui$next[0:0]$12979
+ attribute \src "libresoc.v:189668.5-189668.29"
switch \initial
- attribute \src "libresoc.v:190724.9-190724.17"
+ attribute \src "libresoc.v:189668.9-189668.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$13167 1'1
+ assign $1\alui_l_r_alui$next[0:0]$12979 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$13167 \$98
+ assign $1\alui_l_r_alui$next[0:0]$12979 \$98
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13166
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12978
end
- attribute \src "libresoc.v:190732.3-190740.6"
- process $proc$libresoc.v:190732$13168
+ attribute \src "libresoc.v:189676.3-189684.6"
+ process $proc$libresoc.v:189676$12980
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$13169 $1\alu_l_r_alu$next[0:0]$13170
- attribute \src "libresoc.v:190733.5-190733.29"
+ assign $0\alu_l_r_alu$next[0:0]$12981 $1\alu_l_r_alu$next[0:0]$12982
+ attribute \src "libresoc.v:189677.5-189677.29"
switch \initial
- attribute \src "libresoc.v:190733.9-190733.17"
+ attribute \src "libresoc.v:189677.9-189677.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$13170 1'1
+ assign $1\alu_l_r_alu$next[0:0]$12982 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$13170 \$100
+ assign $1\alu_l_r_alu$next[0:0]$12982 \$100
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13169
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12981
end
- attribute \src "libresoc.v:190741.3-190750.6"
- process $proc$libresoc.v:190741$13171
+ attribute \src "libresoc.v:189685.3-189694.6"
+ process $proc$libresoc.v:189685$12983
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:190742.5-190742.29"
+ attribute \src "libresoc.v:189686.5-189686.29"
switch \initial
- attribute \src "libresoc.v:190742.9-190742.17"
+ attribute \src "libresoc.v:189686.9-189686.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:190751.3-190760.6"
- process $proc$libresoc.v:190751$13172
+ attribute \src "libresoc.v:189695.3-189704.6"
+ process $proc$libresoc.v:189695$12984
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:190752.5-190752.29"
+ attribute \src "libresoc.v:189696.5-189696.29"
switch \initial
- attribute \src "libresoc.v:190752.9-190752.17"
+ attribute \src "libresoc.v:189696.9-189696.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:190761.3-190770.6"
- process $proc$libresoc.v:190761$13173
+ attribute \src "libresoc.v:189705.3-189714.6"
+ process $proc$libresoc.v:189705$12985
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:190762.5-190762.29"
+ attribute \src "libresoc.v:189706.5-189706.29"
switch \initial
- attribute \src "libresoc.v:190762.9-190762.17"
+ attribute \src "libresoc.v:189706.9-189706.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:190771.3-190780.6"
- process $proc$libresoc.v:190771$13174
+ attribute \src "libresoc.v:189715.3-189724.6"
+ process $proc$libresoc.v:189715$12986
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:190772.5-190772.29"
+ attribute \src "libresoc.v:189716.5-189716.29"
switch \initial
- attribute \src "libresoc.v:190772.9-190772.17"
+ attribute \src "libresoc.v:189716.9-189716.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:190781.3-190790.6"
- process $proc$libresoc.v:190781$13175
+ attribute \src "libresoc.v:189725.3-189734.6"
+ process $proc$libresoc.v:189725$12987
assign { } { }
assign { } { }
assign $0\dest5_o[1:0] $1\dest5_o[1:0]
- attribute \src "libresoc.v:190782.5-190782.29"
+ attribute \src "libresoc.v:189726.5-189726.29"
switch \initial
- attribute \src "libresoc.v:190782.9-190782.17"
+ attribute \src "libresoc.v:189726.9-189726.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[1:0]
end
- attribute \src "libresoc.v:190791.3-190800.6"
- process $proc$libresoc.v:190791$13176
+ attribute \src "libresoc.v:189735.3-189744.6"
+ process $proc$libresoc.v:189735$12988
assign { } { }
assign { } { }
assign $0\dest6_o[1:0] $1\dest6_o[1:0]
- attribute \src "libresoc.v:190792.5-190792.29"
+ attribute \src "libresoc.v:189736.5-189736.29"
switch \initial
- attribute \src "libresoc.v:190792.9-190792.17"
+ attribute \src "libresoc.v:189736.9-189736.17"
case 1'1
case
end
sync always
update \dest6_o $0\dest6_o[1:0]
end
- attribute \src "libresoc.v:190801.3-190809.6"
- process $proc$libresoc.v:190801$13177
+ attribute \src "libresoc.v:189745.3-189753.6"
+ process $proc$libresoc.v:189745$12989
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[5:0]$13178 $1\prev_wr_go$next[5:0]$13179
- attribute \src "libresoc.v:190802.5-190802.29"
+ assign $0\prev_wr_go$next[5:0]$12990 $1\prev_wr_go$next[5:0]$12991
+ attribute \src "libresoc.v:189746.5-189746.29"
switch \initial
- attribute \src "libresoc.v:190802.9-190802.17"
+ attribute \src "libresoc.v:189746.9-189746.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[5:0]$13179 6'000000
- case
- assign $1\prev_wr_go$next[5:0]$13179 \$24
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13178
- end
- connect \$9 $not$libresoc.v:190200$12956_Y
- connect \$100 $and$libresoc.v:190201$12957_Y
- connect \$102 $and$libresoc.v:190202$12958_Y
- connect \$104 $and$libresoc.v:190203$12959_Y
- connect \$106 $not$libresoc.v:190204$12960_Y
- connect \$108 $and$libresoc.v:190205$12961_Y
- connect \$110 $and$libresoc.v:190206$12962_Y
- connect \$112 $and$libresoc.v:190207$12963_Y
- connect \$114 $and$libresoc.v:190208$12964_Y
- connect \$116 $and$libresoc.v:190209$12965_Y
- connect \$118 $and$libresoc.v:190210$12966_Y
- connect \$11 $or$libresoc.v:190211$12967_Y
- connect \$120 $and$libresoc.v:190212$12968_Y
- connect \$122 $and$libresoc.v:190213$12969_Y
- connect \$124 $and$libresoc.v:190214$12970_Y
- connect \$126 $and$libresoc.v:190215$12971_Y
- connect \$128 $and$libresoc.v:190216$12972_Y
- connect \$8 $reduce_and$libresoc.v:190217$12973_Y
- connect \$130 $and$libresoc.v:190218$12974_Y
- connect \$132 $and$libresoc.v:190219$12975_Y
- connect \$134 $and$libresoc.v:190220$12976_Y
- connect \$136 $and$libresoc.v:190221$12977_Y
- connect \$14 $and$libresoc.v:190222$12978_Y
- connect \$16 $not$libresoc.v:190223$12979_Y
- connect \$18 $and$libresoc.v:190224$12980_Y
- connect \$20 $not$libresoc.v:190225$12981_Y
- connect \$22 $and$libresoc.v:190226$12982_Y
- connect \$24 $and$libresoc.v:190227$12983_Y
- connect \$28 $not$libresoc.v:190228$12984_Y
- connect \$30 $and$libresoc.v:190229$12985_Y
- connect \$27 $reduce_or$libresoc.v:190230$12986_Y
- connect \$26 $not$libresoc.v:190231$12987_Y
- connect \$34 $and$libresoc.v:190232$12988_Y
- connect \$36 $reduce_or$libresoc.v:190233$12989_Y
- connect \$38 $reduce_or$libresoc.v:190234$12990_Y
- connect \$40 $or$libresoc.v:190235$12991_Y
- connect \$42 $not$libresoc.v:190236$12992_Y
- connect \$44 $and$libresoc.v:190237$12993_Y
- connect \$46 $and$libresoc.v:190238$12994_Y
- connect \$48 $eq$libresoc.v:190239$12995_Y
- connect \$50 $and$libresoc.v:190240$12996_Y
- connect \$52 $eq$libresoc.v:190241$12997_Y
- connect \$54 $and$libresoc.v:190242$12998_Y
- connect \$56 $and$libresoc.v:190243$12999_Y
- connect \$58 $and$libresoc.v:190244$13000_Y
- connect \$60 $or$libresoc.v:190245$13001_Y
- connect \$62 $or$libresoc.v:190246$13002_Y
- connect \$64 $or$libresoc.v:190247$13003_Y
- connect \$66 $or$libresoc.v:190248$13004_Y
- connect \$68 $and$libresoc.v:190249$13005_Y
- connect \$6 $and$libresoc.v:190250$13006_Y
- connect \$70 $and$libresoc.v:190251$13007_Y
- connect \$72 $or$libresoc.v:190252$13008_Y
- connect \$74 $and$libresoc.v:190253$13009_Y
- connect \$76 $and$libresoc.v:190254$13010_Y
- connect \$78 $and$libresoc.v:190255$13011_Y
- connect \$80 $and$libresoc.v:190256$13012_Y
- connect \$82 $and$libresoc.v:190257$13013_Y
- connect \$84 $and$libresoc.v:190258$13014_Y
- connect \$86 $ternary$libresoc.v:190259$13015_Y
- connect \$88 $ternary$libresoc.v:190260$13016_Y
- connect \$90 $ternary$libresoc.v:190261$13017_Y
- connect \$92 $ternary$libresoc.v:190262$13018_Y
- connect \$94 $ternary$libresoc.v:190263$13019_Y
- connect \$96 $ternary$libresoc.v:190264$13020_Y
- connect \$98 $and$libresoc.v:190265$13021_Y
+ assign $1\prev_wr_go$next[5:0]$12991 6'000000
+ case
+ assign $1\prev_wr_go$next[5:0]$12991 \$24
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12990
+ end
+ connect \$9 $not$libresoc.v:189144$12768_Y
+ connect \$100 $and$libresoc.v:189145$12769_Y
+ connect \$102 $and$libresoc.v:189146$12770_Y
+ connect \$104 $and$libresoc.v:189147$12771_Y
+ connect \$106 $not$libresoc.v:189148$12772_Y
+ connect \$108 $and$libresoc.v:189149$12773_Y
+ connect \$110 $and$libresoc.v:189150$12774_Y
+ connect \$112 $and$libresoc.v:189151$12775_Y
+ connect \$114 $and$libresoc.v:189152$12776_Y
+ connect \$116 $and$libresoc.v:189153$12777_Y
+ connect \$118 $and$libresoc.v:189154$12778_Y
+ connect \$11 $or$libresoc.v:189155$12779_Y
+ connect \$120 $and$libresoc.v:189156$12780_Y
+ connect \$122 $and$libresoc.v:189157$12781_Y
+ connect \$124 $and$libresoc.v:189158$12782_Y
+ connect \$126 $and$libresoc.v:189159$12783_Y
+ connect \$128 $and$libresoc.v:189160$12784_Y
+ connect \$8 $reduce_and$libresoc.v:189161$12785_Y
+ connect \$130 $and$libresoc.v:189162$12786_Y
+ connect \$132 $and$libresoc.v:189163$12787_Y
+ connect \$134 $and$libresoc.v:189164$12788_Y
+ connect \$136 $and$libresoc.v:189165$12789_Y
+ connect \$14 $and$libresoc.v:189166$12790_Y
+ connect \$16 $not$libresoc.v:189167$12791_Y
+ connect \$18 $and$libresoc.v:189168$12792_Y
+ connect \$20 $not$libresoc.v:189169$12793_Y
+ connect \$22 $and$libresoc.v:189170$12794_Y
+ connect \$24 $and$libresoc.v:189171$12795_Y
+ connect \$28 $not$libresoc.v:189172$12796_Y
+ connect \$30 $and$libresoc.v:189173$12797_Y
+ connect \$27 $reduce_or$libresoc.v:189174$12798_Y
+ connect \$26 $not$libresoc.v:189175$12799_Y
+ connect \$34 $and$libresoc.v:189176$12800_Y
+ connect \$36 $reduce_or$libresoc.v:189177$12801_Y
+ connect \$38 $reduce_or$libresoc.v:189178$12802_Y
+ connect \$40 $or$libresoc.v:189179$12803_Y
+ connect \$42 $not$libresoc.v:189180$12804_Y
+ connect \$44 $and$libresoc.v:189181$12805_Y
+ connect \$46 $and$libresoc.v:189182$12806_Y
+ connect \$48 $eq$libresoc.v:189183$12807_Y
+ connect \$50 $and$libresoc.v:189184$12808_Y
+ connect \$52 $eq$libresoc.v:189185$12809_Y
+ connect \$54 $and$libresoc.v:189186$12810_Y
+ connect \$56 $and$libresoc.v:189187$12811_Y
+ connect \$58 $and$libresoc.v:189188$12812_Y
+ connect \$60 $or$libresoc.v:189189$12813_Y
+ connect \$62 $or$libresoc.v:189190$12814_Y
+ connect \$64 $or$libresoc.v:189191$12815_Y
+ connect \$66 $or$libresoc.v:189192$12816_Y
+ connect \$68 $and$libresoc.v:189193$12817_Y
+ connect \$6 $and$libresoc.v:189194$12818_Y
+ connect \$70 $and$libresoc.v:189195$12819_Y
+ connect \$72 $or$libresoc.v:189196$12820_Y
+ connect \$74 $and$libresoc.v:189197$12821_Y
+ connect \$76 $and$libresoc.v:189198$12822_Y
+ connect \$78 $and$libresoc.v:189199$12823_Y
+ connect \$80 $and$libresoc.v:189200$12824_Y
+ connect \$82 $and$libresoc.v:189201$12825_Y
+ connect \$84 $and$libresoc.v:189202$12826_Y
+ connect \$86 $ternary$libresoc.v:189203$12827_Y
+ connect \$88 $ternary$libresoc.v:189204$12828_Y
+ connect \$90 $ternary$libresoc.v:189205$12829_Y
+ connect \$92 $ternary$libresoc.v:189206$12830_Y
+ connect \$94 $ternary$libresoc.v:189207$12831_Y
+ connect \$96 $ternary$libresoc.v:189208$12832_Y
+ connect \$98 $and$libresoc.v:189209$12833_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$124
connect \all_rd_dly$next \all_rd
connect \all_rd \$14
end
-attribute \src "libresoc.v:190845.1-191369.10"
+attribute \src "libresoc.v:189789.1-190313.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main"
attribute \generator "nMigen"
module \spr_main
- attribute \src "libresoc.v:191118.3-191133.6"
- wire width 64 $0\fast1$7[63:0]$13226
- attribute \src "libresoc.v:191199.3-191214.6"
+ attribute \src "libresoc.v:190062.3-190077.6"
+ wire width 64 $0\fast1$7[63:0]$13038
+ attribute \src "libresoc.v:190143.3-190158.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:190846.7-190846.20"
+ attribute \src "libresoc.v:189790.7-189790.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:191347.3-191365.6"
- wire width 64 $0\spr1$6[63:0]$13251
- attribute \src "libresoc.v:191134.3-191152.6"
+ attribute \src "libresoc.v:190291.3-190309.6"
+ wire width 64 $0\spr1$6[63:0]$13063
+ attribute \src "libresoc.v:190078.3-190096.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:191302.3-191325.6"
- wire width 2 $0\xer_ca$10[1:0]$13245
- attribute \src "libresoc.v:191326.3-191346.6"
+ attribute \src "libresoc.v:190246.3-190269.6"
+ wire width 2 $0\xer_ca$10[1:0]$13057
+ attribute \src "libresoc.v:190270.3-190290.6"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:191257.3-191280.6"
- wire width 2 $0\xer_ov$9[1:0]$13239
- attribute \src "libresoc.v:191281.3-191301.6"
+ attribute \src "libresoc.v:190201.3-190224.6"
+ wire width 2 $0\xer_ov$9[1:0]$13051
+ attribute \src "libresoc.v:190225.3-190245.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:191215.3-191235.6"
- wire $0\xer_so$8[0:0]$13233
- attribute \src "libresoc.v:191236.3-191256.6"
+ attribute \src "libresoc.v:190159.3-190179.6"
+ wire $0\xer_so$8[0:0]$13045
+ attribute \src "libresoc.v:190180.3-190200.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:191118.3-191133.6"
- wire width 64 $1\fast1$7[63:0]$13227
- attribute \src "libresoc.v:191199.3-191214.6"
+ attribute \src "libresoc.v:190062.3-190077.6"
+ wire width 64 $1\fast1$7[63:0]$13039
+ attribute \src "libresoc.v:190143.3-190158.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:191347.3-191365.6"
- wire width 64 $1\spr1$6[63:0]$13252
- attribute \src "libresoc.v:191134.3-191152.6"
+ attribute \src "libresoc.v:190291.3-190309.6"
+ wire width 64 $1\spr1$6[63:0]$13064
+ attribute \src "libresoc.v:190078.3-190096.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:191302.3-191325.6"
- wire width 2 $1\xer_ca$10[1:0]$13246
- attribute \src "libresoc.v:191326.3-191346.6"
+ attribute \src "libresoc.v:190246.3-190269.6"
+ wire width 2 $1\xer_ca$10[1:0]$13058
+ attribute \src "libresoc.v:190270.3-190290.6"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:191257.3-191280.6"
- wire width 2 $1\xer_ov$9[1:0]$13240
- attribute \src "libresoc.v:191281.3-191301.6"
+ attribute \src "libresoc.v:190201.3-190224.6"
+ wire width 2 $1\xer_ov$9[1:0]$13052
+ attribute \src "libresoc.v:190225.3-190245.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:191215.3-191235.6"
- wire $1\xer_so$8[0:0]$13234
- attribute \src "libresoc.v:191236.3-191256.6"
+ attribute \src "libresoc.v:190159.3-190179.6"
+ wire $1\xer_so$8[0:0]$13046
+ attribute \src "libresoc.v:190180.3-190200.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:191118.3-191133.6"
- wire width 64 $2\fast1$7[63:0]$13228
- attribute \src "libresoc.v:191199.3-191214.6"
+ attribute \src "libresoc.v:190062.3-190077.6"
+ wire width 64 $2\fast1$7[63:0]$13040
+ attribute \src "libresoc.v:190143.3-190158.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:191347.3-191365.6"
- wire width 64 $2\spr1$6[63:0]$13253
- attribute \src "libresoc.v:191134.3-191152.6"
+ attribute \src "libresoc.v:190291.3-190309.6"
+ wire width 64 $2\spr1$6[63:0]$13065
+ attribute \src "libresoc.v:190078.3-190096.6"
wire $2\spr1_ok[0:0]
- attribute \src "libresoc.v:191302.3-191325.6"
- wire width 2 $2\xer_ca$10[1:0]$13247
- attribute \src "libresoc.v:191326.3-191346.6"
+ attribute \src "libresoc.v:190246.3-190269.6"
+ wire width 2 $2\xer_ca$10[1:0]$13059
+ attribute \src "libresoc.v:190270.3-190290.6"
wire $2\xer_ca_ok[0:0]
- attribute \src "libresoc.v:191257.3-191280.6"
- wire width 2 $2\xer_ov$9[1:0]$13241
- attribute \src "libresoc.v:191281.3-191301.6"
+ attribute \src "libresoc.v:190201.3-190224.6"
+ wire width 2 $2\xer_ov$9[1:0]$13053
+ attribute \src "libresoc.v:190225.3-190245.6"
wire $2\xer_ov_ok[0:0]
- attribute \src "libresoc.v:191215.3-191235.6"
- wire $2\xer_so$8[0:0]$13235
- attribute \src "libresoc.v:191236.3-191256.6"
+ attribute \src "libresoc.v:190159.3-190179.6"
+ wire $2\xer_so$8[0:0]$13047
+ attribute \src "libresoc.v:190180.3-190200.6"
wire $2\xer_so_ok[0:0]
- attribute \src "libresoc.v:191153.3-191198.6"
+ attribute \src "libresoc.v:190097.3-190142.6"
wire width 46 $3\o[63:18]
- attribute \src "libresoc.v:191302.3-191325.6"
- wire width 2 $3\xer_ca$10[1:0]$13248
- attribute \src "libresoc.v:191326.3-191346.6"
+ attribute \src "libresoc.v:190246.3-190269.6"
+ wire width 2 $3\xer_ca$10[1:0]$13060
+ attribute \src "libresoc.v:190270.3-190290.6"
wire $3\xer_ca_ok[0:0]
- attribute \src "libresoc.v:191257.3-191280.6"
- wire width 2 $3\xer_ov$9[1:0]$13242
- attribute \src "libresoc.v:191281.3-191301.6"
+ attribute \src "libresoc.v:190201.3-190224.6"
+ wire width 2 $3\xer_ov$9[1:0]$13054
+ attribute \src "libresoc.v:190225.3-190245.6"
wire $3\xer_ov_ok[0:0]
- attribute \src "libresoc.v:191215.3-191235.6"
- wire $3\xer_so$8[0:0]$13236
- attribute \src "libresoc.v:191236.3-191256.6"
+ attribute \src "libresoc.v:190159.3-190179.6"
+ wire $3\xer_so$8[0:0]$13048
+ attribute \src "libresoc.v:190180.3-190200.6"
wire $3\xer_so_ok[0:0]
- attribute \src "libresoc.v:191111.18-191111.106"
- wire $eq$libresoc.v:191111$13218_Y
- attribute \src "libresoc.v:191112.18-191112.106"
- wire $eq$libresoc.v:191112$13219_Y
- attribute \src "libresoc.v:191113.18-191113.106"
- wire $eq$libresoc.v:191113$13220_Y
- attribute \src "libresoc.v:191114.18-191114.106"
- wire $eq$libresoc.v:191114$13221_Y
- attribute \src "libresoc.v:191115.18-191115.106"
- wire $eq$libresoc.v:191115$13222_Y
- attribute \src "libresoc.v:191116.18-191116.106"
- wire $eq$libresoc.v:191116$13223_Y
- attribute \src "libresoc.v:191117.18-191117.106"
- wire $eq$libresoc.v:191117$13224_Y
+ attribute \src "libresoc.v:190055.18-190055.106"
+ wire $eq$libresoc.v:190055$13030_Y
+ attribute \src "libresoc.v:190056.18-190056.106"
+ wire $eq$libresoc.v:190056$13031_Y
+ attribute \src "libresoc.v:190057.18-190057.106"
+ wire $eq$libresoc.v:190057$13032_Y
+ attribute \src "libresoc.v:190058.18-190058.106"
+ wire $eq$libresoc.v:190058$13033_Y
+ attribute \src "libresoc.v:190059.18-190059.106"
+ wire $eq$libresoc.v:190059$13034_Y
+ attribute \src "libresoc.v:190060.18-190060.106"
+ wire $eq$libresoc.v:190060$13035_Y
+ attribute \src "libresoc.v:190061.18-190061.106"
+ wire $eq$libresoc.v:190061$13036_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
wire \$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
wire width 64 output 20 \fast1$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 21 \fast1_ok
- attribute \src "libresoc.v:190846.7-190846.15"
+ attribute \src "libresoc.v:189790.7-189790.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 28 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 23 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191111$13218
+ cell $eq $eq$libresoc.v:190055$13030
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191111$13218_Y
+ connect \Y $eq$libresoc.v:190055$13030_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191112$13219
+ cell $eq $eq$libresoc.v:190056$13031
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191112$13219_Y
+ connect \Y $eq$libresoc.v:190056$13031_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191113$13220
+ cell $eq $eq$libresoc.v:190057$13032
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191113$13220_Y
+ connect \Y $eq$libresoc.v:190057$13032_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191114$13221
+ cell $eq $eq$libresoc.v:190058$13033
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191114$13221_Y
+ connect \Y $eq$libresoc.v:190058$13033_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191115$13222
+ cell $eq $eq$libresoc.v:190059$13034
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191115$13222_Y
+ connect \Y $eq$libresoc.v:190059$13034_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:191116$13223
+ cell $eq $eq$libresoc.v:190060$13035
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191116$13223_Y
+ connect \Y $eq$libresoc.v:190060$13035_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82"
- cell $eq $eq$libresoc.v:191117$13224
+ cell $eq $eq$libresoc.v:190061$13036
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:191117$13224_Y
+ connect \Y $eq$libresoc.v:190061$13036_Y
end
- attribute \src "libresoc.v:190846.7-190846.20"
- process $proc$libresoc.v:190846$13254
+ attribute \src "libresoc.v:189790.7-189790.20"
+ process $proc$libresoc.v:189790$13066
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:191118.3-191133.6"
- process $proc$libresoc.v:191118$13225
+ attribute \src "libresoc.v:190062.3-190077.6"
+ process $proc$libresoc.v:190062$13037
assign { } { }
assign { } { }
- assign $0\fast1$7[63:0]$13226 $1\fast1$7[63:0]$13227
- attribute \src "libresoc.v:191119.5-191119.29"
+ assign $0\fast1$7[63:0]$13038 $1\fast1$7[63:0]$13039
+ attribute \src "libresoc.v:190063.5-190063.29"
switch \initial
- attribute \src "libresoc.v:191119.9-191119.17"
+ attribute \src "libresoc.v:190063.9-190063.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\fast1$7[63:0]$13227 $2\fast1$7[63:0]$13228
+ assign $1\fast1$7[63:0]$13039 $2\fast1$7[63:0]$13040
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\fast1$7[63:0]$13228 \ra
+ assign $2\fast1$7[63:0]$13040 \ra
case
- assign $2\fast1$7[63:0]$13228 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast1$7[63:0]$13040 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $1\fast1$7[63:0]$13227 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$7[63:0]$13039 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast1$7 $0\fast1$7[63:0]$13226
+ update \fast1$7 $0\fast1$7[63:0]$13038
end
- attribute \src "libresoc.v:191134.3-191152.6"
- process $proc$libresoc.v:191134$13229
+ attribute \src "libresoc.v:190078.3-190096.6"
+ process $proc$libresoc.v:190078$13041
assign { } { }
assign { } { }
assign $0\spr1_ok[0:0] $1\spr1_ok[0:0]
- attribute \src "libresoc.v:191135.5-191135.29"
+ attribute \src "libresoc.v:190079.5-190079.29"
switch \initial
- attribute \src "libresoc.v:191135.9-191135.17"
+ attribute \src "libresoc.v:190079.9-190079.17"
case 1'1
case
end
sync always
update \spr1_ok $0\spr1_ok[0:0]
end
- attribute \src "libresoc.v:191153.3-191198.6"
- process $proc$libresoc.v:191153$13230
+ attribute \src "libresoc.v:190097.3-190142.6"
+ process $proc$libresoc.v:190097$13042
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:191154.5-191154.29"
+ attribute \src "libresoc.v:190098.5-190098.29"
switch \initial
- attribute \src "libresoc.v:191154.9-191154.17"
+ attribute \src "libresoc.v:190098.9-190098.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:191199.3-191214.6"
- process $proc$libresoc.v:191199$13231
+ attribute \src "libresoc.v:190143.3-190158.6"
+ process $proc$libresoc.v:190143$13043
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:191200.5-191200.29"
+ attribute \src "libresoc.v:190144.5-190144.29"
switch \initial
- attribute \src "libresoc.v:191200.9-191200.17"
+ attribute \src "libresoc.v:190144.9-190144.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:191215.3-191235.6"
- process $proc$libresoc.v:191215$13232
+ attribute \src "libresoc.v:190159.3-190179.6"
+ process $proc$libresoc.v:190159$13044
assign { } { }
assign { } { }
- assign $0\xer_so$8[0:0]$13233 $1\xer_so$8[0:0]$13234
- attribute \src "libresoc.v:191216.5-191216.29"
+ assign $0\xer_so$8[0:0]$13045 $1\xer_so$8[0:0]$13046
+ attribute \src "libresoc.v:190160.5-190160.29"
switch \initial
- attribute \src "libresoc.v:191216.9-191216.17"
+ attribute \src "libresoc.v:190160.9-190160.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_so$8[0:0]$13234 $2\xer_so$8[0:0]$13235
+ assign $1\xer_so$8[0:0]$13046 $2\xer_so$8[0:0]$13047
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_so$8[0:0]$13235 $3\xer_so$8[0:0]$13236
+ assign $2\xer_so$8[0:0]$13047 $3\xer_so$8[0:0]$13048
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$11
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_so$8[0:0]$13236 \ra [31]
+ assign $3\xer_so$8[0:0]$13048 \ra [31]
case
- assign $3\xer_so$8[0:0]$13236 1'0
+ assign $3\xer_so$8[0:0]$13048 1'0
end
case
- assign $2\xer_so$8[0:0]$13235 1'0
+ assign $2\xer_so$8[0:0]$13047 1'0
end
case
- assign $1\xer_so$8[0:0]$13234 1'0
+ assign $1\xer_so$8[0:0]$13046 1'0
end
sync always
- update \xer_so$8 $0\xer_so$8[0:0]$13233
+ update \xer_so$8 $0\xer_so$8[0:0]$13045
end
- attribute \src "libresoc.v:191236.3-191256.6"
- process $proc$libresoc.v:191236$13237
+ attribute \src "libresoc.v:190180.3-190200.6"
+ process $proc$libresoc.v:190180$13049
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:191237.5-191237.29"
+ attribute \src "libresoc.v:190181.5-190181.29"
switch \initial
- attribute \src "libresoc.v:191237.9-191237.17"
+ attribute \src "libresoc.v:190181.9-190181.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:191257.3-191280.6"
- process $proc$libresoc.v:191257$13238
+ attribute \src "libresoc.v:190201.3-190224.6"
+ process $proc$libresoc.v:190201$13050
assign { } { }
assign { } { }
- assign $0\xer_ov$9[1:0]$13239 $1\xer_ov$9[1:0]$13240
- attribute \src "libresoc.v:191258.5-191258.29"
+ assign $0\xer_ov$9[1:0]$13051 $1\xer_ov$9[1:0]$13052
+ attribute \src "libresoc.v:190202.5-190202.29"
switch \initial
- attribute \src "libresoc.v:191258.9-191258.17"
+ attribute \src "libresoc.v:190202.9-190202.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ov$9[1:0]$13240 $2\xer_ov$9[1:0]$13241
+ assign $1\xer_ov$9[1:0]$13052 $2\xer_ov$9[1:0]$13053
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ov$9[1:0]$13241 $3\xer_ov$9[1:0]$13242
+ assign $2\xer_ov$9[1:0]$13053 $3\xer_ov$9[1:0]$13054
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$15
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ov$9[1:0]$13242 [0] \ra [30]
- assign $3\xer_ov$9[1:0]$13242 [1] \ra [19]
+ assign $3\xer_ov$9[1:0]$13054 [0] \ra [30]
+ assign $3\xer_ov$9[1:0]$13054 [1] \ra [19]
case
- assign $3\xer_ov$9[1:0]$13242 2'00
+ assign $3\xer_ov$9[1:0]$13054 2'00
end
case
- assign $2\xer_ov$9[1:0]$13241 2'00
+ assign $2\xer_ov$9[1:0]$13053 2'00
end
case
- assign $1\xer_ov$9[1:0]$13240 2'00
+ assign $1\xer_ov$9[1:0]$13052 2'00
end
sync always
- update \xer_ov$9 $0\xer_ov$9[1:0]$13239
+ update \xer_ov$9 $0\xer_ov$9[1:0]$13051
end
- attribute \src "libresoc.v:191281.3-191301.6"
- process $proc$libresoc.v:191281$13243
+ attribute \src "libresoc.v:190225.3-190245.6"
+ process $proc$libresoc.v:190225$13055
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:191282.5-191282.29"
+ attribute \src "libresoc.v:190226.5-190226.29"
switch \initial
- attribute \src "libresoc.v:191282.9-191282.17"
+ attribute \src "libresoc.v:190226.9-190226.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:191302.3-191325.6"
- process $proc$libresoc.v:191302$13244
+ attribute \src "libresoc.v:190246.3-190269.6"
+ process $proc$libresoc.v:190246$13056
assign { } { }
assign { } { }
- assign $0\xer_ca$10[1:0]$13245 $1\xer_ca$10[1:0]$13246
- attribute \src "libresoc.v:191303.5-191303.29"
+ assign $0\xer_ca$10[1:0]$13057 $1\xer_ca$10[1:0]$13058
+ attribute \src "libresoc.v:190247.5-190247.29"
switch \initial
- attribute \src "libresoc.v:191303.9-191303.17"
+ attribute \src "libresoc.v:190247.9-190247.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ca$10[1:0]$13246 $2\xer_ca$10[1:0]$13247
+ assign $1\xer_ca$10[1:0]$13058 $2\xer_ca$10[1:0]$13059
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ca$10[1:0]$13247 $3\xer_ca$10[1:0]$13248
+ assign $2\xer_ca$10[1:0]$13059 $3\xer_ca$10[1:0]$13060
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ca$10[1:0]$13248 [0] \ra [29]
- assign $3\xer_ca$10[1:0]$13248 [1] \ra [18]
+ assign $3\xer_ca$10[1:0]$13060 [0] \ra [29]
+ assign $3\xer_ca$10[1:0]$13060 [1] \ra [18]
case
- assign $3\xer_ca$10[1:0]$13248 2'00
+ assign $3\xer_ca$10[1:0]$13060 2'00
end
case
- assign $2\xer_ca$10[1:0]$13247 2'00
+ assign $2\xer_ca$10[1:0]$13059 2'00
end
case
- assign $1\xer_ca$10[1:0]$13246 2'00
+ assign $1\xer_ca$10[1:0]$13058 2'00
end
sync always
- update \xer_ca$10 $0\xer_ca$10[1:0]$13245
+ update \xer_ca$10 $0\xer_ca$10[1:0]$13057
end
- attribute \src "libresoc.v:191326.3-191346.6"
- process $proc$libresoc.v:191326$13249
+ attribute \src "libresoc.v:190270.3-190290.6"
+ process $proc$libresoc.v:190270$13061
assign { } { }
assign { } { }
assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:191327.5-191327.29"
+ attribute \src "libresoc.v:190271.5-190271.29"
switch \initial
- attribute \src "libresoc.v:191327.9-191327.17"
+ attribute \src "libresoc.v:190271.9-190271.17"
case 1'1
case
end
sync always
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:191347.3-191365.6"
- process $proc$libresoc.v:191347$13250
+ attribute \src "libresoc.v:190291.3-190309.6"
+ process $proc$libresoc.v:190291$13062
assign { } { }
assign { } { }
- assign $0\spr1$6[63:0]$13251 $1\spr1$6[63:0]$13252
- attribute \src "libresoc.v:191348.5-191348.29"
+ assign $0\spr1$6[63:0]$13063 $1\spr1$6[63:0]$13064
+ attribute \src "libresoc.v:190292.5-190292.29"
switch \initial
- attribute \src "libresoc.v:191348.9-191348.17"
+ attribute \src "libresoc.v:190292.9-190292.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\spr1$6[63:0]$13252 $2\spr1$6[63:0]$13253
+ assign $1\spr1$6[63:0]$13064 $2\spr1$6[63:0]$13065
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
- assign $2\spr1$6[63:0]$13253 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\spr1$6[63:0]$13065 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\spr1$6[63:0]$13253 \ra
+ assign $2\spr1$6[63:0]$13065 \ra
end
case
- assign $1\spr1$6[63:0]$13252 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\spr1$6[63:0]$13064 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \spr1$6 $0\spr1$6[63:0]$13251
+ update \spr1$6 $0\spr1$6[63:0]$13063
end
- connect \$11 $eq$libresoc.v:191111$13218_Y
- connect \$13 $eq$libresoc.v:191112$13219_Y
- connect \$15 $eq$libresoc.v:191113$13220_Y
- connect \$17 $eq$libresoc.v:191114$13221_Y
- connect \$19 $eq$libresoc.v:191115$13222_Y
- connect \$21 $eq$libresoc.v:191116$13223_Y
- connect \$23 $eq$libresoc.v:191117$13224_Y
+ connect \$11 $eq$libresoc.v:190055$13030_Y
+ connect \$13 $eq$libresoc.v:190056$13031_Y
+ connect \$15 $eq$libresoc.v:190057$13032_Y
+ connect \$17 $eq$libresoc.v:190058$13033_Y
+ connect \$19 $eq$libresoc.v:190059$13034_Y
+ connect \$21 $eq$libresoc.v:190060$13035_Y
+ connect \$23 $eq$libresoc.v:190061$13036_Y
connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
connect \muxid$1 \muxid
connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] }
end
-attribute \src "libresoc.v:191373.1-192839.10"
+attribute \src "libresoc.v:190317.1-191783.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
attribute \generator "nMigen"
module \sprmap
- attribute \src "libresoc.v:191503.3-191824.6"
+ attribute \src "libresoc.v:190447.3-190768.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:191825.3-192146.6"
+ attribute \src "libresoc.v:190769.3-191090.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:191374.7-191374.20"
+ attribute \src "libresoc.v:190318.7-190318.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:192147.3-192492.6"
+ attribute \src "libresoc.v:191091.3-191436.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:192493.3-192838.6"
+ attribute \src "libresoc.v:191437.3-191782.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:191503.3-191824.6"
+ attribute \src "libresoc.v:190447.3-190768.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:191825.3-192146.6"
+ attribute \src "libresoc.v:190769.3-191090.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:192147.3-192492.6"
+ attribute \src "libresoc.v:191091.3-191436.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:192493.3-192838.6"
+ attribute \src "libresoc.v:191437.3-191782.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:191374.7-191374.15"
+ attribute \src "libresoc.v:190318.7-190318.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:191374.7-191374.20"
- process $proc$libresoc.v:191374$13259
+ attribute \src "libresoc.v:190318.7-190318.20"
+ process $proc$libresoc.v:190318$13071
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:191503.3-191824.6"
- process $proc$libresoc.v:191503$13255
+ attribute \src "libresoc.v:190447.3-190768.6"
+ process $proc$libresoc.v:190447$13067
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:191504.5-191504.29"
+ attribute \src "libresoc.v:190448.5-190448.29"
switch \initial
- attribute \src "libresoc.v:191504.9-191504.17"
+ attribute \src "libresoc.v:190448.9-190448.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:191825.3-192146.6"
- process $proc$libresoc.v:191825$13256
+ attribute \src "libresoc.v:190769.3-191090.6"
+ process $proc$libresoc.v:190769$13068
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:191826.5-191826.29"
+ attribute \src "libresoc.v:190770.5-190770.29"
switch \initial
- attribute \src "libresoc.v:191826.9-191826.17"
+ attribute \src "libresoc.v:190770.9-190770.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:192147.3-192492.6"
- process $proc$libresoc.v:192147$13257
+ attribute \src "libresoc.v:191091.3-191436.6"
+ process $proc$libresoc.v:191091$13069
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:192148.5-192148.29"
+ attribute \src "libresoc.v:191092.5-191092.29"
switch \initial
- attribute \src "libresoc.v:192148.9-192148.17"
+ attribute \src "libresoc.v:191092.9-191092.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:192493.3-192838.6"
- process $proc$libresoc.v:192493$13258
+ attribute \src "libresoc.v:191437.3-191782.6"
+ process $proc$libresoc.v:191437$13070
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:192494.5-192494.29"
+ attribute \src "libresoc.v:191438.5-191438.29"
switch \initial
- attribute \src "libresoc.v:192494.9-192494.17"
+ attribute \src "libresoc.v:191438.9-191438.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:192843.1-194309.10"
+attribute \src "libresoc.v:191787.1-193253.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
attribute \generator "nMigen"
module \sprmap$174
- attribute \src "libresoc.v:192973.3-193294.6"
+ attribute \src "libresoc.v:191917.3-192238.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:193295.3-193616.6"
+ attribute \src "libresoc.v:192239.3-192560.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:192844.7-192844.20"
+ attribute \src "libresoc.v:191788.7-191788.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193617.3-193962.6"
+ attribute \src "libresoc.v:192561.3-192906.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:193963.3-194308.6"
+ attribute \src "libresoc.v:192907.3-193252.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:192973.3-193294.6"
+ attribute \src "libresoc.v:191917.3-192238.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:193295.3-193616.6"
+ attribute \src "libresoc.v:192239.3-192560.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:193617.3-193962.6"
+ attribute \src "libresoc.v:192561.3-192906.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:193963.3-194308.6"
+ attribute \src "libresoc.v:192907.3-193252.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:192844.7-192844.15"
+ attribute \src "libresoc.v:191788.7-191788.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:192844.7-192844.20"
- process $proc$libresoc.v:192844$13264
+ attribute \src "libresoc.v:191788.7-191788.20"
+ process $proc$libresoc.v:191788$13076
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:192973.3-193294.6"
- process $proc$libresoc.v:192973$13260
+ attribute \src "libresoc.v:191917.3-192238.6"
+ process $proc$libresoc.v:191917$13072
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:192974.5-192974.29"
+ attribute \src "libresoc.v:191918.5-191918.29"
switch \initial
- attribute \src "libresoc.v:192974.9-192974.17"
+ attribute \src "libresoc.v:191918.9-191918.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:193295.3-193616.6"
- process $proc$libresoc.v:193295$13261
+ attribute \src "libresoc.v:192239.3-192560.6"
+ process $proc$libresoc.v:192239$13073
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:193296.5-193296.29"
+ attribute \src "libresoc.v:192240.5-192240.29"
switch \initial
- attribute \src "libresoc.v:193296.9-193296.17"
+ attribute \src "libresoc.v:192240.9-192240.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:193617.3-193962.6"
- process $proc$libresoc.v:193617$13262
+ attribute \src "libresoc.v:192561.3-192906.6"
+ process $proc$libresoc.v:192561$13074
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:193618.5-193618.29"
+ attribute \src "libresoc.v:192562.5-192562.29"
switch \initial
- attribute \src "libresoc.v:193618.9-193618.17"
+ attribute \src "libresoc.v:192562.9-192562.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:193963.3-194308.6"
- process $proc$libresoc.v:193963$13263
+ attribute \src "libresoc.v:192907.3-193252.6"
+ process $proc$libresoc.v:192907$13075
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:193964.5-193964.29"
+ attribute \src "libresoc.v:192908.5-192908.29"
switch \initial
- attribute \src "libresoc.v:193964.9-193964.17"
+ attribute \src "libresoc.v:192908.9-192908.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:194313.1-194371.10"
+attribute \src "libresoc.v:193257.1-193315.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l"
attribute \generator "nMigen"
module \src_l
- attribute \src "libresoc.v:194314.7-194314.20"
+ attribute \src "libresoc.v:193258.7-193258.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194359.3-194367.6"
- wire width 4 $0\q_int$next[3:0]$13275
- attribute \src "libresoc.v:194357.3-194358.27"
+ attribute \src "libresoc.v:193303.3-193311.6"
+ wire width 4 $0\q_int$next[3:0]$13087
+ attribute \src "libresoc.v:193301.3-193302.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:194359.3-194367.6"
- wire width 4 $1\q_int$next[3:0]$13276
- attribute \src "libresoc.v:194336.13-194336.25"
+ attribute \src "libresoc.v:193303.3-193311.6"
+ wire width 4 $1\q_int$next[3:0]$13088
+ attribute \src "libresoc.v:193280.13-193280.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:194349.17-194349.96"
- wire width 4 $and$libresoc.v:194349$13265_Y
- attribute \src "libresoc.v:194354.17-194354.96"
- wire width 4 $and$libresoc.v:194354$13270_Y
- attribute \src "libresoc.v:194351.18-194351.93"
- wire width 4 $not$libresoc.v:194351$13267_Y
- attribute \src "libresoc.v:194353.17-194353.92"
- wire width 4 $not$libresoc.v:194353$13269_Y
- attribute \src "libresoc.v:194356.17-194356.92"
- wire width 4 $not$libresoc.v:194356$13272_Y
- attribute \src "libresoc.v:194350.18-194350.98"
- wire width 4 $or$libresoc.v:194350$13266_Y
- attribute \src "libresoc.v:194352.18-194352.99"
- wire width 4 $or$libresoc.v:194352$13268_Y
- attribute \src "libresoc.v:194355.17-194355.97"
- wire width 4 $or$libresoc.v:194355$13271_Y
+ attribute \src "libresoc.v:193293.17-193293.96"
+ wire width 4 $and$libresoc.v:193293$13077_Y
+ attribute \src "libresoc.v:193298.17-193298.96"
+ wire width 4 $and$libresoc.v:193298$13082_Y
+ attribute \src "libresoc.v:193295.18-193295.93"
+ wire width 4 $not$libresoc.v:193295$13079_Y
+ attribute \src "libresoc.v:193297.17-193297.92"
+ wire width 4 $not$libresoc.v:193297$13081_Y
+ attribute \src "libresoc.v:193300.17-193300.92"
+ wire width 4 $not$libresoc.v:193300$13084_Y
+ attribute \src "libresoc.v:193294.18-193294.98"
+ wire width 4 $or$libresoc.v:193294$13078_Y
+ attribute \src "libresoc.v:193296.18-193296.99"
+ wire width 4 $or$libresoc.v:193296$13080_Y
+ attribute \src "libresoc.v:193299.17-193299.97"
+ wire width 4 $or$libresoc.v:193299$13083_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194314.7-194314.15"
+ attribute \src "libresoc.v:193258.7-193258.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194349$13265
+ cell $and $and$libresoc.v:193293$13077
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194349$13265_Y
+ connect \Y $and$libresoc.v:193293$13077_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194354$13270
+ cell $and $and$libresoc.v:193298$13082
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194354$13270_Y
+ connect \Y $and$libresoc.v:193298$13082_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194351$13267
+ cell $not $not$libresoc.v:193295$13079
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:194351$13267_Y
+ connect \Y $not$libresoc.v:193295$13079_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194353$13269
+ cell $not $not$libresoc.v:193297$13081
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:194353$13269_Y
+ connect \Y $not$libresoc.v:193297$13081_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194356$13272
+ cell $not $not$libresoc.v:193300$13084
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:194356$13272_Y
+ connect \Y $not$libresoc.v:193300$13084_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194350$13266
+ cell $or $or$libresoc.v:193294$13078
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194350$13266_Y
+ connect \Y $or$libresoc.v:193294$13078_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194352$13268
+ cell $or $or$libresoc.v:193296$13080
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194352$13268_Y
+ connect \Y $or$libresoc.v:193296$13080_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194355$13271
+ cell $or $or$libresoc.v:193299$13083
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194355$13271_Y
+ connect \Y $or$libresoc.v:193299$13083_Y
end
- attribute \src "libresoc.v:194314.7-194314.20"
- process $proc$libresoc.v:194314$13277
+ attribute \src "libresoc.v:193258.7-193258.20"
+ process $proc$libresoc.v:193258$13089
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194336.13-194336.25"
- process $proc$libresoc.v:194336$13278
+ attribute \src "libresoc.v:193280.13-193280.25"
+ process $proc$libresoc.v:193280$13090
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:194357.3-194358.27"
- process $proc$libresoc.v:194357$13273
+ attribute \src "libresoc.v:193301.3-193302.27"
+ process $proc$libresoc.v:193301$13085
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:194359.3-194367.6"
- process $proc$libresoc.v:194359$13274
+ attribute \src "libresoc.v:193303.3-193311.6"
+ process $proc$libresoc.v:193303$13086
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13275 $1\q_int$next[3:0]$13276
- attribute \src "libresoc.v:194360.5-194360.29"
+ assign $0\q_int$next[3:0]$13087 $1\q_int$next[3:0]$13088
+ attribute \src "libresoc.v:193304.5-193304.29"
switch \initial
- attribute \src "libresoc.v:194360.9-194360.17"
+ attribute \src "libresoc.v:193304.9-193304.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13276 4'0000
+ assign $1\q_int$next[3:0]$13088 4'0000
case
- assign $1\q_int$next[3:0]$13276 \$5
+ assign $1\q_int$next[3:0]$13088 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13275
+ update \q_int$next $0\q_int$next[3:0]$13087
end
- connect \$9 $and$libresoc.v:194349$13265_Y
- connect \$11 $or$libresoc.v:194350$13266_Y
- connect \$13 $not$libresoc.v:194351$13267_Y
- connect \$15 $or$libresoc.v:194352$13268_Y
- connect \$1 $not$libresoc.v:194353$13269_Y
- connect \$3 $and$libresoc.v:194354$13270_Y
- connect \$5 $or$libresoc.v:194355$13271_Y
- connect \$7 $not$libresoc.v:194356$13272_Y
+ connect \$9 $and$libresoc.v:193293$13077_Y
+ connect \$11 $or$libresoc.v:193294$13078_Y
+ connect \$13 $not$libresoc.v:193295$13079_Y
+ connect \$15 $or$libresoc.v:193296$13080_Y
+ connect \$1 $not$libresoc.v:193297$13081_Y
+ connect \$3 $and$libresoc.v:193298$13082_Y
+ connect \$5 $or$libresoc.v:193299$13083_Y
+ connect \$7 $not$libresoc.v:193300$13084_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194375.1-194433.10"
+attribute \src "libresoc.v:193319.1-193377.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l"
attribute \generator "nMigen"
module \src_l$10
- attribute \src "libresoc.v:194376.7-194376.20"
+ attribute \src "libresoc.v:193320.7-193320.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194421.3-194429.6"
- wire width 6 $0\q_int$next[5:0]$13289
- attribute \src "libresoc.v:194419.3-194420.27"
+ attribute \src "libresoc.v:193365.3-193373.6"
+ wire width 6 $0\q_int$next[5:0]$13101
+ attribute \src "libresoc.v:193363.3-193364.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:194421.3-194429.6"
- wire width 6 $1\q_int$next[5:0]$13290
- attribute \src "libresoc.v:194398.13-194398.26"
+ attribute \src "libresoc.v:193365.3-193373.6"
+ wire width 6 $1\q_int$next[5:0]$13102
+ attribute \src "libresoc.v:193342.13-193342.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:194411.17-194411.96"
- wire width 6 $and$libresoc.v:194411$13279_Y
- attribute \src "libresoc.v:194416.17-194416.96"
- wire width 6 $and$libresoc.v:194416$13284_Y
- attribute \src "libresoc.v:194413.18-194413.93"
- wire width 6 $not$libresoc.v:194413$13281_Y
- attribute \src "libresoc.v:194415.17-194415.92"
- wire width 6 $not$libresoc.v:194415$13283_Y
- attribute \src "libresoc.v:194418.17-194418.92"
- wire width 6 $not$libresoc.v:194418$13286_Y
- attribute \src "libresoc.v:194412.18-194412.98"
- wire width 6 $or$libresoc.v:194412$13280_Y
- attribute \src "libresoc.v:194414.18-194414.99"
- wire width 6 $or$libresoc.v:194414$13282_Y
- attribute \src "libresoc.v:194417.17-194417.97"
- wire width 6 $or$libresoc.v:194417$13285_Y
+ attribute \src "libresoc.v:193355.17-193355.96"
+ wire width 6 $and$libresoc.v:193355$13091_Y
+ attribute \src "libresoc.v:193360.17-193360.96"
+ wire width 6 $and$libresoc.v:193360$13096_Y
+ attribute \src "libresoc.v:193357.18-193357.93"
+ wire width 6 $not$libresoc.v:193357$13093_Y
+ attribute \src "libresoc.v:193359.17-193359.92"
+ wire width 6 $not$libresoc.v:193359$13095_Y
+ attribute \src "libresoc.v:193362.17-193362.92"
+ wire width 6 $not$libresoc.v:193362$13098_Y
+ attribute \src "libresoc.v:193356.18-193356.98"
+ wire width 6 $or$libresoc.v:193356$13092_Y
+ attribute \src "libresoc.v:193358.18-193358.99"
+ wire width 6 $or$libresoc.v:193358$13094_Y
+ attribute \src "libresoc.v:193361.17-193361.97"
+ wire width 6 $or$libresoc.v:193361$13097_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194376.7-194376.15"
+ attribute \src "libresoc.v:193320.7-193320.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194411$13279
+ cell $and $and$libresoc.v:193355$13091
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194411$13279_Y
+ connect \Y $and$libresoc.v:193355$13091_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194416$13284
+ cell $and $and$libresoc.v:193360$13096
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194416$13284_Y
+ connect \Y $and$libresoc.v:193360$13096_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194413$13281
+ cell $not $not$libresoc.v:193357$13093
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:194413$13281_Y
+ connect \Y $not$libresoc.v:193357$13093_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194415$13283
+ cell $not $not$libresoc.v:193359$13095
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:194415$13283_Y
+ connect \Y $not$libresoc.v:193359$13095_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194418$13286
+ cell $not $not$libresoc.v:193362$13098
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:194418$13286_Y
+ connect \Y $not$libresoc.v:193362$13098_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194412$13280
+ cell $or $or$libresoc.v:193356$13092
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194412$13280_Y
+ connect \Y $or$libresoc.v:193356$13092_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194414$13282
+ cell $or $or$libresoc.v:193358$13094
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194414$13282_Y
+ connect \Y $or$libresoc.v:193358$13094_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194417$13285
+ cell $or $or$libresoc.v:193361$13097
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194417$13285_Y
+ connect \Y $or$libresoc.v:193361$13097_Y
end
- attribute \src "libresoc.v:194376.7-194376.20"
- process $proc$libresoc.v:194376$13291
+ attribute \src "libresoc.v:193320.7-193320.20"
+ process $proc$libresoc.v:193320$13103
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194398.13-194398.26"
- process $proc$libresoc.v:194398$13292
+ attribute \src "libresoc.v:193342.13-193342.26"
+ process $proc$libresoc.v:193342$13104
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:194419.3-194420.27"
- process $proc$libresoc.v:194419$13287
+ attribute \src "libresoc.v:193363.3-193364.27"
+ process $proc$libresoc.v:193363$13099
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:194421.3-194429.6"
- process $proc$libresoc.v:194421$13288
+ attribute \src "libresoc.v:193365.3-193373.6"
+ process $proc$libresoc.v:193365$13100
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13289 $1\q_int$next[5:0]$13290
- attribute \src "libresoc.v:194422.5-194422.29"
+ assign $0\q_int$next[5:0]$13101 $1\q_int$next[5:0]$13102
+ attribute \src "libresoc.v:193366.5-193366.29"
switch \initial
- attribute \src "libresoc.v:194422.9-194422.17"
+ attribute \src "libresoc.v:193366.9-193366.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13290 6'000000
+ assign $1\q_int$next[5:0]$13102 6'000000
case
- assign $1\q_int$next[5:0]$13290 \$5
+ assign $1\q_int$next[5:0]$13102 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13289
+ update \q_int$next $0\q_int$next[5:0]$13101
end
- connect \$9 $and$libresoc.v:194411$13279_Y
- connect \$11 $or$libresoc.v:194412$13280_Y
- connect \$13 $not$libresoc.v:194413$13281_Y
- connect \$15 $or$libresoc.v:194414$13282_Y
- connect \$1 $not$libresoc.v:194415$13283_Y
- connect \$3 $and$libresoc.v:194416$13284_Y
- connect \$5 $or$libresoc.v:194417$13285_Y
- connect \$7 $not$libresoc.v:194418$13286_Y
+ connect \$9 $and$libresoc.v:193355$13091_Y
+ connect \$11 $or$libresoc.v:193356$13092_Y
+ connect \$13 $not$libresoc.v:193357$13093_Y
+ connect \$15 $or$libresoc.v:193358$13094_Y
+ connect \$1 $not$libresoc.v:193359$13095_Y
+ connect \$3 $and$libresoc.v:193360$13096_Y
+ connect \$5 $or$libresoc.v:193361$13097_Y
+ connect \$7 $not$libresoc.v:193362$13098_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194437.1-194495.10"
+attribute \src "libresoc.v:193381.1-193439.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l"
attribute \generator "nMigen"
module \src_l$101
- attribute \src "libresoc.v:194438.7-194438.20"
+ attribute \src "libresoc.v:193382.7-193382.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194483.3-194491.6"
- wire width 3 $0\q_int$next[2:0]$13303
- attribute \src "libresoc.v:194481.3-194482.27"
+ attribute \src "libresoc.v:193427.3-193435.6"
+ wire width 3 $0\q_int$next[2:0]$13115
+ attribute \src "libresoc.v:193425.3-193426.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:194483.3-194491.6"
- wire width 3 $1\q_int$next[2:0]$13304
- attribute \src "libresoc.v:194460.13-194460.25"
+ attribute \src "libresoc.v:193427.3-193435.6"
+ wire width 3 $1\q_int$next[2:0]$13116
+ attribute \src "libresoc.v:193404.13-193404.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:194473.17-194473.96"
- wire width 3 $and$libresoc.v:194473$13293_Y
- attribute \src "libresoc.v:194478.17-194478.96"
- wire width 3 $and$libresoc.v:194478$13298_Y
- attribute \src "libresoc.v:194475.18-194475.93"
- wire width 3 $not$libresoc.v:194475$13295_Y
- attribute \src "libresoc.v:194477.17-194477.92"
- wire width 3 $not$libresoc.v:194477$13297_Y
- attribute \src "libresoc.v:194480.17-194480.92"
- wire width 3 $not$libresoc.v:194480$13300_Y
- attribute \src "libresoc.v:194474.18-194474.98"
- wire width 3 $or$libresoc.v:194474$13294_Y
- attribute \src "libresoc.v:194476.18-194476.99"
- wire width 3 $or$libresoc.v:194476$13296_Y
- attribute \src "libresoc.v:194479.17-194479.97"
- wire width 3 $or$libresoc.v:194479$13299_Y
+ attribute \src "libresoc.v:193417.17-193417.96"
+ wire width 3 $and$libresoc.v:193417$13105_Y
+ attribute \src "libresoc.v:193422.17-193422.96"
+ wire width 3 $and$libresoc.v:193422$13110_Y
+ attribute \src "libresoc.v:193419.18-193419.93"
+ wire width 3 $not$libresoc.v:193419$13107_Y
+ attribute \src "libresoc.v:193421.17-193421.92"
+ wire width 3 $not$libresoc.v:193421$13109_Y
+ attribute \src "libresoc.v:193424.17-193424.92"
+ wire width 3 $not$libresoc.v:193424$13112_Y
+ attribute \src "libresoc.v:193418.18-193418.98"
+ wire width 3 $or$libresoc.v:193418$13106_Y
+ attribute \src "libresoc.v:193420.18-193420.99"
+ wire width 3 $or$libresoc.v:193420$13108_Y
+ attribute \src "libresoc.v:193423.17-193423.97"
+ wire width 3 $or$libresoc.v:193423$13111_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194438.7-194438.15"
+ attribute \src "libresoc.v:193382.7-193382.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194473$13293
+ cell $and $and$libresoc.v:193417$13105
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194473$13293_Y
+ connect \Y $and$libresoc.v:193417$13105_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194478$13298
+ cell $and $and$libresoc.v:193422$13110
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194478$13298_Y
+ connect \Y $and$libresoc.v:193422$13110_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194475$13295
+ cell $not $not$libresoc.v:193419$13107
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:194475$13295_Y
+ connect \Y $not$libresoc.v:193419$13107_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194477$13297
+ cell $not $not$libresoc.v:193421$13109
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194477$13297_Y
+ connect \Y $not$libresoc.v:193421$13109_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194480$13300
+ cell $not $not$libresoc.v:193424$13112
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194480$13300_Y
+ connect \Y $not$libresoc.v:193424$13112_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194474$13294
+ cell $or $or$libresoc.v:193418$13106
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194474$13294_Y
+ connect \Y $or$libresoc.v:193418$13106_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194476$13296
+ cell $or $or$libresoc.v:193420$13108
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194476$13296_Y
+ connect \Y $or$libresoc.v:193420$13108_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194479$13299
+ cell $or $or$libresoc.v:193423$13111
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194479$13299_Y
+ connect \Y $or$libresoc.v:193423$13111_Y
end
- attribute \src "libresoc.v:194438.7-194438.20"
- process $proc$libresoc.v:194438$13305
+ attribute \src "libresoc.v:193382.7-193382.20"
+ process $proc$libresoc.v:193382$13117
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194460.13-194460.25"
- process $proc$libresoc.v:194460$13306
+ attribute \src "libresoc.v:193404.13-193404.25"
+ process $proc$libresoc.v:193404$13118
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:194481.3-194482.27"
- process $proc$libresoc.v:194481$13301
+ attribute \src "libresoc.v:193425.3-193426.27"
+ process $proc$libresoc.v:193425$13113
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:194483.3-194491.6"
- process $proc$libresoc.v:194483$13302
+ attribute \src "libresoc.v:193427.3-193435.6"
+ process $proc$libresoc.v:193427$13114
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13303 $1\q_int$next[2:0]$13304
- attribute \src "libresoc.v:194484.5-194484.29"
+ assign $0\q_int$next[2:0]$13115 $1\q_int$next[2:0]$13116
+ attribute \src "libresoc.v:193428.5-193428.29"
switch \initial
- attribute \src "libresoc.v:194484.9-194484.17"
+ attribute \src "libresoc.v:193428.9-193428.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13304 3'000
+ assign $1\q_int$next[2:0]$13116 3'000
case
- assign $1\q_int$next[2:0]$13304 \$5
+ assign $1\q_int$next[2:0]$13116 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13303
+ update \q_int$next $0\q_int$next[2:0]$13115
end
- connect \$9 $and$libresoc.v:194473$13293_Y
- connect \$11 $or$libresoc.v:194474$13294_Y
- connect \$13 $not$libresoc.v:194475$13295_Y
- connect \$15 $or$libresoc.v:194476$13296_Y
- connect \$1 $not$libresoc.v:194477$13297_Y
- connect \$3 $and$libresoc.v:194478$13298_Y
- connect \$5 $or$libresoc.v:194479$13299_Y
- connect \$7 $not$libresoc.v:194480$13300_Y
+ connect \$9 $and$libresoc.v:193417$13105_Y
+ connect \$11 $or$libresoc.v:193418$13106_Y
+ connect \$13 $not$libresoc.v:193419$13107_Y
+ connect \$15 $or$libresoc.v:193420$13108_Y
+ connect \$1 $not$libresoc.v:193421$13109_Y
+ connect \$3 $and$libresoc.v:193422$13110_Y
+ connect \$5 $or$libresoc.v:193423$13111_Y
+ connect \$7 $not$libresoc.v:193424$13112_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194499.1-194557.10"
+attribute \src "libresoc.v:193443.1-193501.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l"
attribute \generator "nMigen"
module \src_l$119
- attribute \src "libresoc.v:194500.7-194500.20"
+ attribute \src "libresoc.v:193444.7-193444.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194545.3-194553.6"
- wire width 5 $0\q_int$next[4:0]$13317
- attribute \src "libresoc.v:194543.3-194544.27"
+ attribute \src "libresoc.v:193489.3-193497.6"
+ wire width 5 $0\q_int$next[4:0]$13129
+ attribute \src "libresoc.v:193487.3-193488.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:194545.3-194553.6"
- wire width 5 $1\q_int$next[4:0]$13318
- attribute \src "libresoc.v:194522.13-194522.26"
+ attribute \src "libresoc.v:193489.3-193497.6"
+ wire width 5 $1\q_int$next[4:0]$13130
+ attribute \src "libresoc.v:193466.13-193466.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:194535.17-194535.96"
- wire width 5 $and$libresoc.v:194535$13307_Y
- attribute \src "libresoc.v:194540.17-194540.96"
- wire width 5 $and$libresoc.v:194540$13312_Y
- attribute \src "libresoc.v:194537.18-194537.93"
- wire width 5 $not$libresoc.v:194537$13309_Y
- attribute \src "libresoc.v:194539.17-194539.92"
- wire width 5 $not$libresoc.v:194539$13311_Y
- attribute \src "libresoc.v:194542.17-194542.92"
- wire width 5 $not$libresoc.v:194542$13314_Y
- attribute \src "libresoc.v:194536.18-194536.98"
- wire width 5 $or$libresoc.v:194536$13308_Y
- attribute \src "libresoc.v:194538.18-194538.99"
- wire width 5 $or$libresoc.v:194538$13310_Y
- attribute \src "libresoc.v:194541.17-194541.97"
- wire width 5 $or$libresoc.v:194541$13313_Y
+ attribute \src "libresoc.v:193479.17-193479.96"
+ wire width 5 $and$libresoc.v:193479$13119_Y
+ attribute \src "libresoc.v:193484.17-193484.96"
+ wire width 5 $and$libresoc.v:193484$13124_Y
+ attribute \src "libresoc.v:193481.18-193481.93"
+ wire width 5 $not$libresoc.v:193481$13121_Y
+ attribute \src "libresoc.v:193483.17-193483.92"
+ wire width 5 $not$libresoc.v:193483$13123_Y
+ attribute \src "libresoc.v:193486.17-193486.92"
+ wire width 5 $not$libresoc.v:193486$13126_Y
+ attribute \src "libresoc.v:193480.18-193480.98"
+ wire width 5 $or$libresoc.v:193480$13120_Y
+ attribute \src "libresoc.v:193482.18-193482.99"
+ wire width 5 $or$libresoc.v:193482$13122_Y
+ attribute \src "libresoc.v:193485.17-193485.97"
+ wire width 5 $or$libresoc.v:193485$13125_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194500.7-194500.15"
+ attribute \src "libresoc.v:193444.7-193444.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194535$13307
+ cell $and $and$libresoc.v:193479$13119
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194535$13307_Y
+ connect \Y $and$libresoc.v:193479$13119_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194540$13312
+ cell $and $and$libresoc.v:193484$13124
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194540$13312_Y
+ connect \Y $and$libresoc.v:193484$13124_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194537$13309
+ cell $not $not$libresoc.v:193481$13121
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_src
- connect \Y $not$libresoc.v:194537$13309_Y
+ connect \Y $not$libresoc.v:193481$13121_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194539$13311
+ cell $not $not$libresoc.v:193483$13123
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:194539$13311_Y
+ connect \Y $not$libresoc.v:193483$13123_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194542$13314
+ cell $not $not$libresoc.v:193486$13126
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:194542$13314_Y
+ connect \Y $not$libresoc.v:193486$13126_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194536$13308
+ cell $or $or$libresoc.v:193480$13120
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194536$13308_Y
+ connect \Y $or$libresoc.v:193480$13120_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194538$13310
+ cell $or $or$libresoc.v:193482$13122
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194538$13310_Y
+ connect \Y $or$libresoc.v:193482$13122_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194541$13313
+ cell $or $or$libresoc.v:193485$13125
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194541$13313_Y
+ connect \Y $or$libresoc.v:193485$13125_Y
end
- attribute \src "libresoc.v:194500.7-194500.20"
- process $proc$libresoc.v:194500$13319
+ attribute \src "libresoc.v:193444.7-193444.20"
+ process $proc$libresoc.v:193444$13131
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194522.13-194522.26"
- process $proc$libresoc.v:194522$13320
+ attribute \src "libresoc.v:193466.13-193466.26"
+ process $proc$libresoc.v:193466$13132
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:194543.3-194544.27"
- process $proc$libresoc.v:194543$13315
+ attribute \src "libresoc.v:193487.3-193488.27"
+ process $proc$libresoc.v:193487$13127
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:194545.3-194553.6"
- process $proc$libresoc.v:194545$13316
+ attribute \src "libresoc.v:193489.3-193497.6"
+ process $proc$libresoc.v:193489$13128
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$13317 $1\q_int$next[4:0]$13318
- attribute \src "libresoc.v:194546.5-194546.29"
+ assign $0\q_int$next[4:0]$13129 $1\q_int$next[4:0]$13130
+ attribute \src "libresoc.v:193490.5-193490.29"
switch \initial
- attribute \src "libresoc.v:194546.9-194546.17"
+ attribute \src "libresoc.v:193490.9-193490.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$13318 5'00000
+ assign $1\q_int$next[4:0]$13130 5'00000
case
- assign $1\q_int$next[4:0]$13318 \$5
+ assign $1\q_int$next[4:0]$13130 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$13317
+ update \q_int$next $0\q_int$next[4:0]$13129
end
- connect \$9 $and$libresoc.v:194535$13307_Y
- connect \$11 $or$libresoc.v:194536$13308_Y
- connect \$13 $not$libresoc.v:194537$13309_Y
- connect \$15 $or$libresoc.v:194538$13310_Y
- connect \$1 $not$libresoc.v:194539$13311_Y
- connect \$3 $and$libresoc.v:194540$13312_Y
- connect \$5 $or$libresoc.v:194541$13313_Y
- connect \$7 $not$libresoc.v:194542$13314_Y
+ connect \$9 $and$libresoc.v:193479$13119_Y
+ connect \$11 $or$libresoc.v:193480$13120_Y
+ connect \$13 $not$libresoc.v:193481$13121_Y
+ connect \$15 $or$libresoc.v:193482$13122_Y
+ connect \$1 $not$libresoc.v:193483$13123_Y
+ connect \$3 $and$libresoc.v:193484$13124_Y
+ connect \$5 $or$libresoc.v:193485$13125_Y
+ connect \$7 $not$libresoc.v:193486$13126_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194561.1-194619.10"
+attribute \src "libresoc.v:193505.1-193563.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l"
attribute \generator "nMigen"
module \src_l$127
- attribute \src "libresoc.v:194562.7-194562.20"
+ attribute \src "libresoc.v:193506.7-193506.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194607.3-194615.6"
- wire width 3 $0\q_int$next[2:0]$13331
- attribute \src "libresoc.v:194605.3-194606.27"
+ attribute \src "libresoc.v:193551.3-193559.6"
+ wire width 3 $0\q_int$next[2:0]$13143
+ attribute \src "libresoc.v:193549.3-193550.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:194607.3-194615.6"
- wire width 3 $1\q_int$next[2:0]$13332
- attribute \src "libresoc.v:194584.13-194584.25"
+ attribute \src "libresoc.v:193551.3-193559.6"
+ wire width 3 $1\q_int$next[2:0]$13144
+ attribute \src "libresoc.v:193528.13-193528.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:194597.17-194597.96"
- wire width 3 $and$libresoc.v:194597$13321_Y
- attribute \src "libresoc.v:194602.17-194602.96"
- wire width 3 $and$libresoc.v:194602$13326_Y
- attribute \src "libresoc.v:194599.18-194599.93"
- wire width 3 $not$libresoc.v:194599$13323_Y
- attribute \src "libresoc.v:194601.17-194601.92"
- wire width 3 $not$libresoc.v:194601$13325_Y
- attribute \src "libresoc.v:194604.17-194604.92"
- wire width 3 $not$libresoc.v:194604$13328_Y
- attribute \src "libresoc.v:194598.18-194598.98"
- wire width 3 $or$libresoc.v:194598$13322_Y
- attribute \src "libresoc.v:194600.18-194600.99"
- wire width 3 $or$libresoc.v:194600$13324_Y
- attribute \src "libresoc.v:194603.17-194603.97"
- wire width 3 $or$libresoc.v:194603$13327_Y
+ attribute \src "libresoc.v:193541.17-193541.96"
+ wire width 3 $and$libresoc.v:193541$13133_Y
+ attribute \src "libresoc.v:193546.17-193546.96"
+ wire width 3 $and$libresoc.v:193546$13138_Y
+ attribute \src "libresoc.v:193543.18-193543.93"
+ wire width 3 $not$libresoc.v:193543$13135_Y
+ attribute \src "libresoc.v:193545.17-193545.92"
+ wire width 3 $not$libresoc.v:193545$13137_Y
+ attribute \src "libresoc.v:193548.17-193548.92"
+ wire width 3 $not$libresoc.v:193548$13140_Y
+ attribute \src "libresoc.v:193542.18-193542.98"
+ wire width 3 $or$libresoc.v:193542$13134_Y
+ attribute \src "libresoc.v:193544.18-193544.99"
+ wire width 3 $or$libresoc.v:193544$13136_Y
+ attribute \src "libresoc.v:193547.17-193547.97"
+ wire width 3 $or$libresoc.v:193547$13139_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194562.7-194562.15"
+ attribute \src "libresoc.v:193506.7-193506.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194597$13321
+ cell $and $and$libresoc.v:193541$13133
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194597$13321_Y
+ connect \Y $and$libresoc.v:193541$13133_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194602$13326
+ cell $and $and$libresoc.v:193546$13138
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194602$13326_Y
+ connect \Y $and$libresoc.v:193546$13138_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194599$13323
+ cell $not $not$libresoc.v:193543$13135
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:194599$13323_Y
+ connect \Y $not$libresoc.v:193543$13135_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194601$13325
+ cell $not $not$libresoc.v:193545$13137
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194601$13325_Y
+ connect \Y $not$libresoc.v:193545$13137_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194604$13328
+ cell $not $not$libresoc.v:193548$13140
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194604$13328_Y
+ connect \Y $not$libresoc.v:193548$13140_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194598$13322
+ cell $or $or$libresoc.v:193542$13134
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194598$13322_Y
+ connect \Y $or$libresoc.v:193542$13134_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194600$13324
+ cell $or $or$libresoc.v:193544$13136
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194600$13324_Y
+ connect \Y $or$libresoc.v:193544$13136_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194603$13327
+ cell $or $or$libresoc.v:193547$13139
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194603$13327_Y
+ connect \Y $or$libresoc.v:193547$13139_Y
end
- attribute \src "libresoc.v:194562.7-194562.20"
- process $proc$libresoc.v:194562$13333
+ attribute \src "libresoc.v:193506.7-193506.20"
+ process $proc$libresoc.v:193506$13145
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194584.13-194584.25"
- process $proc$libresoc.v:194584$13334
+ attribute \src "libresoc.v:193528.13-193528.25"
+ process $proc$libresoc.v:193528$13146
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:194605.3-194606.27"
- process $proc$libresoc.v:194605$13329
+ attribute \src "libresoc.v:193549.3-193550.27"
+ process $proc$libresoc.v:193549$13141
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:194607.3-194615.6"
- process $proc$libresoc.v:194607$13330
+ attribute \src "libresoc.v:193551.3-193559.6"
+ process $proc$libresoc.v:193551$13142
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13331 $1\q_int$next[2:0]$13332
- attribute \src "libresoc.v:194608.5-194608.29"
+ assign $0\q_int$next[2:0]$13143 $1\q_int$next[2:0]$13144
+ attribute \src "libresoc.v:193552.5-193552.29"
switch \initial
- attribute \src "libresoc.v:194608.9-194608.17"
+ attribute \src "libresoc.v:193552.9-193552.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13332 3'000
+ assign $1\q_int$next[2:0]$13144 3'000
case
- assign $1\q_int$next[2:0]$13332 \$5
+ assign $1\q_int$next[2:0]$13144 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13331
+ update \q_int$next $0\q_int$next[2:0]$13143
end
- connect \$9 $and$libresoc.v:194597$13321_Y
- connect \$11 $or$libresoc.v:194598$13322_Y
- connect \$13 $not$libresoc.v:194599$13323_Y
- connect \$15 $or$libresoc.v:194600$13324_Y
- connect \$1 $not$libresoc.v:194601$13325_Y
- connect \$3 $and$libresoc.v:194602$13326_Y
- connect \$5 $or$libresoc.v:194603$13327_Y
- connect \$7 $not$libresoc.v:194604$13328_Y
+ connect \$9 $and$libresoc.v:193541$13133_Y
+ connect \$11 $or$libresoc.v:193542$13134_Y
+ connect \$13 $not$libresoc.v:193543$13135_Y
+ connect \$15 $or$libresoc.v:193544$13136_Y
+ connect \$1 $not$libresoc.v:193545$13137_Y
+ connect \$3 $and$libresoc.v:193546$13138_Y
+ connect \$5 $or$libresoc.v:193547$13139_Y
+ connect \$7 $not$libresoc.v:193548$13140_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194623.1-194681.10"
+attribute \src "libresoc.v:193567.1-193625.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l"
attribute \generator "nMigen"
module \src_l$23
- attribute \src "libresoc.v:194624.7-194624.20"
+ attribute \src "libresoc.v:193568.7-193568.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194669.3-194677.6"
- wire width 3 $0\q_int$next[2:0]$13345
- attribute \src "libresoc.v:194667.3-194668.27"
+ attribute \src "libresoc.v:193613.3-193621.6"
+ wire width 3 $0\q_int$next[2:0]$13157
+ attribute \src "libresoc.v:193611.3-193612.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:194669.3-194677.6"
- wire width 3 $1\q_int$next[2:0]$13346
- attribute \src "libresoc.v:194646.13-194646.25"
+ attribute \src "libresoc.v:193613.3-193621.6"
+ wire width 3 $1\q_int$next[2:0]$13158
+ attribute \src "libresoc.v:193590.13-193590.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:194659.17-194659.96"
- wire width 3 $and$libresoc.v:194659$13335_Y
- attribute \src "libresoc.v:194664.17-194664.96"
- wire width 3 $and$libresoc.v:194664$13340_Y
- attribute \src "libresoc.v:194661.18-194661.93"
- wire width 3 $not$libresoc.v:194661$13337_Y
- attribute \src "libresoc.v:194663.17-194663.92"
- wire width 3 $not$libresoc.v:194663$13339_Y
- attribute \src "libresoc.v:194666.17-194666.92"
- wire width 3 $not$libresoc.v:194666$13342_Y
- attribute \src "libresoc.v:194660.18-194660.98"
- wire width 3 $or$libresoc.v:194660$13336_Y
- attribute \src "libresoc.v:194662.18-194662.99"
- wire width 3 $or$libresoc.v:194662$13338_Y
- attribute \src "libresoc.v:194665.17-194665.97"
- wire width 3 $or$libresoc.v:194665$13341_Y
+ attribute \src "libresoc.v:193603.17-193603.96"
+ wire width 3 $and$libresoc.v:193603$13147_Y
+ attribute \src "libresoc.v:193608.17-193608.96"
+ wire width 3 $and$libresoc.v:193608$13152_Y
+ attribute \src "libresoc.v:193605.18-193605.93"
+ wire width 3 $not$libresoc.v:193605$13149_Y
+ attribute \src "libresoc.v:193607.17-193607.92"
+ wire width 3 $not$libresoc.v:193607$13151_Y
+ attribute \src "libresoc.v:193610.17-193610.92"
+ wire width 3 $not$libresoc.v:193610$13154_Y
+ attribute \src "libresoc.v:193604.18-193604.98"
+ wire width 3 $or$libresoc.v:193604$13148_Y
+ attribute \src "libresoc.v:193606.18-193606.99"
+ wire width 3 $or$libresoc.v:193606$13150_Y
+ attribute \src "libresoc.v:193609.17-193609.97"
+ wire width 3 $or$libresoc.v:193609$13153_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194624.7-194624.15"
+ attribute \src "libresoc.v:193568.7-193568.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194659$13335
+ cell $and $and$libresoc.v:193603$13147
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194659$13335_Y
+ connect \Y $and$libresoc.v:193603$13147_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194664$13340
+ cell $and $and$libresoc.v:193608$13152
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194664$13340_Y
+ connect \Y $and$libresoc.v:193608$13152_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194661$13337
+ cell $not $not$libresoc.v:193605$13149
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:194661$13337_Y
+ connect \Y $not$libresoc.v:193605$13149_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194663$13339
+ cell $not $not$libresoc.v:193607$13151
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194663$13339_Y
+ connect \Y $not$libresoc.v:193607$13151_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194666$13342
+ cell $not $not$libresoc.v:193610$13154
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194666$13342_Y
+ connect \Y $not$libresoc.v:193610$13154_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194660$13336
+ cell $or $or$libresoc.v:193604$13148
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194660$13336_Y
+ connect \Y $or$libresoc.v:193604$13148_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194662$13338
+ cell $or $or$libresoc.v:193606$13150
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194662$13338_Y
+ connect \Y $or$libresoc.v:193606$13150_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194665$13341
+ cell $or $or$libresoc.v:193609$13153
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194665$13341_Y
+ connect \Y $or$libresoc.v:193609$13153_Y
end
- attribute \src "libresoc.v:194624.7-194624.20"
- process $proc$libresoc.v:194624$13347
+ attribute \src "libresoc.v:193568.7-193568.20"
+ process $proc$libresoc.v:193568$13159
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194646.13-194646.25"
- process $proc$libresoc.v:194646$13348
+ attribute \src "libresoc.v:193590.13-193590.25"
+ process $proc$libresoc.v:193590$13160
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:194667.3-194668.27"
- process $proc$libresoc.v:194667$13343
+ attribute \src "libresoc.v:193611.3-193612.27"
+ process $proc$libresoc.v:193611$13155
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:194669.3-194677.6"
- process $proc$libresoc.v:194669$13344
+ attribute \src "libresoc.v:193613.3-193621.6"
+ process $proc$libresoc.v:193613$13156
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13345 $1\q_int$next[2:0]$13346
- attribute \src "libresoc.v:194670.5-194670.29"
+ assign $0\q_int$next[2:0]$13157 $1\q_int$next[2:0]$13158
+ attribute \src "libresoc.v:193614.5-193614.29"
switch \initial
- attribute \src "libresoc.v:194670.9-194670.17"
+ attribute \src "libresoc.v:193614.9-193614.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13346 3'000
+ assign $1\q_int$next[2:0]$13158 3'000
case
- assign $1\q_int$next[2:0]$13346 \$5
+ assign $1\q_int$next[2:0]$13158 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13345
+ update \q_int$next $0\q_int$next[2:0]$13157
end
- connect \$9 $and$libresoc.v:194659$13335_Y
- connect \$11 $or$libresoc.v:194660$13336_Y
- connect \$13 $not$libresoc.v:194661$13337_Y
- connect \$15 $or$libresoc.v:194662$13338_Y
- connect \$1 $not$libresoc.v:194663$13339_Y
- connect \$3 $and$libresoc.v:194664$13340_Y
- connect \$5 $or$libresoc.v:194665$13341_Y
- connect \$7 $not$libresoc.v:194666$13342_Y
+ connect \$9 $and$libresoc.v:193603$13147_Y
+ connect \$11 $or$libresoc.v:193604$13148_Y
+ connect \$13 $not$libresoc.v:193605$13149_Y
+ connect \$15 $or$libresoc.v:193606$13150_Y
+ connect \$1 $not$libresoc.v:193607$13151_Y
+ connect \$3 $and$libresoc.v:193608$13152_Y
+ connect \$5 $or$libresoc.v:193609$13153_Y
+ connect \$7 $not$libresoc.v:193610$13154_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194685.1-194743.10"
+attribute \src "libresoc.v:193629.1-193687.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l"
attribute \generator "nMigen"
module \src_l$39
- attribute \src "libresoc.v:194686.7-194686.20"
+ attribute \src "libresoc.v:193630.7-193630.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194731.3-194739.6"
- wire width 4 $0\q_int$next[3:0]$13359
- attribute \src "libresoc.v:194729.3-194730.27"
+ attribute \src "libresoc.v:193675.3-193683.6"
+ wire width 4 $0\q_int$next[3:0]$13171
+ attribute \src "libresoc.v:193673.3-193674.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:194731.3-194739.6"
- wire width 4 $1\q_int$next[3:0]$13360
- attribute \src "libresoc.v:194708.13-194708.25"
+ attribute \src "libresoc.v:193675.3-193683.6"
+ wire width 4 $1\q_int$next[3:0]$13172
+ attribute \src "libresoc.v:193652.13-193652.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:194721.17-194721.96"
- wire width 4 $and$libresoc.v:194721$13349_Y
- attribute \src "libresoc.v:194726.17-194726.96"
- wire width 4 $and$libresoc.v:194726$13354_Y
- attribute \src "libresoc.v:194723.18-194723.93"
- wire width 4 $not$libresoc.v:194723$13351_Y
- attribute \src "libresoc.v:194725.17-194725.92"
- wire width 4 $not$libresoc.v:194725$13353_Y
- attribute \src "libresoc.v:194728.17-194728.92"
- wire width 4 $not$libresoc.v:194728$13356_Y
- attribute \src "libresoc.v:194722.18-194722.98"
- wire width 4 $or$libresoc.v:194722$13350_Y
- attribute \src "libresoc.v:194724.18-194724.99"
- wire width 4 $or$libresoc.v:194724$13352_Y
- attribute \src "libresoc.v:194727.17-194727.97"
- wire width 4 $or$libresoc.v:194727$13355_Y
+ attribute \src "libresoc.v:193665.17-193665.96"
+ wire width 4 $and$libresoc.v:193665$13161_Y
+ attribute \src "libresoc.v:193670.17-193670.96"
+ wire width 4 $and$libresoc.v:193670$13166_Y
+ attribute \src "libresoc.v:193667.18-193667.93"
+ wire width 4 $not$libresoc.v:193667$13163_Y
+ attribute \src "libresoc.v:193669.17-193669.92"
+ wire width 4 $not$libresoc.v:193669$13165_Y
+ attribute \src "libresoc.v:193672.17-193672.92"
+ wire width 4 $not$libresoc.v:193672$13168_Y
+ attribute \src "libresoc.v:193666.18-193666.98"
+ wire width 4 $or$libresoc.v:193666$13162_Y
+ attribute \src "libresoc.v:193668.18-193668.99"
+ wire width 4 $or$libresoc.v:193668$13164_Y
+ attribute \src "libresoc.v:193671.17-193671.97"
+ wire width 4 $or$libresoc.v:193671$13167_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194686.7-194686.15"
+ attribute \src "libresoc.v:193630.7-193630.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194721$13349
+ cell $and $and$libresoc.v:193665$13161
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194721$13349_Y
+ connect \Y $and$libresoc.v:193665$13161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194726$13354
+ cell $and $and$libresoc.v:193670$13166
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194726$13354_Y
+ connect \Y $and$libresoc.v:193670$13166_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194723$13351
+ cell $not $not$libresoc.v:193667$13163
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:194723$13351_Y
+ connect \Y $not$libresoc.v:193667$13163_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194725$13353
+ cell $not $not$libresoc.v:193669$13165
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:194725$13353_Y
+ connect \Y $not$libresoc.v:193669$13165_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194728$13356
+ cell $not $not$libresoc.v:193672$13168
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:194728$13356_Y
+ connect \Y $not$libresoc.v:193672$13168_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194722$13350
+ cell $or $or$libresoc.v:193666$13162
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194722$13350_Y
+ connect \Y $or$libresoc.v:193666$13162_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194724$13352
+ cell $or $or$libresoc.v:193668$13164
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194724$13352_Y
+ connect \Y $or$libresoc.v:193668$13164_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194727$13355
+ cell $or $or$libresoc.v:193671$13167
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194727$13355_Y
+ connect \Y $or$libresoc.v:193671$13167_Y
end
- attribute \src "libresoc.v:194686.7-194686.20"
- process $proc$libresoc.v:194686$13361
+ attribute \src "libresoc.v:193630.7-193630.20"
+ process $proc$libresoc.v:193630$13173
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194708.13-194708.25"
- process $proc$libresoc.v:194708$13362
+ attribute \src "libresoc.v:193652.13-193652.25"
+ process $proc$libresoc.v:193652$13174
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:194729.3-194730.27"
- process $proc$libresoc.v:194729$13357
+ attribute \src "libresoc.v:193673.3-193674.27"
+ process $proc$libresoc.v:193673$13169
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:194731.3-194739.6"
- process $proc$libresoc.v:194731$13358
+ attribute \src "libresoc.v:193675.3-193683.6"
+ process $proc$libresoc.v:193675$13170
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13359 $1\q_int$next[3:0]$13360
- attribute \src "libresoc.v:194732.5-194732.29"
+ assign $0\q_int$next[3:0]$13171 $1\q_int$next[3:0]$13172
+ attribute \src "libresoc.v:193676.5-193676.29"
switch \initial
- attribute \src "libresoc.v:194732.9-194732.17"
+ attribute \src "libresoc.v:193676.9-193676.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13360 4'0000
+ assign $1\q_int$next[3:0]$13172 4'0000
case
- assign $1\q_int$next[3:0]$13360 \$5
+ assign $1\q_int$next[3:0]$13172 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13359
+ update \q_int$next $0\q_int$next[3:0]$13171
end
- connect \$9 $and$libresoc.v:194721$13349_Y
- connect \$11 $or$libresoc.v:194722$13350_Y
- connect \$13 $not$libresoc.v:194723$13351_Y
- connect \$15 $or$libresoc.v:194724$13352_Y
- connect \$1 $not$libresoc.v:194725$13353_Y
- connect \$3 $and$libresoc.v:194726$13354_Y
- connect \$5 $or$libresoc.v:194727$13355_Y
- connect \$7 $not$libresoc.v:194728$13356_Y
+ connect \$9 $and$libresoc.v:193665$13161_Y
+ connect \$11 $or$libresoc.v:193666$13162_Y
+ connect \$13 $not$libresoc.v:193667$13163_Y
+ connect \$15 $or$libresoc.v:193668$13164_Y
+ connect \$1 $not$libresoc.v:193669$13165_Y
+ connect \$3 $and$libresoc.v:193670$13166_Y
+ connect \$5 $or$libresoc.v:193671$13167_Y
+ connect \$7 $not$libresoc.v:193672$13168_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194747.1-194805.10"
+attribute \src "libresoc.v:193691.1-193749.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l"
attribute \generator "nMigen"
module \src_l$55
- attribute \src "libresoc.v:194748.7-194748.20"
+ attribute \src "libresoc.v:193692.7-193692.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194793.3-194801.6"
- wire width 3 $0\q_int$next[2:0]$13373
- attribute \src "libresoc.v:194791.3-194792.27"
+ attribute \src "libresoc.v:193737.3-193745.6"
+ wire width 3 $0\q_int$next[2:0]$13185
+ attribute \src "libresoc.v:193735.3-193736.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:194793.3-194801.6"
- wire width 3 $1\q_int$next[2:0]$13374
- attribute \src "libresoc.v:194770.13-194770.25"
+ attribute \src "libresoc.v:193737.3-193745.6"
+ wire width 3 $1\q_int$next[2:0]$13186
+ attribute \src "libresoc.v:193714.13-193714.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:194783.17-194783.96"
- wire width 3 $and$libresoc.v:194783$13363_Y
- attribute \src "libresoc.v:194788.17-194788.96"
- wire width 3 $and$libresoc.v:194788$13368_Y
- attribute \src "libresoc.v:194785.18-194785.93"
- wire width 3 $not$libresoc.v:194785$13365_Y
- attribute \src "libresoc.v:194787.17-194787.92"
- wire width 3 $not$libresoc.v:194787$13367_Y
- attribute \src "libresoc.v:194790.17-194790.92"
- wire width 3 $not$libresoc.v:194790$13370_Y
- attribute \src "libresoc.v:194784.18-194784.98"
- wire width 3 $or$libresoc.v:194784$13364_Y
- attribute \src "libresoc.v:194786.18-194786.99"
- wire width 3 $or$libresoc.v:194786$13366_Y
- attribute \src "libresoc.v:194789.17-194789.97"
- wire width 3 $or$libresoc.v:194789$13369_Y
+ attribute \src "libresoc.v:193727.17-193727.96"
+ wire width 3 $and$libresoc.v:193727$13175_Y
+ attribute \src "libresoc.v:193732.17-193732.96"
+ wire width 3 $and$libresoc.v:193732$13180_Y
+ attribute \src "libresoc.v:193729.18-193729.93"
+ wire width 3 $not$libresoc.v:193729$13177_Y
+ attribute \src "libresoc.v:193731.17-193731.92"
+ wire width 3 $not$libresoc.v:193731$13179_Y
+ attribute \src "libresoc.v:193734.17-193734.92"
+ wire width 3 $not$libresoc.v:193734$13182_Y
+ attribute \src "libresoc.v:193728.18-193728.98"
+ wire width 3 $or$libresoc.v:193728$13176_Y
+ attribute \src "libresoc.v:193730.18-193730.99"
+ wire width 3 $or$libresoc.v:193730$13178_Y
+ attribute \src "libresoc.v:193733.17-193733.97"
+ wire width 3 $or$libresoc.v:193733$13181_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194748.7-194748.15"
+ attribute \src "libresoc.v:193692.7-193692.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194783$13363
+ cell $and $and$libresoc.v:193727$13175
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194783$13363_Y
+ connect \Y $and$libresoc.v:193727$13175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194788$13368
+ cell $and $and$libresoc.v:193732$13180
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194788$13368_Y
+ connect \Y $and$libresoc.v:193732$13180_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194785$13365
+ cell $not $not$libresoc.v:193729$13177
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:194785$13365_Y
+ connect \Y $not$libresoc.v:193729$13177_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194787$13367
+ cell $not $not$libresoc.v:193731$13179
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194787$13367_Y
+ connect \Y $not$libresoc.v:193731$13179_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194790$13370
+ cell $not $not$libresoc.v:193734$13182
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194790$13370_Y
+ connect \Y $not$libresoc.v:193734$13182_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194784$13364
+ cell $or $or$libresoc.v:193728$13176
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194784$13364_Y
+ connect \Y $or$libresoc.v:193728$13176_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194786$13366
+ cell $or $or$libresoc.v:193730$13178
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194786$13366_Y
+ connect \Y $or$libresoc.v:193730$13178_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194789$13369
+ cell $or $or$libresoc.v:193733$13181
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194789$13369_Y
+ connect \Y $or$libresoc.v:193733$13181_Y
end
- attribute \src "libresoc.v:194748.7-194748.20"
- process $proc$libresoc.v:194748$13375
+ attribute \src "libresoc.v:193692.7-193692.20"
+ process $proc$libresoc.v:193692$13187
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194770.13-194770.25"
- process $proc$libresoc.v:194770$13376
+ attribute \src "libresoc.v:193714.13-193714.25"
+ process $proc$libresoc.v:193714$13188
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:194791.3-194792.27"
- process $proc$libresoc.v:194791$13371
+ attribute \src "libresoc.v:193735.3-193736.27"
+ process $proc$libresoc.v:193735$13183
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:194793.3-194801.6"
- process $proc$libresoc.v:194793$13372
+ attribute \src "libresoc.v:193737.3-193745.6"
+ process $proc$libresoc.v:193737$13184
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13373 $1\q_int$next[2:0]$13374
- attribute \src "libresoc.v:194794.5-194794.29"
+ assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186
+ attribute \src "libresoc.v:193738.5-193738.29"
switch \initial
- attribute \src "libresoc.v:194794.9-194794.17"
+ attribute \src "libresoc.v:193738.9-193738.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13374 3'000
+ assign $1\q_int$next[2:0]$13186 3'000
case
- assign $1\q_int$next[2:0]$13374 \$5
+ assign $1\q_int$next[2:0]$13186 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13373
+ update \q_int$next $0\q_int$next[2:0]$13185
end
- connect \$9 $and$libresoc.v:194783$13363_Y
- connect \$11 $or$libresoc.v:194784$13364_Y
- connect \$13 $not$libresoc.v:194785$13365_Y
- connect \$15 $or$libresoc.v:194786$13366_Y
- connect \$1 $not$libresoc.v:194787$13367_Y
- connect \$3 $and$libresoc.v:194788$13368_Y
- connect \$5 $or$libresoc.v:194789$13369_Y
- connect \$7 $not$libresoc.v:194790$13370_Y
+ connect \$9 $and$libresoc.v:193727$13175_Y
+ connect \$11 $or$libresoc.v:193728$13176_Y
+ connect \$13 $not$libresoc.v:193729$13177_Y
+ connect \$15 $or$libresoc.v:193730$13178_Y
+ connect \$1 $not$libresoc.v:193731$13179_Y
+ connect \$3 $and$libresoc.v:193732$13180_Y
+ connect \$5 $or$libresoc.v:193733$13181_Y
+ connect \$7 $not$libresoc.v:193734$13182_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194809.1-194867.10"
+attribute \src "libresoc.v:193753.1-193811.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l"
attribute \generator "nMigen"
module \src_l$67
- attribute \src "libresoc.v:194810.7-194810.20"
+ attribute \src "libresoc.v:193754.7-193754.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194855.3-194863.6"
- wire width 6 $0\q_int$next[5:0]$13387
- attribute \src "libresoc.v:194853.3-194854.27"
+ attribute \src "libresoc.v:193799.3-193807.6"
+ wire width 6 $0\q_int$next[5:0]$13199
+ attribute \src "libresoc.v:193797.3-193798.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:194855.3-194863.6"
- wire width 6 $1\q_int$next[5:0]$13388
- attribute \src "libresoc.v:194832.13-194832.26"
+ attribute \src "libresoc.v:193799.3-193807.6"
+ wire width 6 $1\q_int$next[5:0]$13200
+ attribute \src "libresoc.v:193776.13-193776.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:194845.17-194845.96"
- wire width 6 $and$libresoc.v:194845$13377_Y
- attribute \src "libresoc.v:194850.17-194850.96"
- wire width 6 $and$libresoc.v:194850$13382_Y
- attribute \src "libresoc.v:194847.18-194847.93"
- wire width 6 $not$libresoc.v:194847$13379_Y
- attribute \src "libresoc.v:194849.17-194849.92"
- wire width 6 $not$libresoc.v:194849$13381_Y
- attribute \src "libresoc.v:194852.17-194852.92"
- wire width 6 $not$libresoc.v:194852$13384_Y
- attribute \src "libresoc.v:194846.18-194846.98"
- wire width 6 $or$libresoc.v:194846$13378_Y
- attribute \src "libresoc.v:194848.18-194848.99"
- wire width 6 $or$libresoc.v:194848$13380_Y
- attribute \src "libresoc.v:194851.17-194851.97"
- wire width 6 $or$libresoc.v:194851$13383_Y
+ attribute \src "libresoc.v:193789.17-193789.96"
+ wire width 6 $and$libresoc.v:193789$13189_Y
+ attribute \src "libresoc.v:193794.17-193794.96"
+ wire width 6 $and$libresoc.v:193794$13194_Y
+ attribute \src "libresoc.v:193791.18-193791.93"
+ wire width 6 $not$libresoc.v:193791$13191_Y
+ attribute \src "libresoc.v:193793.17-193793.92"
+ wire width 6 $not$libresoc.v:193793$13193_Y
+ attribute \src "libresoc.v:193796.17-193796.92"
+ wire width 6 $not$libresoc.v:193796$13196_Y
+ attribute \src "libresoc.v:193790.18-193790.98"
+ wire width 6 $or$libresoc.v:193790$13190_Y
+ attribute \src "libresoc.v:193792.18-193792.99"
+ wire width 6 $or$libresoc.v:193792$13192_Y
+ attribute \src "libresoc.v:193795.17-193795.97"
+ wire width 6 $or$libresoc.v:193795$13195_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194810.7-194810.15"
+ attribute \src "libresoc.v:193754.7-193754.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194845$13377
+ cell $and $and$libresoc.v:193789$13189
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194845$13377_Y
+ connect \Y $and$libresoc.v:193789$13189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194850$13382
+ cell $and $and$libresoc.v:193794$13194
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194850$13382_Y
+ connect \Y $and$libresoc.v:193794$13194_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194847$13379
+ cell $not $not$libresoc.v:193791$13191
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:194847$13379_Y
+ connect \Y $not$libresoc.v:193791$13191_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194849$13381
+ cell $not $not$libresoc.v:193793$13193
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:194849$13381_Y
+ connect \Y $not$libresoc.v:193793$13193_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194852$13384
+ cell $not $not$libresoc.v:193796$13196
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:194852$13384_Y
+ connect \Y $not$libresoc.v:193796$13196_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194846$13378
+ cell $or $or$libresoc.v:193790$13190
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194846$13378_Y
+ connect \Y $or$libresoc.v:193790$13190_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194848$13380
+ cell $or $or$libresoc.v:193792$13192
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194848$13380_Y
+ connect \Y $or$libresoc.v:193792$13192_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194851$13383
+ cell $or $or$libresoc.v:193795$13195
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194851$13383_Y
+ connect \Y $or$libresoc.v:193795$13195_Y
end
- attribute \src "libresoc.v:194810.7-194810.20"
- process $proc$libresoc.v:194810$13389
+ attribute \src "libresoc.v:193754.7-193754.20"
+ process $proc$libresoc.v:193754$13201
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194832.13-194832.26"
- process $proc$libresoc.v:194832$13390
+ attribute \src "libresoc.v:193776.13-193776.26"
+ process $proc$libresoc.v:193776$13202
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:194853.3-194854.27"
- process $proc$libresoc.v:194853$13385
+ attribute \src "libresoc.v:193797.3-193798.27"
+ process $proc$libresoc.v:193797$13197
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:194855.3-194863.6"
- process $proc$libresoc.v:194855$13386
+ attribute \src "libresoc.v:193799.3-193807.6"
+ process $proc$libresoc.v:193799$13198
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13387 $1\q_int$next[5:0]$13388
- attribute \src "libresoc.v:194856.5-194856.29"
+ assign $0\q_int$next[5:0]$13199 $1\q_int$next[5:0]$13200
+ attribute \src "libresoc.v:193800.5-193800.29"
switch \initial
- attribute \src "libresoc.v:194856.9-194856.17"
+ attribute \src "libresoc.v:193800.9-193800.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13388 6'000000
+ assign $1\q_int$next[5:0]$13200 6'000000
case
- assign $1\q_int$next[5:0]$13388 \$5
+ assign $1\q_int$next[5:0]$13200 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13387
+ update \q_int$next $0\q_int$next[5:0]$13199
end
- connect \$9 $and$libresoc.v:194845$13377_Y
- connect \$11 $or$libresoc.v:194846$13378_Y
- connect \$13 $not$libresoc.v:194847$13379_Y
- connect \$15 $or$libresoc.v:194848$13380_Y
- connect \$1 $not$libresoc.v:194849$13381_Y
- connect \$3 $and$libresoc.v:194850$13382_Y
- connect \$5 $or$libresoc.v:194851$13383_Y
- connect \$7 $not$libresoc.v:194852$13384_Y
+ connect \$9 $and$libresoc.v:193789$13189_Y
+ connect \$11 $or$libresoc.v:193790$13190_Y
+ connect \$13 $not$libresoc.v:193791$13191_Y
+ connect \$15 $or$libresoc.v:193792$13192_Y
+ connect \$1 $not$libresoc.v:193793$13193_Y
+ connect \$3 $and$libresoc.v:193794$13194_Y
+ connect \$5 $or$libresoc.v:193795$13195_Y
+ connect \$7 $not$libresoc.v:193796$13196_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194871.1-194929.10"
+attribute \src "libresoc.v:193815.1-193873.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l"
attribute \generator "nMigen"
module \src_l$84
- attribute \src "libresoc.v:194872.7-194872.20"
+ attribute \src "libresoc.v:193816.7-193816.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194917.3-194925.6"
- wire width 3 $0\q_int$next[2:0]$13401
- attribute \src "libresoc.v:194915.3-194916.27"
+ attribute \src "libresoc.v:193861.3-193869.6"
+ wire width 3 $0\q_int$next[2:0]$13213
+ attribute \src "libresoc.v:193859.3-193860.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:194917.3-194925.6"
- wire width 3 $1\q_int$next[2:0]$13402
- attribute \src "libresoc.v:194894.13-194894.25"
+ attribute \src "libresoc.v:193861.3-193869.6"
+ wire width 3 $1\q_int$next[2:0]$13214
+ attribute \src "libresoc.v:193838.13-193838.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:194907.17-194907.96"
- wire width 3 $and$libresoc.v:194907$13391_Y
- attribute \src "libresoc.v:194912.17-194912.96"
- wire width 3 $and$libresoc.v:194912$13396_Y
- attribute \src "libresoc.v:194909.18-194909.93"
- wire width 3 $not$libresoc.v:194909$13393_Y
- attribute \src "libresoc.v:194911.17-194911.92"
- wire width 3 $not$libresoc.v:194911$13395_Y
- attribute \src "libresoc.v:194914.17-194914.92"
- wire width 3 $not$libresoc.v:194914$13398_Y
- attribute \src "libresoc.v:194908.18-194908.98"
- wire width 3 $or$libresoc.v:194908$13392_Y
- attribute \src "libresoc.v:194910.18-194910.99"
- wire width 3 $or$libresoc.v:194910$13394_Y
- attribute \src "libresoc.v:194913.17-194913.97"
- wire width 3 $or$libresoc.v:194913$13397_Y
+ attribute \src "libresoc.v:193851.17-193851.96"
+ wire width 3 $and$libresoc.v:193851$13203_Y
+ attribute \src "libresoc.v:193856.17-193856.96"
+ wire width 3 $and$libresoc.v:193856$13208_Y
+ attribute \src "libresoc.v:193853.18-193853.93"
+ wire width 3 $not$libresoc.v:193853$13205_Y
+ attribute \src "libresoc.v:193855.17-193855.92"
+ wire width 3 $not$libresoc.v:193855$13207_Y
+ attribute \src "libresoc.v:193858.17-193858.92"
+ wire width 3 $not$libresoc.v:193858$13210_Y
+ attribute \src "libresoc.v:193852.18-193852.98"
+ wire width 3 $or$libresoc.v:193852$13204_Y
+ attribute \src "libresoc.v:193854.18-193854.99"
+ wire width 3 $or$libresoc.v:193854$13206_Y
+ attribute \src "libresoc.v:193857.17-193857.97"
+ wire width 3 $or$libresoc.v:193857$13209_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194872.7-194872.15"
+ attribute \src "libresoc.v:193816.7-193816.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194907$13391
+ cell $and $and$libresoc.v:193851$13203
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194907$13391_Y
+ connect \Y $and$libresoc.v:193851$13203_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194912$13396
+ cell $and $and$libresoc.v:193856$13208
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194912$13396_Y
+ connect \Y $and$libresoc.v:193856$13208_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194909$13393
+ cell $not $not$libresoc.v:193853$13205
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:194909$13393_Y
+ connect \Y $not$libresoc.v:193853$13205_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194911$13395
+ cell $not $not$libresoc.v:193855$13207
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194911$13395_Y
+ connect \Y $not$libresoc.v:193855$13207_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194914$13398
+ cell $not $not$libresoc.v:193858$13210
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:194914$13398_Y
+ connect \Y $not$libresoc.v:193858$13210_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194908$13392
+ cell $or $or$libresoc.v:193852$13204
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:194908$13392_Y
+ connect \Y $or$libresoc.v:193852$13204_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194910$13394
+ cell $or $or$libresoc.v:193854$13206
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:194910$13394_Y
+ connect \Y $or$libresoc.v:193854$13206_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194913$13397
+ cell $or $or$libresoc.v:193857$13209
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:194913$13397_Y
+ connect \Y $or$libresoc.v:193857$13209_Y
end
- attribute \src "libresoc.v:194872.7-194872.20"
- process $proc$libresoc.v:194872$13403
+ attribute \src "libresoc.v:193816.7-193816.20"
+ process $proc$libresoc.v:193816$13215
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194894.13-194894.25"
- process $proc$libresoc.v:194894$13404
+ attribute \src "libresoc.v:193838.13-193838.25"
+ process $proc$libresoc.v:193838$13216
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:194915.3-194916.27"
- process $proc$libresoc.v:194915$13399
+ attribute \src "libresoc.v:193859.3-193860.27"
+ process $proc$libresoc.v:193859$13211
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:194917.3-194925.6"
- process $proc$libresoc.v:194917$13400
+ attribute \src "libresoc.v:193861.3-193869.6"
+ process $proc$libresoc.v:193861$13212
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13401 $1\q_int$next[2:0]$13402
- attribute \src "libresoc.v:194918.5-194918.29"
+ assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214
+ attribute \src "libresoc.v:193862.5-193862.29"
switch \initial
- attribute \src "libresoc.v:194918.9-194918.17"
+ attribute \src "libresoc.v:193862.9-193862.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13402 3'000
+ assign $1\q_int$next[2:0]$13214 3'000
case
- assign $1\q_int$next[2:0]$13402 \$5
+ assign $1\q_int$next[2:0]$13214 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13401
+ update \q_int$next $0\q_int$next[2:0]$13213
end
- connect \$9 $and$libresoc.v:194907$13391_Y
- connect \$11 $or$libresoc.v:194908$13392_Y
- connect \$13 $not$libresoc.v:194909$13393_Y
- connect \$15 $or$libresoc.v:194910$13394_Y
- connect \$1 $not$libresoc.v:194911$13395_Y
- connect \$3 $and$libresoc.v:194912$13396_Y
- connect \$5 $or$libresoc.v:194913$13397_Y
- connect \$7 $not$libresoc.v:194914$13398_Y
+ connect \$9 $and$libresoc.v:193851$13203_Y
+ connect \$11 $or$libresoc.v:193852$13204_Y
+ connect \$13 $not$libresoc.v:193853$13205_Y
+ connect \$15 $or$libresoc.v:193854$13206_Y
+ connect \$1 $not$libresoc.v:193855$13207_Y
+ connect \$3 $and$libresoc.v:193856$13208_Y
+ connect \$5 $or$libresoc.v:193857$13209_Y
+ connect \$7 $not$libresoc.v:193858$13210_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:194933.1-194991.10"
+attribute \src "libresoc.v:193877.1-193935.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active"
attribute \generator "nMigen"
module \st_active
- attribute \src "libresoc.v:194934.7-194934.20"
+ attribute \src "libresoc.v:193878.7-193878.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194979.3-194987.6"
- wire $0\q_int$next[0:0]$13415
- attribute \src "libresoc.v:194977.3-194978.27"
+ attribute \src "libresoc.v:193923.3-193931.6"
+ wire $0\q_int$next[0:0]$13227
+ attribute \src "libresoc.v:193921.3-193922.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:194979.3-194987.6"
- wire $1\q_int$next[0:0]$13416
- attribute \src "libresoc.v:194956.7-194956.19"
+ attribute \src "libresoc.v:193923.3-193931.6"
+ wire $1\q_int$next[0:0]$13228
+ attribute \src "libresoc.v:193900.7-193900.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:194969.17-194969.96"
- wire $and$libresoc.v:194969$13405_Y
- attribute \src "libresoc.v:194974.17-194974.96"
- wire $and$libresoc.v:194974$13410_Y
- attribute \src "libresoc.v:194971.18-194971.99"
- wire $not$libresoc.v:194971$13407_Y
- attribute \src "libresoc.v:194973.17-194973.98"
- wire $not$libresoc.v:194973$13409_Y
- attribute \src "libresoc.v:194976.17-194976.98"
- wire $not$libresoc.v:194976$13412_Y
- attribute \src "libresoc.v:194970.18-194970.104"
- wire $or$libresoc.v:194970$13406_Y
- attribute \src "libresoc.v:194972.18-194972.105"
- wire $or$libresoc.v:194972$13408_Y
- attribute \src "libresoc.v:194975.17-194975.103"
- wire $or$libresoc.v:194975$13411_Y
+ attribute \src "libresoc.v:193913.17-193913.96"
+ wire $and$libresoc.v:193913$13217_Y
+ attribute \src "libresoc.v:193918.17-193918.96"
+ wire $and$libresoc.v:193918$13222_Y
+ attribute \src "libresoc.v:193915.18-193915.99"
+ wire $not$libresoc.v:193915$13219_Y
+ attribute \src "libresoc.v:193917.17-193917.98"
+ wire $not$libresoc.v:193917$13221_Y
+ attribute \src "libresoc.v:193920.17-193920.98"
+ wire $not$libresoc.v:193920$13224_Y
+ attribute \src "libresoc.v:193914.18-193914.104"
+ wire $or$libresoc.v:193914$13218_Y
+ attribute \src "libresoc.v:193916.18-193916.105"
+ wire $or$libresoc.v:193916$13220_Y
+ attribute \src "libresoc.v:193919.17-193919.103"
+ wire $or$libresoc.v:193919$13223_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194934.7-194934.15"
+ attribute \src "libresoc.v:193878.7-193878.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_st_active
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194969$13405
+ cell $and $and$libresoc.v:193913$13217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194969$13405_Y
+ connect \Y $and$libresoc.v:193913$13217_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194974$13410
+ cell $and $and$libresoc.v:193918$13222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194974$13410_Y
+ connect \Y $and$libresoc.v:193918$13222_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194971$13407
+ cell $not $not$libresoc.v:193915$13219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_active
- connect \Y $not$libresoc.v:194971$13407_Y
+ connect \Y $not$libresoc.v:193915$13219_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194973$13409
+ cell $not $not$libresoc.v:193917$13221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:194973$13409_Y
+ connect \Y $not$libresoc.v:193917$13221_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194976$13412
+ cell $not $not$libresoc.v:193920$13224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:194976$13412_Y
+ connect \Y $not$libresoc.v:193920$13224_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194970$13406
+ cell $or $or$libresoc.v:193914$13218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_active
- connect \Y $or$libresoc.v:194970$13406_Y
+ connect \Y $or$libresoc.v:193914$13218_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194972$13408
+ cell $or $or$libresoc.v:193916$13220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_active
connect \B \q_int
- connect \Y $or$libresoc.v:194972$13408_Y
+ connect \Y $or$libresoc.v:193916$13220_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194975$13411
+ cell $or $or$libresoc.v:193919$13223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_active
- connect \Y $or$libresoc.v:194975$13411_Y
+ connect \Y $or$libresoc.v:193919$13223_Y
end
- attribute \src "libresoc.v:194934.7-194934.20"
- process $proc$libresoc.v:194934$13417
+ attribute \src "libresoc.v:193878.7-193878.20"
+ process $proc$libresoc.v:193878$13229
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194956.7-194956.19"
- process $proc$libresoc.v:194956$13418
+ attribute \src "libresoc.v:193900.7-193900.19"
+ process $proc$libresoc.v:193900$13230
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:194977.3-194978.27"
- process $proc$libresoc.v:194977$13413
+ attribute \src "libresoc.v:193921.3-193922.27"
+ process $proc$libresoc.v:193921$13225
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:194979.3-194987.6"
- process $proc$libresoc.v:194979$13414
+ attribute \src "libresoc.v:193923.3-193931.6"
+ process $proc$libresoc.v:193923$13226
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13415 $1\q_int$next[0:0]$13416
- attribute \src "libresoc.v:194980.5-194980.29"
+ assign $0\q_int$next[0:0]$13227 $1\q_int$next[0:0]$13228
+ attribute \src "libresoc.v:193924.5-193924.29"
switch \initial
- attribute \src "libresoc.v:194980.9-194980.17"
+ attribute \src "libresoc.v:193924.9-193924.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13416 1'0
+ assign $1\q_int$next[0:0]$13228 1'0
case
- assign $1\q_int$next[0:0]$13416 \$5
+ assign $1\q_int$next[0:0]$13228 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13415
+ update \q_int$next $0\q_int$next[0:0]$13227
end
- connect \$9 $and$libresoc.v:194969$13405_Y
- connect \$11 $or$libresoc.v:194970$13406_Y
- connect \$13 $not$libresoc.v:194971$13407_Y
- connect \$15 $or$libresoc.v:194972$13408_Y
- connect \$1 $not$libresoc.v:194973$13409_Y
- connect \$3 $and$libresoc.v:194974$13410_Y
- connect \$5 $or$libresoc.v:194975$13411_Y
- connect \$7 $not$libresoc.v:194976$13412_Y
+ connect \$9 $and$libresoc.v:193913$13217_Y
+ connect \$11 $or$libresoc.v:193914$13218_Y
+ connect \$13 $not$libresoc.v:193915$13219_Y
+ connect \$15 $or$libresoc.v:193916$13220_Y
+ connect \$1 $not$libresoc.v:193917$13221_Y
+ connect \$3 $and$libresoc.v:193918$13222_Y
+ connect \$5 $or$libresoc.v:193919$13223_Y
+ connect \$7 $not$libresoc.v:193920$13224_Y
connect \qlq_st_active \$15
connect \qn_st_active \$13
connect \q_st_active \$11
end
-attribute \src "libresoc.v:194995.1-195053.10"
+attribute \src "libresoc.v:193939.1-193997.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done"
attribute \generator "nMigen"
module \st_done
- attribute \src "libresoc.v:194996.7-194996.20"
+ attribute \src "libresoc.v:193940.7-193940.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:195041.3-195049.6"
- wire $0\q_int$next[0:0]$13429
- attribute \src "libresoc.v:195039.3-195040.27"
+ attribute \src "libresoc.v:193985.3-193993.6"
+ wire $0\q_int$next[0:0]$13241
+ attribute \src "libresoc.v:193983.3-193984.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:195041.3-195049.6"
- wire $1\q_int$next[0:0]$13430
- attribute \src "libresoc.v:195018.7-195018.19"
+ attribute \src "libresoc.v:193985.3-193993.6"
+ wire $1\q_int$next[0:0]$13242
+ attribute \src "libresoc.v:193962.7-193962.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:195031.17-195031.96"
- wire $and$libresoc.v:195031$13419_Y
- attribute \src "libresoc.v:195036.17-195036.96"
- wire $and$libresoc.v:195036$13424_Y
- attribute \src "libresoc.v:195033.18-195033.97"
- wire $not$libresoc.v:195033$13421_Y
- attribute \src "libresoc.v:195035.17-195035.96"
- wire $not$libresoc.v:195035$13423_Y
- attribute \src "libresoc.v:195038.17-195038.96"
- wire $not$libresoc.v:195038$13426_Y
- attribute \src "libresoc.v:195032.18-195032.102"
- wire $or$libresoc.v:195032$13420_Y
- attribute \src "libresoc.v:195034.18-195034.103"
- wire $or$libresoc.v:195034$13422_Y
- attribute \src "libresoc.v:195037.17-195037.101"
- wire $or$libresoc.v:195037$13425_Y
+ attribute \src "libresoc.v:193975.17-193975.96"
+ wire $and$libresoc.v:193975$13231_Y
+ attribute \src "libresoc.v:193980.17-193980.96"
+ wire $and$libresoc.v:193980$13236_Y
+ attribute \src "libresoc.v:193977.18-193977.97"
+ wire $not$libresoc.v:193977$13233_Y
+ attribute \src "libresoc.v:193979.17-193979.96"
+ wire $not$libresoc.v:193979$13235_Y
+ attribute \src "libresoc.v:193982.17-193982.96"
+ wire $not$libresoc.v:193982$13238_Y
+ attribute \src "libresoc.v:193976.18-193976.102"
+ wire $or$libresoc.v:193976$13232_Y
+ attribute \src "libresoc.v:193978.18-193978.103"
+ wire $or$libresoc.v:193978$13234_Y
+ attribute \src "libresoc.v:193981.17-193981.101"
+ wire $or$libresoc.v:193981$13237_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194996.7-194996.15"
+ attribute \src "libresoc.v:193940.7-193940.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_st_done
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:195031$13419
+ cell $and $and$libresoc.v:193975$13231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:195031$13419_Y
+ connect \Y $and$libresoc.v:193975$13231_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:195036$13424
+ cell $and $and$libresoc.v:193980$13236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:195036$13424_Y
+ connect \Y $and$libresoc.v:193980$13236_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:195033$13421
+ cell $not $not$libresoc.v:193977$13233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_done
- connect \Y $not$libresoc.v:195033$13421_Y
+ connect \Y $not$libresoc.v:193977$13233_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:195035$13423
+ cell $not $not$libresoc.v:193979$13235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:195035$13423_Y
+ connect \Y $not$libresoc.v:193979$13235_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:195038$13426
+ cell $not $not$libresoc.v:193982$13238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:195038$13426_Y
+ connect \Y $not$libresoc.v:193982$13238_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:195032$13420
+ cell $or $or$libresoc.v:193976$13232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_done
- connect \Y $or$libresoc.v:195032$13420_Y
+ connect \Y $or$libresoc.v:193976$13232_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:195034$13422
+ cell $or $or$libresoc.v:193978$13234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_done
connect \B \q_int
- connect \Y $or$libresoc.v:195034$13422_Y
+ connect \Y $or$libresoc.v:193978$13234_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:195037$13425
+ cell $or $or$libresoc.v:193981$13237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_done
- connect \Y $or$libresoc.v:195037$13425_Y
+ connect \Y $or$libresoc.v:193981$13237_Y
end
- attribute \src "libresoc.v:194996.7-194996.20"
- process $proc$libresoc.v:194996$13431
+ attribute \src "libresoc.v:193940.7-193940.20"
+ process $proc$libresoc.v:193940$13243
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:195018.7-195018.19"
- process $proc$libresoc.v:195018$13432
+ attribute \src "libresoc.v:193962.7-193962.19"
+ process $proc$libresoc.v:193962$13244
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:195039.3-195040.27"
- process $proc$libresoc.v:195039$13427
+ attribute \src "libresoc.v:193983.3-193984.27"
+ process $proc$libresoc.v:193983$13239
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:195041.3-195049.6"
- process $proc$libresoc.v:195041$13428
+ attribute \src "libresoc.v:193985.3-193993.6"
+ process $proc$libresoc.v:193985$13240
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13429 $1\q_int$next[0:0]$13430
- attribute \src "libresoc.v:195042.5-195042.29"
+ assign $0\q_int$next[0:0]$13241 $1\q_int$next[0:0]$13242
+ attribute \src "libresoc.v:193986.5-193986.29"
switch \initial
- attribute \src "libresoc.v:195042.9-195042.17"
+ attribute \src "libresoc.v:193986.9-193986.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13430 1'0
+ assign $1\q_int$next[0:0]$13242 1'0
case
- assign $1\q_int$next[0:0]$13430 \$5
+ assign $1\q_int$next[0:0]$13242 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13429
+ update \q_int$next $0\q_int$next[0:0]$13241
end
- connect \$9 $and$libresoc.v:195031$13419_Y
- connect \$11 $or$libresoc.v:195032$13420_Y
- connect \$13 $not$libresoc.v:195033$13421_Y
- connect \$15 $or$libresoc.v:195034$13422_Y
- connect \$1 $not$libresoc.v:195035$13423_Y
- connect \$3 $and$libresoc.v:195036$13424_Y
- connect \$5 $or$libresoc.v:195037$13425_Y
- connect \$7 $not$libresoc.v:195038$13426_Y
+ connect \$9 $and$libresoc.v:193975$13231_Y
+ connect \$11 $or$libresoc.v:193976$13232_Y
+ connect \$13 $not$libresoc.v:193977$13233_Y
+ connect \$15 $or$libresoc.v:193978$13234_Y
+ connect \$1 $not$libresoc.v:193979$13235_Y
+ connect \$3 $and$libresoc.v:193980$13236_Y
+ connect \$5 $or$libresoc.v:193981$13237_Y
+ connect \$7 $not$libresoc.v:193982$13238_Y
connect \qlq_st_done \$15
connect \qn_st_done \$13
connect \q_st_done \$11
end
-attribute \src "libresoc.v:195057.1-195353.10"
+attribute \src "libresoc.v:194001.1-194297.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state"
attribute \generator "nMigen"
module \state
- attribute \src "libresoc.v:195305.3-195314.6"
+ attribute \src "libresoc.v:194249.3-194258.6"
wire width 64 $0\cia__data_o[63:0]
- attribute \src "libresoc.v:195058.7-195058.20"
+ attribute \src "libresoc.v:194002.7-194002.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:195324.3-195333.6"
+ attribute \src "libresoc.v:194268.3-194277.6"
wire width 64 $0\msr__data_o[63:0]
- attribute \src "libresoc.v:195315.3-195323.6"
- wire width 3 $0\ren_delay$12$next[2:0]$13456
- attribute \src "libresoc.v:195219.3-195220.43"
- wire width 3 $0\ren_delay$12[2:0]$13445
- attribute \src "libresoc.v:195186.13-195186.34"
- wire width 3 $0\ren_delay$12[2:0]$13462
- attribute \src "libresoc.v:195277.3-195285.6"
- wire width 3 $0\ren_delay$19$next[2:0]$13448
- attribute \src "libresoc.v:195217.3-195218.43"
- wire width 3 $0\ren_delay$19[2:0]$13443
- attribute \src "libresoc.v:195190.13-195190.34"
- wire width 3 $0\ren_delay$19[2:0]$13464
- attribute \src "libresoc.v:195296.3-195304.6"
- wire width 3 $0\ren_delay$next[2:0]$13452
- attribute \src "libresoc.v:195221.3-195222.35"
+ attribute \src "libresoc.v:194259.3-194267.6"
+ wire width 3 $0\ren_delay$12$next[2:0]$13268
+ attribute \src "libresoc.v:194163.3-194164.43"
+ wire width 3 $0\ren_delay$12[2:0]$13257
+ attribute \src "libresoc.v:194130.13-194130.34"
+ wire width 3 $0\ren_delay$12[2:0]$13274
+ attribute \src "libresoc.v:194221.3-194229.6"
+ wire width 3 $0\ren_delay$19$next[2:0]$13260
+ attribute \src "libresoc.v:194161.3-194162.43"
+ wire width 3 $0\ren_delay$19[2:0]$13255
+ attribute \src "libresoc.v:194134.13-194134.34"
+ wire width 3 $0\ren_delay$19[2:0]$13276
+ attribute \src "libresoc.v:194240.3-194248.6"
+ wire width 3 $0\ren_delay$next[2:0]$13264
+ attribute \src "libresoc.v:194165.3-194166.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:195286.3-195295.6"
+ attribute \src "libresoc.v:194230.3-194239.6"
wire width 64 $0\sv__data_o[63:0]
- attribute \src "libresoc.v:195305.3-195314.6"
+ attribute \src "libresoc.v:194249.3-194258.6"
wire width 64 $1\cia__data_o[63:0]
- attribute \src "libresoc.v:195324.3-195333.6"
+ attribute \src "libresoc.v:194268.3-194277.6"
wire width 64 $1\msr__data_o[63:0]
- attribute \src "libresoc.v:195315.3-195323.6"
- wire width 3 $1\ren_delay$12$next[2:0]$13457
- attribute \src "libresoc.v:195277.3-195285.6"
- wire width 3 $1\ren_delay$19$next[2:0]$13449
- attribute \src "libresoc.v:195296.3-195304.6"
- wire width 3 $1\ren_delay$next[2:0]$13453
- attribute \src "libresoc.v:195184.13-195184.29"
+ attribute \src "libresoc.v:194259.3-194267.6"
+ wire width 3 $1\ren_delay$12$next[2:0]$13269
+ attribute \src "libresoc.v:194221.3-194229.6"
+ wire width 3 $1\ren_delay$19$next[2:0]$13261
+ attribute \src "libresoc.v:194240.3-194248.6"
+ wire width 3 $1\ren_delay$next[2:0]$13265
+ attribute \src "libresoc.v:194128.13-194128.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:195286.3-195295.6"
+ attribute \src "libresoc.v:194230.3-194239.6"
wire width 64 $1\sv__data_o[63:0]
- attribute \src "libresoc.v:195208.18-195208.109"
- wire width 64 $or$libresoc.v:195208$13433_Y
- attribute \src "libresoc.v:195210.18-195210.124"
- wire width 64 $or$libresoc.v:195210$13435_Y
- attribute \src "libresoc.v:195211.18-195211.110"
- wire width 64 $or$libresoc.v:195211$13436_Y
- attribute \src "libresoc.v:195213.18-195213.122"
- wire width 64 $or$libresoc.v:195213$13438_Y
- attribute \src "libresoc.v:195214.18-195214.109"
- wire width 64 $or$libresoc.v:195214$13439_Y
- attribute \src "libresoc.v:195216.17-195216.123"
- wire width 64 $or$libresoc.v:195216$13441_Y
- attribute \src "libresoc.v:195209.18-195209.100"
- wire $reduce_or$libresoc.v:195209$13434_Y
- attribute \src "libresoc.v:195212.18-195212.100"
- wire $reduce_or$libresoc.v:195212$13437_Y
- attribute \src "libresoc.v:195215.17-195215.95"
- wire $reduce_or$libresoc.v:195215$13440_Y
+ attribute \src "libresoc.v:194152.18-194152.109"
+ wire width 64 $or$libresoc.v:194152$13245_Y
+ attribute \src "libresoc.v:194154.18-194154.124"
+ wire width 64 $or$libresoc.v:194154$13247_Y
+ attribute \src "libresoc.v:194155.18-194155.110"
+ wire width 64 $or$libresoc.v:194155$13248_Y
+ attribute \src "libresoc.v:194157.18-194157.122"
+ wire width 64 $or$libresoc.v:194157$13250_Y
+ attribute \src "libresoc.v:194158.18-194158.109"
+ wire width 64 $or$libresoc.v:194158$13251_Y
+ attribute \src "libresoc.v:194160.17-194160.123"
+ wire width 64 $or$libresoc.v:194160$13253_Y
+ attribute \src "libresoc.v:194153.18-194153.100"
+ wire $reduce_or$libresoc.v:194153$13246_Y
+ attribute \src "libresoc.v:194156.18-194156.100"
+ wire $reduce_or$libresoc.v:194156$13249_Y
+ attribute \src "libresoc.v:194159.17-194159.95"
+ wire $reduce_or$libresoc.v:194159$13252_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 64 \$10
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 64 output 3 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 2 \cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 7 \data_i
wire width 64 input 13 \data_i$3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 14 \data_i$4
- attribute \src "libresoc.v:195058.7-195058.15"
+ attribute \src "libresoc.v:194002.7-194002.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 9 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:195208$13433
+ cell $or $or$libresoc.v:194152$13245
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_cia0__data_o
connect \B \$8
- connect \Y $or$libresoc.v:195208$13433_Y
+ connect \Y $or$libresoc.v:194152$13245_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:195210$13435
+ cell $or $or$libresoc.v:194154$13247
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_msr1__data_o
connect \B \reg_2_msr2__data_o
- connect \Y $or$libresoc.v:195210$13435_Y
+ connect \Y $or$libresoc.v:194154$13247_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:195211$13436
+ cell $or $or$libresoc.v:194155$13248
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_msr0__data_o
connect \B \$15
- connect \Y $or$libresoc.v:195211$13436_Y
+ connect \Y $or$libresoc.v:194155$13248_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:195213$13438
+ cell $or $or$libresoc.v:194157$13250
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_sv1__data_o
connect \B \reg_2_sv2__data_o
- connect \Y $or$libresoc.v:195213$13438_Y
+ connect \Y $or$libresoc.v:194157$13250_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:195214$13439
+ cell $or $or$libresoc.v:194158$13251
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_sv0__data_o
connect \B \$22
- connect \Y $or$libresoc.v:195214$13439_Y
+ connect \Y $or$libresoc.v:194158$13251_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:195216$13441
+ cell $or $or$libresoc.v:194160$13253
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_cia1__data_o
connect \B \reg_2_cia2__data_o
- connect \Y $or$libresoc.v:195216$13441_Y
+ connect \Y $or$libresoc.v:194160$13253_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:195209$13434
+ cell $reduce_or $reduce_or$libresoc.v:194153$13246
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$12
- connect \Y $reduce_or$libresoc.v:195209$13434_Y
+ connect \Y $reduce_or$libresoc.v:194153$13246_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:195212$13437
+ cell $reduce_or $reduce_or$libresoc.v:194156$13249
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$19
- connect \Y $reduce_or$libresoc.v:195212$13437_Y
+ connect \Y $reduce_or$libresoc.v:194156$13249_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:195215$13440
+ cell $reduce_or $reduce_or$libresoc.v:194159$13252
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:195215$13440_Y
+ connect \Y $reduce_or$libresoc.v:194159$13252_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195223.15-195240.4"
+ attribute \src "libresoc.v:194167.15-194184.4"
cell \reg_0$135 \reg_0
connect \cia0__data_o \reg_0_cia0__data_o
connect \cia0__ren \reg_0_cia0__ren
connect \sv0__wen \reg_0_sv0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195241.15-195258.4"
+ attribute \src "libresoc.v:194185.15-194202.4"
cell \reg_1$136 \reg_1
connect \cia1__data_o \reg_1_cia1__data_o
connect \cia1__ren \reg_1_cia1__ren
connect \sv1__wen \reg_1_sv1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195259.15-195276.4"
+ attribute \src "libresoc.v:194203.15-194220.4"
cell \reg_2$137 \reg_2
connect \cia2__data_o \reg_2_cia2__data_o
connect \cia2__ren \reg_2_cia2__ren
connect \sv2__ren \reg_2_sv2__ren
connect \sv2__wen \reg_2_sv2__wen
end
- attribute \src "libresoc.v:195058.7-195058.20"
- process $proc$libresoc.v:195058$13459
+ attribute \src "libresoc.v:194002.7-194002.20"
+ process $proc$libresoc.v:194002$13271
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:195184.13-195184.29"
- process $proc$libresoc.v:195184$13460
+ attribute \src "libresoc.v:194128.13-194128.29"
+ process $proc$libresoc.v:194128$13272
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:195186.13-195186.34"
- process $proc$libresoc.v:195186$13461
+ attribute \src "libresoc.v:194130.13-194130.34"
+ process $proc$libresoc.v:194130$13273
assign { } { }
- assign $0\ren_delay$12[2:0]$13462 3'000
+ assign $0\ren_delay$12[2:0]$13274 3'000
sync always
sync init
- update \ren_delay$12 $0\ren_delay$12[2:0]$13462
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13274
end
- attribute \src "libresoc.v:195190.13-195190.34"
- process $proc$libresoc.v:195190$13463
+ attribute \src "libresoc.v:194134.13-194134.34"
+ process $proc$libresoc.v:194134$13275
assign { } { }
- assign $0\ren_delay$19[2:0]$13464 3'000
+ assign $0\ren_delay$19[2:0]$13276 3'000
sync always
sync init
- update \ren_delay$19 $0\ren_delay$19[2:0]$13464
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13276
end
- attribute \src "libresoc.v:195217.3-195218.43"
- process $proc$libresoc.v:195217$13442
+ attribute \src "libresoc.v:194161.3-194162.43"
+ process $proc$libresoc.v:194161$13254
assign { } { }
- assign $0\ren_delay$19[2:0]$13443 \ren_delay$19$next
+ assign $0\ren_delay$19[2:0]$13255 \ren_delay$19$next
sync posedge \coresync_clk
- update \ren_delay$19 $0\ren_delay$19[2:0]$13443
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13255
end
- attribute \src "libresoc.v:195219.3-195220.43"
- process $proc$libresoc.v:195219$13444
+ attribute \src "libresoc.v:194163.3-194164.43"
+ process $proc$libresoc.v:194163$13256
assign { } { }
- assign $0\ren_delay$12[2:0]$13445 \ren_delay$12$next
+ assign $0\ren_delay$12[2:0]$13257 \ren_delay$12$next
sync posedge \coresync_clk
- update \ren_delay$12 $0\ren_delay$12[2:0]$13445
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13257
end
- attribute \src "libresoc.v:195221.3-195222.35"
- process $proc$libresoc.v:195221$13446
+ attribute \src "libresoc.v:194165.3-194166.35"
+ process $proc$libresoc.v:194165$13258
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:195277.3-195285.6"
- process $proc$libresoc.v:195277$13447
+ attribute \src "libresoc.v:194221.3-194229.6"
+ process $proc$libresoc.v:194221$13259
assign { } { }
assign { } { }
- assign $0\ren_delay$19$next[2:0]$13448 $1\ren_delay$19$next[2:0]$13449
- attribute \src "libresoc.v:195278.5-195278.29"
+ assign $0\ren_delay$19$next[2:0]$13260 $1\ren_delay$19$next[2:0]$13261
+ attribute \src "libresoc.v:194222.5-194222.29"
switch \initial
- attribute \src "libresoc.v:195278.9-195278.17"
+ attribute \src "libresoc.v:194222.9-194222.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$19$next[2:0]$13449 3'000
+ assign $1\ren_delay$19$next[2:0]$13261 3'000
case
- assign $1\ren_delay$19$next[2:0]$13449 \sv__ren
+ assign $1\ren_delay$19$next[2:0]$13261 \sv__ren
end
sync always
- update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13448
+ update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13260
end
- attribute \src "libresoc.v:195286.3-195295.6"
- process $proc$libresoc.v:195286$13450
+ attribute \src "libresoc.v:194230.3-194239.6"
+ process $proc$libresoc.v:194230$13262
assign { } { }
assign { } { }
assign $0\sv__data_o[63:0] $1\sv__data_o[63:0]
- attribute \src "libresoc.v:195287.5-195287.29"
+ attribute \src "libresoc.v:194231.5-194231.29"
switch \initial
- attribute \src "libresoc.v:195287.9-195287.17"
+ attribute \src "libresoc.v:194231.9-194231.17"
case 1'1
case
end
sync always
update \sv__data_o $0\sv__data_o[63:0]
end
- attribute \src "libresoc.v:195296.3-195304.6"
- process $proc$libresoc.v:195296$13451
+ attribute \src "libresoc.v:194240.3-194248.6"
+ process $proc$libresoc.v:194240$13263
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$13452 $1\ren_delay$next[2:0]$13453
- attribute \src "libresoc.v:195297.5-195297.29"
+ assign $0\ren_delay$next[2:0]$13264 $1\ren_delay$next[2:0]$13265
+ attribute \src "libresoc.v:194241.5-194241.29"
switch \initial
- attribute \src "libresoc.v:195297.9-195297.17"
+ attribute \src "libresoc.v:194241.9-194241.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$13453 3'000
+ assign $1\ren_delay$next[2:0]$13265 3'000
case
- assign $1\ren_delay$next[2:0]$13453 \cia__ren
+ assign $1\ren_delay$next[2:0]$13265 \cia__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$13452
+ update \ren_delay$next $0\ren_delay$next[2:0]$13264
end
- attribute \src "libresoc.v:195305.3-195314.6"
- process $proc$libresoc.v:195305$13454
+ attribute \src "libresoc.v:194249.3-194258.6"
+ process $proc$libresoc.v:194249$13266
assign { } { }
assign { } { }
assign $0\cia__data_o[63:0] $1\cia__data_o[63:0]
- attribute \src "libresoc.v:195306.5-195306.29"
+ attribute \src "libresoc.v:194250.5-194250.29"
switch \initial
- attribute \src "libresoc.v:195306.9-195306.17"
+ attribute \src "libresoc.v:194250.9-194250.17"
case 1'1
case
end
sync always
update \cia__data_o $0\cia__data_o[63:0]
end
- attribute \src "libresoc.v:195315.3-195323.6"
- process $proc$libresoc.v:195315$13455
+ attribute \src "libresoc.v:194259.3-194267.6"
+ process $proc$libresoc.v:194259$13267
assign { } { }
assign { } { }
- assign $0\ren_delay$12$next[2:0]$13456 $1\ren_delay$12$next[2:0]$13457
- attribute \src "libresoc.v:195316.5-195316.29"
+ assign $0\ren_delay$12$next[2:0]$13268 $1\ren_delay$12$next[2:0]$13269
+ attribute \src "libresoc.v:194260.5-194260.29"
switch \initial
- attribute \src "libresoc.v:195316.9-195316.17"
+ attribute \src "libresoc.v:194260.9-194260.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$12$next[2:0]$13457 3'000
+ assign $1\ren_delay$12$next[2:0]$13269 3'000
case
- assign $1\ren_delay$12$next[2:0]$13457 \msr__ren
+ assign $1\ren_delay$12$next[2:0]$13269 \msr__ren
end
sync always
- update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13456
+ update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13268
end
- attribute \src "libresoc.v:195324.3-195333.6"
- process $proc$libresoc.v:195324$13458
+ attribute \src "libresoc.v:194268.3-194277.6"
+ process $proc$libresoc.v:194268$13270
assign { } { }
assign { } { }
assign $0\msr__data_o[63:0] $1\msr__data_o[63:0]
- attribute \src "libresoc.v:195325.5-195325.29"
+ attribute \src "libresoc.v:194269.5-194269.29"
switch \initial
- attribute \src "libresoc.v:195325.9-195325.17"
+ attribute \src "libresoc.v:194269.9-194269.17"
case 1'1
case
end
sync always
update \msr__data_o $0\msr__data_o[63:0]
end
- connect \$10 $or$libresoc.v:195208$13433_Y
- connect \$13 $reduce_or$libresoc.v:195209$13434_Y
- connect \$15 $or$libresoc.v:195210$13435_Y
- connect \$17 $or$libresoc.v:195211$13436_Y
- connect \$20 $reduce_or$libresoc.v:195212$13437_Y
- connect \$22 $or$libresoc.v:195213$13438_Y
- connect \$24 $or$libresoc.v:195214$13439_Y
- connect \$6 $reduce_or$libresoc.v:195215$13440_Y
- connect \$8 $or$libresoc.v:195216$13441_Y
+ connect \$10 $or$libresoc.v:194152$13245_Y
+ connect \$13 $reduce_or$libresoc.v:194153$13246_Y
+ connect \$15 $or$libresoc.v:194154$13247_Y
+ connect \$17 $or$libresoc.v:194155$13248_Y
+ connect \$20 $reduce_or$libresoc.v:194156$13249_Y
+ connect \$22 $or$libresoc.v:194157$13250_Y
+ connect \$24 $or$libresoc.v:194158$13251_Y
+ connect \$6 $reduce_or$libresoc.v:194159$13252_Y
+ connect \$8 $or$libresoc.v:194160$13253_Y
connect \reg_2_d_wr12__data_i \data_i
connect \reg_1_d_wr11__data_i \data_i
connect \reg_0_d_wr10__data_i \data_i
connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
end
-attribute \src "libresoc.v:195357.1-195415.10"
+attribute \src "libresoc.v:194301.1-194359.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l"
attribute \generator "nMigen"
module \sto_l
- attribute \src "libresoc.v:195358.7-195358.20"
+ attribute \src "libresoc.v:194302.7-194302.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:195403.3-195411.6"
- wire $0\q_int$next[0:0]$13475
- attribute \src "libresoc.v:195401.3-195402.27"
+ attribute \src "libresoc.v:194347.3-194355.6"
+ wire $0\q_int$next[0:0]$13287
+ attribute \src "libresoc.v:194345.3-194346.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:195403.3-195411.6"
- wire $1\q_int$next[0:0]$13476
- attribute \src "libresoc.v:195380.7-195380.19"
+ attribute \src "libresoc.v:194347.3-194355.6"
+ wire $1\q_int$next[0:0]$13288
+ attribute \src "libresoc.v:194324.7-194324.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:195393.17-195393.96"
- wire $and$libresoc.v:195393$13465_Y
- attribute \src "libresoc.v:195398.17-195398.96"
- wire $and$libresoc.v:195398$13470_Y
- attribute \src "libresoc.v:195395.18-195395.93"
- wire $not$libresoc.v:195395$13467_Y
- attribute \src "libresoc.v:195397.17-195397.92"
- wire $not$libresoc.v:195397$13469_Y
- attribute \src "libresoc.v:195400.17-195400.92"
- wire $not$libresoc.v:195400$13472_Y
- attribute \src "libresoc.v:195394.18-195394.98"
- wire $or$libresoc.v:195394$13466_Y
- attribute \src "libresoc.v:195396.18-195396.99"
- wire $or$libresoc.v:195396$13468_Y
- attribute \src "libresoc.v:195399.17-195399.97"
- wire $or$libresoc.v:195399$13471_Y
+ attribute \src "libresoc.v:194337.17-194337.96"
+ wire $and$libresoc.v:194337$13277_Y
+ attribute \src "libresoc.v:194342.17-194342.96"
+ wire $and$libresoc.v:194342$13282_Y
+ attribute \src "libresoc.v:194339.18-194339.93"
+ wire $not$libresoc.v:194339$13279_Y
+ attribute \src "libresoc.v:194341.17-194341.92"
+ wire $not$libresoc.v:194341$13281_Y
+ attribute \src "libresoc.v:194344.17-194344.92"
+ wire $not$libresoc.v:194344$13284_Y
+ attribute \src "libresoc.v:194338.18-194338.98"
+ wire $or$libresoc.v:194338$13278_Y
+ attribute \src "libresoc.v:194340.18-194340.99"
+ wire $or$libresoc.v:194340$13280_Y
+ attribute \src "libresoc.v:194343.17-194343.97"
+ wire $or$libresoc.v:194343$13283_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:195358.7-195358.15"
+ attribute \src "libresoc.v:194302.7-194302.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_sto
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:195393$13465
+ cell $and $and$libresoc.v:194337$13277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:195393$13465_Y
+ connect \Y $and$libresoc.v:194337$13277_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:195398$13470
+ cell $and $and$libresoc.v:194342$13282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:195398$13470_Y
+ connect \Y $and$libresoc.v:194342$13282_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:195395$13467
+ cell $not $not$libresoc.v:194339$13279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_sto
- connect \Y $not$libresoc.v:195395$13467_Y
+ connect \Y $not$libresoc.v:194339$13279_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:195397$13469
+ cell $not $not$libresoc.v:194341$13281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:195397$13469_Y
+ connect \Y $not$libresoc.v:194341$13281_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:195400$13472
+ cell $not $not$libresoc.v:194344$13284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:195400$13472_Y
+ connect \Y $not$libresoc.v:194344$13284_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:195394$13466
+ cell $or $or$libresoc.v:194338$13278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_sto
- connect \Y $or$libresoc.v:195394$13466_Y
+ connect \Y $or$libresoc.v:194338$13278_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:195396$13468
+ cell $or $or$libresoc.v:194340$13280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_sto
connect \B \q_int
- connect \Y $or$libresoc.v:195396$13468_Y
+ connect \Y $or$libresoc.v:194340$13280_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:195399$13471
+ cell $or $or$libresoc.v:194343$13283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_sto
- connect \Y $or$libresoc.v:195399$13471_Y
+ connect \Y $or$libresoc.v:194343$13283_Y
end
- attribute \src "libresoc.v:195358.7-195358.20"
- process $proc$libresoc.v:195358$13477
+ attribute \src "libresoc.v:194302.7-194302.20"
+ process $proc$libresoc.v:194302$13289
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:195380.7-195380.19"
- process $proc$libresoc.v:195380$13478
+ attribute \src "libresoc.v:194324.7-194324.19"
+ process $proc$libresoc.v:194324$13290
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:195401.3-195402.27"
- process $proc$libresoc.v:195401$13473
+ attribute \src "libresoc.v:194345.3-194346.27"
+ process $proc$libresoc.v:194345$13285
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:195403.3-195411.6"
- process $proc$libresoc.v:195403$13474
+ attribute \src "libresoc.v:194347.3-194355.6"
+ process $proc$libresoc.v:194347$13286
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13475 $1\q_int$next[0:0]$13476
- attribute \src "libresoc.v:195404.5-195404.29"
+ assign $0\q_int$next[0:0]$13287 $1\q_int$next[0:0]$13288
+ attribute \src "libresoc.v:194348.5-194348.29"
switch \initial
- attribute \src "libresoc.v:195404.9-195404.17"
+ attribute \src "libresoc.v:194348.9-194348.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13476 1'0
+ assign $1\q_int$next[0:0]$13288 1'0
case
- assign $1\q_int$next[0:0]$13476 \$5
+ assign $1\q_int$next[0:0]$13288 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13475
+ update \q_int$next $0\q_int$next[0:0]$13287
end
- connect \$9 $and$libresoc.v:195393$13465_Y
- connect \$11 $or$libresoc.v:195394$13466_Y
- connect \$13 $not$libresoc.v:195395$13467_Y
- connect \$15 $or$libresoc.v:195396$13468_Y
- connect \$1 $not$libresoc.v:195397$13469_Y
- connect \$3 $and$libresoc.v:195398$13470_Y
- connect \$5 $or$libresoc.v:195399$13471_Y
- connect \$7 $not$libresoc.v:195400$13472_Y
+ connect \$9 $and$libresoc.v:194337$13277_Y
+ connect \$11 $or$libresoc.v:194338$13278_Y
+ connect \$13 $not$libresoc.v:194339$13279_Y
+ connect \$15 $or$libresoc.v:194340$13280_Y
+ connect \$1 $not$libresoc.v:194341$13281_Y
+ connect \$3 $and$libresoc.v:194342$13282_Y
+ connect \$5 $or$libresoc.v:194343$13283_Y
+ connect \$7 $not$libresoc.v:194344$13284_Y
connect \qlq_sto \$15
connect \qn_sto \$13
connect \q_sto \$11
end
-attribute \src "libresoc.v:195420.1-196409.10"
+attribute \src "libresoc.v:194364.1-195353.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
wire input 8 \TAP_bus__tms
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
wire output 5 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 320 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
wire width 2 input 322 \clk_sel_i
wire input 1 \pc_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
wire width 64 output 2 \pc_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1080"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083"
wire output 323 \pll_18_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
wire \pll_clk_24_i
wire output 324 \pll_lck_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
wire \pll_pll_18_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1098"
wire \pllclk_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1098"
wire \pllclk_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 321 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 187 \sdr_a_0__core__o
wire input 219 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 220 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire \ti_coresync_clk
attribute \module_not_derived 1
- attribute \src "libresoc.v:196083.7-196089.4"
+ attribute \src "libresoc.v:195027.7-195033.4"
cell \pll \pll
connect \clk_24_i \pll_clk_24_i
connect \clk_pll_o \pll_clk_pll_o
connect \pll_lck_o \pll_lck_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:196090.6-196403.4"
+ attribute \src "libresoc.v:195034.6-195347.4"
cell \ti \ti
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \pll_clk_24_i \clk
connect \pllclk_clk \pll_clk_pll_o
end
-attribute \src "libresoc.v:196413.1-201735.10"
+attribute \src "libresoc.v:195357.1-200679.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti"
attribute \generator "nMigen"
module \ti
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $0\core_asmcode$next[7:0]$13970
- attribute \src "libresoc.v:198843.3-198844.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $0\core_asmcode$next[7:0]$13782
+ attribute \src "libresoc.v:197787.3-197788.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:199654.3-199698.6"
- wire $0\core_bigendian_i$10$next[0:0]$13765
- attribute \src "libresoc.v:198973.3-198974.57"
- wire $0\core_bigendian_i$10[0:0]$13690
- attribute \src "libresoc.v:196688.7-196688.35"
- wire $0\core_bigendian_i$10[0:0]$14183
- attribute \src "libresoc.v:200417.3-200429.6"
+ attribute \src "libresoc.v:198598.3-198642.6"
+ wire $0\core_bigendian_i$10$next[0:0]$13577
+ attribute \src "libresoc.v:197917.3-197918.57"
+ wire $0\core_bigendian_i$10[0:0]$13502
+ attribute \src "libresoc.v:195632.7-195632.35"
+ wire $0\core_bigendian_i$10[0:0]$13995
+ attribute \src "libresoc.v:199361.3-199373.6"
wire width 3 $0\core_cia__ren[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $0\core_core_core_cia$next[63:0]$13971
- attribute \src "libresoc.v:198917.3-198918.53"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $0\core_core_core_cia$next[63:0]$13783
+ attribute \src "libresoc.v:197861.3-197862.53"
wire width 64 $0\core_core_core_cia[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $0\core_core_core_cr_rd$next[7:0]$13972
- attribute \src "libresoc.v:198961.3-198962.57"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $0\core_core_core_cr_rd$next[7:0]$13784
+ attribute \src "libresoc.v:197905.3-197906.57"
wire width 8 $0\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_cr_rd_ok$next[0:0]$13973
- attribute \src "libresoc.v:198963.3-198964.63"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_cr_rd_ok$next[0:0]$13785
+ attribute \src "libresoc.v:197907.3-197908.63"
wire $0\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $0\core_core_core_cr_wr$next[7:0]$13974
- attribute \src "libresoc.v:198965.3-198966.57"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $0\core_core_core_cr_wr$next[7:0]$13786
+ attribute \src "libresoc.v:197909.3-197910.57"
wire width 8 $0\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$3$next[0:0]$13975
- attribute \src "libresoc.v:198943.3-198944.75"
- wire $0\core_core_core_exc_$signal$3[0:0]$13668
- attribute \src "libresoc.v:196714.7-196714.44"
- wire $0\core_core_core_exc_$signal$3[0:0]$14191
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$4$next[0:0]$13976
- attribute \src "libresoc.v:198945.3-198946.75"
- wire $0\core_core_core_exc_$signal$4[0:0]$13670
- attribute \src "libresoc.v:196718.7-196718.44"
- wire $0\core_core_core_exc_$signal$4[0:0]$14193
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$5$next[0:0]$13977
- attribute \src "libresoc.v:198947.3-198948.75"
- wire $0\core_core_core_exc_$signal$5[0:0]$13672
- attribute \src "libresoc.v:196722.7-196722.44"
- wire $0\core_core_core_exc_$signal$5[0:0]$14195
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$6$next[0:0]$13978
- attribute \src "libresoc.v:198949.3-198950.75"
- wire $0\core_core_core_exc_$signal$6[0:0]$13674
- attribute \src "libresoc.v:196726.7-196726.44"
- wire $0\core_core_core_exc_$signal$6[0:0]$14197
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$7$next[0:0]$13979
- attribute \src "libresoc.v:198953.3-198954.75"
- wire $0\core_core_core_exc_$signal$7[0:0]$13677
- attribute \src "libresoc.v:196730.7-196730.44"
- wire $0\core_core_core_exc_$signal$7[0:0]$14199
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$8$next[0:0]$13980
- attribute \src "libresoc.v:198955.3-198956.75"
- wire $0\core_core_core_exc_$signal$8[0:0]$13679
- attribute \src "libresoc.v:196734.7-196734.44"
- wire $0\core_core_core_exc_$signal$8[0:0]$14201
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$9$next[0:0]$13981
- attribute \src "libresoc.v:198957.3-198958.75"
- wire $0\core_core_core_exc_$signal$9[0:0]$13681
- attribute \src "libresoc.v:196738.7-196738.44"
- wire $0\core_core_core_exc_$signal$9[0:0]$14203
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_exc_$signal$next[0:0]$13982
- attribute \src "libresoc.v:198941.3-198942.71"
- wire $0\core_core_core_exc_$signal[0:0]$13666
- attribute \src "libresoc.v:196712.7-196712.42"
- wire $0\core_core_core_exc_$signal[0:0]$14189
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 14 $0\core_core_core_fn_unit$next[13:0]$13983
- attribute \src "libresoc.v:198923.3-198924.61"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$3$next[0:0]$13787
+ attribute \src "libresoc.v:197887.3-197888.75"
+ wire $0\core_core_core_exc_$signal$3[0:0]$13480
+ attribute \src "libresoc.v:195658.7-195658.44"
+ wire $0\core_core_core_exc_$signal$3[0:0]$14003
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$4$next[0:0]$13788
+ attribute \src "libresoc.v:197889.3-197890.75"
+ wire $0\core_core_core_exc_$signal$4[0:0]$13482
+ attribute \src "libresoc.v:195662.7-195662.44"
+ wire $0\core_core_core_exc_$signal$4[0:0]$14005
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$5$next[0:0]$13789
+ attribute \src "libresoc.v:197891.3-197892.75"
+ wire $0\core_core_core_exc_$signal$5[0:0]$13484
+ attribute \src "libresoc.v:195666.7-195666.44"
+ wire $0\core_core_core_exc_$signal$5[0:0]$14007
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$6$next[0:0]$13790
+ attribute \src "libresoc.v:197893.3-197894.75"
+ wire $0\core_core_core_exc_$signal$6[0:0]$13486
+ attribute \src "libresoc.v:195670.7-195670.44"
+ wire $0\core_core_core_exc_$signal$6[0:0]$14009
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$7$next[0:0]$13791
+ attribute \src "libresoc.v:197897.3-197898.75"
+ wire $0\core_core_core_exc_$signal$7[0:0]$13489
+ attribute \src "libresoc.v:195674.7-195674.44"
+ wire $0\core_core_core_exc_$signal$7[0:0]$14011
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$8$next[0:0]$13792
+ attribute \src "libresoc.v:197899.3-197900.75"
+ wire $0\core_core_core_exc_$signal$8[0:0]$13491
+ attribute \src "libresoc.v:195678.7-195678.44"
+ wire $0\core_core_core_exc_$signal$8[0:0]$14013
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$9$next[0:0]$13793
+ attribute \src "libresoc.v:197901.3-197902.75"
+ wire $0\core_core_core_exc_$signal$9[0:0]$13493
+ attribute \src "libresoc.v:195682.7-195682.44"
+ wire $0\core_core_core_exc_$signal$9[0:0]$14015
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_exc_$signal$next[0:0]$13794
+ attribute \src "libresoc.v:197885.3-197886.71"
+ wire $0\core_core_core_exc_$signal[0:0]$13478
+ attribute \src "libresoc.v:195656.7-195656.42"
+ wire $0\core_core_core_exc_$signal[0:0]$14001
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 14 $0\core_core_core_fn_unit$next[13:0]$13795
+ attribute \src "libresoc.v:197867.3-197868.61"
wire width 14 $0\core_core_core_fn_unit[13:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 2 $0\core_core_core_input_carry$next[1:0]$13984
- attribute \src "libresoc.v:198937.3-198938.69"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 2 $0\core_core_core_input_carry$next[1:0]$13796
+ attribute \src "libresoc.v:197881.3-197882.69"
wire width 2 $0\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 32 $0\core_core_core_insn$next[31:0]$13985
- attribute \src "libresoc.v:198919.3-198920.55"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 32 $0\core_core_core_insn$next[31:0]$13797
+ attribute \src "libresoc.v:197863.3-197864.55"
wire width 32 $0\core_core_core_insn[31:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_core_insn_type$next[6:0]$13986
- attribute \src "libresoc.v:198921.3-198922.65"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_core_insn_type$next[6:0]$13798
+ attribute \src "libresoc.v:197865.3-197866.65"
wire width 7 $0\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_is_32bit$next[0:0]$13987
- attribute \src "libresoc.v:198969.3-198970.63"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_is_32bit$next[0:0]$13799
+ attribute \src "libresoc.v:197913.3-197914.63"
wire $0\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $0\core_core_core_msr$next[63:0]$13988
- attribute \src "libresoc.v:198915.3-198916.53"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $0\core_core_core_msr$next[63:0]$13800
+ attribute \src "libresoc.v:197859.3-197860.53"
wire width 64 $0\core_core_core_msr[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_oe$next[0:0]$13989
- attribute \src "libresoc.v:198933.3-198934.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_oe$next[0:0]$13801
+ attribute \src "libresoc.v:197877.3-197878.51"
wire $0\core_core_core_oe[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_oe_ok$next[0:0]$13990
- attribute \src "libresoc.v:198935.3-198936.57"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_oe_ok$next[0:0]$13802
+ attribute \src "libresoc.v:197879.3-197880.57"
wire $0\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_rc$next[0:0]$13991
- attribute \src "libresoc.v:198927.3-198928.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_rc$next[0:0]$13803
+ attribute \src "libresoc.v:197871.3-197872.51"
wire $0\core_core_core_rc[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_core_rc_ok$next[0:0]$13992
- attribute \src "libresoc.v:198931.3-198932.57"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_core_rc_ok$next[0:0]$13804
+ attribute \src "libresoc.v:197875.3-197876.57"
wire $0\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 13 $0\core_core_core_trapaddr$next[12:0]$13993
- attribute \src "libresoc.v:198959.3-198960.63"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 13 $0\core_core_core_trapaddr$next[12:0]$13805
+ attribute \src "libresoc.v:197903.3-197904.63"
wire width 13 $0\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $0\core_core_core_traptype$next[7:0]$13994
- attribute \src "libresoc.v:198939.3-198940.63"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $0\core_core_core_traptype$next[7:0]$13806
+ attribute \src "libresoc.v:197883.3-197884.63"
wire width 8 $0\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_cr_in1$next[6:0]$13995
- attribute \src "libresoc.v:198897.3-198898.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_cr_in1$next[6:0]$13807
+ attribute \src "libresoc.v:197841.3-197842.49"
wire width 7 $0\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_cr_in1_ok$next[0:0]$13996
- attribute \src "libresoc.v:198899.3-198900.55"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_cr_in1_ok$next[0:0]$13808
+ attribute \src "libresoc.v:197843.3-197844.55"
wire $0\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_cr_in2$1$next[6:0]$13997
- attribute \src "libresoc.v:198905.3-198906.55"
- wire width 7 $0\core_core_cr_in2$1[6:0]$13646
- attribute \src "libresoc.v:196896.13-196896.41"
- wire width 7 $0\core_core_cr_in2$1[6:0]$14220
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_cr_in2$next[6:0]$13998
- attribute \src "libresoc.v:198901.3-198902.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_cr_in2$1$next[6:0]$13809
+ attribute \src "libresoc.v:197849.3-197850.55"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$13458
+ attribute \src "libresoc.v:195840.13-195840.41"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$14032
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_cr_in2$next[6:0]$13810
+ attribute \src "libresoc.v:197845.3-197846.49"
wire width 7 $0\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_cr_in2_ok$2$next[0:0]$13999
- attribute \src "libresoc.v:198909.3-198910.61"
- wire $0\core_core_cr_in2_ok$2[0:0]$13649
- attribute \src "libresoc.v:196904.7-196904.37"
- wire $0\core_core_cr_in2_ok$2[0:0]$14223
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_cr_in2_ok$next[0:0]$14000
- attribute \src "libresoc.v:198903.3-198904.55"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_cr_in2_ok$2$next[0:0]$13811
+ attribute \src "libresoc.v:197853.3-197854.61"
+ wire $0\core_core_cr_in2_ok$2[0:0]$13461
+ attribute \src "libresoc.v:195848.7-195848.37"
+ wire $0\core_core_cr_in2_ok$2[0:0]$14035
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_cr_in2_ok$next[0:0]$13812
+ attribute \src "libresoc.v:197847.3-197848.55"
wire $0\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_cr_out$next[6:0]$14001
- attribute \src "libresoc.v:198911.3-198912.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_cr_out$next[6:0]$13813
+ attribute \src "libresoc.v:197855.3-197856.49"
wire width 7 $0\core_core_cr_out[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_cr_wr_ok$next[0:0]$14002
- attribute \src "libresoc.v:198967.3-198968.53"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_cr_wr_ok$next[0:0]$13814
+ attribute \src "libresoc.v:197911.3-197912.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $0\core_core_dststep$next[6:0]$13719
- attribute \src "libresoc.v:198833.3-198834.51"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $0\core_core_dststep$next[6:0]$13531
+ attribute \src "libresoc.v:197777.3-197778.51"
wire width 7 $0\core_core_dststep[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_ea$next[6:0]$14003
- attribute \src "libresoc.v:198849.3-198850.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_ea$next[6:0]$13815
+ attribute \src "libresoc.v:197793.3-197794.41"
wire width 7 $0\core_core_ea[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $0\core_core_fast1$next[2:0]$14004
- attribute \src "libresoc.v:198879.3-198880.47"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $0\core_core_fast1$next[2:0]$13816
+ attribute \src "libresoc.v:197823.3-197824.47"
wire width 3 $0\core_core_fast1[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_fast1_ok$next[0:0]$14005
- attribute \src "libresoc.v:198881.3-198882.53"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_fast1_ok$next[0:0]$13817
+ attribute \src "libresoc.v:197825.3-197826.53"
wire $0\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $0\core_core_fast2$next[2:0]$14006
- attribute \src "libresoc.v:198883.3-198884.47"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $0\core_core_fast2$next[2:0]$13818
+ attribute \src "libresoc.v:197827.3-197828.47"
wire width 3 $0\core_core_fast2[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_fast2_ok$next[0:0]$14007
- attribute \src "libresoc.v:198887.3-198888.53"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_fast2_ok$next[0:0]$13819
+ attribute \src "libresoc.v:197831.3-197832.53"
wire $0\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $0\core_core_fasto1$next[2:0]$14008
- attribute \src "libresoc.v:198889.3-198890.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $0\core_core_fasto1$next[2:0]$13820
+ attribute \src "libresoc.v:197833.3-197834.49"
wire width 3 $0\core_core_fasto1[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $0\core_core_fasto2$next[2:0]$14009
- attribute \src "libresoc.v:198893.3-198894.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $0\core_core_fasto2$next[2:0]$13821
+ attribute \src "libresoc.v:197837.3-197838.49"
wire width 3 $0\core_core_fasto2[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_lk$next[0:0]$14010
- attribute \src "libresoc.v:198925.3-198926.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_lk$next[0:0]$13822
+ attribute \src "libresoc.v:197869.3-197870.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $0\core_core_maxvl$next[6:0]$13720
- attribute \src "libresoc.v:198839.3-198840.47"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $0\core_core_maxvl$next[6:0]$13532
+ attribute \src "libresoc.v:197783.3-197784.47"
wire width 7 $0\core_core_maxvl[6:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $0\core_core_pc$next[63:0]$13721
- attribute \src "libresoc.v:198811.3-198812.41"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $0\core_core_pc$next[63:0]$13533
+ attribute \src "libresoc.v:197755.3-197756.41"
wire width 64 $0\core_core_pc[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_reg1$next[6:0]$14011
- attribute \src "libresoc.v:198853.3-198854.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_reg1$next[6:0]$13823
+ attribute \src "libresoc.v:197797.3-197798.45"
wire width 7 $0\core_core_reg1[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_reg1_ok$next[0:0]$14012
- attribute \src "libresoc.v:198855.3-198856.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_reg1_ok$next[0:0]$13824
+ attribute \src "libresoc.v:197799.3-197800.51"
wire $0\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_reg2$next[6:0]$14013
- attribute \src "libresoc.v:198857.3-198858.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_reg2$next[6:0]$13825
+ attribute \src "libresoc.v:197801.3-197802.45"
wire width 7 $0\core_core_reg2[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_reg2_ok$next[0:0]$14014
- attribute \src "libresoc.v:198859.3-198860.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_reg2_ok$next[0:0]$13826
+ attribute \src "libresoc.v:197803.3-197804.51"
wire $0\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_reg3$next[6:0]$14015
- attribute \src "libresoc.v:198861.3-198862.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_reg3$next[6:0]$13827
+ attribute \src "libresoc.v:197805.3-197806.45"
wire width 7 $0\core_core_reg3[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_reg3_ok$next[0:0]$14016
- attribute \src "libresoc.v:198865.3-198866.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_reg3_ok$next[0:0]$13828
+ attribute \src "libresoc.v:197809.3-197810.51"
wire $0\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $0\core_core_rego$next[6:0]$14017
- attribute \src "libresoc.v:198845.3-198846.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $0\core_core_rego$next[6:0]$13829
+ attribute \src "libresoc.v:197789.3-197790.45"
wire width 7 $0\core_core_rego[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $0\core_core_spr1$next[9:0]$14018
- attribute \src "libresoc.v:198871.3-198872.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $0\core_core_spr1$next[9:0]$13830
+ attribute \src "libresoc.v:197815.3-197816.45"
wire width 10 $0\core_core_spr1[9:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_core_spr1_ok$next[0:0]$14019
- attribute \src "libresoc.v:198873.3-198874.51"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_core_spr1_ok$next[0:0]$13831
+ attribute \src "libresoc.v:197817.3-197818.51"
wire $0\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $0\core_core_spro$next[9:0]$14020
- attribute \src "libresoc.v:198867.3-198868.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $0\core_core_spro$next[9:0]$13832
+ attribute \src "libresoc.v:197811.3-197812.45"
wire width 10 $0\core_core_spro[9:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $0\core_core_srcstep$next[6:0]$13722
- attribute \src "libresoc.v:198835.3-198836.51"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $0\core_core_srcstep$next[6:0]$13534
+ attribute \src "libresoc.v:197779.3-197780.51"
wire width 7 $0\core_core_srcstep[6:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $0\core_core_subvl$next[1:0]$13723
- attribute \src "libresoc.v:198831.3-198832.47"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $0\core_core_subvl$next[1:0]$13535
+ attribute \src "libresoc.v:197775.3-197776.47"
wire width 2 $0\core_core_subvl[1:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $0\core_core_svstep$next[1:0]$13724
- attribute \src "libresoc.v:198829.3-198830.49"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $0\core_core_svstep$next[1:0]$13536
+ attribute \src "libresoc.v:197773.3-197774.49"
wire width 2 $0\core_core_svstep[1:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $0\core_core_vl$next[6:0]$13725
- attribute \src "libresoc.v:198837.3-198838.41"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $0\core_core_vl$next[6:0]$13537
+ attribute \src "libresoc.v:197781.3-197782.41"
wire width 7 $0\core_core_vl[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $0\core_core_xer_in$next[2:0]$14021
- attribute \src "libresoc.v:198875.3-198876.49"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $0\core_core_xer_in$next[2:0]$13833
+ attribute \src "libresoc.v:197819.3-197820.49"
wire width 3 $0\core_core_xer_in[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_cr_out_ok$next[0:0]$14022
- attribute \src "libresoc.v:198913.3-198914.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_cr_out_ok$next[0:0]$13834
+ attribute \src "libresoc.v:197857.3-197858.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:199946.3-199955.6"
- wire width 64 $0\core_data_i$12[63:0]$13784
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:198890.3-198899.6"
+ wire width 64 $0\core_data_i$12[63:0]$13596
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $0\core_data_i[63:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $0\core_dec$next[63:0]$13726
- attribute \src "libresoc.v:198827.3-198828.33"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $0\core_dec$next[63:0]$13538
+ attribute \src "libresoc.v:197771.3-197772.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:200063.3-200072.6"
+ attribute \src "libresoc.v:199007.3-199016.6"
wire width 5 $0\core_dmi__addr[4:0]
- attribute \src "libresoc.v:200073.3-200082.6"
+ attribute \src "libresoc.v:199017.3-199026.6"
wire $0\core_dmi__ren[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_ea_ok$next[0:0]$14023
- attribute \src "libresoc.v:198851.3-198852.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_ea_ok$next[0:0]$13835
+ attribute \src "libresoc.v:197795.3-197796.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire $0\core_eint$next[0:0]$13727
- attribute \src "libresoc.v:198825.3-198826.35"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire $0\core_eint$next[0:0]$13539
+ attribute \src "libresoc.v:197769.3-197770.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_fasto1_ok$next[0:0]$14024
- attribute \src "libresoc.v:198891.3-198892.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_fasto1_ok$next[0:0]$13836
+ attribute \src "libresoc.v:197835.3-197836.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_fasto2_ok$next[0:0]$14025
- attribute \src "libresoc.v:198895.3-198896.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_fasto2_ok$next[0:0]$13837
+ attribute \src "libresoc.v:197839.3-197840.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:200112.3-200121.6"
+ attribute \src "libresoc.v:199056.3-199065.6"
wire width 8 $0\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:200151.3-200160.6"
+ attribute \src "libresoc.v:199095.3-199104.6"
wire width 3 $0\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:200271.3-200293.6"
- wire width 3 $0\core_issue__addr$13[2:0]$13824
- attribute \src "libresoc.v:200190.3-200208.6"
+ attribute \src "libresoc.v:199215.3-199237.6"
+ wire width 3 $0\core_issue__addr$13[2:0]$13636
+ attribute \src "libresoc.v:199134.3-199152.6"
wire width 3 $0\core_issue__addr[2:0]
- attribute \src "libresoc.v:200317.3-200339.6"
+ attribute \src "libresoc.v:199261.3-199283.6"
wire width 64 $0\core_issue__data_i[63:0]
- attribute \src "libresoc.v:200209.3-200227.6"
+ attribute \src "libresoc.v:199153.3-199171.6"
wire $0\core_issue__ren[0:0]
- attribute \src "libresoc.v:200294.3-200316.6"
+ attribute \src "libresoc.v:199238.3-199260.6"
wire $0\core_issue__wen[0:0]
- attribute \src "libresoc.v:199992.3-200007.6"
+ attribute \src "libresoc.v:198936.3-198951.6"
wire $0\core_issue_i[0:0]
- attribute \src "libresoc.v:199967.3-199991.6"
+ attribute \src "libresoc.v:198911.3-198935.6"
wire $0\core_ivalid_i[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $0\core_msr$next[63:0]$13728
- attribute \src "libresoc.v:198823.3-198824.33"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $0\core_msr$next[63:0]$13540
+ attribute \src "libresoc.v:197767.3-197768.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:200628.3-200643.6"
+ attribute \src "libresoc.v:199572.3-199587.6"
wire width 3 $0\core_msr__ren[2:0]
- attribute \src "libresoc.v:199629.3-199653.6"
- wire width 32 $0\core_raw_insn_i$next[31:0]$13760
- attribute \src "libresoc.v:198995.3-198996.47"
+ attribute \src "libresoc.v:198573.3-198597.6"
+ wire width 32 $0\core_raw_insn_i$next[31:0]$13572
+ attribute \src "libresoc.v:197939.3-197940.47"
wire width 32 $0\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_rego_ok$next[0:0]$14026
- attribute \src "libresoc.v:198847.3-198848.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_rego_ok$next[0:0]$13838
+ attribute \src "libresoc.v:197791.3-197792.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_spro_ok$next[0:0]$14027
- attribute \src "libresoc.v:198869.3-198870.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_spro_ok$next[0:0]$13839
+ attribute \src "libresoc.v:197813.3-197814.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:201207.3-201253.6"
+ attribute \src "libresoc.v:200151.3-200197.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:200455.3-200467.6"
+ attribute \src "libresoc.v:199399.3-199411.6"
wire width 3 $0\core_sv__ren[2:0]
- attribute \src "libresoc.v:199699.3-199743.6"
- wire $0\core_sv_a_nz$next[0:0]$13770
- attribute \src "libresoc.v:198951.3-198952.41"
+ attribute \src "libresoc.v:198643.3-198687.6"
+ wire $0\core_sv_a_nz$next[0:0]$13582
+ attribute \src "libresoc.v:197895.3-197896.41"
wire $0\core_sv_a_nz[0:0]
- attribute \src "libresoc.v:199936.3-199945.6"
- wire width 3 $0\core_wen$11[2:0]$13781
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:198880.3-198889.6"
+ wire width 3 $0\core_wen$11[2:0]$13593
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $0\core_wen[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $0\core_xer_out$next[0:0]$14028
- attribute \src "libresoc.v:198877.3-198878.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $0\core_xer_out$next[0:0]$13840
+ attribute \src "libresoc.v:197821.3-197822.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:199009.3-199010.43"
+ attribute \src "libresoc.v:197953.3-197954.43"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $0\cur_cur_dststep$next[6:0]$13865
- attribute \src "libresoc.v:198993.3-198994.47"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $0\cur_cur_dststep$next[6:0]$13677
+ attribute \src "libresoc.v:197937.3-197938.47"
wire width 7 $0\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $0\cur_cur_maxvl$next[6:0]$13866
- attribute \src "libresoc.v:199001.3-199002.43"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $0\cur_cur_maxvl$next[6:0]$13678
+ attribute \src "libresoc.v:197945.3-197946.43"
wire width 7 $0\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $0\cur_cur_srcstep$next[6:0]$13867
- attribute \src "libresoc.v:198997.3-198998.47"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $0\cur_cur_srcstep$next[6:0]$13679
+ attribute \src "libresoc.v:197941.3-197942.47"
wire width 7 $0\cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $0\cur_cur_subvl$next[1:0]$13868
- attribute \src "libresoc.v:198991.3-198992.43"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $0\cur_cur_subvl$next[1:0]$13680
+ attribute \src "libresoc.v:197935.3-197936.43"
wire width 2 $0\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $0\cur_cur_svstep$next[1:0]$13869
- attribute \src "libresoc.v:198989.3-198990.45"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $0\cur_cur_svstep$next[1:0]$13681
+ attribute \src "libresoc.v:197933.3-197934.45"
wire width 2 $0\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $0\cur_cur_vl$next[6:0]$13870
- attribute \src "libresoc.v:198999.3-199000.37"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $0\cur_cur_vl$next[6:0]$13682
+ attribute \src "libresoc.v:197943.3-197944.37"
wire width 7 $0\cur_cur_vl[6:0]
- attribute \src "libresoc.v:200122.3-200130.6"
- wire $0\d_cr_delay$next[0:0]$13806
- attribute \src "libresoc.v:198885.3-198886.37"
+ attribute \src "libresoc.v:199066.3-199074.6"
+ wire $0\d_cr_delay$next[0:0]$13618
+ attribute \src "libresoc.v:197829.3-197830.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:200083.3-200091.6"
- wire $0\d_reg_delay$next[0:0]$13800
- attribute \src "libresoc.v:198907.3-198908.39"
+ attribute \src "libresoc.v:199027.3-199035.6"
+ wire $0\d_reg_delay$next[0:0]$13612
+ attribute \src "libresoc.v:197851.3-197852.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:200161.3-200169.6"
- wire $0\d_xer_delay$next[0:0]$13812
- attribute \src "libresoc.v:198863.3-198864.39"
+ attribute \src "libresoc.v:199105.3-199113.6"
+ wire $0\d_xer_delay$next[0:0]$13624
+ attribute \src "libresoc.v:197807.3-197808.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:201254.3-201300.6"
+ attribute \src "libresoc.v:200198.3-200244.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:200141.3-200150.6"
+ attribute \src "libresoc.v:199085.3-199094.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:200131.3-200140.6"
+ attribute \src "libresoc.v:199075.3-199084.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:200102.3-200111.6"
+ attribute \src "libresoc.v:199046.3-199055.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:200092.3-200101.6"
+ attribute \src "libresoc.v:199036.3-199045.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:200180.3-200189.6"
+ attribute \src "libresoc.v:199124.3-199133.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:200170.3-200179.6"
+ attribute \src "libresoc.v:199114.3-199123.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:199546.3-199554.6"
- wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13713
- attribute \src "libresoc.v:198821.3-198822.45"
+ attribute \src "libresoc.v:198490.3-198498.6"
+ wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13525
+ attribute \src "libresoc.v:197765.3-197766.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:200644.3-200652.6"
- wire width 64 $0\dbg_dmi_din$next[63:0]$13850
- attribute \src "libresoc.v:198815.3-198816.39"
+ attribute \src "libresoc.v:199588.3-199596.6"
+ wire width 64 $0\dbg_dmi_din$next[63:0]$13662
+ attribute \src "libresoc.v:197759.3-197760.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:199555.3-199563.6"
- wire $0\dbg_dmi_req_i$next[0:0]$13716
- attribute \src "libresoc.v:198819.3-198820.43"
+ attribute \src "libresoc.v:198499.3-198507.6"
+ wire $0\dbg_dmi_req_i$next[0:0]$13528
+ attribute \src "libresoc.v:197763.3-197764.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:200383.3-200391.6"
- wire $0\dbg_dmi_we_i$next[0:0]$13834
- attribute \src "libresoc.v:198817.3-198818.41"
+ attribute \src "libresoc.v:199327.3-199335.6"
+ wire $0\dbg_dmi_we_i$next[0:0]$13646
+ attribute \src "libresoc.v:197761.3-197762.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:200340.3-200359.6"
- wire width 64 $0\dec2_cur_dec$next[63:0]$13829
- attribute \src "libresoc.v:198809.3-198810.41"
+ attribute \src "libresoc.v:199284.3-199303.6"
+ wire width 64 $0\dec2_cur_dec$next[63:0]$13641
+ attribute \src "libresoc.v:197753.3-197754.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:201686.3-201694.6"
- wire $0\dec2_cur_eint$next[0:0]$14175
- attribute \src "libresoc.v:199013.3-199014.43"
+ attribute \src "libresoc.v:200630.3-200638.6"
+ wire $0\dec2_cur_eint$next[0:0]$13987
+ attribute \src "libresoc.v:197957.3-197958.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:200910.3-200934.6"
- wire width 64 $0\dec2_cur_msr$next[63:0]$13913
- attribute \src "libresoc.v:198983.3-198984.41"
+ attribute \src "libresoc.v:199854.3-199878.6"
+ wire width 64 $0\dec2_cur_msr$next[63:0]$13725
+ attribute \src "libresoc.v:197927.3-197928.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:200757.3-200777.6"
- wire width 64 $0\dec2_cur_pc$next[63:0]$13860
- attribute \src "libresoc.v:199003.3-199004.39"
+ attribute \src "libresoc.v:199701.3-199721.6"
+ wire width 64 $0\dec2_cur_pc$next[63:0]$13672
+ attribute \src "libresoc.v:197947.3-197948.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:200958.3-200992.6"
- wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13922
- attribute \src "libresoc.v:198979.3-198980.53"
+ attribute \src "libresoc.v:199902.3-199936.6"
+ wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13734
+ attribute \src "libresoc.v:197923.3-197924.53"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:201695.3-201704.6"
- wire width 2 $0\delay$next[1:0]$14178
- attribute \src "libresoc.v:199011.3-199012.27"
+ attribute \src "libresoc.v:200639.3-200648.6"
+ wire width 2 $0\delay$next[1:0]$13990
+ attribute \src "libresoc.v:197955.3-197956.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $0\exec_fsm_state$next[0:0]$13790
- attribute \src "libresoc.v:198929.3-198930.45"
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $0\exec_fsm_state$next[0:0]$13602
+ attribute \src "libresoc.v:197873.3-197874.45"
wire $0\exec_fsm_state[0:0]
- attribute \src "libresoc.v:199956.3-199966.6"
+ attribute \src "libresoc.v:198900.3-198910.6"
wire $0\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:199832.3-199858.6"
+ attribute \src "libresoc.v:198776.3-198802.6"
wire $0\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:199859.3-199894.6"
+ attribute \src "libresoc.v:198803.3-198838.6"
wire $0\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:200043.3-200062.6"
+ attribute \src "libresoc.v:198987.3-199006.6"
wire $0\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $0\fetch_fsm_state$next[1:0]$13905
- attribute \src "libresoc.v:198985.3-198986.47"
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $0\fetch_fsm_state$next[1:0]$13717
+ attribute \src "libresoc.v:197929.3-197930.47"
wire width 2 $0\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:201540.3-201554.6"
+ attribute \src "libresoc.v:200484.3-200498.6"
wire $0\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:200993.3-201015.6"
+ attribute \src "libresoc.v:199937.3-199959.6"
wire $0\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:200653.3-200663.6"
+ attribute \src "libresoc.v:199597.3-199607.6"
wire $0\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:201092.3-201107.6"
+ attribute \src "libresoc.v:200036.3-200051.6"
wire $0\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:200228.3-200255.6"
- wire width 2 $0\fsm_state$next[1:0]$13819
- attribute \src "libresoc.v:198841.3-198842.35"
+ attribute \src "libresoc.v:199172.3-199199.6"
+ wire width 2 $0\fsm_state$next[1:0]$13631
+ attribute \src "libresoc.v:197785.3-197786.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:200664.3-200679.6"
+ attribute \src "libresoc.v:199608.3-199623.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:200689.3-200722.6"
+ attribute \src "libresoc.v:199633.3-199666.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200723.3-200756.6"
+ attribute \src "libresoc.v:199667.3-199700.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:196414.7-196414.20"
+ attribute \src "libresoc.v:195358.7-195358.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $0\insn_done[0:0]
- attribute \src "libresoc.v:199895.3-199935.6"
+ attribute \src "libresoc.v:198839.3-198879.6"
wire $0\is_last[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $0\issue_fsm_state$next[2:0]$13930
- attribute \src "libresoc.v:198977.3-198978.47"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $0\issue_fsm_state$next[2:0]$13742
+ attribute \src "libresoc.v:197921.3-197922.47"
wire width 3 $0\issue_fsm_state[2:0]
- attribute \src "libresoc.v:200680.3-200688.6"
- wire $0\jtag_dmi0__ack_o$next[0:0]$13855
- attribute \src "libresoc.v:198813.3-198814.49"
+ attribute \src "libresoc.v:199624.3-199632.6"
+ wire $0\jtag_dmi0__ack_o$next[0:0]$13667
+ attribute \src "libresoc.v:197757.3-197758.49"
wire $0\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:200847.3-200855.6"
- wire width 64 $0\jtag_dmi0__dout$next[63:0]$13902
- attribute \src "libresoc.v:199015.3-199016.47"
+ attribute \src "libresoc.v:199791.3-199799.6"
+ wire width 64 $0\jtag_dmi0__dout$next[63:0]$13714
+ attribute \src "libresoc.v:197959.3-197960.47"
wire width 64 $0\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:200817.3-200846.6"
- wire $0\msr_read$next[0:0]$13896
- attribute \src "libresoc.v:198987.3-198988.33"
+ attribute \src "libresoc.v:199761.3-199790.6"
+ wire $0\msr_read$next[0:0]$13708
+ attribute \src "libresoc.v:197931.3-197932.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:200256.3-200270.6"
+ attribute \src "libresoc.v:199200.3-199214.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $0\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $0\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $0\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $0\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $0\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $0\new_svstate_vl[6:0]
- attribute \src "libresoc.v:200360.3-200382.6"
+ attribute \src "libresoc.v:199304.3-199326.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:200935.3-200957.6"
- wire width 64 $0\nia$next[63:0]$13918
- attribute \src "libresoc.v:198981.3-198982.23"
+ attribute \src "libresoc.v:199879.3-199901.6"
+ wire width 64 $0\nia$next[63:0]$13730
+ attribute \src "libresoc.v:197925.3-197926.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:200401.3-200416.6"
+ attribute \src "libresoc.v:199345.3-199360.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $0\pc_changed$next[0:0]$13946
- attribute \src "libresoc.v:198975.3-198976.37"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $0\pc_changed$next[0:0]$13758
+ attribute \src "libresoc.v:197919.3-197920.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:200392.3-200400.6"
- wire $0\pc_ok_delay$next[0:0]$13837
- attribute \src "libresoc.v:199007.3-199008.39"
+ attribute \src "libresoc.v:199336.3-199344.6"
+ wire $0\pc_ok_delay$next[0:0]$13649
+ attribute \src "libresoc.v:197951.3-197952.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:199790.3-199808.6"
+ attribute \src "libresoc.v:198734.3-198752.6"
wire $0\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:199809.3-199831.6"
+ attribute \src "libresoc.v:198753.3-198775.6"
wire $0\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $0\sv_changed$next[0:0]$13958
- attribute \src "libresoc.v:198971.3-198972.37"
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $0\sv_changed$next[0:0]$13770
+ attribute \src "libresoc.v:197915.3-197916.37"
wire $0\sv_changed[0:0]
- attribute \src "libresoc.v:200439.3-200454.6"
+ attribute \src "libresoc.v:199383.3-199398.6"
wire width 64 $0\svstate[63:0]
- attribute \src "libresoc.v:200430.3-200438.6"
- wire $0\svstate_ok_delay$next[0:0]$13842
- attribute \src "libresoc.v:199005.3-199006.49"
+ attribute \src "libresoc.v:199374.3-199382.6"
+ wire $0\svstate_ok_delay$next[0:0]$13654
+ attribute \src "libresoc.v:197949.3-197950.49"
wire $0\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $0\update_svstate[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $10\issue_fsm_state$next[2:0]$13940
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $11\issue_fsm_state$next[2:0]$13941
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $12\issue_fsm_state$next[2:0]$13942
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $1\core_asmcode$next[7:0]$14029
- attribute \src "libresoc.v:196682.13-196682.33"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $10\issue_fsm_state$next[2:0]$13752
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $11\issue_fsm_state$next[2:0]$13753
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $12\issue_fsm_state$next[2:0]$13754
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $1\core_asmcode$next[7:0]$13841
+ attribute \src "libresoc.v:195626.13-195626.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:199654.3-199698.6"
- wire $1\core_bigendian_i$10$next[0:0]$13766
- attribute \src "libresoc.v:200417.3-200429.6"
+ attribute \src "libresoc.v:198598.3-198642.6"
+ wire $1\core_bigendian_i$10$next[0:0]$13578
+ attribute \src "libresoc.v:199361.3-199373.6"
wire width 3 $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $1\core_core_core_cia$next[63:0]$14030
- attribute \src "libresoc.v:196696.14-196696.55"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $1\core_core_core_cia$next[63:0]$13842
+ attribute \src "libresoc.v:195640.14-195640.55"
wire width 64 $1\core_core_core_cia[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $1\core_core_core_cr_rd$next[7:0]$14031
- attribute \src "libresoc.v:196700.13-196700.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $1\core_core_core_cr_rd$next[7:0]$13843
+ attribute \src "libresoc.v:195644.13-195644.41"
wire width 8 $1\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_cr_rd_ok$next[0:0]$14032
- attribute \src "libresoc.v:196704.7-196704.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_cr_rd_ok$next[0:0]$13844
+ attribute \src "libresoc.v:195648.7-195648.37"
wire $1\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $1\core_core_core_cr_wr$next[7:0]$14033
- attribute \src "libresoc.v:196708.13-196708.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $1\core_core_core_cr_wr$next[7:0]$13845
+ attribute \src "libresoc.v:195652.13-195652.41"
wire width 8 $1\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$3$next[0:0]$14034
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$4$next[0:0]$14035
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$5$next[0:0]$14036
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$6$next[0:0]$14037
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$7$next[0:0]$14038
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$8$next[0:0]$14039
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$9$next[0:0]$14040
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_exc_$signal$next[0:0]$14041
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 14 $1\core_core_core_fn_unit$next[13:0]$14042
- attribute \src "libresoc.v:196759.14-196759.47"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$3$next[0:0]$13846
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$4$next[0:0]$13847
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$5$next[0:0]$13848
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$6$next[0:0]$13849
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$7$next[0:0]$13850
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$8$next[0:0]$13851
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$9$next[0:0]$13852
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_exc_$signal$next[0:0]$13853
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 14 $1\core_core_core_fn_unit$next[13:0]$13854
+ attribute \src "libresoc.v:195703.14-195703.47"
wire width 14 $1\core_core_core_fn_unit[13:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 2 $1\core_core_core_input_carry$next[1:0]$14043
- attribute \src "libresoc.v:196767.13-196767.46"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 2 $1\core_core_core_input_carry$next[1:0]$13855
+ attribute \src "libresoc.v:195711.13-195711.46"
wire width 2 $1\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 32 $1\core_core_core_insn$next[31:0]$14044
- attribute \src "libresoc.v:196771.14-196771.41"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 32 $1\core_core_core_insn$next[31:0]$13856
+ attribute \src "libresoc.v:195715.14-195715.41"
wire width 32 $1\core_core_core_insn[31:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_core_insn_type$next[6:0]$14045
- attribute \src "libresoc.v:196850.13-196850.45"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_core_insn_type$next[6:0]$13857
+ attribute \src "libresoc.v:195794.13-195794.45"
wire width 7 $1\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_is_32bit$next[0:0]$14046
- attribute \src "libresoc.v:196854.7-196854.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_is_32bit$next[0:0]$13858
+ attribute \src "libresoc.v:195798.7-195798.37"
wire $1\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $1\core_core_core_msr$next[63:0]$14047
- attribute \src "libresoc.v:196858.14-196858.55"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $1\core_core_core_msr$next[63:0]$13859
+ attribute \src "libresoc.v:195802.14-195802.55"
wire width 64 $1\core_core_core_msr[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_oe$next[0:0]$14048
- attribute \src "libresoc.v:196862.7-196862.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_oe$next[0:0]$13860
+ attribute \src "libresoc.v:195806.7-195806.31"
wire $1\core_core_core_oe[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_oe_ok$next[0:0]$14049
- attribute \src "libresoc.v:196866.7-196866.34"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_oe_ok$next[0:0]$13861
+ attribute \src "libresoc.v:195810.7-195810.34"
wire $1\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_rc$next[0:0]$14050
- attribute \src "libresoc.v:196870.7-196870.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_rc$next[0:0]$13862
+ attribute \src "libresoc.v:195814.7-195814.31"
wire $1\core_core_core_rc[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_core_rc_ok$next[0:0]$14051
- attribute \src "libresoc.v:196874.7-196874.34"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_core_rc_ok$next[0:0]$13863
+ attribute \src "libresoc.v:195818.7-195818.34"
wire $1\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 13 $1\core_core_core_trapaddr$next[12:0]$14052
- attribute \src "libresoc.v:196878.14-196878.48"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 13 $1\core_core_core_trapaddr$next[12:0]$13864
+ attribute \src "libresoc.v:195822.14-195822.48"
wire width 13 $1\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $1\core_core_core_traptype$next[7:0]$14053
- attribute \src "libresoc.v:196882.13-196882.44"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $1\core_core_core_traptype$next[7:0]$13865
+ attribute \src "libresoc.v:195826.13-195826.44"
wire width 8 $1\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_cr_in1$next[6:0]$14054
- attribute \src "libresoc.v:196886.13-196886.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_cr_in1$next[6:0]$13866
+ attribute \src "libresoc.v:195830.13-195830.37"
wire width 7 $1\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_cr_in1_ok$next[0:0]$14055
- attribute \src "libresoc.v:196890.7-196890.33"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_cr_in1_ok$next[0:0]$13867
+ attribute \src "libresoc.v:195834.7-195834.33"
wire $1\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_cr_in2$1$next[6:0]$14056
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_cr_in2$next[6:0]$14057
- attribute \src "libresoc.v:196894.13-196894.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_cr_in2$1$next[6:0]$13868
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_cr_in2$next[6:0]$13869
+ attribute \src "libresoc.v:195838.13-195838.37"
wire width 7 $1\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_cr_in2_ok$2$next[0:0]$14058
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_cr_in2_ok$next[0:0]$14059
- attribute \src "libresoc.v:196902.7-196902.33"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_cr_in2_ok$2$next[0:0]$13870
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_cr_in2_ok$next[0:0]$13871
+ attribute \src "libresoc.v:195846.7-195846.33"
wire $1\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_cr_out$next[6:0]$14060
- attribute \src "libresoc.v:196910.13-196910.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_cr_out$next[6:0]$13872
+ attribute \src "libresoc.v:195854.13-195854.37"
wire width 7 $1\core_core_cr_out[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_cr_wr_ok$next[0:0]$14061
- attribute \src "libresoc.v:196914.7-196914.32"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_cr_wr_ok$next[0:0]$13873
+ attribute \src "libresoc.v:195858.7-195858.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $1\core_core_dststep$next[6:0]$13729
- attribute \src "libresoc.v:196918.13-196918.38"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $1\core_core_dststep$next[6:0]$13541
+ attribute \src "libresoc.v:195862.13-195862.38"
wire width 7 $1\core_core_dststep[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_ea$next[6:0]$14062
- attribute \src "libresoc.v:196922.13-196922.33"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_ea$next[6:0]$13874
+ attribute \src "libresoc.v:195866.13-195866.33"
wire width 7 $1\core_core_ea[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $1\core_core_fast1$next[2:0]$14063
- attribute \src "libresoc.v:196926.13-196926.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $1\core_core_fast1$next[2:0]$13875
+ attribute \src "libresoc.v:195870.13-195870.35"
wire width 3 $1\core_core_fast1[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_fast1_ok$next[0:0]$14064
- attribute \src "libresoc.v:196930.7-196930.32"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_fast1_ok$next[0:0]$13876
+ attribute \src "libresoc.v:195874.7-195874.32"
wire $1\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $1\core_core_fast2$next[2:0]$14065
- attribute \src "libresoc.v:196934.13-196934.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $1\core_core_fast2$next[2:0]$13877
+ attribute \src "libresoc.v:195878.13-195878.35"
wire width 3 $1\core_core_fast2[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_fast2_ok$next[0:0]$14066
- attribute \src "libresoc.v:196938.7-196938.32"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_fast2_ok$next[0:0]$13878
+ attribute \src "libresoc.v:195882.7-195882.32"
wire $1\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $1\core_core_fasto1$next[2:0]$14067
- attribute \src "libresoc.v:196942.13-196942.36"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $1\core_core_fasto1$next[2:0]$13879
+ attribute \src "libresoc.v:195886.13-195886.36"
wire width 3 $1\core_core_fasto1[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $1\core_core_fasto2$next[2:0]$14068
- attribute \src "libresoc.v:196946.13-196946.36"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $1\core_core_fasto2$next[2:0]$13880
+ attribute \src "libresoc.v:195890.13-195890.36"
wire width 3 $1\core_core_fasto2[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_lk$next[0:0]$14069
- attribute \src "libresoc.v:196950.7-196950.26"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_lk$next[0:0]$13881
+ attribute \src "libresoc.v:195894.7-195894.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $1\core_core_maxvl$next[6:0]$13730
- attribute \src "libresoc.v:196954.13-196954.36"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $1\core_core_maxvl$next[6:0]$13542
+ attribute \src "libresoc.v:195898.13-195898.36"
wire width 7 $1\core_core_maxvl[6:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $1\core_core_pc$next[63:0]$13731
- attribute \src "libresoc.v:196958.14-196958.49"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $1\core_core_pc$next[63:0]$13543
+ attribute \src "libresoc.v:195902.14-195902.49"
wire width 64 $1\core_core_pc[63:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_reg1$next[6:0]$14070
- attribute \src "libresoc.v:196962.13-196962.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_reg1$next[6:0]$13882
+ attribute \src "libresoc.v:195906.13-195906.35"
wire width 7 $1\core_core_reg1[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_reg1_ok$next[0:0]$14071
- attribute \src "libresoc.v:196966.7-196966.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_reg1_ok$next[0:0]$13883
+ attribute \src "libresoc.v:195910.7-195910.31"
wire $1\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_reg2$next[6:0]$14072
- attribute \src "libresoc.v:196970.13-196970.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_reg2$next[6:0]$13884
+ attribute \src "libresoc.v:195914.13-195914.35"
wire width 7 $1\core_core_reg2[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_reg2_ok$next[0:0]$14073
- attribute \src "libresoc.v:196974.7-196974.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_reg2_ok$next[0:0]$13885
+ attribute \src "libresoc.v:195918.7-195918.31"
wire $1\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_reg3$next[6:0]$14074
- attribute \src "libresoc.v:196978.13-196978.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_reg3$next[6:0]$13886
+ attribute \src "libresoc.v:195922.13-195922.35"
wire width 7 $1\core_core_reg3[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_reg3_ok$next[0:0]$14075
- attribute \src "libresoc.v:196982.7-196982.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_reg3_ok$next[0:0]$13887
+ attribute \src "libresoc.v:195926.7-195926.31"
wire $1\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $1\core_core_rego$next[6:0]$14076
- attribute \src "libresoc.v:196986.13-196986.35"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $1\core_core_rego$next[6:0]$13888
+ attribute \src "libresoc.v:195930.13-195930.35"
wire width 7 $1\core_core_rego[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $1\core_core_spr1$next[9:0]$14077
- attribute \src "libresoc.v:197104.13-197104.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $1\core_core_spr1$next[9:0]$13889
+ attribute \src "libresoc.v:196048.13-196048.37"
wire width 10 $1\core_core_spr1[9:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_core_spr1_ok$next[0:0]$14078
- attribute \src "libresoc.v:197108.7-197108.31"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_core_spr1_ok$next[0:0]$13890
+ attribute \src "libresoc.v:196052.7-196052.31"
wire $1\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $1\core_core_spro$next[9:0]$14079
- attribute \src "libresoc.v:197226.13-197226.37"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $1\core_core_spro$next[9:0]$13891
+ attribute \src "libresoc.v:196170.13-196170.37"
wire width 10 $1\core_core_spro[9:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $1\core_core_srcstep$next[6:0]$13732
- attribute \src "libresoc.v:197230.13-197230.38"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $1\core_core_srcstep$next[6:0]$13544
+ attribute \src "libresoc.v:196174.13-196174.38"
wire width 7 $1\core_core_srcstep[6:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $1\core_core_subvl$next[1:0]$13733
- attribute \src "libresoc.v:197234.13-197234.35"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $1\core_core_subvl$next[1:0]$13545
+ attribute \src "libresoc.v:196178.13-196178.35"
wire width 2 $1\core_core_subvl[1:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $1\core_core_svstep$next[1:0]$13734
- attribute \src "libresoc.v:197238.13-197238.36"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $1\core_core_svstep$next[1:0]$13546
+ attribute \src "libresoc.v:196182.13-196182.36"
wire width 2 $1\core_core_svstep[1:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $1\core_core_vl$next[6:0]$13735
- attribute \src "libresoc.v:197244.13-197244.33"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $1\core_core_vl$next[6:0]$13547
+ attribute \src "libresoc.v:196188.13-196188.33"
wire width 7 $1\core_core_vl[6:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $1\core_core_xer_in$next[2:0]$14080
- attribute \src "libresoc.v:197248.13-197248.36"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $1\core_core_xer_in$next[2:0]$13892
+ attribute \src "libresoc.v:196192.13-196192.36"
wire width 3 $1\core_core_xer_in[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_cr_out_ok$next[0:0]$14081
- attribute \src "libresoc.v:197256.7-197256.28"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_cr_out_ok$next[0:0]$13893
+ attribute \src "libresoc.v:196200.7-196200.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:199946.3-199955.6"
- wire width 64 $1\core_data_i$12[63:0]$13785
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:198890.3-198899.6"
+ wire width 64 $1\core_data_i$12[63:0]$13597
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $1\core_data_i[63:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $1\core_dec$next[63:0]$13736
- attribute \src "libresoc.v:197272.14-197272.45"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $1\core_dec$next[63:0]$13548
+ attribute \src "libresoc.v:196216.14-196216.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:200063.3-200072.6"
+ attribute \src "libresoc.v:199007.3-199016.6"
wire width 5 $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:200073.3-200082.6"
+ attribute \src "libresoc.v:199017.3-199026.6"
wire $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_ea_ok$next[0:0]$14082
- attribute \src "libresoc.v:197282.7-197282.24"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_ea_ok$next[0:0]$13894
+ attribute \src "libresoc.v:196226.7-196226.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire $1\core_eint$next[0:0]$13737
- attribute \src "libresoc.v:197286.7-197286.23"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire $1\core_eint$next[0:0]$13549
+ attribute \src "libresoc.v:196230.7-196230.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_fasto1_ok$next[0:0]$14083
- attribute \src "libresoc.v:197290.7-197290.28"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_fasto1_ok$next[0:0]$13895
+ attribute \src "libresoc.v:196234.7-196234.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_fasto2_ok$next[0:0]$14084
- attribute \src "libresoc.v:197294.7-197294.28"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_fasto2_ok$next[0:0]$13896
+ attribute \src "libresoc.v:196238.7-196238.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:200112.3-200121.6"
+ attribute \src "libresoc.v:199056.3-199065.6"
wire width 8 $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:200151.3-200160.6"
+ attribute \src "libresoc.v:199095.3-199104.6"
wire width 3 $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:200271.3-200293.6"
- wire width 3 $1\core_issue__addr$13[2:0]$13825
- attribute \src "libresoc.v:200190.3-200208.6"
+ attribute \src "libresoc.v:199215.3-199237.6"
+ wire width 3 $1\core_issue__addr$13[2:0]$13637
+ attribute \src "libresoc.v:199134.3-199152.6"
wire width 3 $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:200317.3-200339.6"
+ attribute \src "libresoc.v:199261.3-199283.6"
wire width 64 $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:200209.3-200227.6"
+ attribute \src "libresoc.v:199153.3-199171.6"
wire $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:200294.3-200316.6"
+ attribute \src "libresoc.v:199238.3-199260.6"
wire $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:199992.3-200007.6"
+ attribute \src "libresoc.v:198936.3-198951.6"
wire $1\core_issue_i[0:0]
- attribute \src "libresoc.v:199967.3-199991.6"
+ attribute \src "libresoc.v:198911.3-198935.6"
wire $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $1\core_msr$next[63:0]$13738
- attribute \src "libresoc.v:197322.14-197322.45"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $1\core_msr$next[63:0]$13550
+ attribute \src "libresoc.v:196266.14-196266.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:200628.3-200643.6"
+ attribute \src "libresoc.v:199572.3-199587.6"
wire width 3 $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:199629.3-199653.6"
- wire width 32 $1\core_raw_insn_i$next[31:0]$13761
- attribute \src "libresoc.v:197330.14-197330.37"
+ attribute \src "libresoc.v:198573.3-198597.6"
+ wire width 32 $1\core_raw_insn_i$next[31:0]$13573
+ attribute \src "libresoc.v:196274.14-196274.37"
wire width 32 $1\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_rego_ok$next[0:0]$14085
- attribute \src "libresoc.v:197334.7-197334.26"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_rego_ok$next[0:0]$13897
+ attribute \src "libresoc.v:196278.7-196278.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_spro_ok$next[0:0]$14086
- attribute \src "libresoc.v:197338.7-197338.26"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_spro_ok$next[0:0]$13898
+ attribute \src "libresoc.v:196282.7-196282.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:201207.3-201253.6"
+ attribute \src "libresoc.v:200151.3-200197.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:200455.3-200467.6"
+ attribute \src "libresoc.v:199399.3-199411.6"
wire width 3 $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:199699.3-199743.6"
- wire $1\core_sv_a_nz$next[0:0]$13771
- attribute \src "libresoc.v:197350.7-197350.26"
+ attribute \src "libresoc.v:198643.3-198687.6"
+ wire $1\core_sv_a_nz$next[0:0]$13583
+ attribute \src "libresoc.v:196294.7-196294.26"
wire $1\core_sv_a_nz[0:0]
- attribute \src "libresoc.v:199936.3-199945.6"
- wire width 3 $1\core_wen$11[2:0]$13782
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:198880.3-198889.6"
+ wire width 3 $1\core_wen$11[2:0]$13594
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $1\core_wen[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $1\core_xer_out$next[0:0]$14087
- attribute \src "libresoc.v:197360.7-197360.26"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $1\core_xer_out$next[0:0]$13899
+ attribute \src "libresoc.v:196304.7-196304.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:197366.7-197366.30"
+ attribute \src "libresoc.v:196310.7-196310.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $1\cur_cur_dststep$next[6:0]$13871
- attribute \src "libresoc.v:197372.13-197372.36"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $1\cur_cur_dststep$next[6:0]$13683
+ attribute \src "libresoc.v:196316.13-196316.36"
wire width 7 $1\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $1\cur_cur_maxvl$next[6:0]$13872
- attribute \src "libresoc.v:197376.13-197376.34"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $1\cur_cur_maxvl$next[6:0]$13684
+ attribute \src "libresoc.v:196320.13-196320.34"
wire width 7 $1\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $1\cur_cur_srcstep$next[6:0]$13873
- attribute \src "libresoc.v:197380.13-197380.36"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $1\cur_cur_srcstep$next[6:0]$13685
+ attribute \src "libresoc.v:196324.13-196324.36"
wire width 7 $1\cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $1\cur_cur_subvl$next[1:0]$13874
- attribute \src "libresoc.v:197384.13-197384.33"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $1\cur_cur_subvl$next[1:0]$13686
+ attribute \src "libresoc.v:196328.13-196328.33"
wire width 2 $1\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $1\cur_cur_svstep$next[1:0]$13875
- attribute \src "libresoc.v:197388.13-197388.34"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $1\cur_cur_svstep$next[1:0]$13687
+ attribute \src "libresoc.v:196332.13-196332.34"
wire width 2 $1\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $1\cur_cur_vl$next[6:0]$13876
- attribute \src "libresoc.v:197392.13-197392.31"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $1\cur_cur_vl$next[6:0]$13688
+ attribute \src "libresoc.v:196336.13-196336.31"
wire width 7 $1\cur_cur_vl[6:0]
- attribute \src "libresoc.v:200122.3-200130.6"
- wire $1\d_cr_delay$next[0:0]$13807
- attribute \src "libresoc.v:197396.7-197396.24"
+ attribute \src "libresoc.v:199066.3-199074.6"
+ wire $1\d_cr_delay$next[0:0]$13619
+ attribute \src "libresoc.v:196340.7-196340.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:200083.3-200091.6"
- wire $1\d_reg_delay$next[0:0]$13801
- attribute \src "libresoc.v:197400.7-197400.25"
+ attribute \src "libresoc.v:199027.3-199035.6"
+ wire $1\d_reg_delay$next[0:0]$13613
+ attribute \src "libresoc.v:196344.7-196344.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:200161.3-200169.6"
- wire $1\d_xer_delay$next[0:0]$13813
- attribute \src "libresoc.v:197404.7-197404.25"
+ attribute \src "libresoc.v:199105.3-199113.6"
+ wire $1\d_xer_delay$next[0:0]$13625
+ attribute \src "libresoc.v:196348.7-196348.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:201254.3-201300.6"
+ attribute \src "libresoc.v:200198.3-200244.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:200141.3-200150.6"
+ attribute \src "libresoc.v:199085.3-199094.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:200131.3-200140.6"
+ attribute \src "libresoc.v:199075.3-199084.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:200102.3-200111.6"
+ attribute \src "libresoc.v:199046.3-199055.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:200092.3-200101.6"
+ attribute \src "libresoc.v:199036.3-199045.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:200180.3-200189.6"
+ attribute \src "libresoc.v:199124.3-199133.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:200170.3-200179.6"
+ attribute \src "libresoc.v:199114.3-199123.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:199546.3-199554.6"
- wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13714
- attribute \src "libresoc.v:197452.13-197452.34"
+ attribute \src "libresoc.v:198490.3-198498.6"
+ wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13526
+ attribute \src "libresoc.v:196396.13-196396.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:200644.3-200652.6"
- wire width 64 $1\dbg_dmi_din$next[63:0]$13851
- attribute \src "libresoc.v:197456.14-197456.48"
+ attribute \src "libresoc.v:199588.3-199596.6"
+ wire width 64 $1\dbg_dmi_din$next[63:0]$13663
+ attribute \src "libresoc.v:196400.14-196400.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:199555.3-199563.6"
- wire $1\dbg_dmi_req_i$next[0:0]$13717
- attribute \src "libresoc.v:197462.7-197462.27"
+ attribute \src "libresoc.v:198499.3-198507.6"
+ wire $1\dbg_dmi_req_i$next[0:0]$13529
+ attribute \src "libresoc.v:196406.7-196406.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:200383.3-200391.6"
- wire $1\dbg_dmi_we_i$next[0:0]$13835
- attribute \src "libresoc.v:197466.7-197466.26"
+ attribute \src "libresoc.v:199327.3-199335.6"
+ wire $1\dbg_dmi_we_i$next[0:0]$13647
+ attribute \src "libresoc.v:196410.7-196410.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:200340.3-200359.6"
- wire width 64 $1\dec2_cur_dec$next[63:0]$13830
- attribute \src "libresoc.v:197520.14-197520.49"
+ attribute \src "libresoc.v:199284.3-199303.6"
+ wire width 64 $1\dec2_cur_dec$next[63:0]$13642
+ attribute \src "libresoc.v:196464.14-196464.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:201686.3-201694.6"
- wire $1\dec2_cur_eint$next[0:0]$14176
- attribute \src "libresoc.v:197524.7-197524.27"
+ attribute \src "libresoc.v:200630.3-200638.6"
+ wire $1\dec2_cur_eint$next[0:0]$13988
+ attribute \src "libresoc.v:196468.7-196468.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:200910.3-200934.6"
- wire width 64 $1\dec2_cur_msr$next[63:0]$13914
- attribute \src "libresoc.v:197528.14-197528.49"
+ attribute \src "libresoc.v:199854.3-199878.6"
+ wire width 64 $1\dec2_cur_msr$next[63:0]$13726
+ attribute \src "libresoc.v:196472.14-196472.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:200757.3-200777.6"
- wire width 64 $1\dec2_cur_pc$next[63:0]$13861
- attribute \src "libresoc.v:197532.14-197532.48"
+ attribute \src "libresoc.v:199701.3-199721.6"
+ wire width 64 $1\dec2_cur_pc$next[63:0]$13673
+ attribute \src "libresoc.v:196476.14-196476.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:200958.3-200992.6"
- wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13923
- attribute \src "libresoc.v:197684.14-197684.40"
+ attribute \src "libresoc.v:199902.3-199936.6"
+ wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13735
+ attribute \src "libresoc.v:196628.14-196628.40"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:201695.3-201704.6"
- wire width 2 $1\delay$next[1:0]$14179
- attribute \src "libresoc.v:197954.13-197954.25"
+ attribute \src "libresoc.v:200639.3-200648.6"
+ wire width 2 $1\delay$next[1:0]$13991
+ attribute \src "libresoc.v:196898.13-196898.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $1\exec_fsm_state$next[0:0]$13791
- attribute \src "libresoc.v:197970.7-197970.28"
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $1\exec_fsm_state$next[0:0]$13603
+ attribute \src "libresoc.v:196914.7-196914.28"
wire $1\exec_fsm_state[0:0]
- attribute \src "libresoc.v:199956.3-199966.6"
+ attribute \src "libresoc.v:198900.3-198910.6"
wire $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:199832.3-199858.6"
+ attribute \src "libresoc.v:198776.3-198802.6"
wire $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:199859.3-199894.6"
+ attribute \src "libresoc.v:198803.3-198838.6"
wire $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:200043.3-200062.6"
+ attribute \src "libresoc.v:198987.3-199006.6"
wire $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $1\fetch_fsm_state$next[1:0]$13906
- attribute \src "libresoc.v:197982.13-197982.35"
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $1\fetch_fsm_state$next[1:0]$13718
+ attribute \src "libresoc.v:196926.13-196926.35"
wire width 2 $1\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:201540.3-201554.6"
+ attribute \src "libresoc.v:200484.3-200498.6"
wire $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:200993.3-201015.6"
+ attribute \src "libresoc.v:199937.3-199959.6"
wire $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:200653.3-200663.6"
+ attribute \src "libresoc.v:199597.3-199607.6"
wire $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:201092.3-201107.6"
+ attribute \src "libresoc.v:200036.3-200051.6"
wire $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:200228.3-200255.6"
- wire width 2 $1\fsm_state$next[1:0]$13820
- attribute \src "libresoc.v:197994.13-197994.29"
+ attribute \src "libresoc.v:199172.3-199199.6"
+ wire width 2 $1\fsm_state$next[1:0]$13632
+ attribute \src "libresoc.v:196938.13-196938.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:200664.3-200679.6"
+ attribute \src "libresoc.v:199608.3-199623.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:200689.3-200722.6"
+ attribute \src "libresoc.v:199633.3-199666.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200723.3-200756.6"
+ attribute \src "libresoc.v:199667.3-199700.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $1\insn_done[0:0]
- attribute \src "libresoc.v:199895.3-199935.6"
+ attribute \src "libresoc.v:198839.3-198879.6"
wire $1\is_last[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $1\issue_fsm_state$next[2:0]$13931
- attribute \src "libresoc.v:198254.13-198254.35"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $1\issue_fsm_state$next[2:0]$13743
+ attribute \src "libresoc.v:197198.13-197198.35"
wire width 3 $1\issue_fsm_state[2:0]
- attribute \src "libresoc.v:200680.3-200688.6"
- wire $1\jtag_dmi0__ack_o$next[0:0]$13856
- attribute \src "libresoc.v:198258.7-198258.30"
+ attribute \src "libresoc.v:199624.3-199632.6"
+ wire $1\jtag_dmi0__ack_o$next[0:0]$13668
+ attribute \src "libresoc.v:197202.7-197202.30"
wire $1\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:200847.3-200855.6"
- wire width 64 $1\jtag_dmi0__dout$next[63:0]$13903
- attribute \src "libresoc.v:198266.14-198266.52"
+ attribute \src "libresoc.v:199791.3-199799.6"
+ wire width 64 $1\jtag_dmi0__dout$next[63:0]$13715
+ attribute \src "libresoc.v:197210.14-197210.52"
wire width 64 $1\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:200817.3-200846.6"
- wire $1\msr_read$next[0:0]$13897
- attribute \src "libresoc.v:198306.7-198306.22"
+ attribute \src "libresoc.v:199761.3-199790.6"
+ wire $1\msr_read$next[0:0]$13709
+ attribute \src "libresoc.v:197250.7-197250.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:200256.3-200270.6"
+ attribute \src "libresoc.v:199200.3-199214.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $1\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $1\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $1\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $1\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $1\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $1\new_svstate_vl[6:0]
- attribute \src "libresoc.v:200360.3-200382.6"
+ attribute \src "libresoc.v:199304.3-199326.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:200935.3-200957.6"
- wire width 64 $1\nia$next[63:0]$13919
- attribute \src "libresoc.v:198346.14-198346.40"
+ attribute \src "libresoc.v:199879.3-199901.6"
+ wire width 64 $1\nia$next[63:0]$13731
+ attribute \src "libresoc.v:197290.14-197290.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:200401.3-200416.6"
+ attribute \src "libresoc.v:199345.3-199360.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $1\pc_changed$next[0:0]$13947
- attribute \src "libresoc.v:198352.7-198352.24"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $1\pc_changed$next[0:0]$13759
+ attribute \src "libresoc.v:197296.7-197296.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:200392.3-200400.6"
- wire $1\pc_ok_delay$next[0:0]$13838
- attribute \src "libresoc.v:198362.7-198362.25"
+ attribute \src "libresoc.v:199336.3-199344.6"
+ wire $1\pc_ok_delay$next[0:0]$13650
+ attribute \src "libresoc.v:197306.7-197306.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:199790.3-199808.6"
+ attribute \src "libresoc.v:198734.3-198752.6"
wire $1\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:199809.3-199831.6"
+ attribute \src "libresoc.v:198753.3-198775.6"
wire $1\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $1\sv_changed$next[0:0]$13959
- attribute \src "libresoc.v:198662.7-198662.24"
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $1\sv_changed$next[0:0]$13771
+ attribute \src "libresoc.v:197606.7-197606.24"
wire $1\sv_changed[0:0]
- attribute \src "libresoc.v:200439.3-200454.6"
+ attribute \src "libresoc.v:199383.3-199398.6"
wire width 64 $1\svstate[63:0]
- attribute \src "libresoc.v:200430.3-200438.6"
- wire $1\svstate_ok_delay$next[0:0]$13843
- attribute \src "libresoc.v:198672.7-198672.30"
+ attribute \src "libresoc.v:199374.3-199382.6"
+ wire $1\svstate_ok_delay$next[0:0]$13655
+ attribute \src "libresoc.v:197616.7-197616.30"
wire $1\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $1\update_svstate[0:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $2\core_asmcode$next[7:0]$14088
- attribute \src "libresoc.v:199654.3-199698.6"
- wire $2\core_bigendian_i$10$next[0:0]$13767
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $2\core_core_core_cia$next[63:0]$14089
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $2\core_core_core_cr_rd$next[7:0]$14090
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_cr_rd_ok$next[0:0]$14091
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $2\core_core_core_cr_wr$next[7:0]$14092
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$3$next[0:0]$14093
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$4$next[0:0]$14094
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$5$next[0:0]$14095
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$6$next[0:0]$14096
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$7$next[0:0]$14097
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$8$next[0:0]$14098
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$9$next[0:0]$14099
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_exc_$signal$next[0:0]$14100
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 14 $2\core_core_core_fn_unit$next[13:0]$14101
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 2 $2\core_core_core_input_carry$next[1:0]$14102
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 32 $2\core_core_core_insn$next[31:0]$14103
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_core_insn_type$next[6:0]$14104
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_is_32bit$next[0:0]$14105
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 64 $2\core_core_core_msr$next[63:0]$14106
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_oe$next[0:0]$14107
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_oe_ok$next[0:0]$14108
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_rc$next[0:0]$14109
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_core_rc_ok$next[0:0]$14110
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 13 $2\core_core_core_trapaddr$next[12:0]$14111
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 8 $2\core_core_core_traptype$next[7:0]$14112
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_cr_in1$next[6:0]$14113
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_cr_in1_ok$next[0:0]$14114
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_cr_in2$1$next[6:0]$14115
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_cr_in2$next[6:0]$14116
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_cr_in2_ok$2$next[0:0]$14117
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_cr_in2_ok$next[0:0]$14118
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_cr_out$next[6:0]$14119
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_cr_wr_ok$next[0:0]$14120
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $2\core_core_dststep$next[6:0]$13739
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_ea$next[6:0]$14121
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $2\core_core_fast1$next[2:0]$14122
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_fast1_ok$next[0:0]$14123
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $2\core_core_fast2$next[2:0]$14124
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_fast2_ok$next[0:0]$14125
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $2\core_core_fasto1$next[2:0]$14126
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $2\core_core_fasto2$next[2:0]$14127
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_lk$next[0:0]$14128
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $2\core_core_maxvl$next[6:0]$13740
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $2\core_core_pc$next[63:0]$13741
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_reg1$next[6:0]$14129
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_reg1_ok$next[0:0]$14130
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_reg2$next[6:0]$14131
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_reg2_ok$next[0:0]$14132
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_reg3$next[6:0]$14133
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_reg3_ok$next[0:0]$14134
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 7 $2\core_core_rego$next[6:0]$14135
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $2\core_core_spr1$next[9:0]$14136
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_core_spr1_ok$next[0:0]$14137
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 10 $2\core_core_spro$next[9:0]$14138
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $2\core_core_srcstep$next[6:0]$13742
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $2\core_core_subvl$next[1:0]$13743
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $2\core_core_svstep$next[1:0]$13744
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $2\core_core_vl$next[6:0]$13745
- attribute \src "libresoc.v:201555.3-201685.6"
- wire width 3 $2\core_core_xer_in$next[2:0]$14139
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_cr_out_ok$next[0:0]$14140
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $2\core_asmcode$next[7:0]$13900
+ attribute \src "libresoc.v:198598.3-198642.6"
+ wire $2\core_bigendian_i$10$next[0:0]$13579
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $2\core_core_core_cia$next[63:0]$13901
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $2\core_core_core_cr_rd$next[7:0]$13902
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_cr_rd_ok$next[0:0]$13903
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $2\core_core_core_cr_wr$next[7:0]$13904
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$3$next[0:0]$13905
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$4$next[0:0]$13906
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$5$next[0:0]$13907
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$6$next[0:0]$13908
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$7$next[0:0]$13909
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$8$next[0:0]$13910
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$9$next[0:0]$13911
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_exc_$signal$next[0:0]$13912
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 14 $2\core_core_core_fn_unit$next[13:0]$13913
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 2 $2\core_core_core_input_carry$next[1:0]$13914
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 32 $2\core_core_core_insn$next[31:0]$13915
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_core_insn_type$next[6:0]$13916
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_is_32bit$next[0:0]$13917
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 64 $2\core_core_core_msr$next[63:0]$13918
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_oe$next[0:0]$13919
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_oe_ok$next[0:0]$13920
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_rc$next[0:0]$13921
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_core_rc_ok$next[0:0]$13922
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 13 $2\core_core_core_trapaddr$next[12:0]$13923
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 8 $2\core_core_core_traptype$next[7:0]$13924
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_cr_in1$next[6:0]$13925
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_cr_in1_ok$next[0:0]$13926
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_cr_in2$1$next[6:0]$13927
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_cr_in2$next[6:0]$13928
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_cr_in2_ok$2$next[0:0]$13929
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_cr_in2_ok$next[0:0]$13930
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_cr_out$next[6:0]$13931
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_cr_wr_ok$next[0:0]$13932
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $2\core_core_dststep$next[6:0]$13551
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_ea$next[6:0]$13933
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $2\core_core_fast1$next[2:0]$13934
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_fast1_ok$next[0:0]$13935
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $2\core_core_fast2$next[2:0]$13936
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_fast2_ok$next[0:0]$13937
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $2\core_core_fasto1$next[2:0]$13938
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $2\core_core_fasto2$next[2:0]$13939
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_lk$next[0:0]$13940
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $2\core_core_maxvl$next[6:0]$13552
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $2\core_core_pc$next[63:0]$13553
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_reg1$next[6:0]$13941
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_reg1_ok$next[0:0]$13942
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_reg2$next[6:0]$13943
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_reg2_ok$next[0:0]$13944
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_reg3$next[6:0]$13945
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_reg3_ok$next[0:0]$13946
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 7 $2\core_core_rego$next[6:0]$13947
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $2\core_core_spr1$next[9:0]$13948
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_core_spr1_ok$next[0:0]$13949
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 10 $2\core_core_spro$next[9:0]$13950
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $2\core_core_srcstep$next[6:0]$13554
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $2\core_core_subvl$next[1:0]$13555
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $2\core_core_svstep$next[1:0]$13556
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $2\core_core_vl$next[6:0]$13557
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire width 3 $2\core_core_xer_in$next[2:0]$13951
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_cr_out_ok$next[0:0]$13952
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $2\core_data_i[63:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $2\core_dec$next[63:0]$13746
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_ea_ok$next[0:0]$14141
- attribute \src "libresoc.v:199564.3-199628.6"
- wire $2\core_eint$next[0:0]$13747
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_fasto1_ok$next[0:0]$14142
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_fasto2_ok$next[0:0]$14143
- attribute \src "libresoc.v:199992.3-200007.6"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $2\core_dec$next[63:0]$13558
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_ea_ok$next[0:0]$13953
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire $2\core_eint$next[0:0]$13559
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_fasto1_ok$next[0:0]$13954
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_fasto2_ok$next[0:0]$13955
+ attribute \src "libresoc.v:198936.3-198951.6"
wire $2\core_issue_i[0:0]
- attribute \src "libresoc.v:199967.3-199991.6"
+ attribute \src "libresoc.v:198911.3-198935.6"
wire $2\core_ivalid_i[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $2\core_msr$next[63:0]$13748
- attribute \src "libresoc.v:200628.3-200643.6"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $2\core_msr$next[63:0]$13560
+ attribute \src "libresoc.v:199572.3-199587.6"
wire width 3 $2\core_msr__ren[2:0]
- attribute \src "libresoc.v:199629.3-199653.6"
- wire width 32 $2\core_raw_insn_i$next[31:0]$13762
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_rego_ok$next[0:0]$14144
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_spro_ok$next[0:0]$14145
- attribute \src "libresoc.v:201207.3-201253.6"
+ attribute \src "libresoc.v:198573.3-198597.6"
+ wire width 32 $2\core_raw_insn_i$next[31:0]$13574
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_rego_ok$next[0:0]$13956
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_spro_ok$next[0:0]$13957
+ attribute \src "libresoc.v:200151.3-200197.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:199699.3-199743.6"
- wire $2\core_sv_a_nz$next[0:0]$13772
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:198643.3-198687.6"
+ wire $2\core_sv_a_nz$next[0:0]$13584
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $2\core_wen[2:0]
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $2\core_xer_out$next[0:0]$14146
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $2\cur_cur_dststep$next[6:0]$13877
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $2\cur_cur_maxvl$next[6:0]$13878
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $2\cur_cur_srcstep$next[6:0]$13879
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $2\cur_cur_subvl$next[1:0]$13880
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $2\cur_cur_svstep$next[1:0]$13881
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $2\cur_cur_vl$next[6:0]$13882
- attribute \src "libresoc.v:201254.3-201300.6"
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $2\core_xer_out$next[0:0]$13958
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $2\cur_cur_dststep$next[6:0]$13689
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $2\cur_cur_maxvl$next[6:0]$13690
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $2\cur_cur_srcstep$next[6:0]$13691
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $2\cur_cur_subvl$next[1:0]$13692
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $2\cur_cur_svstep$next[1:0]$13693
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $2\cur_cur_vl$next[6:0]$13694
+ attribute \src "libresoc.v:200198.3-200244.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:200340.3-200359.6"
- wire width 64 $2\dec2_cur_dec$next[63:0]$13831
- attribute \src "libresoc.v:200910.3-200934.6"
- wire width 64 $2\dec2_cur_msr$next[63:0]$13915
- attribute \src "libresoc.v:200757.3-200777.6"
- wire width 64 $2\dec2_cur_pc$next[63:0]$13862
- attribute \src "libresoc.v:200958.3-200992.6"
- wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13924
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $2\exec_fsm_state$next[0:0]$13792
- attribute \src "libresoc.v:199859.3-199894.6"
+ attribute \src "libresoc.v:199284.3-199303.6"
+ wire width 64 $2\dec2_cur_dec$next[63:0]$13643
+ attribute \src "libresoc.v:199854.3-199878.6"
+ wire width 64 $2\dec2_cur_msr$next[63:0]$13727
+ attribute \src "libresoc.v:199701.3-199721.6"
+ wire width 64 $2\dec2_cur_pc$next[63:0]$13674
+ attribute \src "libresoc.v:199902.3-199936.6"
+ wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13736
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $2\exec_fsm_state$next[0:0]$13604
+ attribute \src "libresoc.v:198803.3-198838.6"
wire $2\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:200043.3-200062.6"
+ attribute \src "libresoc.v:198987.3-199006.6"
wire $2\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $2\fetch_fsm_state$next[1:0]$13907
- attribute \src "libresoc.v:201092.3-201107.6"
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $2\fetch_fsm_state$next[1:0]$13719
+ attribute \src "libresoc.v:200036.3-200051.6"
wire $2\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:200228.3-200255.6"
- wire width 2 $2\fsm_state$next[1:0]$13821
- attribute \src "libresoc.v:200664.3-200679.6"
+ attribute \src "libresoc.v:199172.3-199199.6"
+ wire width 2 $2\fsm_state$next[1:0]$13633
+ attribute \src "libresoc.v:199608.3-199623.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:200689.3-200722.6"
+ attribute \src "libresoc.v:199633.3-199666.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200723.3-200756.6"
+ attribute \src "libresoc.v:199667.3-199700.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $2\insn_done[0:0]
- attribute \src "libresoc.v:199895.3-199935.6"
+ attribute \src "libresoc.v:198839.3-198879.6"
wire $2\is_last[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $2\issue_fsm_state$next[2:0]$13932
- attribute \src "libresoc.v:200817.3-200846.6"
- wire $2\msr_read$next[0:0]$13898
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $2\issue_fsm_state$next[2:0]$13744
+ attribute \src "libresoc.v:199761.3-199790.6"
+ wire $2\msr_read$next[0:0]$13710
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $2\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $2\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $2\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $2\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $2\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $2\new_svstate_vl[6:0]
- attribute \src "libresoc.v:200935.3-200957.6"
- wire width 64 $2\nia$next[63:0]$13920
- attribute \src "libresoc.v:200401.3-200416.6"
+ attribute \src "libresoc.v:199879.3-199901.6"
+ wire width 64 $2\nia$next[63:0]$13732
+ attribute \src "libresoc.v:199345.3-199360.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $2\pc_changed$next[0:0]$13948
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $2\sv_changed$next[0:0]$13960
- attribute \src "libresoc.v:200439.3-200454.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $2\pc_changed$next[0:0]$13760
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $2\sv_changed$next[0:0]$13772
+ attribute \src "libresoc.v:199383.3-199398.6"
wire width 64 $2\svstate[63:0]
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $2\update_svstate[0:0]
- attribute \src "libresoc.v:199654.3-199698.6"
- wire $3\core_bigendian_i$10$next[0:0]$13768
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_cr_rd_ok$next[0:0]$14147
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$3$next[0:0]$14148
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$4$next[0:0]$14149
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$5$next[0:0]$14150
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$6$next[0:0]$14151
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$7$next[0:0]$14152
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$8$next[0:0]$14153
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$9$next[0:0]$14154
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_exc_$signal$next[0:0]$14155
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_oe_ok$next[0:0]$14156
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_core_rc_ok$next[0:0]$14157
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_cr_in1_ok$next[0:0]$14158
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_cr_in2_ok$2$next[0:0]$14159
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_cr_in2_ok$next[0:0]$14160
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_cr_wr_ok$next[0:0]$14161
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $3\core_core_dststep$next[6:0]$13749
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_fast1_ok$next[0:0]$14162
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_fast2_ok$next[0:0]$14163
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $3\core_core_maxvl$next[6:0]$13750
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $3\core_core_pc$next[63:0]$13751
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_reg1_ok$next[0:0]$14164
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_reg2_ok$next[0:0]$14165
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_reg3_ok$next[0:0]$14166
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_core_spr1_ok$next[0:0]$14167
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $3\core_core_srcstep$next[6:0]$13752
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $3\core_core_subvl$next[1:0]$13753
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 2 $3\core_core_svstep$next[1:0]$13754
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 7 $3\core_core_vl$next[6:0]$13755
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_cr_out_ok$next[0:0]$14168
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:198598.3-198642.6"
+ wire $3\core_bigendian_i$10$next[0:0]$13580
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_cr_rd_ok$next[0:0]$13959
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$3$next[0:0]$13960
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$4$next[0:0]$13961
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$5$next[0:0]$13962
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$6$next[0:0]$13963
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$7$next[0:0]$13964
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$8$next[0:0]$13965
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$9$next[0:0]$13966
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_exc_$signal$next[0:0]$13967
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_oe_ok$next[0:0]$13968
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_core_rc_ok$next[0:0]$13969
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_cr_in1_ok$next[0:0]$13970
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_cr_in2_ok$2$next[0:0]$13971
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_cr_in2_ok$next[0:0]$13972
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_cr_wr_ok$next[0:0]$13973
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $3\core_core_dststep$next[6:0]$13561
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_fast1_ok$next[0:0]$13974
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_fast2_ok$next[0:0]$13975
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $3\core_core_maxvl$next[6:0]$13562
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $3\core_core_pc$next[63:0]$13563
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_reg1_ok$next[0:0]$13976
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_reg2_ok$next[0:0]$13977
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_reg3_ok$next[0:0]$13978
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_core_spr1_ok$next[0:0]$13979
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $3\core_core_srcstep$next[6:0]$13564
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $3\core_core_subvl$next[1:0]$13565
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 2 $3\core_core_svstep$next[1:0]$13566
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 7 $3\core_core_vl$next[6:0]$13567
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_cr_out_ok$next[0:0]$13980
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $3\core_data_i[63:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $3\core_dec$next[63:0]$13756
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_ea_ok$next[0:0]$14169
- attribute \src "libresoc.v:199564.3-199628.6"
- wire $3\core_eint$next[0:0]$13757
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_fasto1_ok$next[0:0]$14170
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_fasto2_ok$next[0:0]$14171
- attribute \src "libresoc.v:199967.3-199991.6"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $3\core_dec$next[63:0]$13568
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_ea_ok$next[0:0]$13981
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire $3\core_eint$next[0:0]$13569
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_fasto1_ok$next[0:0]$13982
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_fasto2_ok$next[0:0]$13983
+ attribute \src "libresoc.v:198911.3-198935.6"
wire $3\core_ivalid_i[0:0]
- attribute \src "libresoc.v:199564.3-199628.6"
- wire width 64 $3\core_msr$next[63:0]$13758
- attribute \src "libresoc.v:199629.3-199653.6"
- wire width 32 $3\core_raw_insn_i$next[31:0]$13763
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_rego_ok$next[0:0]$14172
- attribute \src "libresoc.v:201555.3-201685.6"
- wire $3\core_spro_ok$next[0:0]$14173
- attribute \src "libresoc.v:201207.3-201253.6"
+ attribute \src "libresoc.v:198508.3-198572.6"
+ wire width 64 $3\core_msr$next[63:0]$13570
+ attribute \src "libresoc.v:198573.3-198597.6"
+ wire width 32 $3\core_raw_insn_i$next[31:0]$13575
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_rego_ok$next[0:0]$13984
+ attribute \src "libresoc.v:200499.3-200629.6"
+ wire $3\core_spro_ok$next[0:0]$13985
+ attribute \src "libresoc.v:200151.3-200197.6"
wire $3\core_stopped_i[0:0]
- attribute \src "libresoc.v:199699.3-199743.6"
- wire $3\core_sv_a_nz$next[0:0]$13773
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:198643.3-198687.6"
+ wire $3\core_sv_a_nz$next[0:0]$13585
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $3\core_wen[2:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $3\cur_cur_dststep$next[6:0]$13883
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $3\cur_cur_maxvl$next[6:0]$13884
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $3\cur_cur_srcstep$next[6:0]$13885
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $3\cur_cur_subvl$next[1:0]$13886
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $3\cur_cur_svstep$next[1:0]$13887
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $3\cur_cur_vl$next[6:0]$13888
- attribute \src "libresoc.v:201254.3-201300.6"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $3\cur_cur_dststep$next[6:0]$13695
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $3\cur_cur_maxvl$next[6:0]$13696
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $3\cur_cur_srcstep$next[6:0]$13697
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $3\cur_cur_subvl$next[1:0]$13698
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $3\cur_cur_svstep$next[1:0]$13699
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $3\cur_cur_vl$next[6:0]$13700
+ attribute \src "libresoc.v:200198.3-200244.6"
wire $3\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:200910.3-200934.6"
- wire width 64 $3\dec2_cur_msr$next[63:0]$13916
- attribute \src "libresoc.v:200757.3-200777.6"
- wire width 64 $3\dec2_cur_pc$next[63:0]$13863
- attribute \src "libresoc.v:200958.3-200992.6"
- wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13925
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $3\exec_fsm_state$next[0:0]$13793
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $3\fetch_fsm_state$next[1:0]$13908
- attribute \src "libresoc.v:200689.3-200722.6"
+ attribute \src "libresoc.v:199854.3-199878.6"
+ wire width 64 $3\dec2_cur_msr$next[63:0]$13728
+ attribute \src "libresoc.v:199701.3-199721.6"
+ wire width 64 $3\dec2_cur_pc$next[63:0]$13675
+ attribute \src "libresoc.v:199902.3-199936.6"
+ wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13737
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $3\exec_fsm_state$next[0:0]$13605
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $3\fetch_fsm_state$next[1:0]$13720
+ attribute \src "libresoc.v:199633.3-199666.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200723.3-200756.6"
+ attribute \src "libresoc.v:199667.3-199700.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $3\insn_done[0:0]
- attribute \src "libresoc.v:199895.3-199935.6"
+ attribute \src "libresoc.v:198839.3-198879.6"
wire $3\is_last[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $3\issue_fsm_state$next[2:0]$13933
- attribute \src "libresoc.v:200817.3-200846.6"
- wire $3\msr_read$next[0:0]$13899
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $3\issue_fsm_state$next[2:0]$13745
+ attribute \src "libresoc.v:199761.3-199790.6"
+ wire $3\msr_read$next[0:0]$13711
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $3\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $3\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $3\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $3\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $3\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $3\new_svstate_vl[6:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $3\pc_changed$next[0:0]$13949
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $3\sv_changed$next[0:0]$13961
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $3\pc_changed$next[0:0]$13761
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $3\sv_changed$next[0:0]$13773
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $3\update_svstate[0:0]
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $4\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $4\core_wen[2:0]
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $4\cur_cur_dststep$next[6:0]$13889
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $4\cur_cur_maxvl$next[6:0]$13890
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $4\cur_cur_srcstep$next[6:0]$13891
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $4\cur_cur_subvl$next[1:0]$13892
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 2 $4\cur_cur_svstep$next[1:0]$13893
- attribute \src "libresoc.v:200778.3-200816.6"
- wire width 7 $4\cur_cur_vl$next[6:0]$13894
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $4\exec_fsm_state$next[0:0]$13794
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $4\fetch_fsm_state$next[1:0]$13909
- attribute \src "libresoc.v:200689.3-200722.6"
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $4\cur_cur_dststep$next[6:0]$13701
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $4\cur_cur_maxvl$next[6:0]$13702
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $4\cur_cur_srcstep$next[6:0]$13703
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $4\cur_cur_subvl$next[1:0]$13704
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 2 $4\cur_cur_svstep$next[1:0]$13705
+ attribute \src "libresoc.v:199722.3-199760.6"
+ wire width 7 $4\cur_cur_vl$next[6:0]$13706
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $4\exec_fsm_state$next[0:0]$13606
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $4\fetch_fsm_state$next[1:0]$13721
+ attribute \src "libresoc.v:199633.3-199666.6"
wire $4\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200723.3-200756.6"
+ attribute \src "libresoc.v:199667.3-199700.6"
wire $4\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $4\insn_done[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $4\issue_fsm_state$next[2:0]$13934
- attribute \src "libresoc.v:200817.3-200846.6"
- wire $4\msr_read$next[0:0]$13900
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $4\issue_fsm_state$next[2:0]$13746
+ attribute \src "libresoc.v:199761.3-199790.6"
+ wire $4\msr_read$next[0:0]$13712
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $4\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $4\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $4\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $4\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $4\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $4\new_svstate_vl[6:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $4\pc_changed$next[0:0]$13950
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $4\sv_changed$next[0:0]$13962
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $4\pc_changed$next[0:0]$13762
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $4\sv_changed$next[0:0]$13774
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $4\update_svstate[0:0]
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $5\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $5\core_wen[2:0]
- attribute \src "libresoc.v:200008.3-200042.6"
- wire $5\exec_fsm_state$next[0:0]$13795
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $5\fetch_fsm_state$next[1:0]$13910
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:198952.3-198986.6"
+ wire $5\exec_fsm_state$next[0:0]$13607
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $5\fetch_fsm_state$next[1:0]$13722
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $5\insn_done[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $5\issue_fsm_state$next[2:0]$13935
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $5\issue_fsm_state$next[2:0]$13747
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $5\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $5\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $5\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $5\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 2 $5\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $5\new_svstate_vl[6:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $5\pc_changed$next[0:0]$13951
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $5\sv_changed$next[0:0]$13963
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $5\pc_changed$next[0:0]$13763
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $5\sv_changed$next[0:0]$13775
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $5\update_svstate[0:0]
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $6\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $6\core_wen[2:0]
- attribute \src "libresoc.v:200856.3-200909.6"
- wire width 2 $6\fetch_fsm_state$next[1:0]$13911
- attribute \src "libresoc.v:199744.3-199789.6"
+ attribute \src "libresoc.v:199800.3-199853.6"
+ wire width 2 $6\fetch_fsm_state$next[1:0]$13723
+ attribute \src "libresoc.v:198688.3-198733.6"
wire $6\insn_done[0:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $6\issue_fsm_state$next[2:0]$13936
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $6\issue_fsm_state$next[2:0]$13748
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $6\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $6\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $6\pc_changed$next[0:0]$13952
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $6\sv_changed$next[0:0]$13964
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $6\pc_changed$next[0:0]$13764
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $6\sv_changed$next[0:0]$13776
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $6\update_svstate[0:0]
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $7\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $7\core_wen[2:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $7\issue_fsm_state$next[2:0]$13937
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $7\issue_fsm_state$next[2:0]$13749
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $7\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:201016.3-201091.6"
+ attribute \src "libresoc.v:199960.3-200035.6"
wire width 7 $7\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $7\pc_changed$next[0:0]$13953
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $7\sv_changed$next[0:0]$13965
- attribute \src "libresoc.v:201384.3-201456.6"
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $7\pc_changed$next[0:0]$13765
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $7\sv_changed$next[0:0]$13777
+ attribute \src "libresoc.v:200328.3-200400.6"
wire $7\update_svstate[0:0]
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $8\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $8\core_wen[2:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $8\issue_fsm_state$next[2:0]$13938
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $8\pc_changed$next[0:0]$13954
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $8\sv_changed$next[0:0]$13966
- attribute \src "libresoc.v:200548.3-200627.6"
+ attribute \src "libresoc.v:200052.3-200150.6"
+ wire width 3 $8\issue_fsm_state$next[2:0]$13750
+ attribute \src "libresoc.v:200245.3-200327.6"
+ wire $8\pc_changed$next[0:0]$13766
+ attribute \src "libresoc.v:200401.3-200483.6"
+ wire $8\sv_changed$next[0:0]$13778
+ attribute \src "libresoc.v:199492.3-199571.6"
wire width 64 $9\core_data_i[63:0]
- attribute \src "libresoc.v:200468.3-200547.6"
+ attribute \src "libresoc.v:199412.3-199491.6"
wire width 3 $9\core_wen[2:0]
- attribute \src "libresoc.v:201108.3-201206.6"
- wire width 3 $9\issue_fsm_state$next[2:0]$13939
- attribute \src "libresoc.v:201301.3-201383.6"
- wire $9\pc_changed$next[0:0]$13955
- attribute \src "libresoc.v:201457.3-201539.6"
- wire $9\sv_changed$next[0:0]$13967
- attribute \src "libresoc.v:198689.19-198689.108"
- wire width 65 $add$libresoc.v:198689$13479_Y
- attribute \src "libresoc.v:198701.19-198701.112"
- wire width 8 $add$libresoc.v:198701$13490_Y
- attribute \src "libresoc.v:198702.19-198702.112"
- wire width 8 $add$libresoc.v:198702$13491_Y
- attribute \src "libresoc.v:198772.19-198772.116"
- wire width 65 $add$libresoc.v:198772$13561_Y
- attribute \src "libresoc.v:198806.18-198806.107"
- wire width 65 $add$libresoc.v:198806$13594_Y
- attribute \src "libresoc.v:198694.19-198694.104"
- wire $and$libresoc.v:198694$13484_Y
- attribute \src "libresoc.v:198697.19-198697.104"
- wire $and$libresoc.v:198697$13487_Y
- attribute \src "libresoc.v:198705.19-198705.104"
- wire $and$libresoc.v:198705$13494_Y
- attribute \src "libresoc.v:198708.19-198708.104"
- wire $and$libresoc.v:198708$13497_Y
- attribute \src "libresoc.v:198710.19-198710.111"
- wire $and$libresoc.v:198710$13499_Y
- attribute \src "libresoc.v:198713.19-198713.104"
- wire $and$libresoc.v:198713$13502_Y
- attribute \src "libresoc.v:198719.19-198719.104"
- wire $and$libresoc.v:198719$13507_Y
- attribute \src "libresoc.v:198722.19-198722.104"
- wire $and$libresoc.v:198722$13510_Y
- attribute \src "libresoc.v:198725.19-198725.104"
- wire $and$libresoc.v:198725$13513_Y
- attribute \src "libresoc.v:198728.19-198728.104"
- wire $and$libresoc.v:198728$13516_Y
- attribute \src "libresoc.v:198731.19-198731.104"
- wire $and$libresoc.v:198731$13519_Y
- attribute \src "libresoc.v:198734.19-198734.104"
- wire $and$libresoc.v:198734$13522_Y
- attribute \src "libresoc.v:198735.19-198735.115"
- wire width 3 $and$libresoc.v:198735$13523_Y
- attribute \src "libresoc.v:198739.19-198739.104"
- wire $and$libresoc.v:198739$13527_Y
- attribute \src "libresoc.v:198742.19-198742.104"
- wire $and$libresoc.v:198742$13530_Y
- attribute \src "libresoc.v:198748.19-198748.104"
- wire $and$libresoc.v:198748$13535_Y
- attribute \src "libresoc.v:198751.19-198751.104"
- wire $and$libresoc.v:198751$13538_Y
- attribute \src "libresoc.v:198752.19-198752.115"
- wire width 3 $and$libresoc.v:198752$13539_Y
- attribute \src "libresoc.v:198755.19-198755.111"
- wire $and$libresoc.v:198755$13542_Y
- attribute \src "libresoc.v:198760.19-198760.104"
- wire $and$libresoc.v:198760$13547_Y
- attribute \src "libresoc.v:198763.19-198763.104"
- wire $and$libresoc.v:198763$13550_Y
- attribute \src "libresoc.v:198778.18-198778.109"
- wire $and$libresoc.v:198778$13567_Y
- attribute \src "libresoc.v:198784.18-198784.101"
- wire $and$libresoc.v:198784$13574_Y
- attribute \src "libresoc.v:198786.18-198786.109"
- wire $and$libresoc.v:198786$13576_Y
- attribute \src "libresoc.v:198789.18-198789.101"
- wire $and$libresoc.v:198789$13579_Y
- attribute \src "libresoc.v:198795.18-198795.101"
- wire $and$libresoc.v:198795$13584_Y
- attribute \src "libresoc.v:198797.18-198797.109"
- wire $and$libresoc.v:198797$13586_Y
- attribute \src "libresoc.v:198800.18-198800.101"
- wire $and$libresoc.v:198800$13589_Y
- attribute \src "libresoc.v:198709.19-198709.108"
- wire $eq$libresoc.v:198709$13498_Y
- attribute \src "libresoc.v:198754.19-198754.108"
- wire $eq$libresoc.v:198754$13541_Y
- attribute \src "libresoc.v:198764.19-198764.116"
- wire $eq$libresoc.v:198764$13551_Y
- attribute \src "libresoc.v:198785.18-198785.107"
- wire $eq$libresoc.v:198785$13575_Y
- attribute \src "libresoc.v:198796.18-198796.107"
- wire $eq$libresoc.v:198796$13585_Y
- attribute \src "libresoc.v:198769.19-198769.114"
- wire width 64 $extend$libresoc.v:198769$13556_Y
- attribute \src "libresoc.v:198770.19-198770.113"
- wire width 64 $extend$libresoc.v:198770$13558_Y
- attribute \src "libresoc.v:198781.18-198781.109"
- wire width 64 $extend$libresoc.v:198781$13570_Y
- attribute \src "libresoc.v:198690.19-198690.106"
- wire width 7 $mul$libresoc.v:198690$13480_Y
- attribute \src "libresoc.v:198807.18-198807.110"
- wire width 7 $mul$libresoc.v:198807$13595_Y
- attribute \src "libresoc.v:198758.18-198758.102"
- wire $ne$libresoc.v:198758$13545_Y
- attribute \src "libresoc.v:198766.19-198766.123"
- wire $ne$libresoc.v:198766$13553_Y
- attribute \src "libresoc.v:198776.18-198776.102"
- wire $ne$libresoc.v:198776$13565_Y
- attribute \src "libresoc.v:198692.19-198692.107"
- wire $not$libresoc.v:198692$13482_Y
- attribute \src "libresoc.v:198693.19-198693.109"
- wire $not$libresoc.v:198693$13483_Y
- attribute \src "libresoc.v:198695.19-198695.107"
- wire $not$libresoc.v:198695$13485_Y
- attribute \src "libresoc.v:198696.19-198696.109"
- wire $not$libresoc.v:198696$13486_Y
- attribute \src "libresoc.v:198703.19-198703.107"
- wire $not$libresoc.v:198703$13492_Y
- attribute \src "libresoc.v:198704.19-198704.109"
- wire $not$libresoc.v:198704$13493_Y
- attribute \src "libresoc.v:198706.19-198706.107"
- wire $not$libresoc.v:198706$13495_Y
- attribute \src "libresoc.v:198707.19-198707.109"
- wire $not$libresoc.v:198707$13496_Y
- attribute \src "libresoc.v:198711.19-198711.107"
- wire $not$libresoc.v:198711$13500_Y
- attribute \src "libresoc.v:198712.19-198712.109"
- wire $not$libresoc.v:198712$13501_Y
- attribute \src "libresoc.v:198717.19-198717.107"
- wire $not$libresoc.v:198717$13505_Y
- attribute \src "libresoc.v:198718.19-198718.109"
- wire $not$libresoc.v:198718$13506_Y
- attribute \src "libresoc.v:198720.19-198720.107"
- wire $not$libresoc.v:198720$13508_Y
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wire \$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
wire width 8 \$124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
wire width 8 \$125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
wire width 8 \$127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
wire width 8 \$128
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$130
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$132
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$134
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$136
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$140
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$142
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$144
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$148
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$150
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$152
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$154
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$156
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$158
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$160
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$162
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$164
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$166
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$168
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$170
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$172
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$174
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$176
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$178
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$180
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$182
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$184
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$186
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$188
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$190
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$192
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$194
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
wire width 3 \$195
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$198
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$200
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$202
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$204
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$206
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$208
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$210
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$212
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$214
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$216
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$218
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$220
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$222
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$224
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$226
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$228
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
wire width 3 \$229
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$232
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$234
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
wire \$236
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$238
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$240
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$242
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$244
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$246
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$248
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
wire width 3 \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
wire \$250
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$252
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
wire \$254
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
wire \$256
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
wire \$258
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
wire width 3 \$26
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$260
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$262
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
wire width 65 \$264
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
wire width 65 \$265
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
wire width 65 \$267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
wire width 65 \$268
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
wire \$32
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$34
wire \$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
wire \$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
wire \$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
wire \$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$84
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
wire \$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
wire \$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
wire \$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
wire width 65 \$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
wire width 65 \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54"
wire width 32 \$95
wire input 295 \TAP_bus__tms
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
wire output 3 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 312 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
wire width 8 \core_asmcode
wire width 8 \core_asmcode$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224"
wire input 4 \core_bigendian_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
wire \core_bigendian_i$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
wire \core_bigendian_i$10$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \core_cia__data_o
wire width 2 \core_core_svstep
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26"
wire width 2 \core_core_svstep$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
wire \core_core_terminate_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \core_core_vl
wire width 3 \core_core_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
wire width 3 \core_core_xer_in$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
wire \core_corebusy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire \core_coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \core_cr_out_ok
wire \core_issue__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire \core_issue__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
wire \core_issue_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
wire \core_ivalid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
wire width 64 \core_msr
wire width 64 \core_msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \core_msr__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
wire width 32 \core_raw_insn_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
wire width 32 \core_raw_insn_i$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \core_rego_ok
wire \core_spro_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \core_state_nia_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106"
wire \core_stopped_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \core_sv__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \core_sv__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire \core_sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire \core_sv_a_nz$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
wire \core_wb_dcache_en
wire \core_xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire \core_xer_out$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 2 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
wire \cu_st__rel_o_dly
wire width 7 \cur_cur_vl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \cur_cur_vl$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960"
wire \d_cr_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960"
wire \d_cr_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950"
wire \d_reg_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950"
wire \d_reg_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970"
wire \d_xer_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970"
wire \d_xer_delay$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 \dbg_core_dbg_core_dbg_dststep
wire width 3 \dec2_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire \dec2_xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire width 2 \delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire width 2 \delay$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 155 \eint_0__core__i
wire output 157 \eint_2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 26 \eint_2__pad__i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
wire \exec_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
wire \exec_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:881"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884"
wire \exec_insn_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883"
wire \exec_insn_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:888"
wire \exec_pc_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:887"
wire \exec_pc_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
wire width 2 \fetch_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
wire width 2 \fetch_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872"
wire \fetch_insn_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871"
wire \fetch_insn_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868"
wire \fetch_pc_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867"
wire \fetch_pc_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
wire width 2 \fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
wire width 2 \fsm_state$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 164 \gpio_e10__core__i
wire \imem_f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire \imem_wb_icache_en
- attribute \src "libresoc.v:196414.7-196414.15"
+ attribute \src "libresoc.v:195358.7-195358.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254"
wire \insn_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 305 \int_level_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \is_last
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861"
wire \is_svp64_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
wire width 3 \issue_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
wire width 3 \issue_fsm_state$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire \jtag_dmi0__ack_o
wire input 77 \mspi0_mosi__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 208 \mspi0_mosi__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276"
wire \msr_read
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276"
wire \msr_read$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 82 \mtwi_scl__core__o
wire output 211 \mtwi_sda__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 212 \mtwi_sda__pad__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1000"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003"
wire width 64 \new_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 \new_svstate_dststep
wire width 2 \new_svstate_svstep
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \new_svstate_vl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020"
wire width 64 \new_tb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509"
wire width 7 \next_dststep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
wire width 7 \next_srcstep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850"
wire width 64 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850"
wire width 64 \nia$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61"
wire width 64 \pc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831"
wire \pc_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831"
wire \pc_changed$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 input 7 \pc_i
wire \pc_ok_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \pc_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788"
wire \por_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876"
wire \pred_insn_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875"
wire \pred_insn_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880"
wire \pred_mask_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879"
wire \pred_mask_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 108 \sdr_a_0__core__o
wire input 124 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 255 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:832"
wire \sv_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:832"
wire \sv_changed$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61"
wire width 64 \svstate
wire \svstate_ok_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \svstate_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
wire \ti_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:498"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:501"
wire \update_svstate
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire \xics_icp_core_irq_o
wire width 8 \xics_ics_icp_o_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349"
- cell $add $add$libresoc.v:198689$13479
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350"
+ cell $add $add$libresoc.v:197633$13291
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:198689$13479_Y
+ connect \Y $add$libresoc.v:197633$13291_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507"
- cell $add $add$libresoc.v:198701$13490
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ cell $add $add$libresoc.v:197645$13302
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \cur_cur_srcstep
connect \B 1'1
- connect \Y $add$libresoc.v:198701$13490_Y
+ connect \Y $add$libresoc.v:197645$13302_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
- cell $add $add$libresoc.v:198702$13491
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
+ cell $add $add$libresoc.v:197646$13303
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \cur_cur_dststep
connect \B 1'1
- connect \Y $add$libresoc.v:198702$13491_Y
+ connect \Y $add$libresoc.v:197646$13303_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018"
- cell $add $add$libresoc.v:198772$13561
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
+ cell $add $add$libresoc.v:197716$13373
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:198772$13561_Y
+ connect \Y $add$libresoc.v:197716$13373_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338"
- cell $add $add$libresoc.v:198806$13594
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ cell $add $add$libresoc.v:197750$13406
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:198806$13594_Y
+ connect \Y $add$libresoc.v:197750$13406_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198694$13484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197638$13296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$106
connect \B \$108
- connect \Y $and$libresoc.v:198694$13484_Y
+ connect \Y $and$libresoc.v:197638$13296_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198697$13487
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197641$13299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$112
connect \B \$114
- connect \Y $and$libresoc.v:198697$13487_Y
+ connect \Y $and$libresoc.v:197641$13299_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198705$13494
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197649$13306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$130
connect \B \$132
- connect \Y $and$libresoc.v:198705$13494_Y
+ connect \Y $and$libresoc.v:197649$13306_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198708$13497
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197652$13309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$136
connect \B \$138
- connect \Y $and$libresoc.v:198708$13497_Y
+ connect \Y $and$libresoc.v:197652$13309_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $and $and$libresoc.v:198710$13499
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $and $and$libresoc.v:197654$13311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$142
- connect \Y $and$libresoc.v:198710$13499_Y
+ connect \Y $and$libresoc.v:197654$13311_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198713$13502
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197657$13314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$146
connect \B \$148
- connect \Y $and$libresoc.v:198713$13502_Y
+ connect \Y $and$libresoc.v:197657$13314_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198719$13507
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197663$13319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$158
connect \B \$160
- connect \Y $and$libresoc.v:198719$13507_Y
+ connect \Y $and$libresoc.v:197663$13319_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198722$13510
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197666$13322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$164
connect \B \$166
- connect \Y $and$libresoc.v:198722$13510_Y
+ connect \Y $and$libresoc.v:197666$13322_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198725$13513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197669$13325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$170
connect \B \$172
- connect \Y $and$libresoc.v:198725$13513_Y
+ connect \Y $and$libresoc.v:197669$13325_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198728$13516
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197672$13328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$176
connect \B \$178
- connect \Y $and$libresoc.v:198728$13516_Y
+ connect \Y $and$libresoc.v:197672$13328_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198731$13519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197675$13331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$182
connect \B \$184
- connect \Y $and$libresoc.v:198731$13519_Y
+ connect \Y $and$libresoc.v:197675$13331_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198734$13522
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197678$13334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$188
connect \B \$190
- connect \Y $and$libresoc.v:198734$13522_Y
+ connect \Y $and$libresoc.v:197678$13334_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729"
- cell $and $and$libresoc.v:198735$13523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
+ cell $and $and$libresoc.v:197679$13335
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
connect \B 1'1
- connect \Y $and$libresoc.v:198735$13523_Y
+ connect \Y $and$libresoc.v:197679$13335_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198739$13527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197683$13339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$198
connect \B \$200
- connect \Y $and$libresoc.v:198739$13527_Y
+ connect \Y $and$libresoc.v:197683$13339_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198742$13530
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197686$13342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$204
connect \B \$206
- connect \Y $and$libresoc.v:198742$13530_Y
+ connect \Y $and$libresoc.v:197686$13342_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198748$13535
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197692$13347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$216
connect \B \$218
- connect \Y $and$libresoc.v:198748$13535_Y
+ connect \Y $and$libresoc.v:197692$13347_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198751$13538
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197695$13350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$222
connect \B \$224
- connect \Y $and$libresoc.v:198751$13538_Y
+ connect \Y $and$libresoc.v:197695$13350_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
- cell $and $and$libresoc.v:198752$13539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
+ cell $and $and$libresoc.v:197696$13351
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
connect \B 3'100
- connect \Y $and$libresoc.v:198752$13539_Y
+ connect \Y $and$libresoc.v:197696$13351_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $and $and$libresoc.v:198755$13542
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $and $and$libresoc.v:197699$13354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$232
- connect \Y $and$libresoc.v:198755$13542_Y
+ connect \Y $and$libresoc.v:197699$13354_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198760$13547
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197704$13359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$238
connect \B \$240
- connect \Y $and$libresoc.v:198760$13547_Y
+ connect \Y $and$libresoc.v:197704$13359_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198763$13550
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197707$13362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$244
connect \B \$246
- connect \Y $and$libresoc.v:198763$13550_Y
+ connect \Y $and$libresoc.v:197707$13362_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:198778$13567
+ cell $and $and$libresoc.v:197722$13379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_cu_st__rel_o
connect \B \$34
- connect \Y $and$libresoc.v:198778$13567_Y
+ connect \Y $and$libresoc.v:197722$13379_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198784$13574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197728$13386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:198784$13574_Y
+ connect \Y $and$libresoc.v:197728$13386_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $and $and$libresoc.v:198786$13576
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $and $and$libresoc.v:197730$13388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$50
- connect \Y $and$libresoc.v:198786$13576_Y
+ connect \Y $and$libresoc.v:197730$13388_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198789$13579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197733$13391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$54
connect \B \$56
- connect \Y $and$libresoc.v:198789$13579_Y
+ connect \Y $and$libresoc.v:197733$13391_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $and $and$libresoc.v:198795$13584
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $and $and$libresoc.v:197739$13396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$66
connect \B \$68
- connect \Y $and$libresoc.v:198795$13584_Y
+ connect \Y $and$libresoc.v:197739$13396_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $and $and$libresoc.v:198797$13586
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $and $and$libresoc.v:197741$13398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$72
- connect \Y $and$libresoc.v:198797$13586_Y
+ connect \Y $and$libresoc.v:197741$13398_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $and $and$libresoc.v:198800$13589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $and $and$libresoc.v:197744$13401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$76
connect \B \$78
- connect \Y $and$libresoc.v:198800$13589_Y
+ connect \Y $and$libresoc.v:197744$13401_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $eq $eq$libresoc.v:198709$13498
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $eq $eq$libresoc.v:197653$13310
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:198709$13498_Y
+ connect \Y $eq$libresoc.v:197653$13310_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $eq $eq$libresoc.v:198754$13541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $eq $eq$libresoc.v:197698$13353
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:198754$13541_Y
+ connect \Y $eq$libresoc.v:197698$13353_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
- cell $eq $eq$libresoc.v:198764$13551
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
+ cell $eq $eq$libresoc.v:197708$13363
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \next_srcstep
connect \B \cur_cur_vl
- connect \Y $eq$libresoc.v:198764$13551_Y
+ connect \Y $eq$libresoc.v:197708$13363_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $eq $eq$libresoc.v:198785$13575
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $eq $eq$libresoc.v:197729$13387
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:198785$13575_Y
+ connect \Y $eq$libresoc.v:197729$13387_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
- cell $eq $eq$libresoc.v:198796$13585
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ cell $eq $eq$libresoc.v:197740$13397
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:198796$13585_Y
+ connect \Y $eq$libresoc.v:197740$13397_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:198769$13556
+ cell $pos $extend$libresoc.v:197713$13368
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \core_full_rd2__data_o
- connect \Y $extend$libresoc.v:198769$13556_Y
+ connect \Y $extend$libresoc.v:197713$13368_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:198770$13558
+ cell $pos $extend$libresoc.v:197714$13370
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \core_full_rd__data_o
- connect \Y $extend$libresoc.v:198770$13558_Y
+ connect \Y $extend$libresoc.v:197714$13370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:198781$13570
+ cell $pos $extend$libresoc.v:197725$13382
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \svstate_i
- connect \Y $extend$libresoc.v:198781$13570_Y
+ connect \Y $extend$libresoc.v:197725$13382_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:198690$13480
+ cell $mul $mul$libresoc.v:197634$13292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \$100 [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:198690$13480_Y
+ connect \Y $mul$libresoc.v:197634$13292_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:198807$13595
+ cell $mul $mul$libresoc.v:197751$13407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:198807$13595_Y
+ connect \Y $mul$libresoc.v:197751$13407_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792"
- cell $ne $ne$libresoc.v:198758$13545
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
+ cell $ne $ne$libresoc.v:197702$13357
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B 1'0
- connect \Y $ne$libresoc.v:198758$13545_Y
+ connect \Y $ne$libresoc.v:197702$13357_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724"
- cell $ne $ne$libresoc.v:198766$13553
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
+ cell $ne $ne$libresoc.v:197710$13365
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_core_insn_type
connect \B 7'0000001
- connect \Y $ne$libresoc.v:198766$13553_Y
+ connect \Y $ne$libresoc.v:197710$13365_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
- cell $ne $ne$libresoc.v:198776$13565
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ cell $ne $ne$libresoc.v:197720$13377
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B \$30
- connect \Y $ne$libresoc.v:198776$13565_Y
+ connect \Y $ne$libresoc.v:197720$13377_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198692$13482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197636$13294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198692$13482_Y
+ connect \Y $not$libresoc.v:197636$13294_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198693$13483
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197637$13295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198693$13483_Y
+ connect \Y $not$libresoc.v:197637$13295_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197639$13297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198695$13485_Y
+ connect \Y $not$libresoc.v:197639$13297_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198696$13486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197640$13298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198703$13492
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197647$13304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198703$13492_Y
+ connect \Y $not$libresoc.v:197647$13304_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197648$13305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198704$13493_Y
+ connect \Y $not$libresoc.v:197648$13305_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198706$13495
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197650$13307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198706$13495_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198707$13496
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197651$13308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198711$13500
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197655$13312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198711$13500_Y
+ connect \Y $not$libresoc.v:197655$13312_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198712$13501
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197656$13313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198712$13501_Y
+ connect \Y $not$libresoc.v:197656$13313_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198717$13505
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197661$13317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198717$13505_Y
+ connect \Y $not$libresoc.v:197661$13317_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198718$13506
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197662$13318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198718$13506_Y
+ connect \Y $not$libresoc.v:197662$13318_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198720$13508
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197664$13320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198720$13508_Y
+ connect \Y $not$libresoc.v:197664$13320_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198721$13509
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197665$13321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198721$13509_Y
+ connect \Y $not$libresoc.v:197665$13321_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198723$13511
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197667$13323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198723$13511_Y
+ connect \Y $not$libresoc.v:197667$13323_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198724$13512
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197668$13324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198724$13512_Y
+ connect \Y $not$libresoc.v:197668$13324_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198726$13514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197670$13326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198726$13514_Y
+ connect \Y $not$libresoc.v:197670$13326_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198727$13515
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197671$13327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198727$13515_Y
+ connect \Y $not$libresoc.v:197671$13327_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198729$13517
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197673$13329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198729$13517_Y
+ connect \Y $not$libresoc.v:197673$13329_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198730$13518
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197674$13330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198730$13518_Y
+ connect \Y $not$libresoc.v:197674$13330_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198732$13520
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197676$13332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198732$13520_Y
+ connect \Y $not$libresoc.v:197676$13332_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198733$13521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197677$13333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198733$13521_Y
+ connect \Y $not$libresoc.v:197677$13333_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198737$13525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197681$13337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198737$13525_Y
+ connect \Y $not$libresoc.v:197681$13337_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198738$13526
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197682$13338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198738$13526_Y
+ connect \Y $not$libresoc.v:197682$13338_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198740$13528
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197684$13340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198740$13528_Y
+ connect \Y $not$libresoc.v:197684$13340_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198741$13529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197685$13341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198741$13529_Y
+ connect \Y $not$libresoc.v:197685$13341_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198746$13533
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197690$13345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198746$13533_Y
+ connect \Y $not$libresoc.v:197690$13345_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198747$13534
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197691$13346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198747$13534_Y
+ connect \Y $not$libresoc.v:197691$13346_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198749$13536
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197693$13348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198749$13536_Y
+ connect \Y $not$libresoc.v:197693$13348_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198750$13537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197694$13349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198750$13537_Y
+ connect \Y $not$libresoc.v:197694$13349_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
- cell $not $not$libresoc.v:198756$13543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ cell $not $not$libresoc.v:197700$13355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:198756$13543_Y
+ connect \Y $not$libresoc.v:197700$13355_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198757$13544
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197701$13356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198757$13544_Y
+ connect \Y $not$libresoc.v:197701$13356_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198759$13546
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197703$13358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198759$13546_Y
+ connect \Y $not$libresoc.v:197703$13358_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198761$13548
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197705$13360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198761$13548_Y
+ connect \Y $not$libresoc.v:197705$13360_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198762$13549
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197706$13361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198762$13549_Y
+ connect \Y $not$libresoc.v:197706$13361_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
- cell $not $not$libresoc.v:198767$13554
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ cell $not $not$libresoc.v:197711$13366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:198767$13554_Y
+ connect \Y $not$libresoc.v:197711$13366_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
- cell $not $not$libresoc.v:198768$13555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ cell $not $not$libresoc.v:197712$13367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:198768$13555_Y
+ connect \Y $not$libresoc.v:197712$13367_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:198777$13566
+ cell $not $not$libresoc.v:197721$13378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o_dly
- connect \Y $not$libresoc.v:198777$13566_Y
+ connect \Y $not$libresoc.v:197721$13378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63"
- cell $not $not$libresoc.v:198779$13568
+ cell $not $not$libresoc.v:197723$13380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_i_ok
- connect \Y $not$libresoc.v:198779$13568_Y
+ connect \Y $not$libresoc.v:197723$13380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63"
- cell $not $not$libresoc.v:198780$13569
+ cell $not $not$libresoc.v:197724$13381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \svstate_i_ok
- connect \Y $not$libresoc.v:198780$13569_Y
+ connect \Y $not$libresoc.v:197724$13381_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198782$13572
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197726$13384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198782$13572_Y
+ connect \Y $not$libresoc.v:197726$13384_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198783$13573
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197727$13385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198783$13573_Y
+ connect \Y $not$libresoc.v:197727$13385_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198787$13577
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197731$13389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198787$13577_Y
+ connect \Y $not$libresoc.v:197731$13389_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198788$13578
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197732$13390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198788$13578_Y
+ connect \Y $not$libresoc.v:197732$13390_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198793$13582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197737$13394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198793$13582_Y
+ connect \Y $not$libresoc.v:197737$13394_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
- cell $not $not$libresoc.v:198794$13583
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ cell $not $not$libresoc.v:197738$13395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198794$13583_Y
+ connect \Y $not$libresoc.v:197738$13395_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198798$13587
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197742$13399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:198798$13587_Y
+ connect \Y $not$libresoc.v:197742$13399_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
- cell $not $not$libresoc.v:198799$13588
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ cell $not $not$libresoc.v:197743$13400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:198799$13588_Y
+ connect \Y $not$libresoc.v:197743$13400_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
- cell $not $not$libresoc.v:198804$13592
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ cell $not $not$libresoc.v:197748$13404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:198804$13592_Y
+ connect \Y $not$libresoc.v:197748$13404_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
- cell $not $not$libresoc.v:198805$13593
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ cell $not $not$libresoc.v:197749$13405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:198805$13593_Y
+ connect \Y $not$libresoc.v:197749$13405_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
- cell $or $or$libresoc.v:198698$13488
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $or $or$libresoc.v:197642$13300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:198698$13488_Y
+ connect \Y $or$libresoc.v:197642$13300_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
- cell $or $or$libresoc.v:198700$13489
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ cell $or $or$libresoc.v:197644$13301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$120
connect \B \is_last
- connect \Y $or$libresoc.v:198700$13489_Y
+ connect \Y $or$libresoc.v:197644$13301_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
- cell $or $or$libresoc.v:198714$13503
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $or $or$libresoc.v:197658$13315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:198714$13503_Y
+ connect \Y $or$libresoc.v:197658$13315_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
- cell $or $or$libresoc.v:198716$13504
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ cell $or $or$libresoc.v:197660$13316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$154
connect \B \is_last
- connect \Y $or$libresoc.v:198716$13504_Y
+ connect \Y $or$libresoc.v:197660$13316_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
- cell $or $or$libresoc.v:198743$13531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $or $or$libresoc.v:197687$13343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:198743$13531_Y
+ connect \Y $or$libresoc.v:197687$13343_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
- cell $or $or$libresoc.v:198745$13532
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ cell $or $or$libresoc.v:197689$13344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$212
connect \B \is_last
- connect \Y $or$libresoc.v:198745$13532_Y
+ connect \Y $or$libresoc.v:197689$13344_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
- cell $or $or$libresoc.v:198774$13563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ cell $or $or$libresoc.v:197718$13375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:198774$13563_Y
+ connect \Y $or$libresoc.v:197718$13375_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
- cell $or $or$libresoc.v:198775$13564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ cell $or $or$libresoc.v:197719$13376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$28
connect \B \rst
- connect \Y $or$libresoc.v:198775$13564_Y
+ connect \Y $or$libresoc.v:197719$13376_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
- cell $or $or$libresoc.v:198790$13580
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $or $or$libresoc.v:197734$13392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:198790$13580_Y
+ connect \Y $or$libresoc.v:197734$13392_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
- cell $or $or$libresoc.v:198792$13581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ cell $or $or$libresoc.v:197736$13393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$62
connect \B \is_last
- connect \Y $or$libresoc.v:198792$13581_Y
+ connect \Y $or$libresoc.v:197736$13393_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
- cell $or $or$libresoc.v:198801$13590
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $or $or$libresoc.v:197745$13402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:198801$13590_Y
+ connect \Y $or$libresoc.v:197745$13402_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
- cell $or $or$libresoc.v:198803$13591
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ cell $or $or$libresoc.v:197747$13403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$84
connect \B \is_last
- connect \Y $or$libresoc.v:198803$13591_Y
+ connect \Y $or$libresoc.v:197747$13403_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:198765$13552
+ cell $pos $pos$libresoc.v:197709$13364
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
- connect \Y $pos$libresoc.v:198765$13552_Y
+ connect \Y $pos$libresoc.v:197709$13364_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:198769$13557
+ cell $pos $pos$libresoc.v:197713$13369
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:198769$13556_Y
- connect \Y $pos$libresoc.v:198769$13557_Y
+ connect \A $extend$libresoc.v:197713$13368_Y
+ connect \Y $pos$libresoc.v:197713$13369_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:198770$13559
+ cell $pos $pos$libresoc.v:197714$13371
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:198770$13558_Y
- connect \Y $pos$libresoc.v:198770$13559_Y
+ connect \A $extend$libresoc.v:197714$13370_Y
+ connect \Y $pos$libresoc.v:197714$13371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:198781$13571
+ cell $pos $pos$libresoc.v:197725$13383
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:198781$13570_Y
- connect \Y $pos$libresoc.v:198781$13571_Y
+ connect \A $extend$libresoc.v:197725$13382_Y
+ connect \Y $pos$libresoc.v:197725$13383_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:198736$13524
+ cell $reduce_or $reduce_or$libresoc.v:197680$13336
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$195
- connect \Y $reduce_or$libresoc.v:198736$13524_Y
+ connect \Y $reduce_or$libresoc.v:197680$13336_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:198753$13540
+ cell $reduce_or $reduce_or$libresoc.v:197697$13352
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$229
- connect \Y $reduce_or$libresoc.v:198753$13540_Y
+ connect \Y $reduce_or$libresoc.v:197697$13352_Y
end
- attribute \src "libresoc.v:198691.18-198691.41"
- cell $shr $shr$libresoc.v:198691$13481
+ attribute \src "libresoc.v:197635.18-197635.41"
+ cell $shr $shr$libresoc.v:197635$13293
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$103
- connect \Y $shr$libresoc.v:198691$13481_Y
+ connect \Y $shr$libresoc.v:197635$13293_Y
end
- attribute \src "libresoc.v:198808.18-198808.40"
- cell $shr $shr$libresoc.v:198808$13596
+ attribute \src "libresoc.v:197752.18-197752.40"
+ cell $shr $shr$libresoc.v:197752$13408
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$96
- connect \Y $shr$libresoc.v:198808$13596_Y
+ connect \Y $shr$libresoc.v:197752$13408_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002"
- cell $sub $sub$libresoc.v:198771$13560
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
+ cell $sub $sub$libresoc.v:197715$13372
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:198771$13560_Y
+ connect \Y $sub$libresoc.v:197715$13372_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
- cell $sub $sub$libresoc.v:198773$13562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
+ cell $sub $sub$libresoc.v:197717$13374
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:198773$13562_Y
+ connect \Y $sub$libresoc.v:197717$13374_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199017.8-199115.4"
+ attribute \src "libresoc.v:197961.8-198059.4"
cell \core \core
connect \bigendian_i \core_bigendian_i$10
connect \cia__data_o \core_cia__data_o
connect \wen$10 \core_wen$11
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199116.7-199147.4"
+ attribute \src "libresoc.v:198060.7-198091.4"
cell \dbg \dbg
connect \clk \clk
connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199148.8-199215.4"
+ attribute \src "libresoc.v:198092.8-198159.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199216.8-199232.4"
+ attribute \src "libresoc.v:198160.8-198176.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199233.8-199516.4"
+ attribute \src "libresoc.v:198177.8-198460.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199517.12-199531.4"
+ attribute \src "libresoc.v:198461.12-198475.4"
cell \xics_icp \xics_icp
connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \rst \rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199532.12-199545.4"
+ attribute \src "libresoc.v:198476.12-198489.4"
cell \xics_ics \xics_ics
connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \int_level_i \int_level_i
connect \rst \rst
end
- attribute \src "libresoc.v:196414.7-196414.20"
- process $proc$libresoc.v:196414$14180
+ attribute \src "libresoc.v:195358.7-195358.20"
+ process $proc$libresoc.v:195358$13992
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:196682.13-196682.33"
- process $proc$libresoc.v:196682$14181
+ attribute \src "libresoc.v:195626.13-195626.33"
+ process $proc$libresoc.v:195626$13993
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:196688.7-196688.35"
- process $proc$libresoc.v:196688$14182
+ attribute \src "libresoc.v:195632.7-195632.35"
+ process $proc$libresoc.v:195632$13994
assign { } { }
- assign $0\core_bigendian_i$10[0:0]$14183 1'0
+ assign $0\core_bigendian_i$10[0:0]$13995 1'0
sync always
sync init
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14183
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13995
end
- attribute \src "libresoc.v:196696.14-196696.55"
- process $proc$libresoc.v:196696$14184
+ attribute \src "libresoc.v:195640.14-195640.55"
+ process $proc$libresoc.v:195640$13996
assign { } { }
assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_cia $1\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:196700.13-196700.41"
- process $proc$libresoc.v:196700$14185
+ attribute \src "libresoc.v:195644.13-195644.41"
+ process $proc$libresoc.v:195644$13997
assign { } { }
assign $1\core_core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:196704.7-196704.37"
- process $proc$libresoc.v:196704$14186
+ attribute \src "libresoc.v:195648.7-195648.37"
+ process $proc$libresoc.v:195648$13998
assign { } { }
assign $1\core_core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:196708.13-196708.41"
- process $proc$libresoc.v:196708$14187
+ attribute \src "libresoc.v:195652.13-195652.41"
+ process $proc$libresoc.v:195652$13999
assign { } { }
assign $1\core_core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:196712.7-196712.42"
- process $proc$libresoc.v:196712$14188
+ attribute \src "libresoc.v:195656.7-195656.42"
+ process $proc$libresoc.v:195656$14000
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$14189 1'0
+ assign $0\core_core_core_exc_$signal[0:0]$14001 1'0
sync always
sync init
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14189
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14001
end
- attribute \src "libresoc.v:196714.7-196714.44"
- process $proc$libresoc.v:196714$14190
+ attribute \src "libresoc.v:195658.7-195658.44"
+ process $proc$libresoc.v:195658$14002
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$14191 1'0
+ assign $0\core_core_core_exc_$signal$3[0:0]$14003 1'0
sync always
sync init
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14191
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14003
end
- attribute \src "libresoc.v:196718.7-196718.44"
- process $proc$libresoc.v:196718$14192
+ attribute \src "libresoc.v:195662.7-195662.44"
+ process $proc$libresoc.v:195662$14004
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$14193 1'0
+ assign $0\core_core_core_exc_$signal$4[0:0]$14005 1'0
sync always
sync init
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14193
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14005
end
- attribute \src "libresoc.v:196722.7-196722.44"
- process $proc$libresoc.v:196722$14194
+ attribute \src "libresoc.v:195666.7-195666.44"
+ process $proc$libresoc.v:195666$14006
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$14195 1'0
+ assign $0\core_core_core_exc_$signal$5[0:0]$14007 1'0
sync always
sync init
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14195
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14007
end
- attribute \src "libresoc.v:196726.7-196726.44"
- process $proc$libresoc.v:196726$14196
+ attribute \src "libresoc.v:195670.7-195670.44"
+ process $proc$libresoc.v:195670$14008
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$14197 1'0
+ assign $0\core_core_core_exc_$signal$6[0:0]$14009 1'0
sync always
sync init
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14197
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14009
end
- attribute \src "libresoc.v:196730.7-196730.44"
- process $proc$libresoc.v:196730$14198
+ attribute \src "libresoc.v:195674.7-195674.44"
+ process $proc$libresoc.v:195674$14010
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$14199 1'0
+ assign $0\core_core_core_exc_$signal$7[0:0]$14011 1'0
sync always
sync init
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14199
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14011
end
- attribute \src "libresoc.v:196734.7-196734.44"
- process $proc$libresoc.v:196734$14200
+ attribute \src "libresoc.v:195678.7-195678.44"
+ process $proc$libresoc.v:195678$14012
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$14201 1'0
+ assign $0\core_core_core_exc_$signal$8[0:0]$14013 1'0
sync always
sync init
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14201
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14013
end
- attribute \src "libresoc.v:196738.7-196738.44"
- process $proc$libresoc.v:196738$14202
+ attribute \src "libresoc.v:195682.7-195682.44"
+ process $proc$libresoc.v:195682$14014
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$14203 1'0
+ assign $0\core_core_core_exc_$signal$9[0:0]$14015 1'0
sync always
sync init
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14203
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14015
end
- attribute \src "libresoc.v:196759.14-196759.47"
- process $proc$libresoc.v:196759$14204
+ attribute \src "libresoc.v:195703.14-195703.47"
+ process $proc$libresoc.v:195703$14016
assign { } { }
assign $1\core_core_core_fn_unit[13:0] 14'00000000000000
sync always
sync init
update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0]
end
- attribute \src "libresoc.v:196767.13-196767.46"
- process $proc$libresoc.v:196767$14205
+ attribute \src "libresoc.v:195711.13-195711.46"
+ process $proc$libresoc.v:195711$14017
assign { } { }
assign $1\core_core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_core_input_carry $1\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:196771.14-196771.41"
- process $proc$libresoc.v:196771$14206
+ attribute \src "libresoc.v:195715.14-195715.41"
+ process $proc$libresoc.v:195715$14018
assign { } { }
assign $1\core_core_core_insn[31:0] 0
sync always
sync init
update \core_core_core_insn $1\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:196850.13-196850.45"
- process $proc$libresoc.v:196850$14207
+ attribute \src "libresoc.v:195794.13-195794.45"
+ process $proc$libresoc.v:195794$14019
assign { } { }
assign $1\core_core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_core_insn_type $1\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:196854.7-196854.37"
- process $proc$libresoc.v:196854$14208
+ attribute \src "libresoc.v:195798.7-195798.37"
+ process $proc$libresoc.v:195798$14020
assign { } { }
assign $1\core_core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:196858.14-196858.55"
- process $proc$libresoc.v:196858$14209
+ attribute \src "libresoc.v:195802.14-195802.55"
+ process $proc$libresoc.v:195802$14021
assign { } { }
assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_msr $1\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:196862.7-196862.31"
- process $proc$libresoc.v:196862$14210
+ attribute \src "libresoc.v:195806.7-195806.31"
+ process $proc$libresoc.v:195806$14022
assign { } { }
assign $1\core_core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_core_oe $1\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:196866.7-196866.34"
- process $proc$libresoc.v:196866$14211
+ attribute \src "libresoc.v:195810.7-195810.34"
+ process $proc$libresoc.v:195810$14023
assign { } { }
assign $1\core_core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:196870.7-196870.31"
- process $proc$libresoc.v:196870$14212
+ attribute \src "libresoc.v:195814.7-195814.31"
+ process $proc$libresoc.v:195814$14024
assign { } { }
assign $1\core_core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_core_rc $1\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:196874.7-196874.34"
- process $proc$libresoc.v:196874$14213
+ attribute \src "libresoc.v:195818.7-195818.34"
+ process $proc$libresoc.v:195818$14025
assign { } { }
assign $1\core_core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:196878.14-196878.48"
- process $proc$libresoc.v:196878$14214
+ attribute \src "libresoc.v:195822.14-195822.48"
+ process $proc$libresoc.v:195822$14026
assign { } { }
assign $1\core_core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:196882.13-196882.44"
- process $proc$libresoc.v:196882$14215
+ attribute \src "libresoc.v:195826.13-195826.44"
+ process $proc$libresoc.v:195826$14027
assign { } { }
assign $1\core_core_core_traptype[7:0] 8'00000000
sync always
sync init
update \core_core_core_traptype $1\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:196886.13-196886.37"
- process $proc$libresoc.v:196886$14216
+ attribute \src "libresoc.v:195830.13-195830.37"
+ process $proc$libresoc.v:195830$14028
assign { } { }
assign $1\core_core_cr_in1[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in1 $1\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:196890.7-196890.33"
- process $proc$libresoc.v:196890$14217
+ attribute \src "libresoc.v:195834.7-195834.33"
+ process $proc$libresoc.v:195834$14029
assign { } { }
assign $1\core_core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:196894.13-196894.37"
- process $proc$libresoc.v:196894$14218
+ attribute \src "libresoc.v:195838.13-195838.37"
+ process $proc$libresoc.v:195838$14030
assign { } { }
assign $1\core_core_cr_in2[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in2 $1\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:196896.13-196896.41"
- process $proc$libresoc.v:196896$14219
+ attribute \src "libresoc.v:195840.13-195840.41"
+ process $proc$libresoc.v:195840$14031
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$14220 7'0000000
+ assign $0\core_core_cr_in2$1[6:0]$14032 7'0000000
sync always
sync init
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14220
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14032
end
- attribute \src "libresoc.v:196902.7-196902.33"
- process $proc$libresoc.v:196902$14221
+ attribute \src "libresoc.v:195846.7-195846.33"
+ process $proc$libresoc.v:195846$14033
assign { } { }
assign $1\core_core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:196904.7-196904.37"
- process $proc$libresoc.v:196904$14222
+ attribute \src "libresoc.v:195848.7-195848.37"
+ process $proc$libresoc.v:195848$14034
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$14223 1'0
+ assign $0\core_core_cr_in2_ok$2[0:0]$14035 1'0
sync always
sync init
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14223
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14035
end
- attribute \src "libresoc.v:196910.13-196910.37"
- process $proc$libresoc.v:196910$14224
+ attribute \src "libresoc.v:195854.13-195854.37"
+ process $proc$libresoc.v:195854$14036
assign { } { }
assign $1\core_core_cr_out[6:0] 7'0000000
sync always
sync init
update \core_core_cr_out $1\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:196914.7-196914.32"
- process $proc$libresoc.v:196914$14225
+ attribute \src "libresoc.v:195858.7-195858.32"
+ process $proc$libresoc.v:195858$14037
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:196918.13-196918.38"
- process $proc$libresoc.v:196918$14226
+ attribute \src "libresoc.v:195862.13-195862.38"
+ process $proc$libresoc.v:195862$14038
assign { } { }
assign $1\core_core_dststep[6:0] 7'0000000
sync always
sync init
update \core_core_dststep $1\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:196922.13-196922.33"
- process $proc$libresoc.v:196922$14227
+ attribute \src "libresoc.v:195866.13-195866.33"
+ process $proc$libresoc.v:195866$14039
assign { } { }
assign $1\core_core_ea[6:0] 7'0000000
sync always
sync init
update \core_core_ea $1\core_core_ea[6:0]
end
- attribute \src "libresoc.v:196926.13-196926.35"
- process $proc$libresoc.v:196926$14228
+ attribute \src "libresoc.v:195870.13-195870.35"
+ process $proc$libresoc.v:195870$14040
assign { } { }
assign $1\core_core_fast1[2:0] 3'000
sync always
sync init
update \core_core_fast1 $1\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:196930.7-196930.32"
- process $proc$libresoc.v:196930$14229
+ attribute \src "libresoc.v:195874.7-195874.32"
+ process $proc$libresoc.v:195874$14041
assign { } { }
assign $1\core_core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_core_fast1_ok $1\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:196934.13-196934.35"
- process $proc$libresoc.v:196934$14230
+ attribute \src "libresoc.v:195878.13-195878.35"
+ process $proc$libresoc.v:195878$14042
assign { } { }
assign $1\core_core_fast2[2:0] 3'000
sync always
sync init
update \core_core_fast2 $1\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:196938.7-196938.32"
- process $proc$libresoc.v:196938$14231
+ attribute \src "libresoc.v:195882.7-195882.32"
+ process $proc$libresoc.v:195882$14043
assign { } { }
assign $1\core_core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_core_fast2_ok $1\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:196942.13-196942.36"
- process $proc$libresoc.v:196942$14232
+ attribute \src "libresoc.v:195886.13-195886.36"
+ process $proc$libresoc.v:195886$14044
assign { } { }
assign $1\core_core_fasto1[2:0] 3'000
sync always
sync init
update \core_core_fasto1 $1\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:196946.13-196946.36"
- process $proc$libresoc.v:196946$14233
+ attribute \src "libresoc.v:195890.13-195890.36"
+ process $proc$libresoc.v:195890$14045
assign { } { }
assign $1\core_core_fasto2[2:0] 3'000
sync always
sync init
update \core_core_fasto2 $1\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:196950.7-196950.26"
- process $proc$libresoc.v:196950$14234
+ attribute \src "libresoc.v:195894.7-195894.26"
+ process $proc$libresoc.v:195894$14046
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:196954.13-196954.36"
- process $proc$libresoc.v:196954$14235
+ attribute \src "libresoc.v:195898.13-195898.36"
+ process $proc$libresoc.v:195898$14047
assign { } { }
assign $1\core_core_maxvl[6:0] 7'0000000
sync always
sync init
update \core_core_maxvl $1\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:196958.14-196958.49"
- process $proc$libresoc.v:196958$14236
+ attribute \src "libresoc.v:195902.14-195902.49"
+ process $proc$libresoc.v:195902$14048
assign { } { }
assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_pc $1\core_core_pc[63:0]
end
- attribute \src "libresoc.v:196962.13-196962.35"
- process $proc$libresoc.v:196962$14237
+ attribute \src "libresoc.v:195906.13-195906.35"
+ process $proc$libresoc.v:195906$14049
assign { } { }
assign $1\core_core_reg1[6:0] 7'0000000
sync always
sync init
update \core_core_reg1 $1\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:196966.7-196966.31"
- process $proc$libresoc.v:196966$14238
+ attribute \src "libresoc.v:195910.7-195910.31"
+ process $proc$libresoc.v:195910$14050
assign { } { }
assign $1\core_core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_core_reg1_ok $1\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:196970.13-196970.35"
- process $proc$libresoc.v:196970$14239
+ attribute \src "libresoc.v:195914.13-195914.35"
+ process $proc$libresoc.v:195914$14051
assign { } { }
assign $1\core_core_reg2[6:0] 7'0000000
sync always
sync init
update \core_core_reg2 $1\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:196974.7-196974.31"
- process $proc$libresoc.v:196974$14240
+ attribute \src "libresoc.v:195918.7-195918.31"
+ process $proc$libresoc.v:195918$14052
assign { } { }
assign $1\core_core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_core_reg2_ok $1\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:196978.13-196978.35"
- process $proc$libresoc.v:196978$14241
+ attribute \src "libresoc.v:195922.13-195922.35"
+ process $proc$libresoc.v:195922$14053
assign { } { }
assign $1\core_core_reg3[6:0] 7'0000000
sync always
sync init
update \core_core_reg3 $1\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:196982.7-196982.31"
- process $proc$libresoc.v:196982$14242
+ attribute \src "libresoc.v:195926.7-195926.31"
+ process $proc$libresoc.v:195926$14054
assign { } { }
assign $1\core_core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_core_reg3_ok $1\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:196986.13-196986.35"
- process $proc$libresoc.v:196986$14243
+ attribute \src "libresoc.v:195930.13-195930.35"
+ process $proc$libresoc.v:195930$14055
assign { } { }
assign $1\core_core_rego[6:0] 7'0000000
sync always
sync init
update \core_core_rego $1\core_core_rego[6:0]
end
- attribute \src "libresoc.v:197104.13-197104.37"
- process $proc$libresoc.v:197104$14244
+ attribute \src "libresoc.v:196048.13-196048.37"
+ process $proc$libresoc.v:196048$14056
assign { } { }
assign $1\core_core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_core_spr1 $1\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:197108.7-197108.31"
- process $proc$libresoc.v:197108$14245
+ attribute \src "libresoc.v:196052.7-196052.31"
+ process $proc$libresoc.v:196052$14057
assign { } { }
assign $1\core_core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_core_spr1_ok $1\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:197226.13-197226.37"
- process $proc$libresoc.v:197226$14246
+ attribute \src "libresoc.v:196170.13-196170.37"
+ process $proc$libresoc.v:196170$14058
assign { } { }
assign $1\core_core_spro[9:0] 10'0000000000
sync always
sync init
update \core_core_spro $1\core_core_spro[9:0]
end
- attribute \src "libresoc.v:197230.13-197230.38"
- process $proc$libresoc.v:197230$14247
+ attribute \src "libresoc.v:196174.13-196174.38"
+ process $proc$libresoc.v:196174$14059
assign { } { }
assign $1\core_core_srcstep[6:0] 7'0000000
sync always
sync init
update \core_core_srcstep $1\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:197234.13-197234.35"
- process $proc$libresoc.v:197234$14248
+ attribute \src "libresoc.v:196178.13-196178.35"
+ process $proc$libresoc.v:196178$14060
assign { } { }
assign $1\core_core_subvl[1:0] 2'00
sync always
sync init
update \core_core_subvl $1\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:197238.13-197238.36"
- process $proc$libresoc.v:197238$14249
+ attribute \src "libresoc.v:196182.13-196182.36"
+ process $proc$libresoc.v:196182$14061
assign { } { }
assign $1\core_core_svstep[1:0] 2'00
sync always
sync init
update \core_core_svstep $1\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:197244.13-197244.33"
- process $proc$libresoc.v:197244$14250
+ attribute \src "libresoc.v:196188.13-196188.33"
+ process $proc$libresoc.v:196188$14062
assign { } { }
assign $1\core_core_vl[6:0] 7'0000000
sync always
sync init
update \core_core_vl $1\core_core_vl[6:0]
end
- attribute \src "libresoc.v:197248.13-197248.36"
- process $proc$libresoc.v:197248$14251
+ attribute \src "libresoc.v:196192.13-196192.36"
+ process $proc$libresoc.v:196192$14063
assign { } { }
assign $1\core_core_xer_in[2:0] 3'000
sync always
sync init
update \core_core_xer_in $1\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:197256.7-197256.28"
- process $proc$libresoc.v:197256$14252
+ attribute \src "libresoc.v:196200.7-196200.28"
+ process $proc$libresoc.v:196200$14064
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:197272.14-197272.45"
- process $proc$libresoc.v:197272$14253
+ attribute \src "libresoc.v:196216.14-196216.45"
+ process $proc$libresoc.v:196216$14065
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:197282.7-197282.24"
- process $proc$libresoc.v:197282$14254
+ attribute \src "libresoc.v:196226.7-196226.24"
+ process $proc$libresoc.v:196226$14066
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:197286.7-197286.23"
- process $proc$libresoc.v:197286$14255
+ attribute \src "libresoc.v:196230.7-196230.23"
+ process $proc$libresoc.v:196230$14067
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:197290.7-197290.28"
- process $proc$libresoc.v:197290$14256
+ attribute \src "libresoc.v:196234.7-196234.28"
+ process $proc$libresoc.v:196234$14068
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:197294.7-197294.28"
- process $proc$libresoc.v:197294$14257
+ attribute \src "libresoc.v:196238.7-196238.28"
+ process $proc$libresoc.v:196238$14069
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:197322.14-197322.45"
- process $proc$libresoc.v:197322$14258
+ attribute \src "libresoc.v:196266.14-196266.45"
+ process $proc$libresoc.v:196266$14070
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:197330.14-197330.37"
- process $proc$libresoc.v:197330$14259
+ attribute \src "libresoc.v:196274.14-196274.37"
+ process $proc$libresoc.v:196274$14071
assign { } { }
assign $1\core_raw_insn_i[31:0] 0
sync always
sync init
update \core_raw_insn_i $1\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:197334.7-197334.26"
- process $proc$libresoc.v:197334$14260
+ attribute \src "libresoc.v:196278.7-196278.26"
+ process $proc$libresoc.v:196278$14072
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:197338.7-197338.26"
- process $proc$libresoc.v:197338$14261
+ attribute \src "libresoc.v:196282.7-196282.26"
+ process $proc$libresoc.v:196282$14073
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:197350.7-197350.26"
- process $proc$libresoc.v:197350$14262
+ attribute \src "libresoc.v:196294.7-196294.26"
+ process $proc$libresoc.v:196294$14074
assign { } { }
assign $1\core_sv_a_nz[0:0] 1'0
sync always
sync init
update \core_sv_a_nz $1\core_sv_a_nz[0:0]
end
- attribute \src "libresoc.v:197360.7-197360.26"
- process $proc$libresoc.v:197360$14263
+ attribute \src "libresoc.v:196304.7-196304.26"
+ process $proc$libresoc.v:196304$14075
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:197366.7-197366.30"
- process $proc$libresoc.v:197366$14264
+ attribute \src "libresoc.v:196310.7-196310.30"
+ process $proc$libresoc.v:196310$14076
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:197372.13-197372.36"
- process $proc$libresoc.v:197372$14265
+ attribute \src "libresoc.v:196316.13-196316.36"
+ process $proc$libresoc.v:196316$14077
assign { } { }
assign $1\cur_cur_dststep[6:0] 7'0000000
sync always
sync init
update \cur_cur_dststep $1\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:197376.13-197376.34"
- process $proc$libresoc.v:197376$14266
+ attribute \src "libresoc.v:196320.13-196320.34"
+ process $proc$libresoc.v:196320$14078
assign { } { }
assign $1\cur_cur_maxvl[6:0] 7'0000000
sync always
sync init
update \cur_cur_maxvl $1\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:197380.13-197380.36"
- process $proc$libresoc.v:197380$14267
+ attribute \src "libresoc.v:196324.13-196324.36"
+ process $proc$libresoc.v:196324$14079
assign { } { }
assign $1\cur_cur_srcstep[6:0] 7'0000000
sync always
sync init
update \cur_cur_srcstep $1\cur_cur_srcstep[6:0]
end
- attribute \src "libresoc.v:197384.13-197384.33"
- process $proc$libresoc.v:197384$14268
+ attribute \src "libresoc.v:196328.13-196328.33"
+ process $proc$libresoc.v:196328$14080
assign { } { }
assign $1\cur_cur_subvl[1:0] 2'00
sync always
sync init
update \cur_cur_subvl $1\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:197388.13-197388.34"
- process $proc$libresoc.v:197388$14269
+ attribute \src "libresoc.v:196332.13-196332.34"
+ process $proc$libresoc.v:196332$14081
assign { } { }
assign $1\cur_cur_svstep[1:0] 2'00
sync always
sync init
update \cur_cur_svstep $1\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:197392.13-197392.31"
- process $proc$libresoc.v:197392$14270
+ attribute \src "libresoc.v:196336.13-196336.31"
+ process $proc$libresoc.v:196336$14082
assign { } { }
assign $1\cur_cur_vl[6:0] 7'0000000
sync always
sync init
update \cur_cur_vl $1\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:197396.7-197396.24"
- process $proc$libresoc.v:197396$14271
+ attribute \src "libresoc.v:196340.7-196340.24"
+ process $proc$libresoc.v:196340$14083
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:197400.7-197400.25"
- process $proc$libresoc.v:197400$14272
+ attribute \src "libresoc.v:196344.7-196344.25"
+ process $proc$libresoc.v:196344$14084
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:197404.7-197404.25"
- process $proc$libresoc.v:197404$14273
+ attribute \src "libresoc.v:196348.7-196348.25"
+ process $proc$libresoc.v:196348$14085
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:197452.13-197452.34"
- process $proc$libresoc.v:197452$14274
+ attribute \src "libresoc.v:196396.13-196396.34"
+ process $proc$libresoc.v:196396$14086
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:197456.14-197456.48"
- process $proc$libresoc.v:197456$14275
+ attribute \src "libresoc.v:196400.14-196400.48"
+ process $proc$libresoc.v:196400$14087
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:197462.7-197462.27"
- process $proc$libresoc.v:197462$14276
+ attribute \src "libresoc.v:196406.7-196406.27"
+ process $proc$libresoc.v:196406$14088
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:197466.7-197466.26"
- process $proc$libresoc.v:197466$14277
+ attribute \src "libresoc.v:196410.7-196410.26"
+ process $proc$libresoc.v:196410$14089
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:197520.14-197520.49"
- process $proc$libresoc.v:197520$14278
+ attribute \src "libresoc.v:196464.14-196464.49"
+ process $proc$libresoc.v:196464$14090
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:197524.7-197524.27"
- process $proc$libresoc.v:197524$14279
+ attribute \src "libresoc.v:196468.7-196468.27"
+ process $proc$libresoc.v:196468$14091
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:197528.14-197528.49"
- process $proc$libresoc.v:197528$14280
+ attribute \src "libresoc.v:196472.14-196472.49"
+ process $proc$libresoc.v:196472$14092
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:197532.14-197532.48"
- process $proc$libresoc.v:197532$14281
+ attribute \src "libresoc.v:196476.14-196476.48"
+ process $proc$libresoc.v:196476$14093
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:197684.14-197684.40"
- process $proc$libresoc.v:197684$14282
+ attribute \src "libresoc.v:196628.14-196628.40"
+ process $proc$libresoc.v:196628$14094
assign { } { }
assign $1\dec2_raw_opcode_in[31:0] 0
sync always
sync init
update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:197954.13-197954.25"
- process $proc$libresoc.v:197954$14283
+ attribute \src "libresoc.v:196898.13-196898.25"
+ process $proc$libresoc.v:196898$14095
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:197970.7-197970.28"
- process $proc$libresoc.v:197970$14284
+ attribute \src "libresoc.v:196914.7-196914.28"
+ process $proc$libresoc.v:196914$14096
assign { } { }
assign $1\exec_fsm_state[0:0] 1'0
sync always
sync init
update \exec_fsm_state $1\exec_fsm_state[0:0]
end
- attribute \src "libresoc.v:197982.13-197982.35"
- process $proc$libresoc.v:197982$14285
+ attribute \src "libresoc.v:196926.13-196926.35"
+ process $proc$libresoc.v:196926$14097
assign { } { }
assign $1\fetch_fsm_state[1:0] 2'00
sync always
sync init
update \fetch_fsm_state $1\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:197994.13-197994.29"
- process $proc$libresoc.v:197994$14286
+ attribute \src "libresoc.v:196938.13-196938.29"
+ process $proc$libresoc.v:196938$14098
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:198254.13-198254.35"
- process $proc$libresoc.v:198254$14287
+ attribute \src "libresoc.v:197198.13-197198.35"
+ process $proc$libresoc.v:197198$14099
assign { } { }
assign $1\issue_fsm_state[2:0] 3'000
sync always
sync init
update \issue_fsm_state $1\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:198258.7-198258.30"
- process $proc$libresoc.v:198258$14288
+ attribute \src "libresoc.v:197202.7-197202.30"
+ process $proc$libresoc.v:197202$14100
assign { } { }
assign $1\jtag_dmi0__ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:198266.14-198266.52"
- process $proc$libresoc.v:198266$14289
+ attribute \src "libresoc.v:197210.14-197210.52"
+ process $proc$libresoc.v:197210$14101
assign { } { }
assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:198306.7-198306.22"
- process $proc$libresoc.v:198306$14290
+ attribute \src "libresoc.v:197250.7-197250.22"
+ process $proc$libresoc.v:197250$14102
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:198346.14-198346.40"
- process $proc$libresoc.v:198346$14291
+ attribute \src "libresoc.v:197290.14-197290.40"
+ process $proc$libresoc.v:197290$14103
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:198352.7-198352.24"
- process $proc$libresoc.v:198352$14292
+ attribute \src "libresoc.v:197296.7-197296.24"
+ process $proc$libresoc.v:197296$14104
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:198362.7-198362.25"
- process $proc$libresoc.v:198362$14293
+ attribute \src "libresoc.v:197306.7-197306.25"
+ process $proc$libresoc.v:197306$14105
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:198662.7-198662.24"
- process $proc$libresoc.v:198662$14294
+ attribute \src "libresoc.v:197606.7-197606.24"
+ process $proc$libresoc.v:197606$14106
assign { } { }
assign $1\sv_changed[0:0] 1'0
sync always
sync init
update \sv_changed $1\sv_changed[0:0]
end
- attribute \src "libresoc.v:198672.7-198672.30"
- process $proc$libresoc.v:198672$14295
+ attribute \src "libresoc.v:197616.7-197616.30"
+ process $proc$libresoc.v:197616$14107
assign { } { }
assign $1\svstate_ok_delay[0:0] 1'0
sync always
sync init
update \svstate_ok_delay $1\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:198809.3-198810.41"
- process $proc$libresoc.v:198809$13597
+ attribute \src "libresoc.v:197753.3-197754.41"
+ process $proc$libresoc.v:197753$13409
assign { } { }
assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
sync posedge \clk
update \dec2_cur_dec $0\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:198811.3-198812.41"
- process $proc$libresoc.v:198811$13598
+ attribute \src "libresoc.v:197755.3-197756.41"
+ process $proc$libresoc.v:197755$13410
assign { } { }
assign $0\core_core_pc[63:0] \core_core_pc$next
sync posedge \clk
update \core_core_pc $0\core_core_pc[63:0]
end
- attribute \src "libresoc.v:198813.3-198814.49"
- process $proc$libresoc.v:198813$13599
+ attribute \src "libresoc.v:197757.3-197758.49"
+ process $proc$libresoc.v:197757$13411
assign { } { }
assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
sync posedge \clk
update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:198815.3-198816.39"
- process $proc$libresoc.v:198815$13600
+ attribute \src "libresoc.v:197759.3-197760.39"
+ process $proc$libresoc.v:197759$13412
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
sync posedge \clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:198817.3-198818.41"
- process $proc$libresoc.v:198817$13601
+ attribute \src "libresoc.v:197761.3-197762.41"
+ process $proc$libresoc.v:197761$13413
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
sync posedge \clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:198819.3-198820.43"
- process $proc$libresoc.v:198819$13602
+ attribute \src "libresoc.v:197763.3-197764.43"
+ process $proc$libresoc.v:197763$13414
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
sync posedge \clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:198821.3-198822.45"
- process $proc$libresoc.v:198821$13603
+ attribute \src "libresoc.v:197765.3-197766.45"
+ process $proc$libresoc.v:197765$13415
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
sync posedge \clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:198823.3-198824.33"
- process $proc$libresoc.v:198823$13604
+ attribute \src "libresoc.v:197767.3-197768.33"
+ process $proc$libresoc.v:197767$13416
assign { } { }
assign $0\core_msr[63:0] \core_msr$next
sync posedge \clk
update \core_msr $0\core_msr[63:0]
end
- attribute \src "libresoc.v:198825.3-198826.35"
- process $proc$libresoc.v:198825$13605
+ attribute \src "libresoc.v:197769.3-197770.35"
+ process $proc$libresoc.v:197769$13417
assign { } { }
assign $0\core_eint[0:0] \core_eint$next
sync posedge \clk
update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:198827.3-198828.33"
- process $proc$libresoc.v:198827$13606
+ attribute \src "libresoc.v:197771.3-197772.33"
+ process $proc$libresoc.v:197771$13418
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
sync posedge \clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:198829.3-198830.49"
- process $proc$libresoc.v:198829$13607
+ attribute \src "libresoc.v:197773.3-197774.49"
+ process $proc$libresoc.v:197773$13419
assign { } { }
assign $0\core_core_svstep[1:0] \core_core_svstep$next
sync posedge \clk
update \core_core_svstep $0\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:198831.3-198832.47"
- process $proc$libresoc.v:198831$13608
+ attribute \src "libresoc.v:197775.3-197776.47"
+ process $proc$libresoc.v:197775$13420
assign { } { }
assign $0\core_core_subvl[1:0] \core_core_subvl$next
sync posedge \clk
update \core_core_subvl $0\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:198833.3-198834.51"
- process $proc$libresoc.v:198833$13609
+ attribute \src "libresoc.v:197777.3-197778.51"
+ process $proc$libresoc.v:197777$13421
assign { } { }
assign $0\core_core_dststep[6:0] \core_core_dststep$next
sync posedge \clk
update \core_core_dststep $0\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:198835.3-198836.51"
- process $proc$libresoc.v:198835$13610
+ attribute \src "libresoc.v:197779.3-197780.51"
+ process $proc$libresoc.v:197779$13422
assign { } { }
assign $0\core_core_srcstep[6:0] \core_core_srcstep$next
sync posedge \clk
update \core_core_srcstep $0\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:198837.3-198838.41"
- process $proc$libresoc.v:198837$13611
+ attribute \src "libresoc.v:197781.3-197782.41"
+ process $proc$libresoc.v:197781$13423
assign { } { }
assign $0\core_core_vl[6:0] \core_core_vl$next
sync posedge \clk
update \core_core_vl $0\core_core_vl[6:0]
end
- attribute \src "libresoc.v:198839.3-198840.47"
- process $proc$libresoc.v:198839$13612
+ attribute \src "libresoc.v:197783.3-197784.47"
+ process $proc$libresoc.v:197783$13424
assign { } { }
assign $0\core_core_maxvl[6:0] \core_core_maxvl$next
sync posedge \clk
update \core_core_maxvl $0\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:198841.3-198842.35"
- process $proc$libresoc.v:198841$13613
+ attribute \src "libresoc.v:197785.3-197786.35"
+ process $proc$libresoc.v:197785$13425
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:198843.3-198844.41"
- process $proc$libresoc.v:198843$13614
+ attribute \src "libresoc.v:197787.3-197788.41"
+ process $proc$libresoc.v:197787$13426
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
sync posedge \clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:198845.3-198846.45"
- process $proc$libresoc.v:198845$13615
+ attribute \src "libresoc.v:197789.3-197790.45"
+ process $proc$libresoc.v:197789$13427
assign { } { }
assign $0\core_core_rego[6:0] \core_core_rego$next
sync posedge \clk
update \core_core_rego $0\core_core_rego[6:0]
end
- attribute \src "libresoc.v:198847.3-198848.41"
- process $proc$libresoc.v:198847$13616
+ attribute \src "libresoc.v:197791.3-197792.41"
+ process $proc$libresoc.v:197791$13428
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
sync posedge \clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:198849.3-198850.41"
- process $proc$libresoc.v:198849$13617
+ attribute \src "libresoc.v:197793.3-197794.41"
+ process $proc$libresoc.v:197793$13429
assign { } { }
assign $0\core_core_ea[6:0] \core_core_ea$next
sync posedge \clk
update \core_core_ea $0\core_core_ea[6:0]
end
- attribute \src "libresoc.v:198851.3-198852.37"
- process $proc$libresoc.v:198851$13618
+ attribute \src "libresoc.v:197795.3-197796.37"
+ process $proc$libresoc.v:197795$13430
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
sync posedge \clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:198853.3-198854.45"
- process $proc$libresoc.v:198853$13619
+ attribute \src "libresoc.v:197797.3-197798.45"
+ process $proc$libresoc.v:197797$13431
assign { } { }
assign $0\core_core_reg1[6:0] \core_core_reg1$next
sync posedge \clk
update \core_core_reg1 $0\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:198855.3-198856.51"
- process $proc$libresoc.v:198855$13620
+ attribute \src "libresoc.v:197799.3-197800.51"
+ process $proc$libresoc.v:197799$13432
assign { } { }
assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next
sync posedge \clk
update \core_core_reg1_ok $0\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:198857.3-198858.45"
- process $proc$libresoc.v:198857$13621
+ attribute \src "libresoc.v:197801.3-197802.45"
+ process $proc$libresoc.v:197801$13433
assign { } { }
assign $0\core_core_reg2[6:0] \core_core_reg2$next
sync posedge \clk
update \core_core_reg2 $0\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:198859.3-198860.51"
- process $proc$libresoc.v:198859$13622
+ attribute \src "libresoc.v:197803.3-197804.51"
+ process $proc$libresoc.v:197803$13434
assign { } { }
assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next
sync posedge \clk
update \core_core_reg2_ok $0\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:198861.3-198862.45"
- process $proc$libresoc.v:198861$13623
+ attribute \src "libresoc.v:197805.3-197806.45"
+ process $proc$libresoc.v:197805$13435
assign { } { }
assign $0\core_core_reg3[6:0] \core_core_reg3$next
sync posedge \clk
update \core_core_reg3 $0\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:198863.3-198864.39"
- process $proc$libresoc.v:198863$13624
+ attribute \src "libresoc.v:197807.3-197808.39"
+ process $proc$libresoc.v:197807$13436
assign { } { }
assign $0\d_xer_delay[0:0] \d_xer_delay$next
sync posedge \clk
update \d_xer_delay $0\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:198865.3-198866.51"
- process $proc$libresoc.v:198865$13625
+ attribute \src "libresoc.v:197809.3-197810.51"
+ process $proc$libresoc.v:197809$13437
assign { } { }
assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next
sync posedge \clk
update \core_core_reg3_ok $0\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:198867.3-198868.45"
- process $proc$libresoc.v:198867$13626
+ attribute \src "libresoc.v:197811.3-197812.45"
+ process $proc$libresoc.v:197811$13438
assign { } { }
assign $0\core_core_spro[9:0] \core_core_spro$next
sync posedge \clk
update \core_core_spro $0\core_core_spro[9:0]
end
- attribute \src "libresoc.v:198869.3-198870.41"
- process $proc$libresoc.v:198869$13627
+ attribute \src "libresoc.v:197813.3-197814.41"
+ process $proc$libresoc.v:197813$13439
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
sync posedge \clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:198871.3-198872.45"
- process $proc$libresoc.v:198871$13628
+ attribute \src "libresoc.v:197815.3-197816.45"
+ process $proc$libresoc.v:197815$13440
assign { } { }
assign $0\core_core_spr1[9:0] \core_core_spr1$next
sync posedge \clk
update \core_core_spr1 $0\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:198873.3-198874.51"
- process $proc$libresoc.v:198873$13629
+ attribute \src "libresoc.v:197817.3-197818.51"
+ process $proc$libresoc.v:197817$13441
assign { } { }
assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next
sync posedge \clk
update \core_core_spr1_ok $0\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:198875.3-198876.49"
- process $proc$libresoc.v:198875$13630
+ attribute \src "libresoc.v:197819.3-197820.49"
+ process $proc$libresoc.v:197819$13442
assign { } { }
assign $0\core_core_xer_in[2:0] \core_core_xer_in$next
sync posedge \clk
update \core_core_xer_in $0\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:198877.3-198878.41"
- process $proc$libresoc.v:198877$13631
+ attribute \src "libresoc.v:197821.3-197822.41"
+ process $proc$libresoc.v:197821$13443
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
sync posedge \clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:198879.3-198880.47"
- process $proc$libresoc.v:198879$13632
+ attribute \src "libresoc.v:197823.3-197824.47"
+ process $proc$libresoc.v:197823$13444
assign { } { }
assign $0\core_core_fast1[2:0] \core_core_fast1$next
sync posedge \clk
update \core_core_fast1 $0\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:198881.3-198882.53"
- process $proc$libresoc.v:198881$13633
+ attribute \src "libresoc.v:197825.3-197826.53"
+ process $proc$libresoc.v:197825$13445
assign { } { }
assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next
sync posedge \clk
update \core_core_fast1_ok $0\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:198883.3-198884.47"
- process $proc$libresoc.v:198883$13634
+ attribute \src "libresoc.v:197827.3-197828.47"
+ process $proc$libresoc.v:197827$13446
assign { } { }
assign $0\core_core_fast2[2:0] \core_core_fast2$next
sync posedge \clk
update \core_core_fast2 $0\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:198885.3-198886.37"
- process $proc$libresoc.v:198885$13635
+ attribute \src "libresoc.v:197829.3-197830.37"
+ process $proc$libresoc.v:197829$13447
assign { } { }
assign $0\d_cr_delay[0:0] \d_cr_delay$next
sync posedge \clk
update \d_cr_delay $0\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:198887.3-198888.53"
- process $proc$libresoc.v:198887$13636
+ attribute \src "libresoc.v:197831.3-197832.53"
+ process $proc$libresoc.v:197831$13448
assign { } { }
assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next
sync posedge \clk
update \core_core_fast2_ok $0\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:198889.3-198890.49"
- process $proc$libresoc.v:198889$13637
+ attribute \src "libresoc.v:197833.3-197834.49"
+ process $proc$libresoc.v:197833$13449
assign { } { }
assign $0\core_core_fasto1[2:0] \core_core_fasto1$next
sync posedge \clk
update \core_core_fasto1 $0\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:198891.3-198892.45"
- process $proc$libresoc.v:198891$13638
+ attribute \src "libresoc.v:197835.3-197836.45"
+ process $proc$libresoc.v:197835$13450
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
sync posedge \clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:198893.3-198894.49"
- process $proc$libresoc.v:198893$13639
+ attribute \src "libresoc.v:197837.3-197838.49"
+ process $proc$libresoc.v:197837$13451
assign { } { }
assign $0\core_core_fasto2[2:0] \core_core_fasto2$next
sync posedge \clk
update \core_core_fasto2 $0\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:198895.3-198896.45"
- process $proc$libresoc.v:198895$13640
+ attribute \src "libresoc.v:197839.3-197840.45"
+ process $proc$libresoc.v:197839$13452
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
sync posedge \clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:198897.3-198898.49"
- process $proc$libresoc.v:198897$13641
+ attribute \src "libresoc.v:197841.3-197842.49"
+ process $proc$libresoc.v:197841$13453
assign { } { }
assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next
sync posedge \clk
update \core_core_cr_in1 $0\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:198899.3-198900.55"
- process $proc$libresoc.v:198899$13642
+ attribute \src "libresoc.v:197843.3-197844.55"
+ process $proc$libresoc.v:197843$13454
assign { } { }
assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next
sync posedge \clk
update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:198901.3-198902.49"
- process $proc$libresoc.v:198901$13643
+ attribute \src "libresoc.v:197845.3-197846.49"
+ process $proc$libresoc.v:197845$13455
assign { } { }
assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next
sync posedge \clk
update \core_core_cr_in2 $0\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:198903.3-198904.55"
- process $proc$libresoc.v:198903$13644
+ attribute \src "libresoc.v:197847.3-197848.55"
+ process $proc$libresoc.v:197847$13456
assign { } { }
assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next
sync posedge \clk
update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:198905.3-198906.55"
- process $proc$libresoc.v:198905$13645
+ attribute \src "libresoc.v:197849.3-197850.55"
+ process $proc$libresoc.v:197849$13457
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$13646 \core_core_cr_in2$1$next
+ assign $0\core_core_cr_in2$1[6:0]$13458 \core_core_cr_in2$1$next
sync posedge \clk
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13646
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13458
end
- attribute \src "libresoc.v:198907.3-198908.39"
- process $proc$libresoc.v:198907$13647
+ attribute \src "libresoc.v:197851.3-197852.39"
+ process $proc$libresoc.v:197851$13459
assign { } { }
assign $0\d_reg_delay[0:0] \d_reg_delay$next
sync posedge \clk
update \d_reg_delay $0\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:198909.3-198910.61"
- process $proc$libresoc.v:198909$13648
+ attribute \src "libresoc.v:197853.3-197854.61"
+ process $proc$libresoc.v:197853$13460
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$13649 \core_core_cr_in2_ok$2$next
+ assign $0\core_core_cr_in2_ok$2[0:0]$13461 \core_core_cr_in2_ok$2$next
sync posedge \clk
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13649
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13461
end
- attribute \src "libresoc.v:198911.3-198912.49"
- process $proc$libresoc.v:198911$13650
+ attribute \src "libresoc.v:197855.3-197856.49"
+ process $proc$libresoc.v:197855$13462
assign { } { }
assign $0\core_core_cr_out[6:0] \core_core_cr_out$next
sync posedge \clk
update \core_core_cr_out $0\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:198913.3-198914.45"
- process $proc$libresoc.v:198913$13651
+ attribute \src "libresoc.v:197857.3-197858.45"
+ process $proc$libresoc.v:197857$13463
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
sync posedge \clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:198915.3-198916.53"
- process $proc$libresoc.v:198915$13652
+ attribute \src "libresoc.v:197859.3-197860.53"
+ process $proc$libresoc.v:197859$13464
assign { } { }
assign $0\core_core_core_msr[63:0] \core_core_core_msr$next
sync posedge \clk
update \core_core_core_msr $0\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:198917.3-198918.53"
- process $proc$libresoc.v:198917$13653
+ attribute \src "libresoc.v:197861.3-197862.53"
+ process $proc$libresoc.v:197861$13465
assign { } { }
assign $0\core_core_core_cia[63:0] \core_core_core_cia$next
sync posedge \clk
update \core_core_core_cia $0\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:198919.3-198920.55"
- process $proc$libresoc.v:198919$13654
+ attribute \src "libresoc.v:197863.3-197864.55"
+ process $proc$libresoc.v:197863$13466
assign { } { }
assign $0\core_core_core_insn[31:0] \core_core_core_insn$next
sync posedge \clk
update \core_core_core_insn $0\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:198921.3-198922.65"
- process $proc$libresoc.v:198921$13655
+ attribute \src "libresoc.v:197865.3-197866.65"
+ process $proc$libresoc.v:197865$13467
assign { } { }
assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next
sync posedge \clk
update \core_core_core_insn_type $0\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:198923.3-198924.61"
- process $proc$libresoc.v:198923$13656
+ attribute \src "libresoc.v:197867.3-197868.61"
+ process $proc$libresoc.v:197867$13468
assign { } { }
assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next
sync posedge \clk
update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0]
end
- attribute \src "libresoc.v:198925.3-198926.41"
- process $proc$libresoc.v:198925$13657
+ attribute \src "libresoc.v:197869.3-197870.41"
+ process $proc$libresoc.v:197869$13469
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
sync posedge \clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:198927.3-198928.51"
- process $proc$libresoc.v:198927$13658
+ attribute \src "libresoc.v:197871.3-197872.51"
+ process $proc$libresoc.v:197871$13470
assign { } { }
assign $0\core_core_core_rc[0:0] \core_core_core_rc$next
sync posedge \clk
update \core_core_core_rc $0\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:198929.3-198930.45"
- process $proc$libresoc.v:198929$13659
+ attribute \src "libresoc.v:197873.3-197874.45"
+ process $proc$libresoc.v:197873$13471
assign { } { }
assign $0\exec_fsm_state[0:0] \exec_fsm_state$next
sync posedge \clk
update \exec_fsm_state $0\exec_fsm_state[0:0]
end
- attribute \src "libresoc.v:198931.3-198932.57"
- process $proc$libresoc.v:198931$13660
+ attribute \src "libresoc.v:197875.3-197876.57"
+ process $proc$libresoc.v:197875$13472
assign { } { }
assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next
sync posedge \clk
update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:198933.3-198934.51"
- process $proc$libresoc.v:198933$13661
+ attribute \src "libresoc.v:197877.3-197878.51"
+ process $proc$libresoc.v:197877$13473
assign { } { }
assign $0\core_core_core_oe[0:0] \core_core_core_oe$next
sync posedge \clk
update \core_core_core_oe $0\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:198935.3-198936.57"
- process $proc$libresoc.v:198935$13662
+ attribute \src "libresoc.v:197879.3-197880.57"
+ process $proc$libresoc.v:197879$13474
assign { } { }
assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next
sync posedge \clk
update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:198937.3-198938.69"
- process $proc$libresoc.v:198937$13663
+ attribute \src "libresoc.v:197881.3-197882.69"
+ process $proc$libresoc.v:197881$13475
assign { } { }
assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next
sync posedge \clk
update \core_core_core_input_carry $0\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:198939.3-198940.63"
- process $proc$libresoc.v:198939$13664
+ attribute \src "libresoc.v:197883.3-197884.63"
+ process $proc$libresoc.v:197883$13476
assign { } { }
assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next
sync posedge \clk
update \core_core_core_traptype $0\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:198941.3-198942.71"
- process $proc$libresoc.v:198941$13665
+ attribute \src "libresoc.v:197885.3-197886.71"
+ process $proc$libresoc.v:197885$13477
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$13666 \core_core_core_exc_$signal$next
+ assign $0\core_core_core_exc_$signal[0:0]$13478 \core_core_core_exc_$signal$next
sync posedge \clk
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13666
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13478
end
- attribute \src "libresoc.v:198943.3-198944.75"
- process $proc$libresoc.v:198943$13667
+ attribute \src "libresoc.v:197887.3-197888.75"
+ process $proc$libresoc.v:197887$13479
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$13668 \core_core_core_exc_$signal$3$next
+ assign $0\core_core_core_exc_$signal$3[0:0]$13480 \core_core_core_exc_$signal$3$next
sync posedge \clk
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13668
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13480
end
- attribute \src "libresoc.v:198945.3-198946.75"
- process $proc$libresoc.v:198945$13669
+ attribute \src "libresoc.v:197889.3-197890.75"
+ process $proc$libresoc.v:197889$13481
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$13670 \core_core_core_exc_$signal$4$next
+ assign $0\core_core_core_exc_$signal$4[0:0]$13482 \core_core_core_exc_$signal$4$next
sync posedge \clk
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13670
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13482
end
- attribute \src "libresoc.v:198947.3-198948.75"
- process $proc$libresoc.v:198947$13671
+ attribute \src "libresoc.v:197891.3-197892.75"
+ process $proc$libresoc.v:197891$13483
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$13672 \core_core_core_exc_$signal$5$next
+ assign $0\core_core_core_exc_$signal$5[0:0]$13484 \core_core_core_exc_$signal$5$next
sync posedge \clk
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13672
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13484
end
- attribute \src "libresoc.v:198949.3-198950.75"
- process $proc$libresoc.v:198949$13673
+ attribute \src "libresoc.v:197893.3-197894.75"
+ process $proc$libresoc.v:197893$13485
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$13674 \core_core_core_exc_$signal$6$next
+ assign $0\core_core_core_exc_$signal$6[0:0]$13486 \core_core_core_exc_$signal$6$next
sync posedge \clk
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13674
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13486
end
- attribute \src "libresoc.v:198951.3-198952.41"
- process $proc$libresoc.v:198951$13675
+ attribute \src "libresoc.v:197895.3-197896.41"
+ process $proc$libresoc.v:197895$13487
assign { } { }
assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next
sync posedge \clk
update \core_sv_a_nz $0\core_sv_a_nz[0:0]
end
- attribute \src "libresoc.v:198953.3-198954.75"
- process $proc$libresoc.v:198953$13676
+ attribute \src "libresoc.v:197897.3-197898.75"
+ process $proc$libresoc.v:197897$13488
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$13677 \core_core_core_exc_$signal$7$next
+ assign $0\core_core_core_exc_$signal$7[0:0]$13489 \core_core_core_exc_$signal$7$next
sync posedge \clk
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13677
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13489
end
- attribute \src "libresoc.v:198955.3-198956.75"
- process $proc$libresoc.v:198955$13678
+ attribute \src "libresoc.v:197899.3-197900.75"
+ process $proc$libresoc.v:197899$13490
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$13679 \core_core_core_exc_$signal$8$next
+ assign $0\core_core_core_exc_$signal$8[0:0]$13491 \core_core_core_exc_$signal$8$next
sync posedge \clk
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13679
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13491
end
- attribute \src "libresoc.v:198957.3-198958.75"
- process $proc$libresoc.v:198957$13680
+ attribute \src "libresoc.v:197901.3-197902.75"
+ process $proc$libresoc.v:197901$13492
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$13681 \core_core_core_exc_$signal$9$next
+ assign $0\core_core_core_exc_$signal$9[0:0]$13493 \core_core_core_exc_$signal$9$next
sync posedge \clk
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13681
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13493
end
- attribute \src "libresoc.v:198959.3-198960.63"
- process $proc$libresoc.v:198959$13682
+ attribute \src "libresoc.v:197903.3-197904.63"
+ process $proc$libresoc.v:197903$13494
assign { } { }
assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next
sync posedge \clk
update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:198961.3-198962.57"
- process $proc$libresoc.v:198961$13683
+ attribute \src "libresoc.v:197905.3-197906.57"
+ process $proc$libresoc.v:197905$13495
assign { } { }
assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next
sync posedge \clk
update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:198963.3-198964.63"
- process $proc$libresoc.v:198963$13684
+ attribute \src "libresoc.v:197907.3-197908.63"
+ process $proc$libresoc.v:197907$13496
assign { } { }
assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next
sync posedge \clk
update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:198965.3-198966.57"
- process $proc$libresoc.v:198965$13685
+ attribute \src "libresoc.v:197909.3-197910.57"
+ process $proc$libresoc.v:197909$13497
assign { } { }
assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next
sync posedge \clk
update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:198967.3-198968.53"
- process $proc$libresoc.v:198967$13686
+ attribute \src "libresoc.v:197911.3-197912.53"
+ process $proc$libresoc.v:197911$13498
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
sync posedge \clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:198969.3-198970.63"
- process $proc$libresoc.v:198969$13687
+ attribute \src "libresoc.v:197913.3-197914.63"
+ process $proc$libresoc.v:197913$13499
assign { } { }
assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next
sync posedge \clk
update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:198971.3-198972.37"
- process $proc$libresoc.v:198971$13688
+ attribute \src "libresoc.v:197915.3-197916.37"
+ process $proc$libresoc.v:197915$13500
assign { } { }
assign $0\sv_changed[0:0] \sv_changed$next
sync posedge \clk
update \sv_changed $0\sv_changed[0:0]
end
- attribute \src "libresoc.v:198973.3-198974.57"
- process $proc$libresoc.v:198973$13689
+ attribute \src "libresoc.v:197917.3-197918.57"
+ process $proc$libresoc.v:197917$13501
assign { } { }
- assign $0\core_bigendian_i$10[0:0]$13690 \core_bigendian_i$10$next
+ assign $0\core_bigendian_i$10[0:0]$13502 \core_bigendian_i$10$next
sync posedge \clk
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13690
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13502
end
- attribute \src "libresoc.v:198975.3-198976.37"
- process $proc$libresoc.v:198975$13691
+ attribute \src "libresoc.v:197919.3-197920.37"
+ process $proc$libresoc.v:197919$13503
assign { } { }
assign $0\pc_changed[0:0] \pc_changed$next
sync posedge \clk
update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:198977.3-198978.47"
- process $proc$libresoc.v:198977$13692
+ attribute \src "libresoc.v:197921.3-197922.47"
+ process $proc$libresoc.v:197921$13504
assign { } { }
assign $0\issue_fsm_state[2:0] \issue_fsm_state$next
sync posedge \clk
update \issue_fsm_state $0\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:198979.3-198980.53"
- process $proc$libresoc.v:198979$13693
+ attribute \src "libresoc.v:197923.3-197924.53"
+ process $proc$libresoc.v:197923$13505
assign { } { }
assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next
sync posedge \clk
update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:198981.3-198982.23"
- process $proc$libresoc.v:198981$13694
+ attribute \src "libresoc.v:197925.3-197926.23"
+ process $proc$libresoc.v:197925$13506
assign { } { }
assign $0\nia[63:0] \nia$next
sync posedge \clk
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:198983.3-198984.41"
- process $proc$libresoc.v:198983$13695
+ attribute \src "libresoc.v:197927.3-197928.41"
+ process $proc$libresoc.v:197927$13507
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
sync posedge \clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:198985.3-198986.47"
- process $proc$libresoc.v:198985$13696
+ attribute \src "libresoc.v:197929.3-197930.47"
+ process $proc$libresoc.v:197929$13508
assign { } { }
assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next
sync posedge \clk
update \fetch_fsm_state $0\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:198987.3-198988.33"
- process $proc$libresoc.v:198987$13697
+ attribute \src "libresoc.v:197931.3-197932.33"
+ process $proc$libresoc.v:197931$13509
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
sync posedge \clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:198989.3-198990.45"
- process $proc$libresoc.v:198989$13698
+ attribute \src "libresoc.v:197933.3-197934.45"
+ process $proc$libresoc.v:197933$13510
assign { } { }
assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next
sync posedge \clk
update \cur_cur_svstep $0\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:198991.3-198992.43"
- process $proc$libresoc.v:198991$13699
+ attribute \src "libresoc.v:197935.3-197936.43"
+ process $proc$libresoc.v:197935$13511
assign { } { }
assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next
sync posedge \clk
update \cur_cur_subvl $0\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:198993.3-198994.47"
- process $proc$libresoc.v:198993$13700
+ attribute \src "libresoc.v:197937.3-197938.47"
+ process $proc$libresoc.v:197937$13512
assign { } { }
assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next
sync posedge \clk
update \cur_cur_dststep $0\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:198995.3-198996.47"
- process $proc$libresoc.v:198995$13701
+ attribute \src "libresoc.v:197939.3-197940.47"
+ process $proc$libresoc.v:197939$13513
assign { } { }
assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next
sync posedge \clk
update \core_raw_insn_i $0\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:198997.3-198998.47"
- process $proc$libresoc.v:198997$13702
+ attribute \src "libresoc.v:197941.3-197942.47"
+ process $proc$libresoc.v:197941$13514
assign { } { }
assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next
sync posedge \clk
update \cur_cur_srcstep $0\cur_cur_srcstep[6:0]
end
- attribute \src "libresoc.v:198999.3-199000.37"
- process $proc$libresoc.v:198999$13703
+ attribute \src "libresoc.v:197943.3-197944.37"
+ process $proc$libresoc.v:197943$13515
assign { } { }
assign $0\cur_cur_vl[6:0] \cur_cur_vl$next
sync posedge \clk
update \cur_cur_vl $0\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:199001.3-199002.43"
- process $proc$libresoc.v:199001$13704
+ attribute \src "libresoc.v:197945.3-197946.43"
+ process $proc$libresoc.v:197945$13516
assign { } { }
assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next
sync posedge \clk
update \cur_cur_maxvl $0\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:199003.3-199004.39"
- process $proc$libresoc.v:199003$13705
+ attribute \src "libresoc.v:197947.3-197948.39"
+ process $proc$libresoc.v:197947$13517
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
sync posedge \clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:199005.3-199006.49"
- process $proc$libresoc.v:199005$13706
+ attribute \src "libresoc.v:197949.3-197950.49"
+ process $proc$libresoc.v:197949$13518
assign { } { }
assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next
sync posedge \clk
update \svstate_ok_delay $0\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:199007.3-199008.39"
- process $proc$libresoc.v:199007$13707
+ attribute \src "libresoc.v:197951.3-197952.39"
+ process $proc$libresoc.v:197951$13519
assign { } { }
assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
sync posedge \clk
update \pc_ok_delay $0\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:199009.3-199010.43"
- process $proc$libresoc.v:199009$13708
+ attribute \src "libresoc.v:197953.3-197954.43"
+ process $proc$libresoc.v:197953$13520
assign { } { }
assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o
sync posedge \clk
update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:199011.3-199012.27"
- process $proc$libresoc.v:199011$13709
+ attribute \src "libresoc.v:197955.3-197956.27"
+ process $proc$libresoc.v:197955$13521
assign { } { }
assign $0\delay[1:0] \delay$next
sync posedge \por_clk
update \delay $0\delay[1:0]
end
- attribute \src "libresoc.v:199013.3-199014.43"
- process $proc$libresoc.v:199013$13710
+ attribute \src "libresoc.v:197957.3-197958.43"
+ process $proc$libresoc.v:197957$13522
assign { } { }
assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
sync posedge \clk
update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:199015.3-199016.47"
- process $proc$libresoc.v:199015$13711
+ attribute \src "libresoc.v:197959.3-197960.47"
+ process $proc$libresoc.v:197959$13523
assign { } { }
assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
sync posedge \clk
update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:199546.3-199554.6"
- process $proc$libresoc.v:199546$13712
+ attribute \src "libresoc.v:198490.3-198498.6"
+ process $proc$libresoc.v:198490$13524
assign { } { }
assign { } { }
- assign $0\dbg_dmi_addr_i$next[3:0]$13713 $1\dbg_dmi_addr_i$next[3:0]$13714
- attribute \src "libresoc.v:199547.5-199547.29"
+ assign $0\dbg_dmi_addr_i$next[3:0]$13525 $1\dbg_dmi_addr_i$next[3:0]$13526
+ attribute \src "libresoc.v:198491.5-198491.29"
switch \initial
- attribute \src "libresoc.v:199547.9-199547.17"
+ attribute \src "libresoc.v:198491.9-198491.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_addr_i$next[3:0]$13714 4'0000
+ assign $1\dbg_dmi_addr_i$next[3:0]$13526 4'0000
case
- assign $1\dbg_dmi_addr_i$next[3:0]$13714 \jtag_dmi0__addr_i
+ assign $1\dbg_dmi_addr_i$next[3:0]$13526 \jtag_dmi0__addr_i
end
sync always
- update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13713
+ update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13525
end
- attribute \src "libresoc.v:199555.3-199563.6"
- process $proc$libresoc.v:199555$13715
+ attribute \src "libresoc.v:198499.3-198507.6"
+ process $proc$libresoc.v:198499$13527
assign { } { }
assign { } { }
- assign $0\dbg_dmi_req_i$next[0:0]$13716 $1\dbg_dmi_req_i$next[0:0]$13717
- attribute \src "libresoc.v:199556.5-199556.29"
+ assign $0\dbg_dmi_req_i$next[0:0]$13528 $1\dbg_dmi_req_i$next[0:0]$13529
+ attribute \src "libresoc.v:198500.5-198500.29"
switch \initial
- attribute \src "libresoc.v:199556.9-199556.17"
+ attribute \src "libresoc.v:198500.9-198500.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_req_i$next[0:0]$13717 1'0
+ assign $1\dbg_dmi_req_i$next[0:0]$13529 1'0
case
- assign $1\dbg_dmi_req_i$next[0:0]$13717 \jtag_dmi0__req_i
+ assign $1\dbg_dmi_req_i$next[0:0]$13529 \jtag_dmi0__req_i
end
sync always
- update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13716
+ update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13528
end
- attribute \src "libresoc.v:199564.3-199628.6"
- process $proc$libresoc.v:199564$13718
+ attribute \src "libresoc.v:198508.3-198572.6"
+ process $proc$libresoc.v:198508$13530
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_dststep$next[6:0]$13719 $3\core_core_dststep$next[6:0]$13749
- assign $0\core_core_maxvl$next[6:0]$13720 $3\core_core_maxvl$next[6:0]$13750
- assign $0\core_core_pc$next[63:0]$13721 $3\core_core_pc$next[63:0]$13751
- assign $0\core_core_srcstep$next[6:0]$13722 $3\core_core_srcstep$next[6:0]$13752
- assign $0\core_core_subvl$next[1:0]$13723 $3\core_core_subvl$next[1:0]$13753
- assign $0\core_core_svstep$next[1:0]$13724 $3\core_core_svstep$next[1:0]$13754
- assign $0\core_core_vl$next[6:0]$13725 $3\core_core_vl$next[6:0]$13755
- assign $0\core_dec$next[63:0]$13726 $3\core_dec$next[63:0]$13756
- assign $0\core_eint$next[0:0]$13727 $3\core_eint$next[0:0]$13757
- assign $0\core_msr$next[63:0]$13728 $3\core_msr$next[63:0]$13758
- attribute \src "libresoc.v:199565.5-199565.29"
+ assign $0\core_core_dststep$next[6:0]$13531 $3\core_core_dststep$next[6:0]$13561
+ assign $0\core_core_maxvl$next[6:0]$13532 $3\core_core_maxvl$next[6:0]$13562
+ assign $0\core_core_pc$next[63:0]$13533 $3\core_core_pc$next[63:0]$13563
+ assign $0\core_core_srcstep$next[6:0]$13534 $3\core_core_srcstep$next[6:0]$13564
+ assign $0\core_core_subvl$next[1:0]$13535 $3\core_core_subvl$next[1:0]$13565
+ assign $0\core_core_svstep$next[1:0]$13536 $3\core_core_svstep$next[1:0]$13566
+ assign $0\core_core_vl$next[6:0]$13537 $3\core_core_vl$next[6:0]$13567
+ assign $0\core_dec$next[63:0]$13538 $3\core_dec$next[63:0]$13568
+ assign $0\core_eint$next[0:0]$13539 $3\core_eint$next[0:0]$13569
+ assign $0\core_msr$next[63:0]$13540 $3\core_msr$next[63:0]$13570
+ attribute \src "libresoc.v:198509.5-198509.29"
switch \initial
- attribute \src "libresoc.v:199565.9-199565.17"
+ attribute \src "libresoc.v:198509.9-198509.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_core_dststep$next[6:0]$13729 $2\core_core_dststep$next[6:0]$13739
- assign $1\core_core_maxvl$next[6:0]$13730 $2\core_core_maxvl$next[6:0]$13740
- assign $1\core_core_pc$next[63:0]$13731 $2\core_core_pc$next[63:0]$13741
- assign $1\core_core_srcstep$next[6:0]$13732 $2\core_core_srcstep$next[6:0]$13742
- assign $1\core_core_subvl$next[1:0]$13733 $2\core_core_subvl$next[1:0]$13743
- assign $1\core_core_svstep$next[1:0]$13734 $2\core_core_svstep$next[1:0]$13744
- assign $1\core_core_vl$next[6:0]$13735 $2\core_core_vl$next[6:0]$13745
- assign $1\core_dec$next[63:0]$13736 $2\core_dec$next[63:0]$13746
- assign $1\core_eint$next[0:0]$13737 $2\core_eint$next[0:0]$13747
- assign $1\core_msr$next[63:0]$13738 $2\core_msr$next[63:0]$13748
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\core_core_dststep$next[6:0]$13541 $2\core_core_dststep$next[6:0]$13551
+ assign $1\core_core_maxvl$next[6:0]$13542 $2\core_core_maxvl$next[6:0]$13552
+ assign $1\core_core_pc$next[63:0]$13543 $2\core_core_pc$next[63:0]$13553
+ assign $1\core_core_srcstep$next[6:0]$13544 $2\core_core_srcstep$next[6:0]$13554
+ assign $1\core_core_subvl$next[1:0]$13545 $2\core_core_subvl$next[1:0]$13555
+ assign $1\core_core_svstep$next[1:0]$13546 $2\core_core_svstep$next[1:0]$13556
+ assign $1\core_core_vl$next[6:0]$13547 $2\core_core_vl$next[6:0]$13557
+ assign $1\core_dec$next[63:0]$13548 $2\core_dec$next[63:0]$13558
+ assign $1\core_eint$next[0:0]$13549 $2\core_eint$next[0:0]$13559
+ assign $1\core_msr$next[63:0]$13550 $2\core_msr$next[63:0]$13560
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_maxvl$next[6:0]$13740 $2\core_core_vl$next[6:0]$13745 $2\core_core_srcstep$next[6:0]$13742 $2\core_core_dststep$next[6:0]$13739 $2\core_core_subvl$next[1:0]$13743 $2\core_core_svstep$next[1:0]$13744 $2\core_dec$next[63:0]$13746 $2\core_eint$next[0:0]$13747 $2\core_msr$next[63:0]$13748 $2\core_core_pc$next[63:0]$13741 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $2\core_core_maxvl$next[6:0]$13552 $2\core_core_vl$next[6:0]$13557 $2\core_core_srcstep$next[6:0]$13554 $2\core_core_dststep$next[6:0]$13551 $2\core_core_subvl$next[1:0]$13555 $2\core_core_svstep$next[1:0]$13556 $2\core_dec$next[63:0]$13558 $2\core_eint$next[0:0]$13559 $2\core_msr$next[63:0]$13560 $2\core_core_pc$next[63:0]$13553 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $2\core_core_dststep$next[6:0]$13739 \core_core_dststep
- assign $2\core_core_maxvl$next[6:0]$13740 \core_core_maxvl
- assign $2\core_core_pc$next[63:0]$13741 \core_core_pc
- assign $2\core_core_srcstep$next[6:0]$13742 \core_core_srcstep
- assign $2\core_core_subvl$next[1:0]$13743 \core_core_subvl
- assign $2\core_core_svstep$next[1:0]$13744 \core_core_svstep
- assign $2\core_core_vl$next[6:0]$13745 \core_core_vl
- assign $2\core_dec$next[63:0]$13746 \core_dec
- assign $2\core_eint$next[0:0]$13747 \core_eint
- assign $2\core_msr$next[63:0]$13748 \core_msr
+ assign $2\core_core_dststep$next[6:0]$13551 \core_core_dststep
+ assign $2\core_core_maxvl$next[6:0]$13552 \core_core_maxvl
+ assign $2\core_core_pc$next[63:0]$13553 \core_core_pc
+ assign $2\core_core_srcstep$next[6:0]$13554 \core_core_srcstep
+ assign $2\core_core_subvl$next[1:0]$13555 \core_core_subvl
+ assign $2\core_core_svstep$next[1:0]$13556 \core_core_svstep
+ assign $2\core_core_vl$next[6:0]$13557 \core_core_vl
+ assign $2\core_dec$next[63:0]$13558 \core_dec
+ assign $2\core_eint$next[0:0]$13559 \core_eint
+ assign $2\core_msr$next[63:0]$13560 \core_msr
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_maxvl$next[6:0]$13730 $1\core_core_vl$next[6:0]$13735 $1\core_core_srcstep$next[6:0]$13732 $1\core_core_dststep$next[6:0]$13729 $1\core_core_subvl$next[1:0]$13733 $1\core_core_svstep$next[1:0]$13734 $1\core_dec$next[63:0]$13736 $1\core_eint$next[0:0]$13737 $1\core_msr$next[63:0]$13738 $1\core_core_pc$next[63:0]$13731 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $1\core_core_maxvl$next[6:0]$13542 $1\core_core_vl$next[6:0]$13547 $1\core_core_srcstep$next[6:0]$13544 $1\core_core_dststep$next[6:0]$13541 $1\core_core_subvl$next[1:0]$13545 $1\core_core_svstep$next[1:0]$13546 $1\core_dec$next[63:0]$13548 $1\core_eint$next[0:0]$13549 $1\core_msr$next[63:0]$13550 $1\core_core_pc$next[63:0]$13543 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13731 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13735 \core_core_vl
- assign $1\core_dec$next[63:0]$13736 \core_dec
- assign $1\core_eint$next[0:0]$13737 \core_eint
- assign $1\core_msr$next[63:0]$13738 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
+ assign $1\core_dec$next[63:0]$13548 \core_dec
+ assign $1\core_eint$next[0:0]$13549 \core_eint
+ assign $1\core_msr$next[63:0]$13550 \core_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_core_pc$next[63:0]$13751 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_msr$next[63:0]$13758 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_eint$next[0:0]$13757 1'0
- assign $3\core_dec$next[63:0]$13756 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_core_svstep$next[1:0]$13754 2'00
- assign $3\core_core_subvl$next[1:0]$13753 2'00
- assign $3\core_core_dststep$next[6:0]$13749 7'0000000
- assign $3\core_core_srcstep$next[6:0]$13752 7'0000000
- assign $3\core_core_vl$next[6:0]$13755 7'0000000
- assign $3\core_core_maxvl$next[6:0]$13750 7'0000000
+ assign $3\core_core_pc$next[63:0]$13563 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_msr$next[63:0]$13570 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_eint$next[0:0]$13569 1'0
+ assign $3\core_dec$next[63:0]$13568 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_core_svstep$next[1:0]$13566 2'00
+ assign $3\core_core_subvl$next[1:0]$13565 2'00
+ assign $3\core_core_dststep$next[6:0]$13561 7'0000000
+ assign $3\core_core_srcstep$next[6:0]$13564 7'0000000
+ assign $3\core_core_vl$next[6:0]$13567 7'0000000
+ assign $3\core_core_maxvl$next[6:0]$13562 7'0000000
case
- assign $3\core_core_dststep$next[6:0]$13749 $1\core_core_dststep$next[6:0]$13729
- assign $3\core_core_maxvl$next[6:0]$13750 $1\core_core_maxvl$next[6:0]$13730
- assign $3\core_core_pc$next[63:0]$13751 $1\core_core_pc$next[63:0]$13731
- assign $3\core_core_srcstep$next[6:0]$13752 $1\core_core_srcstep$next[6:0]$13732
- assign $3\core_core_subvl$next[1:0]$13753 $1\core_core_subvl$next[1:0]$13733
- assign $3\core_core_svstep$next[1:0]$13754 $1\core_core_svstep$next[1:0]$13734
- assign $3\core_core_vl$next[6:0]$13755 $1\core_core_vl$next[6:0]$13735
- assign $3\core_dec$next[63:0]$13756 $1\core_dec$next[63:0]$13736
- assign $3\core_eint$next[0:0]$13757 $1\core_eint$next[0:0]$13737
- assign $3\core_msr$next[63:0]$13758 $1\core_msr$next[63:0]$13738
+ assign $3\core_core_dststep$next[6:0]$13561 $1\core_core_dststep$next[6:0]$13541
+ assign $3\core_core_maxvl$next[6:0]$13562 $1\core_core_maxvl$next[6:0]$13542
+ assign $3\core_core_pc$next[63:0]$13563 $1\core_core_pc$next[63:0]$13543
+ assign $3\core_core_srcstep$next[6:0]$13564 $1\core_core_srcstep$next[6:0]$13544
+ assign $3\core_core_subvl$next[1:0]$13565 $1\core_core_subvl$next[1:0]$13545
+ assign $3\core_core_svstep$next[1:0]$13566 $1\core_core_svstep$next[1:0]$13546
+ assign $3\core_core_vl$next[6:0]$13567 $1\core_core_vl$next[6:0]$13547
+ assign $3\core_dec$next[63:0]$13568 $1\core_dec$next[63:0]$13548
+ assign $3\core_eint$next[0:0]$13569 $1\core_eint$next[0:0]$13549
+ assign $3\core_msr$next[63:0]$13570 $1\core_msr$next[63:0]$13550
end
sync always
- update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13719
- update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13720
- update \core_core_pc$next $0\core_core_pc$next[63:0]$13721
- update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13722
- update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13723
- update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13724
- update \core_core_vl$next $0\core_core_vl$next[6:0]$13725
- update \core_dec$next $0\core_dec$next[63:0]$13726
- update \core_eint$next $0\core_eint$next[0:0]$13727
- update \core_msr$next $0\core_msr$next[63:0]$13728
+ update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13531
+ update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13532
+ update \core_core_pc$next $0\core_core_pc$next[63:0]$13533
+ update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13534
+ update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13535
+ update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13536
+ update \core_core_vl$next $0\core_core_vl$next[6:0]$13537
+ update \core_dec$next $0\core_dec$next[63:0]$13538
+ update \core_eint$next $0\core_eint$next[0:0]$13539
+ update \core_msr$next $0\core_msr$next[63:0]$13540
end
- attribute \src "libresoc.v:199629.3-199653.6"
- process $proc$libresoc.v:199629$13759
+ attribute \src "libresoc.v:198573.3-198597.6"
+ process $proc$libresoc.v:198573$13571
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_raw_insn_i$next[31:0]$13760 $3\core_raw_insn_i$next[31:0]$13763
- attribute \src "libresoc.v:199630.5-199630.29"
+ assign $0\core_raw_insn_i$next[31:0]$13572 $3\core_raw_insn_i$next[31:0]$13575
+ attribute \src "libresoc.v:198574.5-198574.29"
switch \initial
- attribute \src "libresoc.v:199630.9-199630.17"
+ attribute \src "libresoc.v:198574.9-198574.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_raw_insn_i$next[31:0]$13761 \core_raw_insn_i
+ assign $1\core_raw_insn_i$next[31:0]$13573 \core_raw_insn_i
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_raw_insn_i$next[31:0]$13761 $2\core_raw_insn_i$next[31:0]$13762
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\core_raw_insn_i$next[31:0]$13573 $2\core_raw_insn_i$next[31:0]$13574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_raw_insn_i$next[31:0]$13762 \dec2_raw_opcode_in
+ assign $2\core_raw_insn_i$next[31:0]$13574 \dec2_raw_opcode_in
case
- assign $2\core_raw_insn_i$next[31:0]$13762 \core_raw_insn_i
+ assign $2\core_raw_insn_i$next[31:0]$13574 \core_raw_insn_i
end
case
- assign $1\core_raw_insn_i$next[31:0]$13761 \core_raw_insn_i
+ assign $1\core_raw_insn_i$next[31:0]$13573 \core_raw_insn_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_raw_insn_i$next[31:0]$13763 0
+ assign $3\core_raw_insn_i$next[31:0]$13575 0
case
- assign $3\core_raw_insn_i$next[31:0]$13763 $1\core_raw_insn_i$next[31:0]$13761
+ assign $3\core_raw_insn_i$next[31:0]$13575 $1\core_raw_insn_i$next[31:0]$13573
end
sync always
- update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13760
+ update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13572
end
- attribute \src "libresoc.v:199654.3-199698.6"
- process $proc$libresoc.v:199654$13764
+ attribute \src "libresoc.v:198598.3-198642.6"
+ process $proc$libresoc.v:198598$13576
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_bigendian_i$10$next[0:0]$13765 $3\core_bigendian_i$10$next[0:0]$13768
- attribute \src "libresoc.v:199655.5-199655.29"
+ assign $0\core_bigendian_i$10$next[0:0]$13577 $3\core_bigendian_i$10$next[0:0]$13580
+ attribute \src "libresoc.v:198599.5-198599.29"
switch \initial
- attribute \src "libresoc.v:199655.9-199655.17"
+ attribute \src "libresoc.v:198599.9-198599.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_bigendian_i$10$next[0:0]$13766 $2\core_bigendian_i$10$next[0:0]$13767
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\core_bigendian_i$10$next[0:0]$13578 $2\core_bigendian_i$10$next[0:0]$13579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_bigendian_i$10$next[0:0]$13767 \core_bigendian_i
+ assign $2\core_bigendian_i$10$next[0:0]$13579 \core_bigendian_i
case
- assign $2\core_bigendian_i$10$next[0:0]$13767 \core_bigendian_i$10
+ assign $2\core_bigendian_i$10$next[0:0]$13579 \core_bigendian_i$10
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i
case
- assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_bigendian_i$10$next[0:0]$13768 1'0
+ assign $3\core_bigendian_i$10$next[0:0]$13580 1'0
case
- assign $3\core_bigendian_i$10$next[0:0]$13768 $1\core_bigendian_i$10$next[0:0]$13766
+ assign $3\core_bigendian_i$10$next[0:0]$13580 $1\core_bigendian_i$10$next[0:0]$13578
end
sync always
- update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13765
+ update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13577
end
- attribute \src "libresoc.v:199699.3-199743.6"
- process $proc$libresoc.v:199699$13769
+ attribute \src "libresoc.v:198643.3-198687.6"
+ process $proc$libresoc.v:198643$13581
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_sv_a_nz$next[0:0]$13770 $3\core_sv_a_nz$next[0:0]$13773
- attribute \src "libresoc.v:199700.5-199700.29"
+ assign $0\core_sv_a_nz$next[0:0]$13582 $3\core_sv_a_nz$next[0:0]$13585
+ attribute \src "libresoc.v:198644.5-198644.29"
switch \initial
- attribute \src "libresoc.v:199700.9-199700.17"
+ attribute \src "libresoc.v:198644.9-198644.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_sv_a_nz$next[0:0]$13771 $2\core_sv_a_nz$next[0:0]$13772
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\core_sv_a_nz$next[0:0]$13583 $2\core_sv_a_nz$next[0:0]$13584
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_sv_a_nz$next[0:0]$13772 \dec2_sv_a_nz
+ assign $2\core_sv_a_nz$next[0:0]$13584 \dec2_sv_a_nz
case
- assign $2\core_sv_a_nz$next[0:0]$13772 \core_sv_a_nz
+ assign $2\core_sv_a_nz$next[0:0]$13584 \core_sv_a_nz
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\core_sv_a_nz$next[0:0]$13771 \dec2_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \dec2_sv_a_nz
case
- assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_sv_a_nz$next[0:0]$13773 1'0
+ assign $3\core_sv_a_nz$next[0:0]$13585 1'0
case
- assign $3\core_sv_a_nz$next[0:0]$13773 $1\core_sv_a_nz$next[0:0]$13771
+ assign $3\core_sv_a_nz$next[0:0]$13585 $1\core_sv_a_nz$next[0:0]$13583
end
sync always
- update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13770
+ update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13582
end
- attribute \src "libresoc.v:199744.3-199789.6"
- process $proc$libresoc.v:199744$13774
+ attribute \src "libresoc.v:198688.3-198733.6"
+ process $proc$libresoc.v:198688$13586
assign { } { }
assign { } { }
assign { } { }
assign $0\insn_done[0:0] $4\insn_done[0:0]
- attribute \src "libresoc.v:199745.5-199745.29"
+ attribute \src "libresoc.v:198689.5-198689.29"
switch \initial
- attribute \src "libresoc.v:199745.9-199745.17"
+ attribute \src "libresoc.v:198689.9-198689.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'001
assign { } { }
assign $1\insn_done[0:0] $2\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\insn_done[0:0] $3\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
switch \$234
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\insn_done[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
case 1'1
assign { } { }
assign $4\insn_done[0:0] $5\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
switch \$236
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\insn_done[0:0] $6\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:736"
switch \exec_pc_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \insn_done $0\insn_done[0:0]
end
- attribute \src "libresoc.v:199790.3-199808.6"
- process $proc$libresoc.v:199790$13775
+ attribute \src "libresoc.v:198734.3-198752.6"
+ process $proc$libresoc.v:198734$13587
assign { } { }
assign { } { }
assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:199791.5-199791.29"
+ attribute \src "libresoc.v:198735.5-198735.29"
switch \initial
- attribute \src "libresoc.v:199791.9-199791.17"
+ attribute \src "libresoc.v:198735.9-198735.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \pred_insn_valid_i $0\pred_insn_valid_i[0:0]
end
- attribute \src "libresoc.v:199809.3-199831.6"
- process $proc$libresoc.v:199809$13776
+ attribute \src "libresoc.v:198753.3-198775.6"
+ process $proc$libresoc.v:198753$13588
assign { } { }
assign { } { }
assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:199810.5-199810.29"
+ attribute \src "libresoc.v:198754.5-198754.29"
switch \initial
- attribute \src "libresoc.v:199810.9-199810.17"
+ attribute \src "libresoc.v:198754.9-198754.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \pred_mask_ready_i $0\pred_mask_ready_i[0:0]
end
- attribute \src "libresoc.v:199832.3-199858.6"
- process $proc$libresoc.v:199832$13777
+ attribute \src "libresoc.v:198776.3-198802.6"
+ process $proc$libresoc.v:198776$13589
assign { } { }
assign { } { }
assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:199833.5-199833.29"
+ attribute \src "libresoc.v:198777.5-198777.29"
switch \initial
- attribute \src "libresoc.v:199833.9-199833.17"
+ attribute \src "libresoc.v:198777.9-198777.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \exec_insn_valid_i $0\exec_insn_valid_i[0:0]
end
- attribute \src "libresoc.v:199859.3-199894.6"
- process $proc$libresoc.v:199859$13778
+ attribute \src "libresoc.v:198803.3-198838.6"
+ process $proc$libresoc.v:198803$13590
assign { } { }
assign { } { }
assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:199860.5-199860.29"
+ attribute \src "libresoc.v:198804.5-198804.29"
switch \initial
- attribute \src "libresoc.v:199860.9-199860.17"
+ attribute \src "libresoc.v:198804.9-198804.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'101
assign { } { }
assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$242
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \exec_pc_ready_i $0\exec_pc_ready_i[0:0]
end
- attribute \src "libresoc.v:199895.3-199935.6"
- process $proc$libresoc.v:199895$13779
+ attribute \src "libresoc.v:198839.3-198879.6"
+ process $proc$libresoc.v:198839$13591
assign { } { }
assign { } { }
assign $0\is_last[0:0] $1\is_last[0:0]
- attribute \src "libresoc.v:199896.5-199896.29"
+ attribute \src "libresoc.v:198840.5-198840.29"
switch \initial
- attribute \src "libresoc.v:199896.9-199896.17"
+ attribute \src "libresoc.v:198840.9-198840.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'101
assign { } { }
assign $1\is_last[0:0] $2\is_last[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$248
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\is_last[0:0] $3\is_last[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \is_last $0\is_last[0:0]
end
- attribute \src "libresoc.v:199936.3-199945.6"
- process $proc$libresoc.v:199936$13780
+ attribute \src "libresoc.v:198880.3-198889.6"
+ process $proc$libresoc.v:198880$13592
assign { } { }
assign { } { }
- assign $0\core_wen$11[2:0]$13781 $1\core_wen$11[2:0]$13782
- attribute \src "libresoc.v:199937.5-199937.29"
+ assign $0\core_wen$11[2:0]$13593 $1\core_wen$11[2:0]$13594
+ attribute \src "libresoc.v:198881.5-198881.29"
switch \initial
- attribute \src "libresoc.v:199937.9-199937.17"
+ attribute \src "libresoc.v:198881.9-198881.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_wen$11[2:0]$13782 3'100
+ assign $1\core_wen$11[2:0]$13594 3'100
case
- assign $1\core_wen$11[2:0]$13782 3'000
+ assign $1\core_wen$11[2:0]$13594 3'000
end
sync always
- update \core_wen$11 $0\core_wen$11[2:0]$13781
+ update \core_wen$11 $0\core_wen$11[2:0]$13593
end
- attribute \src "libresoc.v:199946.3-199955.6"
- process $proc$libresoc.v:199946$13783
+ attribute \src "libresoc.v:198890.3-198899.6"
+ process $proc$libresoc.v:198890$13595
assign { } { }
assign { } { }
- assign $0\core_data_i$12[63:0]$13784 $1\core_data_i$12[63:0]$13785
- attribute \src "libresoc.v:199947.5-199947.29"
+ assign $0\core_data_i$12[63:0]$13596 $1\core_data_i$12[63:0]$13597
+ attribute \src "libresoc.v:198891.5-198891.29"
switch \initial
- attribute \src "libresoc.v:199947.9-199947.17"
+ attribute \src "libresoc.v:198891.9-198891.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_data_i$12[63:0]$13785 \$252
+ assign $1\core_data_i$12[63:0]$13597 \$252
case
- assign $1\core_data_i$12[63:0]$13785 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\core_data_i$12[63:0]$13597 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \core_data_i$12 $0\core_data_i$12[63:0]$13784
+ update \core_data_i$12 $0\core_data_i$12[63:0]$13596
end
- attribute \src "libresoc.v:199956.3-199966.6"
- process $proc$libresoc.v:199956$13786
+ attribute \src "libresoc.v:198900.3-198910.6"
+ process $proc$libresoc.v:198900$13598
assign { } { }
assign { } { }
assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:199957.5-199957.29"
+ attribute \src "libresoc.v:198901.5-198901.29"
switch \initial
- attribute \src "libresoc.v:199957.9-199957.17"
+ attribute \src "libresoc.v:198901.9-198901.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
sync always
update \exec_insn_ready_o $0\exec_insn_ready_o[0:0]
end
- attribute \src "libresoc.v:199967.3-199991.6"
- process $proc$libresoc.v:199967$13787
+ attribute \src "libresoc.v:198911.3-198935.6"
+ process $proc$libresoc.v:198911$13599
assign { } { }
assign { } { }
assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:199968.5-199968.29"
+ attribute \src "libresoc.v:198912.5-198912.29"
switch \initial
- attribute \src "libresoc.v:199968.9-199968.17"
+ attribute \src "libresoc.v:198912.9-198912.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
assign { } { }
assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
switch \$254
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_ivalid_i $0\core_ivalid_i[0:0]
end
- attribute \src "libresoc.v:199992.3-200007.6"
- process $proc$libresoc.v:199992$13788
+ attribute \src "libresoc.v:198936.3-198951.6"
+ process $proc$libresoc.v:198936$13600
assign { } { }
assign { } { }
assign $0\core_issue_i[0:0] $1\core_issue_i[0:0]
- attribute \src "libresoc.v:199993.5-199993.29"
+ attribute \src "libresoc.v:198937.5-198937.29"
switch \initial
- attribute \src "libresoc.v:199993.9-199993.17"
+ attribute \src "libresoc.v:198937.9-198937.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_issue_i[0:0] $2\core_issue_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_issue_i $0\core_issue_i[0:0]
end
- attribute \src "libresoc.v:200008.3-200042.6"
- process $proc$libresoc.v:200008$13789
+ attribute \src "libresoc.v:198952.3-198986.6"
+ process $proc$libresoc.v:198952$13601
assign { } { }
assign { } { }
assign { } { }
- assign $0\exec_fsm_state$next[0:0]$13790 $5\exec_fsm_state$next[0:0]$13795
- attribute \src "libresoc.v:200009.5-200009.29"
+ assign $0\exec_fsm_state$next[0:0]$13602 $5\exec_fsm_state$next[0:0]$13607
+ attribute \src "libresoc.v:198953.5-198953.29"
switch \initial
- attribute \src "libresoc.v:200009.9-200009.17"
+ attribute \src "libresoc.v:198953.9-198953.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13791 $2\exec_fsm_state$next[0:0]$13792
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715"
+ assign $1\exec_fsm_state$next[0:0]$13603 $2\exec_fsm_state$next[0:0]$13604
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\exec_fsm_state$next[0:0]$13792 1'1
+ assign $2\exec_fsm_state$next[0:0]$13604 1'1
case
- assign $2\exec_fsm_state$next[0:0]$13792 \exec_fsm_state
+ assign $2\exec_fsm_state$next[0:0]$13604 \exec_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13791 $3\exec_fsm_state$next[0:0]$13793
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ assign $1\exec_fsm_state$next[0:0]$13603 $3\exec_fsm_state$next[0:0]$13605
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
switch \$256
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\exec_fsm_state$next[0:0]$13793 $4\exec_fsm_state$next[0:0]$13794
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733"
+ assign $3\exec_fsm_state$next[0:0]$13605 $4\exec_fsm_state$next[0:0]$13606
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:736"
switch \exec_pc_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\exec_fsm_state$next[0:0]$13794 1'0
+ assign $4\exec_fsm_state$next[0:0]$13606 1'0
case
- assign $4\exec_fsm_state$next[0:0]$13794 \exec_fsm_state
+ assign $4\exec_fsm_state$next[0:0]$13606 \exec_fsm_state
end
case
- assign $3\exec_fsm_state$next[0:0]$13793 \exec_fsm_state
+ assign $3\exec_fsm_state$next[0:0]$13605 \exec_fsm_state
end
case
- assign $1\exec_fsm_state$next[0:0]$13791 \exec_fsm_state
+ assign $1\exec_fsm_state$next[0:0]$13603 \exec_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\exec_fsm_state$next[0:0]$13795 1'0
+ assign $5\exec_fsm_state$next[0:0]$13607 1'0
case
- assign $5\exec_fsm_state$next[0:0]$13795 $1\exec_fsm_state$next[0:0]$13791
+ assign $5\exec_fsm_state$next[0:0]$13607 $1\exec_fsm_state$next[0:0]$13603
end
sync always
- update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13790
+ update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13602
end
- attribute \src "libresoc.v:200043.3-200062.6"
- process $proc$libresoc.v:200043$13796
+ attribute \src "libresoc.v:198987.3-199006.6"
+ process $proc$libresoc.v:198987$13608
assign { } { }
assign { } { }
assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:200044.5-200044.29"
+ attribute \src "libresoc.v:198988.5-198988.29"
switch \initial
- attribute \src "libresoc.v:200044.9-200044.17"
+ attribute \src "libresoc.v:198988.9-198988.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
case 1'1
assign { } { }
assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
switch \$258
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \exec_pc_valid_o $0\exec_pc_valid_o[0:0]
end
- attribute \src "libresoc.v:200063.3-200072.6"
- process $proc$libresoc.v:200063$13797
+ attribute \src "libresoc.v:199007.3-199016.6"
+ process $proc$libresoc.v:199007$13609
assign { } { }
assign { } { }
assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:200064.5-200064.29"
+ attribute \src "libresoc.v:199008.5-199008.29"
switch \initial
- attribute \src "libresoc.v:200064.9-200064.17"
+ attribute \src "libresoc.v:199008.9-199008.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__addr $0\core_dmi__addr[4:0]
end
- attribute \src "libresoc.v:200073.3-200082.6"
- process $proc$libresoc.v:200073$13798
+ attribute \src "libresoc.v:199017.3-199026.6"
+ process $proc$libresoc.v:199017$13610
assign { } { }
assign { } { }
assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:200074.5-200074.29"
+ attribute \src "libresoc.v:199018.5-199018.29"
switch \initial
- attribute \src "libresoc.v:200074.9-200074.17"
+ attribute \src "libresoc.v:199018.9-199018.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__ren $0\core_dmi__ren[0:0]
end
- attribute \src "libresoc.v:200083.3-200091.6"
- process $proc$libresoc.v:200083$13799
+ attribute \src "libresoc.v:199027.3-199035.6"
+ process $proc$libresoc.v:199027$13611
assign { } { }
assign { } { }
- assign $0\d_reg_delay$next[0:0]$13800 $1\d_reg_delay$next[0:0]$13801
- attribute \src "libresoc.v:200084.5-200084.29"
+ assign $0\d_reg_delay$next[0:0]$13612 $1\d_reg_delay$next[0:0]$13613
+ attribute \src "libresoc.v:199028.5-199028.29"
switch \initial
- attribute \src "libresoc.v:200084.9-200084.17"
+ attribute \src "libresoc.v:199028.9-199028.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_reg_delay$next[0:0]$13801 1'0
+ assign $1\d_reg_delay$next[0:0]$13613 1'0
case
- assign $1\d_reg_delay$next[0:0]$13801 \dbg_d_gpr_req
+ assign $1\d_reg_delay$next[0:0]$13613 \dbg_d_gpr_req
end
sync always
- update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13800
+ update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13612
end
- attribute \src "libresoc.v:200092.3-200101.6"
- process $proc$libresoc.v:200092$13802
+ attribute \src "libresoc.v:199036.3-199045.6"
+ process $proc$libresoc.v:199036$13614
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:200093.5-200093.29"
+ attribute \src "libresoc.v:199037.5-199037.29"
switch \initial
- attribute \src "libresoc.v:200093.9-200093.17"
+ attribute \src "libresoc.v:199037.9-199037.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:200102.3-200111.6"
- process $proc$libresoc.v:200102$13803
+ attribute \src "libresoc.v:199046.3-199055.6"
+ process $proc$libresoc.v:199046$13615
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:200103.5-200103.29"
+ attribute \src "libresoc.v:199047.5-199047.29"
switch \initial
- attribute \src "libresoc.v:200103.9-200103.17"
+ attribute \src "libresoc.v:199047.9-199047.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:200112.3-200121.6"
- process $proc$libresoc.v:200112$13804
+ attribute \src "libresoc.v:199056.3-199065.6"
+ process $proc$libresoc.v:199056$13616
assign { } { }
assign { } { }
assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:200113.5-200113.29"
+ attribute \src "libresoc.v:199057.5-199057.29"
switch \initial
- attribute \src "libresoc.v:200113.9-200113.17"
+ attribute \src "libresoc.v:199057.9-199057.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958"
switch \dbg_d_cr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd2__ren $0\core_full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:200122.3-200130.6"
- process $proc$libresoc.v:200122$13805
+ attribute \src "libresoc.v:199066.3-199074.6"
+ process $proc$libresoc.v:199066$13617
assign { } { }
assign { } { }
- assign $0\d_cr_delay$next[0:0]$13806 $1\d_cr_delay$next[0:0]$13807
- attribute \src "libresoc.v:200123.5-200123.29"
+ assign $0\d_cr_delay$next[0:0]$13618 $1\d_cr_delay$next[0:0]$13619
+ attribute \src "libresoc.v:199067.5-199067.29"
switch \initial
- attribute \src "libresoc.v:200123.9-200123.17"
+ attribute \src "libresoc.v:199067.9-199067.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_cr_delay$next[0:0]$13807 1'0
+ assign $1\d_cr_delay$next[0:0]$13619 1'0
case
- assign $1\d_cr_delay$next[0:0]$13807 \dbg_d_cr_req
+ assign $1\d_cr_delay$next[0:0]$13619 \dbg_d_cr_req
end
sync always
- update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13806
+ update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13618
end
- attribute \src "libresoc.v:200131.3-200140.6"
- process $proc$libresoc.v:200131$13808
+ attribute \src "libresoc.v:199075.3-199084.6"
+ process $proc$libresoc.v:199075$13620
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:200132.5-200132.29"
+ attribute \src "libresoc.v:199076.5-199076.29"
switch \initial
- attribute \src "libresoc.v:200132.9-200132.17"
+ attribute \src "libresoc.v:199076.9-199076.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:962"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:200141.3-200150.6"
- process $proc$libresoc.v:200141$13809
+ attribute \src "libresoc.v:199085.3-199094.6"
+ process $proc$libresoc.v:199085$13621
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:200142.5-200142.29"
+ attribute \src "libresoc.v:199086.5-199086.29"
switch \initial
- attribute \src "libresoc.v:200142.9-200142.17"
+ attribute \src "libresoc.v:199086.9-199086.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:962"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:200151.3-200160.6"
- process $proc$libresoc.v:200151$13810
+ attribute \src "libresoc.v:199095.3-199104.6"
+ process $proc$libresoc.v:199095$13622
assign { } { }
assign { } { }
assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:200152.5-200152.29"
+ attribute \src "libresoc.v:199096.5-199096.29"
switch \initial
- attribute \src "libresoc.v:200152.9-200152.17"
+ attribute \src "libresoc.v:199096.9-199096.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:965"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968"
switch \dbg_d_xer_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd__ren $0\core_full_rd__ren[2:0]
end
- attribute \src "libresoc.v:200161.3-200169.6"
- process $proc$libresoc.v:200161$13811
+ attribute \src "libresoc.v:199105.3-199113.6"
+ process $proc$libresoc.v:199105$13623
assign { } { }
assign { } { }
- assign $0\d_xer_delay$next[0:0]$13812 $1\d_xer_delay$next[0:0]$13813
- attribute \src "libresoc.v:200162.5-200162.29"
+ assign $0\d_xer_delay$next[0:0]$13624 $1\d_xer_delay$next[0:0]$13625
+ attribute \src "libresoc.v:199106.5-199106.29"
switch \initial
- attribute \src "libresoc.v:200162.9-200162.17"
+ attribute \src "libresoc.v:199106.9-199106.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_xer_delay$next[0:0]$13813 1'0
+ assign $1\d_xer_delay$next[0:0]$13625 1'0
case
- assign $1\d_xer_delay$next[0:0]$13813 \dbg_d_xer_req
+ assign $1\d_xer_delay$next[0:0]$13625 \dbg_d_xer_req
end
sync always
- update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13812
+ update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13624
end
- attribute \src "libresoc.v:200170.3-200179.6"
- process $proc$libresoc.v:200170$13814
+ attribute \src "libresoc.v:199114.3-199123.6"
+ process $proc$libresoc.v:199114$13626
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:200171.5-200171.29"
+ attribute \src "libresoc.v:199115.5-199115.29"
switch \initial
- attribute \src "libresoc.v:200171.9-200171.17"
+ attribute \src "libresoc.v:199115.9-199115.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:969"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:200180.3-200189.6"
- process $proc$libresoc.v:200180$13815
+ attribute \src "libresoc.v:199124.3-199133.6"
+ process $proc$libresoc.v:199124$13627
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:200181.5-200181.29"
+ attribute \src "libresoc.v:199125.5-199125.29"
switch \initial
- attribute \src "libresoc.v:200181.9-200181.17"
+ attribute \src "libresoc.v:199125.9-199125.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:969"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:200190.3-200208.6"
- process $proc$libresoc.v:200190$13816
+ attribute \src "libresoc.v:199134.3-199152.6"
+ process $proc$libresoc.v:199134$13628
assign { } { }
assign { } { }
assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:200191.5-200191.29"
+ attribute \src "libresoc.v:199135.5-199135.29"
switch \initial
- attribute \src "libresoc.v:200191.9-200191.17"
+ attribute \src "libresoc.v:199135.9-199135.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__addr $0\core_issue__addr[2:0]
end
- attribute \src "libresoc.v:200209.3-200227.6"
- process $proc$libresoc.v:200209$13817
+ attribute \src "libresoc.v:199153.3-199171.6"
+ process $proc$libresoc.v:199153$13629
assign { } { }
assign { } { }
assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:200210.5-200210.29"
+ attribute \src "libresoc.v:199154.5-199154.29"
switch \initial
- attribute \src "libresoc.v:200210.9-200210.17"
+ attribute \src "libresoc.v:199154.9-199154.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__ren $0\core_issue__ren[0:0]
end
- attribute \src "libresoc.v:200228.3-200255.6"
- process $proc$libresoc.v:200228$13818
+ attribute \src "libresoc.v:199172.3-199199.6"
+ process $proc$libresoc.v:199172$13630
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$13819 $2\fsm_state$next[1:0]$13821
- attribute \src "libresoc.v:200229.5-200229.29"
+ assign $0\fsm_state$next[1:0]$13631 $2\fsm_state$next[1:0]$13633
+ attribute \src "libresoc.v:199173.5-199173.29"
switch \initial
- attribute \src "libresoc.v:200229.9-200229.17"
+ attribute \src "libresoc.v:199173.9-199173.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$13820 2'01
+ assign $1\fsm_state$next[1:0]$13632 2'01
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$13820 2'10
+ assign $1\fsm_state$next[1:0]$13632 2'10
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$13820 2'11
+ assign $1\fsm_state$next[1:0]$13632 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$next[1:0]$13820 2'00
+ assign $1\fsm_state$next[1:0]$13632 2'00
case
- assign $1\fsm_state$next[1:0]$13820 \fsm_state
+ assign $1\fsm_state$next[1:0]$13632 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$13821 2'00
+ assign $2\fsm_state$next[1:0]$13633 2'00
case
- assign $2\fsm_state$next[1:0]$13821 $1\fsm_state$next[1:0]$13820
+ assign $2\fsm_state$next[1:0]$13633 $1\fsm_state$next[1:0]$13632
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$13819
+ update \fsm_state$next $0\fsm_state$next[1:0]$13631
end
- attribute \src "libresoc.v:200256.3-200270.6"
- process $proc$libresoc.v:200256$13822
+ attribute \src "libresoc.v:199200.3-199214.6"
+ process $proc$libresoc.v:199200$13634
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:200257.5-200257.29"
+ attribute \src "libresoc.v:199201.5-199201.29"
switch \initial
- attribute \src "libresoc.v:200257.9-200257.17"
+ attribute \src "libresoc.v:199201.9-199201.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:200271.3-200293.6"
- process $proc$libresoc.v:200271$13823
+ attribute \src "libresoc.v:199215.3-199237.6"
+ process $proc$libresoc.v:199215$13635
assign { } { }
assign { } { }
- assign $0\core_issue__addr$13[2:0]$13824 $1\core_issue__addr$13[2:0]$13825
- attribute \src "libresoc.v:200272.5-200272.29"
+ assign $0\core_issue__addr$13[2:0]$13636 $1\core_issue__addr$13[2:0]$13637
+ attribute \src "libresoc.v:199216.5-199216.29"
switch \initial
- attribute \src "libresoc.v:200272.9-200272.17"
+ attribute \src "libresoc.v:199216.9-199216.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\core_issue__addr$13[2:0]$13825 3'000
+ assign $1\core_issue__addr$13[2:0]$13637 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13825 3'110
+ assign $1\core_issue__addr$13[2:0]$13637 3'110
attribute \src "libresoc.v:0.0-0.0"
case 2'10
- assign $1\core_issue__addr$13[2:0]$13825 3'000
+ assign $1\core_issue__addr$13[2:0]$13637 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13825 3'111
+ assign $1\core_issue__addr$13[2:0]$13637 3'111
case
- assign $1\core_issue__addr$13[2:0]$13825 3'000
+ assign $1\core_issue__addr$13[2:0]$13637 3'000
end
sync always
- update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13824
+ update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13636
end
- attribute \src "libresoc.v:200294.3-200316.6"
- process $proc$libresoc.v:200294$13826
+ attribute \src "libresoc.v:199238.3-199260.6"
+ process $proc$libresoc.v:199238$13638
assign { } { }
assign { } { }
assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:200295.5-200295.29"
+ attribute \src "libresoc.v:199239.5-199239.29"
switch \initial
- attribute \src "libresoc.v:200295.9-200295.17"
+ attribute \src "libresoc.v:199239.9-199239.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__wen $0\core_issue__wen[0:0]
end
- attribute \src "libresoc.v:200317.3-200339.6"
- process $proc$libresoc.v:200317$13827
+ attribute \src "libresoc.v:199261.3-199283.6"
+ process $proc$libresoc.v:199261$13639
assign { } { }
assign { } { }
assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:200318.5-200318.29"
+ attribute \src "libresoc.v:199262.5-199262.29"
switch \initial
- attribute \src "libresoc.v:200318.9-200318.17"
+ attribute \src "libresoc.v:199262.9-199262.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__data_i $0\core_issue__data_i[63:0]
end
- attribute \src "libresoc.v:200340.3-200359.6"
- process $proc$libresoc.v:200340$13828
+ attribute \src "libresoc.v:199284.3-199303.6"
+ process $proc$libresoc.v:199284$13640
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_dec$next[63:0]$13829 $2\dec2_cur_dec$next[63:0]$13831
- attribute \src "libresoc.v:200341.5-200341.29"
+ assign $0\dec2_cur_dec$next[63:0]$13641 $2\dec2_cur_dec$next[63:0]$13643
+ attribute \src "libresoc.v:199285.5-199285.29"
switch \initial
- attribute \src "libresoc.v:200341.9-200341.17"
+ attribute \src "libresoc.v:199285.9-199285.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_cur_dec$next[63:0]$13830 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$13642 \dec2_cur_dec
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_dec$next[63:0]$13830 \new_dec
+ assign $1\dec2_cur_dec$next[63:0]$13642 \new_dec
case
- assign $1\dec2_cur_dec$next[63:0]$13830 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$13642 \dec2_cur_dec
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_dec$next[63:0]$13831 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dec2_cur_dec$next[63:0]$13643 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\dec2_cur_dec$next[63:0]$13831 $1\dec2_cur_dec$next[63:0]$13830
+ assign $2\dec2_cur_dec$next[63:0]$13643 $1\dec2_cur_dec$next[63:0]$13642
end
sync always
- update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13829
+ update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13641
end
- attribute \src "libresoc.v:200360.3-200382.6"
- process $proc$libresoc.v:200360$13832
+ attribute \src "libresoc.v:199304.3-199326.6"
+ process $proc$libresoc.v:199304$13644
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:200361.5-200361.29"
+ attribute \src "libresoc.v:199305.5-199305.29"
switch \initial
- attribute \src "libresoc.v:200361.9-200361.17"
+ attribute \src "libresoc.v:199305.9-199305.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:200383.3-200391.6"
- process $proc$libresoc.v:200383$13833
+ attribute \src "libresoc.v:199327.3-199335.6"
+ process $proc$libresoc.v:199327$13645
assign { } { }
assign { } { }
- assign $0\dbg_dmi_we_i$next[0:0]$13834 $1\dbg_dmi_we_i$next[0:0]$13835
- attribute \src "libresoc.v:200384.5-200384.29"
+ assign $0\dbg_dmi_we_i$next[0:0]$13646 $1\dbg_dmi_we_i$next[0:0]$13647
+ attribute \src "libresoc.v:199328.5-199328.29"
switch \initial
- attribute \src "libresoc.v:200384.9-200384.17"
+ attribute \src "libresoc.v:199328.9-199328.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_we_i$next[0:0]$13835 1'0
+ assign $1\dbg_dmi_we_i$next[0:0]$13647 1'0
case
- assign $1\dbg_dmi_we_i$next[0:0]$13835 \jtag_dmi0__we_i
+ assign $1\dbg_dmi_we_i$next[0:0]$13647 \jtag_dmi0__we_i
end
sync always
- update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13834
+ update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13646
end
- attribute \src "libresoc.v:200392.3-200400.6"
- process $proc$libresoc.v:200392$13836
+ attribute \src "libresoc.v:199336.3-199344.6"
+ process $proc$libresoc.v:199336$13648
assign { } { }
assign { } { }
- assign $0\pc_ok_delay$next[0:0]$13837 $1\pc_ok_delay$next[0:0]$13838
- attribute \src "libresoc.v:200393.5-200393.29"
+ assign $0\pc_ok_delay$next[0:0]$13649 $1\pc_ok_delay$next[0:0]$13650
+ attribute \src "libresoc.v:199337.5-199337.29"
switch \initial
- attribute \src "libresoc.v:200393.9-200393.17"
+ attribute \src "libresoc.v:199337.9-199337.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pc_ok_delay$next[0:0]$13838 1'0
+ assign $1\pc_ok_delay$next[0:0]$13650 1'0
case
- assign $1\pc_ok_delay$next[0:0]$13838 \$38
+ assign $1\pc_ok_delay$next[0:0]$13650 \$38
end
sync always
- update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13837
+ update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13649
end
- attribute \src "libresoc.v:200401.3-200416.6"
- process $proc$libresoc.v:200401$13839
+ attribute \src "libresoc.v:199345.3-199360.6"
+ process $proc$libresoc.v:199345$13651
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:200402.5-200402.29"
+ attribute \src "libresoc.v:199346.5-199346.29"
switch \initial
- attribute \src "libresoc.v:200402.9-200402.17"
+ attribute \src "libresoc.v:199346.9-199346.17"
case 1'1
case
end
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:200417.3-200429.6"
- process $proc$libresoc.v:200417$13840
+ attribute \src "libresoc.v:199361.3-199373.6"
+ process $proc$libresoc.v:199361$13652
assign { } { }
assign { } { }
assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:200418.5-200418.29"
+ attribute \src "libresoc.v:199362.5-199362.29"
switch \initial
- attribute \src "libresoc.v:200418.9-200418.17"
+ attribute \src "libresoc.v:199362.9-199362.17"
case 1'1
case
end
sync always
update \core_cia__ren $0\core_cia__ren[2:0]
end
- attribute \src "libresoc.v:200430.3-200438.6"
- process $proc$libresoc.v:200430$13841
+ attribute \src "libresoc.v:199374.3-199382.6"
+ process $proc$libresoc.v:199374$13653
assign { } { }
assign { } { }
- assign $0\svstate_ok_delay$next[0:0]$13842 $1\svstate_ok_delay$next[0:0]$13843
- attribute \src "libresoc.v:200431.5-200431.29"
+ assign $0\svstate_ok_delay$next[0:0]$13654 $1\svstate_ok_delay$next[0:0]$13655
+ attribute \src "libresoc.v:199375.5-199375.29"
switch \initial
- attribute \src "libresoc.v:200431.9-200431.17"
+ attribute \src "libresoc.v:199375.9-199375.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\svstate_ok_delay$next[0:0]$13843 1'0
+ assign $1\svstate_ok_delay$next[0:0]$13655 1'0
case
- assign $1\svstate_ok_delay$next[0:0]$13843 \$40
+ assign $1\svstate_ok_delay$next[0:0]$13655 \$40
end
sync always
- update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13842
+ update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13654
end
- attribute \src "libresoc.v:200439.3-200454.6"
- process $proc$libresoc.v:200439$13844
+ attribute \src "libresoc.v:199383.3-199398.6"
+ process $proc$libresoc.v:199383$13656
assign { } { }
assign { } { }
assign { } { }
assign $0\svstate[63:0] $2\svstate[63:0]
- attribute \src "libresoc.v:200440.5-200440.29"
+ attribute \src "libresoc.v:199384.5-199384.29"
switch \initial
- attribute \src "libresoc.v:200440.9-200440.17"
+ attribute \src "libresoc.v:199384.9-199384.17"
case 1'1
case
end
sync always
update \svstate $0\svstate[63:0]
end
- attribute \src "libresoc.v:200455.3-200467.6"
- process $proc$libresoc.v:200455$13845
+ attribute \src "libresoc.v:199399.3-199411.6"
+ process $proc$libresoc.v:199399$13657
assign { } { }
assign { } { }
assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:200456.5-200456.29"
+ attribute \src "libresoc.v:199400.5-199400.29"
switch \initial
- attribute \src "libresoc.v:200456.9-200456.17"
+ attribute \src "libresoc.v:199400.9-199400.17"
case 1'1
case
end
sync always
update \core_sv__ren $0\core_sv__ren[2:0]
end
- attribute \src "libresoc.v:200468.3-200547.6"
- process $proc$libresoc.v:200468$13846
+ attribute \src "libresoc.v:199412.3-199491.6"
+ process $proc$libresoc.v:199412$13658
assign { } { }
assign { } { }
assign $0\core_wen[2:0] $1\core_wen[2:0]
- attribute \src "libresoc.v:200469.5-200469.29"
+ attribute \src "libresoc.v:199413.5-199413.29"
switch \initial
- attribute \src "libresoc.v:200469.9-200469.17"
+ attribute \src "libresoc.v:199413.9-199413.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_wen[2:0] $2\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$48
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\core_wen[2:0] $3\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'001
assign { } { }
assign $1\core_wen[2:0] $4\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\core_wen[2:0] $5\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
switch \$52
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_wen[2:0] $6\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$58
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $6\core_wen[2:0] $7\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $7\core_wen[2:0] $8\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
switch { \$64 \$60 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $6\core_wen[2:0] $9\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_wen $0\core_wen[2:0]
end
- attribute \src "libresoc.v:200548.3-200627.6"
- process $proc$libresoc.v:200548$13847
+ attribute \src "libresoc.v:199492.3-199571.6"
+ process $proc$libresoc.v:199492$13659
assign { } { }
assign { } { }
assign $0\core_data_i[63:0] $1\core_data_i[63:0]
- attribute \src "libresoc.v:200549.5-200549.29"
+ attribute \src "libresoc.v:199493.5-199493.29"
switch \initial
- attribute \src "libresoc.v:200549.9-200549.17"
+ attribute \src "libresoc.v:199493.9-199493.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_data_i[63:0] $2\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$70
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\core_data_i[63:0] $3\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'001
assign { } { }
assign $1\core_data_i[63:0] $4\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\core_data_i[63:0] $5\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
switch \$74
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_data_i[63:0] $6\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$80
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $6\core_data_i[63:0] $7\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $7\core_data_i[63:0] $8\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
switch { \$86 \$82 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $6\core_data_i[63:0] $9\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_data_i $0\core_data_i[63:0]
end
- attribute \src "libresoc.v:200628.3-200643.6"
- process $proc$libresoc.v:200628$13848
+ attribute \src "libresoc.v:199572.3-199587.6"
+ process $proc$libresoc.v:199572$13660
assign { } { }
assign { } { }
assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:200629.5-200629.29"
+ attribute \src "libresoc.v:199573.5-199573.29"
switch \initial
- attribute \src "libresoc.v:200629.9-200629.17"
+ attribute \src "libresoc.v:199573.9-199573.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_msr__ren $0\core_msr__ren[2:0]
end
- attribute \src "libresoc.v:200644.3-200652.6"
- process $proc$libresoc.v:200644$13849
+ attribute \src "libresoc.v:199588.3-199596.6"
+ process $proc$libresoc.v:199588$13661
assign { } { }
assign { } { }
- assign $0\dbg_dmi_din$next[63:0]$13850 $1\dbg_dmi_din$next[63:0]$13851
- attribute \src "libresoc.v:200645.5-200645.29"
+ assign $0\dbg_dmi_din$next[63:0]$13662 $1\dbg_dmi_din$next[63:0]$13663
+ attribute \src "libresoc.v:199589.5-199589.29"
switch \initial
- attribute \src "libresoc.v:200645.9-200645.17"
+ attribute \src "libresoc.v:199589.9-199589.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_din$next[63:0]$13851 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\dbg_dmi_din$next[63:0]$13663 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\dbg_dmi_din$next[63:0]$13851 \jtag_dmi0__din
+ assign $1\dbg_dmi_din$next[63:0]$13663 \jtag_dmi0__din
end
sync always
- update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13850
+ update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13662
end
- attribute \src "libresoc.v:200653.3-200663.6"
- process $proc$libresoc.v:200653$13852
+ attribute \src "libresoc.v:199597.3-199607.6"
+ process $proc$libresoc.v:199597$13664
assign { } { }
assign { } { }
assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:200654.5-200654.29"
+ attribute \src "libresoc.v:199598.5-199598.29"
switch \initial
- attribute \src "libresoc.v:200654.9-200654.17"
+ attribute \src "libresoc.v:199598.9-199598.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0]
end
- attribute \src "libresoc.v:200664.3-200679.6"
- process $proc$libresoc.v:200664$13853
+ attribute \src "libresoc.v:199608.3-199623.6"
+ process $proc$libresoc.v:199608$13665
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:200665.5-200665.29"
+ attribute \src "libresoc.v:199609.5-199609.29"
switch \initial
- attribute \src "libresoc.v:200665.9-200665.17"
+ attribute \src "libresoc.v:199609.9-199609.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:200680.3-200688.6"
- process $proc$libresoc.v:200680$13854
+ attribute \src "libresoc.v:199624.3-199632.6"
+ process $proc$libresoc.v:199624$13666
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__ack_o$next[0:0]$13855 $1\jtag_dmi0__ack_o$next[0:0]$13856
- attribute \src "libresoc.v:200681.5-200681.29"
+ assign $0\jtag_dmi0__ack_o$next[0:0]$13667 $1\jtag_dmi0__ack_o$next[0:0]$13668
+ attribute \src "libresoc.v:199625.5-199625.29"
switch \initial
- attribute \src "libresoc.v:200681.9-200681.17"
+ attribute \src "libresoc.v:199625.9-199625.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__ack_o$next[0:0]$13856 1'0
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13668 1'0
case
- assign $1\jtag_dmi0__ack_o$next[0:0]$13856 \dbg_dmi_ack_o
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13668 \dbg_dmi_ack_o
end
sync always
- update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13855
+ update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13667
end
- attribute \src "libresoc.v:200689.3-200722.6"
- process $proc$libresoc.v:200689$13857
+ attribute \src "libresoc.v:199633.3-199666.6"
+ process $proc$libresoc.v:199633$13669
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:200690.5-200690.29"
+ attribute \src "libresoc.v:199634.5-199634.29"
switch \initial
- attribute \src "libresoc.v:200690.9-200690.17"
+ attribute \src "libresoc.v:199634.9-199634.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'11
assign { } { }
assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:200723.3-200756.6"
- process $proc$libresoc.v:200723$13858
+ attribute \src "libresoc.v:199667.3-199700.6"
+ process $proc$libresoc.v:199667$13670
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:200724.5-200724.29"
+ attribute \src "libresoc.v:199668.5-199668.29"
switch \initial
- attribute \src "libresoc.v:200724.9-200724.17"
+ attribute \src "libresoc.v:199668.9-199668.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'11
assign { } { }
assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:200757.3-200777.6"
- process $proc$libresoc.v:200757$13859
+ attribute \src "libresoc.v:199701.3-199721.6"
+ process $proc$libresoc.v:199701$13671
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_pc$next[63:0]$13860 $3\dec2_cur_pc$next[63:0]$13863
- attribute \src "libresoc.v:200758.5-200758.29"
+ assign $0\dec2_cur_pc$next[63:0]$13672 $3\dec2_cur_pc$next[63:0]$13675
+ attribute \src "libresoc.v:199702.5-199702.29"
switch \initial
- attribute \src "libresoc.v:200758.9-200758.17"
+ attribute \src "libresoc.v:199702.9-199702.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\dec2_cur_pc$next[63:0]$13861 $2\dec2_cur_pc$next[63:0]$13862
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ assign $1\dec2_cur_pc$next[63:0]$13673 $2\dec2_cur_pc$next[63:0]$13674
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_pc$next[63:0]$13862 \pc
+ assign $2\dec2_cur_pc$next[63:0]$13674 \pc
case
- assign $2\dec2_cur_pc$next[63:0]$13862 \dec2_cur_pc
+ assign $2\dec2_cur_pc$next[63:0]$13674 \dec2_cur_pc
end
case
- assign $1\dec2_cur_pc$next[63:0]$13861 \dec2_cur_pc
+ assign $1\dec2_cur_pc$next[63:0]$13673 \dec2_cur_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_pc$next[63:0]$13863 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_pc$next[63:0]$13675 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_pc$next[63:0]$13863 $1\dec2_cur_pc$next[63:0]$13861
+ assign $3\dec2_cur_pc$next[63:0]$13675 $1\dec2_cur_pc$next[63:0]$13673
end
sync always
- update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13860
+ update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13672
end
- attribute \src "libresoc.v:200778.3-200816.6"
- process $proc$libresoc.v:200778$13864
+ attribute \src "libresoc.v:199722.3-199760.6"
+ process $proc$libresoc.v:199722$13676
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cur_cur_dststep$next[6:0]$13865 $4\cur_cur_dststep$next[6:0]$13889
- assign $0\cur_cur_maxvl$next[6:0]$13866 $4\cur_cur_maxvl$next[6:0]$13890
- assign $0\cur_cur_srcstep$next[6:0]$13867 $4\cur_cur_srcstep$next[6:0]$13891
- assign $0\cur_cur_subvl$next[1:0]$13868 $4\cur_cur_subvl$next[1:0]$13892
- assign $0\cur_cur_svstep$next[1:0]$13869 $4\cur_cur_svstep$next[1:0]$13893
- assign $0\cur_cur_vl$next[6:0]$13870 $4\cur_cur_vl$next[6:0]$13894
- attribute \src "libresoc.v:200779.5-200779.29"
+ assign $0\cur_cur_dststep$next[6:0]$13677 $4\cur_cur_dststep$next[6:0]$13701
+ assign $0\cur_cur_maxvl$next[6:0]$13678 $4\cur_cur_maxvl$next[6:0]$13702
+ assign $0\cur_cur_srcstep$next[6:0]$13679 $4\cur_cur_srcstep$next[6:0]$13703
+ assign $0\cur_cur_subvl$next[1:0]$13680 $4\cur_cur_subvl$next[1:0]$13704
+ assign $0\cur_cur_svstep$next[1:0]$13681 $4\cur_cur_svstep$next[1:0]$13705
+ assign $0\cur_cur_vl$next[6:0]$13682 $4\cur_cur_vl$next[6:0]$13706
+ attribute \src "libresoc.v:199723.5-199723.29"
switch \initial
- attribute \src "libresoc.v:200779.9-200779.17"
+ attribute \src "libresoc.v:199723.9-199723.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign { } { }
assign { } { }
- assign $1\cur_cur_dststep$next[6:0]$13871 $2\cur_cur_dststep$next[6:0]$13877
- assign $1\cur_cur_maxvl$next[6:0]$13872 $2\cur_cur_maxvl$next[6:0]$13878
- assign $1\cur_cur_srcstep$next[6:0]$13873 $2\cur_cur_srcstep$next[6:0]$13879
- assign $1\cur_cur_subvl$next[1:0]$13874 $2\cur_cur_subvl$next[1:0]$13880
- assign $1\cur_cur_svstep$next[1:0]$13875 $2\cur_cur_svstep$next[1:0]$13881
- assign $1\cur_cur_vl$next[6:0]$13876 $2\cur_cur_vl$next[6:0]$13882
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ assign $1\cur_cur_dststep$next[6:0]$13683 $2\cur_cur_dststep$next[6:0]$13689
+ assign $1\cur_cur_maxvl$next[6:0]$13684 $2\cur_cur_maxvl$next[6:0]$13690
+ assign $1\cur_cur_srcstep$next[6:0]$13685 $2\cur_cur_srcstep$next[6:0]$13691
+ assign $1\cur_cur_subvl$next[1:0]$13686 $2\cur_cur_subvl$next[1:0]$13692
+ assign $1\cur_cur_svstep$next[1:0]$13687 $2\cur_cur_svstep$next[1:0]$13693
+ assign $1\cur_cur_vl$next[6:0]$13688 $2\cur_cur_vl$next[6:0]$13694
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\cur_cur_maxvl$next[6:0]$13878 $2\cur_cur_vl$next[6:0]$13882 $2\cur_cur_srcstep$next[6:0]$13879 $2\cur_cur_dststep$next[6:0]$13877 $2\cur_cur_subvl$next[1:0]$13880 $2\cur_cur_svstep$next[1:0]$13881 } \svstate [31:0]
+ assign { $2\cur_cur_maxvl$next[6:0]$13690 $2\cur_cur_vl$next[6:0]$13694 $2\cur_cur_srcstep$next[6:0]$13691 $2\cur_cur_dststep$next[6:0]$13689 $2\cur_cur_subvl$next[1:0]$13692 $2\cur_cur_svstep$next[1:0]$13693 } \svstate [31:0]
case
- assign $2\cur_cur_dststep$next[6:0]$13877 \cur_cur_dststep
- assign $2\cur_cur_maxvl$next[6:0]$13878 \cur_cur_maxvl
- assign $2\cur_cur_srcstep$next[6:0]$13879 \cur_cur_srcstep
- assign $2\cur_cur_subvl$next[1:0]$13880 \cur_cur_subvl
- assign $2\cur_cur_svstep$next[1:0]$13881 \cur_cur_svstep
- assign $2\cur_cur_vl$next[6:0]$13882 \cur_cur_vl
+ assign $2\cur_cur_dststep$next[6:0]$13689 \cur_cur_dststep
+ assign $2\cur_cur_maxvl$next[6:0]$13690 \cur_cur_maxvl
+ assign $2\cur_cur_srcstep$next[6:0]$13691 \cur_cur_srcstep
+ assign $2\cur_cur_subvl$next[1:0]$13692 \cur_cur_subvl
+ assign $2\cur_cur_svstep$next[1:0]$13693 \cur_cur_svstep
+ assign $2\cur_cur_vl$next[6:0]$13694 \cur_cur_vl
end
case
- assign $1\cur_cur_dststep$next[6:0]$13871 \cur_cur_dststep
- assign $1\cur_cur_maxvl$next[6:0]$13872 \cur_cur_maxvl
- assign $1\cur_cur_srcstep$next[6:0]$13873 \cur_cur_srcstep
- assign $1\cur_cur_subvl$next[1:0]$13874 \cur_cur_subvl
- assign $1\cur_cur_svstep$next[1:0]$13875 \cur_cur_svstep
- assign $1\cur_cur_vl$next[6:0]$13876 \cur_cur_vl
+ assign $1\cur_cur_dststep$next[6:0]$13683 \cur_cur_dststep
+ assign $1\cur_cur_maxvl$next[6:0]$13684 \cur_cur_maxvl
+ assign $1\cur_cur_srcstep$next[6:0]$13685 \cur_cur_srcstep
+ assign $1\cur_cur_subvl$next[1:0]$13686 \cur_cur_subvl
+ assign $1\cur_cur_svstep$next[1:0]$13687 \cur_cur_svstep
+ assign $1\cur_cur_vl$next[6:0]$13688 \cur_cur_vl
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $3\cur_cur_maxvl$next[6:0]$13884 $3\cur_cur_vl$next[6:0]$13888 $3\cur_cur_srcstep$next[6:0]$13885 $3\cur_cur_dststep$next[6:0]$13883 $3\cur_cur_subvl$next[1:0]$13886 $3\cur_cur_svstep$next[1:0]$13887 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
+ assign { $3\cur_cur_maxvl$next[6:0]$13696 $3\cur_cur_vl$next[6:0]$13700 $3\cur_cur_srcstep$next[6:0]$13697 $3\cur_cur_dststep$next[6:0]$13695 $3\cur_cur_subvl$next[1:0]$13698 $3\cur_cur_svstep$next[1:0]$13699 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
case
- assign $3\cur_cur_dststep$next[6:0]$13883 $1\cur_cur_dststep$next[6:0]$13871
- assign $3\cur_cur_maxvl$next[6:0]$13884 $1\cur_cur_maxvl$next[6:0]$13872
- assign $3\cur_cur_srcstep$next[6:0]$13885 $1\cur_cur_srcstep$next[6:0]$13873
- assign $3\cur_cur_subvl$next[1:0]$13886 $1\cur_cur_subvl$next[1:0]$13874
- assign $3\cur_cur_svstep$next[1:0]$13887 $1\cur_cur_svstep$next[1:0]$13875
- assign $3\cur_cur_vl$next[6:0]$13888 $1\cur_cur_vl$next[6:0]$13876
+ assign $3\cur_cur_dststep$next[6:0]$13695 $1\cur_cur_dststep$next[6:0]$13683
+ assign $3\cur_cur_maxvl$next[6:0]$13696 $1\cur_cur_maxvl$next[6:0]$13684
+ assign $3\cur_cur_srcstep$next[6:0]$13697 $1\cur_cur_srcstep$next[6:0]$13685
+ assign $3\cur_cur_subvl$next[1:0]$13698 $1\cur_cur_subvl$next[1:0]$13686
+ assign $3\cur_cur_svstep$next[1:0]$13699 $1\cur_cur_svstep$next[1:0]$13687
+ assign $3\cur_cur_vl$next[6:0]$13700 $1\cur_cur_vl$next[6:0]$13688
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\cur_cur_svstep$next[1:0]$13893 2'00
- assign $4\cur_cur_subvl$next[1:0]$13892 2'00
- assign $4\cur_cur_dststep$next[6:0]$13889 7'0000000
- assign $4\cur_cur_srcstep$next[6:0]$13891 7'0000000
- assign $4\cur_cur_vl$next[6:0]$13894 7'0000000
- assign $4\cur_cur_maxvl$next[6:0]$13890 7'0000000
+ assign $4\cur_cur_svstep$next[1:0]$13705 2'00
+ assign $4\cur_cur_subvl$next[1:0]$13704 2'00
+ assign $4\cur_cur_dststep$next[6:0]$13701 7'0000000
+ assign $4\cur_cur_srcstep$next[6:0]$13703 7'0000000
+ assign $4\cur_cur_vl$next[6:0]$13706 7'0000000
+ assign $4\cur_cur_maxvl$next[6:0]$13702 7'0000000
case
- assign $4\cur_cur_dststep$next[6:0]$13889 $3\cur_cur_dststep$next[6:0]$13883
- assign $4\cur_cur_maxvl$next[6:0]$13890 $3\cur_cur_maxvl$next[6:0]$13884
- assign $4\cur_cur_srcstep$next[6:0]$13891 $3\cur_cur_srcstep$next[6:0]$13885
- assign $4\cur_cur_subvl$next[1:0]$13892 $3\cur_cur_subvl$next[1:0]$13886
- assign $4\cur_cur_svstep$next[1:0]$13893 $3\cur_cur_svstep$next[1:0]$13887
- assign $4\cur_cur_vl$next[6:0]$13894 $3\cur_cur_vl$next[6:0]$13888
+ assign $4\cur_cur_dststep$next[6:0]$13701 $3\cur_cur_dststep$next[6:0]$13695
+ assign $4\cur_cur_maxvl$next[6:0]$13702 $3\cur_cur_maxvl$next[6:0]$13696
+ assign $4\cur_cur_srcstep$next[6:0]$13703 $3\cur_cur_srcstep$next[6:0]$13697
+ assign $4\cur_cur_subvl$next[1:0]$13704 $3\cur_cur_subvl$next[1:0]$13698
+ assign $4\cur_cur_svstep$next[1:0]$13705 $3\cur_cur_svstep$next[1:0]$13699
+ assign $4\cur_cur_vl$next[6:0]$13706 $3\cur_cur_vl$next[6:0]$13700
end
sync always
- update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13865
- update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13866
- update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13867
- update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13868
- update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13869
- update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13870
+ update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13677
+ update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13678
+ update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13679
+ update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13680
+ update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13681
+ update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13682
end
- attribute \src "libresoc.v:200817.3-200846.6"
- process $proc$libresoc.v:200817$13895
+ attribute \src "libresoc.v:199761.3-199790.6"
+ process $proc$libresoc.v:199761$13707
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr_read$next[0:0]$13896 $4\msr_read$next[0:0]$13900
- attribute \src "libresoc.v:200818.5-200818.29"
+ assign $0\msr_read$next[0:0]$13708 $4\msr_read$next[0:0]$13712
+ attribute \src "libresoc.v:199762.5-199762.29"
switch \initial
- attribute \src "libresoc.v:200818.9-200818.17"
+ attribute \src "libresoc.v:199762.9-199762.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\msr_read$next[0:0]$13897 $2\msr_read$next[0:0]$13898
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ assign $1\msr_read$next[0:0]$13709 $2\msr_read$next[0:0]$13710
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_read$next[0:0]$13898 1'0
+ assign $2\msr_read$next[0:0]$13710 1'0
case
- assign $2\msr_read$next[0:0]$13898 \msr_read
+ assign $2\msr_read$next[0:0]$13710 \msr_read
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\msr_read$next[0:0]$13897 $3\msr_read$next[0:0]$13899
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
+ assign $1\msr_read$next[0:0]$13709 $3\msr_read$next[0:0]$13711
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
switch \$88
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr_read$next[0:0]$13899 1'1
+ assign $3\msr_read$next[0:0]$13711 1'1
case
- assign $3\msr_read$next[0:0]$13899 \msr_read
+ assign $3\msr_read$next[0:0]$13711 \msr_read
end
case
- assign $1\msr_read$next[0:0]$13897 \msr_read
+ assign $1\msr_read$next[0:0]$13709 \msr_read
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr_read$next[0:0]$13900 1'1
+ assign $4\msr_read$next[0:0]$13712 1'1
case
- assign $4\msr_read$next[0:0]$13900 $1\msr_read$next[0:0]$13897
+ assign $4\msr_read$next[0:0]$13712 $1\msr_read$next[0:0]$13709
end
sync always
- update \msr_read$next $0\msr_read$next[0:0]$13896
+ update \msr_read$next $0\msr_read$next[0:0]$13708
end
- attribute \src "libresoc.v:200847.3-200855.6"
- process $proc$libresoc.v:200847$13901
+ attribute \src "libresoc.v:199791.3-199799.6"
+ process $proc$libresoc.v:199791$13713
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__dout$next[63:0]$13902 $1\jtag_dmi0__dout$next[63:0]$13903
- attribute \src "libresoc.v:200848.5-200848.29"
+ assign $0\jtag_dmi0__dout$next[63:0]$13714 $1\jtag_dmi0__dout$next[63:0]$13715
+ attribute \src "libresoc.v:199792.5-199792.29"
switch \initial
- attribute \src "libresoc.v:200848.9-200848.17"
+ attribute \src "libresoc.v:199792.9-199792.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__dout$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\jtag_dmi0__dout$next[63:0]$13715 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\jtag_dmi0__dout$next[63:0]$13903 \dbg_dmi_dout
+ assign $1\jtag_dmi0__dout$next[63:0]$13715 \dbg_dmi_dout
end
sync always
- update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13902
+ update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13714
end
- attribute \src "libresoc.v:200856.3-200909.6"
- process $proc$libresoc.v:200856$13904
+ attribute \src "libresoc.v:199800.3-199853.6"
+ process $proc$libresoc.v:199800$13716
assign { } { }
assign { } { }
assign { } { }
- assign $0\fetch_fsm_state$next[1:0]$13905 $6\fetch_fsm_state$next[1:0]$13911
- attribute \src "libresoc.v:200857.5-200857.29"
+ assign $0\fetch_fsm_state$next[1:0]$13717 $6\fetch_fsm_state$next[1:0]$13723
+ attribute \src "libresoc.v:199801.5-199801.29"
switch \initial
- attribute \src "libresoc.v:200857.9-200857.17"
+ attribute \src "libresoc.v:199801.9-199801.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13906 $2\fetch_fsm_state$next[1:0]$13907
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282"
+ assign $1\fetch_fsm_state$next[1:0]$13718 $2\fetch_fsm_state$next[1:0]$13719
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fetch_fsm_state$next[1:0]$13907 2'01
+ assign $2\fetch_fsm_state$next[1:0]$13719 2'01
case
- assign $2\fetch_fsm_state$next[1:0]$13907 \fetch_fsm_state
+ assign $2\fetch_fsm_state$next[1:0]$13719 \fetch_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13906 $3\fetch_fsm_state$next[1:0]$13908
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ assign $1\fetch_fsm_state$next[1:0]$13718 $3\fetch_fsm_state$next[1:0]$13720
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\fetch_fsm_state$next[1:0]$13908 \fetch_fsm_state
+ assign $3\fetch_fsm_state$next[1:0]$13720 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\fetch_fsm_state$next[1:0]$13908 2'10
+ assign $3\fetch_fsm_state$next[1:0]$13720 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13906 $4\fetch_fsm_state$next[1:0]$13909
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
+ assign $1\fetch_fsm_state$next[1:0]$13718 $4\fetch_fsm_state$next[1:0]$13721
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\fetch_fsm_state$next[1:0]$13909 \fetch_fsm_state
+ assign $4\fetch_fsm_state$next[1:0]$13721 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\fetch_fsm_state$next[1:0]$13909 2'10
+ assign $4\fetch_fsm_state$next[1:0]$13721 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13906 $5\fetch_fsm_state$next[1:0]$13910
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371"
+ assign $1\fetch_fsm_state$next[1:0]$13718 $5\fetch_fsm_state$next[1:0]$13722
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372"
switch \fetch_insn_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fetch_fsm_state$next[1:0]$13910 2'00
+ assign $5\fetch_fsm_state$next[1:0]$13722 2'00
case
- assign $5\fetch_fsm_state$next[1:0]$13910 \fetch_fsm_state
+ assign $5\fetch_fsm_state$next[1:0]$13722 \fetch_fsm_state
end
case
- assign $1\fetch_fsm_state$next[1:0]$13906 \fetch_fsm_state
+ assign $1\fetch_fsm_state$next[1:0]$13718 \fetch_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\fetch_fsm_state$next[1:0]$13911 2'00
+ assign $6\fetch_fsm_state$next[1:0]$13723 2'00
case
- assign $6\fetch_fsm_state$next[1:0]$13911 $1\fetch_fsm_state$next[1:0]$13906
+ assign $6\fetch_fsm_state$next[1:0]$13723 $1\fetch_fsm_state$next[1:0]$13718
end
sync always
- update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13905
+ update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13717
end
- attribute \src "libresoc.v:200910.3-200934.6"
- process $proc$libresoc.v:200910$13912
+ attribute \src "libresoc.v:199854.3-199878.6"
+ process $proc$libresoc.v:199854$13724
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_msr$next[63:0]$13913 $3\dec2_cur_msr$next[63:0]$13916
- attribute \src "libresoc.v:200911.5-200911.29"
+ assign $0\dec2_cur_msr$next[63:0]$13725 $3\dec2_cur_msr$next[63:0]$13728
+ attribute \src "libresoc.v:199855.5-199855.29"
switch \initial
- attribute \src "libresoc.v:200911.9-200911.17"
+ attribute \src "libresoc.v:199855.9-199855.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_cur_msr$next[63:0]$13914 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$13726 \dec2_cur_msr
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_msr$next[63:0]$13914 $2\dec2_cur_msr$next[63:0]$13915
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302"
+ assign $1\dec2_cur_msr$next[63:0]$13726 $2\dec2_cur_msr$next[63:0]$13727
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
switch \$90
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_msr$next[63:0]$13915 \core_msr__data_o
+ assign $2\dec2_cur_msr$next[63:0]$13727 \core_msr__data_o
case
- assign $2\dec2_cur_msr$next[63:0]$13915 \dec2_cur_msr
+ assign $2\dec2_cur_msr$next[63:0]$13727 \dec2_cur_msr
end
case
- assign $1\dec2_cur_msr$next[63:0]$13914 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$13726 \dec2_cur_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_msr$next[63:0]$13916 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_msr$next[63:0]$13728 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_msr$next[63:0]$13916 $1\dec2_cur_msr$next[63:0]$13914
+ assign $3\dec2_cur_msr$next[63:0]$13728 $1\dec2_cur_msr$next[63:0]$13726
end
sync always
- update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13913
+ update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13725
end
- attribute \src "libresoc.v:200935.3-200957.6"
- process $proc$libresoc.v:200935$13917
+ attribute \src "libresoc.v:199879.3-199901.6"
+ process $proc$libresoc.v:199879$13729
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$13918 $1\nia$next[63:0]$13919
- attribute \src "libresoc.v:200936.5-200936.29"
+ assign $0\nia$next[63:0]$13730 $1\nia$next[63:0]$13731
+ attribute \src "libresoc.v:199880.5-199880.29"
switch \initial
- attribute \src "libresoc.v:200936.9-200936.17"
+ attribute \src "libresoc.v:199880.9-199880.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\nia$next[63:0]$13919 \nia
+ assign $1\nia$next[63:0]$13731 \nia
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\nia$next[63:0]$13919 $2\nia$next[63:0]$13920
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ assign $1\nia$next[63:0]$13731 $2\nia$next[63:0]$13732
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\nia$next[63:0]$13920 \nia
+ assign $2\nia$next[63:0]$13732 \nia
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\nia$next[63:0]$13920 \$92 [63:0]
+ assign $2\nia$next[63:0]$13732 \$92 [63:0]
end
case
- assign $1\nia$next[63:0]$13919 \nia
+ assign $1\nia$next[63:0]$13731 \nia
end
sync always
- update \nia$next $0\nia$next[63:0]$13918
+ update \nia$next $0\nia$next[63:0]$13730
end
- attribute \src "libresoc.v:200958.3-200992.6"
- process $proc$libresoc.v:200958$13921
+ attribute \src "libresoc.v:199902.3-199936.6"
+ process $proc$libresoc.v:199902$13733
assign { } { }
assign { } { }
- assign $0\dec2_raw_opcode_in$next[31:0]$13922 $1\dec2_raw_opcode_in$next[31:0]$13923
- attribute \src "libresoc.v:200959.5-200959.29"
+ assign $0\dec2_raw_opcode_in$next[31:0]$13734 $1\dec2_raw_opcode_in$next[31:0]$13735
+ attribute \src "libresoc.v:199903.5-199903.29"
switch \initial
- attribute \src "libresoc.v:200959.9-200959.17"
+ attribute \src "libresoc.v:199903.9-199903.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_raw_opcode_in$next[31:0]$13923 \dec2_raw_opcode_in
+ assign $1\dec2_raw_opcode_in$next[31:0]$13735 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_raw_opcode_in$next[31:0]$13923 $2\dec2_raw_opcode_in$next[31:0]$13924
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ assign $1\dec2_raw_opcode_in$next[31:0]$13735 $2\dec2_raw_opcode_in$next[31:0]$13736
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\dec2_raw_opcode_in$next[31:0]$13924 \dec2_raw_opcode_in
+ assign $2\dec2_raw_opcode_in$next[31:0]$13736 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dec2_raw_opcode_in$next[31:0]$13924 \$95
+ assign $2\dec2_raw_opcode_in$next[31:0]$13736 \$95
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\dec2_raw_opcode_in$next[31:0]$13923 $3\dec2_raw_opcode_in$next[31:0]$13925
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
+ assign $1\dec2_raw_opcode_in$next[31:0]$13735 $3\dec2_raw_opcode_in$next[31:0]$13737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\dec2_raw_opcode_in$next[31:0]$13925 \dec2_raw_opcode_in
+ assign $3\dec2_raw_opcode_in$next[31:0]$13737 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\dec2_raw_opcode_in$next[31:0]$13925 \$99
+ assign $3\dec2_raw_opcode_in$next[31:0]$13737 \$99
end
case
- assign $1\dec2_raw_opcode_in$next[31:0]$13923 \dec2_raw_opcode_in
+ assign $1\dec2_raw_opcode_in$next[31:0]$13735 \dec2_raw_opcode_in
end
sync always
- update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13922
+ update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13734
end
- attribute \src "libresoc.v:200993.3-201015.6"
- process $proc$libresoc.v:200993$13926
+ attribute \src "libresoc.v:199937.3-199959.6"
+ process $proc$libresoc.v:199937$13738
assign { } { }
assign { } { }
assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:200994.5-200994.29"
+ attribute \src "libresoc.v:199938.5-199938.29"
switch \initial
- attribute \src "libresoc.v:200994.9-200994.17"
+ attribute \src "libresoc.v:199938.9-199938.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0]
end
- attribute \src "libresoc.v:201016.3-201091.6"
- process $proc$libresoc.v:201016$13927
+ attribute \src "libresoc.v:199960.3-200035.6"
+ process $proc$libresoc.v:199960$13739
assign { } { }
assign { } { }
assign { } { }
assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0]
assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0]
assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0]
- attribute \src "libresoc.v:201017.5-201017.29"
+ attribute \src "libresoc.v:199961.5-199961.29"
switch \initial
- attribute \src "libresoc.v:201017.9-201017.17"
+ attribute \src "libresoc.v:199961.9-199961.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0]
assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0]
assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$110
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0]
assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0]
assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0]
assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0]
assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$116
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $4\new_svstate_vl[6:0] \cur_cur_vl
assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0]
assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0]
assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
switch { \$122 \$118 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0]
assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0]
assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \new_svstate_svstep $0\new_svstate_svstep[1:0]
update \new_svstate_vl $0\new_svstate_vl[6:0]
end
- attribute \src "libresoc.v:201092.3-201107.6"
- process $proc$libresoc.v:201092$13928
+ attribute \src "libresoc.v:200036.3-200051.6"
+ process $proc$libresoc.v:200036$13740
assign { } { }
assign { } { }
assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:201093.5-201093.29"
+ attribute \src "libresoc.v:200037.5-200037.29"
switch \initial
- attribute \src "libresoc.v:201093.9-201093.17"
+ attribute \src "libresoc.v:200037.9-200037.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$134
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0]
end
- attribute \src "libresoc.v:201108.3-201206.6"
- process $proc$libresoc.v:201108$13929
+ attribute \src "libresoc.v:200052.3-200150.6"
+ process $proc$libresoc.v:200052$13741
assign { } { }
assign { } { }
assign { } { }
- assign $0\issue_fsm_state$next[2:0]$13930 $12\issue_fsm_state$next[2:0]$13942
- attribute \src "libresoc.v:201109.5-201109.29"
+ assign $0\issue_fsm_state$next[2:0]$13742 $12\issue_fsm_state$next[2:0]$13754
+ attribute \src "libresoc.v:200053.5-200053.29"
switch \initial
- attribute \src "libresoc.v:201109.9-201109.17"
+ attribute \src "libresoc.v:200053.9-200053.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $2\issue_fsm_state$next[2:0]$13932
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ assign $1\issue_fsm_state$next[2:0]$13743 $2\issue_fsm_state$next[2:0]$13744
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$140
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\issue_fsm_state$next[2:0]$13932 $3\issue_fsm_state$next[2:0]$13933
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520"
+ assign $2\issue_fsm_state$next[2:0]$13744 $3\issue_fsm_state$next[2:0]$13745
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523"
switch \fetch_pc_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\issue_fsm_state$next[2:0]$13933 3'001
+ assign $3\issue_fsm_state$next[2:0]$13745 3'001
case
- assign $3\issue_fsm_state$next[2:0]$13933 \issue_fsm_state
+ assign $3\issue_fsm_state$next[2:0]$13745 \issue_fsm_state
end
case
- assign $2\issue_fsm_state$next[2:0]$13932 \issue_fsm_state
+ assign $2\issue_fsm_state$next[2:0]$13744 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $4\issue_fsm_state$next[2:0]$13934
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\issue_fsm_state$next[2:0]$13743 $4\issue_fsm_state$next[2:0]$13746
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\issue_fsm_state$next[2:0]$13934 $5\issue_fsm_state$next[2:0]$13935
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ assign $4\issue_fsm_state$next[2:0]$13746 $5\issue_fsm_state$next[2:0]$13747
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
switch \$144
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\issue_fsm_state$next[2:0]$13935 3'000
+ assign $5\issue_fsm_state$next[2:0]$13747 3'000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $5\issue_fsm_state$next[2:0]$13935 3'010
+ assign $5\issue_fsm_state$next[2:0]$13747 3'010
end
case
- assign $4\issue_fsm_state$next[2:0]$13934 \issue_fsm_state
+ assign $4\issue_fsm_state$next[2:0]$13746 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $6\issue_fsm_state$next[2:0]$13936
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567"
+ assign $1\issue_fsm_state$next[2:0]$13743 $6\issue_fsm_state$next[2:0]$13748
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
switch \pred_insn_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\issue_fsm_state$next[2:0]$13936 3'100
+ assign $6\issue_fsm_state$next[2:0]$13748 3'100
case
- assign $6\issue_fsm_state$next[2:0]$13936 \issue_fsm_state
+ assign $6\issue_fsm_state$next[2:0]$13748 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $7\issue_fsm_state$next[2:0]$13937
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572"
+ assign $1\issue_fsm_state$next[2:0]$13743 $7\issue_fsm_state$next[2:0]$13749
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:575"
switch \pred_mask_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\issue_fsm_state$next[2:0]$13937 3'010
+ assign $7\issue_fsm_state$next[2:0]$13749 3'010
case
- assign $7\issue_fsm_state$next[2:0]$13937 \issue_fsm_state
+ assign $7\issue_fsm_state$next[2:0]$13749 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $8\issue_fsm_state$next[2:0]$13938
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613"
+ assign $1\issue_fsm_state$next[2:0]$13743 $8\issue_fsm_state$next[2:0]$13750
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616"
switch \exec_insn_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\issue_fsm_state$next[2:0]$13938 3'101
+ assign $8\issue_fsm_state$next[2:0]$13750 3'101
case
- assign $8\issue_fsm_state$next[2:0]$13938 \issue_fsm_state
+ assign $8\issue_fsm_state$next[2:0]$13750 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 $9\issue_fsm_state$next[2:0]$13939
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ assign $1\issue_fsm_state$next[2:0]$13743 $9\issue_fsm_state$next[2:0]$13751
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$150
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\issue_fsm_state$next[2:0]$13939 $10\issue_fsm_state$next[2:0]$13940
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ assign $9\issue_fsm_state$next[2:0]$13751 $10\issue_fsm_state$next[2:0]$13752
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $10\issue_fsm_state$next[2:0]$13940 $11\issue_fsm_state$next[2:0]$13941
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ assign $10\issue_fsm_state$next[2:0]$13752 $11\issue_fsm_state$next[2:0]$13753
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
switch { \$156 \$152 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13941 3'000
+ assign $11\issue_fsm_state$next[2:0]$13753 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13941 3'000
+ assign $11\issue_fsm_state$next[2:0]$13753 3'000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13941 3'110
+ assign $11\issue_fsm_state$next[2:0]$13753 3'110
end
case
- assign $10\issue_fsm_state$next[2:0]$13940 \issue_fsm_state
+ assign $10\issue_fsm_state$next[2:0]$13752 \issue_fsm_state
end
case
- assign $9\issue_fsm_state$next[2:0]$13939 \issue_fsm_state
+ assign $9\issue_fsm_state$next[2:0]$13751 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13931 3'010
+ assign $1\issue_fsm_state$next[2:0]$13743 3'010
case
- assign $1\issue_fsm_state$next[2:0]$13931 \issue_fsm_state
+ assign $1\issue_fsm_state$next[2:0]$13743 \issue_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $12\issue_fsm_state$next[2:0]$13942 3'000
+ assign $12\issue_fsm_state$next[2:0]$13754 3'000
case
- assign $12\issue_fsm_state$next[2:0]$13942 $1\issue_fsm_state$next[2:0]$13931
+ assign $12\issue_fsm_state$next[2:0]$13754 $1\issue_fsm_state$next[2:0]$13743
end
sync always
- update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13930
+ update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13742
end
- attribute \src "libresoc.v:201207.3-201253.6"
- process $proc$libresoc.v:201207$13943
+ attribute \src "libresoc.v:200151.3-200197.6"
+ process $proc$libresoc.v:200151$13755
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:201208.5-201208.29"
+ attribute \src "libresoc.v:200152.5-200152.29"
switch \initial
- attribute \src "libresoc.v:201208.9-201208.17"
+ attribute \src "libresoc.v:200152.9-200152.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$162
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$168
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:201254.3-201300.6"
- process $proc$libresoc.v:201254$13944
+ attribute \src "libresoc.v:200198.3-200244.6"
+ process $proc$libresoc.v:200198$13756
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:201255.5-201255.29"
+ attribute \src "libresoc.v:200199.5-200199.29"
switch \initial
- attribute \src "libresoc.v:201255.9-201255.17"
+ attribute \src "libresoc.v:200199.9-200199.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$174
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$180
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- attribute \src "libresoc.v:201301.3-201383.6"
- process $proc$libresoc.v:201301$13945
+ attribute \src "libresoc.v:200245.3-200327.6"
+ process $proc$libresoc.v:200245$13757
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\pc_changed$next[0:0]$13946 $9\pc_changed$next[0:0]$13955
- attribute \src "libresoc.v:201302.5-201302.29"
+ assign $0\pc_changed$next[0:0]$13758 $9\pc_changed$next[0:0]$13767
+ attribute \src "libresoc.v:200246.5-200246.29"
switch \initial
- attribute \src "libresoc.v:201302.9-201302.17"
+ attribute \src "libresoc.v:200246.9-200246.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\pc_changed$next[0:0]$13947 $2\pc_changed$next[0:0]$13948
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ assign $1\pc_changed$next[0:0]$13759 $2\pc_changed$next[0:0]$13760
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$186
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\pc_changed$next[0:0]$13948 \pc_changed
+ assign $2\pc_changed$next[0:0]$13760 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\pc_changed$next[0:0]$13948 $3\pc_changed$next[0:0]$13949
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527"
+ assign $2\pc_changed$next[0:0]$13760 $3\pc_changed$next[0:0]$13761
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\pc_changed$next[0:0]$13949 1'1
+ assign $3\pc_changed$next[0:0]$13761 1'1
case
- assign $3\pc_changed$next[0:0]$13949 \pc_changed
+ assign $3\pc_changed$next[0:0]$13761 \pc_changed
end
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\pc_changed$next[0:0]$13947 \pc_changed
+ assign $1\pc_changed$next[0:0]$13759 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\pc_changed$next[0:0]$13947 \pc_changed
+ assign $1\pc_changed$next[0:0]$13759 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\pc_changed$next[0:0]$13947 \pc_changed
+ assign $1\pc_changed$next[0:0]$13759 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\pc_changed$next[0:0]$13947 \pc_changed
+ assign $1\pc_changed$next[0:0]$13759 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\pc_changed$next[0:0]$13947 $4\pc_changed$next[0:0]$13950
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ assign $1\pc_changed$next[0:0]$13759 $4\pc_changed$next[0:0]$13762
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$192
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\pc_changed$next[0:0]$13950 \pc_changed
+ assign $4\pc_changed$next[0:0]$13762 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\pc_changed$next[0:0]$13950 $5\pc_changed$next[0:0]$13951
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663"
+ assign $4\pc_changed$next[0:0]$13762 $5\pc_changed$next[0:0]$13763
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\pc_changed$next[0:0]$13951 1'1
+ assign $5\pc_changed$next[0:0]$13763 1'1
case
- assign $5\pc_changed$next[0:0]$13951 \pc_changed
+ assign $5\pc_changed$next[0:0]$13763 \pc_changed
end
end
case
- assign $1\pc_changed$next[0:0]$13947 \pc_changed
+ assign $1\pc_changed$next[0:0]$13759 \pc_changed
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $6\pc_changed$next[0:0]$13952 $7\pc_changed$next[0:0]$13953
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715"
+ assign $6\pc_changed$next[0:0]$13764 $7\pc_changed$next[0:0]$13765
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\pc_changed$next[0:0]$13953 1'0
+ assign $7\pc_changed$next[0:0]$13765 1'0
case
- assign $7\pc_changed$next[0:0]$13953 $1\pc_changed$next[0:0]$13947
+ assign $7\pc_changed$next[0:0]$13765 $1\pc_changed$next[0:0]$13759
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\pc_changed$next[0:0]$13952 $8\pc_changed$next[0:0]$13954
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729"
+ assign $6\pc_changed$next[0:0]$13764 $8\pc_changed$next[0:0]$13766
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
switch \$194
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\pc_changed$next[0:0]$13954 1'1
+ assign $8\pc_changed$next[0:0]$13766 1'1
case
- assign $8\pc_changed$next[0:0]$13954 $1\pc_changed$next[0:0]$13947
+ assign $8\pc_changed$next[0:0]$13766 $1\pc_changed$next[0:0]$13759
end
case
- assign $6\pc_changed$next[0:0]$13952 $1\pc_changed$next[0:0]$13947
+ assign $6\pc_changed$next[0:0]$13764 $1\pc_changed$next[0:0]$13759
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\pc_changed$next[0:0]$13955 1'0
+ assign $9\pc_changed$next[0:0]$13767 1'0
case
- assign $9\pc_changed$next[0:0]$13955 $6\pc_changed$next[0:0]$13952
+ assign $9\pc_changed$next[0:0]$13767 $6\pc_changed$next[0:0]$13764
end
sync always
- update \pc_changed$next $0\pc_changed$next[0:0]$13946
+ update \pc_changed$next $0\pc_changed$next[0:0]$13758
end
- attribute \src "libresoc.v:201384.3-201456.6"
- process $proc$libresoc.v:201384$13956
+ attribute \src "libresoc.v:200328.3-200400.6"
+ process $proc$libresoc.v:200328$13768
assign { } { }
assign { } { }
assign $0\update_svstate[0:0] $1\update_svstate[0:0]
- attribute \src "libresoc.v:201385.5-201385.29"
+ attribute \src "libresoc.v:200329.5-200329.29"
switch \initial
- attribute \src "libresoc.v:201385.9-201385.17"
+ attribute \src "libresoc.v:200329.9-200329.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\update_svstate[0:0] $2\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$202
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\update_svstate[0:0] $3\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\update_svstate[0:0] $4\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$208
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\update_svstate[0:0] $5\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\update_svstate[0:0] $6\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
switch { \$214 \$210 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $4\update_svstate[0:0] $7\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \update_svstate $0\update_svstate[0:0]
end
- attribute \src "libresoc.v:201457.3-201539.6"
- process $proc$libresoc.v:201457$13957
+ attribute \src "libresoc.v:200401.3-200483.6"
+ process $proc$libresoc.v:200401$13769
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv_changed$next[0:0]$13958 $9\sv_changed$next[0:0]$13967
- attribute \src "libresoc.v:201458.5-201458.29"
+ assign $0\sv_changed$next[0:0]$13770 $9\sv_changed$next[0:0]$13779
+ attribute \src "libresoc.v:200402.5-200402.29"
switch \initial
- attribute \src "libresoc.v:201458.9-201458.17"
+ attribute \src "libresoc.v:200402.9-200402.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\sv_changed$next[0:0]$13959 $2\sv_changed$next[0:0]$13960
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
+ assign $1\sv_changed$next[0:0]$13771 $2\sv_changed$next[0:0]$13772
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
switch \$220
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\sv_changed$next[0:0]$13960 \sv_changed
+ assign $2\sv_changed$next[0:0]$13772 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\sv_changed$next[0:0]$13960 $3\sv_changed$next[0:0]$13961
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531"
+ assign $2\sv_changed$next[0:0]$13772 $3\sv_changed$next[0:0]$13773
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv_changed$next[0:0]$13961 1'1
+ assign $3\sv_changed$next[0:0]$13773 1'1
case
- assign $3\sv_changed$next[0:0]$13961 \sv_changed
+ assign $3\sv_changed$next[0:0]$13773 \sv_changed
end
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\sv_changed$next[0:0]$13959 \sv_changed
+ assign $1\sv_changed$next[0:0]$13771 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\sv_changed$next[0:0]$13959 \sv_changed
+ assign $1\sv_changed$next[0:0]$13771 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\sv_changed$next[0:0]$13959 \sv_changed
+ assign $1\sv_changed$next[0:0]$13771 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\sv_changed$next[0:0]$13959 \sv_changed
+ assign $1\sv_changed$next[0:0]$13771 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\sv_changed$next[0:0]$13959 $4\sv_changed$next[0:0]$13962
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619"
+ assign $1\sv_changed$next[0:0]$13771 $4\sv_changed$next[0:0]$13774
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
switch \$226
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\sv_changed$next[0:0]$13962 \sv_changed
+ assign $4\sv_changed$next[0:0]$13774 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\sv_changed$next[0:0]$13962 $5\sv_changed$next[0:0]$13963
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667"
+ assign $4\sv_changed$next[0:0]$13774 $5\sv_changed$next[0:0]$13775
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv_changed$next[0:0]$13963 1'1
+ assign $5\sv_changed$next[0:0]$13775 1'1
case
- assign $5\sv_changed$next[0:0]$13963 \sv_changed
+ assign $5\sv_changed$next[0:0]$13775 \sv_changed
end
end
case
- assign $1\sv_changed$next[0:0]$13959 \sv_changed
+ assign $1\sv_changed$next[0:0]$13771 \sv_changed
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $6\sv_changed$next[0:0]$13964 $7\sv_changed$next[0:0]$13965
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715"
+ assign $6\sv_changed$next[0:0]$13776 $7\sv_changed$next[0:0]$13777
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv_changed$next[0:0]$13965 1'0
+ assign $7\sv_changed$next[0:0]$13777 1'0
case
- assign $7\sv_changed$next[0:0]$13965 $1\sv_changed$next[0:0]$13959
+ assign $7\sv_changed$next[0:0]$13777 $1\sv_changed$next[0:0]$13771
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv_changed$next[0:0]$13964 $8\sv_changed$next[0:0]$13966
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
+ assign $6\sv_changed$next[0:0]$13776 $8\sv_changed$next[0:0]$13778
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
switch \$228
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\sv_changed$next[0:0]$13966 1'1
+ assign $8\sv_changed$next[0:0]$13778 1'1
case
- assign $8\sv_changed$next[0:0]$13966 $1\sv_changed$next[0:0]$13959
+ assign $8\sv_changed$next[0:0]$13778 $1\sv_changed$next[0:0]$13771
end
case
- assign $6\sv_changed$next[0:0]$13964 $1\sv_changed$next[0:0]$13959
+ assign $6\sv_changed$next[0:0]$13776 $1\sv_changed$next[0:0]$13771
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\sv_changed$next[0:0]$13967 1'0
+ assign $9\sv_changed$next[0:0]$13779 1'0
case
- assign $9\sv_changed$next[0:0]$13967 $6\sv_changed$next[0:0]$13964
+ assign $9\sv_changed$next[0:0]$13779 $6\sv_changed$next[0:0]$13776
end
sync always
- update \sv_changed$next $0\sv_changed$next[0:0]$13958
+ update \sv_changed$next $0\sv_changed$next[0:0]$13770
end
- attribute \src "libresoc.v:201540.3-201554.6"
- process $proc$libresoc.v:201540$13968
+ attribute \src "libresoc.v:200484.3-200498.6"
+ process $proc$libresoc.v:200484$13780
assign { } { }
assign { } { }
assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:201541.5-201541.29"
+ attribute \src "libresoc.v:200485.5-200485.29"
switch \initial
- attribute \src "libresoc.v:201541.9-201541.17"
+ attribute \src "libresoc.v:200485.9-200485.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0]
end
- attribute \src "libresoc.v:201555.3-201685.6"
- process $proc$libresoc.v:201555$13969
+ attribute \src "libresoc.v:200499.3-200629.6"
+ process $proc$libresoc.v:200499$13781
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_asmcode$next[7:0]$13970 $1\core_asmcode$next[7:0]$14029
- assign $0\core_core_core_cia$next[63:0]$13971 $1\core_core_core_cia$next[63:0]$14030
- assign $0\core_core_core_cr_rd$next[7:0]$13972 $1\core_core_core_cr_rd$next[7:0]$14031
+ assign $0\core_asmcode$next[7:0]$13782 $1\core_asmcode$next[7:0]$13841
+ assign $0\core_core_core_cia$next[63:0]$13783 $1\core_core_core_cia$next[63:0]$13842
+ assign $0\core_core_core_cr_rd$next[7:0]$13784 $1\core_core_core_cr_rd$next[7:0]$13843
assign { } { }
- assign $0\core_core_core_cr_wr$next[7:0]$13974 $1\core_core_core_cr_wr$next[7:0]$14033
+ assign $0\core_core_core_cr_wr$next[7:0]$13786 $1\core_core_core_cr_wr$next[7:0]$13845
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_core_fn_unit$next[13:0]$13983 $1\core_core_core_fn_unit$next[13:0]$14042
- assign $0\core_core_core_input_carry$next[1:0]$13984 $1\core_core_core_input_carry$next[1:0]$14043
- assign $0\core_core_core_insn$next[31:0]$13985 $1\core_core_core_insn$next[31:0]$14044
- assign $0\core_core_core_insn_type$next[6:0]$13986 $1\core_core_core_insn_type$next[6:0]$14045
- assign $0\core_core_core_is_32bit$next[0:0]$13987 $1\core_core_core_is_32bit$next[0:0]$14046
- assign $0\core_core_core_msr$next[63:0]$13988 $1\core_core_core_msr$next[63:0]$14047
- assign $0\core_core_core_oe$next[0:0]$13989 $1\core_core_core_oe$next[0:0]$14048
+ assign $0\core_core_core_fn_unit$next[13:0]$13795 $1\core_core_core_fn_unit$next[13:0]$13854
+ assign $0\core_core_core_input_carry$next[1:0]$13796 $1\core_core_core_input_carry$next[1:0]$13855
+ assign $0\core_core_core_insn$next[31:0]$13797 $1\core_core_core_insn$next[31:0]$13856
+ assign $0\core_core_core_insn_type$next[6:0]$13798 $1\core_core_core_insn_type$next[6:0]$13857
+ assign $0\core_core_core_is_32bit$next[0:0]$13799 $1\core_core_core_is_32bit$next[0:0]$13858
+ assign $0\core_core_core_msr$next[63:0]$13800 $1\core_core_core_msr$next[63:0]$13859
+ assign $0\core_core_core_oe$next[0:0]$13801 $1\core_core_core_oe$next[0:0]$13860
assign { } { }
- assign $0\core_core_core_rc$next[0:0]$13991 $1\core_core_core_rc$next[0:0]$14050
+ assign $0\core_core_core_rc$next[0:0]$13803 $1\core_core_core_rc$next[0:0]$13862
assign { } { }
- assign $0\core_core_core_trapaddr$next[12:0]$13993 $1\core_core_core_trapaddr$next[12:0]$14052
- assign $0\core_core_core_traptype$next[7:0]$13994 $1\core_core_core_traptype$next[7:0]$14053
- assign $0\core_core_cr_in1$next[6:0]$13995 $1\core_core_cr_in1$next[6:0]$14054
+ assign $0\core_core_core_trapaddr$next[12:0]$13805 $1\core_core_core_trapaddr$next[12:0]$13864
+ assign $0\core_core_core_traptype$next[7:0]$13806 $1\core_core_core_traptype$next[7:0]$13865
+ assign $0\core_core_cr_in1$next[6:0]$13807 $1\core_core_cr_in1$next[6:0]$13866
assign { } { }
- assign $0\core_core_cr_in2$1$next[6:0]$13997 $1\core_core_cr_in2$1$next[6:0]$14056
- assign $0\core_core_cr_in2$next[6:0]$13998 $1\core_core_cr_in2$next[6:0]$14057
+ assign $0\core_core_cr_in2$1$next[6:0]$13809 $1\core_core_cr_in2$1$next[6:0]$13868
+ assign $0\core_core_cr_in2$next[6:0]$13810 $1\core_core_cr_in2$next[6:0]$13869
assign { } { }
assign { } { }
- assign $0\core_core_cr_out$next[6:0]$14001 $1\core_core_cr_out$next[6:0]$14060
+ assign $0\core_core_cr_out$next[6:0]$13813 $1\core_core_cr_out$next[6:0]$13872
assign { } { }
- assign $0\core_core_ea$next[6:0]$14003 $1\core_core_ea$next[6:0]$14062
- assign $0\core_core_fast1$next[2:0]$14004 $1\core_core_fast1$next[2:0]$14063
+ assign $0\core_core_ea$next[6:0]$13815 $1\core_core_ea$next[6:0]$13874
+ assign $0\core_core_fast1$next[2:0]$13816 $1\core_core_fast1$next[2:0]$13875
assign { } { }
- assign $0\core_core_fast2$next[2:0]$14006 $1\core_core_fast2$next[2:0]$14065
+ assign $0\core_core_fast2$next[2:0]$13818 $1\core_core_fast2$next[2:0]$13877
assign { } { }
- assign $0\core_core_fasto1$next[2:0]$14008 $1\core_core_fasto1$next[2:0]$14067
- assign $0\core_core_fasto2$next[2:0]$14009 $1\core_core_fasto2$next[2:0]$14068
- assign $0\core_core_lk$next[0:0]$14010 $1\core_core_lk$next[0:0]$14069
- assign $0\core_core_reg1$next[6:0]$14011 $1\core_core_reg1$next[6:0]$14070
+ assign $0\core_core_fasto1$next[2:0]$13820 $1\core_core_fasto1$next[2:0]$13879
+ assign $0\core_core_fasto2$next[2:0]$13821 $1\core_core_fasto2$next[2:0]$13880
+ assign $0\core_core_lk$next[0:0]$13822 $1\core_core_lk$next[0:0]$13881
+ assign $0\core_core_reg1$next[6:0]$13823 $1\core_core_reg1$next[6:0]$13882
assign { } { }
- assign $0\core_core_reg2$next[6:0]$14013 $1\core_core_reg2$next[6:0]$14072
+ assign $0\core_core_reg2$next[6:0]$13825 $1\core_core_reg2$next[6:0]$13884
assign { } { }
- assign $0\core_core_reg3$next[6:0]$14015 $1\core_core_reg3$next[6:0]$14074
+ assign $0\core_core_reg3$next[6:0]$13827 $1\core_core_reg3$next[6:0]$13886
assign { } { }
- assign $0\core_core_rego$next[6:0]$14017 $1\core_core_rego$next[6:0]$14076
- assign $0\core_core_spr1$next[9:0]$14018 $1\core_core_spr1$next[9:0]$14077
+ assign $0\core_core_rego$next[6:0]$13829 $1\core_core_rego$next[6:0]$13888
+ assign $0\core_core_spr1$next[9:0]$13830 $1\core_core_spr1$next[9:0]$13889
assign { } { }
- assign $0\core_core_spro$next[9:0]$14020 $1\core_core_spro$next[9:0]$14079
- assign $0\core_core_xer_in$next[2:0]$14021 $1\core_core_xer_in$next[2:0]$14080
+ assign $0\core_core_spro$next[9:0]$13832 $1\core_core_spro$next[9:0]$13891
+ assign $0\core_core_xer_in$next[2:0]$13833 $1\core_core_xer_in$next[2:0]$13892
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_xer_out$next[0:0]$14028 $1\core_xer_out$next[0:0]$14087
- assign $0\core_core_core_cr_rd_ok$next[0:0]$13973 $3\core_core_core_cr_rd_ok$next[0:0]$14147
- assign $0\core_core_core_exc_$signal$3$next[0:0]$13975 $3\core_core_core_exc_$signal$3$next[0:0]$14148
- assign $0\core_core_core_exc_$signal$4$next[0:0]$13976 $3\core_core_core_exc_$signal$4$next[0:0]$14149
- assign $0\core_core_core_exc_$signal$5$next[0:0]$13977 $3\core_core_core_exc_$signal$5$next[0:0]$14150
- assign $0\core_core_core_exc_$signal$6$next[0:0]$13978 $3\core_core_core_exc_$signal$6$next[0:0]$14151
- assign $0\core_core_core_exc_$signal$7$next[0:0]$13979 $3\core_core_core_exc_$signal$7$next[0:0]$14152
- assign $0\core_core_core_exc_$signal$8$next[0:0]$13980 $3\core_core_core_exc_$signal$8$next[0:0]$14153
- assign $0\core_core_core_exc_$signal$9$next[0:0]$13981 $3\core_core_core_exc_$signal$9$next[0:0]$14154
- assign $0\core_core_core_exc_$signal$next[0:0]$13982 $3\core_core_core_exc_$signal$next[0:0]$14155
- assign $0\core_core_core_oe_ok$next[0:0]$13990 $3\core_core_core_oe_ok$next[0:0]$14156
- assign $0\core_core_core_rc_ok$next[0:0]$13992 $3\core_core_core_rc_ok$next[0:0]$14157
- assign $0\core_core_cr_in1_ok$next[0:0]$13996 $3\core_core_cr_in1_ok$next[0:0]$14158
- assign $0\core_core_cr_in2_ok$2$next[0:0]$13999 $3\core_core_cr_in2_ok$2$next[0:0]$14159
- assign $0\core_core_cr_in2_ok$next[0:0]$14000 $3\core_core_cr_in2_ok$next[0:0]$14160
- assign $0\core_core_cr_wr_ok$next[0:0]$14002 $3\core_core_cr_wr_ok$next[0:0]$14161
- assign $0\core_core_fast1_ok$next[0:0]$14005 $3\core_core_fast1_ok$next[0:0]$14162
- assign $0\core_core_fast2_ok$next[0:0]$14007 $3\core_core_fast2_ok$next[0:0]$14163
- assign $0\core_core_reg1_ok$next[0:0]$14012 $3\core_core_reg1_ok$next[0:0]$14164
- assign $0\core_core_reg2_ok$next[0:0]$14014 $3\core_core_reg2_ok$next[0:0]$14165
- assign $0\core_core_reg3_ok$next[0:0]$14016 $3\core_core_reg3_ok$next[0:0]$14166
- assign $0\core_core_spr1_ok$next[0:0]$14019 $3\core_core_spr1_ok$next[0:0]$14167
- assign $0\core_cr_out_ok$next[0:0]$14022 $3\core_cr_out_ok$next[0:0]$14168
- assign $0\core_ea_ok$next[0:0]$14023 $3\core_ea_ok$next[0:0]$14169
- assign $0\core_fasto1_ok$next[0:0]$14024 $3\core_fasto1_ok$next[0:0]$14170
- assign $0\core_fasto2_ok$next[0:0]$14025 $3\core_fasto2_ok$next[0:0]$14171
- assign $0\core_rego_ok$next[0:0]$14026 $3\core_rego_ok$next[0:0]$14172
- assign $0\core_spro_ok$next[0:0]$14027 $3\core_spro_ok$next[0:0]$14173
- attribute \src "libresoc.v:201556.5-201556.29"
+ assign $0\core_xer_out$next[0:0]$13840 $1\core_xer_out$next[0:0]$13899
+ assign $0\core_core_core_cr_rd_ok$next[0:0]$13785 $3\core_core_core_cr_rd_ok$next[0:0]$13959
+ assign $0\core_core_core_exc_$signal$3$next[0:0]$13787 $3\core_core_core_exc_$signal$3$next[0:0]$13960
+ assign $0\core_core_core_exc_$signal$4$next[0:0]$13788 $3\core_core_core_exc_$signal$4$next[0:0]$13961
+ assign $0\core_core_core_exc_$signal$5$next[0:0]$13789 $3\core_core_core_exc_$signal$5$next[0:0]$13962
+ assign $0\core_core_core_exc_$signal$6$next[0:0]$13790 $3\core_core_core_exc_$signal$6$next[0:0]$13963
+ assign $0\core_core_core_exc_$signal$7$next[0:0]$13791 $3\core_core_core_exc_$signal$7$next[0:0]$13964
+ assign $0\core_core_core_exc_$signal$8$next[0:0]$13792 $3\core_core_core_exc_$signal$8$next[0:0]$13965
+ assign $0\core_core_core_exc_$signal$9$next[0:0]$13793 $3\core_core_core_exc_$signal$9$next[0:0]$13966
+ assign $0\core_core_core_exc_$signal$next[0:0]$13794 $3\core_core_core_exc_$signal$next[0:0]$13967
+ assign $0\core_core_core_oe_ok$next[0:0]$13802 $3\core_core_core_oe_ok$next[0:0]$13968
+ assign $0\core_core_core_rc_ok$next[0:0]$13804 $3\core_core_core_rc_ok$next[0:0]$13969
+ assign $0\core_core_cr_in1_ok$next[0:0]$13808 $3\core_core_cr_in1_ok$next[0:0]$13970
+ assign $0\core_core_cr_in2_ok$2$next[0:0]$13811 $3\core_core_cr_in2_ok$2$next[0:0]$13971
+ assign $0\core_core_cr_in2_ok$next[0:0]$13812 $3\core_core_cr_in2_ok$next[0:0]$13972
+ assign $0\core_core_cr_wr_ok$next[0:0]$13814 $3\core_core_cr_wr_ok$next[0:0]$13973
+ assign $0\core_core_fast1_ok$next[0:0]$13817 $3\core_core_fast1_ok$next[0:0]$13974
+ assign $0\core_core_fast2_ok$next[0:0]$13819 $3\core_core_fast2_ok$next[0:0]$13975
+ assign $0\core_core_reg1_ok$next[0:0]$13824 $3\core_core_reg1_ok$next[0:0]$13976
+ assign $0\core_core_reg2_ok$next[0:0]$13826 $3\core_core_reg2_ok$next[0:0]$13977
+ assign $0\core_core_reg3_ok$next[0:0]$13828 $3\core_core_reg3_ok$next[0:0]$13978
+ assign $0\core_core_spr1_ok$next[0:0]$13831 $3\core_core_spr1_ok$next[0:0]$13979
+ assign $0\core_cr_out_ok$next[0:0]$13834 $3\core_cr_out_ok$next[0:0]$13980
+ assign $0\core_ea_ok$next[0:0]$13835 $3\core_ea_ok$next[0:0]$13981
+ assign $0\core_fasto1_ok$next[0:0]$13836 $3\core_fasto1_ok$next[0:0]$13982
+ assign $0\core_fasto2_ok$next[0:0]$13837 $3\core_fasto2_ok$next[0:0]$13983
+ assign $0\core_rego_ok$next[0:0]$13838 $3\core_rego_ok$next[0:0]$13984
+ assign $0\core_spro_ok$next[0:0]$13839 $3\core_spro_ok$next[0:0]$13985
+ attribute \src "libresoc.v:200500.5-200500.29"
switch \initial
- attribute \src "libresoc.v:201556.9-201556.17"
+ attribute \src "libresoc.v:200500.9-200500.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$14029 $2\core_asmcode$next[7:0]$14088
- assign $1\core_core_core_cia$next[63:0]$14030 $2\core_core_core_cia$next[63:0]$14089
- assign $1\core_core_core_cr_rd$next[7:0]$14031 $2\core_core_core_cr_rd$next[7:0]$14090
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 $2\core_core_core_cr_rd_ok$next[0:0]$14091
- assign $1\core_core_core_cr_wr$next[7:0]$14033 $2\core_core_core_cr_wr$next[7:0]$14092
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 $2\core_core_core_exc_$signal$3$next[0:0]$14093
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 $2\core_core_core_exc_$signal$4$next[0:0]$14094
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 $2\core_core_core_exc_$signal$5$next[0:0]$14095
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 $2\core_core_core_exc_$signal$6$next[0:0]$14096
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 $2\core_core_core_exc_$signal$7$next[0:0]$14097
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 $2\core_core_core_exc_$signal$8$next[0:0]$14098
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 $2\core_core_core_exc_$signal$9$next[0:0]$14099
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 $2\core_core_core_exc_$signal$next[0:0]$14100
- assign $1\core_core_core_fn_unit$next[13:0]$14042 $2\core_core_core_fn_unit$next[13:0]$14101
- assign $1\core_core_core_input_carry$next[1:0]$14043 $2\core_core_core_input_carry$next[1:0]$14102
- assign $1\core_core_core_insn$next[31:0]$14044 $2\core_core_core_insn$next[31:0]$14103
- assign $1\core_core_core_insn_type$next[6:0]$14045 $2\core_core_core_insn_type$next[6:0]$14104
- assign $1\core_core_core_is_32bit$next[0:0]$14046 $2\core_core_core_is_32bit$next[0:0]$14105
- assign $1\core_core_core_msr$next[63:0]$14047 $2\core_core_core_msr$next[63:0]$14106
- assign $1\core_core_core_oe$next[0:0]$14048 $2\core_core_core_oe$next[0:0]$14107
- assign $1\core_core_core_oe_ok$next[0:0]$14049 $2\core_core_core_oe_ok$next[0:0]$14108
- assign $1\core_core_core_rc$next[0:0]$14050 $2\core_core_core_rc$next[0:0]$14109
- assign $1\core_core_core_rc_ok$next[0:0]$14051 $2\core_core_core_rc_ok$next[0:0]$14110
- assign $1\core_core_core_trapaddr$next[12:0]$14052 $2\core_core_core_trapaddr$next[12:0]$14111
- assign $1\core_core_core_traptype$next[7:0]$14053 $2\core_core_core_traptype$next[7:0]$14112
- assign $1\core_core_cr_in1$next[6:0]$14054 $2\core_core_cr_in1$next[6:0]$14113
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 $2\core_core_cr_in1_ok$next[0:0]$14114
- assign $1\core_core_cr_in2$1$next[6:0]$14056 $2\core_core_cr_in2$1$next[6:0]$14115
- assign $1\core_core_cr_in2$next[6:0]$14057 $2\core_core_cr_in2$next[6:0]$14116
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 $2\core_core_cr_in2_ok$2$next[0:0]$14117
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 $2\core_core_cr_in2_ok$next[0:0]$14118
- assign $1\core_core_cr_out$next[6:0]$14060 $2\core_core_cr_out$next[6:0]$14119
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 $2\core_core_cr_wr_ok$next[0:0]$14120
- assign $1\core_core_ea$next[6:0]$14062 $2\core_core_ea$next[6:0]$14121
- assign $1\core_core_fast1$next[2:0]$14063 $2\core_core_fast1$next[2:0]$14122
- assign $1\core_core_fast1_ok$next[0:0]$14064 $2\core_core_fast1_ok$next[0:0]$14123
- assign $1\core_core_fast2$next[2:0]$14065 $2\core_core_fast2$next[2:0]$14124
- assign $1\core_core_fast2_ok$next[0:0]$14066 $2\core_core_fast2_ok$next[0:0]$14125
- assign $1\core_core_fasto1$next[2:0]$14067 $2\core_core_fasto1$next[2:0]$14126
- assign $1\core_core_fasto2$next[2:0]$14068 $2\core_core_fasto2$next[2:0]$14127
- assign $1\core_core_lk$next[0:0]$14069 $2\core_core_lk$next[0:0]$14128
- assign $1\core_core_reg1$next[6:0]$14070 $2\core_core_reg1$next[6:0]$14129
- assign $1\core_core_reg1_ok$next[0:0]$14071 $2\core_core_reg1_ok$next[0:0]$14130
- assign $1\core_core_reg2$next[6:0]$14072 $2\core_core_reg2$next[6:0]$14131
- assign $1\core_core_reg2_ok$next[0:0]$14073 $2\core_core_reg2_ok$next[0:0]$14132
- assign $1\core_core_reg3$next[6:0]$14074 $2\core_core_reg3$next[6:0]$14133
- assign $1\core_core_reg3_ok$next[0:0]$14075 $2\core_core_reg3_ok$next[0:0]$14134
- assign $1\core_core_rego$next[6:0]$14076 $2\core_core_rego$next[6:0]$14135
- assign $1\core_core_spr1$next[9:0]$14077 $2\core_core_spr1$next[9:0]$14136
- assign $1\core_core_spr1_ok$next[0:0]$14078 $2\core_core_spr1_ok$next[0:0]$14137
- assign $1\core_core_spro$next[9:0]$14079 $2\core_core_spro$next[9:0]$14138
- assign $1\core_core_xer_in$next[2:0]$14080 $2\core_core_xer_in$next[2:0]$14139
- assign $1\core_cr_out_ok$next[0:0]$14081 $2\core_cr_out_ok$next[0:0]$14140
- assign $1\core_ea_ok$next[0:0]$14082 $2\core_ea_ok$next[0:0]$14141
- assign $1\core_fasto1_ok$next[0:0]$14083 $2\core_fasto1_ok$next[0:0]$14142
- assign $1\core_fasto2_ok$next[0:0]$14084 $2\core_fasto2_ok$next[0:0]$14143
- assign $1\core_rego_ok$next[0:0]$14085 $2\core_rego_ok$next[0:0]$14144
- assign $1\core_spro_ok$next[0:0]$14086 $2\core_spro_ok$next[0:0]$14145
- assign $1\core_xer_out$next[0:0]$14087 $2\core_xer_out$next[0:0]$14146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
+ assign $1\core_asmcode$next[7:0]$13841 $2\core_asmcode$next[7:0]$13900
+ assign $1\core_core_core_cia$next[63:0]$13842 $2\core_core_core_cia$next[63:0]$13901
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 $2\core_core_core_cr_rd$next[7:0]$13902
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 $2\core_core_core_cr_rd_ok$next[0:0]$13903
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 $2\core_core_core_cr_wr$next[7:0]$13904
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 $2\core_core_core_exc_$signal$3$next[0:0]$13905
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 $2\core_core_core_exc_$signal$4$next[0:0]$13906
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 $2\core_core_core_exc_$signal$5$next[0:0]$13907
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 $2\core_core_core_exc_$signal$6$next[0:0]$13908
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 $2\core_core_core_exc_$signal$7$next[0:0]$13909
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 $2\core_core_core_exc_$signal$8$next[0:0]$13910
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 $2\core_core_core_exc_$signal$9$next[0:0]$13911
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 $2\core_core_core_exc_$signal$next[0:0]$13912
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 $2\core_core_core_fn_unit$next[13:0]$13913
+ assign $1\core_core_core_input_carry$next[1:0]$13855 $2\core_core_core_input_carry$next[1:0]$13914
+ assign $1\core_core_core_insn$next[31:0]$13856 $2\core_core_core_insn$next[31:0]$13915
+ assign $1\core_core_core_insn_type$next[6:0]$13857 $2\core_core_core_insn_type$next[6:0]$13916
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 $2\core_core_core_is_32bit$next[0:0]$13917
+ assign $1\core_core_core_msr$next[63:0]$13859 $2\core_core_core_msr$next[63:0]$13918
+ assign $1\core_core_core_oe$next[0:0]$13860 $2\core_core_core_oe$next[0:0]$13919
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 $2\core_core_core_oe_ok$next[0:0]$13920
+ assign $1\core_core_core_rc$next[0:0]$13862 $2\core_core_core_rc$next[0:0]$13921
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 $2\core_core_core_rc_ok$next[0:0]$13922
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 $2\core_core_core_trapaddr$next[12:0]$13923
+ assign $1\core_core_core_traptype$next[7:0]$13865 $2\core_core_core_traptype$next[7:0]$13924
+ assign $1\core_core_cr_in1$next[6:0]$13866 $2\core_core_cr_in1$next[6:0]$13925
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 $2\core_core_cr_in1_ok$next[0:0]$13926
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 $2\core_core_cr_in2$1$next[6:0]$13927
+ assign $1\core_core_cr_in2$next[6:0]$13869 $2\core_core_cr_in2$next[6:0]$13928
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 $2\core_core_cr_in2_ok$2$next[0:0]$13929
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 $2\core_core_cr_in2_ok$next[0:0]$13930
+ assign $1\core_core_cr_out$next[6:0]$13872 $2\core_core_cr_out$next[6:0]$13931
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 $2\core_core_cr_wr_ok$next[0:0]$13932
+ assign $1\core_core_ea$next[6:0]$13874 $2\core_core_ea$next[6:0]$13933
+ assign $1\core_core_fast1$next[2:0]$13875 $2\core_core_fast1$next[2:0]$13934
+ assign $1\core_core_fast1_ok$next[0:0]$13876 $2\core_core_fast1_ok$next[0:0]$13935
+ assign $1\core_core_fast2$next[2:0]$13877 $2\core_core_fast2$next[2:0]$13936
+ assign $1\core_core_fast2_ok$next[0:0]$13878 $2\core_core_fast2_ok$next[0:0]$13937
+ assign $1\core_core_fasto1$next[2:0]$13879 $2\core_core_fasto1$next[2:0]$13938
+ assign $1\core_core_fasto2$next[2:0]$13880 $2\core_core_fasto2$next[2:0]$13939
+ assign $1\core_core_lk$next[0:0]$13881 $2\core_core_lk$next[0:0]$13940
+ assign $1\core_core_reg1$next[6:0]$13882 $2\core_core_reg1$next[6:0]$13941
+ assign $1\core_core_reg1_ok$next[0:0]$13883 $2\core_core_reg1_ok$next[0:0]$13942
+ assign $1\core_core_reg2$next[6:0]$13884 $2\core_core_reg2$next[6:0]$13943
+ assign $1\core_core_reg2_ok$next[0:0]$13885 $2\core_core_reg2_ok$next[0:0]$13944
+ assign $1\core_core_reg3$next[6:0]$13886 $2\core_core_reg3$next[6:0]$13945
+ assign $1\core_core_reg3_ok$next[0:0]$13887 $2\core_core_reg3_ok$next[0:0]$13946
+ assign $1\core_core_rego$next[6:0]$13888 $2\core_core_rego$next[6:0]$13947
+ assign $1\core_core_spr1$next[9:0]$13889 $2\core_core_spr1$next[9:0]$13948
+ assign $1\core_core_spr1_ok$next[0:0]$13890 $2\core_core_spr1_ok$next[0:0]$13949
+ assign $1\core_core_spro$next[9:0]$13891 $2\core_core_spro$next[9:0]$13950
+ assign $1\core_core_xer_in$next[2:0]$13892 $2\core_core_xer_in$next[2:0]$13951
+ assign $1\core_cr_out_ok$next[0:0]$13893 $2\core_cr_out_ok$next[0:0]$13952
+ assign $1\core_ea_ok$next[0:0]$13894 $2\core_ea_ok$next[0:0]$13953
+ assign $1\core_fasto1_ok$next[0:0]$13895 $2\core_fasto1_ok$next[0:0]$13954
+ assign $1\core_fasto2_ok$next[0:0]$13896 $2\core_fasto2_ok$next[0:0]$13955
+ assign $1\core_rego_ok$next[0:0]$13897 $2\core_rego_ok$next[0:0]$13956
+ assign $1\core_spro_ok$next[0:0]$13898 $2\core_spro_ok$next[0:0]$13957
+ assign $1\core_xer_out$next[0:0]$13899 $2\core_xer_out$next[0:0]$13958
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_core_is_32bit$next[0:0]$14105 $2\core_core_cr_wr_ok$next[0:0]$14120 $2\core_core_core_cr_wr$next[7:0]$14092 $2\core_core_core_cr_rd_ok$next[0:0]$14091 $2\core_core_core_cr_rd$next[7:0]$14090 $2\core_core_core_trapaddr$next[12:0]$14111 $2\core_core_core_exc_$signal$9$next[0:0]$14099 $2\core_core_core_exc_$signal$8$next[0:0]$14098 $2\core_core_core_exc_$signal$7$next[0:0]$14097 $2\core_core_core_exc_$signal$6$next[0:0]$14096 $2\core_core_core_exc_$signal$5$next[0:0]$14095 $2\core_core_core_exc_$signal$4$next[0:0]$14094 $2\core_core_core_exc_$signal$3$next[0:0]$14093 $2\core_core_core_exc_$signal$next[0:0]$14100 $2\core_core_core_traptype$next[7:0]$14112 $2\core_core_core_input_carry$next[1:0]$14102 $2\core_core_core_oe_ok$next[0:0]$14108 $2\core_core_core_oe$next[0:0]$14107 $2\core_core_core_rc_ok$next[0:0]$14110 $2\core_core_core_rc$next[0:0]$14109 $2\core_core_lk$next[0:0]$14128 $2\core_core_core_fn_unit$next[13:0]$14101 $2\core_core_core_insn_type$next[6:0]$14104 $2\core_core_core_insn$next[31:0]$14103 $2\core_core_core_cia$next[63:0]$14089 $2\core_core_core_msr$next[63:0]$14106 $2\core_cr_out_ok$next[0:0]$14140 $2\core_core_cr_out$next[6:0]$14119 $2\core_core_cr_in2_ok$2$next[0:0]$14117 $2\core_core_cr_in2$1$next[6:0]$14115 $2\core_core_cr_in2_ok$next[0:0]$14118 $2\core_core_cr_in2$next[6:0]$14116 $2\core_core_cr_in1_ok$next[0:0]$14114 $2\core_core_cr_in1$next[6:0]$14113 $2\core_fasto2_ok$next[0:0]$14143 $2\core_core_fasto2$next[2:0]$14127 $2\core_fasto1_ok$next[0:0]$14142 $2\core_core_fasto1$next[2:0]$14126 $2\core_core_fast2_ok$next[0:0]$14125 $2\core_core_fast2$next[2:0]$14124 $2\core_core_fast1_ok$next[0:0]$14123 $2\core_core_fast1$next[2:0]$14122 $2\core_xer_out$next[0:0]$14146 $2\core_core_xer_in$next[2:0]$14139 $2\core_core_spr1_ok$next[0:0]$14137 $2\core_core_spr1$next[9:0]$14136 $2\core_spro_ok$next[0:0]$14145 $2\core_core_spro$next[9:0]$14138 $2\core_core_reg3_ok$next[0:0]$14134 $2\core_core_reg3$next[6:0]$14133 $2\core_core_reg2_ok$next[0:0]$14132 $2\core_core_reg2$next[6:0]$14131 $2\core_core_reg1_ok$next[0:0]$14130 $2\core_core_reg1$next[6:0]$14129 $2\core_ea_ok$next[0:0]$14141 $2\core_core_ea$next[6:0]$14121 $2\core_rego_ok$next[0:0]$14144 $2\core_core_rego$next[6:0]$14135 $2\core_asmcode$next[7:0]$14088 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $2\core_core_core_is_32bit$next[0:0]$13917 $2\core_core_cr_wr_ok$next[0:0]$13932 $2\core_core_core_cr_wr$next[7:0]$13904 $2\core_core_core_cr_rd_ok$next[0:0]$13903 $2\core_core_core_cr_rd$next[7:0]$13902 $2\core_core_core_trapaddr$next[12:0]$13923 $2\core_core_core_exc_$signal$9$next[0:0]$13911 $2\core_core_core_exc_$signal$8$next[0:0]$13910 $2\core_core_core_exc_$signal$7$next[0:0]$13909 $2\core_core_core_exc_$signal$6$next[0:0]$13908 $2\core_core_core_exc_$signal$5$next[0:0]$13907 $2\core_core_core_exc_$signal$4$next[0:0]$13906 $2\core_core_core_exc_$signal$3$next[0:0]$13905 $2\core_core_core_exc_$signal$next[0:0]$13912 $2\core_core_core_traptype$next[7:0]$13924 $2\core_core_core_input_carry$next[1:0]$13914 $2\core_core_core_oe_ok$next[0:0]$13920 $2\core_core_core_oe$next[0:0]$13919 $2\core_core_core_rc_ok$next[0:0]$13922 $2\core_core_core_rc$next[0:0]$13921 $2\core_core_lk$next[0:0]$13940 $2\core_core_core_fn_unit$next[13:0]$13913 $2\core_core_core_insn_type$next[6:0]$13916 $2\core_core_core_insn$next[31:0]$13915 $2\core_core_core_cia$next[63:0]$13901 $2\core_core_core_msr$next[63:0]$13918 $2\core_cr_out_ok$next[0:0]$13952 $2\core_core_cr_out$next[6:0]$13931 $2\core_core_cr_in2_ok$2$next[0:0]$13929 $2\core_core_cr_in2$1$next[6:0]$13927 $2\core_core_cr_in2_ok$next[0:0]$13930 $2\core_core_cr_in2$next[6:0]$13928 $2\core_core_cr_in1_ok$next[0:0]$13926 $2\core_core_cr_in1$next[6:0]$13925 $2\core_fasto2_ok$next[0:0]$13955 $2\core_core_fasto2$next[2:0]$13939 $2\core_fasto1_ok$next[0:0]$13954 $2\core_core_fasto1$next[2:0]$13938 $2\core_core_fast2_ok$next[0:0]$13937 $2\core_core_fast2$next[2:0]$13936 $2\core_core_fast1_ok$next[0:0]$13935 $2\core_core_fast1$next[2:0]$13934 $2\core_xer_out$next[0:0]$13958 $2\core_core_xer_in$next[2:0]$13951 $2\core_core_spr1_ok$next[0:0]$13949 $2\core_core_spr1$next[9:0]$13948 $2\core_spro_ok$next[0:0]$13957 $2\core_core_spro$next[9:0]$13950 $2\core_core_reg3_ok$next[0:0]$13946 $2\core_core_reg3$next[6:0]$13945 $2\core_core_reg2_ok$next[0:0]$13944 $2\core_core_reg2$next[6:0]$13943 $2\core_core_reg1_ok$next[0:0]$13942 $2\core_core_reg1$next[6:0]$13941 $2\core_ea_ok$next[0:0]$13953 $2\core_core_ea$next[6:0]$13933 $2\core_rego_ok$next[0:0]$13956 $2\core_core_rego$next[6:0]$13947 $2\core_asmcode$next[7:0]$13900 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $2\core_asmcode$next[7:0]$14088 \core_asmcode
- assign $2\core_core_core_cia$next[63:0]$14089 \core_core_core_cia
- assign $2\core_core_core_cr_rd$next[7:0]$14090 \core_core_core_cr_rd
- assign $2\core_core_core_cr_rd_ok$next[0:0]$14091 \core_core_core_cr_rd_ok
- assign $2\core_core_core_cr_wr$next[7:0]$14092 \core_core_core_cr_wr
- assign $2\core_core_core_exc_$signal$3$next[0:0]$14093 \core_core_core_exc_$signal$3
- assign $2\core_core_core_exc_$signal$4$next[0:0]$14094 \core_core_core_exc_$signal$4
- assign $2\core_core_core_exc_$signal$5$next[0:0]$14095 \core_core_core_exc_$signal$5
- assign $2\core_core_core_exc_$signal$6$next[0:0]$14096 \core_core_core_exc_$signal$6
- assign $2\core_core_core_exc_$signal$7$next[0:0]$14097 \core_core_core_exc_$signal$7
- assign $2\core_core_core_exc_$signal$8$next[0:0]$14098 \core_core_core_exc_$signal$8
- assign $2\core_core_core_exc_$signal$9$next[0:0]$14099 \core_core_core_exc_$signal$9
- assign $2\core_core_core_exc_$signal$next[0:0]$14100 \core_core_core_exc_$signal
- assign $2\core_core_core_fn_unit$next[13:0]$14101 \core_core_core_fn_unit
- assign $2\core_core_core_input_carry$next[1:0]$14102 \core_core_core_input_carry
- assign $2\core_core_core_insn$next[31:0]$14103 \core_core_core_insn
- assign $2\core_core_core_insn_type$next[6:0]$14104 \core_core_core_insn_type
- assign $2\core_core_core_is_32bit$next[0:0]$14105 \core_core_core_is_32bit
- assign $2\core_core_core_msr$next[63:0]$14106 \core_core_core_msr
- assign $2\core_core_core_oe$next[0:0]$14107 \core_core_core_oe
- assign $2\core_core_core_oe_ok$next[0:0]$14108 \core_core_core_oe_ok
- assign $2\core_core_core_rc$next[0:0]$14109 \core_core_core_rc
- assign $2\core_core_core_rc_ok$next[0:0]$14110 \core_core_core_rc_ok
- assign $2\core_core_core_trapaddr$next[12:0]$14111 \core_core_core_trapaddr
- assign $2\core_core_core_traptype$next[7:0]$14112 \core_core_core_traptype
- assign $2\core_core_cr_in1$next[6:0]$14113 \core_core_cr_in1
- assign $2\core_core_cr_in1_ok$next[0:0]$14114 \core_core_cr_in1_ok
- assign $2\core_core_cr_in2$1$next[6:0]$14115 \core_core_cr_in2$1
- assign $2\core_core_cr_in2$next[6:0]$14116 \core_core_cr_in2
- assign $2\core_core_cr_in2_ok$2$next[0:0]$14117 \core_core_cr_in2_ok$2
- assign $2\core_core_cr_in2_ok$next[0:0]$14118 \core_core_cr_in2_ok
- assign $2\core_core_cr_out$next[6:0]$14119 \core_core_cr_out
- assign $2\core_core_cr_wr_ok$next[0:0]$14120 \core_core_cr_wr_ok
- assign $2\core_core_ea$next[6:0]$14121 \core_core_ea
- assign $2\core_core_fast1$next[2:0]$14122 \core_core_fast1
- assign $2\core_core_fast1_ok$next[0:0]$14123 \core_core_fast1_ok
- assign $2\core_core_fast2$next[2:0]$14124 \core_core_fast2
- assign $2\core_core_fast2_ok$next[0:0]$14125 \core_core_fast2_ok
- assign $2\core_core_fasto1$next[2:0]$14126 \core_core_fasto1
- assign $2\core_core_fasto2$next[2:0]$14127 \core_core_fasto2
- assign $2\core_core_lk$next[0:0]$14128 \core_core_lk
- assign $2\core_core_reg1$next[6:0]$14129 \core_core_reg1
- assign $2\core_core_reg1_ok$next[0:0]$14130 \core_core_reg1_ok
- assign $2\core_core_reg2$next[6:0]$14131 \core_core_reg2
- assign $2\core_core_reg2_ok$next[0:0]$14132 \core_core_reg2_ok
- assign $2\core_core_reg3$next[6:0]$14133 \core_core_reg3
- assign $2\core_core_reg3_ok$next[0:0]$14134 \core_core_reg3_ok
- assign $2\core_core_rego$next[6:0]$14135 \core_core_rego
- assign $2\core_core_spr1$next[9:0]$14136 \core_core_spr1
- assign $2\core_core_spr1_ok$next[0:0]$14137 \core_core_spr1_ok
- assign $2\core_core_spro$next[9:0]$14138 \core_core_spro
- assign $2\core_core_xer_in$next[2:0]$14139 \core_core_xer_in
- assign $2\core_cr_out_ok$next[0:0]$14140 \core_cr_out_ok
- assign $2\core_ea_ok$next[0:0]$14141 \core_ea_ok
- assign $2\core_fasto1_ok$next[0:0]$14142 \core_fasto1_ok
- assign $2\core_fasto2_ok$next[0:0]$14143 \core_fasto2_ok
- assign $2\core_rego_ok$next[0:0]$14144 \core_rego_ok
- assign $2\core_spro_ok$next[0:0]$14145 \core_spro_ok
- assign $2\core_xer_out$next[0:0]$14146 \core_xer_out
+ assign $2\core_asmcode$next[7:0]$13900 \core_asmcode
+ assign $2\core_core_core_cia$next[63:0]$13901 \core_core_core_cia
+ assign $2\core_core_core_cr_rd$next[7:0]$13902 \core_core_core_cr_rd
+ assign $2\core_core_core_cr_rd_ok$next[0:0]$13903 \core_core_core_cr_rd_ok
+ assign $2\core_core_core_cr_wr$next[7:0]$13904 \core_core_core_cr_wr
+ assign $2\core_core_core_exc_$signal$3$next[0:0]$13905 \core_core_core_exc_$signal$3
+ assign $2\core_core_core_exc_$signal$4$next[0:0]$13906 \core_core_core_exc_$signal$4
+ assign $2\core_core_core_exc_$signal$5$next[0:0]$13907 \core_core_core_exc_$signal$5
+ assign $2\core_core_core_exc_$signal$6$next[0:0]$13908 \core_core_core_exc_$signal$6
+ assign $2\core_core_core_exc_$signal$7$next[0:0]$13909 \core_core_core_exc_$signal$7
+ assign $2\core_core_core_exc_$signal$8$next[0:0]$13910 \core_core_core_exc_$signal$8
+ assign $2\core_core_core_exc_$signal$9$next[0:0]$13911 \core_core_core_exc_$signal$9
+ assign $2\core_core_core_exc_$signal$next[0:0]$13912 \core_core_core_exc_$signal
+ assign $2\core_core_core_fn_unit$next[13:0]$13913 \core_core_core_fn_unit
+ assign $2\core_core_core_input_carry$next[1:0]$13914 \core_core_core_input_carry
+ assign $2\core_core_core_insn$next[31:0]$13915 \core_core_core_insn
+ assign $2\core_core_core_insn_type$next[6:0]$13916 \core_core_core_insn_type
+ assign $2\core_core_core_is_32bit$next[0:0]$13917 \core_core_core_is_32bit
+ assign $2\core_core_core_msr$next[63:0]$13918 \core_core_core_msr
+ assign $2\core_core_core_oe$next[0:0]$13919 \core_core_core_oe
+ assign $2\core_core_core_oe_ok$next[0:0]$13920 \core_core_core_oe_ok
+ assign $2\core_core_core_rc$next[0:0]$13921 \core_core_core_rc
+ assign $2\core_core_core_rc_ok$next[0:0]$13922 \core_core_core_rc_ok
+ assign $2\core_core_core_trapaddr$next[12:0]$13923 \core_core_core_trapaddr
+ assign $2\core_core_core_traptype$next[7:0]$13924 \core_core_core_traptype
+ assign $2\core_core_cr_in1$next[6:0]$13925 \core_core_cr_in1
+ assign $2\core_core_cr_in1_ok$next[0:0]$13926 \core_core_cr_in1_ok
+ assign $2\core_core_cr_in2$1$next[6:0]$13927 \core_core_cr_in2$1
+ assign $2\core_core_cr_in2$next[6:0]$13928 \core_core_cr_in2
+ assign $2\core_core_cr_in2_ok$2$next[0:0]$13929 \core_core_cr_in2_ok$2
+ assign $2\core_core_cr_in2_ok$next[0:0]$13930 \core_core_cr_in2_ok
+ assign $2\core_core_cr_out$next[6:0]$13931 \core_core_cr_out
+ assign $2\core_core_cr_wr_ok$next[0:0]$13932 \core_core_cr_wr_ok
+ assign $2\core_core_ea$next[6:0]$13933 \core_core_ea
+ assign $2\core_core_fast1$next[2:0]$13934 \core_core_fast1
+ assign $2\core_core_fast1_ok$next[0:0]$13935 \core_core_fast1_ok
+ assign $2\core_core_fast2$next[2:0]$13936 \core_core_fast2
+ assign $2\core_core_fast2_ok$next[0:0]$13937 \core_core_fast2_ok
+ assign $2\core_core_fasto1$next[2:0]$13938 \core_core_fasto1
+ assign $2\core_core_fasto2$next[2:0]$13939 \core_core_fasto2
+ assign $2\core_core_lk$next[0:0]$13940 \core_core_lk
+ assign $2\core_core_reg1$next[6:0]$13941 \core_core_reg1
+ assign $2\core_core_reg1_ok$next[0:0]$13942 \core_core_reg1_ok
+ assign $2\core_core_reg2$next[6:0]$13943 \core_core_reg2
+ assign $2\core_core_reg2_ok$next[0:0]$13944 \core_core_reg2_ok
+ assign $2\core_core_reg3$next[6:0]$13945 \core_core_reg3
+ assign $2\core_core_reg3_ok$next[0:0]$13946 \core_core_reg3_ok
+ assign $2\core_core_rego$next[6:0]$13947 \core_core_rego
+ assign $2\core_core_spr1$next[9:0]$13948 \core_core_spr1
+ assign $2\core_core_spr1_ok$next[0:0]$13949 \core_core_spr1_ok
+ assign $2\core_core_spro$next[9:0]$13950 \core_core_spro
+ assign $2\core_core_xer_in$next[2:0]$13951 \core_core_xer_in
+ assign $2\core_cr_out_ok$next[0:0]$13952 \core_cr_out_ok
+ assign $2\core_ea_ok$next[0:0]$13953 \core_ea_ok
+ assign $2\core_fasto1_ok$next[0:0]$13954 \core_fasto1_ok
+ assign $2\core_fasto2_ok$next[0:0]$13955 \core_fasto2_ok
+ assign $2\core_rego_ok$next[0:0]$13956 \core_rego_ok
+ assign $2\core_spro_ok$next[0:0]$13957 \core_spro_ok
+ assign $2\core_xer_out$next[0:0]$13958 \core_xer_out
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_core_is_32bit$next[0:0]$14046 $1\core_core_cr_wr_ok$next[0:0]$14061 $1\core_core_core_cr_wr$next[7:0]$14033 $1\core_core_core_cr_rd_ok$next[0:0]$14032 $1\core_core_core_cr_rd$next[7:0]$14031 $1\core_core_core_trapaddr$next[12:0]$14052 $1\core_core_core_exc_$signal$9$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$14034 $1\core_core_core_exc_$signal$next[0:0]$14041 $1\core_core_core_traptype$next[7:0]$14053 $1\core_core_core_input_carry$next[1:0]$14043 $1\core_core_core_oe_ok$next[0:0]$14049 $1\core_core_core_oe$next[0:0]$14048 $1\core_core_core_rc_ok$next[0:0]$14051 $1\core_core_core_rc$next[0:0]$14050 $1\core_core_lk$next[0:0]$14069 $1\core_core_core_fn_unit$next[13:0]$14042 $1\core_core_core_insn_type$next[6:0]$14045 $1\core_core_core_insn$next[31:0]$14044 $1\core_core_core_cia$next[63:0]$14030 $1\core_core_core_msr$next[63:0]$14047 $1\core_cr_out_ok$next[0:0]$14081 $1\core_core_cr_out$next[6:0]$14060 $1\core_core_cr_in2_ok$2$next[0:0]$14058 $1\core_core_cr_in2$1$next[6:0]$14056 $1\core_core_cr_in2_ok$next[0:0]$14059 $1\core_core_cr_in2$next[6:0]$14057 $1\core_core_cr_in1_ok$next[0:0]$14055 $1\core_core_cr_in1$next[6:0]$14054 $1\core_fasto2_ok$next[0:0]$14084 $1\core_core_fasto2$next[2:0]$14068 $1\core_fasto1_ok$next[0:0]$14083 $1\core_core_fasto1$next[2:0]$14067 $1\core_core_fast2_ok$next[0:0]$14066 $1\core_core_fast2$next[2:0]$14065 $1\core_core_fast1_ok$next[0:0]$14064 $1\core_core_fast1$next[2:0]$14063 $1\core_xer_out$next[0:0]$14087 $1\core_core_xer_in$next[2:0]$14080 $1\core_core_spr1_ok$next[0:0]$14078 $1\core_core_spr1$next[9:0]$14077 $1\core_spro_ok$next[0:0]$14086 $1\core_core_spro$next[9:0]$14079 $1\core_core_reg3_ok$next[0:0]$14075 $1\core_core_reg3$next[6:0]$14074 $1\core_core_reg2_ok$next[0:0]$14073 $1\core_core_reg2$next[6:0]$14072 $1\core_core_reg1_ok$next[0:0]$14071 $1\core_core_reg1$next[6:0]$14070 $1\core_ea_ok$next[0:0]$14082 $1\core_core_ea$next[6:0]$14062 $1\core_rego_ok$next[0:0]$14085 $1\core_core_rego$next[6:0]$14076 $1\core_asmcode$next[7:0]$14029 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $1\core_core_core_is_32bit$next[0:0]$13858 $1\core_core_cr_wr_ok$next[0:0]$13873 $1\core_core_core_cr_wr$next[7:0]$13845 $1\core_core_core_cr_rd_ok$next[0:0]$13844 $1\core_core_core_cr_rd$next[7:0]$13843 $1\core_core_core_trapaddr$next[12:0]$13864 $1\core_core_core_exc_$signal$9$next[0:0]$13852 $1\core_core_core_exc_$signal$8$next[0:0]$13851 $1\core_core_core_exc_$signal$7$next[0:0]$13850 $1\core_core_core_exc_$signal$6$next[0:0]$13849 $1\core_core_core_exc_$signal$5$next[0:0]$13848 $1\core_core_core_exc_$signal$4$next[0:0]$13847 $1\core_core_core_exc_$signal$3$next[0:0]$13846 $1\core_core_core_exc_$signal$next[0:0]$13853 $1\core_core_core_traptype$next[7:0]$13865 $1\core_core_core_input_carry$next[1:0]$13855 $1\core_core_core_oe_ok$next[0:0]$13861 $1\core_core_core_oe$next[0:0]$13860 $1\core_core_core_rc_ok$next[0:0]$13863 $1\core_core_core_rc$next[0:0]$13862 $1\core_core_lk$next[0:0]$13881 $1\core_core_core_fn_unit$next[13:0]$13854 $1\core_core_core_insn_type$next[6:0]$13857 $1\core_core_core_insn$next[31:0]$13856 $1\core_core_core_cia$next[63:0]$13842 $1\core_core_core_msr$next[63:0]$13859 $1\core_cr_out_ok$next[0:0]$13893 $1\core_core_cr_out$next[6:0]$13872 $1\core_core_cr_in2_ok$2$next[0:0]$13870 $1\core_core_cr_in2$1$next[6:0]$13868 $1\core_core_cr_in2_ok$next[0:0]$13871 $1\core_core_cr_in2$next[6:0]$13869 $1\core_core_cr_in1_ok$next[0:0]$13867 $1\core_core_cr_in1$next[6:0]$13866 $1\core_fasto2_ok$next[0:0]$13896 $1\core_core_fasto2$next[2:0]$13880 $1\core_fasto1_ok$next[0:0]$13895 $1\core_core_fasto1$next[2:0]$13879 $1\core_core_fast2_ok$next[0:0]$13878 $1\core_core_fast2$next[2:0]$13877 $1\core_core_fast1_ok$next[0:0]$13876 $1\core_core_fast1$next[2:0]$13875 $1\core_xer_out$next[0:0]$13899 $1\core_core_xer_in$next[2:0]$13892 $1\core_core_spr1_ok$next[0:0]$13890 $1\core_core_spr1$next[9:0]$13889 $1\core_spro_ok$next[0:0]$13898 $1\core_core_spro$next[9:0]$13891 $1\core_core_reg3_ok$next[0:0]$13887 $1\core_core_reg3$next[6:0]$13886 $1\core_core_reg2_ok$next[0:0]$13885 $1\core_core_reg2$next[6:0]$13884 $1\core_core_reg1_ok$next[0:0]$13883 $1\core_core_reg1$next[6:0]$13882 $1\core_ea_ok$next[0:0]$13894 $1\core_core_ea$next[6:0]$13874 $1\core_rego_ok$next[0:0]$13897 $1\core_core_rego$next[6:0]$13888 $1\core_asmcode$next[7:0]$13841 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $1\core_asmcode$next[7:0]$14029 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$14062 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$14069 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$14076 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$14079 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$14087 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_rego_ok$next[0:0]$14172 1'0
- assign $3\core_ea_ok$next[0:0]$14169 1'0
- assign $3\core_core_reg1_ok$next[0:0]$14164 1'0
- assign $3\core_core_reg2_ok$next[0:0]$14165 1'0
- assign $3\core_core_reg3_ok$next[0:0]$14166 1'0
- assign $3\core_spro_ok$next[0:0]$14173 1'0
- assign $3\core_core_spr1_ok$next[0:0]$14167 1'0
- assign $3\core_core_fast1_ok$next[0:0]$14162 1'0
- assign $3\core_core_fast2_ok$next[0:0]$14163 1'0
- assign $3\core_fasto1_ok$next[0:0]$14170 1'0
- assign $3\core_fasto2_ok$next[0:0]$14171 1'0
- assign $3\core_core_cr_in1_ok$next[0:0]$14158 1'0
- assign $3\core_core_cr_in2_ok$next[0:0]$14160 1'0
- assign $3\core_core_cr_in2_ok$2$next[0:0]$14159 1'0
- assign $3\core_cr_out_ok$next[0:0]$14168 1'0
- assign $3\core_core_core_rc_ok$next[0:0]$14157 1'0
- assign $3\core_core_core_oe_ok$next[0:0]$14156 1'0
- assign $3\core_core_core_exc_$signal$next[0:0]$14155 1'0
- assign $3\core_core_core_exc_$signal$3$next[0:0]$14148 1'0
- assign $3\core_core_core_exc_$signal$4$next[0:0]$14149 1'0
- assign $3\core_core_core_exc_$signal$5$next[0:0]$14150 1'0
- assign $3\core_core_core_exc_$signal$6$next[0:0]$14151 1'0
- assign $3\core_core_core_exc_$signal$7$next[0:0]$14152 1'0
- assign $3\core_core_core_exc_$signal$8$next[0:0]$14153 1'0
- assign $3\core_core_core_exc_$signal$9$next[0:0]$14154 1'0
- assign $3\core_core_core_cr_rd_ok$next[0:0]$14147 1'0
- assign $3\core_core_cr_wr_ok$next[0:0]$14161 1'0
+ assign $3\core_rego_ok$next[0:0]$13984 1'0
+ assign $3\core_ea_ok$next[0:0]$13981 1'0
+ assign $3\core_core_reg1_ok$next[0:0]$13976 1'0
+ assign $3\core_core_reg2_ok$next[0:0]$13977 1'0
+ assign $3\core_core_reg3_ok$next[0:0]$13978 1'0
+ assign $3\core_spro_ok$next[0:0]$13985 1'0
+ assign $3\core_core_spr1_ok$next[0:0]$13979 1'0
+ assign $3\core_core_fast1_ok$next[0:0]$13974 1'0
+ assign $3\core_core_fast2_ok$next[0:0]$13975 1'0
+ assign $3\core_fasto1_ok$next[0:0]$13982 1'0
+ assign $3\core_fasto2_ok$next[0:0]$13983 1'0
+ assign $3\core_core_cr_in1_ok$next[0:0]$13970 1'0
+ assign $3\core_core_cr_in2_ok$next[0:0]$13972 1'0
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13971 1'0
+ assign $3\core_cr_out_ok$next[0:0]$13980 1'0
+ assign $3\core_core_core_rc_ok$next[0:0]$13969 1'0
+ assign $3\core_core_core_oe_ok$next[0:0]$13968 1'0
+ assign $3\core_core_core_exc_$signal$next[0:0]$13967 1'0
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13960 1'0
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13961 1'0
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13962 1'0
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13963 1'0
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13964 1'0
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13965 1'0
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13966 1'0
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13959 1'0
+ assign $3\core_core_cr_wr_ok$next[0:0]$13973 1'0
case
- assign $3\core_core_core_cr_rd_ok$next[0:0]$14147 $1\core_core_core_cr_rd_ok$next[0:0]$14032
- assign $3\core_core_core_exc_$signal$3$next[0:0]$14148 $1\core_core_core_exc_$signal$3$next[0:0]$14034
- assign $3\core_core_core_exc_$signal$4$next[0:0]$14149 $1\core_core_core_exc_$signal$4$next[0:0]$14035
- assign $3\core_core_core_exc_$signal$5$next[0:0]$14150 $1\core_core_core_exc_$signal$5$next[0:0]$14036
- assign $3\core_core_core_exc_$signal$6$next[0:0]$14151 $1\core_core_core_exc_$signal$6$next[0:0]$14037
- assign $3\core_core_core_exc_$signal$7$next[0:0]$14152 $1\core_core_core_exc_$signal$7$next[0:0]$14038
- assign $3\core_core_core_exc_$signal$8$next[0:0]$14153 $1\core_core_core_exc_$signal$8$next[0:0]$14039
- assign $3\core_core_core_exc_$signal$9$next[0:0]$14154 $1\core_core_core_exc_$signal$9$next[0:0]$14040
- assign $3\core_core_core_exc_$signal$next[0:0]$14155 $1\core_core_core_exc_$signal$next[0:0]$14041
- assign $3\core_core_core_oe_ok$next[0:0]$14156 $1\core_core_core_oe_ok$next[0:0]$14049
- assign $3\core_core_core_rc_ok$next[0:0]$14157 $1\core_core_core_rc_ok$next[0:0]$14051
- assign $3\core_core_cr_in1_ok$next[0:0]$14158 $1\core_core_cr_in1_ok$next[0:0]$14055
- assign $3\core_core_cr_in2_ok$2$next[0:0]$14159 $1\core_core_cr_in2_ok$2$next[0:0]$14058
- assign $3\core_core_cr_in2_ok$next[0:0]$14160 $1\core_core_cr_in2_ok$next[0:0]$14059
- assign $3\core_core_cr_wr_ok$next[0:0]$14161 $1\core_core_cr_wr_ok$next[0:0]$14061
- assign $3\core_core_fast1_ok$next[0:0]$14162 $1\core_core_fast1_ok$next[0:0]$14064
- assign $3\core_core_fast2_ok$next[0:0]$14163 $1\core_core_fast2_ok$next[0:0]$14066
- assign $3\core_core_reg1_ok$next[0:0]$14164 $1\core_core_reg1_ok$next[0:0]$14071
- assign $3\core_core_reg2_ok$next[0:0]$14165 $1\core_core_reg2_ok$next[0:0]$14073
- assign $3\core_core_reg3_ok$next[0:0]$14166 $1\core_core_reg3_ok$next[0:0]$14075
- assign $3\core_core_spr1_ok$next[0:0]$14167 $1\core_core_spr1_ok$next[0:0]$14078
- assign $3\core_cr_out_ok$next[0:0]$14168 $1\core_cr_out_ok$next[0:0]$14081
- assign $3\core_ea_ok$next[0:0]$14169 $1\core_ea_ok$next[0:0]$14082
- assign $3\core_fasto1_ok$next[0:0]$14170 $1\core_fasto1_ok$next[0:0]$14083
- assign $3\core_fasto2_ok$next[0:0]$14171 $1\core_fasto2_ok$next[0:0]$14084
- assign $3\core_rego_ok$next[0:0]$14172 $1\core_rego_ok$next[0:0]$14085
- assign $3\core_spro_ok$next[0:0]$14173 $1\core_spro_ok$next[0:0]$14086
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13959 $1\core_core_core_cr_rd_ok$next[0:0]$13844
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13960 $1\core_core_core_exc_$signal$3$next[0:0]$13846
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13961 $1\core_core_core_exc_$signal$4$next[0:0]$13847
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13962 $1\core_core_core_exc_$signal$5$next[0:0]$13848
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13963 $1\core_core_core_exc_$signal$6$next[0:0]$13849
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13964 $1\core_core_core_exc_$signal$7$next[0:0]$13850
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13965 $1\core_core_core_exc_$signal$8$next[0:0]$13851
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13966 $1\core_core_core_exc_$signal$9$next[0:0]$13852
+ assign $3\core_core_core_exc_$signal$next[0:0]$13967 $1\core_core_core_exc_$signal$next[0:0]$13853
+ assign $3\core_core_core_oe_ok$next[0:0]$13968 $1\core_core_core_oe_ok$next[0:0]$13861
+ assign $3\core_core_core_rc_ok$next[0:0]$13969 $1\core_core_core_rc_ok$next[0:0]$13863
+ assign $3\core_core_cr_in1_ok$next[0:0]$13970 $1\core_core_cr_in1_ok$next[0:0]$13867
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13971 $1\core_core_cr_in2_ok$2$next[0:0]$13870
+ assign $3\core_core_cr_in2_ok$next[0:0]$13972 $1\core_core_cr_in2_ok$next[0:0]$13871
+ assign $3\core_core_cr_wr_ok$next[0:0]$13973 $1\core_core_cr_wr_ok$next[0:0]$13873
+ assign $3\core_core_fast1_ok$next[0:0]$13974 $1\core_core_fast1_ok$next[0:0]$13876
+ assign $3\core_core_fast2_ok$next[0:0]$13975 $1\core_core_fast2_ok$next[0:0]$13878
+ assign $3\core_core_reg1_ok$next[0:0]$13976 $1\core_core_reg1_ok$next[0:0]$13883
+ assign $3\core_core_reg2_ok$next[0:0]$13977 $1\core_core_reg2_ok$next[0:0]$13885
+ assign $3\core_core_reg3_ok$next[0:0]$13978 $1\core_core_reg3_ok$next[0:0]$13887
+ assign $3\core_core_spr1_ok$next[0:0]$13979 $1\core_core_spr1_ok$next[0:0]$13890
+ assign $3\core_cr_out_ok$next[0:0]$13980 $1\core_cr_out_ok$next[0:0]$13893
+ assign $3\core_ea_ok$next[0:0]$13981 $1\core_ea_ok$next[0:0]$13894
+ assign $3\core_fasto1_ok$next[0:0]$13982 $1\core_fasto1_ok$next[0:0]$13895
+ assign $3\core_fasto2_ok$next[0:0]$13983 $1\core_fasto2_ok$next[0:0]$13896
+ assign $3\core_rego_ok$next[0:0]$13984 $1\core_rego_ok$next[0:0]$13897
+ assign $3\core_spro_ok$next[0:0]$13985 $1\core_spro_ok$next[0:0]$13898
end
sync always
- update \core_asmcode$next $0\core_asmcode$next[7:0]$13970
- update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13971
- update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13972
- update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13973
- update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13974
- update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13975
- update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13976
- update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13977
- update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13978
- update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13979
- update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13980
- update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13981
- update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13982
- update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13983
- update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13984
- update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13985
- update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13986
- update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13987
- update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13988
- update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13989
- update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13990
- update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13991
- update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13992
- update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13993
- update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13994
- update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13995
- update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13996
- update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13997
- update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13998
- update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13999
- update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14000
- update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14001
- update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14002
- update \core_core_ea$next $0\core_core_ea$next[6:0]$14003
- update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14004
- update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14005
- update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14006
- update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14007
- update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14008
- update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14009
- update \core_core_lk$next $0\core_core_lk$next[0:0]$14010
- update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14011
- update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14012
- update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14013
- update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14014
- update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14015
- update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14016
- update \core_core_rego$next $0\core_core_rego$next[6:0]$14017
- update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14018
- update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14019
- update \core_core_spro$next $0\core_core_spro$next[9:0]$14020
- update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14021
- update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14022
- update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14023
- update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14024
- update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14025
- update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14026
- update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14027
- update \core_xer_out$next $0\core_xer_out$next[0:0]$14028
- end
- attribute \src "libresoc.v:201686.3-201694.6"
- process $proc$libresoc.v:201686$14174
- assign { } { }
- assign { } { }
- assign $0\dec2_cur_eint$next[0:0]$14175 $1\dec2_cur_eint$next[0:0]$14176
- attribute \src "libresoc.v:201687.5-201687.29"
- switch \initial
- attribute \src "libresoc.v:201687.9-201687.17"
+ update \core_asmcode$next $0\core_asmcode$next[7:0]$13782
+ update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13783
+ update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13784
+ update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13785
+ update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13786
+ update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13787
+ update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13788
+ update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13789
+ update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13790
+ update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13791
+ update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13792
+ update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13793
+ update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13794
+ update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13795
+ update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13796
+ update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13797
+ update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13798
+ update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13799
+ update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13800
+ update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13801
+ update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13802
+ update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13803
+ update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13804
+ update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13805
+ update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13806
+ update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13807
+ update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13808
+ update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13809
+ update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13810
+ update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13811
+ update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13812
+ update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13813
+ update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13814
+ update \core_core_ea$next $0\core_core_ea$next[6:0]$13815
+ update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13816
+ update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13817
+ update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13818
+ update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13819
+ update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13820
+ update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13821
+ update \core_core_lk$next $0\core_core_lk$next[0:0]$13822
+ update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13823
+ update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13824
+ update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13825
+ update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13826
+ update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13827
+ update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13828
+ update \core_core_rego$next $0\core_core_rego$next[6:0]$13829
+ update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13830
+ update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13831
+ update \core_core_spro$next $0\core_core_spro$next[9:0]$13832
+ update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13833
+ update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13834
+ update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13835
+ update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13836
+ update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13837
+ update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13838
+ update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13839
+ update \core_xer_out$next $0\core_xer_out$next[0:0]$13840
+ end
+ attribute \src "libresoc.v:200630.3-200638.6"
+ process $proc$libresoc.v:200630$13986
+ assign { } { }
+ assign { } { }
+ assign $0\dec2_cur_eint$next[0:0]$13987 $1\dec2_cur_eint$next[0:0]$13988
+ attribute \src "libresoc.v:200631.5-200631.29"
+ switch \initial
+ attribute \src "libresoc.v:200631.9-200631.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dec2_cur_eint$next[0:0]$14176 1'0
+ assign $1\dec2_cur_eint$next[0:0]$13988 1'0
case
- assign $1\dec2_cur_eint$next[0:0]$14176 \xics_icp_core_irq_o
+ assign $1\dec2_cur_eint$next[0:0]$13988 \xics_icp_core_irq_o
end
sync always
- update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14175
+ update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13987
end
- attribute \src "libresoc.v:201695.3-201704.6"
- process $proc$libresoc.v:201695$14177
+ attribute \src "libresoc.v:200639.3-200648.6"
+ process $proc$libresoc.v:200639$13989
assign { } { }
assign { } { }
- assign $0\delay$next[1:0]$14178 $1\delay$next[1:0]$14179
- attribute \src "libresoc.v:201696.5-201696.29"
+ assign $0\delay$next[1:0]$13990 $1\delay$next[1:0]$13991
+ attribute \src "libresoc.v:200640.5-200640.29"
switch \initial
- attribute \src "libresoc.v:201696.9-201696.17"
+ attribute \src "libresoc.v:200640.9-200640.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
switch \$23
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\delay$next[1:0]$14179 \$25 [1:0]
+ assign $1\delay$next[1:0]$13991 \$25 [1:0]
case
- assign $1\delay$next[1:0]$14179 \delay
+ assign $1\delay$next[1:0]$13991 \delay
end
sync always
- update \delay$next $0\delay$next[1:0]$14178
+ update \delay$next $0\delay$next[1:0]$13990
end
- connect \$101 $add$libresoc.v:198689$13479_Y
- connect \$103 $mul$libresoc.v:198690$13480_Y
- connect \$99 $shr$libresoc.v:198691$13481_Y [31:0]
- connect \$106 $not$libresoc.v:198692$13482_Y
- connect \$108 $not$libresoc.v:198693$13483_Y
- connect \$110 $and$libresoc.v:198694$13484_Y
- connect \$112 $not$libresoc.v:198695$13485_Y
- connect \$114 $not$libresoc.v:198696$13486_Y
- connect \$116 $and$libresoc.v:198697$13487_Y
- connect \$118 $or$libresoc.v:198698$13488_Y
+ connect \$101 $add$libresoc.v:197633$13291_Y
+ connect \$103 $mul$libresoc.v:197634$13292_Y
+ connect \$99 $shr$libresoc.v:197635$13293_Y [31:0]
+ connect \$106 $not$libresoc.v:197636$13294_Y
+ connect \$108 $not$libresoc.v:197637$13295_Y
+ connect \$110 $and$libresoc.v:197638$13296_Y
+ connect \$112 $not$libresoc.v:197639$13297_Y
+ connect \$114 $not$libresoc.v:197640$13298_Y
+ connect \$116 $and$libresoc.v:197641$13299_Y
+ connect \$118 $or$libresoc.v:197642$13300_Y
connect \$120 1'1
- connect \$122 $or$libresoc.v:198700$13489_Y
- connect \$125 $add$libresoc.v:198701$13490_Y
- connect \$128 $add$libresoc.v:198702$13491_Y
- connect \$130 $not$libresoc.v:198703$13492_Y
- connect \$132 $not$libresoc.v:198704$13493_Y
- connect \$134 $and$libresoc.v:198705$13494_Y
- connect \$136 $not$libresoc.v:198706$13495_Y
- connect \$138 $not$libresoc.v:198707$13496_Y
- connect \$140 $and$libresoc.v:198708$13497_Y
- connect \$142 $eq$libresoc.v:198709$13498_Y
- connect \$144 $and$libresoc.v:198710$13499_Y
- connect \$146 $not$libresoc.v:198711$13500_Y
- connect \$148 $not$libresoc.v:198712$13501_Y
- connect \$150 $and$libresoc.v:198713$13502_Y
- connect \$152 $or$libresoc.v:198714$13503_Y
+ connect \$122 $or$libresoc.v:197644$13301_Y
+ connect \$125 $add$libresoc.v:197645$13302_Y
+ connect \$128 $add$libresoc.v:197646$13303_Y
+ connect \$130 $not$libresoc.v:197647$13304_Y
+ connect \$132 $not$libresoc.v:197648$13305_Y
+ connect \$134 $and$libresoc.v:197649$13306_Y
+ connect \$136 $not$libresoc.v:197650$13307_Y
+ connect \$138 $not$libresoc.v:197651$13308_Y
+ connect \$140 $and$libresoc.v:197652$13309_Y
+ connect \$142 $eq$libresoc.v:197653$13310_Y
+ connect \$144 $and$libresoc.v:197654$13311_Y
+ connect \$146 $not$libresoc.v:197655$13312_Y
+ connect \$148 $not$libresoc.v:197656$13313_Y
+ connect \$150 $and$libresoc.v:197657$13314_Y
+ connect \$152 $or$libresoc.v:197658$13315_Y
connect \$154 1'1
- connect \$156 $or$libresoc.v:198716$13504_Y
- connect \$158 $not$libresoc.v:198717$13505_Y
- connect \$160 $not$libresoc.v:198718$13506_Y
- connect \$162 $and$libresoc.v:198719$13507_Y
- connect \$164 $not$libresoc.v:198720$13508_Y
- connect \$166 $not$libresoc.v:198721$13509_Y
- connect \$168 $and$libresoc.v:198722$13510_Y
- connect \$170 $not$libresoc.v:198723$13511_Y
- connect \$172 $not$libresoc.v:198724$13512_Y
- connect \$174 $and$libresoc.v:198725$13513_Y
- connect \$176 $not$libresoc.v:198726$13514_Y
- connect \$178 $not$libresoc.v:198727$13515_Y
- connect \$180 $and$libresoc.v:198728$13516_Y
- connect \$182 $not$libresoc.v:198729$13517_Y
- connect \$184 $not$libresoc.v:198730$13518_Y
- connect \$186 $and$libresoc.v:198731$13519_Y
- connect \$188 $not$libresoc.v:198732$13520_Y
- connect \$190 $not$libresoc.v:198733$13521_Y
- connect \$192 $and$libresoc.v:198734$13522_Y
- connect \$195 $and$libresoc.v:198735$13523_Y
- connect \$194 $reduce_or$libresoc.v:198736$13524_Y
- connect \$198 $not$libresoc.v:198737$13525_Y
- connect \$200 $not$libresoc.v:198738$13526_Y
- connect \$202 $and$libresoc.v:198739$13527_Y
- connect \$204 $not$libresoc.v:198740$13528_Y
- connect \$206 $not$libresoc.v:198741$13529_Y
- connect \$208 $and$libresoc.v:198742$13530_Y
- connect \$210 $or$libresoc.v:198743$13531_Y
+ connect \$156 $or$libresoc.v:197660$13316_Y
+ connect \$158 $not$libresoc.v:197661$13317_Y
+ connect \$160 $not$libresoc.v:197662$13318_Y
+ connect \$162 $and$libresoc.v:197663$13319_Y
+ connect \$164 $not$libresoc.v:197664$13320_Y
+ connect \$166 $not$libresoc.v:197665$13321_Y
+ connect \$168 $and$libresoc.v:197666$13322_Y
+ connect \$170 $not$libresoc.v:197667$13323_Y
+ connect \$172 $not$libresoc.v:197668$13324_Y
+ connect \$174 $and$libresoc.v:197669$13325_Y
+ connect \$176 $not$libresoc.v:197670$13326_Y
+ connect \$178 $not$libresoc.v:197671$13327_Y
+ connect \$180 $and$libresoc.v:197672$13328_Y
+ connect \$182 $not$libresoc.v:197673$13329_Y
+ connect \$184 $not$libresoc.v:197674$13330_Y
+ connect \$186 $and$libresoc.v:197675$13331_Y
+ connect \$188 $not$libresoc.v:197676$13332_Y
+ connect \$190 $not$libresoc.v:197677$13333_Y
+ connect \$192 $and$libresoc.v:197678$13334_Y
+ connect \$195 $and$libresoc.v:197679$13335_Y
+ connect \$194 $reduce_or$libresoc.v:197680$13336_Y
+ connect \$198 $not$libresoc.v:197681$13337_Y
+ connect \$200 $not$libresoc.v:197682$13338_Y
+ connect \$202 $and$libresoc.v:197683$13339_Y
+ connect \$204 $not$libresoc.v:197684$13340_Y
+ connect \$206 $not$libresoc.v:197685$13341_Y
+ connect \$208 $and$libresoc.v:197686$13342_Y
+ connect \$210 $or$libresoc.v:197687$13343_Y
connect \$212 1'1
- connect \$214 $or$libresoc.v:198745$13532_Y
- connect \$216 $not$libresoc.v:198746$13533_Y
- connect \$218 $not$libresoc.v:198747$13534_Y
- connect \$220 $and$libresoc.v:198748$13535_Y
- connect \$222 $not$libresoc.v:198749$13536_Y
- connect \$224 $not$libresoc.v:198750$13537_Y
- connect \$226 $and$libresoc.v:198751$13538_Y
- connect \$229 $and$libresoc.v:198752$13539_Y
- connect \$228 $reduce_or$libresoc.v:198753$13540_Y
- connect \$232 $eq$libresoc.v:198754$13541_Y
- connect \$234 $and$libresoc.v:198755$13542_Y
- connect \$236 $not$libresoc.v:198756$13543_Y
- connect \$238 $not$libresoc.v:198757$13544_Y
- connect \$23 $ne$libresoc.v:198758$13545_Y
- connect \$240 $not$libresoc.v:198759$13546_Y
- connect \$242 $and$libresoc.v:198760$13547_Y
- connect \$244 $not$libresoc.v:198761$13548_Y
- connect \$246 $not$libresoc.v:198762$13549_Y
- connect \$248 $and$libresoc.v:198763$13550_Y
- connect \$250 $eq$libresoc.v:198764$13551_Y
- connect \$252 $pos$libresoc.v:198765$13552_Y
- connect \$254 $ne$libresoc.v:198766$13553_Y
- connect \$256 $not$libresoc.v:198767$13554_Y
- connect \$258 $not$libresoc.v:198768$13555_Y
- connect \$260 $pos$libresoc.v:198769$13557_Y
- connect \$262 $pos$libresoc.v:198770$13559_Y
- connect \$265 $sub$libresoc.v:198771$13560_Y
- connect \$268 $add$libresoc.v:198772$13561_Y
- connect \$26 $sub$libresoc.v:198773$13562_Y
- connect \$28 $or$libresoc.v:198774$13563_Y
- connect \$30 $or$libresoc.v:198775$13564_Y
- connect \$32 $ne$libresoc.v:198776$13565_Y
- connect \$34 $not$libresoc.v:198777$13566_Y
- connect \$36 $and$libresoc.v:198778$13567_Y
- connect \$38 $not$libresoc.v:198779$13568_Y
- connect \$40 $not$libresoc.v:198780$13569_Y
- connect \$42 $pos$libresoc.v:198781$13571_Y
- connect \$44 $not$libresoc.v:198782$13572_Y
- connect \$46 $not$libresoc.v:198783$13573_Y
- connect \$48 $and$libresoc.v:198784$13574_Y
- connect \$50 $eq$libresoc.v:198785$13575_Y
- connect \$52 $and$libresoc.v:198786$13576_Y
- connect \$54 $not$libresoc.v:198787$13577_Y
- connect \$56 $not$libresoc.v:198788$13578_Y
- connect \$58 $and$libresoc.v:198789$13579_Y
- connect \$60 $or$libresoc.v:198790$13580_Y
+ connect \$214 $or$libresoc.v:197689$13344_Y
+ connect \$216 $not$libresoc.v:197690$13345_Y
+ connect \$218 $not$libresoc.v:197691$13346_Y
+ connect \$220 $and$libresoc.v:197692$13347_Y
+ connect \$222 $not$libresoc.v:197693$13348_Y
+ connect \$224 $not$libresoc.v:197694$13349_Y
+ connect \$226 $and$libresoc.v:197695$13350_Y
+ connect \$229 $and$libresoc.v:197696$13351_Y
+ connect \$228 $reduce_or$libresoc.v:197697$13352_Y
+ connect \$232 $eq$libresoc.v:197698$13353_Y
+ connect \$234 $and$libresoc.v:197699$13354_Y
+ connect \$236 $not$libresoc.v:197700$13355_Y
+ connect \$238 $not$libresoc.v:197701$13356_Y
+ connect \$23 $ne$libresoc.v:197702$13357_Y
+ connect \$240 $not$libresoc.v:197703$13358_Y
+ connect \$242 $and$libresoc.v:197704$13359_Y
+ connect \$244 $not$libresoc.v:197705$13360_Y
+ connect \$246 $not$libresoc.v:197706$13361_Y
+ connect \$248 $and$libresoc.v:197707$13362_Y
+ connect \$250 $eq$libresoc.v:197708$13363_Y
+ connect \$252 $pos$libresoc.v:197709$13364_Y
+ connect \$254 $ne$libresoc.v:197710$13365_Y
+ connect \$256 $not$libresoc.v:197711$13366_Y
+ connect \$258 $not$libresoc.v:197712$13367_Y
+ connect \$260 $pos$libresoc.v:197713$13369_Y
+ connect \$262 $pos$libresoc.v:197714$13371_Y
+ connect \$265 $sub$libresoc.v:197715$13372_Y
+ connect \$268 $add$libresoc.v:197716$13373_Y
+ connect \$26 $sub$libresoc.v:197717$13374_Y
+ connect \$28 $or$libresoc.v:197718$13375_Y
+ connect \$30 $or$libresoc.v:197719$13376_Y
+ connect \$32 $ne$libresoc.v:197720$13377_Y
+ connect \$34 $not$libresoc.v:197721$13378_Y
+ connect \$36 $and$libresoc.v:197722$13379_Y
+ connect \$38 $not$libresoc.v:197723$13380_Y
+ connect \$40 $not$libresoc.v:197724$13381_Y
+ connect \$42 $pos$libresoc.v:197725$13383_Y
+ connect \$44 $not$libresoc.v:197726$13384_Y
+ connect \$46 $not$libresoc.v:197727$13385_Y
+ connect \$48 $and$libresoc.v:197728$13386_Y
+ connect \$50 $eq$libresoc.v:197729$13387_Y
+ connect \$52 $and$libresoc.v:197730$13388_Y
+ connect \$54 $not$libresoc.v:197731$13389_Y
+ connect \$56 $not$libresoc.v:197732$13390_Y
+ connect \$58 $and$libresoc.v:197733$13391_Y
+ connect \$60 $or$libresoc.v:197734$13392_Y
connect \$62 1'1
- connect \$64 $or$libresoc.v:198792$13581_Y
- connect \$66 $not$libresoc.v:198793$13582_Y
- connect \$68 $not$libresoc.v:198794$13583_Y
- connect \$70 $and$libresoc.v:198795$13584_Y
- connect \$72 $eq$libresoc.v:198796$13585_Y
- connect \$74 $and$libresoc.v:198797$13586_Y
- connect \$76 $not$libresoc.v:198798$13587_Y
- connect \$78 $not$libresoc.v:198799$13588_Y
- connect \$80 $and$libresoc.v:198800$13589_Y
- connect \$82 $or$libresoc.v:198801$13590_Y
+ connect \$64 $or$libresoc.v:197736$13393_Y
+ connect \$66 $not$libresoc.v:197737$13394_Y
+ connect \$68 $not$libresoc.v:197738$13395_Y
+ connect \$70 $and$libresoc.v:197739$13396_Y
+ connect \$72 $eq$libresoc.v:197740$13397_Y
+ connect \$74 $and$libresoc.v:197741$13398_Y
+ connect \$76 $not$libresoc.v:197742$13399_Y
+ connect \$78 $not$libresoc.v:197743$13400_Y
+ connect \$80 $and$libresoc.v:197744$13401_Y
+ connect \$82 $or$libresoc.v:197745$13402_Y
connect \$84 1'1
- connect \$86 $or$libresoc.v:198803$13591_Y
- connect \$88 $not$libresoc.v:198804$13592_Y
- connect \$90 $not$libresoc.v:198805$13593_Y
- connect \$93 $add$libresoc.v:198806$13594_Y
- connect \$96 $mul$libresoc.v:198807$13595_Y
- connect \$95 $shr$libresoc.v:198808$13596_Y [31:0]
+ connect \$86 $or$libresoc.v:197747$13403_Y
+ connect \$88 $not$libresoc.v:197748$13404_Y
+ connect \$90 $not$libresoc.v:197749$13405_Y
+ connect \$93 $add$libresoc.v:197750$13406_Y
+ connect \$96 $mul$libresoc.v:197751$13407_Y
+ connect \$95 $shr$libresoc.v:197752$13408_Y [31:0]
connect \$25 \$26
connect \$92 \$93
connect \$100 \$101
connect \por_clk \clk
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
end
-attribute \src "libresoc.v:201739.1-202930.10"
+attribute \src "libresoc.v:200683.1-201874.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0"
attribute \generator "nMigen"
module \trap0
- attribute \src "libresoc.v:202475.3-202476.25"
+ attribute \src "libresoc.v:201419.3-201420.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:202473.3-202474.41"
+ attribute \src "libresoc.v:201417.3-201418.41"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:202833.3-202841.6"
- wire $0\alu_l_r_alu$next[0:0]$14501
- attribute \src "libresoc.v:202401.3-202402.39"
+ attribute \src "libresoc.v:201777.3-201785.6"
+ wire $0\alu_l_r_alu$next[0:0]$14313
+ attribute \src "libresoc.v:201345.3-201346.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14427
- attribute \src "libresoc.v:202441.3-202442.61"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14239
+ attribute \src "libresoc.v:201385.3-201386.61"
wire width 64 $0\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428
- attribute \src "libresoc.v:202435.3-202436.69"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240
+ attribute \src "libresoc.v:201379.3-201380.69"
wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14429
- attribute \src "libresoc.v:202437.3-202438.63"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14241
+ attribute \src "libresoc.v:201381.3-201382.63"
wire width 32 $0\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14430
- attribute \src "libresoc.v:202433.3-202434.73"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14242
+ attribute \src "libresoc.v:201377.3-201378.73"
wire width 7 $0\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431
- attribute \src "libresoc.v:202443.3-202444.71"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243
+ attribute \src "libresoc.v:201387.3-201388.71"
wire $0\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432
- attribute \src "libresoc.v:202449.3-202450.71"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244
+ attribute \src "libresoc.v:201393.3-201394.71"
wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14433
- attribute \src "libresoc.v:202439.3-202440.61"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14245
+ attribute \src "libresoc.v:201383.3-201384.61"
wire width 64 $0\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434
- attribute \src "libresoc.v:202447.3-202448.71"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246
+ attribute \src "libresoc.v:201391.3-201392.71"
wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14435
- attribute \src "libresoc.v:202445.3-202446.71"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14247
+ attribute \src "libresoc.v:201389.3-201390.71"
wire width 8 $0\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:202824.3-202832.6"
- wire $0\alui_l_r_alui$next[0:0]$14498
- attribute \src "libresoc.v:202403.3-202404.43"
+ attribute \src "libresoc.v:201768.3-201776.6"
+ wire $0\alui_l_r_alui$next[0:0]$14310
+ attribute \src "libresoc.v:201347.3-201348.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:202674.3-202695.6"
- wire width 64 $0\data_r0__o$next[63:0]$14446
- attribute \src "libresoc.v:202429.3-202430.37"
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire width 64 $0\data_r0__o$next[63:0]$14258
+ attribute \src "libresoc.v:201373.3-201374.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:202674.3-202695.6"
- wire $0\data_r0__o_ok$next[0:0]$14447
- attribute \src "libresoc.v:202431.3-202432.43"
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire $0\data_r0__o_ok$next[0:0]$14259
+ attribute \src "libresoc.v:201375.3-201376.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:202696.3-202717.6"
- wire width 64 $0\data_r1__fast1$next[63:0]$14454
- attribute \src "libresoc.v:202425.3-202426.45"
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire width 64 $0\data_r1__fast1$next[63:0]$14266
+ attribute \src "libresoc.v:201369.3-201370.45"
wire width 64 $0\data_r1__fast1[63:0]
- attribute \src "libresoc.v:202696.3-202717.6"
- wire $0\data_r1__fast1_ok$next[0:0]$14455
- attribute \src "libresoc.v:202427.3-202428.51"
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire $0\data_r1__fast1_ok$next[0:0]$14267
+ attribute \src "libresoc.v:201371.3-201372.51"
wire $0\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:202718.3-202739.6"
- wire width 64 $0\data_r2__fast2$next[63:0]$14462
- attribute \src "libresoc.v:202421.3-202422.45"
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire width 64 $0\data_r2__fast2$next[63:0]$14274
+ attribute \src "libresoc.v:201365.3-201366.45"
wire width 64 $0\data_r2__fast2[63:0]
- attribute \src "libresoc.v:202718.3-202739.6"
- wire $0\data_r2__fast2_ok$next[0:0]$14463
- attribute \src "libresoc.v:202423.3-202424.51"
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire $0\data_r2__fast2_ok$next[0:0]$14275
+ attribute \src "libresoc.v:201367.3-201368.51"
wire $0\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:202740.3-202761.6"
- wire width 64 $0\data_r3__nia$next[63:0]$14470
- attribute \src "libresoc.v:202417.3-202418.41"
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire width 64 $0\data_r3__nia$next[63:0]$14282
+ attribute \src "libresoc.v:201361.3-201362.41"
wire width 64 $0\data_r3__nia[63:0]
- attribute \src "libresoc.v:202740.3-202761.6"
- wire $0\data_r3__nia_ok$next[0:0]$14471
- attribute \src "libresoc.v:202419.3-202420.47"
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire $0\data_r3__nia_ok$next[0:0]$14283
+ attribute \src "libresoc.v:201363.3-201364.47"
wire $0\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:202762.3-202783.6"
- wire width 64 $0\data_r4__msr$next[63:0]$14478
- attribute \src "libresoc.v:202413.3-202414.41"
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire width 64 $0\data_r4__msr$next[63:0]$14290
+ attribute \src "libresoc.v:201357.3-201358.41"
wire width 64 $0\data_r4__msr[63:0]
- attribute \src "libresoc.v:202762.3-202783.6"
- wire $0\data_r4__msr_ok$next[0:0]$14479
- attribute \src "libresoc.v:202415.3-202416.47"
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire $0\data_r4__msr_ok$next[0:0]$14291
+ attribute \src "libresoc.v:201359.3-201360.47"
wire $0\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:202842.3-202851.6"
+ attribute \src "libresoc.v:201786.3-201795.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:202852.3-202861.6"
+ attribute \src "libresoc.v:201796.3-201805.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:202862.3-202871.6"
+ attribute \src "libresoc.v:201806.3-201815.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:202872.3-202881.6"
+ attribute \src "libresoc.v:201816.3-201825.6"
wire width 64 $0\dest4_o[63:0]
- attribute \src "libresoc.v:202882.3-202891.6"
+ attribute \src "libresoc.v:201826.3-201835.6"
wire width 64 $0\dest5_o[63:0]
- attribute \src "libresoc.v:201740.7-201740.20"
+ attribute \src "libresoc.v:200684.7-200684.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:202611.3-202619.6"
- wire $0\opc_l_r_opc$next[0:0]$14412
- attribute \src "libresoc.v:202459.3-202460.39"
+ attribute \src "libresoc.v:201555.3-201563.6"
+ wire $0\opc_l_r_opc$next[0:0]$14224
+ attribute \src "libresoc.v:201403.3-201404.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:202602.3-202610.6"
- wire $0\opc_l_s_opc$next[0:0]$14409
- attribute \src "libresoc.v:202461.3-202462.39"
+ attribute \src "libresoc.v:201546.3-201554.6"
+ wire $0\opc_l_s_opc$next[0:0]$14221
+ attribute \src "libresoc.v:201405.3-201406.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:202892.3-202900.6"
- wire width 5 $0\prev_wr_go$next[4:0]$14509
- attribute \src "libresoc.v:202471.3-202472.37"
+ attribute \src "libresoc.v:201836.3-201844.6"
+ wire width 5 $0\prev_wr_go$next[4:0]$14321
+ attribute \src "libresoc.v:201415.3-201416.37"
wire width 5 $0\prev_wr_go[4:0]
- attribute \src "libresoc.v:202556.3-202565.6"
+ attribute \src "libresoc.v:201500.3-201509.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:202647.3-202655.6"
- wire width 5 $0\req_l_r_req$next[4:0]$14424
- attribute \src "libresoc.v:202451.3-202452.39"
+ attribute \src "libresoc.v:201591.3-201599.6"
+ wire width 5 $0\req_l_r_req$next[4:0]$14236
+ attribute \src "libresoc.v:201395.3-201396.39"
wire width 5 $0\req_l_r_req[4:0]
- attribute \src "libresoc.v:202638.3-202646.6"
- wire width 5 $0\req_l_s_req$next[4:0]$14421
- attribute \src "libresoc.v:202453.3-202454.39"
+ attribute \src "libresoc.v:201582.3-201590.6"
+ wire width 5 $0\req_l_s_req$next[4:0]$14233
+ attribute \src "libresoc.v:201397.3-201398.39"
wire width 5 $0\req_l_s_req[4:0]
- attribute \src "libresoc.v:202575.3-202583.6"
- wire $0\rok_l_r_rdok$next[0:0]$14400
- attribute \src "libresoc.v:202467.3-202468.41"
+ attribute \src "libresoc.v:201519.3-201527.6"
+ wire $0\rok_l_r_rdok$next[0:0]$14212
+ attribute \src "libresoc.v:201411.3-201412.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:202566.3-202574.6"
- wire $0\rok_l_s_rdok$next[0:0]$14397
- attribute \src "libresoc.v:202469.3-202470.41"
+ attribute \src "libresoc.v:201510.3-201518.6"
+ wire $0\rok_l_s_rdok$next[0:0]$14209
+ attribute \src "libresoc.v:201413.3-201414.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:202593.3-202601.6"
- wire $0\rst_l_r_rst$next[0:0]$14406
- attribute \src "libresoc.v:202463.3-202464.39"
+ attribute \src "libresoc.v:201537.3-201545.6"
+ wire $0\rst_l_r_rst$next[0:0]$14218
+ attribute \src "libresoc.v:201407.3-201408.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:202584.3-202592.6"
- wire $0\rst_l_s_rst$next[0:0]$14403
- attribute \src "libresoc.v:202465.3-202466.39"
+ attribute \src "libresoc.v:201528.3-201536.6"
+ wire $0\rst_l_s_rst$next[0:0]$14215
+ attribute \src "libresoc.v:201409.3-201410.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:202629.3-202637.6"
- wire width 4 $0\src_l_r_src$next[3:0]$14418
- attribute \src "libresoc.v:202455.3-202456.39"
+ attribute \src "libresoc.v:201573.3-201581.6"
+ wire width 4 $0\src_l_r_src$next[3:0]$14230
+ attribute \src "libresoc.v:201399.3-201400.39"
wire width 4 $0\src_l_r_src[3:0]
- attribute \src "libresoc.v:202620.3-202628.6"
- wire width 4 $0\src_l_s_src$next[3:0]$14415
- attribute \src "libresoc.v:202457.3-202458.39"
+ attribute \src "libresoc.v:201564.3-201572.6"
+ wire width 4 $0\src_l_s_src$next[3:0]$14227
+ attribute \src "libresoc.v:201401.3-201402.39"
wire width 4 $0\src_l_s_src[3:0]
- attribute \src "libresoc.v:202784.3-202793.6"
- wire width 64 $0\src_r0$next[63:0]$14486
- attribute \src "libresoc.v:202411.3-202412.29"
+ attribute \src "libresoc.v:201728.3-201737.6"
+ wire width 64 $0\src_r0$next[63:0]$14298
+ attribute \src "libresoc.v:201355.3-201356.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:202794.3-202803.6"
- wire width 64 $0\src_r1$next[63:0]$14489
- attribute \src "libresoc.v:202409.3-202410.29"
+ attribute \src "libresoc.v:201738.3-201747.6"
+ wire width 64 $0\src_r1$next[63:0]$14301
+ attribute \src "libresoc.v:201353.3-201354.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:202804.3-202813.6"
- wire width 64 $0\src_r2$next[63:0]$14492
- attribute \src "libresoc.v:202407.3-202408.29"
+ attribute \src "libresoc.v:201748.3-201757.6"
+ wire width 64 $0\src_r2$next[63:0]$14304
+ attribute \src "libresoc.v:201351.3-201352.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:202814.3-202823.6"
- wire width 64 $0\src_r3$next[63:0]$14495
- attribute \src "libresoc.v:202405.3-202406.29"
+ attribute \src "libresoc.v:201758.3-201767.6"
+ wire width 64 $0\src_r3$next[63:0]$14307
+ attribute \src "libresoc.v:201349.3-201350.29"
wire width 64 $0\src_r3[63:0]
- attribute \src "libresoc.v:201866.7-201866.24"
+ attribute \src "libresoc.v:200810.7-200810.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:201876.7-201876.26"
+ attribute \src "libresoc.v:200820.7-200820.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:202833.3-202841.6"
- wire $1\alu_l_r_alu$next[0:0]$14502
- attribute \src "libresoc.v:201884.7-201884.25"
+ attribute \src "libresoc.v:201777.3-201785.6"
+ wire $1\alu_l_r_alu$next[0:0]$14314
+ attribute \src "libresoc.v:200828.7-200828.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14436
- attribute \src "libresoc.v:201920.14-201920.59"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14248
+ attribute \src "libresoc.v:200864.14-200864.59"
wire width 64 $1\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437
- attribute \src "libresoc.v:201939.14-201939.51"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249
+ attribute \src "libresoc.v:200883.14-200883.51"
wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14438
- attribute \src "libresoc.v:201943.14-201943.45"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14250
+ attribute \src "libresoc.v:200887.14-200887.45"
wire width 32 $1\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439
- attribute \src "libresoc.v:202022.13-202022.49"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251
+ attribute \src "libresoc.v:200966.13-200966.49"
wire width 7 $1\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440
- attribute \src "libresoc.v:202026.7-202026.41"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252
+ attribute \src "libresoc.v:200970.7-200970.41"
wire $1\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441
- attribute \src "libresoc.v:202030.13-202030.48"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253
+ attribute \src "libresoc.v:200974.13-200974.48"
wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14442
- attribute \src "libresoc.v:202034.14-202034.59"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14254
+ attribute \src "libresoc.v:200978.14-200978.59"
wire width 64 $1\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443
- attribute \src "libresoc.v:202038.14-202038.52"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255
+ attribute \src "libresoc.v:200982.14-200982.52"
wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:202656.3-202673.6"
- wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14444
- attribute \src "libresoc.v:202042.13-202042.48"
+ attribute \src "libresoc.v:201600.3-201617.6"
+ wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14256
+ attribute \src "libresoc.v:200986.13-200986.48"
wire width 8 $1\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:202824.3-202832.6"
- wire $1\alui_l_r_alui$next[0:0]$14499
- attribute \src "libresoc.v:202048.7-202048.27"
+ attribute \src "libresoc.v:201768.3-201776.6"
+ wire $1\alui_l_r_alui$next[0:0]$14311
+ attribute \src "libresoc.v:200992.7-200992.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:202674.3-202695.6"
- wire width 64 $1\data_r0__o$next[63:0]$14448
- attribute \src "libresoc.v:202080.14-202080.47"
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire width 64 $1\data_r0__o$next[63:0]$14260
+ attribute \src "libresoc.v:201024.14-201024.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:202674.3-202695.6"
- wire $1\data_r0__o_ok$next[0:0]$14449
- attribute \src "libresoc.v:202084.7-202084.27"
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire $1\data_r0__o_ok$next[0:0]$14261
+ attribute \src "libresoc.v:201028.7-201028.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:202696.3-202717.6"
- wire width 64 $1\data_r1__fast1$next[63:0]$14456
- attribute \src "libresoc.v:202088.14-202088.51"
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire width 64 $1\data_r1__fast1$next[63:0]$14268
+ attribute \src "libresoc.v:201032.14-201032.51"
wire width 64 $1\data_r1__fast1[63:0]
- attribute \src "libresoc.v:202696.3-202717.6"
- wire $1\data_r1__fast1_ok$next[0:0]$14457
- attribute \src "libresoc.v:202092.7-202092.31"
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire $1\data_r1__fast1_ok$next[0:0]$14269
+ attribute \src "libresoc.v:201036.7-201036.31"
wire $1\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:202718.3-202739.6"
- wire width 64 $1\data_r2__fast2$next[63:0]$14464
- attribute \src "libresoc.v:202096.14-202096.51"
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire width 64 $1\data_r2__fast2$next[63:0]$14276
+ attribute \src "libresoc.v:201040.14-201040.51"
wire width 64 $1\data_r2__fast2[63:0]
- attribute \src "libresoc.v:202718.3-202739.6"
- wire $1\data_r2__fast2_ok$next[0:0]$14465
- attribute \src "libresoc.v:202100.7-202100.31"
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire $1\data_r2__fast2_ok$next[0:0]$14277
+ attribute \src "libresoc.v:201044.7-201044.31"
wire $1\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:202740.3-202761.6"
- wire width 64 $1\data_r3__nia$next[63:0]$14472
- attribute \src "libresoc.v:202104.14-202104.49"
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire width 64 $1\data_r3__nia$next[63:0]$14284
+ attribute \src "libresoc.v:201048.14-201048.49"
wire width 64 $1\data_r3__nia[63:0]
- attribute \src "libresoc.v:202740.3-202761.6"
- wire $1\data_r3__nia_ok$next[0:0]$14473
- attribute \src "libresoc.v:202108.7-202108.29"
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire $1\data_r3__nia_ok$next[0:0]$14285
+ attribute \src "libresoc.v:201052.7-201052.29"
wire $1\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:202762.3-202783.6"
- wire width 64 $1\data_r4__msr$next[63:0]$14480
- attribute \src "libresoc.v:202112.14-202112.49"
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire width 64 $1\data_r4__msr$next[63:0]$14292
+ attribute \src "libresoc.v:201056.14-201056.49"
wire width 64 $1\data_r4__msr[63:0]
- attribute \src "libresoc.v:202762.3-202783.6"
- wire $1\data_r4__msr_ok$next[0:0]$14481
- attribute \src "libresoc.v:202116.7-202116.29"
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire $1\data_r4__msr_ok$next[0:0]$14293
+ attribute \src "libresoc.v:201060.7-201060.29"
wire $1\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:202842.3-202851.6"
+ attribute \src "libresoc.v:201786.3-201795.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:202852.3-202861.6"
+ attribute \src "libresoc.v:201796.3-201805.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:202862.3-202871.6"
+ attribute \src "libresoc.v:201806.3-201815.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:202872.3-202881.6"
+ attribute \src "libresoc.v:201816.3-201825.6"
wire width 64 $1\dest4_o[63:0]
- attribute \src "libresoc.v:202882.3-202891.6"
+ attribute \src "libresoc.v:201826.3-201835.6"
wire width 64 $1\dest5_o[63:0]
- attribute \src "libresoc.v:202611.3-202619.6"
- wire $1\opc_l_r_opc$next[0:0]$14413
- attribute \src "libresoc.v:202147.7-202147.25"
+ attribute \src "libresoc.v:201555.3-201563.6"
+ wire $1\opc_l_r_opc$next[0:0]$14225
+ attribute \src "libresoc.v:201091.7-201091.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:202602.3-202610.6"
- wire $1\opc_l_s_opc$next[0:0]$14410
- attribute \src "libresoc.v:202151.7-202151.25"
+ attribute \src "libresoc.v:201546.3-201554.6"
+ wire $1\opc_l_s_opc$next[0:0]$14222
+ attribute \src "libresoc.v:201095.7-201095.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:202892.3-202900.6"
- wire width 5 $1\prev_wr_go$next[4:0]$14510
- attribute \src "libresoc.v:202263.13-202263.31"
+ attribute \src "libresoc.v:201836.3-201844.6"
+ wire width 5 $1\prev_wr_go$next[4:0]$14322
+ attribute \src "libresoc.v:201207.13-201207.31"
wire width 5 $1\prev_wr_go[4:0]
- attribute \src "libresoc.v:202556.3-202565.6"
+ attribute \src "libresoc.v:201500.3-201509.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:202647.3-202655.6"
- wire width 5 $1\req_l_r_req$next[4:0]$14425
- attribute \src "libresoc.v:202271.13-202271.32"
+ attribute \src "libresoc.v:201591.3-201599.6"
+ wire width 5 $1\req_l_r_req$next[4:0]$14237
+ attribute \src "libresoc.v:201215.13-201215.32"
wire width 5 $1\req_l_r_req[4:0]
- attribute \src "libresoc.v:202638.3-202646.6"
- wire width 5 $1\req_l_s_req$next[4:0]$14422
- attribute \src "libresoc.v:202275.13-202275.32"
+ attribute \src "libresoc.v:201582.3-201590.6"
+ wire width 5 $1\req_l_s_req$next[4:0]$14234
+ attribute \src "libresoc.v:201219.13-201219.32"
wire width 5 $1\req_l_s_req[4:0]
- attribute \src "libresoc.v:202575.3-202583.6"
- wire $1\rok_l_r_rdok$next[0:0]$14401
- attribute \src "libresoc.v:202287.7-202287.26"
+ attribute \src "libresoc.v:201519.3-201527.6"
+ wire $1\rok_l_r_rdok$next[0:0]$14213
+ attribute \src "libresoc.v:201231.7-201231.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:202566.3-202574.6"
- wire $1\rok_l_s_rdok$next[0:0]$14398
- attribute \src "libresoc.v:202291.7-202291.26"
+ attribute \src "libresoc.v:201510.3-201518.6"
+ wire $1\rok_l_s_rdok$next[0:0]$14210
+ attribute \src "libresoc.v:201235.7-201235.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:202593.3-202601.6"
- wire $1\rst_l_r_rst$next[0:0]$14407
- attribute \src "libresoc.v:202295.7-202295.25"
+ attribute \src "libresoc.v:201537.3-201545.6"
+ wire $1\rst_l_r_rst$next[0:0]$14219
+ attribute \src "libresoc.v:201239.7-201239.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:202584.3-202592.6"
- wire $1\rst_l_s_rst$next[0:0]$14404
- attribute \src "libresoc.v:202299.7-202299.25"
+ attribute \src "libresoc.v:201528.3-201536.6"
+ wire $1\rst_l_s_rst$next[0:0]$14216
+ attribute \src "libresoc.v:201243.7-201243.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:202629.3-202637.6"
- wire width 4 $1\src_l_r_src$next[3:0]$14419
- attribute \src "libresoc.v:202315.13-202315.31"
+ attribute \src "libresoc.v:201573.3-201581.6"
+ wire width 4 $1\src_l_r_src$next[3:0]$14231
+ attribute \src "libresoc.v:201259.13-201259.31"
wire width 4 $1\src_l_r_src[3:0]
- attribute \src "libresoc.v:202620.3-202628.6"
- wire width 4 $1\src_l_s_src$next[3:0]$14416
- attribute \src "libresoc.v:202319.13-202319.31"
+ attribute \src "libresoc.v:201564.3-201572.6"
+ wire width 4 $1\src_l_s_src$next[3:0]$14228
+ attribute \src "libresoc.v:201263.13-201263.31"
wire width 4 $1\src_l_s_src[3:0]
- attribute \src "libresoc.v:202784.3-202793.6"
- wire width 64 $1\src_r0$next[63:0]$14487
- attribute \src "libresoc.v:202323.14-202323.43"
+ attribute \src "libresoc.v:201728.3-201737.6"
+ wire width 64 $1\src_r0$next[63:0]$14299
+ attribute \src "libresoc.v:201267.14-201267.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:202794.3-202803.6"
- wire width 64 $1\src_r1$next[63:0]$14490
- attribute \src "libresoc.v:202327.14-202327.43"
+ attribute \src "libresoc.v:201738.3-201747.6"
+ wire width 64 $1\src_r1$next[63:0]$14302
+ attribute \src "libresoc.v:201271.14-201271.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:202804.3-202813.6"
- wire width 64 $1\src_r2$next[63:0]$14493
- attribute \src "libresoc.v:202331.14-202331.43"
+ attribute \src "libresoc.v:201748.3-201757.6"
+ wire width 64 $1\src_r2$next[63:0]$14305
+ attribute \src "libresoc.v:201275.14-201275.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:202814.3-202823.6"
- wire width 64 $1\src_r3$next[63:0]$14496
- attribute \src "libresoc.v:202335.14-202335.43"
+ attribute \src "libresoc.v:201758.3-201767.6"
+ wire width 64 $1\src_r3$next[63:0]$14308
+ attribute \src "libresoc.v:201279.14-201279.43"
wire width 64 $1\src_r3[63:0]
- attribute \src "libresoc.v:202674.3-202695.6"
- wire width 64 $2\data_r0__o$next[63:0]$14450
- attribute \src "libresoc.v:202674.3-202695.6"
- wire $2\data_r0__o_ok$next[0:0]$14451
- attribute \src "libresoc.v:202696.3-202717.6"
- wire width 64 $2\data_r1__fast1$next[63:0]$14458
- attribute \src "libresoc.v:202696.3-202717.6"
- wire $2\data_r1__fast1_ok$next[0:0]$14459
- attribute \src "libresoc.v:202718.3-202739.6"
- wire width 64 $2\data_r2__fast2$next[63:0]$14466
- attribute \src "libresoc.v:202718.3-202739.6"
- wire $2\data_r2__fast2_ok$next[0:0]$14467
- attribute \src "libresoc.v:202740.3-202761.6"
- wire width 64 $2\data_r3__nia$next[63:0]$14474
- attribute \src "libresoc.v:202740.3-202761.6"
- wire $2\data_r3__nia_ok$next[0:0]$14475
- attribute \src "libresoc.v:202762.3-202783.6"
- wire width 64 $2\data_r4__msr$next[63:0]$14482
- attribute \src "libresoc.v:202762.3-202783.6"
- wire $2\data_r4__msr_ok$next[0:0]$14483
- attribute \src "libresoc.v:202674.3-202695.6"
- wire $3\data_r0__o_ok$next[0:0]$14452
- attribute \src "libresoc.v:202696.3-202717.6"
- wire $3\data_r1__fast1_ok$next[0:0]$14460
- attribute \src "libresoc.v:202718.3-202739.6"
- wire $3\data_r2__fast2_ok$next[0:0]$14468
- attribute \src "libresoc.v:202740.3-202761.6"
- wire $3\data_r3__nia_ok$next[0:0]$14476
- attribute \src "libresoc.v:202762.3-202783.6"
- wire $3\data_r4__msr_ok$next[0:0]$14484
- attribute \src "libresoc.v:202341.18-202341.112"
- wire width 4 $and$libresoc.v:202341$14297_Y
- attribute \src "libresoc.v:202342.19-202342.125"
- wire $and$libresoc.v:202342$14298_Y
- attribute \src "libresoc.v:202343.19-202343.125"
- wire $and$libresoc.v:202343$14299_Y
- attribute \src "libresoc.v:202344.19-202344.125"
- wire $and$libresoc.v:202344$14300_Y
- attribute \src "libresoc.v:202345.19-202345.125"
- wire $and$libresoc.v:202345$14301_Y
- attribute \src "libresoc.v:202346.19-202346.125"
- wire $and$libresoc.v:202346$14302_Y
- attribute \src "libresoc.v:202347.19-202347.157"
- wire width 5 $and$libresoc.v:202347$14303_Y
- attribute \src "libresoc.v:202348.19-202348.121"
- wire width 5 $and$libresoc.v:202348$14304_Y
- attribute \src "libresoc.v:202349.19-202349.127"
- wire $and$libresoc.v:202349$14305_Y
- attribute \src "libresoc.v:202350.19-202350.127"
- wire $and$libresoc.v:202350$14306_Y
- attribute \src "libresoc.v:202351.18-202351.110"
- wire $and$libresoc.v:202351$14307_Y
- attribute \src "libresoc.v:202352.19-202352.127"
- wire $and$libresoc.v:202352$14308_Y
- attribute \src "libresoc.v:202353.19-202353.127"
- wire $and$libresoc.v:202353$14309_Y
- attribute \src "libresoc.v:202354.19-202354.127"
- wire $and$libresoc.v:202354$14310_Y
- attribute \src "libresoc.v:202356.18-202356.98"
- wire $and$libresoc.v:202356$14312_Y
- attribute \src "libresoc.v:202358.18-202358.100"
- wire $and$libresoc.v:202358$14314_Y
- attribute \src "libresoc.v:202359.18-202359.171"
- wire width 5 $and$libresoc.v:202359$14315_Y
- attribute \src "libresoc.v:202361.18-202361.119"
- wire width 5 $and$libresoc.v:202361$14317_Y
- attribute \src "libresoc.v:202364.18-202364.116"
- wire $and$libresoc.v:202364$14320_Y
- attribute \src "libresoc.v:202368.17-202368.123"
- wire $and$libresoc.v:202368$14324_Y
- attribute \src "libresoc.v:202370.18-202370.113"
- wire $and$libresoc.v:202370$14326_Y
- attribute \src "libresoc.v:202371.18-202371.125"
- wire width 5 $and$libresoc.v:202371$14327_Y
- attribute \src "libresoc.v:202373.18-202373.112"
- wire $and$libresoc.v:202373$14329_Y
- attribute \src "libresoc.v:202375.18-202375.127"
- wire $and$libresoc.v:202375$14331_Y
- attribute \src "libresoc.v:202376.18-202376.127"
- wire $and$libresoc.v:202376$14332_Y
- attribute \src "libresoc.v:202377.18-202377.117"
- wire $and$libresoc.v:202377$14333_Y
- attribute \src "libresoc.v:202382.18-202382.131"
- wire $and$libresoc.v:202382$14338_Y
- attribute \src "libresoc.v:202383.18-202383.124"
- wire width 5 $and$libresoc.v:202383$14339_Y
- attribute \src "libresoc.v:202386.18-202386.116"
- wire $and$libresoc.v:202386$14342_Y
- attribute \src "libresoc.v:202387.18-202387.120"
- wire $and$libresoc.v:202387$14343_Y
- attribute \src "libresoc.v:202388.18-202388.120"
- wire $and$libresoc.v:202388$14344_Y
- attribute \src "libresoc.v:202389.18-202389.118"
- wire $and$libresoc.v:202389$14345_Y
- attribute \src "libresoc.v:202390.18-202390.118"
- wire $and$libresoc.v:202390$14346_Y
- attribute \src "libresoc.v:202396.18-202396.135"
- wire $and$libresoc.v:202396$14352_Y
- attribute \src "libresoc.v:202397.18-202397.133"
- wire $and$libresoc.v:202397$14353_Y
- attribute \src "libresoc.v:202398.18-202398.160"
- wire width 4 $and$libresoc.v:202398$14354_Y
- attribute \src "libresoc.v:202399.18-202399.112"
- wire width 4 $and$libresoc.v:202399$14355_Y
- attribute \src "libresoc.v:202372.18-202372.113"
- wire $eq$libresoc.v:202372$14328_Y
- attribute \src "libresoc.v:202374.18-202374.119"
- wire $eq$libresoc.v:202374$14330_Y
- attribute \src "libresoc.v:202355.18-202355.97"
- wire $not$libresoc.v:202355$14311_Y
- attribute \src "libresoc.v:202357.18-202357.99"
- wire $not$libresoc.v:202357$14313_Y
- attribute \src "libresoc.v:202360.18-202360.113"
- wire width 5 $not$libresoc.v:202360$14316_Y
- attribute \src "libresoc.v:202363.18-202363.106"
- wire $not$libresoc.v:202363$14319_Y
- attribute \src "libresoc.v:202369.18-202369.121"
- wire $not$libresoc.v:202369$14325_Y
- attribute \src "libresoc.v:202384.17-202384.113"
- wire width 4 $not$libresoc.v:202384$14340_Y
- attribute \src "libresoc.v:202400.18-202400.114"
- wire width 4 $not$libresoc.v:202400$14356_Y
- attribute \src "libresoc.v:202367.18-202367.112"
- wire $or$libresoc.v:202367$14323_Y
- attribute \src "libresoc.v:202378.18-202378.122"
- wire $or$libresoc.v:202378$14334_Y
- attribute \src "libresoc.v:202379.18-202379.124"
- wire $or$libresoc.v:202379$14335_Y
- attribute \src "libresoc.v:202380.18-202380.181"
- wire width 5 $or$libresoc.v:202380$14336_Y
- attribute \src "libresoc.v:202381.18-202381.168"
- wire width 4 $or$libresoc.v:202381$14337_Y
- attribute \src "libresoc.v:202385.18-202385.120"
- wire width 5 $or$libresoc.v:202385$14341_Y
- attribute \src "libresoc.v:202395.17-202395.117"
- wire width 4 $or$libresoc.v:202395$14351_Y
- attribute \src "libresoc.v:202340.17-202340.104"
- wire $reduce_and$libresoc.v:202340$14296_Y
- attribute \src "libresoc.v:202362.18-202362.106"
- wire $reduce_or$libresoc.v:202362$14318_Y
- attribute \src "libresoc.v:202365.18-202365.113"
- wire $reduce_or$libresoc.v:202365$14321_Y
- attribute \src "libresoc.v:202366.18-202366.112"
- wire $reduce_or$libresoc.v:202366$14322_Y
- attribute \src "libresoc.v:202391.18-202391.118"
- wire width 64 $ternary$libresoc.v:202391$14347_Y
- attribute \src "libresoc.v:202392.18-202392.118"
- wire width 64 $ternary$libresoc.v:202392$14348_Y
- attribute \src "libresoc.v:202393.18-202393.118"
- wire width 64 $ternary$libresoc.v:202393$14349_Y
- attribute \src "libresoc.v:202394.18-202394.118"
- wire width 64 $ternary$libresoc.v:202394$14350_Y
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire width 64 $2\data_r0__o$next[63:0]$14262
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire $2\data_r0__o_ok$next[0:0]$14263
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire width 64 $2\data_r1__fast1$next[63:0]$14270
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire $2\data_r1__fast1_ok$next[0:0]$14271
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire width 64 $2\data_r2__fast2$next[63:0]$14278
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire $2\data_r2__fast2_ok$next[0:0]$14279
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire width 64 $2\data_r3__nia$next[63:0]$14286
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire $2\data_r3__nia_ok$next[0:0]$14287
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire width 64 $2\data_r4__msr$next[63:0]$14294
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire $2\data_r4__msr_ok$next[0:0]$14295
+ attribute \src "libresoc.v:201618.3-201639.6"
+ wire $3\data_r0__o_ok$next[0:0]$14264
+ attribute \src "libresoc.v:201640.3-201661.6"
+ wire $3\data_r1__fast1_ok$next[0:0]$14272
+ attribute \src "libresoc.v:201662.3-201683.6"
+ wire $3\data_r2__fast2_ok$next[0:0]$14280
+ attribute \src "libresoc.v:201684.3-201705.6"
+ wire $3\data_r3__nia_ok$next[0:0]$14288
+ attribute \src "libresoc.v:201706.3-201727.6"
+ wire $3\data_r4__msr_ok$next[0:0]$14296
+ attribute \src "libresoc.v:201285.18-201285.112"
+ wire width 4 $and$libresoc.v:201285$14109_Y
+ attribute \src "libresoc.v:201286.19-201286.125"
+ wire $and$libresoc.v:201286$14110_Y
+ attribute \src "libresoc.v:201287.19-201287.125"
+ wire $and$libresoc.v:201287$14111_Y
+ attribute \src "libresoc.v:201288.19-201288.125"
+ wire $and$libresoc.v:201288$14112_Y
+ attribute \src "libresoc.v:201289.19-201289.125"
+ wire $and$libresoc.v:201289$14113_Y
+ attribute \src "libresoc.v:201290.19-201290.125"
+ wire $and$libresoc.v:201290$14114_Y
+ attribute \src "libresoc.v:201291.19-201291.157"
+ wire width 5 $and$libresoc.v:201291$14115_Y
+ attribute \src "libresoc.v:201292.19-201292.121"
+ wire width 5 $and$libresoc.v:201292$14116_Y
+ attribute \src "libresoc.v:201293.19-201293.127"
+ wire $and$libresoc.v:201293$14117_Y
+ attribute \src "libresoc.v:201294.19-201294.127"
+ wire $and$libresoc.v:201294$14118_Y
+ attribute \src "libresoc.v:201295.18-201295.110"
+ wire $and$libresoc.v:201295$14119_Y
+ attribute \src "libresoc.v:201296.19-201296.127"
+ wire $and$libresoc.v:201296$14120_Y
+ attribute \src "libresoc.v:201297.19-201297.127"
+ wire $and$libresoc.v:201297$14121_Y
+ attribute \src "libresoc.v:201298.19-201298.127"
+ wire $and$libresoc.v:201298$14122_Y
+ attribute \src "libresoc.v:201300.18-201300.98"
+ wire $and$libresoc.v:201300$14124_Y
+ attribute \src "libresoc.v:201302.18-201302.100"
+ wire $and$libresoc.v:201302$14126_Y
+ attribute \src "libresoc.v:201303.18-201303.171"
+ wire width 5 $and$libresoc.v:201303$14127_Y
+ attribute \src "libresoc.v:201305.18-201305.119"
+ wire width 5 $and$libresoc.v:201305$14129_Y
+ attribute \src "libresoc.v:201308.18-201308.116"
+ wire $and$libresoc.v:201308$14132_Y
+ attribute \src "libresoc.v:201312.17-201312.123"
+ wire $and$libresoc.v:201312$14136_Y
+ attribute \src "libresoc.v:201314.18-201314.113"
+ wire $and$libresoc.v:201314$14138_Y
+ attribute \src "libresoc.v:201315.18-201315.125"
+ wire width 5 $and$libresoc.v:201315$14139_Y
+ attribute \src "libresoc.v:201317.18-201317.112"
+ wire $and$libresoc.v:201317$14141_Y
+ attribute \src "libresoc.v:201319.18-201319.127"
+ wire $and$libresoc.v:201319$14143_Y
+ attribute \src "libresoc.v:201320.18-201320.127"
+ wire $and$libresoc.v:201320$14144_Y
+ attribute \src "libresoc.v:201321.18-201321.117"
+ wire $and$libresoc.v:201321$14145_Y
+ attribute \src "libresoc.v:201326.18-201326.131"
+ wire $and$libresoc.v:201326$14150_Y
+ attribute \src "libresoc.v:201327.18-201327.124"
+ wire width 5 $and$libresoc.v:201327$14151_Y
+ attribute \src "libresoc.v:201330.18-201330.116"
+ wire $and$libresoc.v:201330$14154_Y
+ attribute \src "libresoc.v:201331.18-201331.120"
+ wire $and$libresoc.v:201331$14155_Y
+ attribute \src "libresoc.v:201332.18-201332.120"
+ wire $and$libresoc.v:201332$14156_Y
+ attribute \src "libresoc.v:201333.18-201333.118"
+ wire $and$libresoc.v:201333$14157_Y
+ attribute \src "libresoc.v:201334.18-201334.118"
+ wire $and$libresoc.v:201334$14158_Y
+ attribute \src "libresoc.v:201340.18-201340.135"
+ wire $and$libresoc.v:201340$14164_Y
+ attribute \src "libresoc.v:201341.18-201341.133"
+ wire $and$libresoc.v:201341$14165_Y
+ attribute \src "libresoc.v:201342.18-201342.160"
+ wire width 4 $and$libresoc.v:201342$14166_Y
+ attribute \src "libresoc.v:201343.18-201343.112"
+ wire width 4 $and$libresoc.v:201343$14167_Y
+ attribute \src "libresoc.v:201316.18-201316.113"
+ wire $eq$libresoc.v:201316$14140_Y
+ attribute \src "libresoc.v:201318.18-201318.119"
+ wire $eq$libresoc.v:201318$14142_Y
+ attribute \src "libresoc.v:201299.18-201299.97"
+ wire $not$libresoc.v:201299$14123_Y
+ attribute \src "libresoc.v:201301.18-201301.99"
+ wire $not$libresoc.v:201301$14125_Y
+ attribute \src "libresoc.v:201304.18-201304.113"
+ wire width 5 $not$libresoc.v:201304$14128_Y
+ attribute \src "libresoc.v:201307.18-201307.106"
+ wire $not$libresoc.v:201307$14131_Y
+ attribute \src "libresoc.v:201313.18-201313.121"
+ wire $not$libresoc.v:201313$14137_Y
+ attribute \src "libresoc.v:201328.17-201328.113"
+ wire width 4 $not$libresoc.v:201328$14152_Y
+ attribute \src "libresoc.v:201344.18-201344.114"
+ wire width 4 $not$libresoc.v:201344$14168_Y
+ attribute \src "libresoc.v:201311.18-201311.112"
+ wire $or$libresoc.v:201311$14135_Y
+ attribute \src "libresoc.v:201322.18-201322.122"
+ wire $or$libresoc.v:201322$14146_Y
+ attribute \src "libresoc.v:201323.18-201323.124"
+ wire $or$libresoc.v:201323$14147_Y
+ attribute \src "libresoc.v:201324.18-201324.181"
+ wire width 5 $or$libresoc.v:201324$14148_Y
+ attribute \src "libresoc.v:201325.18-201325.168"
+ wire width 4 $or$libresoc.v:201325$14149_Y
+ attribute \src "libresoc.v:201329.18-201329.120"
+ wire width 5 $or$libresoc.v:201329$14153_Y
+ attribute \src "libresoc.v:201339.17-201339.117"
+ wire width 4 $or$libresoc.v:201339$14163_Y
+ attribute \src "libresoc.v:201284.17-201284.104"
+ wire $reduce_and$libresoc.v:201284$14108_Y
+ attribute \src "libresoc.v:201306.18-201306.106"
+ wire $reduce_or$libresoc.v:201306$14130_Y
+ attribute \src "libresoc.v:201309.18-201309.113"
+ wire $reduce_or$libresoc.v:201309$14133_Y
+ attribute \src "libresoc.v:201310.18-201310.112"
+ wire $reduce_or$libresoc.v:201310$14134_Y
+ attribute \src "libresoc.v:201335.18-201335.118"
+ wire width 64 $ternary$libresoc.v:201335$14159_Y
+ attribute \src "libresoc.v:201336.18-201336.118"
+ wire width 64 $ternary$libresoc.v:201336$14160_Y
+ attribute \src "libresoc.v:201337.18-201337.118"
+ wire width 64 $ternary$libresoc.v:201337$14161_Y
+ attribute \src "libresoc.v:201338.18-201338.118"
+ wire width 64 $ternary$libresoc.v:201338$14162_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 12 \cu_busy_o
wire output 24 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 25 \fast2_ok
- attribute \src "libresoc.v:201740.7-201740.15"
+ attribute \src "libresoc.v:200684.7-200684.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 30 \msr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 16 \src1_i
+ wire width 64 input 17 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
- wire width 64 input 17 \src2_i
+ wire width 64 input 16 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 18 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:202341$14297
+ cell $and $and$libresoc.v:201285$14109
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:202341$14297_Y
+ connect \Y $and$libresoc.v:201285$14109_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:202342$14298
+ cell $and $and$libresoc.v:201286$14110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:202342$14298_Y
+ connect \Y $and$libresoc.v:201286$14110_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:202343$14299
+ cell $and $and$libresoc.v:201287$14111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:202343$14299_Y
+ connect \Y $and$libresoc.v:201287$14111_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:202344$14300
+ cell $and $and$libresoc.v:201288$14112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:202344$14300_Y
+ connect \Y $and$libresoc.v:201288$14112_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:202345$14301
+ cell $and $and$libresoc.v:201289$14113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:202345$14301_Y
+ connect \Y $and$libresoc.v:201289$14113_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:202346$14302
+ cell $and $and$libresoc.v:201290$14114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:202346$14302_Y
+ connect \Y $and$libresoc.v:201290$14114_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:202347$14303
+ cell $and $and$libresoc.v:201291$14115
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B { \$101 \$103 \$105 \$107 \$109 }
- connect \Y $and$libresoc.v:202347$14303_Y
+ connect \Y $and$libresoc.v:201291$14115_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:202348$14304
+ cell $and $and$libresoc.v:201292$14116
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$111
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:202348$14304_Y
+ connect \Y $and$libresoc.v:201292$14116_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:202349$14305
+ cell $and $and$libresoc.v:201293$14117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202349$14305_Y
+ connect \Y $and$libresoc.v:201293$14117_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:202350$14306
+ cell $and $and$libresoc.v:201294$14118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202350$14306_Y
+ connect \Y $and$libresoc.v:201294$14118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:202351$14307
+ cell $and $and$libresoc.v:201295$14119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:202351$14307_Y
+ connect \Y $and$libresoc.v:201295$14119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:202352$14308
+ cell $and $and$libresoc.v:201296$14120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202352$14308_Y
+ connect \Y $and$libresoc.v:201296$14120_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:202353$14309
+ cell $and $and$libresoc.v:201297$14121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202353$14309_Y
+ connect \Y $and$libresoc.v:201297$14121_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:202354$14310
+ cell $and $and$libresoc.v:201298$14122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202354$14310_Y
+ connect \Y $and$libresoc.v:201298$14122_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:202356$14312
+ cell $and $and$libresoc.v:201300$14124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$13
- connect \Y $and$libresoc.v:202356$14312_Y
+ connect \Y $and$libresoc.v:201300$14124_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:202358$14314
+ cell $and $and$libresoc.v:201302$14126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$17
- connect \Y $and$libresoc.v:202358$14314_Y
+ connect \Y $and$libresoc.v:201302$14126_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:202359$14315
+ cell $and $and$libresoc.v:201303$14127
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:202359$14315_Y
+ connect \Y $and$libresoc.v:201303$14127_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:202361$14317
+ cell $and $and$libresoc.v:201305$14129
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__rel_o
connect \B \$25
- connect \Y $and$libresoc.v:202361$14317_Y
+ connect \Y $and$libresoc.v:201305$14129_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:202364$14320
+ cell $and $and$libresoc.v:201308$14132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$23
- connect \Y $and$libresoc.v:202364$14320_Y
+ connect \Y $and$libresoc.v:201308$14132_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:202368$14324
+ cell $and $and$libresoc.v:201312$14136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:202368$14324_Y
+ connect \Y $and$libresoc.v:201312$14136_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:202370$14326
+ cell $and $and$libresoc.v:201314$14138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$39
- connect \Y $and$libresoc.v:202370$14326_Y
+ connect \Y $and$libresoc.v:201314$14138_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:202371$14327
+ cell $and $and$libresoc.v:201315$14139
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:202371$14327_Y
+ connect \Y $and$libresoc.v:201315$14139_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:202373$14329
+ cell $and $and$libresoc.v:201317$14141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B \$45
- connect \Y $and$libresoc.v:202373$14329_Y
+ connect \Y $and$libresoc.v:201317$14141_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:202375$14331
+ cell $and $and$libresoc.v:201319$14143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_trap0_n_ready_i
- connect \Y $and$libresoc.v:202375$14331_Y
+ connect \Y $and$libresoc.v:201319$14143_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:202376$14332
+ cell $and $and$libresoc.v:201320$14144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \alu_trap0_n_valid_o
- connect \Y $and$libresoc.v:202376$14332_Y
+ connect \Y $and$libresoc.v:201320$14144_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:202377$14333
+ cell $and $and$libresoc.v:201321$14145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202377$14333_Y
+ connect \Y $and$libresoc.v:201321$14145_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:202382$14338
+ cell $and $and$libresoc.v:201326$14150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202382$14338_Y
+ connect \Y $and$libresoc.v:201326$14150_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:202383$14339
+ cell $and $and$libresoc.v:201327$14151
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:202383$14339_Y
+ connect \Y $and$libresoc.v:201327$14151_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:202386$14342
+ cell $and $and$libresoc.v:201330$14154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202386$14342_Y
+ connect \Y $and$libresoc.v:201330$14154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:202387$14343
+ cell $and $and$libresoc.v:201331$14155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202387$14343_Y
+ connect \Y $and$libresoc.v:201331$14155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:202388$14344
+ cell $and $and$libresoc.v:201332$14156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast2_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202388$14344_Y
+ connect \Y $and$libresoc.v:201332$14156_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:202389$14345
+ cell $and $and$libresoc.v:201333$14157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nia_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202389$14345_Y
+ connect \Y $and$libresoc.v:201333$14157_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:202390$14346
+ cell $and $and$libresoc.v:201334$14158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msr_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:202390$14346_Y
+ connect \Y $and$libresoc.v:201334$14158_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:202396$14352
+ cell $and $and$libresoc.v:201340$14164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:202396$14352_Y
+ connect \Y $and$libresoc.v:201340$14164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:202397$14353
+ cell $and $and$libresoc.v:201341$14165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:202397$14353_Y
+ connect \Y $and$libresoc.v:201341$14165_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:202398$14354
+ cell $and $and$libresoc.v:201342$14166
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:202398$14354_Y
+ connect \Y $and$libresoc.v:201342$14166_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:202399$14355
+ cell $and $and$libresoc.v:201343$14167
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$93
connect \B 4'1111
- connect \Y $and$libresoc.v:202399$14355_Y
+ connect \Y $and$libresoc.v:201343$14167_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:202372$14328
+ cell $eq $eq$libresoc.v:201316$14140
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B 1'0
- connect \Y $eq$libresoc.v:202372$14328_Y
+ connect \Y $eq$libresoc.v:201316$14140_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:202374$14330
+ cell $eq $eq$libresoc.v:201318$14142
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:202374$14330_Y
+ connect \Y $eq$libresoc.v:201318$14142_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:202355$14311
+ cell $not $not$libresoc.v:201299$14123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:202355$14311_Y
+ connect \Y $not$libresoc.v:201299$14123_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:202357$14313
+ cell $not $not$libresoc.v:201301$14125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:202357$14313_Y
+ connect \Y $not$libresoc.v:201301$14125_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:202360$14316
+ cell $not $not$libresoc.v:201304$14128
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:202360$14316_Y
+ connect \Y $not$libresoc.v:201304$14128_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:202363$14319
+ cell $not $not$libresoc.v:201307$14131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:202363$14319_Y
+ connect \Y $not$libresoc.v:201307$14131_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:202369$14325
+ cell $not $not$libresoc.v:201313$14137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_ready_i
- connect \Y $not$libresoc.v:202369$14325_Y
+ connect \Y $not$libresoc.v:201313$14137_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:202384$14340
+ cell $not $not$libresoc.v:201328$14152
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:202384$14340_Y
+ connect \Y $not$libresoc.v:201328$14152_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:202400$14356
+ cell $not $not$libresoc.v:201344$14168
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:202400$14356_Y
+ connect \Y $not$libresoc.v:201344$14168_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:202367$14323
+ cell $or $or$libresoc.v:201311$14135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:202367$14323_Y
+ connect \Y $or$libresoc.v:201311$14135_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:202378$14334
+ cell $or $or$libresoc.v:201322$14146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:202378$14334_Y
+ connect \Y $or$libresoc.v:201322$14146_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:202379$14335
+ cell $or $or$libresoc.v:201323$14147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:202379$14335_Y
+ connect \Y $or$libresoc.v:201323$14147_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:202380$14336
+ cell $or $or$libresoc.v:201324$14148
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:202380$14336_Y
+ connect \Y $or$libresoc.v:201324$14148_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:202381$14337
+ cell $or $or$libresoc.v:201325$14149
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:202381$14337_Y
+ connect \Y $or$libresoc.v:201325$14149_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:202385$14341
+ cell $or $or$libresoc.v:201329$14153
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:202385$14341_Y
+ connect \Y $or$libresoc.v:201329$14153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:202395$14351
+ cell $or $or$libresoc.v:201339$14163
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$6
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:202395$14351_Y
+ connect \Y $or$libresoc.v:201339$14163_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:202340$14296
+ cell $reduce_and $reduce_and$libresoc.v:201284$14108
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $reduce_and$libresoc.v:202340$14296_Y
+ connect \Y $reduce_and$libresoc.v:201284$14108_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:202362$14318
+ cell $reduce_or $reduce_or$libresoc.v:201306$14130
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $reduce_or$libresoc.v:202362$14318_Y
+ connect \Y $reduce_or$libresoc.v:201306$14130_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:202365$14321
+ cell $reduce_or $reduce_or$libresoc.v:201309$14133
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:202365$14321_Y
+ connect \Y $reduce_or$libresoc.v:201309$14133_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:202366$14322
+ cell $reduce_or $reduce_or$libresoc.v:201310$14134
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:202366$14322_Y
+ connect \Y $reduce_or$libresoc.v:201310$14134_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:202391$14347
+ cell $mux $ternary$libresoc.v:201335$14159
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:202391$14347_Y
+ connect \Y $ternary$libresoc.v:201335$14159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:202392$14348
+ cell $mux $ternary$libresoc.v:201336$14160
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:202392$14348_Y
+ connect \Y $ternary$libresoc.v:201336$14160_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:202393$14349
+ cell $mux $ternary$libresoc.v:201337$14161
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:202393$14349_Y
+ connect \Y $ternary$libresoc.v:201337$14161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:202394$14350
+ cell $mux $ternary$libresoc.v:201338$14162
parameter \WIDTH 64
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:202394$14350_Y
+ connect \Y $ternary$libresoc.v:201338$14162_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202477.14-202483.4"
+ attribute \src "libresoc.v:201421.14-201427.4"
cell \alu_l$45 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202484.13-202514.4"
+ attribute \src "libresoc.v:201428.13-201458.4"
cell \alu_trap0 \alu_trap0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \trap_op__traptype \alu_trap0_trap_op__traptype
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202515.15-202521.4"
+ attribute \src "libresoc.v:201459.15-201465.4"
cell \alui_l$44 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202522.14-202528.4"
+ attribute \src "libresoc.v:201466.14-201472.4"
cell \opc_l$40 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202529.14-202535.4"
+ attribute \src "libresoc.v:201473.14-201479.4"
cell \req_l$41 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202536.14-202542.4"
+ attribute \src "libresoc.v:201480.14-201486.4"
cell \rok_l$43 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202543.14-202548.4"
+ attribute \src "libresoc.v:201487.14-201492.4"
cell \rst_l$42 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202549.14-202555.4"
+ attribute \src "libresoc.v:201493.14-201499.4"
cell \src_l$39 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:201740.7-201740.20"
- process $proc$libresoc.v:201740$14511
+ attribute \src "libresoc.v:200684.7-200684.20"
+ process $proc$libresoc.v:200684$14323
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:201866.7-201866.24"
- process $proc$libresoc.v:201866$14512
+ attribute \src "libresoc.v:200810.7-200810.24"
+ process $proc$libresoc.v:200810$14324
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:201876.7-201876.26"
- process $proc$libresoc.v:201876$14513
+ attribute \src "libresoc.v:200820.7-200820.26"
+ process $proc$libresoc.v:200820$14325
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:201884.7-201884.25"
- process $proc$libresoc.v:201884$14514
+ attribute \src "libresoc.v:200828.7-200828.25"
+ process $proc$libresoc.v:200828$14326
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:201920.14-201920.59"
- process $proc$libresoc.v:201920$14515
+ attribute \src "libresoc.v:200864.14-200864.59"
+ process $proc$libresoc.v:200864$14327
assign { } { }
assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:201939.14-201939.51"
- process $proc$libresoc.v:201939$14516
+ attribute \src "libresoc.v:200883.14-200883.51"
+ process $proc$libresoc.v:200883$14328
assign { } { }
assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:201943.14-201943.45"
- process $proc$libresoc.v:201943$14517
+ attribute \src "libresoc.v:200887.14-200887.45"
+ process $proc$libresoc.v:200887$14329
assign { } { }
assign $1\alu_trap0_trap_op__insn[31:0] 0
sync always
sync init
update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:202022.13-202022.49"
- process $proc$libresoc.v:202022$14518
+ attribute \src "libresoc.v:200966.13-200966.49"
+ process $proc$libresoc.v:200966$14330
assign { } { }
assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:202026.7-202026.41"
- process $proc$libresoc.v:202026$14519
+ attribute \src "libresoc.v:200970.7-200970.41"
+ process $proc$libresoc.v:200970$14331
assign { } { }
assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:202030.13-202030.48"
- process $proc$libresoc.v:202030$14520
+ attribute \src "libresoc.v:200974.13-200974.48"
+ process $proc$libresoc.v:200974$14332
assign { } { }
assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:202034.14-202034.59"
- process $proc$libresoc.v:202034$14521
+ attribute \src "libresoc.v:200978.14-200978.59"
+ process $proc$libresoc.v:200978$14333
assign { } { }
assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:202038.14-202038.52"
- process $proc$libresoc.v:202038$14522
+ attribute \src "libresoc.v:200982.14-200982.52"
+ process $proc$libresoc.v:200982$14334
assign { } { }
assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000
sync always
sync init
update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:202042.13-202042.48"
- process $proc$libresoc.v:202042$14523
+ attribute \src "libresoc.v:200986.13-200986.48"
+ process $proc$libresoc.v:200986$14335
assign { } { }
assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:202048.7-202048.27"
- process $proc$libresoc.v:202048$14524
+ attribute \src "libresoc.v:200992.7-200992.27"
+ process $proc$libresoc.v:200992$14336
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:202080.14-202080.47"
- process $proc$libresoc.v:202080$14525
+ attribute \src "libresoc.v:201024.14-201024.47"
+ process $proc$libresoc.v:201024$14337
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:202084.7-202084.27"
- process $proc$libresoc.v:202084$14526
+ attribute \src "libresoc.v:201028.7-201028.27"
+ process $proc$libresoc.v:201028$14338
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:202088.14-202088.51"
- process $proc$libresoc.v:202088$14527
+ attribute \src "libresoc.v:201032.14-201032.51"
+ process $proc$libresoc.v:201032$14339
assign { } { }
assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__fast1 $1\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:202092.7-202092.31"
- process $proc$libresoc.v:202092$14528
+ attribute \src "libresoc.v:201036.7-201036.31"
+ process $proc$libresoc.v:201036$14340
assign { } { }
assign $1\data_r1__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:202096.14-202096.51"
- process $proc$libresoc.v:202096$14529
+ attribute \src "libresoc.v:201040.14-201040.51"
+ process $proc$libresoc.v:201040$14341
assign { } { }
assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast2 $1\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:202100.7-202100.31"
- process $proc$libresoc.v:202100$14530
+ attribute \src "libresoc.v:201044.7-201044.31"
+ process $proc$libresoc.v:201044$14342
assign { } { }
assign $1\data_r2__fast2_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:202104.14-202104.49"
- process $proc$libresoc.v:202104$14531
+ attribute \src "libresoc.v:201048.14-201048.49"
+ process $proc$libresoc.v:201048$14343
assign { } { }
assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r3__nia $1\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:202108.7-202108.29"
- process $proc$libresoc.v:202108$14532
+ attribute \src "libresoc.v:201052.7-201052.29"
+ process $proc$libresoc.v:201052$14344
assign { } { }
assign $1\data_r3__nia_ok[0:0] 1'0
sync always
sync init
update \data_r3__nia_ok $1\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:202112.14-202112.49"
- process $proc$libresoc.v:202112$14533
+ attribute \src "libresoc.v:201056.14-201056.49"
+ process $proc$libresoc.v:201056$14345
assign { } { }
assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r4__msr $1\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:202116.7-202116.29"
- process $proc$libresoc.v:202116$14534
+ attribute \src "libresoc.v:201060.7-201060.29"
+ process $proc$libresoc.v:201060$14346
assign { } { }
assign $1\data_r4__msr_ok[0:0] 1'0
sync always
sync init
update \data_r4__msr_ok $1\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:202147.7-202147.25"
- process $proc$libresoc.v:202147$14535
+ attribute \src "libresoc.v:201091.7-201091.25"
+ process $proc$libresoc.v:201091$14347
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:202151.7-202151.25"
- process $proc$libresoc.v:202151$14536
+ attribute \src "libresoc.v:201095.7-201095.25"
+ process $proc$libresoc.v:201095$14348
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:202263.13-202263.31"
- process $proc$libresoc.v:202263$14537
+ attribute \src "libresoc.v:201207.13-201207.31"
+ process $proc$libresoc.v:201207$14349
assign { } { }
assign $1\prev_wr_go[4:0] 5'00000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:202271.13-202271.32"
- process $proc$libresoc.v:202271$14538
+ attribute \src "libresoc.v:201215.13-201215.32"
+ process $proc$libresoc.v:201215$14350
assign { } { }
assign $1\req_l_r_req[4:0] 5'11111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:202275.13-202275.32"
- process $proc$libresoc.v:202275$14539
+ attribute \src "libresoc.v:201219.13-201219.32"
+ process $proc$libresoc.v:201219$14351
assign { } { }
assign $1\req_l_s_req[4:0] 5'00000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:202287.7-202287.26"
- process $proc$libresoc.v:202287$14540
+ attribute \src "libresoc.v:201231.7-201231.26"
+ process $proc$libresoc.v:201231$14352
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:202291.7-202291.26"
- process $proc$libresoc.v:202291$14541
+ attribute \src "libresoc.v:201235.7-201235.26"
+ process $proc$libresoc.v:201235$14353
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:202295.7-202295.25"
- process $proc$libresoc.v:202295$14542
+ attribute \src "libresoc.v:201239.7-201239.25"
+ process $proc$libresoc.v:201239$14354
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:202299.7-202299.25"
- process $proc$libresoc.v:202299$14543
+ attribute \src "libresoc.v:201243.7-201243.25"
+ process $proc$libresoc.v:201243$14355
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:202315.13-202315.31"
- process $proc$libresoc.v:202315$14544
+ attribute \src "libresoc.v:201259.13-201259.31"
+ process $proc$libresoc.v:201259$14356
assign { } { }
assign $1\src_l_r_src[3:0] 4'1111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:202319.13-202319.31"
- process $proc$libresoc.v:202319$14545
+ attribute \src "libresoc.v:201263.13-201263.31"
+ process $proc$libresoc.v:201263$14357
assign { } { }
assign $1\src_l_s_src[3:0] 4'0000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:202323.14-202323.43"
- process $proc$libresoc.v:202323$14546
+ attribute \src "libresoc.v:201267.14-201267.43"
+ process $proc$libresoc.v:201267$14358
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:202327.14-202327.43"
- process $proc$libresoc.v:202327$14547
+ attribute \src "libresoc.v:201271.14-201271.43"
+ process $proc$libresoc.v:201271$14359
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:202331.14-202331.43"
- process $proc$libresoc.v:202331$14548
+ attribute \src "libresoc.v:201275.14-201275.43"
+ process $proc$libresoc.v:201275$14360
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:202335.14-202335.43"
- process $proc$libresoc.v:202335$14549
+ attribute \src "libresoc.v:201279.14-201279.43"
+ process $proc$libresoc.v:201279$14361
assign { } { }
assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r3 $1\src_r3[63:0]
end
- attribute \src "libresoc.v:202401.3-202402.39"
- process $proc$libresoc.v:202401$14357
+ attribute \src "libresoc.v:201345.3-201346.39"
+ process $proc$libresoc.v:201345$14169
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:202403.3-202404.43"
- process $proc$libresoc.v:202403$14358
+ attribute \src "libresoc.v:201347.3-201348.43"
+ process $proc$libresoc.v:201347$14170
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:202405.3-202406.29"
- process $proc$libresoc.v:202405$14359
+ attribute \src "libresoc.v:201349.3-201350.29"
+ process $proc$libresoc.v:201349$14171
assign { } { }
assign $0\src_r3[63:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[63:0]
end
- attribute \src "libresoc.v:202407.3-202408.29"
- process $proc$libresoc.v:202407$14360
+ attribute \src "libresoc.v:201351.3-201352.29"
+ process $proc$libresoc.v:201351$14172
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:202409.3-202410.29"
- process $proc$libresoc.v:202409$14361
+ attribute \src "libresoc.v:201353.3-201354.29"
+ process $proc$libresoc.v:201353$14173
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:202411.3-202412.29"
- process $proc$libresoc.v:202411$14362
+ attribute \src "libresoc.v:201355.3-201356.29"
+ process $proc$libresoc.v:201355$14174
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:202413.3-202414.41"
- process $proc$libresoc.v:202413$14363
+ attribute \src "libresoc.v:201357.3-201358.41"
+ process $proc$libresoc.v:201357$14175
assign { } { }
assign $0\data_r4__msr[63:0] \data_r4__msr$next
sync posedge \coresync_clk
update \data_r4__msr $0\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:202415.3-202416.47"
- process $proc$libresoc.v:202415$14364
+ attribute \src "libresoc.v:201359.3-201360.47"
+ process $proc$libresoc.v:201359$14176
assign { } { }
assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next
sync posedge \coresync_clk
update \data_r4__msr_ok $0\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:202417.3-202418.41"
- process $proc$libresoc.v:202417$14365
+ attribute \src "libresoc.v:201361.3-201362.41"
+ process $proc$libresoc.v:201361$14177
assign { } { }
assign $0\data_r3__nia[63:0] \data_r3__nia$next
sync posedge \coresync_clk
update \data_r3__nia $0\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:202419.3-202420.47"
- process $proc$libresoc.v:202419$14366
+ attribute \src "libresoc.v:201363.3-201364.47"
+ process $proc$libresoc.v:201363$14178
assign { } { }
assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next
sync posedge \coresync_clk
update \data_r3__nia_ok $0\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:202421.3-202422.45"
- process $proc$libresoc.v:202421$14367
+ attribute \src "libresoc.v:201365.3-201366.45"
+ process $proc$libresoc.v:201365$14179
assign { } { }
assign $0\data_r2__fast2[63:0] \data_r2__fast2$next
sync posedge \coresync_clk
update \data_r2__fast2 $0\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:202423.3-202424.51"
- process $proc$libresoc.v:202423$14368
+ attribute \src "libresoc.v:201367.3-201368.51"
+ process $proc$libresoc.v:201367$14180
assign { } { }
assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next
sync posedge \coresync_clk
update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:202425.3-202426.45"
- process $proc$libresoc.v:202425$14369
+ attribute \src "libresoc.v:201369.3-201370.45"
+ process $proc$libresoc.v:201369$14181
assign { } { }
assign $0\data_r1__fast1[63:0] \data_r1__fast1$next
sync posedge \coresync_clk
update \data_r1__fast1 $0\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:202427.3-202428.51"
- process $proc$libresoc.v:202427$14370
+ attribute \src "libresoc.v:201371.3-201372.51"
+ process $proc$libresoc.v:201371$14182
assign { } { }
assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next
sync posedge \coresync_clk
update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:202429.3-202430.37"
- process $proc$libresoc.v:202429$14371
+ attribute \src "libresoc.v:201373.3-201374.37"
+ process $proc$libresoc.v:201373$14183
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:202431.3-202432.43"
- process $proc$libresoc.v:202431$14372
+ attribute \src "libresoc.v:201375.3-201376.43"
+ process $proc$libresoc.v:201375$14184
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:202433.3-202434.73"
- process $proc$libresoc.v:202433$14373
+ attribute \src "libresoc.v:201377.3-201378.73"
+ process $proc$libresoc.v:201377$14185
assign { } { }
assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:202435.3-202436.69"
- process $proc$libresoc.v:202435$14374
+ attribute \src "libresoc.v:201379.3-201380.69"
+ process $proc$libresoc.v:201379$14186
assign { } { }
assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:202437.3-202438.63"
- process $proc$libresoc.v:202437$14375
+ attribute \src "libresoc.v:201381.3-201382.63"
+ process $proc$libresoc.v:201381$14187
assign { } { }
assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:202439.3-202440.61"
- process $proc$libresoc.v:202439$14376
+ attribute \src "libresoc.v:201383.3-201384.61"
+ process $proc$libresoc.v:201383$14188
assign { } { }
assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:202441.3-202442.61"
- process $proc$libresoc.v:202441$14377
+ attribute \src "libresoc.v:201385.3-201386.61"
+ process $proc$libresoc.v:201385$14189
assign { } { }
assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:202443.3-202444.71"
- process $proc$libresoc.v:202443$14378
+ attribute \src "libresoc.v:201387.3-201388.71"
+ process $proc$libresoc.v:201387$14190
assign { } { }
assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:202445.3-202446.71"
- process $proc$libresoc.v:202445$14379
+ attribute \src "libresoc.v:201389.3-201390.71"
+ process $proc$libresoc.v:201389$14191
assign { } { }
assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:202447.3-202448.71"
- process $proc$libresoc.v:202447$14380
+ attribute \src "libresoc.v:201391.3-201392.71"
+ process $proc$libresoc.v:201391$14192
assign { } { }
assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:202449.3-202450.71"
- process $proc$libresoc.v:202449$14381
+ attribute \src "libresoc.v:201393.3-201394.71"
+ process $proc$libresoc.v:201393$14193
assign { } { }
assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:202451.3-202452.39"
- process $proc$libresoc.v:202451$14382
+ attribute \src "libresoc.v:201395.3-201396.39"
+ process $proc$libresoc.v:201395$14194
assign { } { }
assign $0\req_l_r_req[4:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:202453.3-202454.39"
- process $proc$libresoc.v:202453$14383
+ attribute \src "libresoc.v:201397.3-201398.39"
+ process $proc$libresoc.v:201397$14195
assign { } { }
assign $0\req_l_s_req[4:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:202455.3-202456.39"
- process $proc$libresoc.v:202455$14384
+ attribute \src "libresoc.v:201399.3-201400.39"
+ process $proc$libresoc.v:201399$14196
assign { } { }
assign $0\src_l_r_src[3:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:202457.3-202458.39"
- process $proc$libresoc.v:202457$14385
+ attribute \src "libresoc.v:201401.3-201402.39"
+ process $proc$libresoc.v:201401$14197
assign { } { }
assign $0\src_l_s_src[3:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:202459.3-202460.39"
- process $proc$libresoc.v:202459$14386
+ attribute \src "libresoc.v:201403.3-201404.39"
+ process $proc$libresoc.v:201403$14198
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:202461.3-202462.39"
- process $proc$libresoc.v:202461$14387
+ attribute \src "libresoc.v:201405.3-201406.39"
+ process $proc$libresoc.v:201405$14199
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:202463.3-202464.39"
- process $proc$libresoc.v:202463$14388
+ attribute \src "libresoc.v:201407.3-201408.39"
+ process $proc$libresoc.v:201407$14200
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:202465.3-202466.39"
- process $proc$libresoc.v:202465$14389
+ attribute \src "libresoc.v:201409.3-201410.39"
+ process $proc$libresoc.v:201409$14201
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:202467.3-202468.41"
- process $proc$libresoc.v:202467$14390
+ attribute \src "libresoc.v:201411.3-201412.41"
+ process $proc$libresoc.v:201411$14202
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:202469.3-202470.41"
- process $proc$libresoc.v:202469$14391
+ attribute \src "libresoc.v:201413.3-201414.41"
+ process $proc$libresoc.v:201413$14203
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:202471.3-202472.37"
- process $proc$libresoc.v:202471$14392
+ attribute \src "libresoc.v:201415.3-201416.37"
+ process $proc$libresoc.v:201415$14204
assign { } { }
assign $0\prev_wr_go[4:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:202473.3-202474.41"
- process $proc$libresoc.v:202473$14393
+ attribute \src "libresoc.v:201417.3-201418.41"
+ process $proc$libresoc.v:201417$14205
assign { } { }
assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:202475.3-202476.25"
- process $proc$libresoc.v:202475$14394
+ attribute \src "libresoc.v:201419.3-201420.25"
+ process $proc$libresoc.v:201419$14206
assign { } { }
assign $0\all_rd_dly[0:0] \$11
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:202556.3-202565.6"
- process $proc$libresoc.v:202556$14395
+ attribute \src "libresoc.v:201500.3-201509.6"
+ process $proc$libresoc.v:201500$14207
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:202557.5-202557.29"
+ attribute \src "libresoc.v:201501.5-201501.29"
switch \initial
- attribute \src "libresoc.v:202557.9-202557.17"
+ attribute \src "libresoc.v:201501.9-201501.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:202566.3-202574.6"
- process $proc$libresoc.v:202566$14396
+ attribute \src "libresoc.v:201510.3-201518.6"
+ process $proc$libresoc.v:201510$14208
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$14397 $1\rok_l_s_rdok$next[0:0]$14398
- attribute \src "libresoc.v:202567.5-202567.29"
+ assign $0\rok_l_s_rdok$next[0:0]$14209 $1\rok_l_s_rdok$next[0:0]$14210
+ attribute \src "libresoc.v:201511.5-201511.29"
switch \initial
- attribute \src "libresoc.v:202567.9-202567.17"
+ attribute \src "libresoc.v:201511.9-201511.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$14398 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$14210 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$14398 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$14210 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14397
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14209
end
- attribute \src "libresoc.v:202575.3-202583.6"
- process $proc$libresoc.v:202575$14399
+ attribute \src "libresoc.v:201519.3-201527.6"
+ process $proc$libresoc.v:201519$14211
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$14400 $1\rok_l_r_rdok$next[0:0]$14401
- attribute \src "libresoc.v:202576.5-202576.29"
+ assign $0\rok_l_r_rdok$next[0:0]$14212 $1\rok_l_r_rdok$next[0:0]$14213
+ attribute \src "libresoc.v:201520.5-201520.29"
switch \initial
- attribute \src "libresoc.v:202576.9-202576.17"
+ attribute \src "libresoc.v:201520.9-201520.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$14401 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$14213 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$14401 \$65
+ assign $1\rok_l_r_rdok$next[0:0]$14213 \$65
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14400
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14212
end
- attribute \src "libresoc.v:202584.3-202592.6"
- process $proc$libresoc.v:202584$14402
+ attribute \src "libresoc.v:201528.3-201536.6"
+ process $proc$libresoc.v:201528$14214
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$14403 $1\rst_l_s_rst$next[0:0]$14404
- attribute \src "libresoc.v:202585.5-202585.29"
+ assign $0\rst_l_s_rst$next[0:0]$14215 $1\rst_l_s_rst$next[0:0]$14216
+ attribute \src "libresoc.v:201529.5-201529.29"
switch \initial
- attribute \src "libresoc.v:202585.9-202585.17"
+ attribute \src "libresoc.v:201529.9-201529.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$14404 1'0
+ assign $1\rst_l_s_rst$next[0:0]$14216 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$14404 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$14216 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14403
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14215
end
- attribute \src "libresoc.v:202593.3-202601.6"
- process $proc$libresoc.v:202593$14405
+ attribute \src "libresoc.v:201537.3-201545.6"
+ process $proc$libresoc.v:201537$14217
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$14406 $1\rst_l_r_rst$next[0:0]$14407
- attribute \src "libresoc.v:202594.5-202594.29"
+ assign $0\rst_l_r_rst$next[0:0]$14218 $1\rst_l_r_rst$next[0:0]$14219
+ attribute \src "libresoc.v:201538.5-201538.29"
switch \initial
- attribute \src "libresoc.v:202594.9-202594.17"
+ attribute \src "libresoc.v:201538.9-201538.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$14407 1'1
+ assign $1\rst_l_r_rst$next[0:0]$14219 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$14407 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$14219 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14406
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14218
end
- attribute \src "libresoc.v:202602.3-202610.6"
- process $proc$libresoc.v:202602$14408
+ attribute \src "libresoc.v:201546.3-201554.6"
+ process $proc$libresoc.v:201546$14220
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$14409 $1\opc_l_s_opc$next[0:0]$14410
- attribute \src "libresoc.v:202603.5-202603.29"
+ assign $0\opc_l_s_opc$next[0:0]$14221 $1\opc_l_s_opc$next[0:0]$14222
+ attribute \src "libresoc.v:201547.5-201547.29"
switch \initial
- attribute \src "libresoc.v:202603.9-202603.17"
+ attribute \src "libresoc.v:201547.9-201547.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$14410 1'0
+ assign $1\opc_l_s_opc$next[0:0]$14222 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$14410 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$14222 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14409
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14221
end
- attribute \src "libresoc.v:202611.3-202619.6"
- process $proc$libresoc.v:202611$14411
+ attribute \src "libresoc.v:201555.3-201563.6"
+ process $proc$libresoc.v:201555$14223
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$14412 $1\opc_l_r_opc$next[0:0]$14413
- attribute \src "libresoc.v:202612.5-202612.29"
+ assign $0\opc_l_r_opc$next[0:0]$14224 $1\opc_l_r_opc$next[0:0]$14225
+ attribute \src "libresoc.v:201556.5-201556.29"
switch \initial
- attribute \src "libresoc.v:202612.9-202612.17"
+ attribute \src "libresoc.v:201556.9-201556.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$14413 1'1
+ assign $1\opc_l_r_opc$next[0:0]$14225 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$14413 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$14225 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14412
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14224
end
- attribute \src "libresoc.v:202620.3-202628.6"
- process $proc$libresoc.v:202620$14414
+ attribute \src "libresoc.v:201564.3-201572.6"
+ process $proc$libresoc.v:201564$14226
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[3:0]$14415 $1\src_l_s_src$next[3:0]$14416
- attribute \src "libresoc.v:202621.5-202621.29"
+ assign $0\src_l_s_src$next[3:0]$14227 $1\src_l_s_src$next[3:0]$14228
+ attribute \src "libresoc.v:201565.5-201565.29"
switch \initial
- attribute \src "libresoc.v:202621.9-202621.17"
+ attribute \src "libresoc.v:201565.9-201565.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[3:0]$14416 4'0000
+ assign $1\src_l_s_src$next[3:0]$14228 4'0000
case
- assign $1\src_l_s_src$next[3:0]$14416 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[3:0]$14228 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14415
+ update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14227
end
- attribute \src "libresoc.v:202629.3-202637.6"
- process $proc$libresoc.v:202629$14417
+ attribute \src "libresoc.v:201573.3-201581.6"
+ process $proc$libresoc.v:201573$14229
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[3:0]$14418 $1\src_l_r_src$next[3:0]$14419
- attribute \src "libresoc.v:202630.5-202630.29"
+ assign $0\src_l_r_src$next[3:0]$14230 $1\src_l_r_src$next[3:0]$14231
+ attribute \src "libresoc.v:201574.5-201574.29"
switch \initial
- attribute \src "libresoc.v:202630.9-202630.17"
+ attribute \src "libresoc.v:201574.9-201574.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[3:0]$14419 4'1111
+ assign $1\src_l_r_src$next[3:0]$14231 4'1111
case
- assign $1\src_l_r_src$next[3:0]$14419 \reset_r
+ assign $1\src_l_r_src$next[3:0]$14231 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14418
+ update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14230
end
- attribute \src "libresoc.v:202638.3-202646.6"
- process $proc$libresoc.v:202638$14420
+ attribute \src "libresoc.v:201582.3-201590.6"
+ process $proc$libresoc.v:201582$14232
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[4:0]$14421 $1\req_l_s_req$next[4:0]$14422
- attribute \src "libresoc.v:202639.5-202639.29"
+ assign $0\req_l_s_req$next[4:0]$14233 $1\req_l_s_req$next[4:0]$14234
+ attribute \src "libresoc.v:201583.5-201583.29"
switch \initial
- attribute \src "libresoc.v:202639.9-202639.17"
+ attribute \src "libresoc.v:201583.9-201583.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[4:0]$14422 5'00000
+ assign $1\req_l_s_req$next[4:0]$14234 5'00000
case
- assign $1\req_l_s_req$next[4:0]$14422 \$67
+ assign $1\req_l_s_req$next[4:0]$14234 \$67
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14421
+ update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14233
end
- attribute \src "libresoc.v:202647.3-202655.6"
- process $proc$libresoc.v:202647$14423
+ attribute \src "libresoc.v:201591.3-201599.6"
+ process $proc$libresoc.v:201591$14235
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[4:0]$14424 $1\req_l_r_req$next[4:0]$14425
- attribute \src "libresoc.v:202648.5-202648.29"
+ assign $0\req_l_r_req$next[4:0]$14236 $1\req_l_r_req$next[4:0]$14237
+ attribute \src "libresoc.v:201592.5-201592.29"
switch \initial
- attribute \src "libresoc.v:202648.9-202648.17"
+ attribute \src "libresoc.v:201592.9-201592.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[4:0]$14425 5'11111
+ assign $1\req_l_r_req$next[4:0]$14237 5'11111
case
- assign $1\req_l_r_req$next[4:0]$14425 \$69
+ assign $1\req_l_r_req$next[4:0]$14237 \$69
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14424
+ update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14236
end
- attribute \src "libresoc.v:202656.3-202673.6"
- process $proc$libresoc.v:202656$14426
+ attribute \src "libresoc.v:201600.3-201617.6"
+ process $proc$libresoc.v:201600$14238
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_trap0_trap_op__cia$next[63:0]$14427 $1\alu_trap0_trap_op__cia$next[63:0]$14436
- assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437
- assign $0\alu_trap0_trap_op__insn$next[31:0]$14429 $1\alu_trap0_trap_op__insn$next[31:0]$14438
- assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14430 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439
- assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440
- assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441
- assign $0\alu_trap0_trap_op__msr$next[63:0]$14433 $1\alu_trap0_trap_op__msr$next[63:0]$14442
- assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443
- assign $0\alu_trap0_trap_op__traptype$next[7:0]$14435 $1\alu_trap0_trap_op__traptype$next[7:0]$14444
- attribute \src "libresoc.v:202657.5-202657.29"
+ assign $0\alu_trap0_trap_op__cia$next[63:0]$14239 $1\alu_trap0_trap_op__cia$next[63:0]$14248
+ assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249
+ assign $0\alu_trap0_trap_op__insn$next[31:0]$14241 $1\alu_trap0_trap_op__insn$next[31:0]$14250
+ assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14242 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251
+ assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252
+ assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253
+ assign $0\alu_trap0_trap_op__msr$next[63:0]$14245 $1\alu_trap0_trap_op__msr$next[63:0]$14254
+ assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255
+ assign $0\alu_trap0_trap_op__traptype$next[7:0]$14247 $1\alu_trap0_trap_op__traptype$next[7:0]$14256
+ attribute \src "libresoc.v:201601.5-201601.29"
switch \initial
- attribute \src "libresoc.v:202657.9-202657.17"
+ attribute \src "libresoc.v:201601.9-201601.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 $1\alu_trap0_trap_op__traptype$next[7:0]$14444 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 $1\alu_trap0_trap_op__cia$next[63:0]$14436 $1\alu_trap0_trap_op__msr$next[63:0]$14442 $1\alu_trap0_trap_op__insn$next[31:0]$14438 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
+ assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255 $1\alu_trap0_trap_op__traptype$next[7:0]$14256 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252 $1\alu_trap0_trap_op__cia$next[63:0]$14248 $1\alu_trap0_trap_op__msr$next[63:0]$14254 $1\alu_trap0_trap_op__insn$next[31:0]$14250 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
case
- assign $1\alu_trap0_trap_op__cia$next[63:0]$14436 \alu_trap0_trap_op__cia
- assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 \alu_trap0_trap_op__fn_unit
- assign $1\alu_trap0_trap_op__insn$next[31:0]$14438 \alu_trap0_trap_op__insn
- assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 \alu_trap0_trap_op__insn_type
- assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 \alu_trap0_trap_op__is_32bit
- assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 \alu_trap0_trap_op__ldst_exc
- assign $1\alu_trap0_trap_op__msr$next[63:0]$14442 \alu_trap0_trap_op__msr
- assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 \alu_trap0_trap_op__trapaddr
- assign $1\alu_trap0_trap_op__traptype$next[7:0]$14444 \alu_trap0_trap_op__traptype
+ assign $1\alu_trap0_trap_op__cia$next[63:0]$14248 \alu_trap0_trap_op__cia
+ assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249 \alu_trap0_trap_op__fn_unit
+ assign $1\alu_trap0_trap_op__insn$next[31:0]$14250 \alu_trap0_trap_op__insn
+ assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14251 \alu_trap0_trap_op__insn_type
+ assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252 \alu_trap0_trap_op__is_32bit
+ assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253 \alu_trap0_trap_op__ldst_exc
+ assign $1\alu_trap0_trap_op__msr$next[63:0]$14254 \alu_trap0_trap_op__msr
+ assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255 \alu_trap0_trap_op__trapaddr
+ assign $1\alu_trap0_trap_op__traptype$next[7:0]$14256 \alu_trap0_trap_op__traptype
end
sync always
- update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14427
- update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428
- update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14429
- update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14430
- update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431
- update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432
- update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14433
- update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434
- update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14435
+ update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14239
+ update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240
+ update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14241
+ update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14242
+ update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243
+ update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244
+ update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14245
+ update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246
+ update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14247
end
- attribute \src "libresoc.v:202674.3-202695.6"
- process $proc$libresoc.v:202674$14445
+ attribute \src "libresoc.v:201618.3-201639.6"
+ process $proc$libresoc.v:201618$14257
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$14446 $2\data_r0__o$next[63:0]$14450
+ assign $0\data_r0__o$next[63:0]$14258 $2\data_r0__o$next[63:0]$14262
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$14447 $3\data_r0__o_ok$next[0:0]$14452
- attribute \src "libresoc.v:202675.5-202675.29"
+ assign $0\data_r0__o_ok$next[0:0]$14259 $3\data_r0__o_ok$next[0:0]$14264
+ attribute \src "libresoc.v:201619.5-201619.29"
switch \initial
- attribute \src "libresoc.v:202675.9-202675.17"
+ attribute \src "libresoc.v:201619.9-201619.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$14449 $1\data_r0__o$next[63:0]$14448 } { \o_ok \alu_trap0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$14261 $1\data_r0__o$next[63:0]$14260 } { \o_ok \alu_trap0_o }
case
- assign $1\data_r0__o$next[63:0]$14448 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$14449 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$14260 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$14261 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$14451 $2\data_r0__o$next[63:0]$14450 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$14263 $2\data_r0__o$next[63:0]$14262 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$14450 $1\data_r0__o$next[63:0]$14448
- assign $2\data_r0__o_ok$next[0:0]$14451 $1\data_r0__o_ok$next[0:0]$14449
+ assign $2\data_r0__o$next[63:0]$14262 $1\data_r0__o$next[63:0]$14260
+ assign $2\data_r0__o_ok$next[0:0]$14263 $1\data_r0__o_ok$next[0:0]$14261
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$14452 1'0
+ assign $3\data_r0__o_ok$next[0:0]$14264 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$14452 $2\data_r0__o_ok$next[0:0]$14451
+ assign $3\data_r0__o_ok$next[0:0]$14264 $2\data_r0__o_ok$next[0:0]$14263
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$14446
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14447
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$14258
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14259
end
- attribute \src "libresoc.v:202696.3-202717.6"
- process $proc$libresoc.v:202696$14453
+ attribute \src "libresoc.v:201640.3-201661.6"
+ process $proc$libresoc.v:201640$14265
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__fast1$next[63:0]$14454 $2\data_r1__fast1$next[63:0]$14458
+ assign $0\data_r1__fast1$next[63:0]$14266 $2\data_r1__fast1$next[63:0]$14270
assign { } { }
- assign $0\data_r1__fast1_ok$next[0:0]$14455 $3\data_r1__fast1_ok$next[0:0]$14460
- attribute \src "libresoc.v:202697.5-202697.29"
+ assign $0\data_r1__fast1_ok$next[0:0]$14267 $3\data_r1__fast1_ok$next[0:0]$14272
+ attribute \src "libresoc.v:201641.5-201641.29"
switch \initial
- attribute \src "libresoc.v:202697.9-202697.17"
+ attribute \src "libresoc.v:201641.9-201641.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__fast1_ok$next[0:0]$14457 $1\data_r1__fast1$next[63:0]$14456 } { \fast1_ok \alu_trap0_fast1 }
+ assign { $1\data_r1__fast1_ok$next[0:0]$14269 $1\data_r1__fast1$next[63:0]$14268 } { \fast1_ok \alu_trap0_fast1 }
case
- assign $1\data_r1__fast1$next[63:0]$14456 \data_r1__fast1
- assign $1\data_r1__fast1_ok$next[0:0]$14457 \data_r1__fast1_ok
+ assign $1\data_r1__fast1$next[63:0]$14268 \data_r1__fast1
+ assign $1\data_r1__fast1_ok$next[0:0]$14269 \data_r1__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__fast1_ok$next[0:0]$14459 $2\data_r1__fast1$next[63:0]$14458 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__fast1_ok$next[0:0]$14271 $2\data_r1__fast1$next[63:0]$14270 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__fast1$next[63:0]$14458 $1\data_r1__fast1$next[63:0]$14456
- assign $2\data_r1__fast1_ok$next[0:0]$14459 $1\data_r1__fast1_ok$next[0:0]$14457
+ assign $2\data_r1__fast1$next[63:0]$14270 $1\data_r1__fast1$next[63:0]$14268
+ assign $2\data_r1__fast1_ok$next[0:0]$14271 $1\data_r1__fast1_ok$next[0:0]$14269
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__fast1_ok$next[0:0]$14460 1'0
+ assign $3\data_r1__fast1_ok$next[0:0]$14272 1'0
case
- assign $3\data_r1__fast1_ok$next[0:0]$14460 $2\data_r1__fast1_ok$next[0:0]$14459
+ assign $3\data_r1__fast1_ok$next[0:0]$14272 $2\data_r1__fast1_ok$next[0:0]$14271
end
sync always
- update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14454
- update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14455
+ update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14266
+ update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14267
end
- attribute \src "libresoc.v:202718.3-202739.6"
- process $proc$libresoc.v:202718$14461
+ attribute \src "libresoc.v:201662.3-201683.6"
+ process $proc$libresoc.v:201662$14273
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast2$next[63:0]$14462 $2\data_r2__fast2$next[63:0]$14466
+ assign $0\data_r2__fast2$next[63:0]$14274 $2\data_r2__fast2$next[63:0]$14278
assign { } { }
- assign $0\data_r2__fast2_ok$next[0:0]$14463 $3\data_r2__fast2_ok$next[0:0]$14468
- attribute \src "libresoc.v:202719.5-202719.29"
+ assign $0\data_r2__fast2_ok$next[0:0]$14275 $3\data_r2__fast2_ok$next[0:0]$14280
+ attribute \src "libresoc.v:201663.5-201663.29"
switch \initial
- attribute \src "libresoc.v:202719.9-202719.17"
+ attribute \src "libresoc.v:201663.9-201663.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast2_ok$next[0:0]$14465 $1\data_r2__fast2$next[63:0]$14464 } { \fast2_ok \alu_trap0_fast2 }
+ assign { $1\data_r2__fast2_ok$next[0:0]$14277 $1\data_r2__fast2$next[63:0]$14276 } { \fast2_ok \alu_trap0_fast2 }
case
- assign $1\data_r2__fast2$next[63:0]$14464 \data_r2__fast2
- assign $1\data_r2__fast2_ok$next[0:0]$14465 \data_r2__fast2_ok
+ assign $1\data_r2__fast2$next[63:0]$14276 \data_r2__fast2
+ assign $1\data_r2__fast2_ok$next[0:0]$14277 \data_r2__fast2_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast2_ok$next[0:0]$14467 $2\data_r2__fast2$next[63:0]$14466 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast2_ok$next[0:0]$14279 $2\data_r2__fast2$next[63:0]$14278 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast2$next[63:0]$14466 $1\data_r2__fast2$next[63:0]$14464
- assign $2\data_r2__fast2_ok$next[0:0]$14467 $1\data_r2__fast2_ok$next[0:0]$14465
+ assign $2\data_r2__fast2$next[63:0]$14278 $1\data_r2__fast2$next[63:0]$14276
+ assign $2\data_r2__fast2_ok$next[0:0]$14279 $1\data_r2__fast2_ok$next[0:0]$14277
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast2_ok$next[0:0]$14468 1'0
+ assign $3\data_r2__fast2_ok$next[0:0]$14280 1'0
case
- assign $3\data_r2__fast2_ok$next[0:0]$14468 $2\data_r2__fast2_ok$next[0:0]$14467
+ assign $3\data_r2__fast2_ok$next[0:0]$14280 $2\data_r2__fast2_ok$next[0:0]$14279
end
sync always
- update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14462
- update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14463
+ update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14274
+ update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14275
end
- attribute \src "libresoc.v:202740.3-202761.6"
- process $proc$libresoc.v:202740$14469
+ attribute \src "libresoc.v:201684.3-201705.6"
+ process $proc$libresoc.v:201684$14281
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__nia$next[63:0]$14470 $2\data_r3__nia$next[63:0]$14474
+ assign $0\data_r3__nia$next[63:0]$14282 $2\data_r3__nia$next[63:0]$14286
assign { } { }
- assign $0\data_r3__nia_ok$next[0:0]$14471 $3\data_r3__nia_ok$next[0:0]$14476
- attribute \src "libresoc.v:202741.5-202741.29"
+ assign $0\data_r3__nia_ok$next[0:0]$14283 $3\data_r3__nia_ok$next[0:0]$14288
+ attribute \src "libresoc.v:201685.5-201685.29"
switch \initial
- attribute \src "libresoc.v:202741.9-202741.17"
+ attribute \src "libresoc.v:201685.9-201685.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__nia_ok$next[0:0]$14473 $1\data_r3__nia$next[63:0]$14472 } { \nia_ok \alu_trap0_nia }
+ assign { $1\data_r3__nia_ok$next[0:0]$14285 $1\data_r3__nia$next[63:0]$14284 } { \nia_ok \alu_trap0_nia }
case
- assign $1\data_r3__nia$next[63:0]$14472 \data_r3__nia
- assign $1\data_r3__nia_ok$next[0:0]$14473 \data_r3__nia_ok
+ assign $1\data_r3__nia$next[63:0]$14284 \data_r3__nia
+ assign $1\data_r3__nia_ok$next[0:0]$14285 \data_r3__nia_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__nia_ok$next[0:0]$14475 $2\data_r3__nia$next[63:0]$14474 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r3__nia_ok$next[0:0]$14287 $2\data_r3__nia$next[63:0]$14286 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r3__nia$next[63:0]$14474 $1\data_r3__nia$next[63:0]$14472
- assign $2\data_r3__nia_ok$next[0:0]$14475 $1\data_r3__nia_ok$next[0:0]$14473
+ assign $2\data_r3__nia$next[63:0]$14286 $1\data_r3__nia$next[63:0]$14284
+ assign $2\data_r3__nia_ok$next[0:0]$14287 $1\data_r3__nia_ok$next[0:0]$14285
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__nia_ok$next[0:0]$14476 1'0
+ assign $3\data_r3__nia_ok$next[0:0]$14288 1'0
case
- assign $3\data_r3__nia_ok$next[0:0]$14476 $2\data_r3__nia_ok$next[0:0]$14475
+ assign $3\data_r3__nia_ok$next[0:0]$14288 $2\data_r3__nia_ok$next[0:0]$14287
end
sync always
- update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14470
- update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14471
+ update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14282
+ update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14283
end
- attribute \src "libresoc.v:202762.3-202783.6"
- process $proc$libresoc.v:202762$14477
+ attribute \src "libresoc.v:201706.3-201727.6"
+ process $proc$libresoc.v:201706$14289
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__msr$next[63:0]$14478 $2\data_r4__msr$next[63:0]$14482
+ assign $0\data_r4__msr$next[63:0]$14290 $2\data_r4__msr$next[63:0]$14294
assign { } { }
- assign $0\data_r4__msr_ok$next[0:0]$14479 $3\data_r4__msr_ok$next[0:0]$14484
- attribute \src "libresoc.v:202763.5-202763.29"
+ assign $0\data_r4__msr_ok$next[0:0]$14291 $3\data_r4__msr_ok$next[0:0]$14296
+ attribute \src "libresoc.v:201707.5-201707.29"
switch \initial
- attribute \src "libresoc.v:202763.9-202763.17"
+ attribute \src "libresoc.v:201707.9-201707.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__msr_ok$next[0:0]$14481 $1\data_r4__msr$next[63:0]$14480 } { \msr_ok \alu_trap0_msr }
+ assign { $1\data_r4__msr_ok$next[0:0]$14293 $1\data_r4__msr$next[63:0]$14292 } { \msr_ok \alu_trap0_msr }
case
- assign $1\data_r4__msr$next[63:0]$14480 \data_r4__msr
- assign $1\data_r4__msr_ok$next[0:0]$14481 \data_r4__msr_ok
+ assign $1\data_r4__msr$next[63:0]$14292 \data_r4__msr
+ assign $1\data_r4__msr_ok$next[0:0]$14293 \data_r4__msr_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__msr_ok$next[0:0]$14483 $2\data_r4__msr$next[63:0]$14482 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r4__msr_ok$next[0:0]$14295 $2\data_r4__msr$next[63:0]$14294 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r4__msr$next[63:0]$14482 $1\data_r4__msr$next[63:0]$14480
- assign $2\data_r4__msr_ok$next[0:0]$14483 $1\data_r4__msr_ok$next[0:0]$14481
+ assign $2\data_r4__msr$next[63:0]$14294 $1\data_r4__msr$next[63:0]$14292
+ assign $2\data_r4__msr_ok$next[0:0]$14295 $1\data_r4__msr_ok$next[0:0]$14293
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__msr_ok$next[0:0]$14484 1'0
+ assign $3\data_r4__msr_ok$next[0:0]$14296 1'0
case
- assign $3\data_r4__msr_ok$next[0:0]$14484 $2\data_r4__msr_ok$next[0:0]$14483
+ assign $3\data_r4__msr_ok$next[0:0]$14296 $2\data_r4__msr_ok$next[0:0]$14295
end
sync always
- update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14478
- update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14479
+ update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14290
+ update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14291
end
- attribute \src "libresoc.v:202784.3-202793.6"
- process $proc$libresoc.v:202784$14485
+ attribute \src "libresoc.v:201728.3-201737.6"
+ process $proc$libresoc.v:201728$14297
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$14486 $1\src_r0$next[63:0]$14487
- attribute \src "libresoc.v:202785.5-202785.29"
+ assign $0\src_r0$next[63:0]$14298 $1\src_r0$next[63:0]$14299
+ attribute \src "libresoc.v:201729.5-201729.29"
switch \initial
- attribute \src "libresoc.v:202785.9-202785.17"
+ attribute \src "libresoc.v:201729.9-201729.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$14487 \src1_i
+ assign $1\src_r0$next[63:0]$14299 \src1_i
case
- assign $1\src_r0$next[63:0]$14487 \src_r0
+ assign $1\src_r0$next[63:0]$14299 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$14486
+ update \src_r0$next $0\src_r0$next[63:0]$14298
end
- attribute \src "libresoc.v:202794.3-202803.6"
- process $proc$libresoc.v:202794$14488
+ attribute \src "libresoc.v:201738.3-201747.6"
+ process $proc$libresoc.v:201738$14300
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$14489 $1\src_r1$next[63:0]$14490
- attribute \src "libresoc.v:202795.5-202795.29"
+ assign $0\src_r1$next[63:0]$14301 $1\src_r1$next[63:0]$14302
+ attribute \src "libresoc.v:201739.5-201739.29"
switch \initial
- attribute \src "libresoc.v:202795.9-202795.17"
+ attribute \src "libresoc.v:201739.9-201739.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$14490 \src2_i
+ assign $1\src_r1$next[63:0]$14302 \src2_i
case
- assign $1\src_r1$next[63:0]$14490 \src_r1
+ assign $1\src_r1$next[63:0]$14302 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$14489
+ update \src_r1$next $0\src_r1$next[63:0]$14301
end
- attribute \src "libresoc.v:202804.3-202813.6"
- process $proc$libresoc.v:202804$14491
+ attribute \src "libresoc.v:201748.3-201757.6"
+ process $proc$libresoc.v:201748$14303
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$14492 $1\src_r2$next[63:0]$14493
- attribute \src "libresoc.v:202805.5-202805.29"
+ assign $0\src_r2$next[63:0]$14304 $1\src_r2$next[63:0]$14305
+ attribute \src "libresoc.v:201749.5-201749.29"
switch \initial
- attribute \src "libresoc.v:202805.9-202805.17"
+ attribute \src "libresoc.v:201749.9-201749.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$14493 \src3_i
+ assign $1\src_r2$next[63:0]$14305 \src3_i
case
- assign $1\src_r2$next[63:0]$14493 \src_r2
+ assign $1\src_r2$next[63:0]$14305 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$14492
+ update \src_r2$next $0\src_r2$next[63:0]$14304
end
- attribute \src "libresoc.v:202814.3-202823.6"
- process $proc$libresoc.v:202814$14494
+ attribute \src "libresoc.v:201758.3-201767.6"
+ process $proc$libresoc.v:201758$14306
assign { } { }
assign { } { }
- assign $0\src_r3$next[63:0]$14495 $1\src_r3$next[63:0]$14496
- attribute \src "libresoc.v:202815.5-202815.29"
+ assign $0\src_r3$next[63:0]$14307 $1\src_r3$next[63:0]$14308
+ attribute \src "libresoc.v:201759.5-201759.29"
switch \initial
- attribute \src "libresoc.v:202815.9-202815.17"
+ attribute \src "libresoc.v:201759.9-201759.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[63:0]$14496 \src4_i
+ assign $1\src_r3$next[63:0]$14308 \src4_i
case
- assign $1\src_r3$next[63:0]$14496 \src_r3
+ assign $1\src_r3$next[63:0]$14308 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[63:0]$14495
+ update \src_r3$next $0\src_r3$next[63:0]$14307
end
- attribute \src "libresoc.v:202824.3-202832.6"
- process $proc$libresoc.v:202824$14497
+ attribute \src "libresoc.v:201768.3-201776.6"
+ process $proc$libresoc.v:201768$14309
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$14498 $1\alui_l_r_alui$next[0:0]$14499
- attribute \src "libresoc.v:202825.5-202825.29"
+ assign $0\alui_l_r_alui$next[0:0]$14310 $1\alui_l_r_alui$next[0:0]$14311
+ attribute \src "libresoc.v:201769.5-201769.29"
switch \initial
- attribute \src "libresoc.v:202825.9-202825.17"
+ attribute \src "libresoc.v:201769.9-201769.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$14499 1'1
+ assign $1\alui_l_r_alui$next[0:0]$14311 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$14499 \$89
+ assign $1\alui_l_r_alui$next[0:0]$14311 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14498
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14310
end
- attribute \src "libresoc.v:202833.3-202841.6"
- process $proc$libresoc.v:202833$14500
+ attribute \src "libresoc.v:201777.3-201785.6"
+ process $proc$libresoc.v:201777$14312
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$14501 $1\alu_l_r_alu$next[0:0]$14502
- attribute \src "libresoc.v:202834.5-202834.29"
+ assign $0\alu_l_r_alu$next[0:0]$14313 $1\alu_l_r_alu$next[0:0]$14314
+ attribute \src "libresoc.v:201778.5-201778.29"
switch \initial
- attribute \src "libresoc.v:202834.9-202834.17"
+ attribute \src "libresoc.v:201778.9-201778.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$14502 1'1
+ assign $1\alu_l_r_alu$next[0:0]$14314 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$14502 \$91
+ assign $1\alu_l_r_alu$next[0:0]$14314 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14501
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14313
end
- attribute \src "libresoc.v:202842.3-202851.6"
- process $proc$libresoc.v:202842$14503
+ attribute \src "libresoc.v:201786.3-201795.6"
+ process $proc$libresoc.v:201786$14315
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:202843.5-202843.29"
+ attribute \src "libresoc.v:201787.5-201787.29"
switch \initial
- attribute \src "libresoc.v:202843.9-202843.17"
+ attribute \src "libresoc.v:201787.9-201787.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:202852.3-202861.6"
- process $proc$libresoc.v:202852$14504
+ attribute \src "libresoc.v:201796.3-201805.6"
+ process $proc$libresoc.v:201796$14316
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:202853.5-202853.29"
+ attribute \src "libresoc.v:201797.5-201797.29"
switch \initial
- attribute \src "libresoc.v:202853.9-202853.17"
+ attribute \src "libresoc.v:201797.9-201797.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:202862.3-202871.6"
- process $proc$libresoc.v:202862$14505
+ attribute \src "libresoc.v:201806.3-201815.6"
+ process $proc$libresoc.v:201806$14317
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:202863.5-202863.29"
+ attribute \src "libresoc.v:201807.5-201807.29"
switch \initial
- attribute \src "libresoc.v:202863.9-202863.17"
+ attribute \src "libresoc.v:201807.9-201807.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:202872.3-202881.6"
- process $proc$libresoc.v:202872$14506
+ attribute \src "libresoc.v:201816.3-201825.6"
+ process $proc$libresoc.v:201816$14318
assign { } { }
assign { } { }
assign $0\dest4_o[63:0] $1\dest4_o[63:0]
- attribute \src "libresoc.v:202873.5-202873.29"
+ attribute \src "libresoc.v:201817.5-201817.29"
switch \initial
- attribute \src "libresoc.v:202873.9-202873.17"
+ attribute \src "libresoc.v:201817.9-201817.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[63:0]
end
- attribute \src "libresoc.v:202882.3-202891.6"
- process $proc$libresoc.v:202882$14507
+ attribute \src "libresoc.v:201826.3-201835.6"
+ process $proc$libresoc.v:201826$14319
assign { } { }
assign { } { }
assign $0\dest5_o[63:0] $1\dest5_o[63:0]
- attribute \src "libresoc.v:202883.5-202883.29"
+ attribute \src "libresoc.v:201827.5-201827.29"
switch \initial
- attribute \src "libresoc.v:202883.9-202883.17"
+ attribute \src "libresoc.v:201827.9-201827.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[63:0]
end
- attribute \src "libresoc.v:202892.3-202900.6"
- process $proc$libresoc.v:202892$14508
+ attribute \src "libresoc.v:201836.3-201844.6"
+ process $proc$libresoc.v:201836$14320
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[4:0]$14509 $1\prev_wr_go$next[4:0]$14510
- attribute \src "libresoc.v:202893.5-202893.29"
+ assign $0\prev_wr_go$next[4:0]$14321 $1\prev_wr_go$next[4:0]$14322
+ attribute \src "libresoc.v:201837.5-201837.29"
switch \initial
- attribute \src "libresoc.v:202893.9-202893.17"
+ attribute \src "libresoc.v:201837.9-201837.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[4:0]$14510 5'00000
- case
- assign $1\prev_wr_go$next[4:0]$14510 \$21
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14509
- end
- connect \$5 $reduce_and$libresoc.v:202340$14296_Y
- connect \$99 $and$libresoc.v:202341$14297_Y
- connect \$101 $and$libresoc.v:202342$14298_Y
- connect \$103 $and$libresoc.v:202343$14299_Y
- connect \$105 $and$libresoc.v:202344$14300_Y
- connect \$107 $and$libresoc.v:202345$14301_Y
- connect \$109 $and$libresoc.v:202346$14302_Y
- connect \$111 $and$libresoc.v:202347$14303_Y
- connect \$113 $and$libresoc.v:202348$14304_Y
- connect \$115 $and$libresoc.v:202349$14305_Y
- connect \$117 $and$libresoc.v:202350$14306_Y
- connect \$11 $and$libresoc.v:202351$14307_Y
- connect \$119 $and$libresoc.v:202352$14308_Y
- connect \$121 $and$libresoc.v:202353$14309_Y
- connect \$123 $and$libresoc.v:202354$14310_Y
- connect \$13 $not$libresoc.v:202355$14311_Y
- connect \$15 $and$libresoc.v:202356$14312_Y
- connect \$17 $not$libresoc.v:202357$14313_Y
- connect \$19 $and$libresoc.v:202358$14314_Y
- connect \$21 $and$libresoc.v:202359$14315_Y
- connect \$25 $not$libresoc.v:202360$14316_Y
- connect \$27 $and$libresoc.v:202361$14317_Y
- connect \$24 $reduce_or$libresoc.v:202362$14318_Y
- connect \$23 $not$libresoc.v:202363$14319_Y
- connect \$31 $and$libresoc.v:202364$14320_Y
- connect \$33 $reduce_or$libresoc.v:202365$14321_Y
- connect \$35 $reduce_or$libresoc.v:202366$14322_Y
- connect \$37 $or$libresoc.v:202367$14323_Y
- connect \$3 $and$libresoc.v:202368$14324_Y
- connect \$39 $not$libresoc.v:202369$14325_Y
- connect \$41 $and$libresoc.v:202370$14326_Y
- connect \$43 $and$libresoc.v:202371$14327_Y
- connect \$45 $eq$libresoc.v:202372$14328_Y
- connect \$47 $and$libresoc.v:202373$14329_Y
- connect \$49 $eq$libresoc.v:202374$14330_Y
- connect \$51 $and$libresoc.v:202375$14331_Y
- connect \$53 $and$libresoc.v:202376$14332_Y
- connect \$55 $and$libresoc.v:202377$14333_Y
- connect \$57 $or$libresoc.v:202378$14334_Y
- connect \$59 $or$libresoc.v:202379$14335_Y
- connect \$61 $or$libresoc.v:202380$14336_Y
- connect \$63 $or$libresoc.v:202381$14337_Y
- connect \$65 $and$libresoc.v:202382$14338_Y
- connect \$67 $and$libresoc.v:202383$14339_Y
- connect \$6 $not$libresoc.v:202384$14340_Y
- connect \$69 $or$libresoc.v:202385$14341_Y
- connect \$71 $and$libresoc.v:202386$14342_Y
- connect \$73 $and$libresoc.v:202387$14343_Y
- connect \$75 $and$libresoc.v:202388$14344_Y
- connect \$77 $and$libresoc.v:202389$14345_Y
- connect \$79 $and$libresoc.v:202390$14346_Y
- connect \$81 $ternary$libresoc.v:202391$14347_Y
- connect \$83 $ternary$libresoc.v:202392$14348_Y
- connect \$85 $ternary$libresoc.v:202393$14349_Y
- connect \$87 $ternary$libresoc.v:202394$14350_Y
- connect \$8 $or$libresoc.v:202395$14351_Y
- connect \$89 $and$libresoc.v:202396$14352_Y
- connect \$91 $and$libresoc.v:202397$14353_Y
- connect \$93 $and$libresoc.v:202398$14354_Y
- connect \$95 $and$libresoc.v:202399$14355_Y
- connect \$97 $not$libresoc.v:202400$14356_Y
+ assign $1\prev_wr_go$next[4:0]$14322 5'00000
+ case
+ assign $1\prev_wr_go$next[4:0]$14322 \$21
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14321
+ end
+ connect \$5 $reduce_and$libresoc.v:201284$14108_Y
+ connect \$99 $and$libresoc.v:201285$14109_Y
+ connect \$101 $and$libresoc.v:201286$14110_Y
+ connect \$103 $and$libresoc.v:201287$14111_Y
+ connect \$105 $and$libresoc.v:201288$14112_Y
+ connect \$107 $and$libresoc.v:201289$14113_Y
+ connect \$109 $and$libresoc.v:201290$14114_Y
+ connect \$111 $and$libresoc.v:201291$14115_Y
+ connect \$113 $and$libresoc.v:201292$14116_Y
+ connect \$115 $and$libresoc.v:201293$14117_Y
+ connect \$117 $and$libresoc.v:201294$14118_Y
+ connect \$11 $and$libresoc.v:201295$14119_Y
+ connect \$119 $and$libresoc.v:201296$14120_Y
+ connect \$121 $and$libresoc.v:201297$14121_Y
+ connect \$123 $and$libresoc.v:201298$14122_Y
+ connect \$13 $not$libresoc.v:201299$14123_Y
+ connect \$15 $and$libresoc.v:201300$14124_Y
+ connect \$17 $not$libresoc.v:201301$14125_Y
+ connect \$19 $and$libresoc.v:201302$14126_Y
+ connect \$21 $and$libresoc.v:201303$14127_Y
+ connect \$25 $not$libresoc.v:201304$14128_Y
+ connect \$27 $and$libresoc.v:201305$14129_Y
+ connect \$24 $reduce_or$libresoc.v:201306$14130_Y
+ connect \$23 $not$libresoc.v:201307$14131_Y
+ connect \$31 $and$libresoc.v:201308$14132_Y
+ connect \$33 $reduce_or$libresoc.v:201309$14133_Y
+ connect \$35 $reduce_or$libresoc.v:201310$14134_Y
+ connect \$37 $or$libresoc.v:201311$14135_Y
+ connect \$3 $and$libresoc.v:201312$14136_Y
+ connect \$39 $not$libresoc.v:201313$14137_Y
+ connect \$41 $and$libresoc.v:201314$14138_Y
+ connect \$43 $and$libresoc.v:201315$14139_Y
+ connect \$45 $eq$libresoc.v:201316$14140_Y
+ connect \$47 $and$libresoc.v:201317$14141_Y
+ connect \$49 $eq$libresoc.v:201318$14142_Y
+ connect \$51 $and$libresoc.v:201319$14143_Y
+ connect \$53 $and$libresoc.v:201320$14144_Y
+ connect \$55 $and$libresoc.v:201321$14145_Y
+ connect \$57 $or$libresoc.v:201322$14146_Y
+ connect \$59 $or$libresoc.v:201323$14147_Y
+ connect \$61 $or$libresoc.v:201324$14148_Y
+ connect \$63 $or$libresoc.v:201325$14149_Y
+ connect \$65 $and$libresoc.v:201326$14150_Y
+ connect \$67 $and$libresoc.v:201327$14151_Y
+ connect \$6 $not$libresoc.v:201328$14152_Y
+ connect \$69 $or$libresoc.v:201329$14153_Y
+ connect \$71 $and$libresoc.v:201330$14154_Y
+ connect \$73 $and$libresoc.v:201331$14155_Y
+ connect \$75 $and$libresoc.v:201332$14156_Y
+ connect \$77 $and$libresoc.v:201333$14157_Y
+ connect \$79 $and$libresoc.v:201334$14158_Y
+ connect \$81 $ternary$libresoc.v:201335$14159_Y
+ connect \$83 $ternary$libresoc.v:201336$14160_Y
+ connect \$85 $ternary$libresoc.v:201337$14161_Y
+ connect \$87 $ternary$libresoc.v:201338$14162_Y
+ connect \$8 $or$libresoc.v:201339$14163_Y
+ connect \$89 $and$libresoc.v:201340$14164_Y
+ connect \$91 $and$libresoc.v:201341$14165_Y
+ connect \$93 $and$libresoc.v:201342$14166_Y
+ connect \$95 $and$libresoc.v:201343$14167_Y
+ connect \$97 $not$libresoc.v:201344$14168_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$113
connect \all_rd_dly$next \all_rd
connect \all_rd \$11
end
-attribute \src "libresoc.v:202934.1-202992.10"
+attribute \src "libresoc.v:201878.1-201936.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l"
attribute \generator "nMigen"
module \upd_l
- attribute \src "libresoc.v:202935.7-202935.20"
+ attribute \src "libresoc.v:201879.7-201879.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:202980.3-202988.6"
- wire $0\q_int$next[0:0]$14560
- attribute \src "libresoc.v:202978.3-202979.27"
+ attribute \src "libresoc.v:201924.3-201932.6"
+ wire $0\q_int$next[0:0]$14372
+ attribute \src "libresoc.v:201922.3-201923.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:202980.3-202988.6"
- wire $1\q_int$next[0:0]$14561
- attribute \src "libresoc.v:202957.7-202957.19"
+ attribute \src "libresoc.v:201924.3-201932.6"
+ wire $1\q_int$next[0:0]$14373
+ attribute \src "libresoc.v:201901.7-201901.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:202970.17-202970.96"
- wire $and$libresoc.v:202970$14550_Y
- attribute \src "libresoc.v:202975.17-202975.96"
- wire $and$libresoc.v:202975$14555_Y
- attribute \src "libresoc.v:202972.18-202972.93"
- wire $not$libresoc.v:202972$14552_Y
- attribute \src "libresoc.v:202974.17-202974.92"
- wire $not$libresoc.v:202974$14554_Y
- attribute \src "libresoc.v:202977.17-202977.92"
- wire $not$libresoc.v:202977$14557_Y
- attribute \src "libresoc.v:202971.18-202971.98"
- wire $or$libresoc.v:202971$14551_Y
- attribute \src "libresoc.v:202973.18-202973.99"
- wire $or$libresoc.v:202973$14553_Y
- attribute \src "libresoc.v:202976.17-202976.97"
- wire $or$libresoc.v:202976$14556_Y
+ attribute \src "libresoc.v:201914.17-201914.96"
+ wire $and$libresoc.v:201914$14362_Y
+ attribute \src "libresoc.v:201919.17-201919.96"
+ wire $and$libresoc.v:201919$14367_Y
+ attribute \src "libresoc.v:201916.18-201916.93"
+ wire $not$libresoc.v:201916$14364_Y
+ attribute \src "libresoc.v:201918.17-201918.92"
+ wire $not$libresoc.v:201918$14366_Y
+ attribute \src "libresoc.v:201921.17-201921.92"
+ wire $not$libresoc.v:201921$14369_Y
+ attribute \src "libresoc.v:201915.18-201915.98"
+ wire $or$libresoc.v:201915$14363_Y
+ attribute \src "libresoc.v:201917.18-201917.99"
+ wire $or$libresoc.v:201917$14365_Y
+ attribute \src "libresoc.v:201920.17-201920.97"
+ wire $or$libresoc.v:201920$14368_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:202935.7-202935.15"
+ attribute \src "libresoc.v:201879.7-201879.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_upd
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:202970$14550
+ cell $and $and$libresoc.v:201914$14362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:202970$14550_Y
+ connect \Y $and$libresoc.v:201914$14362_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:202975$14555
+ cell $and $and$libresoc.v:201919$14367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:202975$14555_Y
+ connect \Y $and$libresoc.v:201919$14367_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:202972$14552
+ cell $not $not$libresoc.v:201916$14364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_upd
- connect \Y $not$libresoc.v:202972$14552_Y
+ connect \Y $not$libresoc.v:201916$14364_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:202974$14554
+ cell $not $not$libresoc.v:201918$14366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:202974$14554_Y
+ connect \Y $not$libresoc.v:201918$14366_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:202977$14557
+ cell $not $not$libresoc.v:201921$14369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:202977$14557_Y
+ connect \Y $not$libresoc.v:201921$14369_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:202971$14551
+ cell $or $or$libresoc.v:201915$14363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_upd
- connect \Y $or$libresoc.v:202971$14551_Y
+ connect \Y $or$libresoc.v:201915$14363_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:202973$14553
+ cell $or $or$libresoc.v:201917$14365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_upd
connect \B \q_int
- connect \Y $or$libresoc.v:202973$14553_Y
+ connect \Y $or$libresoc.v:201917$14365_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:202976$14556
+ cell $or $or$libresoc.v:201920$14368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_upd
- connect \Y $or$libresoc.v:202976$14556_Y
+ connect \Y $or$libresoc.v:201920$14368_Y
end
- attribute \src "libresoc.v:202935.7-202935.20"
- process $proc$libresoc.v:202935$14562
+ attribute \src "libresoc.v:201879.7-201879.20"
+ process $proc$libresoc.v:201879$14374
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:202957.7-202957.19"
- process $proc$libresoc.v:202957$14563
+ attribute \src "libresoc.v:201901.7-201901.19"
+ process $proc$libresoc.v:201901$14375
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:202978.3-202979.27"
- process $proc$libresoc.v:202978$14558
+ attribute \src "libresoc.v:201922.3-201923.27"
+ process $proc$libresoc.v:201922$14370
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:202980.3-202988.6"
- process $proc$libresoc.v:202980$14559
+ attribute \src "libresoc.v:201924.3-201932.6"
+ process $proc$libresoc.v:201924$14371
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14560 $1\q_int$next[0:0]$14561
- attribute \src "libresoc.v:202981.5-202981.29"
+ assign $0\q_int$next[0:0]$14372 $1\q_int$next[0:0]$14373
+ attribute \src "libresoc.v:201925.5-201925.29"
switch \initial
- attribute \src "libresoc.v:202981.9-202981.17"
+ attribute \src "libresoc.v:201925.9-201925.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14561 1'0
+ assign $1\q_int$next[0:0]$14373 1'0
case
- assign $1\q_int$next[0:0]$14561 \$5
+ assign $1\q_int$next[0:0]$14373 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14560
+ update \q_int$next $0\q_int$next[0:0]$14372
end
- connect \$9 $and$libresoc.v:202970$14550_Y
- connect \$11 $or$libresoc.v:202971$14551_Y
- connect \$13 $not$libresoc.v:202972$14552_Y
- connect \$15 $or$libresoc.v:202973$14553_Y
- connect \$1 $not$libresoc.v:202974$14554_Y
- connect \$3 $and$libresoc.v:202975$14555_Y
- connect \$5 $or$libresoc.v:202976$14556_Y
- connect \$7 $not$libresoc.v:202977$14557_Y
+ connect \$9 $and$libresoc.v:201914$14362_Y
+ connect \$11 $or$libresoc.v:201915$14363_Y
+ connect \$13 $not$libresoc.v:201916$14364_Y
+ connect \$15 $or$libresoc.v:201917$14365_Y
+ connect \$1 $not$libresoc.v:201918$14366_Y
+ connect \$3 $and$libresoc.v:201919$14367_Y
+ connect \$5 $or$libresoc.v:201920$14368_Y
+ connect \$7 $not$libresoc.v:201921$14369_Y
connect \qlq_upd \$15
connect \qn_upd \$13
connect \q_upd \$11
end
-attribute \src "libresoc.v:202996.1-203054.10"
+attribute \src "libresoc.v:201940.1-201998.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l"
attribute \generator "nMigen"
module \valid_l
- attribute \src "libresoc.v:202997.7-202997.20"
+ attribute \src "libresoc.v:201941.7-201941.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:203042.3-203050.6"
- wire $0\q_int$next[0:0]$14574
- attribute \src "libresoc.v:203040.3-203041.27"
+ attribute \src "libresoc.v:201986.3-201994.6"
+ wire $0\q_int$next[0:0]$14386
+ attribute \src "libresoc.v:201984.3-201985.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:203042.3-203050.6"
- wire $1\q_int$next[0:0]$14575
- attribute \src "libresoc.v:203019.7-203019.19"
+ attribute \src "libresoc.v:201986.3-201994.6"
+ wire $1\q_int$next[0:0]$14387
+ attribute \src "libresoc.v:201963.7-201963.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:203032.17-203032.96"
- wire $and$libresoc.v:203032$14564_Y
- attribute \src "libresoc.v:203037.17-203037.96"
- wire $and$libresoc.v:203037$14569_Y
- attribute \src "libresoc.v:203034.18-203034.95"
- wire $not$libresoc.v:203034$14566_Y
- attribute \src "libresoc.v:203036.17-203036.94"
- wire $not$libresoc.v:203036$14568_Y
- attribute \src "libresoc.v:203039.17-203039.94"
- wire $not$libresoc.v:203039$14571_Y
- attribute \src "libresoc.v:203033.18-203033.100"
- wire $or$libresoc.v:203033$14565_Y
- attribute \src "libresoc.v:203035.18-203035.101"
- wire $or$libresoc.v:203035$14567_Y
- attribute \src "libresoc.v:203038.17-203038.99"
- wire $or$libresoc.v:203038$14570_Y
+ attribute \src "libresoc.v:201976.17-201976.96"
+ wire $and$libresoc.v:201976$14376_Y
+ attribute \src "libresoc.v:201981.17-201981.96"
+ wire $and$libresoc.v:201981$14381_Y
+ attribute \src "libresoc.v:201978.18-201978.95"
+ wire $not$libresoc.v:201978$14378_Y
+ attribute \src "libresoc.v:201980.17-201980.94"
+ wire $not$libresoc.v:201980$14380_Y
+ attribute \src "libresoc.v:201983.17-201983.94"
+ wire $not$libresoc.v:201983$14383_Y
+ attribute \src "libresoc.v:201977.18-201977.100"
+ wire $or$libresoc.v:201977$14377_Y
+ attribute \src "libresoc.v:201979.18-201979.101"
+ wire $or$libresoc.v:201979$14379_Y
+ attribute \src "libresoc.v:201982.17-201982.99"
+ wire $or$libresoc.v:201982$14382_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:202997.7-202997.15"
+ attribute \src "libresoc.v:201941.7-201941.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_valid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:203032$14564
+ cell $and $and$libresoc.v:201976$14376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:203032$14564_Y
+ connect \Y $and$libresoc.v:201976$14376_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:203037$14569
+ cell $and $and$libresoc.v:201981$14381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:203037$14569_Y
+ connect \Y $and$libresoc.v:201981$14381_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:203034$14566
+ cell $not $not$libresoc.v:201978$14378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_valid
- connect \Y $not$libresoc.v:203034$14566_Y
+ connect \Y $not$libresoc.v:201978$14378_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:203036$14568
+ cell $not $not$libresoc.v:201980$14380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:203036$14568_Y
+ connect \Y $not$libresoc.v:201980$14380_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:203039$14571
+ cell $not $not$libresoc.v:201983$14383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:203039$14571_Y
+ connect \Y $not$libresoc.v:201983$14383_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:203033$14565
+ cell $or $or$libresoc.v:201977$14377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_valid
- connect \Y $or$libresoc.v:203033$14565_Y
+ connect \Y $or$libresoc.v:201977$14377_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:203035$14567
+ cell $or $or$libresoc.v:201979$14379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_valid
connect \B \q_int
- connect \Y $or$libresoc.v:203035$14567_Y
+ connect \Y $or$libresoc.v:201979$14379_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:203038$14570
+ cell $or $or$libresoc.v:201982$14382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_valid
- connect \Y $or$libresoc.v:203038$14570_Y
+ connect \Y $or$libresoc.v:201982$14382_Y
end
- attribute \src "libresoc.v:202997.7-202997.20"
- process $proc$libresoc.v:202997$14576
+ attribute \src "libresoc.v:201941.7-201941.20"
+ process $proc$libresoc.v:201941$14388
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:203019.7-203019.19"
- process $proc$libresoc.v:203019$14577
+ attribute \src "libresoc.v:201963.7-201963.19"
+ process $proc$libresoc.v:201963$14389
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:203040.3-203041.27"
- process $proc$libresoc.v:203040$14572
+ attribute \src "libresoc.v:201984.3-201985.27"
+ process $proc$libresoc.v:201984$14384
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:203042.3-203050.6"
- process $proc$libresoc.v:203042$14573
+ attribute \src "libresoc.v:201986.3-201994.6"
+ process $proc$libresoc.v:201986$14385
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14574 $1\q_int$next[0:0]$14575
- attribute \src "libresoc.v:203043.5-203043.29"
+ assign $0\q_int$next[0:0]$14386 $1\q_int$next[0:0]$14387
+ attribute \src "libresoc.v:201987.5-201987.29"
switch \initial
- attribute \src "libresoc.v:203043.9-203043.17"
+ attribute \src "libresoc.v:201987.9-201987.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14575 1'0
+ assign $1\q_int$next[0:0]$14387 1'0
case
- assign $1\q_int$next[0:0]$14575 \$5
+ assign $1\q_int$next[0:0]$14387 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14574
+ update \q_int$next $0\q_int$next[0:0]$14386
end
- connect \$9 $and$libresoc.v:203032$14564_Y
- connect \$11 $or$libresoc.v:203033$14565_Y
- connect \$13 $not$libresoc.v:203034$14566_Y
- connect \$15 $or$libresoc.v:203035$14567_Y
- connect \$1 $not$libresoc.v:203036$14568_Y
- connect \$3 $and$libresoc.v:203037$14569_Y
- connect \$5 $or$libresoc.v:203038$14570_Y
- connect \$7 $not$libresoc.v:203039$14571_Y
+ connect \$9 $and$libresoc.v:201976$14376_Y
+ connect \$11 $or$libresoc.v:201977$14377_Y
+ connect \$13 $not$libresoc.v:201978$14378_Y
+ connect \$15 $or$libresoc.v:201979$14379_Y
+ connect \$1 $not$libresoc.v:201980$14380_Y
+ connect \$3 $and$libresoc.v:201981$14381_Y
+ connect \$5 $or$libresoc.v:201982$14382_Y
+ connect \$7 $not$libresoc.v:201983$14383_Y
connect \qlq_valid \$15
connect \qn_valid \$13
connect \q_valid \$11
end
-attribute \src "libresoc.v:203058.1-203116.10"
+attribute \src "libresoc.v:202002.1-202060.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l"
attribute \generator "nMigen"
module \wri_l
- attribute \src "libresoc.v:203059.7-203059.20"
+ attribute \src "libresoc.v:202003.7-202003.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:203104.3-203112.6"
- wire $0\q_int$next[0:0]$14588
- attribute \src "libresoc.v:203102.3-203103.27"
+ attribute \src "libresoc.v:202048.3-202056.6"
+ wire $0\q_int$next[0:0]$14400
+ attribute \src "libresoc.v:202046.3-202047.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:203104.3-203112.6"
- wire $1\q_int$next[0:0]$14589
- attribute \src "libresoc.v:203081.7-203081.19"
+ attribute \src "libresoc.v:202048.3-202056.6"
+ wire $1\q_int$next[0:0]$14401
+ attribute \src "libresoc.v:202025.7-202025.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:203094.17-203094.96"
- wire $and$libresoc.v:203094$14578_Y
- attribute \src "libresoc.v:203099.17-203099.96"
- wire $and$libresoc.v:203099$14583_Y
- attribute \src "libresoc.v:203096.18-203096.93"
- wire $not$libresoc.v:203096$14580_Y
- attribute \src "libresoc.v:203098.17-203098.92"
- wire $not$libresoc.v:203098$14582_Y
- attribute \src "libresoc.v:203101.17-203101.92"
- wire $not$libresoc.v:203101$14585_Y
- attribute \src "libresoc.v:203095.18-203095.98"
- wire $or$libresoc.v:203095$14579_Y
- attribute \src "libresoc.v:203097.18-203097.99"
- wire $or$libresoc.v:203097$14581_Y
- attribute \src "libresoc.v:203100.17-203100.97"
- wire $or$libresoc.v:203100$14584_Y
+ attribute \src "libresoc.v:202038.17-202038.96"
+ wire $and$libresoc.v:202038$14390_Y
+ attribute \src "libresoc.v:202043.17-202043.96"
+ wire $and$libresoc.v:202043$14395_Y
+ attribute \src "libresoc.v:202040.18-202040.93"
+ wire $not$libresoc.v:202040$14392_Y
+ attribute \src "libresoc.v:202042.17-202042.92"
+ wire $not$libresoc.v:202042$14394_Y
+ attribute \src "libresoc.v:202045.17-202045.92"
+ wire $not$libresoc.v:202045$14397_Y
+ attribute \src "libresoc.v:202039.18-202039.98"
+ wire $or$libresoc.v:202039$14391_Y
+ attribute \src "libresoc.v:202041.18-202041.99"
+ wire $or$libresoc.v:202041$14393_Y
+ attribute \src "libresoc.v:202044.17-202044.97"
+ wire $or$libresoc.v:202044$14396_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:203059.7-203059.15"
+ attribute \src "libresoc.v:202003.7-202003.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_wri
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:203094$14578
+ cell $and $and$libresoc.v:202038$14390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:203094$14578_Y
+ connect \Y $and$libresoc.v:202038$14390_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:203099$14583
+ cell $and $and$libresoc.v:202043$14395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:203099$14583_Y
+ connect \Y $and$libresoc.v:202043$14395_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:203096$14580
+ cell $not $not$libresoc.v:202040$14392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_wri
- connect \Y $not$libresoc.v:203096$14580_Y
+ connect \Y $not$libresoc.v:202040$14392_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:203098$14582
+ cell $not $not$libresoc.v:202042$14394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:203098$14582_Y
+ connect \Y $not$libresoc.v:202042$14394_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:203101$14585
+ cell $not $not$libresoc.v:202045$14397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:203101$14585_Y
+ connect \Y $not$libresoc.v:202045$14397_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:203095$14579
+ cell $or $or$libresoc.v:202039$14391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_wri
- connect \Y $or$libresoc.v:203095$14579_Y
+ connect \Y $or$libresoc.v:202039$14391_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:203097$14581
+ cell $or $or$libresoc.v:202041$14393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_wri
connect \B \q_int
- connect \Y $or$libresoc.v:203097$14581_Y
+ connect \Y $or$libresoc.v:202041$14393_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:203100$14584
+ cell $or $or$libresoc.v:202044$14396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_wri
- connect \Y $or$libresoc.v:203100$14584_Y
+ connect \Y $or$libresoc.v:202044$14396_Y
end
- attribute \src "libresoc.v:203059.7-203059.20"
- process $proc$libresoc.v:203059$14590
+ attribute \src "libresoc.v:202003.7-202003.20"
+ process $proc$libresoc.v:202003$14402
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:203081.7-203081.19"
- process $proc$libresoc.v:203081$14591
+ attribute \src "libresoc.v:202025.7-202025.19"
+ process $proc$libresoc.v:202025$14403
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:203102.3-203103.27"
- process $proc$libresoc.v:203102$14586
+ attribute \src "libresoc.v:202046.3-202047.27"
+ process $proc$libresoc.v:202046$14398
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:203104.3-203112.6"
- process $proc$libresoc.v:203104$14587
+ attribute \src "libresoc.v:202048.3-202056.6"
+ process $proc$libresoc.v:202048$14399
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14588 $1\q_int$next[0:0]$14589
- attribute \src "libresoc.v:203105.5-203105.29"
+ assign $0\q_int$next[0:0]$14400 $1\q_int$next[0:0]$14401
+ attribute \src "libresoc.v:202049.5-202049.29"
switch \initial
- attribute \src "libresoc.v:203105.9-203105.17"
+ attribute \src "libresoc.v:202049.9-202049.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14589 1'0
+ assign $1\q_int$next[0:0]$14401 1'0
case
- assign $1\q_int$next[0:0]$14589 \$5
+ assign $1\q_int$next[0:0]$14401 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14588
+ update \q_int$next $0\q_int$next[0:0]$14400
end
- connect \$9 $and$libresoc.v:203094$14578_Y
- connect \$11 $or$libresoc.v:203095$14579_Y
- connect \$13 $not$libresoc.v:203096$14580_Y
- connect \$15 $or$libresoc.v:203097$14581_Y
- connect \$1 $not$libresoc.v:203098$14582_Y
- connect \$3 $and$libresoc.v:203099$14583_Y
- connect \$5 $or$libresoc.v:203100$14584_Y
- connect \$7 $not$libresoc.v:203101$14585_Y
+ connect \$9 $and$libresoc.v:202038$14390_Y
+ connect \$11 $or$libresoc.v:202039$14391_Y
+ connect \$13 $not$libresoc.v:202040$14392_Y
+ connect \$15 $or$libresoc.v:202041$14393_Y
+ connect \$1 $not$libresoc.v:202042$14394_Y
+ connect \$3 $and$libresoc.v:202043$14395_Y
+ connect \$5 $or$libresoc.v:202044$14396_Y
+ connect \$7 $not$libresoc.v:202045$14397_Y
connect \qlq_wri \$15
connect \qn_wri \$13
connect \q_wri \$11
end
-attribute \src "libresoc.v:203120.1-203186.10"
+attribute \src "libresoc.v:202064.1-202130.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a"
attribute \generator "nMigen"
module \wrpick_CR_cr_a
- attribute \src "libresoc.v:203165.17-203165.91"
- wire $not$libresoc.v:203165$14592_Y
- attribute \src "libresoc.v:203167.18-203167.93"
- wire $not$libresoc.v:203167$14594_Y
- attribute \src "libresoc.v:203169.18-203169.93"
- wire $not$libresoc.v:203169$14596_Y
- attribute \src "libresoc.v:203170.17-203170.89"
- wire width 6 $not$libresoc.v:203170$14597_Y
- attribute \src "libresoc.v:203172.18-203172.93"
- wire $not$libresoc.v:203172$14599_Y
- attribute \src "libresoc.v:203175.17-203175.91"
- wire $not$libresoc.v:203175$14602_Y
- attribute \src "libresoc.v:203166.18-203166.106"
- wire $reduce_or$libresoc.v:203166$14593_Y
- attribute \src "libresoc.v:203168.18-203168.106"
- wire $reduce_or$libresoc.v:203168$14595_Y
- attribute \src "libresoc.v:203171.18-203171.106"
- wire $reduce_or$libresoc.v:203171$14598_Y
- attribute \src "libresoc.v:203173.18-203173.90"
- wire $reduce_or$libresoc.v:203173$14600_Y
- attribute \src "libresoc.v:203174.17-203174.103"
- wire $reduce_or$libresoc.v:203174$14601_Y
- attribute \src "libresoc.v:203176.17-203176.105"
- wire $reduce_or$libresoc.v:203176$14603_Y
+ attribute \src "libresoc.v:202109.17-202109.91"
+ wire $not$libresoc.v:202109$14404_Y
+ attribute \src "libresoc.v:202111.18-202111.93"
+ wire $not$libresoc.v:202111$14406_Y
+ attribute \src "libresoc.v:202113.18-202113.93"
+ wire $not$libresoc.v:202113$14408_Y
+ attribute \src "libresoc.v:202114.17-202114.89"
+ wire width 6 $not$libresoc.v:202114$14409_Y
+ attribute \src "libresoc.v:202116.18-202116.93"
+ wire $not$libresoc.v:202116$14411_Y
+ attribute \src "libresoc.v:202119.17-202119.91"
+ wire $not$libresoc.v:202119$14414_Y
+ attribute \src "libresoc.v:202110.18-202110.106"
+ wire $reduce_or$libresoc.v:202110$14405_Y
+ attribute \src "libresoc.v:202112.18-202112.106"
+ wire $reduce_or$libresoc.v:202112$14407_Y
+ attribute \src "libresoc.v:202115.18-202115.106"
+ wire $reduce_or$libresoc.v:202115$14410_Y
+ attribute \src "libresoc.v:202117.18-202117.90"
+ wire $reduce_or$libresoc.v:202117$14412_Y
+ attribute \src "libresoc.v:202118.17-202118.103"
+ wire $reduce_or$libresoc.v:202118$14413_Y
+ attribute \src "libresoc.v:202120.17-202120.105"
+ wire $reduce_or$libresoc.v:202120$14415_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203165$14592
+ cell $not $not$libresoc.v:202109$14404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203165$14592_Y
+ connect \Y $not$libresoc.v:202109$14404_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203167$14594
+ cell $not $not$libresoc.v:202111$14406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:203167$14594_Y
+ connect \Y $not$libresoc.v:202111$14406_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203169$14596
+ cell $not $not$libresoc.v:202113$14408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:203169$14596_Y
+ connect \Y $not$libresoc.v:202113$14408_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203170$14597
+ cell $not $not$libresoc.v:202114$14409
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \i
- connect \Y $not$libresoc.v:203170$14597_Y
+ connect \Y $not$libresoc.v:202114$14409_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203172$14599
+ cell $not $not$libresoc.v:202116$14411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:203172$14599_Y
+ connect \Y $not$libresoc.v:202116$14411_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203175$14602
+ cell $not $not$libresoc.v:202119$14414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203175$14602_Y
+ connect \Y $not$libresoc.v:202119$14414_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203166$14593
+ cell $reduce_or $reduce_or$libresoc.v:202110$14405
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:203166$14593_Y
+ connect \Y $reduce_or$libresoc.v:202110$14405_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203168$14595
+ cell $reduce_or $reduce_or$libresoc.v:202112$14407
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:203168$14595_Y
+ connect \Y $reduce_or$libresoc.v:202112$14407_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203171$14598
+ cell $reduce_or $reduce_or$libresoc.v:202115$14410
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:203171$14598_Y
+ connect \Y $reduce_or$libresoc.v:202115$14410_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203173$14600
+ cell $reduce_or $reduce_or$libresoc.v:202117$14412
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203173$14600_Y
+ connect \Y $reduce_or$libresoc.v:202117$14412_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203174$14601
+ cell $reduce_or $reduce_or$libresoc.v:202118$14413
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203174$14601_Y
+ connect \Y $reduce_or$libresoc.v:202118$14413_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203176$14603
+ cell $reduce_or $reduce_or$libresoc.v:202120$14415
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203176$14603_Y
- end
- connect \$7 $not$libresoc.v:203165$14592_Y
- connect \$12 $reduce_or$libresoc.v:203166$14593_Y
- connect \$11 $not$libresoc.v:203167$14594_Y
- connect \$16 $reduce_or$libresoc.v:203168$14595_Y
- connect \$15 $not$libresoc.v:203169$14596_Y
- connect \$1 $not$libresoc.v:203170$14597_Y
- connect \$20 $reduce_or$libresoc.v:203171$14598_Y
- connect \$19 $not$libresoc.v:203172$14599_Y
- connect \$23 $reduce_or$libresoc.v:203173$14600_Y
- connect \$4 $reduce_or$libresoc.v:203174$14601_Y
- connect \$3 $not$libresoc.v:203175$14602_Y
- connect \$8 $reduce_or$libresoc.v:203176$14603_Y
+ connect \Y $reduce_or$libresoc.v:202120$14415_Y
+ end
+ connect \$7 $not$libresoc.v:202109$14404_Y
+ connect \$12 $reduce_or$libresoc.v:202110$14405_Y
+ connect \$11 $not$libresoc.v:202111$14406_Y
+ connect \$16 $reduce_or$libresoc.v:202112$14407_Y
+ connect \$15 $not$libresoc.v:202113$14408_Y
+ connect \$1 $not$libresoc.v:202114$14409_Y
+ connect \$20 $reduce_or$libresoc.v:202115$14410_Y
+ connect \$19 $not$libresoc.v:202116$14411_Y
+ connect \$23 $reduce_or$libresoc.v:202117$14412_Y
+ connect \$4 $reduce_or$libresoc.v:202118$14413_Y
+ connect \$3 $not$libresoc.v:202119$14414_Y
+ connect \$8 $reduce_or$libresoc.v:202120$14415_Y
connect \en_o \$23
connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t5 \$19
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203190.1-203211.10"
+attribute \src "libresoc.v:202134.1-202155.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr"
attribute \generator "nMigen"
module \wrpick_CR_full_cr
- attribute \src "libresoc.v:203205.17-203205.89"
- wire $not$libresoc.v:203205$14604_Y
- attribute \src "libresoc.v:203206.17-203206.89"
- wire $reduce_or$libresoc.v:203206$14605_Y
+ attribute \src "libresoc.v:202149.17-202149.89"
+ wire $not$libresoc.v:202149$14416_Y
+ attribute \src "libresoc.v:202150.17-202150.89"
+ wire $reduce_or$libresoc.v:202150$14417_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203205$14604
+ cell $not $not$libresoc.v:202149$14416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:203205$14604_Y
+ connect \Y $not$libresoc.v:202149$14416_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203206$14605
+ cell $reduce_or $reduce_or$libresoc.v:202150$14417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203206$14605_Y
+ connect \Y $reduce_or$libresoc.v:202150$14417_Y
end
- connect \$1 $not$libresoc.v:203205$14604_Y
- connect \$3 $reduce_or$libresoc.v:203206$14605_Y
+ connect \$1 $not$libresoc.v:202149$14416_Y
+ connect \$3 $reduce_or$libresoc.v:202150$14417_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:203215.1-203272.10"
+attribute \src "libresoc.v:202159.1-202216.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1"
attribute \generator "nMigen"
module \wrpick_FAST_fast1
- attribute \src "libresoc.v:203254.17-203254.91"
- wire $not$libresoc.v:203254$14606_Y
- attribute \src "libresoc.v:203256.18-203256.93"
- wire $not$libresoc.v:203256$14608_Y
- attribute \src "libresoc.v:203258.18-203258.93"
- wire $not$libresoc.v:203258$14610_Y
- attribute \src "libresoc.v:203259.17-203259.89"
- wire width 5 $not$libresoc.v:203259$14611_Y
- attribute \src "libresoc.v:203262.17-203262.91"
- wire $not$libresoc.v:203262$14614_Y
- attribute \src "libresoc.v:203255.18-203255.106"
- wire $reduce_or$libresoc.v:203255$14607_Y
- attribute \src "libresoc.v:203257.18-203257.106"
- wire $reduce_or$libresoc.v:203257$14609_Y
- attribute \src "libresoc.v:203260.18-203260.90"
- wire $reduce_or$libresoc.v:203260$14612_Y
- attribute \src "libresoc.v:203261.17-203261.103"
- wire $reduce_or$libresoc.v:203261$14613_Y
- attribute \src "libresoc.v:203263.17-203263.105"
- wire $reduce_or$libresoc.v:203263$14615_Y
+ attribute \src "libresoc.v:202198.17-202198.91"
+ wire $not$libresoc.v:202198$14418_Y
+ attribute \src "libresoc.v:202200.18-202200.93"
+ wire $not$libresoc.v:202200$14420_Y
+ attribute \src "libresoc.v:202202.18-202202.93"
+ wire $not$libresoc.v:202202$14422_Y
+ attribute \src "libresoc.v:202203.17-202203.89"
+ wire width 5 $not$libresoc.v:202203$14423_Y
+ attribute \src "libresoc.v:202206.17-202206.91"
+ wire $not$libresoc.v:202206$14426_Y
+ attribute \src "libresoc.v:202199.18-202199.106"
+ wire $reduce_or$libresoc.v:202199$14419_Y
+ attribute \src "libresoc.v:202201.18-202201.106"
+ wire $reduce_or$libresoc.v:202201$14421_Y
+ attribute \src "libresoc.v:202204.18-202204.90"
+ wire $reduce_or$libresoc.v:202204$14424_Y
+ attribute \src "libresoc.v:202205.17-202205.103"
+ wire $reduce_or$libresoc.v:202205$14425_Y
+ attribute \src "libresoc.v:202207.17-202207.105"
+ wire $reduce_or$libresoc.v:202207$14427_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203254$14606
+ cell $not $not$libresoc.v:202198$14418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203254$14606_Y
+ connect \Y $not$libresoc.v:202198$14418_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203256$14608
+ cell $not $not$libresoc.v:202200$14420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:203256$14608_Y
+ connect \Y $not$libresoc.v:202200$14420_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203258$14610
+ cell $not $not$libresoc.v:202202$14422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:203258$14610_Y
+ connect \Y $not$libresoc.v:202202$14422_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203259$14611
+ cell $not $not$libresoc.v:202203$14423
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \i
- connect \Y $not$libresoc.v:203259$14611_Y
+ connect \Y $not$libresoc.v:202203$14423_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203262$14614
+ cell $not $not$libresoc.v:202206$14426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203262$14614_Y
+ connect \Y $not$libresoc.v:202206$14426_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203255$14607
+ cell $reduce_or $reduce_or$libresoc.v:202199$14419
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:203255$14607_Y
+ connect \Y $reduce_or$libresoc.v:202199$14419_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203257$14609
+ cell $reduce_or $reduce_or$libresoc.v:202201$14421
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:203257$14609_Y
+ connect \Y $reduce_or$libresoc.v:202201$14421_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203260$14612
+ cell $reduce_or $reduce_or$libresoc.v:202204$14424
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203260$14612_Y
+ connect \Y $reduce_or$libresoc.v:202204$14424_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203261$14613
+ cell $reduce_or $reduce_or$libresoc.v:202205$14425
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203261$14613_Y
+ connect \Y $reduce_or$libresoc.v:202205$14425_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203263$14615
+ cell $reduce_or $reduce_or$libresoc.v:202207$14427
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203263$14615_Y
- end
- connect \$7 $not$libresoc.v:203254$14606_Y
- connect \$12 $reduce_or$libresoc.v:203255$14607_Y
- connect \$11 $not$libresoc.v:203256$14608_Y
- connect \$16 $reduce_or$libresoc.v:203257$14609_Y
- connect \$15 $not$libresoc.v:203258$14610_Y
- connect \$1 $not$libresoc.v:203259$14611_Y
- connect \$19 $reduce_or$libresoc.v:203260$14612_Y
- connect \$4 $reduce_or$libresoc.v:203261$14613_Y
- connect \$3 $not$libresoc.v:203262$14614_Y
- connect \$8 $reduce_or$libresoc.v:203263$14615_Y
+ connect \Y $reduce_or$libresoc.v:202207$14427_Y
+ end
+ connect \$7 $not$libresoc.v:202198$14418_Y
+ connect \$12 $reduce_or$libresoc.v:202199$14419_Y
+ connect \$11 $not$libresoc.v:202200$14420_Y
+ connect \$16 $reduce_or$libresoc.v:202201$14421_Y
+ connect \$15 $not$libresoc.v:202202$14422_Y
+ connect \$1 $not$libresoc.v:202203$14423_Y
+ connect \$19 $reduce_or$libresoc.v:202204$14424_Y
+ connect \$4 $reduce_or$libresoc.v:202205$14425_Y
+ connect \$3 $not$libresoc.v:202206$14426_Y
+ connect \$8 $reduce_or$libresoc.v:202207$14427_Y
connect \en_o \$19
connect \o { \t4 \t3 \t2 \t1 \t0 }
connect \t4 \$15
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203276.1-203378.10"
+attribute \src "libresoc.v:202220.1-202322.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o"
attribute \generator "nMigen"
module \wrpick_INT_o
- attribute \src "libresoc.v:203345.17-203345.91"
- wire $not$libresoc.v:203345$14616_Y
- attribute \src "libresoc.v:203347.18-203347.93"
- wire $not$libresoc.v:203347$14618_Y
- attribute \src "libresoc.v:203349.18-203349.93"
- wire $not$libresoc.v:203349$14620_Y
- attribute \src "libresoc.v:203350.17-203350.89"
- wire width 10 $not$libresoc.v:203350$14621_Y
- attribute \src "libresoc.v:203352.18-203352.93"
- wire $not$libresoc.v:203352$14623_Y
- attribute \src "libresoc.v:203354.18-203354.93"
- wire $not$libresoc.v:203354$14625_Y
- attribute \src "libresoc.v:203356.18-203356.93"
- wire $not$libresoc.v:203356$14627_Y
- attribute \src "libresoc.v:203358.18-203358.93"
- wire $not$libresoc.v:203358$14629_Y
- attribute \src "libresoc.v:203360.18-203360.93"
- wire $not$libresoc.v:203360$14631_Y
- attribute \src "libresoc.v:203363.17-203363.91"
- wire $not$libresoc.v:203363$14634_Y
- attribute \src "libresoc.v:203346.18-203346.106"
- wire $reduce_or$libresoc.v:203346$14617_Y
- attribute \src "libresoc.v:203348.18-203348.106"
- wire $reduce_or$libresoc.v:203348$14619_Y
- attribute \src "libresoc.v:203351.18-203351.106"
- wire $reduce_or$libresoc.v:203351$14622_Y
- attribute \src "libresoc.v:203353.18-203353.106"
- wire $reduce_or$libresoc.v:203353$14624_Y
- attribute \src "libresoc.v:203355.18-203355.106"
- wire $reduce_or$libresoc.v:203355$14626_Y
- attribute \src "libresoc.v:203357.18-203357.106"
- wire $reduce_or$libresoc.v:203357$14628_Y
- attribute \src "libresoc.v:203359.18-203359.106"
- wire $reduce_or$libresoc.v:203359$14630_Y
- attribute \src "libresoc.v:203361.18-203361.90"
- wire $reduce_or$libresoc.v:203361$14632_Y
- attribute \src "libresoc.v:203362.17-203362.103"
- wire $reduce_or$libresoc.v:203362$14633_Y
- attribute \src "libresoc.v:203364.17-203364.105"
- wire $reduce_or$libresoc.v:203364$14635_Y
+ attribute \src "libresoc.v:202289.17-202289.91"
+ wire $not$libresoc.v:202289$14428_Y
+ attribute \src "libresoc.v:202291.18-202291.93"
+ wire $not$libresoc.v:202291$14430_Y
+ attribute \src "libresoc.v:202293.18-202293.93"
+ wire $not$libresoc.v:202293$14432_Y
+ attribute \src "libresoc.v:202294.17-202294.89"
+ wire width 10 $not$libresoc.v:202294$14433_Y
+ attribute \src "libresoc.v:202296.18-202296.93"
+ wire $not$libresoc.v:202296$14435_Y
+ attribute \src "libresoc.v:202298.18-202298.93"
+ wire $not$libresoc.v:202298$14437_Y
+ attribute \src "libresoc.v:202300.18-202300.93"
+ wire $not$libresoc.v:202300$14439_Y
+ attribute \src "libresoc.v:202302.18-202302.93"
+ wire $not$libresoc.v:202302$14441_Y
+ attribute \src "libresoc.v:202304.18-202304.93"
+ wire $not$libresoc.v:202304$14443_Y
+ attribute \src "libresoc.v:202307.17-202307.91"
+ wire $not$libresoc.v:202307$14446_Y
+ attribute \src "libresoc.v:202290.18-202290.106"
+ wire $reduce_or$libresoc.v:202290$14429_Y
+ attribute \src "libresoc.v:202292.18-202292.106"
+ wire $reduce_or$libresoc.v:202292$14431_Y
+ attribute \src "libresoc.v:202295.18-202295.106"
+ wire $reduce_or$libresoc.v:202295$14434_Y
+ attribute \src "libresoc.v:202297.18-202297.106"
+ wire $reduce_or$libresoc.v:202297$14436_Y
+ attribute \src "libresoc.v:202299.18-202299.106"
+ wire $reduce_or$libresoc.v:202299$14438_Y
+ attribute \src "libresoc.v:202301.18-202301.106"
+ wire $reduce_or$libresoc.v:202301$14440_Y
+ attribute \src "libresoc.v:202303.18-202303.106"
+ wire $reduce_or$libresoc.v:202303$14442_Y
+ attribute \src "libresoc.v:202305.18-202305.90"
+ wire $reduce_or$libresoc.v:202305$14444_Y
+ attribute \src "libresoc.v:202306.17-202306.103"
+ wire $reduce_or$libresoc.v:202306$14445_Y
+ attribute \src "libresoc.v:202308.17-202308.105"
+ wire $reduce_or$libresoc.v:202308$14447_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 10 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203345$14616
+ cell $not $not$libresoc.v:202289$14428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203345$14616_Y
+ connect \Y $not$libresoc.v:202289$14428_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203347$14618
+ cell $not $not$libresoc.v:202291$14430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:203347$14618_Y
+ connect \Y $not$libresoc.v:202291$14430_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203349$14620
+ cell $not $not$libresoc.v:202293$14432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:203349$14620_Y
+ connect \Y $not$libresoc.v:202293$14432_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203350$14621
+ cell $not $not$libresoc.v:202294$14433
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 10
connect \A \i
- connect \Y $not$libresoc.v:203350$14621_Y
+ connect \Y $not$libresoc.v:202294$14433_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203352$14623
+ cell $not $not$libresoc.v:202296$14435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:203352$14623_Y
+ connect \Y $not$libresoc.v:202296$14435_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203354$14625
+ cell $not $not$libresoc.v:202298$14437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:203354$14625_Y
+ connect \Y $not$libresoc.v:202298$14437_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203356$14627
+ cell $not $not$libresoc.v:202300$14439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:203356$14627_Y
+ connect \Y $not$libresoc.v:202300$14439_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203358$14629
+ cell $not $not$libresoc.v:202302$14441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$32
- connect \Y $not$libresoc.v:203358$14629_Y
+ connect \Y $not$libresoc.v:202302$14441_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203360$14631
+ cell $not $not$libresoc.v:202304$14443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$36
- connect \Y $not$libresoc.v:203360$14631_Y
+ connect \Y $not$libresoc.v:202304$14443_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203363$14634
+ cell $not $not$libresoc.v:202307$14446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203363$14634_Y
+ connect \Y $not$libresoc.v:202307$14446_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203346$14617
+ cell $reduce_or $reduce_or$libresoc.v:202290$14429
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:203346$14617_Y
+ connect \Y $reduce_or$libresoc.v:202290$14429_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203348$14619
+ cell $reduce_or $reduce_or$libresoc.v:202292$14431
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:203348$14619_Y
+ connect \Y $reduce_or$libresoc.v:202292$14431_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203351$14622
+ cell $reduce_or $reduce_or$libresoc.v:202295$14434
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:203351$14622_Y
+ connect \Y $reduce_or$libresoc.v:202295$14434_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203353$14624
+ cell $reduce_or $reduce_or$libresoc.v:202297$14436
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:203353$14624_Y
+ connect \Y $reduce_or$libresoc.v:202297$14436_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203355$14626
+ cell $reduce_or $reduce_or$libresoc.v:202299$14438
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:203355$14626_Y
+ connect \Y $reduce_or$libresoc.v:202299$14438_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203357$14628
+ cell $reduce_or $reduce_or$libresoc.v:202301$14440
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 1
connect \A { \i [7:0] \ni [8] }
- connect \Y $reduce_or$libresoc.v:203357$14628_Y
+ connect \Y $reduce_or$libresoc.v:202301$14440_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203359$14630
+ cell $reduce_or $reduce_or$libresoc.v:202303$14442
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A { \i [8:0] \ni [9] }
- connect \Y $reduce_or$libresoc.v:203359$14630_Y
+ connect \Y $reduce_or$libresoc.v:202303$14442_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203361$14632
+ cell $reduce_or $reduce_or$libresoc.v:202305$14444
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203361$14632_Y
+ connect \Y $reduce_or$libresoc.v:202305$14444_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203362$14633
+ cell $reduce_or $reduce_or$libresoc.v:202306$14445
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203362$14633_Y
+ connect \Y $reduce_or$libresoc.v:202306$14445_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203364$14635
+ cell $reduce_or $reduce_or$libresoc.v:202308$14447
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203364$14635_Y
- end
- connect \$7 $not$libresoc.v:203345$14616_Y
- connect \$12 $reduce_or$libresoc.v:203346$14617_Y
- connect \$11 $not$libresoc.v:203347$14618_Y
- connect \$16 $reduce_or$libresoc.v:203348$14619_Y
- connect \$15 $not$libresoc.v:203349$14620_Y
- connect \$1 $not$libresoc.v:203350$14621_Y
- connect \$20 $reduce_or$libresoc.v:203351$14622_Y
- connect \$19 $not$libresoc.v:203352$14623_Y
- connect \$24 $reduce_or$libresoc.v:203353$14624_Y
- connect \$23 $not$libresoc.v:203354$14625_Y
- connect \$28 $reduce_or$libresoc.v:203355$14626_Y
- connect \$27 $not$libresoc.v:203356$14627_Y
- connect \$32 $reduce_or$libresoc.v:203357$14628_Y
- connect \$31 $not$libresoc.v:203358$14629_Y
- connect \$36 $reduce_or$libresoc.v:203359$14630_Y
- connect \$35 $not$libresoc.v:203360$14631_Y
- connect \$39 $reduce_or$libresoc.v:203361$14632_Y
- connect \$4 $reduce_or$libresoc.v:203362$14633_Y
- connect \$3 $not$libresoc.v:203363$14634_Y
- connect \$8 $reduce_or$libresoc.v:203364$14635_Y
+ connect \Y $reduce_or$libresoc.v:202308$14447_Y
+ end
+ connect \$7 $not$libresoc.v:202289$14428_Y
+ connect \$12 $reduce_or$libresoc.v:202290$14429_Y
+ connect \$11 $not$libresoc.v:202291$14430_Y
+ connect \$16 $reduce_or$libresoc.v:202292$14431_Y
+ connect \$15 $not$libresoc.v:202293$14432_Y
+ connect \$1 $not$libresoc.v:202294$14433_Y
+ connect \$20 $reduce_or$libresoc.v:202295$14434_Y
+ connect \$19 $not$libresoc.v:202296$14435_Y
+ connect \$24 $reduce_or$libresoc.v:202297$14436_Y
+ connect \$23 $not$libresoc.v:202298$14437_Y
+ connect \$28 $reduce_or$libresoc.v:202299$14438_Y
+ connect \$27 $not$libresoc.v:202300$14439_Y
+ connect \$32 $reduce_or$libresoc.v:202301$14440_Y
+ connect \$31 $not$libresoc.v:202302$14441_Y
+ connect \$36 $reduce_or$libresoc.v:202303$14442_Y
+ connect \$35 $not$libresoc.v:202304$14443_Y
+ connect \$39 $reduce_or$libresoc.v:202305$14444_Y
+ connect \$4 $reduce_or$libresoc.v:202306$14445_Y
+ connect \$3 $not$libresoc.v:202307$14446_Y
+ connect \$8 $reduce_or$libresoc.v:202308$14447_Y
connect \en_o \$39
connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t9 \$35
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203382.1-203403.10"
+attribute \src "libresoc.v:202326.1-202347.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1"
attribute \generator "nMigen"
module \wrpick_SPR_spr1
- attribute \src "libresoc.v:203397.17-203397.89"
- wire $not$libresoc.v:203397$14636_Y
- attribute \src "libresoc.v:203398.17-203398.89"
- wire $reduce_or$libresoc.v:203398$14637_Y
+ attribute \src "libresoc.v:202341.17-202341.89"
+ wire $not$libresoc.v:202341$14448_Y
+ attribute \src "libresoc.v:202342.17-202342.89"
+ wire $reduce_or$libresoc.v:202342$14449_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203397$14636
+ cell $not $not$libresoc.v:202341$14448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:203397$14636_Y
+ connect \Y $not$libresoc.v:202341$14448_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203398$14637
+ cell $reduce_or $reduce_or$libresoc.v:202342$14449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203398$14637_Y
+ connect \Y $reduce_or$libresoc.v:202342$14449_Y
end
- connect \$1 $not$libresoc.v:203397$14636_Y
- connect \$3 $reduce_or$libresoc.v:203398$14637_Y
+ connect \$1 $not$libresoc.v:202341$14448_Y
+ connect \$3 $reduce_or$libresoc.v:202342$14449_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:203407.1-203428.10"
+attribute \src "libresoc.v:202351.1-202372.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr"
attribute \generator "nMigen"
module \wrpick_STATE_msr
- attribute \src "libresoc.v:203422.17-203422.89"
- wire $not$libresoc.v:203422$14638_Y
- attribute \src "libresoc.v:203423.17-203423.89"
- wire $reduce_or$libresoc.v:203423$14639_Y
+ attribute \src "libresoc.v:202366.17-202366.89"
+ wire $not$libresoc.v:202366$14450_Y
+ attribute \src "libresoc.v:202367.17-202367.89"
+ wire $reduce_or$libresoc.v:202367$14451_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203422$14638
+ cell $not $not$libresoc.v:202366$14450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:203422$14638_Y
+ connect \Y $not$libresoc.v:202366$14450_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203423$14639
+ cell $reduce_or $reduce_or$libresoc.v:202367$14451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203423$14639_Y
+ connect \Y $reduce_or$libresoc.v:202367$14451_Y
end
- connect \$1 $not$libresoc.v:203422$14638_Y
- connect \$3 $reduce_or$libresoc.v:203423$14639_Y
+ connect \$1 $not$libresoc.v:202366$14450_Y
+ connect \$3 $reduce_or$libresoc.v:202367$14451_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:203432.1-203462.10"
+attribute \src "libresoc.v:202376.1-202406.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia"
attribute \generator "nMigen"
module \wrpick_STATE_nia
- attribute \src "libresoc.v:203453.17-203453.89"
- wire width 2 $not$libresoc.v:203453$14640_Y
- attribute \src "libresoc.v:203455.17-203455.91"
- wire $not$libresoc.v:203455$14642_Y
- attribute \src "libresoc.v:203454.17-203454.103"
- wire $reduce_or$libresoc.v:203454$14641_Y
- attribute \src "libresoc.v:203456.17-203456.89"
- wire $reduce_or$libresoc.v:203456$14643_Y
+ attribute \src "libresoc.v:202397.17-202397.89"
+ wire width 2 $not$libresoc.v:202397$14452_Y
+ attribute \src "libresoc.v:202399.17-202399.91"
+ wire $not$libresoc.v:202399$14454_Y
+ attribute \src "libresoc.v:202398.17-202398.103"
+ wire $reduce_or$libresoc.v:202398$14453_Y
+ attribute \src "libresoc.v:202400.17-202400.89"
+ wire $reduce_or$libresoc.v:202400$14455_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203453$14640
+ cell $not $not$libresoc.v:202397$14452
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:203453$14640_Y
+ connect \Y $not$libresoc.v:202397$14452_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203455$14642
+ cell $not $not$libresoc.v:202399$14454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203455$14642_Y
+ connect \Y $not$libresoc.v:202399$14454_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203454$14641
+ cell $reduce_or $reduce_or$libresoc.v:202398$14453
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203454$14641_Y
+ connect \Y $reduce_or$libresoc.v:202398$14453_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203456$14643
+ cell $reduce_or $reduce_or$libresoc.v:202400$14455
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203456$14643_Y
+ connect \Y $reduce_or$libresoc.v:202400$14455_Y
end
- connect \$1 $not$libresoc.v:203453$14640_Y
- connect \$4 $reduce_or$libresoc.v:203454$14641_Y
- connect \$3 $not$libresoc.v:203455$14642_Y
- connect \$7 $reduce_or$libresoc.v:203456$14643_Y
+ connect \$1 $not$libresoc.v:202397$14452_Y
+ connect \$4 $reduce_or$libresoc.v:202398$14453_Y
+ connect \$3 $not$libresoc.v:202399$14454_Y
+ connect \$7 $reduce_or$libresoc.v:202400$14455_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203466.1-203505.10"
+attribute \src "libresoc.v:202410.1-202449.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca"
attribute \generator "nMigen"
module \wrpick_XER_xer_ca
- attribute \src "libresoc.v:203493.17-203493.91"
- wire $not$libresoc.v:203493$14644_Y
- attribute \src "libresoc.v:203495.17-203495.89"
- wire width 3 $not$libresoc.v:203495$14646_Y
- attribute \src "libresoc.v:203497.17-203497.91"
- wire $not$libresoc.v:203497$14648_Y
- attribute \src "libresoc.v:203494.18-203494.90"
- wire $reduce_or$libresoc.v:203494$14645_Y
- attribute \src "libresoc.v:203496.17-203496.103"
- wire $reduce_or$libresoc.v:203496$14647_Y
- attribute \src "libresoc.v:203498.17-203498.105"
- wire $reduce_or$libresoc.v:203498$14649_Y
+ attribute \src "libresoc.v:202437.17-202437.91"
+ wire $not$libresoc.v:202437$14456_Y
+ attribute \src "libresoc.v:202439.17-202439.89"
+ wire width 3 $not$libresoc.v:202439$14458_Y
+ attribute \src "libresoc.v:202441.17-202441.91"
+ wire $not$libresoc.v:202441$14460_Y
+ attribute \src "libresoc.v:202438.18-202438.90"
+ wire $reduce_or$libresoc.v:202438$14457_Y
+ attribute \src "libresoc.v:202440.17-202440.103"
+ wire $reduce_or$libresoc.v:202440$14459_Y
+ attribute \src "libresoc.v:202442.17-202442.105"
+ wire $reduce_or$libresoc.v:202442$14461_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203493$14644
+ cell $not $not$libresoc.v:202437$14456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203493$14644_Y
+ connect \Y $not$libresoc.v:202437$14456_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203495$14646
+ cell $not $not$libresoc.v:202439$14458
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:203495$14646_Y
+ connect \Y $not$libresoc.v:202439$14458_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203497$14648
+ cell $not $not$libresoc.v:202441$14460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203497$14648_Y
+ connect \Y $not$libresoc.v:202441$14460_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203494$14645
+ cell $reduce_or $reduce_or$libresoc.v:202438$14457
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203494$14645_Y
+ connect \Y $reduce_or$libresoc.v:202438$14457_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203496$14647
+ cell $reduce_or $reduce_or$libresoc.v:202440$14459
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203496$14647_Y
+ connect \Y $reduce_or$libresoc.v:202440$14459_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203498$14649
+ cell $reduce_or $reduce_or$libresoc.v:202442$14461
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203498$14649_Y
- end
- connect \$7 $not$libresoc.v:203493$14644_Y
- connect \$11 $reduce_or$libresoc.v:203494$14645_Y
- connect \$1 $not$libresoc.v:203495$14646_Y
- connect \$4 $reduce_or$libresoc.v:203496$14647_Y
- connect \$3 $not$libresoc.v:203497$14648_Y
- connect \$8 $reduce_or$libresoc.v:203498$14649_Y
+ connect \Y $reduce_or$libresoc.v:202442$14461_Y
+ end
+ connect \$7 $not$libresoc.v:202437$14456_Y
+ connect \$11 $reduce_or$libresoc.v:202438$14457_Y
+ connect \$1 $not$libresoc.v:202439$14458_Y
+ connect \$4 $reduce_or$libresoc.v:202440$14459_Y
+ connect \$3 $not$libresoc.v:202441$14460_Y
+ connect \$8 $reduce_or$libresoc.v:202442$14461_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203509.1-203557.10"
+attribute \src "libresoc.v:202453.1-202501.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov"
attribute \generator "nMigen"
module \wrpick_XER_xer_ov
- attribute \src "libresoc.v:203542.17-203542.91"
- wire $not$libresoc.v:203542$14650_Y
- attribute \src "libresoc.v:203544.18-203544.93"
- wire $not$libresoc.v:203544$14652_Y
- attribute \src "libresoc.v:203546.17-203546.89"
- wire width 4 $not$libresoc.v:203546$14654_Y
- attribute \src "libresoc.v:203548.17-203548.91"
- wire $not$libresoc.v:203548$14656_Y
- attribute \src "libresoc.v:203543.18-203543.106"
- wire $reduce_or$libresoc.v:203543$14651_Y
- attribute \src "libresoc.v:203545.18-203545.90"
- wire $reduce_or$libresoc.v:203545$14653_Y
- attribute \src "libresoc.v:203547.17-203547.103"
- wire $reduce_or$libresoc.v:203547$14655_Y
- attribute \src "libresoc.v:203549.17-203549.105"
- wire $reduce_or$libresoc.v:203549$14657_Y
+ attribute \src "libresoc.v:202486.17-202486.91"
+ wire $not$libresoc.v:202486$14462_Y
+ attribute \src "libresoc.v:202488.18-202488.93"
+ wire $not$libresoc.v:202488$14464_Y
+ attribute \src "libresoc.v:202490.17-202490.89"
+ wire width 4 $not$libresoc.v:202490$14466_Y
+ attribute \src "libresoc.v:202492.17-202492.91"
+ wire $not$libresoc.v:202492$14468_Y
+ attribute \src "libresoc.v:202487.18-202487.106"
+ wire $reduce_or$libresoc.v:202487$14463_Y
+ attribute \src "libresoc.v:202489.18-202489.90"
+ wire $reduce_or$libresoc.v:202489$14465_Y
+ attribute \src "libresoc.v:202491.17-202491.103"
+ wire $reduce_or$libresoc.v:202491$14467_Y
+ attribute \src "libresoc.v:202493.17-202493.105"
+ wire $reduce_or$libresoc.v:202493$14469_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203542$14650
+ cell $not $not$libresoc.v:202486$14462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203542$14650_Y
+ connect \Y $not$libresoc.v:202486$14462_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203544$14652
+ cell $not $not$libresoc.v:202488$14464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:203544$14652_Y
+ connect \Y $not$libresoc.v:202488$14464_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203546$14654
+ cell $not $not$libresoc.v:202490$14466
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:203546$14654_Y
+ connect \Y $not$libresoc.v:202490$14466_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203548$14656
+ cell $not $not$libresoc.v:202492$14468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203548$14656_Y
+ connect \Y $not$libresoc.v:202492$14468_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203543$14651
+ cell $reduce_or $reduce_or$libresoc.v:202487$14463
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:203543$14651_Y
+ connect \Y $reduce_or$libresoc.v:202487$14463_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203545$14653
+ cell $reduce_or $reduce_or$libresoc.v:202489$14465
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203545$14653_Y
+ connect \Y $reduce_or$libresoc.v:202489$14465_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203547$14655
+ cell $reduce_or $reduce_or$libresoc.v:202491$14467
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203547$14655_Y
+ connect \Y $reduce_or$libresoc.v:202491$14467_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203549$14657
+ cell $reduce_or $reduce_or$libresoc.v:202493$14469
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203549$14657_Y
- end
- connect \$7 $not$libresoc.v:203542$14650_Y
- connect \$12 $reduce_or$libresoc.v:203543$14651_Y
- connect \$11 $not$libresoc.v:203544$14652_Y
- connect \$15 $reduce_or$libresoc.v:203545$14653_Y
- connect \$1 $not$libresoc.v:203546$14654_Y
- connect \$4 $reduce_or$libresoc.v:203547$14655_Y
- connect \$3 $not$libresoc.v:203548$14656_Y
- connect \$8 $reduce_or$libresoc.v:203549$14657_Y
+ connect \Y $reduce_or$libresoc.v:202493$14469_Y
+ end
+ connect \$7 $not$libresoc.v:202486$14462_Y
+ connect \$12 $reduce_or$libresoc.v:202487$14463_Y
+ connect \$11 $not$libresoc.v:202488$14464_Y
+ connect \$15 $reduce_or$libresoc.v:202489$14465_Y
+ connect \$1 $not$libresoc.v:202490$14466_Y
+ connect \$4 $reduce_or$libresoc.v:202491$14467_Y
+ connect \$3 $not$libresoc.v:202492$14468_Y
+ connect \$8 $reduce_or$libresoc.v:202493$14469_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203561.1-203609.10"
+attribute \src "libresoc.v:202505.1-202553.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so"
attribute \generator "nMigen"
module \wrpick_XER_xer_so
- attribute \src "libresoc.v:203594.17-203594.91"
- wire $not$libresoc.v:203594$14658_Y
- attribute \src "libresoc.v:203596.18-203596.93"
- wire $not$libresoc.v:203596$14660_Y
- attribute \src "libresoc.v:203598.17-203598.89"
- wire width 4 $not$libresoc.v:203598$14662_Y
- attribute \src "libresoc.v:203600.17-203600.91"
- wire $not$libresoc.v:203600$14664_Y
- attribute \src "libresoc.v:203595.18-203595.106"
- wire $reduce_or$libresoc.v:203595$14659_Y
- attribute \src "libresoc.v:203597.18-203597.90"
- wire $reduce_or$libresoc.v:203597$14661_Y
- attribute \src "libresoc.v:203599.17-203599.103"
- wire $reduce_or$libresoc.v:203599$14663_Y
- attribute \src "libresoc.v:203601.17-203601.105"
- wire $reduce_or$libresoc.v:203601$14665_Y
+ attribute \src "libresoc.v:202538.17-202538.91"
+ wire $not$libresoc.v:202538$14470_Y
+ attribute \src "libresoc.v:202540.18-202540.93"
+ wire $not$libresoc.v:202540$14472_Y
+ attribute \src "libresoc.v:202542.17-202542.89"
+ wire width 4 $not$libresoc.v:202542$14474_Y
+ attribute \src "libresoc.v:202544.17-202544.91"
+ wire $not$libresoc.v:202544$14476_Y
+ attribute \src "libresoc.v:202539.18-202539.106"
+ wire $reduce_or$libresoc.v:202539$14471_Y
+ attribute \src "libresoc.v:202541.18-202541.90"
+ wire $reduce_or$libresoc.v:202541$14473_Y
+ attribute \src "libresoc.v:202543.17-202543.103"
+ wire $reduce_or$libresoc.v:202543$14475_Y
+ attribute \src "libresoc.v:202545.17-202545.105"
+ wire $reduce_or$libresoc.v:202545$14477_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203594$14658
+ cell $not $not$libresoc.v:202538$14470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:203594$14658_Y
+ connect \Y $not$libresoc.v:202538$14470_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203596$14660
+ cell $not $not$libresoc.v:202540$14472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:203596$14660_Y
+ connect \Y $not$libresoc.v:202540$14472_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:203598$14662
+ cell $not $not$libresoc.v:202542$14474
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:203598$14662_Y
+ connect \Y $not$libresoc.v:202542$14474_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:203600$14664
+ cell $not $not$libresoc.v:202544$14476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:203600$14664_Y
+ connect \Y $not$libresoc.v:202544$14476_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203595$14659
+ cell $reduce_or $reduce_or$libresoc.v:202539$14471
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:203595$14659_Y
+ connect \Y $reduce_or$libresoc.v:202539$14471_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:203597$14661
+ cell $reduce_or $reduce_or$libresoc.v:202541$14473
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:203597$14661_Y
+ connect \Y $reduce_or$libresoc.v:202541$14473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203599$14663
+ cell $reduce_or $reduce_or$libresoc.v:202543$14475
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:203599$14663_Y
+ connect \Y $reduce_or$libresoc.v:202543$14475_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:203601$14665
+ cell $reduce_or $reduce_or$libresoc.v:202545$14477
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:203601$14665_Y
- end
- connect \$7 $not$libresoc.v:203594$14658_Y
- connect \$12 $reduce_or$libresoc.v:203595$14659_Y
- connect \$11 $not$libresoc.v:203596$14660_Y
- connect \$15 $reduce_or$libresoc.v:203597$14661_Y
- connect \$1 $not$libresoc.v:203598$14662_Y
- connect \$4 $reduce_or$libresoc.v:203599$14663_Y
- connect \$3 $not$libresoc.v:203600$14664_Y
- connect \$8 $reduce_or$libresoc.v:203601$14665_Y
+ connect \Y $reduce_or$libresoc.v:202545$14477_Y
+ end
+ connect \$7 $not$libresoc.v:202538$14470_Y
+ connect \$12 $reduce_or$libresoc.v:202539$14471_Y
+ connect \$11 $not$libresoc.v:202540$14472_Y
+ connect \$15 $reduce_or$libresoc.v:202541$14473_Y
+ connect \$1 $not$libresoc.v:202542$14474_Y
+ connect \$4 $reduce_or$libresoc.v:202543$14475_Y
+ connect \$3 $not$libresoc.v:202544$14476_Y
+ connect \$8 $reduce_or$libresoc.v:202545$14477_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:203613.1-203933.10"
+attribute \src "libresoc.v:202557.1-202877.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer"
attribute \generator "nMigen"
module \xer
- attribute \src "libresoc.v:203614.7-203614.20"
+ attribute \src "libresoc.v:202558.7-202558.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:203893.3-203901.6"
- wire width 3 $0\ren_delay$11$next[2:0]$14689
- attribute \src "libresoc.v:203791.3-203792.43"
- wire width 3 $0\ren_delay$11[2:0]$14678
- attribute \src "libresoc.v:203750.13-203750.34"
- wire width 3 $0\ren_delay$11[2:0]$14695
- attribute \src "libresoc.v:203855.3-203863.6"
- wire width 3 $0\ren_delay$18$next[2:0]$14681
- attribute \src "libresoc.v:203789.3-203790.43"
- wire width 3 $0\ren_delay$18[2:0]$14676
- attribute \src "libresoc.v:203754.13-203754.34"
- wire width 3 $0\ren_delay$18[2:0]$14697
- attribute \src "libresoc.v:203874.3-203882.6"
- wire width 3 $0\ren_delay$next[2:0]$14685
- attribute \src "libresoc.v:203793.3-203794.35"
+ attribute \src "libresoc.v:202837.3-202845.6"
+ wire width 3 $0\ren_delay$11$next[2:0]$14501
+ attribute \src "libresoc.v:202735.3-202736.43"
+ wire width 3 $0\ren_delay$11[2:0]$14490
+ attribute \src "libresoc.v:202694.13-202694.34"
+ wire width 3 $0\ren_delay$11[2:0]$14507
+ attribute \src "libresoc.v:202799.3-202807.6"
+ wire width 3 $0\ren_delay$18$next[2:0]$14493
+ attribute \src "libresoc.v:202733.3-202734.43"
+ wire width 3 $0\ren_delay$18[2:0]$14488
+ attribute \src "libresoc.v:202698.13-202698.34"
+ wire width 3 $0\ren_delay$18[2:0]$14509
+ attribute \src "libresoc.v:202818.3-202826.6"
+ wire width 3 $0\ren_delay$next[2:0]$14497
+ attribute \src "libresoc.v:202737.3-202738.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:203883.3-203892.6"
+ attribute \src "libresoc.v:202827.3-202836.6"
wire width 2 $0\src1__data_o[1:0]
- attribute \src "libresoc.v:203902.3-203911.6"
+ attribute \src "libresoc.v:202846.3-202855.6"
wire width 2 $0\src2__data_o[1:0]
- attribute \src "libresoc.v:203864.3-203873.6"
+ attribute \src "libresoc.v:202808.3-202817.6"
wire width 2 $0\src3__data_o[1:0]
- attribute \src "libresoc.v:203893.3-203901.6"
- wire width 3 $1\ren_delay$11$next[2:0]$14690
- attribute \src "libresoc.v:203855.3-203863.6"
- wire width 3 $1\ren_delay$18$next[2:0]$14682
- attribute \src "libresoc.v:203874.3-203882.6"
- wire width 3 $1\ren_delay$next[2:0]$14686
- attribute \src "libresoc.v:203748.13-203748.29"
+ attribute \src "libresoc.v:202837.3-202845.6"
+ wire width 3 $1\ren_delay$11$next[2:0]$14502
+ attribute \src "libresoc.v:202799.3-202807.6"
+ wire width 3 $1\ren_delay$18$next[2:0]$14494
+ attribute \src "libresoc.v:202818.3-202826.6"
+ wire width 3 $1\ren_delay$next[2:0]$14498
+ attribute \src "libresoc.v:202692.13-202692.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:203883.3-203892.6"
+ attribute \src "libresoc.v:202827.3-202836.6"
wire width 2 $1\src1__data_o[1:0]
- attribute \src "libresoc.v:203902.3-203911.6"
+ attribute \src "libresoc.v:202846.3-202855.6"
wire width 2 $1\src2__data_o[1:0]
- attribute \src "libresoc.v:203864.3-203873.6"
+ attribute \src "libresoc.v:202808.3-202817.6"
wire width 2 $1\src3__data_o[1:0]
- attribute \src "libresoc.v:203780.17-203780.109"
- wire width 2 $or$libresoc.v:203780$14666_Y
- attribute \src "libresoc.v:203782.18-203782.126"
- wire width 2 $or$libresoc.v:203782$14668_Y
- attribute \src "libresoc.v:203783.18-203783.111"
- wire width 2 $or$libresoc.v:203783$14669_Y
- attribute \src "libresoc.v:203785.18-203785.126"
- wire width 2 $or$libresoc.v:203785$14671_Y
- attribute \src "libresoc.v:203786.18-203786.111"
- wire width 2 $or$libresoc.v:203786$14672_Y
- attribute \src "libresoc.v:203788.17-203788.125"
- wire width 2 $or$libresoc.v:203788$14674_Y
- attribute \src "libresoc.v:203781.18-203781.100"
- wire $reduce_or$libresoc.v:203781$14667_Y
- attribute \src "libresoc.v:203784.18-203784.100"
- wire $reduce_or$libresoc.v:203784$14670_Y
- attribute \src "libresoc.v:203787.17-203787.95"
- wire $reduce_or$libresoc.v:203787$14673_Y
+ attribute \src "libresoc.v:202724.17-202724.109"
+ wire width 2 $or$libresoc.v:202724$14478_Y
+ attribute \src "libresoc.v:202726.18-202726.126"
+ wire width 2 $or$libresoc.v:202726$14480_Y
+ attribute \src "libresoc.v:202727.18-202727.111"
+ wire width 2 $or$libresoc.v:202727$14481_Y
+ attribute \src "libresoc.v:202729.18-202729.126"
+ wire width 2 $or$libresoc.v:202729$14483_Y
+ attribute \src "libresoc.v:202730.18-202730.111"
+ wire width 2 $or$libresoc.v:202730$14484_Y
+ attribute \src "libresoc.v:202732.17-202732.125"
+ wire width 2 $or$libresoc.v:202732$14486_Y
+ attribute \src "libresoc.v:202725.18-202725.100"
+ wire $reduce_or$libresoc.v:202725$14479_Y
+ attribute \src "libresoc.v:202728.18-202728.100"
+ wire $reduce_or$libresoc.v:202728$14482_Y
+ attribute \src "libresoc.v:202731.17-202731.95"
+ wire $reduce_or$libresoc.v:202731$14485_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$12
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 10 \data_i
wire width 6 \full_wr__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \full_wr__wen
- attribute \src "libresoc.v:203614.7-203614.15"
+ attribute \src "libresoc.v:202558.7-202558.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 \reg_0_dest10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:203780$14666
+ cell $or $or$libresoc.v:202724$14478
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src10__data_o
connect \B \$7
- connect \Y $or$libresoc.v:203780$14666_Y
+ connect \Y $or$libresoc.v:202724$14478_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:203782$14668
+ cell $or $or$libresoc.v:202726$14480
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src21__data_o
connect \B \reg_2_src22__data_o
- connect \Y $or$libresoc.v:203782$14668_Y
+ connect \Y $or$libresoc.v:202726$14480_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:203783$14669
+ cell $or $or$libresoc.v:202727$14481
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src20__data_o
connect \B \$14
- connect \Y $or$libresoc.v:203783$14669_Y
+ connect \Y $or$libresoc.v:202727$14481_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:203785$14671
+ cell $or $or$libresoc.v:202729$14483
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src31__data_o
connect \B \reg_2_src32__data_o
- connect \Y $or$libresoc.v:203785$14671_Y
+ connect \Y $or$libresoc.v:202729$14483_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:203786$14672
+ cell $or $or$libresoc.v:202730$14484
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src30__data_o
connect \B \$21
- connect \Y $or$libresoc.v:203786$14672_Y
+ connect \Y $or$libresoc.v:202730$14484_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:203788$14674
+ cell $or $or$libresoc.v:202732$14486
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src11__data_o
connect \B \reg_2_src12__data_o
- connect \Y $or$libresoc.v:203788$14674_Y
+ connect \Y $or$libresoc.v:202732$14486_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:203781$14667
+ cell $reduce_or $reduce_or$libresoc.v:202725$14479
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$11
- connect \Y $reduce_or$libresoc.v:203781$14667_Y
+ connect \Y $reduce_or$libresoc.v:202725$14479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:203784$14670
+ cell $reduce_or $reduce_or$libresoc.v:202728$14482
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$18
- connect \Y $reduce_or$libresoc.v:203784$14670_Y
+ connect \Y $reduce_or$libresoc.v:202728$14482_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:203787$14673
+ cell $reduce_or $reduce_or$libresoc.v:202731$14485
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:203787$14673_Y
+ connect \Y $reduce_or$libresoc.v:202731$14485_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:203795.15-203814.4"
+ attribute \src "libresoc.v:202739.15-202758.4"
cell \reg_0$132 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w0__wen \reg_0_w0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:203815.15-203834.4"
+ attribute \src "libresoc.v:202759.15-202778.4"
cell \reg_1$133 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w1__wen \reg_1_w1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:203835.15-203854.4"
+ attribute \src "libresoc.v:202779.15-202798.4"
cell \reg_2$134 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w2__data_i \reg_2_w2__data_i
connect \w2__wen \reg_2_w2__wen
end
- attribute \src "libresoc.v:203614.7-203614.20"
- process $proc$libresoc.v:203614$14692
+ attribute \src "libresoc.v:202558.7-202558.20"
+ process $proc$libresoc.v:202558$14504
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:203748.13-203748.29"
- process $proc$libresoc.v:203748$14693
+ attribute \src "libresoc.v:202692.13-202692.29"
+ process $proc$libresoc.v:202692$14505
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:203750.13-203750.34"
- process $proc$libresoc.v:203750$14694
+ attribute \src "libresoc.v:202694.13-202694.34"
+ process $proc$libresoc.v:202694$14506
assign { } { }
- assign $0\ren_delay$11[2:0]$14695 3'000
+ assign $0\ren_delay$11[2:0]$14507 3'000
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[2:0]$14695
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14507
end
- attribute \src "libresoc.v:203754.13-203754.34"
- process $proc$libresoc.v:203754$14696
+ attribute \src "libresoc.v:202698.13-202698.34"
+ process $proc$libresoc.v:202698$14508
assign { } { }
- assign $0\ren_delay$18[2:0]$14697 3'000
+ assign $0\ren_delay$18[2:0]$14509 3'000
sync always
sync init
- update \ren_delay$18 $0\ren_delay$18[2:0]$14697
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14509
end
- attribute \src "libresoc.v:203789.3-203790.43"
- process $proc$libresoc.v:203789$14675
+ attribute \src "libresoc.v:202733.3-202734.43"
+ process $proc$libresoc.v:202733$14487
assign { } { }
- assign $0\ren_delay$18[2:0]$14676 \ren_delay$18$next
+ assign $0\ren_delay$18[2:0]$14488 \ren_delay$18$next
sync posedge \coresync_clk
- update \ren_delay$18 $0\ren_delay$18[2:0]$14676
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14488
end
- attribute \src "libresoc.v:203791.3-203792.43"
- process $proc$libresoc.v:203791$14677
+ attribute \src "libresoc.v:202735.3-202736.43"
+ process $proc$libresoc.v:202735$14489
assign { } { }
- assign $0\ren_delay$11[2:0]$14678 \ren_delay$11$next
+ assign $0\ren_delay$11[2:0]$14490 \ren_delay$11$next
sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[2:0]$14678
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14490
end
- attribute \src "libresoc.v:203793.3-203794.35"
- process $proc$libresoc.v:203793$14679
+ attribute \src "libresoc.v:202737.3-202738.35"
+ process $proc$libresoc.v:202737$14491
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:203855.3-203863.6"
- process $proc$libresoc.v:203855$14680
+ attribute \src "libresoc.v:202799.3-202807.6"
+ process $proc$libresoc.v:202799$14492
assign { } { }
assign { } { }
- assign $0\ren_delay$18$next[2:0]$14681 $1\ren_delay$18$next[2:0]$14682
- attribute \src "libresoc.v:203856.5-203856.29"
+ assign $0\ren_delay$18$next[2:0]$14493 $1\ren_delay$18$next[2:0]$14494
+ attribute \src "libresoc.v:202800.5-202800.29"
switch \initial
- attribute \src "libresoc.v:203856.9-203856.17"
+ attribute \src "libresoc.v:202800.9-202800.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$18$next[2:0]$14682 3'000
+ assign $1\ren_delay$18$next[2:0]$14494 3'000
case
- assign $1\ren_delay$18$next[2:0]$14682 \src3__ren
+ assign $1\ren_delay$18$next[2:0]$14494 \src3__ren
end
sync always
- update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14681
+ update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14493
end
- attribute \src "libresoc.v:203864.3-203873.6"
- process $proc$libresoc.v:203864$14683
+ attribute \src "libresoc.v:202808.3-202817.6"
+ process $proc$libresoc.v:202808$14495
assign { } { }
assign { } { }
assign $0\src3__data_o[1:0] $1\src3__data_o[1:0]
- attribute \src "libresoc.v:203865.5-203865.29"
+ attribute \src "libresoc.v:202809.5-202809.29"
switch \initial
- attribute \src "libresoc.v:203865.9-203865.17"
+ attribute \src "libresoc.v:202809.9-202809.17"
case 1'1
case
end
sync always
update \src3__data_o $0\src3__data_o[1:0]
end
- attribute \src "libresoc.v:203874.3-203882.6"
- process $proc$libresoc.v:203874$14684
+ attribute \src "libresoc.v:202818.3-202826.6"
+ process $proc$libresoc.v:202818$14496
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$14685 $1\ren_delay$next[2:0]$14686
- attribute \src "libresoc.v:203875.5-203875.29"
+ assign $0\ren_delay$next[2:0]$14497 $1\ren_delay$next[2:0]$14498
+ attribute \src "libresoc.v:202819.5-202819.29"
switch \initial
- attribute \src "libresoc.v:203875.9-203875.17"
+ attribute \src "libresoc.v:202819.9-202819.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$14686 3'000
+ assign $1\ren_delay$next[2:0]$14498 3'000
case
- assign $1\ren_delay$next[2:0]$14686 \src1__ren
+ assign $1\ren_delay$next[2:0]$14498 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$14685
+ update \ren_delay$next $0\ren_delay$next[2:0]$14497
end
- attribute \src "libresoc.v:203883.3-203892.6"
- process $proc$libresoc.v:203883$14687
+ attribute \src "libresoc.v:202827.3-202836.6"
+ process $proc$libresoc.v:202827$14499
assign { } { }
assign { } { }
assign $0\src1__data_o[1:0] $1\src1__data_o[1:0]
- attribute \src "libresoc.v:203884.5-203884.29"
+ attribute \src "libresoc.v:202828.5-202828.29"
switch \initial
- attribute \src "libresoc.v:203884.9-203884.17"
+ attribute \src "libresoc.v:202828.9-202828.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[1:0]
end
- attribute \src "libresoc.v:203893.3-203901.6"
- process $proc$libresoc.v:203893$14688
+ attribute \src "libresoc.v:202837.3-202845.6"
+ process $proc$libresoc.v:202837$14500
assign { } { }
assign { } { }
- assign $0\ren_delay$11$next[2:0]$14689 $1\ren_delay$11$next[2:0]$14690
- attribute \src "libresoc.v:203894.5-203894.29"
+ assign $0\ren_delay$11$next[2:0]$14501 $1\ren_delay$11$next[2:0]$14502
+ attribute \src "libresoc.v:202838.5-202838.29"
switch \initial
- attribute \src "libresoc.v:203894.9-203894.17"
+ attribute \src "libresoc.v:202838.9-202838.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$11$next[2:0]$14690 3'000
+ assign $1\ren_delay$11$next[2:0]$14502 3'000
case
- assign $1\ren_delay$11$next[2:0]$14690 \src2__ren
+ assign $1\ren_delay$11$next[2:0]$14502 \src2__ren
end
sync always
- update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14689
+ update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14501
end
- attribute \src "libresoc.v:203902.3-203911.6"
- process $proc$libresoc.v:203902$14691
+ attribute \src "libresoc.v:202846.3-202855.6"
+ process $proc$libresoc.v:202846$14503
assign { } { }
assign { } { }
assign $0\src2__data_o[1:0] $1\src2__data_o[1:0]
- attribute \src "libresoc.v:203903.5-203903.29"
+ attribute \src "libresoc.v:202847.5-202847.29"
switch \initial
- attribute \src "libresoc.v:203903.9-203903.17"
+ attribute \src "libresoc.v:202847.9-202847.17"
case 1'1
case
end
sync always
update \src2__data_o $0\src2__data_o[1:0]
end
- connect \$9 $or$libresoc.v:203780$14666_Y
- connect \$12 $reduce_or$libresoc.v:203781$14667_Y
- connect \$14 $or$libresoc.v:203782$14668_Y
- connect \$16 $or$libresoc.v:203783$14669_Y
- connect \$19 $reduce_or$libresoc.v:203784$14670_Y
- connect \$21 $or$libresoc.v:203785$14671_Y
- connect \$23 $or$libresoc.v:203786$14672_Y
- connect \$5 $reduce_or$libresoc.v:203787$14673_Y
- connect \$7 $or$libresoc.v:203788$14674_Y
+ connect \$9 $or$libresoc.v:202724$14478_Y
+ connect \$12 $reduce_or$libresoc.v:202725$14479_Y
+ connect \$14 $or$libresoc.v:202726$14480_Y
+ connect \$16 $or$libresoc.v:202727$14481_Y
+ connect \$19 $reduce_or$libresoc.v:202728$14482_Y
+ connect \$21 $or$libresoc.v:202729$14483_Y
+ connect \$23 $or$libresoc.v:202730$14484_Y
+ connect \$5 $reduce_or$libresoc.v:202731$14485_Y
+ connect \$7 $or$libresoc.v:202732$14486_Y
connect \full_wr__data_i 6'000000
connect \full_wr__wen 3'000
connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000
connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
end
-attribute \src "libresoc.v:203937.1-204254.10"
+attribute \src "libresoc.v:202881.1-203198.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:204118.3-204146.6"
+ attribute \src "libresoc.v:203062.3-203090.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:204169.3-204177.6"
- wire $0\core_irq_o$next[0:0]$14733
- attribute \src "libresoc.v:204057.3-204058.37"
+ attribute \src "libresoc.v:203113.3-203121.6"
+ wire $0\core_irq_o$next[0:0]$14545
+ attribute \src "libresoc.v:203001.3-203002.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $0\cppr$10[7:0]$14737
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 8 $0\cppr$next[7:0]$14716
- attribute \src "libresoc.v:204061.3-204062.25"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $0\cppr$10[7:0]$14549
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 8 $0\cppr$next[7:0]$14528
+ attribute \src "libresoc.v:203005.3-203006.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:204178.3-204187.6"
+ attribute \src "libresoc.v:203122.3-203131.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:203938.7-203938.20"
+ attribute \src "libresoc.v:202882.7-202882.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire $0\irq$12[0:0]$14738
- attribute \src "libresoc.v:204071.3-204086.6"
- wire $0\irq$next[0:0]$14717
- attribute \src "libresoc.v:204065.3-204066.23"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire $0\irq$12[0:0]$14550
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire $0\irq$next[0:0]$14529
+ attribute \src "libresoc.v:203009.3-203010.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $0\mfrr$11[7:0]$14739
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 8 $0\mfrr$next[7:0]$14718
- attribute \src "libresoc.v:204063.3-204064.25"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $0\mfrr$11[7:0]$14551
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 8 $0\mfrr$next[7:0]$14530
+ attribute \src "libresoc.v:203007.3-203008.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:204157.3-204168.6"
+ attribute \src "libresoc.v:203101.3-203112.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:204147.3-204156.6"
+ attribute \src "libresoc.v:203091.3-203100.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire $0\wb_ack$14[0:0]$14740
- attribute \src "libresoc.v:204071.3-204086.6"
- wire $0\wb_ack$next[0:0]$14719
- attribute \src "libresoc.v:204069.3-204070.29"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire $0\wb_ack$14[0:0]$14552
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire $0\wb_ack$next[0:0]$14531
+ attribute \src "libresoc.v:203013.3-203014.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 32 $0\wb_rd_data$13[31:0]$14741
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 32 $0\wb_rd_data$next[31:0]$14720
- attribute \src "libresoc.v:204067.3-204068.37"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 32 $0\wb_rd_data$13[31:0]$14553
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 32 $0\wb_rd_data$next[31:0]$14532
+ attribute \src "libresoc.v:203011.3-203012.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:204087.3-204117.6"
+ attribute \src "libresoc.v:203031.3-203061.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 24 $0\xisr$9[23:0]$14742
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 24 $0\xisr$next[23:0]$14721
- attribute \src "libresoc.v:204059.3-204060.25"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 24 $0\xisr$9[23:0]$14554
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 24 $0\xisr$next[23:0]$14533
+ attribute \src "libresoc.v:203003.3-203004.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:204118.3-204146.6"
+ attribute \src "libresoc.v:203062.3-203090.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:204169.3-204177.6"
- wire $1\core_irq_o$next[0:0]$14734
- attribute \src "libresoc.v:203967.7-203967.24"
+ attribute \src "libresoc.v:203113.3-203121.6"
+ wire $1\core_irq_o$next[0:0]$14546
+ attribute \src "libresoc.v:202911.7-202911.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $1\cppr$10[7:0]$14743
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 8 $1\cppr$next[7:0]$14722
- attribute \src "libresoc.v:203971.13-203971.25"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $1\cppr$10[7:0]$14555
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 8 $1\cppr$next[7:0]$14534
+ attribute \src "libresoc.v:202915.13-202915.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:204178.3-204187.6"
+ attribute \src "libresoc.v:203122.3-203131.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire $1\irq$12[0:0]$14753
- attribute \src "libresoc.v:204071.3-204086.6"
- wire $1\irq$next[0:0]$14723
- attribute \src "libresoc.v:204000.7-204000.17"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire $1\irq$12[0:0]$14565
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire $1\irq$next[0:0]$14535
+ attribute \src "libresoc.v:202944.7-202944.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $1\mfrr$11[7:0]$14744
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 8 $1\mfrr$next[7:0]$14724
- attribute \src "libresoc.v:204008.13-204008.25"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $1\mfrr$11[7:0]$14556
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 8 $1\mfrr$next[7:0]$14536
+ attribute \src "libresoc.v:202952.13-202952.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:204157.3-204168.6"
+ attribute \src "libresoc.v:203101.3-203112.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:204147.3-204156.6"
+ attribute \src "libresoc.v:203091.3-203100.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire $1\wb_ack$14[0:0]$14745
- attribute \src "libresoc.v:204071.3-204086.6"
- wire $1\wb_ack$next[0:0]$14725
- attribute \src "libresoc.v:204022.7-204022.20"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire $1\wb_ack$14[0:0]$14557
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire $1\wb_ack$next[0:0]$14537
+ attribute \src "libresoc.v:202966.7-202966.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 32 $1\wb_rd_data$next[31:0]$14726
- attribute \src "libresoc.v:204030.14-204030.32"
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 32 $1\wb_rd_data$next[31:0]$14538
+ attribute \src "libresoc.v:202974.14-202974.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:204087.3-204117.6"
+ attribute \src "libresoc.v:203031.3-203061.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 24 $1\xisr$9[23:0]$14750
- attribute \src "libresoc.v:204071.3-204086.6"
- wire width 24 $1\xisr$next[23:0]$14727
- attribute \src "libresoc.v:204040.14-204040.31"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 24 $1\xisr$9[23:0]$14562
+ attribute \src "libresoc.v:203015.3-203030.6"
+ wire width 24 $1\xisr$next[23:0]$14539
+ attribute \src "libresoc.v:202984.14-202984.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:204118.3-204146.6"
+ attribute \src "libresoc.v:203062.3-203090.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $2\cppr$10[7:0]$14746
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $2\mfrr$11[7:0]$14747
- attribute \src "libresoc.v:204087.3-204117.6"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $2\cppr$10[7:0]$14558
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $2\mfrr$11[7:0]$14559
+ attribute \src "libresoc.v:203031.3-203061.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 24 $2\xisr$9[23:0]$14751
- attribute \src "libresoc.v:204118.3-204146.6"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 24 $2\xisr$9[23:0]$14563
+ attribute \src "libresoc.v:203062.3-203090.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $3\cppr$10[7:0]$14748
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $3\mfrr$11[7:0]$14749
- attribute \src "libresoc.v:204087.3-204117.6"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $3\cppr$10[7:0]$14560
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $3\mfrr$11[7:0]$14561
+ attribute \src "libresoc.v:203031.3-203061.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204188.3-204250.6"
- wire width 8 $4\cppr$10[7:0]$14752
- attribute \src "libresoc.v:204087.3-204117.6"
+ attribute \src "libresoc.v:203132.3-203194.6"
+ wire width 8 $4\cppr$10[7:0]$14564
+ attribute \src "libresoc.v:203031.3-203061.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204047.18-204047.116"
- wire $and$libresoc.v:204047$14698_Y
- attribute \src "libresoc.v:204051.18-204051.116"
- wire $and$libresoc.v:204051$14702_Y
- attribute \src "libresoc.v:204053.18-204053.116"
- wire $and$libresoc.v:204053$14704_Y
- attribute \src "libresoc.v:204056.17-204056.109"
- wire $and$libresoc.v:204056$14707_Y
- attribute \src "libresoc.v:204052.18-204052.110"
- wire $eq$libresoc.v:204052$14703_Y
- attribute \src "libresoc.v:204049.18-204049.114"
- wire $lt$libresoc.v:204049$14700_Y
- attribute \src "libresoc.v:204050.18-204050.109"
- wire $lt$libresoc.v:204050$14701_Y
- attribute \src "libresoc.v:204055.18-204055.114"
- wire $lt$libresoc.v:204055$14706_Y
- attribute \src "libresoc.v:204048.18-204048.109"
- wire $ne$libresoc.v:204048$14699_Y
- attribute \src "libresoc.v:204054.18-204054.109"
- wire $ne$libresoc.v:204054$14705_Y
+ attribute \src "libresoc.v:202991.18-202991.116"
+ wire $and$libresoc.v:202991$14510_Y
+ attribute \src "libresoc.v:202995.18-202995.116"
+ wire $and$libresoc.v:202995$14514_Y
+ attribute \src "libresoc.v:202997.18-202997.116"
+ wire $and$libresoc.v:202997$14516_Y
+ attribute \src "libresoc.v:203000.17-203000.109"
+ wire $and$libresoc.v:203000$14519_Y
+ attribute \src "libresoc.v:202996.18-202996.110"
+ wire $eq$libresoc.v:202996$14515_Y
+ attribute \src "libresoc.v:202993.18-202993.114"
+ wire $lt$libresoc.v:202993$14512_Y
+ attribute \src "libresoc.v:202994.18-202994.109"
+ wire $lt$libresoc.v:202994$14513_Y
+ attribute \src "libresoc.v:202999.18-202999.114"
+ wire $lt$libresoc.v:202999$14518_Y
+ attribute \src "libresoc.v:202992.18-202992.109"
+ wire $ne$libresoc.v:202992$14511_Y
+ attribute \src "libresoc.v:202998.18-202998.109"
+ wire $ne$libresoc.v:202998$14517_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 13 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire output 4 \core_irq_o
wire width 8 input 3 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 input 2 \ics_i_src
- attribute \src "libresoc.v:203938.7-203938.15"
+ attribute \src "libresoc.v:202882.7-202882.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
wire width 8 \min_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
wire width 8 \pending_priority
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
wire \wb_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:204047$14698
+ cell $and $and$libresoc.v:202991$14510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:204047$14698_Y
+ connect \Y $and$libresoc.v:202991$14510_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:204051$14702
+ cell $and $and$libresoc.v:202995$14514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:204051$14702_Y
+ connect \Y $and$libresoc.v:202995$14514_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:204053$14704
+ cell $and $and$libresoc.v:202997$14516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:204053$14704_Y
+ connect \Y $and$libresoc.v:202997$14516_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:204056$14707
+ cell $and $and$libresoc.v:203000$14519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:204056$14707_Y
+ connect \Y $and$libresoc.v:203000$14519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:204052$14703
+ cell $eq $eq$libresoc.v:202996$14515
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:204052$14703_Y
+ connect \Y $eq$libresoc.v:202996$14515_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:204049$14700
+ cell $lt $lt$libresoc.v:202993$14512
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:204049$14700_Y
+ connect \Y $lt$libresoc.v:202993$14512_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:204050$14701
+ cell $lt $lt$libresoc.v:202994$14513
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:204050$14701_Y
+ connect \Y $lt$libresoc.v:202994$14513_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:204055$14706
+ cell $lt $lt$libresoc.v:202999$14518
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:204055$14706_Y
+ connect \Y $lt$libresoc.v:202999$14518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:204048$14699
+ cell $ne $ne$libresoc.v:202992$14511
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:204048$14699_Y
+ connect \Y $ne$libresoc.v:202992$14511_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:204054$14705
+ cell $ne $ne$libresoc.v:202998$14517
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:204054$14705_Y
+ connect \Y $ne$libresoc.v:202998$14517_Y
end
- attribute \src "libresoc.v:203938.7-203938.20"
- process $proc$libresoc.v:203938$14754
+ attribute \src "libresoc.v:202882.7-202882.20"
+ process $proc$libresoc.v:202882$14566
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:203967.7-203967.24"
- process $proc$libresoc.v:203967$14755
+ attribute \src "libresoc.v:202911.7-202911.24"
+ process $proc$libresoc.v:202911$14567
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:203971.13-203971.25"
- process $proc$libresoc.v:203971$14756
+ attribute \src "libresoc.v:202915.13-202915.25"
+ process $proc$libresoc.v:202915$14568
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:204000.7-204000.17"
- process $proc$libresoc.v:204000$14757
+ attribute \src "libresoc.v:202944.7-202944.17"
+ process $proc$libresoc.v:202944$14569
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:204008.13-204008.25"
- process $proc$libresoc.v:204008$14758
+ attribute \src "libresoc.v:202952.13-202952.25"
+ process $proc$libresoc.v:202952$14570
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:204022.7-204022.20"
- process $proc$libresoc.v:204022$14759
+ attribute \src "libresoc.v:202966.7-202966.20"
+ process $proc$libresoc.v:202966$14571
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:204030.14-204030.32"
- process $proc$libresoc.v:204030$14760
+ attribute \src "libresoc.v:202974.14-202974.32"
+ process $proc$libresoc.v:202974$14572
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:204040.14-204040.31"
- process $proc$libresoc.v:204040$14761
+ attribute \src "libresoc.v:202984.14-202984.31"
+ process $proc$libresoc.v:202984$14573
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:204057.3-204058.37"
- process $proc$libresoc.v:204057$14708
+ attribute \src "libresoc.v:203001.3-203002.37"
+ process $proc$libresoc.v:203001$14520
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
sync posedge \clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:204059.3-204060.25"
- process $proc$libresoc.v:204059$14709
+ attribute \src "libresoc.v:203003.3-203004.25"
+ process $proc$libresoc.v:203003$14521
assign { } { }
assign $0\xisr[23:0] \xisr$next
sync posedge \clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:204061.3-204062.25"
- process $proc$libresoc.v:204061$14710
+ attribute \src "libresoc.v:203005.3-203006.25"
+ process $proc$libresoc.v:203005$14522
assign { } { }
assign $0\cppr[7:0] \cppr$next
sync posedge \clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:204063.3-204064.25"
- process $proc$libresoc.v:204063$14711
+ attribute \src "libresoc.v:203007.3-203008.25"
+ process $proc$libresoc.v:203007$14523
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
sync posedge \clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:204065.3-204066.23"
- process $proc$libresoc.v:204065$14712
+ attribute \src "libresoc.v:203009.3-203010.23"
+ process $proc$libresoc.v:203009$14524
assign { } { }
assign $0\irq[0:0] \irq$next
sync posedge \clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:204067.3-204068.37"
- process $proc$libresoc.v:204067$14713
+ attribute \src "libresoc.v:203011.3-203012.37"
+ process $proc$libresoc.v:203011$14525
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
sync posedge \clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:204069.3-204070.29"
- process $proc$libresoc.v:204069$14714
+ attribute \src "libresoc.v:203013.3-203014.29"
+ process $proc$libresoc.v:203013$14526
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
sync posedge \clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:204071.3-204086.6"
- process $proc$libresoc.v:204071$14715
+ attribute \src "libresoc.v:203015.3-203030.6"
+ process $proc$libresoc.v:203015$14527
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cppr$next[7:0]$14716 $1\cppr$next[7:0]$14722
- assign $0\irq$next[0:0]$14717 $1\irq$next[0:0]$14723
- assign $0\mfrr$next[7:0]$14718 $1\mfrr$next[7:0]$14724
- assign $0\wb_ack$next[0:0]$14719 $1\wb_ack$next[0:0]$14725
- assign $0\wb_rd_data$next[31:0]$14720 $1\wb_rd_data$next[31:0]$14726
- assign $0\xisr$next[23:0]$14721 $1\xisr$next[23:0]$14727
- attribute \src "libresoc.v:204072.5-204072.29"
+ assign $0\cppr$next[7:0]$14528 $1\cppr$next[7:0]$14534
+ assign $0\irq$next[0:0]$14529 $1\irq$next[0:0]$14535
+ assign $0\mfrr$next[7:0]$14530 $1\mfrr$next[7:0]$14536
+ assign $0\wb_ack$next[0:0]$14531 $1\wb_ack$next[0:0]$14537
+ assign $0\wb_rd_data$next[31:0]$14532 $1\wb_rd_data$next[31:0]$14538
+ assign $0\xisr$next[23:0]$14533 $1\xisr$next[23:0]$14539
+ attribute \src "libresoc.v:203016.5-203016.29"
switch \initial
- attribute \src "libresoc.v:204072.9-204072.17"
+ attribute \src "libresoc.v:203016.9-203016.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xisr$next[23:0]$14727 24'000000000000000000000000
- assign $1\cppr$next[7:0]$14722 8'00000000
- assign $1\mfrr$next[7:0]$14724 8'11111111
- assign $1\irq$next[0:0]$14723 1'0
- assign $1\wb_rd_data$next[31:0]$14726 0
- assign $1\wb_ack$next[0:0]$14725 1'0
+ assign $1\xisr$next[23:0]$14539 24'000000000000000000000000
+ assign $1\cppr$next[7:0]$14534 8'00000000
+ assign $1\mfrr$next[7:0]$14536 8'11111111
+ assign $1\irq$next[0:0]$14535 1'0
+ assign $1\wb_rd_data$next[31:0]$14538 0
+ assign $1\wb_ack$next[0:0]$14537 1'0
case
- assign $1\cppr$next[7:0]$14722 \cppr$2
- assign $1\irq$next[0:0]$14723 \irq$4
- assign $1\mfrr$next[7:0]$14724 \mfrr$3
- assign $1\wb_ack$next[0:0]$14725 \wb_ack$6
- assign $1\wb_rd_data$next[31:0]$14726 \wb_rd_data$5
- assign $1\xisr$next[23:0]$14727 \xisr$1
+ assign $1\cppr$next[7:0]$14534 \cppr$2
+ assign $1\irq$next[0:0]$14535 \irq$4
+ assign $1\mfrr$next[7:0]$14536 \mfrr$3
+ assign $1\wb_ack$next[0:0]$14537 \wb_ack$6
+ assign $1\wb_rd_data$next[31:0]$14538 \wb_rd_data$5
+ assign $1\xisr$next[23:0]$14539 \xisr$1
end
sync always
- update \cppr$next $0\cppr$next[7:0]$14716
- update \irq$next $0\irq$next[0:0]$14717
- update \mfrr$next $0\mfrr$next[7:0]$14718
- update \wb_ack$next $0\wb_ack$next[0:0]$14719
- update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14720
- update \xisr$next $0\xisr$next[23:0]$14721
+ update \cppr$next $0\cppr$next[7:0]$14528
+ update \irq$next $0\irq$next[0:0]$14529
+ update \mfrr$next $0\mfrr$next[7:0]$14530
+ update \wb_ack$next $0\wb_ack$next[0:0]$14531
+ update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14532
+ update \xisr$next $0\xisr$next[23:0]$14533
end
- attribute \src "libresoc.v:204087.3-204117.6"
- process $proc$libresoc.v:204087$14728
+ attribute \src "libresoc.v:203031.3-203061.6"
+ process $proc$libresoc.v:203031$14540
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:204088.5-204088.29"
+ attribute \src "libresoc.v:203032.5-203032.29"
switch \initial
- attribute \src "libresoc.v:204088.9-204088.17"
+ attribute \src "libresoc.v:203032.9-203032.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:204118.3-204146.6"
- process $proc$libresoc.v:204118$14729
+ attribute \src "libresoc.v:203062.3-203090.6"
+ process $proc$libresoc.v:203062$14541
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:204119.5-204119.29"
+ attribute \src "libresoc.v:203063.5-203063.29"
switch \initial
- attribute \src "libresoc.v:204119.9-204119.17"
+ attribute \src "libresoc.v:203063.9-203063.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:204147.3-204156.6"
- process $proc$libresoc.v:204147$14730
+ attribute \src "libresoc.v:203091.3-203100.6"
+ process $proc$libresoc.v:203091$14542
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:204148.5-204148.29"
+ attribute \src "libresoc.v:203092.5-203092.29"
switch \initial
- attribute \src "libresoc.v:204148.9-204148.17"
+ attribute \src "libresoc.v:203092.9-203092.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:204157.3-204168.6"
- process $proc$libresoc.v:204157$14731
+ attribute \src "libresoc.v:203101.3-203112.6"
+ process $proc$libresoc.v:203101$14543
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:204158.5-204158.29"
+ attribute \src "libresoc.v:203102.5-203102.29"
switch \initial
- attribute \src "libresoc.v:204158.9-204158.17"
+ attribute \src "libresoc.v:203102.9-203102.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:204169.3-204177.6"
- process $proc$libresoc.v:204169$14732
+ attribute \src "libresoc.v:203113.3-203121.6"
+ process $proc$libresoc.v:203113$14544
assign { } { }
assign { } { }
- assign $0\core_irq_o$next[0:0]$14733 $1\core_irq_o$next[0:0]$14734
- attribute \src "libresoc.v:204170.5-204170.29"
+ assign $0\core_irq_o$next[0:0]$14545 $1\core_irq_o$next[0:0]$14546
+ attribute \src "libresoc.v:203114.5-203114.29"
switch \initial
- attribute \src "libresoc.v:204170.9-204170.17"
+ attribute \src "libresoc.v:203114.9-203114.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_irq_o$next[0:0]$14734 1'0
+ assign $1\core_irq_o$next[0:0]$14546 1'0
case
- assign $1\core_irq_o$next[0:0]$14734 \irq
+ assign $1\core_irq_o$next[0:0]$14546 \irq
end
sync always
- update \core_irq_o$next $0\core_irq_o$next[0:0]$14733
+ update \core_irq_o$next $0\core_irq_o$next[0:0]$14545
end
- attribute \src "libresoc.v:204178.3-204187.6"
- process $proc$libresoc.v:204178$14735
+ attribute \src "libresoc.v:203122.3-203131.6"
+ process $proc$libresoc.v:203122$14547
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:204179.5-204179.29"
+ attribute \src "libresoc.v:203123.5-203123.29"
switch \initial
- attribute \src "libresoc.v:204179.9-204179.17"
+ attribute \src "libresoc.v:203123.9-203123.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:204188.3-204250.6"
- process $proc$libresoc.v:204188$14736
+ attribute \src "libresoc.v:203132.3-203194.6"
+ process $proc$libresoc.v:203132$14548
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mfrr$11[7:0]$14739 $1\mfrr$11[7:0]$14744
- assign $0\wb_ack$14[0:0]$14740 $1\wb_ack$14[0:0]$14745
+ assign $0\mfrr$11[7:0]$14551 $1\mfrr$11[7:0]$14556
+ assign $0\wb_ack$14[0:0]$14552 $1\wb_ack$14[0:0]$14557
assign { } { }
assign { } { }
assign { } { }
- assign $0\xisr$9[23:0]$14742 $2\xisr$9[23:0]$14751
- assign $0\cppr$10[7:0]$14737 $4\cppr$10[7:0]$14752
- assign $0\wb_rd_data$13[31:0]$14741 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
- assign $0\irq$12[0:0]$14738 $1\irq$12[0:0]$14753
- attribute \src "libresoc.v:204189.5-204189.29"
+ assign $0\xisr$9[23:0]$14554 $2\xisr$9[23:0]$14563
+ assign $0\cppr$10[7:0]$14549 $4\cppr$10[7:0]$14564
+ assign $0\wb_rd_data$13[31:0]$14553 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $0\irq$12[0:0]$14550 $1\irq$12[0:0]$14565
+ attribute \src "libresoc.v:203133.5-203133.29"
switch \initial
- attribute \src "libresoc.v:204189.9-204189.17"
+ attribute \src "libresoc.v:203133.9-203133.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wb_ack$14[0:0]$14745 1'1
- assign $1\cppr$10[7:0]$14743 $2\cppr$10[7:0]$14746
- assign $1\mfrr$11[7:0]$14744 $2\mfrr$11[7:0]$14747
+ assign $1\wb_ack$14[0:0]$14557 1'1
+ assign $1\cppr$10[7:0]$14555 $2\cppr$10[7:0]$14558
+ assign $1\mfrr$11[7:0]$14556 $2\mfrr$11[7:0]$14559
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
switch \icp_wb__we
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
- assign $2\cppr$10[7:0]$14746 $3\cppr$10[7:0]$14748
- assign $2\mfrr$11[7:0]$14747 $3\mfrr$11[7:0]$14749
+ assign $2\cppr$10[7:0]$14558 $3\cppr$10[7:0]$14560
+ assign $2\mfrr$11[7:0]$14559 $3\mfrr$11[7:0]$14561
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
switch \icp_wb__adr [5:0]
attribute \src "libresoc.v:0.0-0.0"
case 6'000000
assign { } { }
- assign $3\mfrr$11[7:0]$14749 \mfrr
- assign $3\cppr$10[7:0]$14748 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14561 \mfrr
+ assign $3\cppr$10[7:0]$14560 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000001
assign { } { }
- assign $3\mfrr$11[7:0]$14749 \mfrr
- assign $3\cppr$10[7:0]$14748 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14561 \mfrr
+ assign $3\cppr$10[7:0]$14560 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000011
- assign $3\cppr$10[7:0]$14748 \cppr
+ assign $3\cppr$10[7:0]$14560 \cppr
assign { } { }
- assign $3\mfrr$11[7:0]$14749 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14561 \be_in [31:24]
case
- assign $3\cppr$10[7:0]$14748 \cppr
- assign $3\mfrr$11[7:0]$14749 \mfrr
+ assign $3\cppr$10[7:0]$14560 \cppr
+ assign $3\mfrr$11[7:0]$14561 \mfrr
end
case
- assign $2\cppr$10[7:0]$14746 \cppr
- assign $2\mfrr$11[7:0]$14747 \mfrr
+ assign $2\cppr$10[7:0]$14558 \cppr
+ assign $2\mfrr$11[7:0]$14559 \mfrr
end
case
- assign $1\cppr$10[7:0]$14743 \cppr
- assign $1\mfrr$11[7:0]$14744 \mfrr
- assign $1\wb_ack$14[0:0]$14745 1'0
+ assign $1\cppr$10[7:0]$14555 \cppr
+ assign $1\mfrr$11[7:0]$14556 \mfrr
+ assign $1\wb_ack$14[0:0]$14557 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xisr$9[23:0]$14750 { 20'00000000000000000001 \ics_i_src }
+ assign $1\xisr$9[23:0]$14562 { 20'00000000000000000001 \ics_i_src }
case
- assign $1\xisr$9[23:0]$14750 24'000000000000000000000000
+ assign $1\xisr$9[23:0]$14562 24'000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xisr$9[23:0]$14751 24'000000000000000000000010
+ assign $2\xisr$9[23:0]$14563 24'000000000000000000000010
case
- assign $2\xisr$9[23:0]$14751 $1\xisr$9[23:0]$14750
+ assign $2\xisr$9[23:0]$14563 $1\xisr$9[23:0]$14562
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
switch \xirr_accept_rd
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cppr$10[7:0]$14752 \min_pri
+ assign $4\cppr$10[7:0]$14564 \min_pri
case
- assign $4\cppr$10[7:0]$14752 $1\cppr$10[7:0]$14743
+ assign $4\cppr$10[7:0]$14564 $1\cppr$10[7:0]$14555
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
switch { \irq \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\irq$12[0:0]$14753 1'1
+ assign $1\irq$12[0:0]$14565 1'1
case
- assign $1\irq$12[0:0]$14753 1'0
+ assign $1\irq$12[0:0]$14565 1'0
end
sync always
- update \cppr$10 $0\cppr$10[7:0]$14737
- update \irq$12 $0\irq$12[0:0]$14738
- update \mfrr$11 $0\mfrr$11[7:0]$14739
- update \wb_ack$14 $0\wb_ack$14[0:0]$14740
- update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14741
- update \xisr$9 $0\xisr$9[23:0]$14742
+ update \cppr$10 $0\cppr$10[7:0]$14549
+ update \irq$12 $0\irq$12[0:0]$14550
+ update \mfrr$11 $0\mfrr$11[7:0]$14551
+ update \wb_ack$14 $0\wb_ack$14[0:0]$14552
+ update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14553
+ update \xisr$9 $0\xisr$9[23:0]$14554
end
- connect \$15 $and$libresoc.v:204047$14698_Y
- connect \$17 $ne$libresoc.v:204048$14699_Y
- connect \$19 $lt$libresoc.v:204049$14700_Y
- connect \$21 $lt$libresoc.v:204050$14701_Y
- connect \$23 $and$libresoc.v:204051$14702_Y
- connect \$25 $eq$libresoc.v:204052$14703_Y
- connect \$27 $and$libresoc.v:204053$14704_Y
- connect \$29 $ne$libresoc.v:204054$14705_Y
- connect \$31 $lt$libresoc.v:204055$14706_Y
- connect \$7 $and$libresoc.v:204056$14707_Y
+ connect \$15 $and$libresoc.v:202991$14510_Y
+ connect \$17 $ne$libresoc.v:202992$14511_Y
+ connect \$19 $lt$libresoc.v:202993$14512_Y
+ connect \$21 $lt$libresoc.v:202994$14513_Y
+ connect \$23 $and$libresoc.v:202995$14514_Y
+ connect \$25 $eq$libresoc.v:202996$14515_Y
+ connect \$27 $and$libresoc.v:202997$14516_Y
+ connect \$29 $ne$libresoc.v:202998$14517_Y
+ connect \$31 $lt$libresoc.v:202999$14518_Y
+ connect \$7 $and$libresoc.v:203000$14519_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:204258.1-205307.10"
+attribute \src "libresoc.v:203202.1-204251.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:205188.3-205237.6"
+ attribute \src "libresoc.v:204132.3-204181.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:204899.3-204908.6"
+ attribute \src "libresoc.v:203843.3-203852.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:205108.3-205117.6"
+ attribute \src "libresoc.v:204052.3-204061.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:205128.3-205137.6"
+ attribute \src "libresoc.v:204072.3-204081.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:205148.3-205157.6"
+ attribute \src "libresoc.v:204092.3-204101.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:205168.3-205177.6"
+ attribute \src "libresoc.v:204112.3-204121.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:205238.3-205247.6"
+ attribute \src "libresoc.v:204182.3-204191.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:205258.3-205267.6"
+ attribute \src "libresoc.v:204202.3-204211.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:204919.3-204928.6"
+ attribute \src "libresoc.v:203863.3-203872.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:204939.3-204948.6"
+ attribute \src "libresoc.v:203883.3-203892.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:204959.3-204968.6"
+ attribute \src "libresoc.v:203903.3-203912.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:204988.3-204997.6"
+ attribute \src "libresoc.v:203932.3-203941.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:205008.3-205017.6"
+ attribute \src "libresoc.v:203952.3-203961.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:205028.3-205037.6"
+ attribute \src "libresoc.v:203972.3-203981.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:205048.3-205057.6"
+ attribute \src "libresoc.v:203992.3-204001.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:205068.3-205077.6"
+ attribute \src "libresoc.v:204012.3-204021.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:205088.3-205097.6"
+ attribute \src "libresoc.v:204032.3-204041.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:204889.3-204898.6"
+ attribute \src "libresoc.v:203833.3-203842.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:205098.3-205107.6"
+ attribute \src "libresoc.v:204042.3-204051.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:205118.3-205127.6"
+ attribute \src "libresoc.v:204062.3-204071.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:205138.3-205147.6"
+ attribute \src "libresoc.v:204082.3-204091.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:205158.3-205167.6"
+ attribute \src "libresoc.v:204102.3-204111.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:205178.3-205187.6"
+ attribute \src "libresoc.v:204122.3-204131.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:205248.3-205257.6"
+ attribute \src "libresoc.v:204192.3-204201.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:204909.3-204918.6"
+ attribute \src "libresoc.v:203853.3-203862.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:204929.3-204938.6"
+ attribute \src "libresoc.v:203873.3-203882.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:204949.3-204958.6"
+ attribute \src "libresoc.v:203893.3-203902.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:204969.3-204978.6"
+ attribute \src "libresoc.v:203913.3-203922.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:204998.3-205007.6"
+ attribute \src "libresoc.v:203942.3-203951.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:205018.3-205027.6"
+ attribute \src "libresoc.v:203962.3-203971.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:205038.3-205047.6"
+ attribute \src "libresoc.v:203982.3-203991.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:205058.3-205067.6"
+ attribute \src "libresoc.v:204002.3-204011.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:205078.3-205087.6"
+ attribute \src "libresoc.v:204022.3-204031.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:205268.3-205277.6"
+ attribute \src "libresoc.v:204212.3-204221.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:204763.3-204764.25"
+ attribute \src "libresoc.v:203707.3-203708.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:204761.3-204762.28"
+ attribute \src "libresoc.v:203705.3-203706.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:205287.3-205295.6"
- wire $0\ics_wb__ack$next[0:0]$15008
- attribute \src "libresoc.v:204797.3-204798.39"
+ attribute \src "libresoc.v:204231.3-204239.6"
+ wire $0\ics_wb__ack$next[0:0]$14820
+ attribute \src "libresoc.v:203741.3-203742.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:205278.3-205286.6"
- wire width 32 $0\ics_wb__dat_r$next[31:0]$15005
- attribute \src "libresoc.v:204799.3-204800.43"
+ attribute \src "libresoc.v:204222.3-204230.6"
+ wire width 32 $0\ics_wb__dat_r$next[31:0]$14817
+ attribute \src "libresoc.v:203743.3-203744.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:204259.7-204259.20"
+ attribute \src "libresoc.v:203203.7-203203.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:204979.3-204987.6"
- wire width 16 $0\int_level_l$next[15:0]$14977
- attribute \src "libresoc.v:204801.3-204802.39"
+ attribute \src "libresoc.v:203923.3-203931.6"
+ wire width 16 $0\int_level_l$next[15:0]$14789
+ attribute \src "libresoc.v:203745.3-203746.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive0_pri$next[7:0]$14887
- attribute \src "libresoc.v:204765.3-204766.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive0_pri$next[7:0]$14699
+ attribute \src "libresoc.v:203709.3-203710.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive10_pri$next[7:0]$14888
- attribute \src "libresoc.v:204785.3-204786.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive10_pri$next[7:0]$14700
+ attribute \src "libresoc.v:203729.3-203730.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive11_pri$next[7:0]$14889
- attribute \src "libresoc.v:204787.3-204788.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive11_pri$next[7:0]$14701
+ attribute \src "libresoc.v:203731.3-203732.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive12_pri$next[7:0]$14890
- attribute \src "libresoc.v:204789.3-204790.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive12_pri$next[7:0]$14702
+ attribute \src "libresoc.v:203733.3-203734.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive13_pri$next[7:0]$14891
- attribute \src "libresoc.v:204791.3-204792.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive13_pri$next[7:0]$14703
+ attribute \src "libresoc.v:203735.3-203736.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive14_pri$next[7:0]$14892
- attribute \src "libresoc.v:204793.3-204794.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive14_pri$next[7:0]$14704
+ attribute \src "libresoc.v:203737.3-203738.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive15_pri$next[7:0]$14893
- attribute \src "libresoc.v:204795.3-204796.37"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive15_pri$next[7:0]$14705
+ attribute \src "libresoc.v:203739.3-203740.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive1_pri$next[7:0]$14894
- attribute \src "libresoc.v:204767.3-204768.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive1_pri$next[7:0]$14706
+ attribute \src "libresoc.v:203711.3-203712.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive2_pri$next[7:0]$14895
- attribute \src "libresoc.v:204769.3-204770.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive2_pri$next[7:0]$14707
+ attribute \src "libresoc.v:203713.3-203714.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive3_pri$next[7:0]$14896
- attribute \src "libresoc.v:204771.3-204772.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive3_pri$next[7:0]$14708
+ attribute \src "libresoc.v:203715.3-203716.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive4_pri$next[7:0]$14897
- attribute \src "libresoc.v:204773.3-204774.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive4_pri$next[7:0]$14709
+ attribute \src "libresoc.v:203717.3-203718.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive5_pri$next[7:0]$14898
- attribute \src "libresoc.v:204775.3-204776.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive5_pri$next[7:0]$14710
+ attribute \src "libresoc.v:203719.3-203720.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive6_pri$next[7:0]$14899
- attribute \src "libresoc.v:204777.3-204778.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive6_pri$next[7:0]$14711
+ attribute \src "libresoc.v:203721.3-203722.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive7_pri$next[7:0]$14900
- attribute \src "libresoc.v:204779.3-204780.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive7_pri$next[7:0]$14712
+ attribute \src "libresoc.v:203723.3-203724.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive8_pri$next[7:0]$14901
- attribute \src "libresoc.v:204781.3-204782.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive8_pri$next[7:0]$14713
+ attribute \src "libresoc.v:203725.3-203726.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $0\xive9_pri$next[7:0]$14902
- attribute \src "libresoc.v:204783.3-204784.35"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $0\xive9_pri$next[7:0]$14714
+ attribute \src "libresoc.v:203727.3-203728.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:205188.3-205237.6"
+ attribute \src "libresoc.v:204132.3-204181.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:204899.3-204908.6"
+ attribute \src "libresoc.v:203843.3-203852.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:205108.3-205117.6"
+ attribute \src "libresoc.v:204052.3-204061.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:205128.3-205137.6"
+ attribute \src "libresoc.v:204072.3-204081.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:205148.3-205157.6"
+ attribute \src "libresoc.v:204092.3-204101.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:205168.3-205177.6"
+ attribute \src "libresoc.v:204112.3-204121.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:205238.3-205247.6"
+ attribute \src "libresoc.v:204182.3-204191.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:205258.3-205267.6"
+ attribute \src "libresoc.v:204202.3-204211.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:204919.3-204928.6"
+ attribute \src "libresoc.v:203863.3-203872.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:204939.3-204948.6"
+ attribute \src "libresoc.v:203883.3-203892.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:204959.3-204968.6"
+ attribute \src "libresoc.v:203903.3-203912.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:204988.3-204997.6"
+ attribute \src "libresoc.v:203932.3-203941.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:205008.3-205017.6"
+ attribute \src "libresoc.v:203952.3-203961.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:205028.3-205037.6"
+ attribute \src "libresoc.v:203972.3-203981.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:205048.3-205057.6"
+ attribute \src "libresoc.v:203992.3-204001.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:205068.3-205077.6"
+ attribute \src "libresoc.v:204012.3-204021.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:205088.3-205097.6"
+ attribute \src "libresoc.v:204032.3-204041.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:204889.3-204898.6"
+ attribute \src "libresoc.v:203833.3-203842.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:205098.3-205107.6"
+ attribute \src "libresoc.v:204042.3-204051.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:205118.3-205127.6"
+ attribute \src "libresoc.v:204062.3-204071.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:205138.3-205147.6"
+ attribute \src "libresoc.v:204082.3-204091.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:205158.3-205167.6"
+ attribute \src "libresoc.v:204102.3-204111.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:205178.3-205187.6"
+ attribute \src "libresoc.v:204122.3-204131.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:205248.3-205257.6"
+ attribute \src "libresoc.v:204192.3-204201.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:204909.3-204918.6"
+ attribute \src "libresoc.v:203853.3-203862.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:204929.3-204938.6"
+ attribute \src "libresoc.v:203873.3-203882.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:204949.3-204958.6"
+ attribute \src "libresoc.v:203893.3-203902.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:204969.3-204978.6"
+ attribute \src "libresoc.v:203913.3-203922.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:204998.3-205007.6"
+ attribute \src "libresoc.v:203942.3-203951.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:205018.3-205027.6"
+ attribute \src "libresoc.v:203962.3-203971.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:205038.3-205047.6"
+ attribute \src "libresoc.v:203982.3-203991.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:205058.3-205067.6"
+ attribute \src "libresoc.v:204002.3-204011.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:205078.3-205087.6"
+ attribute \src "libresoc.v:204022.3-204031.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:205268.3-205277.6"
+ attribute \src "libresoc.v:204212.3-204221.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:204540.13-204540.30"
+ attribute \src "libresoc.v:203484.13-203484.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:204545.13-204545.29"
+ attribute \src "libresoc.v:203489.13-203489.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:205287.3-205295.6"
- wire $1\ics_wb__ack$next[0:0]$15009
- attribute \src "libresoc.v:204554.7-204554.25"
+ attribute \src "libresoc.v:204231.3-204239.6"
+ wire $1\ics_wb__ack$next[0:0]$14821
+ attribute \src "libresoc.v:203498.7-203498.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:205278.3-205286.6"
- wire width 32 $1\ics_wb__dat_r$next[31:0]$15006
- attribute \src "libresoc.v:204563.14-204563.35"
+ attribute \src "libresoc.v:204222.3-204230.6"
+ wire width 32 $1\ics_wb__dat_r$next[31:0]$14818
+ attribute \src "libresoc.v:203507.14-203507.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:204979.3-204987.6"
- wire width 16 $1\int_level_l$next[15:0]$14978
- attribute \src "libresoc.v:204575.14-204575.36"
+ attribute \src "libresoc.v:203923.3-203931.6"
+ wire width 16 $1\int_level_l$next[15:0]$14790
+ attribute \src "libresoc.v:203519.14-203519.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive0_pri$next[7:0]$14903
- attribute \src "libresoc.v:204595.13-204595.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive0_pri$next[7:0]$14715
+ attribute \src "libresoc.v:203539.13-203539.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive10_pri$next[7:0]$14904
- attribute \src "libresoc.v:204599.13-204599.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive10_pri$next[7:0]$14716
+ attribute \src "libresoc.v:203543.13-203543.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive11_pri$next[7:0]$14905
- attribute \src "libresoc.v:204603.13-204603.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive11_pri$next[7:0]$14717
+ attribute \src "libresoc.v:203547.13-203547.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive12_pri$next[7:0]$14906
- attribute \src "libresoc.v:204607.13-204607.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive12_pri$next[7:0]$14718
+ attribute \src "libresoc.v:203551.13-203551.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive13_pri$next[7:0]$14907
- attribute \src "libresoc.v:204611.13-204611.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive13_pri$next[7:0]$14719
+ attribute \src "libresoc.v:203555.13-203555.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive14_pri$next[7:0]$14908
- attribute \src "libresoc.v:204615.13-204615.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive14_pri$next[7:0]$14720
+ attribute \src "libresoc.v:203559.13-203559.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive15_pri$next[7:0]$14909
- attribute \src "libresoc.v:204619.13-204619.31"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive15_pri$next[7:0]$14721
+ attribute \src "libresoc.v:203563.13-203563.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive1_pri$next[7:0]$14910
- attribute \src "libresoc.v:204623.13-204623.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive1_pri$next[7:0]$14722
+ attribute \src "libresoc.v:203567.13-203567.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive2_pri$next[7:0]$14911
- attribute \src "libresoc.v:204627.13-204627.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive2_pri$next[7:0]$14723
+ attribute \src "libresoc.v:203571.13-203571.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive3_pri$next[7:0]$14912
- attribute \src "libresoc.v:204631.13-204631.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive3_pri$next[7:0]$14724
+ attribute \src "libresoc.v:203575.13-203575.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive4_pri$next[7:0]$14913
- attribute \src "libresoc.v:204635.13-204635.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive4_pri$next[7:0]$14725
+ attribute \src "libresoc.v:203579.13-203579.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive5_pri$next[7:0]$14914
- attribute \src "libresoc.v:204639.13-204639.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive5_pri$next[7:0]$14726
+ attribute \src "libresoc.v:203583.13-203583.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive6_pri$next[7:0]$14915
- attribute \src "libresoc.v:204643.13-204643.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive6_pri$next[7:0]$14727
+ attribute \src "libresoc.v:203587.13-203587.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive7_pri$next[7:0]$14916
- attribute \src "libresoc.v:204647.13-204647.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive7_pri$next[7:0]$14728
+ attribute \src "libresoc.v:203591.13-203591.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive8_pri$next[7:0]$14917
- attribute \src "libresoc.v:204651.13-204651.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive8_pri$next[7:0]$14729
+ attribute \src "libresoc.v:203595.13-203595.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $1\xive9_pri$next[7:0]$14918
- attribute \src "libresoc.v:204655.13-204655.30"
+ attribute \src "libresoc.v:203747.3-203832.6"
+ wire width 8 $1\xive9_pri$next[7:0]$14730
+ attribute \src "libresoc.v:203599.13-203599.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:205188.3-205237.6"
+ attribute \src "libresoc.v:204132.3-204181.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive0_pri$next[7:0]$14919
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive10_pri$next[7:0]$14920
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive11_pri$next[7:0]$14921
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive12_pri$next[7:0]$14922
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive13_pri$next[7:0]$14923
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive14_pri$next[7:0]$14924
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive15_pri$next[7:0]$14925
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive1_pri$next[7:0]$14926
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive2_pri$next[7:0]$14927
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive3_pri$next[7:0]$14928
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive4_pri$next[7:0]$14929
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive5_pri$next[7:0]$14930
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive6_pri$next[7:0]$14931
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive7_pri$next[7:0]$14932
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive8_pri$next[7:0]$14933
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $2\xive9_pri$next[7:0]$14934
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive0_pri$next[7:0]$14935
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive10_pri$next[7:0]$14936
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive11_pri$next[7:0]$14937
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive12_pri$next[7:0]$14938
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive13_pri$next[7:0]$14939
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive14_pri$next[7:0]$14940
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive15_pri$next[7:0]$14941
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive1_pri$next[7:0]$14942
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive2_pri$next[7:0]$14943
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive3_pri$next[7:0]$14944
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive4_pri$next[7:0]$14945
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive5_pri$next[7:0]$14946
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive6_pri$next[7:0]$14947
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive7_pri$next[7:0]$14948
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive8_pri$next[7:0]$14949
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $3\xive9_pri$next[7:0]$14950
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive0_pri$next[7:0]$14951
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive10_pri$next[7:0]$14952
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive11_pri$next[7:0]$14953
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive12_pri$next[7:0]$14954
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive13_pri$next[7:0]$14955
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive14_pri$next[7:0]$14956
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive15_pri$next[7:0]$14957
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive1_pri$next[7:0]$14958
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive2_pri$next[7:0]$14959
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive3_pri$next[7:0]$14960
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive4_pri$next[7:0]$14961
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive5_pri$next[7:0]$14962
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive6_pri$next[7:0]$14963
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive7_pri$next[7:0]$14964
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive8_pri$next[7:0]$14965
- attribute \src "libresoc.v:204803.3-204888.6"
- wire width 8 $4\xive9_pri$next[7:0]$14966
- attribute \src "libresoc.v:204660.19-204660.113"
- wire $and$libresoc.v:204660$14764_Y
- attribute \src "libresoc.v:204662.19-204662.114"
- wire $and$libresoc.v:204662$14766_Y
- attribute \src "libresoc.v:204664.19-204664.114"
- wire $and$libresoc.v:204664$14768_Y
- attribute \src "libresoc.v:204666.19-204666.114"
- wire $and$libresoc.v:204666$14770_Y
- attribute \src "libresoc.v:204668.19-204668.114"
- wire $and$libresoc.v:204668$14772_Y
- attribute \src "libresoc.v:204670.19-204670.114"
- wire $and$libresoc.v:204670$14774_Y
- attribute \src "libresoc.v:204672.19-204672.114"
- wire $and$libresoc.v:204672$14776_Y
- attribute \src "libresoc.v:204675.19-204675.114"
- wire $and$libresoc.v:204675$14779_Y
- attribute \src "libresoc.v:204677.19-204677.114"
- wire $and$libresoc.v:204677$14781_Y
- attribute \src "libresoc.v:204679.19-204679.114"
- wire $and$libresoc.v:204679$14783_Y
- attribute \src "libresoc.v:204682.19-204682.114"
- wire $and$libresoc.v:204682$14786_Y
- attribute \src "libresoc.v:204684.19-204684.114"
- wire $and$libresoc.v:204684$14788_Y
- attribute \src "libresoc.v:204686.19-204686.114"
- wire $and$libresoc.v:204686$14790_Y
- attribute \src "libresoc.v:204688.19-204688.114"
- wire $and$libresoc.v:204688$14792_Y
- attribute \src "libresoc.v:204690.19-204690.115"
- wire $and$libresoc.v:204690$14794_Y
- attribute \src "libresoc.v:204692.19-204692.115"
- wire $and$libresoc.v:204692$14796_Y
- attribute \src "libresoc.v:204694.19-204694.115"
- wire $and$libresoc.v:204694$14798_Y
- attribute \src "libresoc.v:204697.19-204697.115"
- wire $and$libresoc.v:204697$14801_Y
- attribute \src "libresoc.v:204699.19-204699.115"
- wire $and$libresoc.v:204699$14803_Y
- attribute \src "libresoc.v:204701.19-204701.115"
- wire $and$libresoc.v:204701$14805_Y
- attribute \src "libresoc.v:204704.19-204704.115"
- wire $and$libresoc.v:204704$14808_Y
- attribute \src "libresoc.v:204706.19-204706.115"
- wire $and$libresoc.v:204706$14810_Y
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+ wire $eq$libresoc.v:203677$14649_Y
+ attribute \src "libresoc.v:203679.18-203679.110"
+ wire $eq$libresoc.v:203679$14651_Y
+ attribute \src "libresoc.v:203681.18-203681.110"
+ wire $eq$libresoc.v:203681$14653_Y
+ attribute \src "libresoc.v:203684.18-203684.110"
+ wire $eq$libresoc.v:203684$14656_Y
+ attribute \src "libresoc.v:203686.18-203686.110"
+ wire $eq$libresoc.v:203686$14658_Y
+ attribute \src "libresoc.v:203688.18-203688.110"
+ wire $eq$libresoc.v:203688$14660_Y
+ attribute \src "libresoc.v:203699.17-203699.108"
+ wire $eq$libresoc.v:203699$14671_Y
+ attribute \src "libresoc.v:203603.18-203603.111"
+ wire $lt$libresoc.v:203603$14575_Y
+ attribute \src "libresoc.v:203605.19-203605.112"
+ wire $lt$libresoc.v:203605$14577_Y
+ attribute \src "libresoc.v:203607.19-203607.112"
+ wire $lt$libresoc.v:203607$14579_Y
+ attribute \src "libresoc.v:203609.19-203609.112"
+ wire $lt$libresoc.v:203609$14581_Y
+ attribute \src "libresoc.v:203611.19-203611.112"
+ wire $lt$libresoc.v:203611$14583_Y
+ attribute \src "libresoc.v:203613.19-203613.112"
+ wire $lt$libresoc.v:203613$14585_Y
+ attribute \src "libresoc.v:203615.19-203615.112"
+ wire $lt$libresoc.v:203615$14587_Y
+ attribute \src "libresoc.v:203617.19-203617.112"
+ wire $lt$libresoc.v:203617$14589_Y
+ attribute \src "libresoc.v:203620.19-203620.112"
+ wire $lt$libresoc.v:203620$14592_Y
+ attribute \src "libresoc.v:203622.19-203622.112"
+ wire $lt$libresoc.v:203622$14594_Y
+ attribute \src "libresoc.v:203625.19-203625.112"
+ wire $lt$libresoc.v:203625$14597_Y
+ attribute \src "libresoc.v:203627.19-203627.112"
+ wire $lt$libresoc.v:203627$14599_Y
+ attribute \src "libresoc.v:203629.19-203629.112"
+ wire $lt$libresoc.v:203629$14601_Y
+ attribute \src "libresoc.v:203631.19-203631.112"
+ wire $lt$libresoc.v:203631$14603_Y
+ attribute \src "libresoc.v:203633.19-203633.113"
+ wire $lt$libresoc.v:203633$14605_Y
+ attribute \src "libresoc.v:203635.19-203635.113"
+ wire $lt$libresoc.v:203635$14607_Y
+ attribute \src "libresoc.v:203637.19-203637.114"
+ wire $lt$libresoc.v:203637$14609_Y
+ attribute \src "libresoc.v:203639.19-203639.114"
+ wire $lt$libresoc.v:203639$14611_Y
+ attribute \src "libresoc.v:203642.19-203642.114"
+ wire $lt$libresoc.v:203642$14614_Y
+ attribute \src "libresoc.v:203644.19-203644.114"
+ wire $lt$libresoc.v:203644$14616_Y
+ attribute \src "libresoc.v:203647.19-203647.114"
+ wire $lt$libresoc.v:203647$14619_Y
+ attribute \src "libresoc.v:203649.19-203649.114"
+ wire $lt$libresoc.v:203649$14621_Y
+ attribute \src "libresoc.v:203651.19-203651.114"
+ wire $lt$libresoc.v:203651$14623_Y
+ attribute \src "libresoc.v:203653.19-203653.114"
+ wire $lt$libresoc.v:203653$14625_Y
+ attribute \src "libresoc.v:203655.19-203655.114"
+ wire $lt$libresoc.v:203655$14627_Y
+ attribute \src "libresoc.v:203658.19-203658.114"
+ wire $lt$libresoc.v:203658$14630_Y
+ attribute \src "libresoc.v:203692.18-203692.110"
+ wire $lt$libresoc.v:203692$14664_Y
+ attribute \src "libresoc.v:203694.18-203694.110"
+ wire $lt$libresoc.v:203694$14666_Y
+ attribute \src "libresoc.v:203696.18-203696.111"
+ wire $lt$libresoc.v:203696$14668_Y
+ attribute \src "libresoc.v:203698.18-203698.111"
+ wire $lt$libresoc.v:203698$14670_Y
+ attribute \src "libresoc.v:203701.18-203701.111"
+ wire $lt$libresoc.v:203701$14673_Y
+ attribute \src "libresoc.v:203703.18-203703.111"
+ wire $lt$libresoc.v:203703$14675_Y
+ attribute \src "libresoc.v:203690.18-203690.40"
+ wire width 16 $shr$libresoc.v:203690$14662_Y
+ attribute \src "libresoc.v:203602.17-203602.114"
+ wire width 8 $ternary$libresoc.v:203602$14574_Y
+ attribute \src "libresoc.v:203624.18-203624.116"
+ wire width 8 $ternary$libresoc.v:203624$14596_Y
+ attribute \src "libresoc.v:203646.18-203646.116"
+ wire width 8 $ternary$libresoc.v:203646$14618_Y
+ attribute \src "libresoc.v:203661.19-203661.118"
+ wire width 8 $ternary$libresoc.v:203661$14633_Y
+ attribute \src "libresoc.v:203663.18-203663.116"
+ wire width 8 $ternary$libresoc.v:203663$14635_Y
+ attribute \src "libresoc.v:203665.18-203665.116"
+ wire width 8 $ternary$libresoc.v:203665$14637_Y
+ attribute \src "libresoc.v:203667.18-203667.116"
+ wire width 8 $ternary$libresoc.v:203667$14639_Y
+ attribute \src "libresoc.v:203669.18-203669.116"
+ wire width 8 $ternary$libresoc.v:203669$14641_Y
+ attribute \src "libresoc.v:203671.18-203671.116"
+ wire width 8 $ternary$libresoc.v:203671$14643_Y
+ attribute \src "libresoc.v:203674.18-203674.116"
+ wire width 8 $ternary$libresoc.v:203674$14646_Y
+ attribute \src "libresoc.v:203676.18-203676.116"
+ wire width 8 $ternary$libresoc.v:203676$14648_Y
+ attribute \src "libresoc.v:203678.18-203678.117"
+ wire width 8 $ternary$libresoc.v:203678$14650_Y
+ attribute \src "libresoc.v:203680.18-203680.117"
+ wire width 8 $ternary$libresoc.v:203680$14652_Y
+ attribute \src "libresoc.v:203682.18-203682.117"
+ wire width 8 $ternary$libresoc.v:203682$14654_Y
+ attribute \src "libresoc.v:203685.18-203685.117"
+ wire width 8 $ternary$libresoc.v:203685$14657_Y
+ attribute \src "libresoc.v:203687.18-203687.117"
+ wire width 8 $ternary$libresoc.v:203687$14659_Y
+ attribute \src "libresoc.v:203689.18-203689.117"
+ wire width 8 $ternary$libresoc.v:203689$14661_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 12 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
wire width 4 \cur_idx0
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:204259.7-204259.15"
+ attribute \src "libresoc.v:203203.7-203203.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
wire \reg_is_debug
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
wire \reg_is_xive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
wire \wb_valid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204660$14764
+ cell $and $and$libresoc.v:203604$14576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:204660$14764_Y
+ connect \Y $and$libresoc.v:203604$14576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204662$14766
+ cell $and $and$libresoc.v:203606$14578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:204662$14766_Y
+ connect \Y $and$libresoc.v:203606$14578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204664$14768
+ cell $and $and$libresoc.v:203608$14580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:204664$14768_Y
+ connect \Y $and$libresoc.v:203608$14580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204666$14770
+ cell $and $and$libresoc.v:203610$14582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:204666$14770_Y
+ connect \Y $and$libresoc.v:203610$14582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204668$14772
+ cell $and $and$libresoc.v:203612$14584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:204668$14772_Y
+ connect \Y $and$libresoc.v:203612$14584_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204670$14774
+ cell $and $and$libresoc.v:203614$14586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:204670$14774_Y
+ connect \Y $and$libresoc.v:203614$14586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204672$14776
+ cell $and $and$libresoc.v:203616$14588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:204672$14776_Y
+ connect \Y $and$libresoc.v:203616$14588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204675$14779
+ cell $and $and$libresoc.v:203619$14591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:204675$14779_Y
+ connect \Y $and$libresoc.v:203619$14591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204677$14781
+ cell $and $and$libresoc.v:203621$14593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:204677$14781_Y
+ connect \Y $and$libresoc.v:203621$14593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204679$14783
+ cell $and $and$libresoc.v:203623$14595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:204679$14783_Y
+ connect \Y $and$libresoc.v:203623$14595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204682$14786
+ cell $and $and$libresoc.v:203626$14598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:204682$14786_Y
+ connect \Y $and$libresoc.v:203626$14598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204684$14788
+ cell $and $and$libresoc.v:203628$14600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:204684$14788_Y
+ connect \Y $and$libresoc.v:203628$14600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204686$14790
+ cell $and $and$libresoc.v:203630$14602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:204686$14790_Y
+ connect \Y $and$libresoc.v:203630$14602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204688$14792
+ cell $and $and$libresoc.v:203632$14604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:204688$14792_Y
+ connect \Y $and$libresoc.v:203632$14604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204690$14794
+ cell $and $and$libresoc.v:203634$14606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:204690$14794_Y
+ connect \Y $and$libresoc.v:203634$14606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204692$14796
+ cell $and $and$libresoc.v:203636$14608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:204692$14796_Y
+ connect \Y $and$libresoc.v:203636$14608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204694$14798
+ cell $and $and$libresoc.v:203638$14610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:204694$14798_Y
+ connect \Y $and$libresoc.v:203638$14610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204697$14801
+ cell $and $and$libresoc.v:203641$14613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:204697$14801_Y
+ connect \Y $and$libresoc.v:203641$14613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204699$14803
+ cell $and $and$libresoc.v:203643$14615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:204699$14803_Y
+ connect \Y $and$libresoc.v:203643$14615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204701$14805
+ cell $and $and$libresoc.v:203645$14617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:204701$14805_Y
+ connect \Y $and$libresoc.v:203645$14617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204704$14808
+ cell $and $and$libresoc.v:203648$14620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:204704$14808_Y
+ connect \Y $and$libresoc.v:203648$14620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204706$14810
+ cell $and $and$libresoc.v:203650$14622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:204706$14810_Y
+ connect \Y $and$libresoc.v:203650$14622_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204708$14812
+ cell $and $and$libresoc.v:203652$14624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:204708$14812_Y
+ connect \Y $and$libresoc.v:203652$14624_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204710$14814
+ cell $and $and$libresoc.v:203654$14626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:204710$14814_Y
+ connect \Y $and$libresoc.v:203654$14626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204712$14816
+ cell $and $and$libresoc.v:203656$14628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:204712$14816_Y
+ connect \Y $and$libresoc.v:203656$14628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204715$14819
+ cell $and $and$libresoc.v:203659$14631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:204715$14819_Y
+ connect \Y $and$libresoc.v:203659$14631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:204739$14843
+ cell $and $and$libresoc.v:203683$14655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:204739$14843_Y
+ connect \Y $and$libresoc.v:203683$14655_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:204747$14851
+ cell $and $and$libresoc.v:203691$14663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:204747$14851_Y
+ connect \Y $and$libresoc.v:203691$14663_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204749$14853
+ cell $and $and$libresoc.v:203693$14665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:204749$14853_Y
+ connect \Y $and$libresoc.v:203693$14665_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204751$14855
+ cell $and $and$libresoc.v:203695$14667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:204751$14855_Y
+ connect \Y $and$libresoc.v:203695$14667_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204753$14857
+ cell $and $and$libresoc.v:203697$14669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:204753$14857_Y
+ connect \Y $and$libresoc.v:203697$14669_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204756$14860
+ cell $and $and$libresoc.v:203700$14672
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:204756$14860_Y
+ connect \Y $and$libresoc.v:203700$14672_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204758$14862
+ cell $and $and$libresoc.v:203702$14674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:204758$14862_Y
+ connect \Y $and$libresoc.v:203702$14674_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:204760$14864
+ cell $and $and$libresoc.v:203704$14676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:204760$14864_Y
+ connect \Y $and$libresoc.v:203704$14676_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204674$14778
+ cell $eq $eq$libresoc.v:203618$14590
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204674$14778_Y
+ connect \Y $eq$libresoc.v:203618$14590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204696$14800
+ cell $eq $eq$libresoc.v:203640$14612
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204696$14800_Y
+ connect \Y $eq$libresoc.v:203640$14612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:204713$14817
+ cell $eq $eq$libresoc.v:203657$14629
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:204713$14817_Y
+ connect \Y $eq$libresoc.v:203657$14629_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204716$14820
+ cell $eq $eq$libresoc.v:203660$14632
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204716$14820_Y
+ connect \Y $eq$libresoc.v:203660$14632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204718$14822
+ cell $eq $eq$libresoc.v:203662$14634
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204718$14822_Y
+ connect \Y $eq$libresoc.v:203662$14634_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204720$14824
+ cell $eq $eq$libresoc.v:203664$14636
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204720$14824_Y
+ connect \Y $eq$libresoc.v:203664$14636_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204722$14826
+ cell $eq $eq$libresoc.v:203666$14638
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204722$14826_Y
+ connect \Y $eq$libresoc.v:203666$14638_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204724$14828
+ cell $eq $eq$libresoc.v:203668$14640
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204724$14828_Y
+ connect \Y $eq$libresoc.v:203668$14640_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204726$14830
+ cell $eq $eq$libresoc.v:203670$14642
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204726$14830_Y
+ connect \Y $eq$libresoc.v:203670$14642_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:204728$14832
+ cell $eq $eq$libresoc.v:203672$14644
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:204728$14832_Y
+ connect \Y $eq$libresoc.v:203672$14644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204729$14833
+ cell $eq $eq$libresoc.v:203673$14645
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204729$14833_Y
+ connect \Y $eq$libresoc.v:203673$14645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204731$14835
+ cell $eq $eq$libresoc.v:203675$14647
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204731$14835_Y
+ connect \Y $eq$libresoc.v:203675$14647_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204733$14837
+ cell $eq $eq$libresoc.v:203677$14649
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204733$14837_Y
+ connect \Y $eq$libresoc.v:203677$14649_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204735$14839
+ cell $eq $eq$libresoc.v:203679$14651
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204735$14839_Y
+ connect \Y $eq$libresoc.v:203679$14651_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204737$14841
+ cell $eq $eq$libresoc.v:203681$14653
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204737$14841_Y
+ connect \Y $eq$libresoc.v:203681$14653_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204740$14844
+ cell $eq $eq$libresoc.v:203684$14656
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204740$14844_Y
+ connect \Y $eq$libresoc.v:203684$14656_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204742$14846
+ cell $eq $eq$libresoc.v:203686$14658
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204742$14846_Y
+ connect \Y $eq$libresoc.v:203686$14658_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204744$14848
+ cell $eq $eq$libresoc.v:203688$14660
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204744$14848_Y
+ connect \Y $eq$libresoc.v:203688$14660_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:204755$14859
+ cell $eq $eq$libresoc.v:203699$14671
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:204755$14859_Y
+ connect \Y $eq$libresoc.v:203699$14671_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204659$14763
+ cell $lt $lt$libresoc.v:203603$14575
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:204659$14763_Y
+ connect \Y $lt$libresoc.v:203603$14575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204661$14765
+ cell $lt $lt$libresoc.v:203605$14577
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:204661$14765_Y
+ connect \Y $lt$libresoc.v:203605$14577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204663$14767
+ cell $lt $lt$libresoc.v:203607$14579
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:204663$14767_Y
+ connect \Y $lt$libresoc.v:203607$14579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204665$14769
+ cell $lt $lt$libresoc.v:203609$14581
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:204665$14769_Y
+ connect \Y $lt$libresoc.v:203609$14581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204667$14771
+ cell $lt $lt$libresoc.v:203611$14583
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:204667$14771_Y
+ connect \Y $lt$libresoc.v:203611$14583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204669$14773
+ cell $lt $lt$libresoc.v:203613$14585
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:204669$14773_Y
+ connect \Y $lt$libresoc.v:203613$14585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204671$14775
+ cell $lt $lt$libresoc.v:203615$14587
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:204671$14775_Y
+ connect \Y $lt$libresoc.v:203615$14587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204673$14777
+ cell $lt $lt$libresoc.v:203617$14589
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:204673$14777_Y
+ connect \Y $lt$libresoc.v:203617$14589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204676$14780
+ cell $lt $lt$libresoc.v:203620$14592
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:204676$14780_Y
+ connect \Y $lt$libresoc.v:203620$14592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204678$14782
+ cell $lt $lt$libresoc.v:203622$14594
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:204678$14782_Y
+ connect \Y $lt$libresoc.v:203622$14594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204681$14785
+ cell $lt $lt$libresoc.v:203625$14597
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:204681$14785_Y
+ connect \Y $lt$libresoc.v:203625$14597_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204683$14787
+ cell $lt $lt$libresoc.v:203627$14599
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:204683$14787_Y
+ connect \Y $lt$libresoc.v:203627$14599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204685$14789
+ cell $lt $lt$libresoc.v:203629$14601
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:204685$14789_Y
+ connect \Y $lt$libresoc.v:203629$14601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204687$14791
+ cell $lt $lt$libresoc.v:203631$14603
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:204687$14791_Y
+ connect \Y $lt$libresoc.v:203631$14603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204689$14793
+ cell $lt $lt$libresoc.v:203633$14605
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:204689$14793_Y
+ connect \Y $lt$libresoc.v:203633$14605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204691$14795
+ cell $lt $lt$libresoc.v:203635$14607
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:204691$14795_Y
+ connect \Y $lt$libresoc.v:203635$14607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204693$14797
+ cell $lt $lt$libresoc.v:203637$14609
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:204693$14797_Y
+ connect \Y $lt$libresoc.v:203637$14609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204695$14799
+ cell $lt $lt$libresoc.v:203639$14611
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:204695$14799_Y
+ connect \Y $lt$libresoc.v:203639$14611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204698$14802
+ cell $lt $lt$libresoc.v:203642$14614
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:204698$14802_Y
+ connect \Y $lt$libresoc.v:203642$14614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204700$14804
+ cell $lt $lt$libresoc.v:203644$14616
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:204700$14804_Y
+ connect \Y $lt$libresoc.v:203644$14616_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204703$14807
+ cell $lt $lt$libresoc.v:203647$14619
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:204703$14807_Y
+ connect \Y $lt$libresoc.v:203647$14619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204705$14809
+ cell $lt $lt$libresoc.v:203649$14621
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:204705$14809_Y
+ connect \Y $lt$libresoc.v:203649$14621_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204707$14811
+ cell $lt $lt$libresoc.v:203651$14623
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:204707$14811_Y
+ connect \Y $lt$libresoc.v:203651$14623_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204709$14813
+ cell $lt $lt$libresoc.v:203653$14625
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:204709$14813_Y
+ connect \Y $lt$libresoc.v:203653$14625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204711$14815
+ cell $lt $lt$libresoc.v:203655$14627
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:204711$14815_Y
+ connect \Y $lt$libresoc.v:203655$14627_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204714$14818
+ cell $lt $lt$libresoc.v:203658$14630
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:204714$14818_Y
+ connect \Y $lt$libresoc.v:203658$14630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204748$14852
+ cell $lt $lt$libresoc.v:203692$14664
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:204748$14852_Y
+ connect \Y $lt$libresoc.v:203692$14664_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204750$14854
+ cell $lt $lt$libresoc.v:203694$14666
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:204750$14854_Y
+ connect \Y $lt$libresoc.v:203694$14666_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204752$14856
+ cell $lt $lt$libresoc.v:203696$14668
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:204752$14856_Y
+ connect \Y $lt$libresoc.v:203696$14668_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204754$14858
+ cell $lt $lt$libresoc.v:203698$14670
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:204754$14858_Y
+ connect \Y $lt$libresoc.v:203698$14670_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204757$14861
+ cell $lt $lt$libresoc.v:203701$14673
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:204757$14861_Y
+ connect \Y $lt$libresoc.v:203701$14673_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:204759$14863
+ cell $lt $lt$libresoc.v:203703$14675
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:204759$14863_Y
+ connect \Y $lt$libresoc.v:203703$14675_Y
end
- attribute \src "libresoc.v:204746.18-204746.40"
- cell $shr $shr$libresoc.v:204746$14850
+ attribute \src "libresoc.v:203690.18-203690.40"
+ cell $shr $shr$libresoc.v:203690$14662
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:204746$14850_Y
+ connect \Y $shr$libresoc.v:203690$14662_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204658$14762
+ cell $mux $ternary$libresoc.v:203602$14574
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:204658$14762_Y
+ connect \Y $ternary$libresoc.v:203602$14574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204680$14784
+ cell $mux $ternary$libresoc.v:203624$14596
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:204680$14784_Y
+ connect \Y $ternary$libresoc.v:203624$14596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204702$14806
+ cell $mux $ternary$libresoc.v:203646$14618
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:204702$14806_Y
+ connect \Y $ternary$libresoc.v:203646$14618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204717$14821
+ cell $mux $ternary$libresoc.v:203661$14633
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:204717$14821_Y
+ connect \Y $ternary$libresoc.v:203661$14633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204719$14823
+ cell $mux $ternary$libresoc.v:203663$14635
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:204719$14823_Y
+ connect \Y $ternary$libresoc.v:203663$14635_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204721$14825
+ cell $mux $ternary$libresoc.v:203665$14637
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:204721$14825_Y
+ connect \Y $ternary$libresoc.v:203665$14637_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204723$14827
+ cell $mux $ternary$libresoc.v:203667$14639
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:204723$14827_Y
+ connect \Y $ternary$libresoc.v:203667$14639_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204725$14829
+ cell $mux $ternary$libresoc.v:203669$14641
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:204725$14829_Y
+ connect \Y $ternary$libresoc.v:203669$14641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204727$14831
+ cell $mux $ternary$libresoc.v:203671$14643
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:204727$14831_Y
+ connect \Y $ternary$libresoc.v:203671$14643_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204730$14834
+ cell $mux $ternary$libresoc.v:203674$14646
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:204730$14834_Y
+ connect \Y $ternary$libresoc.v:203674$14646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204732$14836
+ cell $mux $ternary$libresoc.v:203676$14648
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:204732$14836_Y
+ connect \Y $ternary$libresoc.v:203676$14648_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204734$14838
+ cell $mux $ternary$libresoc.v:203678$14650
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:204734$14838_Y
+ connect \Y $ternary$libresoc.v:203678$14650_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204736$14840
+ cell $mux $ternary$libresoc.v:203680$14652
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:204736$14840_Y
+ connect \Y $ternary$libresoc.v:203680$14652_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204738$14842
+ cell $mux $ternary$libresoc.v:203682$14654
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:204738$14842_Y
+ connect \Y $ternary$libresoc.v:203682$14654_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204741$14845
+ cell $mux $ternary$libresoc.v:203685$14657
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:204741$14845_Y
+ connect \Y $ternary$libresoc.v:203685$14657_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204743$14847
+ cell $mux $ternary$libresoc.v:203687$14659
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:204743$14847_Y
+ connect \Y $ternary$libresoc.v:203687$14659_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:204745$14849
+ cell $mux $ternary$libresoc.v:203689$14661
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:204745$14849_Y
+ connect \Y $ternary$libresoc.v:203689$14661_Y
end
- attribute \src "libresoc.v:204259.7-204259.20"
- process $proc$libresoc.v:204259$15010
+ attribute \src "libresoc.v:203203.7-203203.20"
+ process $proc$libresoc.v:203203$14822
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:204540.13-204540.30"
- process $proc$libresoc.v:204540$15011
+ attribute \src "libresoc.v:203484.13-203484.30"
+ process $proc$libresoc.v:203484$14823
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:204545.13-204545.29"
- process $proc$libresoc.v:204545$15012
+ attribute \src "libresoc.v:203489.13-203489.29"
+ process $proc$libresoc.v:203489$14824
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:204554.7-204554.25"
- process $proc$libresoc.v:204554$15013
+ attribute \src "libresoc.v:203498.7-203498.25"
+ process $proc$libresoc.v:203498$14825
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:204563.14-204563.35"
- process $proc$libresoc.v:204563$15014
+ attribute \src "libresoc.v:203507.14-203507.35"
+ process $proc$libresoc.v:203507$14826
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:204575.14-204575.36"
- process $proc$libresoc.v:204575$15015
+ attribute \src "libresoc.v:203519.14-203519.36"
+ process $proc$libresoc.v:203519$14827
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:204595.13-204595.30"
- process $proc$libresoc.v:204595$15016
+ attribute \src "libresoc.v:203539.13-203539.30"
+ process $proc$libresoc.v:203539$14828
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:204599.13-204599.31"
- process $proc$libresoc.v:204599$15017
+ attribute \src "libresoc.v:203543.13-203543.31"
+ process $proc$libresoc.v:203543$14829
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:204603.13-204603.31"
- process $proc$libresoc.v:204603$15018
+ attribute \src "libresoc.v:203547.13-203547.31"
+ process $proc$libresoc.v:203547$14830
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:204607.13-204607.31"
- process $proc$libresoc.v:204607$15019
+ attribute \src "libresoc.v:203551.13-203551.31"
+ process $proc$libresoc.v:203551$14831
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:204611.13-204611.31"
- process $proc$libresoc.v:204611$15020
+ attribute \src "libresoc.v:203555.13-203555.31"
+ process $proc$libresoc.v:203555$14832
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:204615.13-204615.31"
- process $proc$libresoc.v:204615$15021
+ attribute \src "libresoc.v:203559.13-203559.31"
+ process $proc$libresoc.v:203559$14833
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:204619.13-204619.31"
- process $proc$libresoc.v:204619$15022
+ attribute \src "libresoc.v:203563.13-203563.31"
+ process $proc$libresoc.v:203563$14834
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:204623.13-204623.30"
- process $proc$libresoc.v:204623$15023
+ attribute \src "libresoc.v:203567.13-203567.30"
+ process $proc$libresoc.v:203567$14835
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:204627.13-204627.30"
- process $proc$libresoc.v:204627$15024
+ attribute \src "libresoc.v:203571.13-203571.30"
+ process $proc$libresoc.v:203571$14836
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:204631.13-204631.30"
- process $proc$libresoc.v:204631$15025
+ attribute \src "libresoc.v:203575.13-203575.30"
+ process $proc$libresoc.v:203575$14837
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:204635.13-204635.30"
- process $proc$libresoc.v:204635$15026
+ attribute \src "libresoc.v:203579.13-203579.30"
+ process $proc$libresoc.v:203579$14838
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:204639.13-204639.30"
- process $proc$libresoc.v:204639$15027
+ attribute \src "libresoc.v:203583.13-203583.30"
+ process $proc$libresoc.v:203583$14839
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:204643.13-204643.30"
- process $proc$libresoc.v:204643$15028
+ attribute \src "libresoc.v:203587.13-203587.30"
+ process $proc$libresoc.v:203587$14840
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:204647.13-204647.30"
- process $proc$libresoc.v:204647$15029
+ attribute \src "libresoc.v:203591.13-203591.30"
+ process $proc$libresoc.v:203591$14841
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:204651.13-204651.30"
- process $proc$libresoc.v:204651$15030
+ attribute \src "libresoc.v:203595.13-203595.30"
+ process $proc$libresoc.v:203595$14842
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:204655.13-204655.30"
- process $proc$libresoc.v:204655$15031
+ attribute \src "libresoc.v:203599.13-203599.30"
+ process $proc$libresoc.v:203599$14843
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:204761.3-204762.28"
- process $proc$libresoc.v:204761$14865
+ attribute \src "libresoc.v:203705.3-203706.28"
+ process $proc$libresoc.v:203705$14677
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
sync posedge \clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:204763.3-204764.25"
- process $proc$libresoc.v:204763$14866
+ attribute \src "libresoc.v:203707.3-203708.25"
+ process $proc$libresoc.v:203707$14678
assign { } { }
assign $0\icp_o_pri[7:0] \$203
sync posedge \clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:204765.3-204766.35"
- process $proc$libresoc.v:204765$14867
+ attribute \src "libresoc.v:203709.3-203710.35"
+ process $proc$libresoc.v:203709$14679
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
sync posedge \clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:204767.3-204768.35"
- process $proc$libresoc.v:204767$14868
+ attribute \src "libresoc.v:203711.3-203712.35"
+ process $proc$libresoc.v:203711$14680
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
sync posedge \clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:204769.3-204770.35"
- process $proc$libresoc.v:204769$14869
+ attribute \src "libresoc.v:203713.3-203714.35"
+ process $proc$libresoc.v:203713$14681
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
sync posedge \clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:204771.3-204772.35"
- process $proc$libresoc.v:204771$14870
+ attribute \src "libresoc.v:203715.3-203716.35"
+ process $proc$libresoc.v:203715$14682
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
sync posedge \clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:204773.3-204774.35"
- process $proc$libresoc.v:204773$14871
+ attribute \src "libresoc.v:203717.3-203718.35"
+ process $proc$libresoc.v:203717$14683
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
sync posedge \clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:204775.3-204776.35"
- process $proc$libresoc.v:204775$14872
+ attribute \src "libresoc.v:203719.3-203720.35"
+ process $proc$libresoc.v:203719$14684
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
sync posedge \clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:204777.3-204778.35"
- process $proc$libresoc.v:204777$14873
+ attribute \src "libresoc.v:203721.3-203722.35"
+ process $proc$libresoc.v:203721$14685
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
sync posedge \clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:204779.3-204780.35"
- process $proc$libresoc.v:204779$14874
+ attribute \src "libresoc.v:203723.3-203724.35"
+ process $proc$libresoc.v:203723$14686
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
sync posedge \clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:204781.3-204782.35"
- process $proc$libresoc.v:204781$14875
+ attribute \src "libresoc.v:203725.3-203726.35"
+ process $proc$libresoc.v:203725$14687
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
sync posedge \clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:204783.3-204784.35"
- process $proc$libresoc.v:204783$14876
+ attribute \src "libresoc.v:203727.3-203728.35"
+ process $proc$libresoc.v:203727$14688
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
sync posedge \clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:204785.3-204786.37"
- process $proc$libresoc.v:204785$14877
+ attribute \src "libresoc.v:203729.3-203730.37"
+ process $proc$libresoc.v:203729$14689
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
sync posedge \clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:204787.3-204788.37"
- process $proc$libresoc.v:204787$14878
+ attribute \src "libresoc.v:203731.3-203732.37"
+ process $proc$libresoc.v:203731$14690
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
sync posedge \clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:204789.3-204790.37"
- process $proc$libresoc.v:204789$14879
+ attribute \src "libresoc.v:203733.3-203734.37"
+ process $proc$libresoc.v:203733$14691
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
sync posedge \clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:204791.3-204792.37"
- process $proc$libresoc.v:204791$14880
+ attribute \src "libresoc.v:203735.3-203736.37"
+ process $proc$libresoc.v:203735$14692
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
sync posedge \clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:204793.3-204794.37"
- process $proc$libresoc.v:204793$14881
+ attribute \src "libresoc.v:203737.3-203738.37"
+ process $proc$libresoc.v:203737$14693
assign { } { }
assign $0\xive14_pri[7:0] \xive14_pri$next
sync posedge \clk
update \xive14_pri $0\xive14_pri[7:0]
end
- attribute \src "libresoc.v:204795.3-204796.37"
- process $proc$libresoc.v:204795$14882
+ attribute \src "libresoc.v:203739.3-203740.37"
+ process $proc$libresoc.v:203739$14694
assign { } { }
assign $0\xive15_pri[7:0] \xive15_pri$next
sync posedge \clk
update \xive15_pri $0\xive15_pri[7:0]
end
- attribute \src "libresoc.v:204797.3-204798.39"
- process $proc$libresoc.v:204797$14883
+ attribute \src "libresoc.v:203741.3-203742.39"
+ process $proc$libresoc.v:203741$14695
assign { } { }
assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
sync posedge \clk
update \ics_wb__ack $0\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:204799.3-204800.43"
- process $proc$libresoc.v:204799$14884
+ attribute \src "libresoc.v:203743.3-203744.43"
+ process $proc$libresoc.v:203743$14696
assign { } { }
assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
sync posedge \clk
update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:204801.3-204802.39"
- process $proc$libresoc.v:204801$14885
+ attribute \src "libresoc.v:203745.3-203746.39"
+ process $proc$libresoc.v:203745$14697
assign { } { }
assign $0\int_level_l[15:0] \int_level_l$next
sync posedge \clk
update \int_level_l $0\int_level_l[15:0]
end
- attribute \src "libresoc.v:204803.3-204888.6"
- process $proc$libresoc.v:204803$14886
+ attribute \src "libresoc.v:203747.3-203832.6"
+ process $proc$libresoc.v:203747$14698
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xive0_pri$next[7:0]$14887 $4\xive0_pri$next[7:0]$14951
- assign $0\xive10_pri$next[7:0]$14888 $4\xive10_pri$next[7:0]$14952
- assign $0\xive11_pri$next[7:0]$14889 $4\xive11_pri$next[7:0]$14953
- assign $0\xive12_pri$next[7:0]$14890 $4\xive12_pri$next[7:0]$14954
- assign $0\xive13_pri$next[7:0]$14891 $4\xive13_pri$next[7:0]$14955
- assign $0\xive14_pri$next[7:0]$14892 $4\xive14_pri$next[7:0]$14956
- assign $0\xive15_pri$next[7:0]$14893 $4\xive15_pri$next[7:0]$14957
- assign $0\xive1_pri$next[7:0]$14894 $4\xive1_pri$next[7:0]$14958
- assign $0\xive2_pri$next[7:0]$14895 $4\xive2_pri$next[7:0]$14959
- assign $0\xive3_pri$next[7:0]$14896 $4\xive3_pri$next[7:0]$14960
- assign $0\xive4_pri$next[7:0]$14897 $4\xive4_pri$next[7:0]$14961
- assign $0\xive5_pri$next[7:0]$14898 $4\xive5_pri$next[7:0]$14962
- assign $0\xive6_pri$next[7:0]$14899 $4\xive6_pri$next[7:0]$14963
- assign $0\xive7_pri$next[7:0]$14900 $4\xive7_pri$next[7:0]$14964
- assign $0\xive8_pri$next[7:0]$14901 $4\xive8_pri$next[7:0]$14965
- assign $0\xive9_pri$next[7:0]$14902 $4\xive9_pri$next[7:0]$14966
- attribute \src "libresoc.v:204804.5-204804.29"
+ assign $0\xive0_pri$next[7:0]$14699 $4\xive0_pri$next[7:0]$14763
+ assign $0\xive10_pri$next[7:0]$14700 $4\xive10_pri$next[7:0]$14764
+ assign $0\xive11_pri$next[7:0]$14701 $4\xive11_pri$next[7:0]$14765
+ assign $0\xive12_pri$next[7:0]$14702 $4\xive12_pri$next[7:0]$14766
+ assign $0\xive13_pri$next[7:0]$14703 $4\xive13_pri$next[7:0]$14767
+ assign $0\xive14_pri$next[7:0]$14704 $4\xive14_pri$next[7:0]$14768
+ assign $0\xive15_pri$next[7:0]$14705 $4\xive15_pri$next[7:0]$14769
+ assign $0\xive1_pri$next[7:0]$14706 $4\xive1_pri$next[7:0]$14770
+ assign $0\xive2_pri$next[7:0]$14707 $4\xive2_pri$next[7:0]$14771
+ assign $0\xive3_pri$next[7:0]$14708 $4\xive3_pri$next[7:0]$14772
+ assign $0\xive4_pri$next[7:0]$14709 $4\xive4_pri$next[7:0]$14773
+ assign $0\xive5_pri$next[7:0]$14710 $4\xive5_pri$next[7:0]$14774
+ assign $0\xive6_pri$next[7:0]$14711 $4\xive6_pri$next[7:0]$14775
+ assign $0\xive7_pri$next[7:0]$14712 $4\xive7_pri$next[7:0]$14776
+ assign $0\xive8_pri$next[7:0]$14713 $4\xive8_pri$next[7:0]$14777
+ assign $0\xive9_pri$next[7:0]$14714 $4\xive9_pri$next[7:0]$14778
+ attribute \src "libresoc.v:203748.5-203748.29"
switch \initial
- attribute \src "libresoc.v:204804.9-204804.17"
+ attribute \src "libresoc.v:203748.9-203748.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xive0_pri$next[7:0]$14903 $2\xive0_pri$next[7:0]$14919
- assign $1\xive10_pri$next[7:0]$14904 $2\xive10_pri$next[7:0]$14920
- assign $1\xive11_pri$next[7:0]$14905 $2\xive11_pri$next[7:0]$14921
- assign $1\xive12_pri$next[7:0]$14906 $2\xive12_pri$next[7:0]$14922
- assign $1\xive13_pri$next[7:0]$14907 $2\xive13_pri$next[7:0]$14923
- assign $1\xive14_pri$next[7:0]$14908 $2\xive14_pri$next[7:0]$14924
- assign $1\xive15_pri$next[7:0]$14909 $2\xive15_pri$next[7:0]$14925
- assign $1\xive1_pri$next[7:0]$14910 $2\xive1_pri$next[7:0]$14926
- assign $1\xive2_pri$next[7:0]$14911 $2\xive2_pri$next[7:0]$14927
- assign $1\xive3_pri$next[7:0]$14912 $2\xive3_pri$next[7:0]$14928
- assign $1\xive4_pri$next[7:0]$14913 $2\xive4_pri$next[7:0]$14929
- assign $1\xive5_pri$next[7:0]$14914 $2\xive5_pri$next[7:0]$14930
- assign $1\xive6_pri$next[7:0]$14915 $2\xive6_pri$next[7:0]$14931
- assign $1\xive7_pri$next[7:0]$14916 $2\xive7_pri$next[7:0]$14932
- assign $1\xive8_pri$next[7:0]$14917 $2\xive8_pri$next[7:0]$14933
- assign $1\xive9_pri$next[7:0]$14918 $2\xive9_pri$next[7:0]$14934
+ assign $1\xive0_pri$next[7:0]$14715 $2\xive0_pri$next[7:0]$14731
+ assign $1\xive10_pri$next[7:0]$14716 $2\xive10_pri$next[7:0]$14732
+ assign $1\xive11_pri$next[7:0]$14717 $2\xive11_pri$next[7:0]$14733
+ assign $1\xive12_pri$next[7:0]$14718 $2\xive12_pri$next[7:0]$14734
+ assign $1\xive13_pri$next[7:0]$14719 $2\xive13_pri$next[7:0]$14735
+ assign $1\xive14_pri$next[7:0]$14720 $2\xive14_pri$next[7:0]$14736
+ assign $1\xive15_pri$next[7:0]$14721 $2\xive15_pri$next[7:0]$14737
+ assign $1\xive1_pri$next[7:0]$14722 $2\xive1_pri$next[7:0]$14738
+ assign $1\xive2_pri$next[7:0]$14723 $2\xive2_pri$next[7:0]$14739
+ assign $1\xive3_pri$next[7:0]$14724 $2\xive3_pri$next[7:0]$14740
+ assign $1\xive4_pri$next[7:0]$14725 $2\xive4_pri$next[7:0]$14741
+ assign $1\xive5_pri$next[7:0]$14726 $2\xive5_pri$next[7:0]$14742
+ assign $1\xive6_pri$next[7:0]$14727 $2\xive6_pri$next[7:0]$14743
+ assign $1\xive7_pri$next[7:0]$14728 $2\xive7_pri$next[7:0]$14744
+ assign $1\xive8_pri$next[7:0]$14729 $2\xive8_pri$next[7:0]$14745
+ assign $1\xive9_pri$next[7:0]$14730 $2\xive9_pri$next[7:0]$14746
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
switch \reg_is_xive
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\xive0_pri$next[7:0]$14919 $3\xive0_pri$next[7:0]$14935
- assign $2\xive10_pri$next[7:0]$14920 $3\xive10_pri$next[7:0]$14936
- assign $2\xive11_pri$next[7:0]$14921 $3\xive11_pri$next[7:0]$14937
- assign $2\xive12_pri$next[7:0]$14922 $3\xive12_pri$next[7:0]$14938
- assign $2\xive13_pri$next[7:0]$14923 $3\xive13_pri$next[7:0]$14939
- assign $2\xive14_pri$next[7:0]$14924 $3\xive14_pri$next[7:0]$14940
- assign $2\xive15_pri$next[7:0]$14925 $3\xive15_pri$next[7:0]$14941
- assign $2\xive1_pri$next[7:0]$14926 $3\xive1_pri$next[7:0]$14942
- assign $2\xive2_pri$next[7:0]$14927 $3\xive2_pri$next[7:0]$14943
- assign $2\xive3_pri$next[7:0]$14928 $3\xive3_pri$next[7:0]$14944
- assign $2\xive4_pri$next[7:0]$14929 $3\xive4_pri$next[7:0]$14945
- assign $2\xive5_pri$next[7:0]$14930 $3\xive5_pri$next[7:0]$14946
- assign $2\xive6_pri$next[7:0]$14931 $3\xive6_pri$next[7:0]$14947
- assign $2\xive7_pri$next[7:0]$14932 $3\xive7_pri$next[7:0]$14948
- assign $2\xive8_pri$next[7:0]$14933 $3\xive8_pri$next[7:0]$14949
- assign $2\xive9_pri$next[7:0]$14934 $3\xive9_pri$next[7:0]$14950
+ assign $2\xive0_pri$next[7:0]$14731 $3\xive0_pri$next[7:0]$14747
+ assign $2\xive10_pri$next[7:0]$14732 $3\xive10_pri$next[7:0]$14748
+ assign $2\xive11_pri$next[7:0]$14733 $3\xive11_pri$next[7:0]$14749
+ assign $2\xive12_pri$next[7:0]$14734 $3\xive12_pri$next[7:0]$14750
+ assign $2\xive13_pri$next[7:0]$14735 $3\xive13_pri$next[7:0]$14751
+ assign $2\xive14_pri$next[7:0]$14736 $3\xive14_pri$next[7:0]$14752
+ assign $2\xive15_pri$next[7:0]$14737 $3\xive15_pri$next[7:0]$14753
+ assign $2\xive1_pri$next[7:0]$14738 $3\xive1_pri$next[7:0]$14754
+ assign $2\xive2_pri$next[7:0]$14739 $3\xive2_pri$next[7:0]$14755
+ assign $2\xive3_pri$next[7:0]$14740 $3\xive3_pri$next[7:0]$14756
+ assign $2\xive4_pri$next[7:0]$14741 $3\xive4_pri$next[7:0]$14757
+ assign $2\xive5_pri$next[7:0]$14742 $3\xive5_pri$next[7:0]$14758
+ assign $2\xive6_pri$next[7:0]$14743 $3\xive6_pri$next[7:0]$14759
+ assign $2\xive7_pri$next[7:0]$14744 $3\xive7_pri$next[7:0]$14760
+ assign $2\xive8_pri$next[7:0]$14745 $3\xive8_pri$next[7:0]$14761
+ assign $2\xive9_pri$next[7:0]$14746 $3\xive9_pri$next[7:0]$14762
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
switch \reg_idx
attribute \src "libresoc.v:0.0-0.0"
case 4'0000
assign { } { }
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive0_pri$next[7:0]$14935 \be_in [7:0]
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14747 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
assign { } { }
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive1_pri$next[7:0]$14942 \be_in [7:0]
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive1_pri$next[7:0]$14754 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
assign { } { }
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive2_pri$next[7:0]$14943 \be_in [7:0]
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive2_pri$next[7:0]$14755 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0011
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
assign { } { }
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive3_pri$next[7:0]$14944 \be_in [7:0]
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive3_pri$next[7:0]$14756 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0100
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
assign { } { }
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive4_pri$next[7:0]$14945 \be_in [7:0]
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive4_pri$next[7:0]$14757 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
assign { } { }
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive5_pri$next[7:0]$14946 \be_in [7:0]
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive5_pri$next[7:0]$14758 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0110
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
assign { } { }
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive6_pri$next[7:0]$14947 \be_in [7:0]
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive6_pri$next[7:0]$14759 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0111
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
assign { } { }
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive7_pri$next[7:0]$14948 \be_in [7:0]
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive7_pri$next[7:0]$14760 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive8_pri$next[7:0]$14949 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive8_pri$next[7:0]$14761 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14950 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14762 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1010
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
assign { } { }
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive10_pri$next[7:0]$14936 \be_in [7:0]
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive10_pri$next[7:0]$14748 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1011
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
assign { } { }
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive11_pri$next[7:0]$14937 \be_in [7:0]
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive11_pri$next[7:0]$14749 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1100
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
assign { } { }
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive12_pri$next[7:0]$14938 \be_in [7:0]
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive12_pri$next[7:0]$14750 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1101
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
assign { } { }
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive13_pri$next[7:0]$14939 \be_in [7:0]
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive13_pri$next[7:0]$14751 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1110
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
assign { } { }
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive14_pri$next[7:0]$14940 \be_in [7:0]
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive14_pri$next[7:0]$14752 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'----
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
assign { } { }
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
- assign $3\xive15_pri$next[7:0]$14941 \be_in [7:0]
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive15_pri$next[7:0]$14753 \be_in [7:0]
case
- assign $3\xive0_pri$next[7:0]$14935 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14936 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14937 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14938 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14939 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14940 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14941 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14942 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14943 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14944 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14945 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14946 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14947 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14948 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14949 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14950 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
end
case
- assign $2\xive0_pri$next[7:0]$14919 \xive0_pri
- assign $2\xive10_pri$next[7:0]$14920 \xive10_pri
- assign $2\xive11_pri$next[7:0]$14921 \xive11_pri
- assign $2\xive12_pri$next[7:0]$14922 \xive12_pri
- assign $2\xive13_pri$next[7:0]$14923 \xive13_pri
- assign $2\xive14_pri$next[7:0]$14924 \xive14_pri
- assign $2\xive15_pri$next[7:0]$14925 \xive15_pri
- assign $2\xive1_pri$next[7:0]$14926 \xive1_pri
- assign $2\xive2_pri$next[7:0]$14927 \xive2_pri
- assign $2\xive3_pri$next[7:0]$14928 \xive3_pri
- assign $2\xive4_pri$next[7:0]$14929 \xive4_pri
- assign $2\xive5_pri$next[7:0]$14930 \xive5_pri
- assign $2\xive6_pri$next[7:0]$14931 \xive6_pri
- assign $2\xive7_pri$next[7:0]$14932 \xive7_pri
- assign $2\xive8_pri$next[7:0]$14933 \xive8_pri
- assign $2\xive9_pri$next[7:0]$14934 \xive9_pri
- end
- case
- assign $1\xive0_pri$next[7:0]$14903 \xive0_pri
- assign $1\xive10_pri$next[7:0]$14904 \xive10_pri
- assign $1\xive11_pri$next[7:0]$14905 \xive11_pri
- assign $1\xive12_pri$next[7:0]$14906 \xive12_pri
- assign $1\xive13_pri$next[7:0]$14907 \xive13_pri
- assign $1\xive14_pri$next[7:0]$14908 \xive14_pri
- assign $1\xive15_pri$next[7:0]$14909 \xive15_pri
- assign $1\xive1_pri$next[7:0]$14910 \xive1_pri
- assign $1\xive2_pri$next[7:0]$14911 \xive2_pri
- assign $1\xive3_pri$next[7:0]$14912 \xive3_pri
- assign $1\xive4_pri$next[7:0]$14913 \xive4_pri
- assign $1\xive5_pri$next[7:0]$14914 \xive5_pri
- assign $1\xive6_pri$next[7:0]$14915 \xive6_pri
- assign $1\xive7_pri$next[7:0]$14916 \xive7_pri
- assign $1\xive8_pri$next[7:0]$14917 \xive8_pri
- assign $1\xive9_pri$next[7:0]$14918 \xive9_pri
+ assign $2\xive0_pri$next[7:0]$14731 \xive0_pri
+ assign $2\xive10_pri$next[7:0]$14732 \xive10_pri
+ assign $2\xive11_pri$next[7:0]$14733 \xive11_pri
+ assign $2\xive12_pri$next[7:0]$14734 \xive12_pri
+ assign $2\xive13_pri$next[7:0]$14735 \xive13_pri
+ assign $2\xive14_pri$next[7:0]$14736 \xive14_pri
+ assign $2\xive15_pri$next[7:0]$14737 \xive15_pri
+ assign $2\xive1_pri$next[7:0]$14738 \xive1_pri
+ assign $2\xive2_pri$next[7:0]$14739 \xive2_pri
+ assign $2\xive3_pri$next[7:0]$14740 \xive3_pri
+ assign $2\xive4_pri$next[7:0]$14741 \xive4_pri
+ assign $2\xive5_pri$next[7:0]$14742 \xive5_pri
+ assign $2\xive6_pri$next[7:0]$14743 \xive6_pri
+ assign $2\xive7_pri$next[7:0]$14744 \xive7_pri
+ assign $2\xive8_pri$next[7:0]$14745 \xive8_pri
+ assign $2\xive9_pri$next[7:0]$14746 \xive9_pri
+ end
+ case
+ assign $1\xive0_pri$next[7:0]$14715 \xive0_pri
+ assign $1\xive10_pri$next[7:0]$14716 \xive10_pri
+ assign $1\xive11_pri$next[7:0]$14717 \xive11_pri
+ assign $1\xive12_pri$next[7:0]$14718 \xive12_pri
+ assign $1\xive13_pri$next[7:0]$14719 \xive13_pri
+ assign $1\xive14_pri$next[7:0]$14720 \xive14_pri
+ assign $1\xive15_pri$next[7:0]$14721 \xive15_pri
+ assign $1\xive1_pri$next[7:0]$14722 \xive1_pri
+ assign $1\xive2_pri$next[7:0]$14723 \xive2_pri
+ assign $1\xive3_pri$next[7:0]$14724 \xive3_pri
+ assign $1\xive4_pri$next[7:0]$14725 \xive4_pri
+ assign $1\xive5_pri$next[7:0]$14726 \xive5_pri
+ assign $1\xive6_pri$next[7:0]$14727 \xive6_pri
+ assign $1\xive7_pri$next[7:0]$14728 \xive7_pri
+ assign $1\xive8_pri$next[7:0]$14729 \xive8_pri
+ assign $1\xive9_pri$next[7:0]$14730 \xive9_pri
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\xive0_pri$next[7:0]$14951 8'11111111
- assign $4\xive1_pri$next[7:0]$14958 8'11111111
- assign $4\xive2_pri$next[7:0]$14959 8'11111111
- assign $4\xive3_pri$next[7:0]$14960 8'11111111
- assign $4\xive4_pri$next[7:0]$14961 8'11111111
- assign $4\xive5_pri$next[7:0]$14962 8'11111111
- assign $4\xive6_pri$next[7:0]$14963 8'11111111
- assign $4\xive7_pri$next[7:0]$14964 8'11111111
- assign $4\xive8_pri$next[7:0]$14965 8'11111111
- assign $4\xive9_pri$next[7:0]$14966 8'11111111
- assign $4\xive10_pri$next[7:0]$14952 8'11111111
- assign $4\xive11_pri$next[7:0]$14953 8'11111111
- assign $4\xive12_pri$next[7:0]$14954 8'11111111
- assign $4\xive13_pri$next[7:0]$14955 8'11111111
- assign $4\xive14_pri$next[7:0]$14956 8'11111111
- assign $4\xive15_pri$next[7:0]$14957 8'11111111
+ assign $4\xive0_pri$next[7:0]$14763 8'11111111
+ assign $4\xive1_pri$next[7:0]$14770 8'11111111
+ assign $4\xive2_pri$next[7:0]$14771 8'11111111
+ assign $4\xive3_pri$next[7:0]$14772 8'11111111
+ assign $4\xive4_pri$next[7:0]$14773 8'11111111
+ assign $4\xive5_pri$next[7:0]$14774 8'11111111
+ assign $4\xive6_pri$next[7:0]$14775 8'11111111
+ assign $4\xive7_pri$next[7:0]$14776 8'11111111
+ assign $4\xive8_pri$next[7:0]$14777 8'11111111
+ assign $4\xive9_pri$next[7:0]$14778 8'11111111
+ assign $4\xive10_pri$next[7:0]$14764 8'11111111
+ assign $4\xive11_pri$next[7:0]$14765 8'11111111
+ assign $4\xive12_pri$next[7:0]$14766 8'11111111
+ assign $4\xive13_pri$next[7:0]$14767 8'11111111
+ assign $4\xive14_pri$next[7:0]$14768 8'11111111
+ assign $4\xive15_pri$next[7:0]$14769 8'11111111
case
- assign $4\xive0_pri$next[7:0]$14951 $1\xive0_pri$next[7:0]$14903
- assign $4\xive10_pri$next[7:0]$14952 $1\xive10_pri$next[7:0]$14904
- assign $4\xive11_pri$next[7:0]$14953 $1\xive11_pri$next[7:0]$14905
- assign $4\xive12_pri$next[7:0]$14954 $1\xive12_pri$next[7:0]$14906
- assign $4\xive13_pri$next[7:0]$14955 $1\xive13_pri$next[7:0]$14907
- assign $4\xive14_pri$next[7:0]$14956 $1\xive14_pri$next[7:0]$14908
- assign $4\xive15_pri$next[7:0]$14957 $1\xive15_pri$next[7:0]$14909
- assign $4\xive1_pri$next[7:0]$14958 $1\xive1_pri$next[7:0]$14910
- assign $4\xive2_pri$next[7:0]$14959 $1\xive2_pri$next[7:0]$14911
- assign $4\xive3_pri$next[7:0]$14960 $1\xive3_pri$next[7:0]$14912
- assign $4\xive4_pri$next[7:0]$14961 $1\xive4_pri$next[7:0]$14913
- assign $4\xive5_pri$next[7:0]$14962 $1\xive5_pri$next[7:0]$14914
- assign $4\xive6_pri$next[7:0]$14963 $1\xive6_pri$next[7:0]$14915
- assign $4\xive7_pri$next[7:0]$14964 $1\xive7_pri$next[7:0]$14916
- assign $4\xive8_pri$next[7:0]$14965 $1\xive8_pri$next[7:0]$14917
- assign $4\xive9_pri$next[7:0]$14966 $1\xive9_pri$next[7:0]$14918
+ assign $4\xive0_pri$next[7:0]$14763 $1\xive0_pri$next[7:0]$14715
+ assign $4\xive10_pri$next[7:0]$14764 $1\xive10_pri$next[7:0]$14716
+ assign $4\xive11_pri$next[7:0]$14765 $1\xive11_pri$next[7:0]$14717
+ assign $4\xive12_pri$next[7:0]$14766 $1\xive12_pri$next[7:0]$14718
+ assign $4\xive13_pri$next[7:0]$14767 $1\xive13_pri$next[7:0]$14719
+ assign $4\xive14_pri$next[7:0]$14768 $1\xive14_pri$next[7:0]$14720
+ assign $4\xive15_pri$next[7:0]$14769 $1\xive15_pri$next[7:0]$14721
+ assign $4\xive1_pri$next[7:0]$14770 $1\xive1_pri$next[7:0]$14722
+ assign $4\xive2_pri$next[7:0]$14771 $1\xive2_pri$next[7:0]$14723
+ assign $4\xive3_pri$next[7:0]$14772 $1\xive3_pri$next[7:0]$14724
+ assign $4\xive4_pri$next[7:0]$14773 $1\xive4_pri$next[7:0]$14725
+ assign $4\xive5_pri$next[7:0]$14774 $1\xive5_pri$next[7:0]$14726
+ assign $4\xive6_pri$next[7:0]$14775 $1\xive6_pri$next[7:0]$14727
+ assign $4\xive7_pri$next[7:0]$14776 $1\xive7_pri$next[7:0]$14728
+ assign $4\xive8_pri$next[7:0]$14777 $1\xive8_pri$next[7:0]$14729
+ assign $4\xive9_pri$next[7:0]$14778 $1\xive9_pri$next[7:0]$14730
end
sync always
- update \xive0_pri$next $0\xive0_pri$next[7:0]$14887
- update \xive10_pri$next $0\xive10_pri$next[7:0]$14888
- update \xive11_pri$next $0\xive11_pri$next[7:0]$14889
- update \xive12_pri$next $0\xive12_pri$next[7:0]$14890
- update \xive13_pri$next $0\xive13_pri$next[7:0]$14891
- update \xive14_pri$next $0\xive14_pri$next[7:0]$14892
- update \xive15_pri$next $0\xive15_pri$next[7:0]$14893
- update \xive1_pri$next $0\xive1_pri$next[7:0]$14894
- update \xive2_pri$next $0\xive2_pri$next[7:0]$14895
- update \xive3_pri$next $0\xive3_pri$next[7:0]$14896
- update \xive4_pri$next $0\xive4_pri$next[7:0]$14897
- update \xive5_pri$next $0\xive5_pri$next[7:0]$14898
- update \xive6_pri$next $0\xive6_pri$next[7:0]$14899
- update \xive7_pri$next $0\xive7_pri$next[7:0]$14900
- update \xive8_pri$next $0\xive8_pri$next[7:0]$14901
- update \xive9_pri$next $0\xive9_pri$next[7:0]$14902
+ update \xive0_pri$next $0\xive0_pri$next[7:0]$14699
+ update \xive10_pri$next $0\xive10_pri$next[7:0]$14700
+ update \xive11_pri$next $0\xive11_pri$next[7:0]$14701
+ update \xive12_pri$next $0\xive12_pri$next[7:0]$14702
+ update \xive13_pri$next $0\xive13_pri$next[7:0]$14703
+ update \xive14_pri$next $0\xive14_pri$next[7:0]$14704
+ update \xive15_pri$next $0\xive15_pri$next[7:0]$14705
+ update \xive1_pri$next $0\xive1_pri$next[7:0]$14706
+ update \xive2_pri$next $0\xive2_pri$next[7:0]$14707
+ update \xive3_pri$next $0\xive3_pri$next[7:0]$14708
+ update \xive4_pri$next $0\xive4_pri$next[7:0]$14709
+ update \xive5_pri$next $0\xive5_pri$next[7:0]$14710
+ update \xive6_pri$next $0\xive6_pri$next[7:0]$14711
+ update \xive7_pri$next $0\xive7_pri$next[7:0]$14712
+ update \xive8_pri$next $0\xive8_pri$next[7:0]$14713
+ update \xive9_pri$next $0\xive9_pri$next[7:0]$14714
end
- attribute \src "libresoc.v:204889.3-204898.6"
- process $proc$libresoc.v:204889$14967
+ attribute \src "libresoc.v:203833.3-203842.6"
+ process $proc$libresoc.v:203833$14779
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:204890.5-204890.29"
+ attribute \src "libresoc.v:203834.5-203834.29"
switch \initial
- attribute \src "libresoc.v:204890.9-204890.17"
+ attribute \src "libresoc.v:203834.9-203834.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:204899.3-204908.6"
- process $proc$libresoc.v:204899$14968
+ attribute \src "libresoc.v:203843.3-203852.6"
+ process $proc$libresoc.v:203843$14780
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:204900.5-204900.29"
+ attribute \src "libresoc.v:203844.5-203844.29"
switch \initial
- attribute \src "libresoc.v:204900.9-204900.17"
+ attribute \src "libresoc.v:203844.9-203844.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:204909.3-204918.6"
- process $proc$libresoc.v:204909$14969
+ attribute \src "libresoc.v:203853.3-203862.6"
+ process $proc$libresoc.v:203853$14781
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:204910.5-204910.29"
+ attribute \src "libresoc.v:203854.5-203854.29"
switch \initial
- attribute \src "libresoc.v:204910.9-204910.17"
+ attribute \src "libresoc.v:203854.9-203854.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:204919.3-204928.6"
- process $proc$libresoc.v:204919$14970
+ attribute \src "libresoc.v:203863.3-203872.6"
+ process $proc$libresoc.v:203863$14782
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:204920.5-204920.29"
+ attribute \src "libresoc.v:203864.5-203864.29"
switch \initial
- attribute \src "libresoc.v:204920.9-204920.17"
+ attribute \src "libresoc.v:203864.9-203864.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:204929.3-204938.6"
- process $proc$libresoc.v:204929$14971
+ attribute \src "libresoc.v:203873.3-203882.6"
+ process $proc$libresoc.v:203873$14783
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:204930.5-204930.29"
+ attribute \src "libresoc.v:203874.5-203874.29"
switch \initial
- attribute \src "libresoc.v:204930.9-204930.17"
+ attribute \src "libresoc.v:203874.9-203874.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:204939.3-204948.6"
- process $proc$libresoc.v:204939$14972
+ attribute \src "libresoc.v:203883.3-203892.6"
+ process $proc$libresoc.v:203883$14784
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:204940.5-204940.29"
+ attribute \src "libresoc.v:203884.5-203884.29"
switch \initial
- attribute \src "libresoc.v:204940.9-204940.17"
+ attribute \src "libresoc.v:203884.9-203884.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:204949.3-204958.6"
- process $proc$libresoc.v:204949$14973
+ attribute \src "libresoc.v:203893.3-203902.6"
+ process $proc$libresoc.v:203893$14785
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:204950.5-204950.29"
+ attribute \src "libresoc.v:203894.5-203894.29"
switch \initial
- attribute \src "libresoc.v:204950.9-204950.17"
+ attribute \src "libresoc.v:203894.9-203894.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:204959.3-204968.6"
- process $proc$libresoc.v:204959$14974
+ attribute \src "libresoc.v:203903.3-203912.6"
+ process $proc$libresoc.v:203903$14786
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:204960.5-204960.29"
+ attribute \src "libresoc.v:203904.5-203904.29"
switch \initial
- attribute \src "libresoc.v:204960.9-204960.17"
+ attribute \src "libresoc.v:203904.9-203904.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:204969.3-204978.6"
- process $proc$libresoc.v:204969$14975
+ attribute \src "libresoc.v:203913.3-203922.6"
+ process $proc$libresoc.v:203913$14787
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:204970.5-204970.29"
+ attribute \src "libresoc.v:203914.5-203914.29"
switch \initial
- attribute \src "libresoc.v:204970.9-204970.17"
+ attribute \src "libresoc.v:203914.9-203914.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:204979.3-204987.6"
- process $proc$libresoc.v:204979$14976
+ attribute \src "libresoc.v:203923.3-203931.6"
+ process $proc$libresoc.v:203923$14788
assign { } { }
assign { } { }
- assign $0\int_level_l$next[15:0]$14977 $1\int_level_l$next[15:0]$14978
- attribute \src "libresoc.v:204980.5-204980.29"
+ assign $0\int_level_l$next[15:0]$14789 $1\int_level_l$next[15:0]$14790
+ attribute \src "libresoc.v:203924.5-203924.29"
switch \initial
- attribute \src "libresoc.v:204980.9-204980.17"
+ attribute \src "libresoc.v:203924.9-203924.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\int_level_l$next[15:0]$14978 16'0000000000000000
+ assign $1\int_level_l$next[15:0]$14790 16'0000000000000000
case
- assign $1\int_level_l$next[15:0]$14978 \int_level_i
+ assign $1\int_level_l$next[15:0]$14790 \int_level_i
end
sync always
- update \int_level_l$next $0\int_level_l$next[15:0]$14977
+ update \int_level_l$next $0\int_level_l$next[15:0]$14789
end
- attribute \src "libresoc.v:204988.3-204997.6"
- process $proc$libresoc.v:204988$14979
+ attribute \src "libresoc.v:203932.3-203941.6"
+ process $proc$libresoc.v:203932$14791
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:204989.5-204989.29"
+ attribute \src "libresoc.v:203933.5-203933.29"
switch \initial
- attribute \src "libresoc.v:204989.9-204989.17"
+ attribute \src "libresoc.v:203933.9-203933.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:204998.3-205007.6"
- process $proc$libresoc.v:204998$14980
+ attribute \src "libresoc.v:203942.3-203951.6"
+ process $proc$libresoc.v:203942$14792
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:204999.5-204999.29"
+ attribute \src "libresoc.v:203943.5-203943.29"
switch \initial
- attribute \src "libresoc.v:204999.9-204999.17"
+ attribute \src "libresoc.v:203943.9-203943.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:205008.3-205017.6"
- process $proc$libresoc.v:205008$14981
+ attribute \src "libresoc.v:203952.3-203961.6"
+ process $proc$libresoc.v:203952$14793
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:205009.5-205009.29"
+ attribute \src "libresoc.v:203953.5-203953.29"
switch \initial
- attribute \src "libresoc.v:205009.9-205009.17"
+ attribute \src "libresoc.v:203953.9-203953.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:205018.3-205027.6"
- process $proc$libresoc.v:205018$14982
+ attribute \src "libresoc.v:203962.3-203971.6"
+ process $proc$libresoc.v:203962$14794
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:205019.5-205019.29"
+ attribute \src "libresoc.v:203963.5-203963.29"
switch \initial
- attribute \src "libresoc.v:205019.9-205019.17"
+ attribute \src "libresoc.v:203963.9-203963.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:205028.3-205037.6"
- process $proc$libresoc.v:205028$14983
+ attribute \src "libresoc.v:203972.3-203981.6"
+ process $proc$libresoc.v:203972$14795
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:205029.5-205029.29"
+ attribute \src "libresoc.v:203973.5-203973.29"
switch \initial
- attribute \src "libresoc.v:205029.9-205029.17"
+ attribute \src "libresoc.v:203973.9-203973.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:205038.3-205047.6"
- process $proc$libresoc.v:205038$14984
+ attribute \src "libresoc.v:203982.3-203991.6"
+ process $proc$libresoc.v:203982$14796
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:205039.5-205039.29"
+ attribute \src "libresoc.v:203983.5-203983.29"
switch \initial
- attribute \src "libresoc.v:205039.9-205039.17"
+ attribute \src "libresoc.v:203983.9-203983.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:205048.3-205057.6"
- process $proc$libresoc.v:205048$14985
+ attribute \src "libresoc.v:203992.3-204001.6"
+ process $proc$libresoc.v:203992$14797
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:205049.5-205049.29"
+ attribute \src "libresoc.v:203993.5-203993.29"
switch \initial
- attribute \src "libresoc.v:205049.9-205049.17"
+ attribute \src "libresoc.v:203993.9-203993.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:205058.3-205067.6"
- process $proc$libresoc.v:205058$14986
+ attribute \src "libresoc.v:204002.3-204011.6"
+ process $proc$libresoc.v:204002$14798
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:205059.5-205059.29"
+ attribute \src "libresoc.v:204003.5-204003.29"
switch \initial
- attribute \src "libresoc.v:205059.9-205059.17"
+ attribute \src "libresoc.v:204003.9-204003.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:205068.3-205077.6"
- process $proc$libresoc.v:205068$14987
+ attribute \src "libresoc.v:204012.3-204021.6"
+ process $proc$libresoc.v:204012$14799
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:205069.5-205069.29"
+ attribute \src "libresoc.v:204013.5-204013.29"
switch \initial
- attribute \src "libresoc.v:205069.9-205069.17"
+ attribute \src "libresoc.v:204013.9-204013.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:205078.3-205087.6"
- process $proc$libresoc.v:205078$14988
+ attribute \src "libresoc.v:204022.3-204031.6"
+ process $proc$libresoc.v:204022$14800
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:205079.5-205079.29"
+ attribute \src "libresoc.v:204023.5-204023.29"
switch \initial
- attribute \src "libresoc.v:205079.9-205079.17"
+ attribute \src "libresoc.v:204023.9-204023.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:205088.3-205097.6"
- process $proc$libresoc.v:205088$14989
+ attribute \src "libresoc.v:204032.3-204041.6"
+ process $proc$libresoc.v:204032$14801
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:205089.5-205089.29"
+ attribute \src "libresoc.v:204033.5-204033.29"
switch \initial
- attribute \src "libresoc.v:205089.9-205089.17"
+ attribute \src "libresoc.v:204033.9-204033.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:205098.3-205107.6"
- process $proc$libresoc.v:205098$14990
+ attribute \src "libresoc.v:204042.3-204051.6"
+ process $proc$libresoc.v:204042$14802
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:205099.5-205099.29"
+ attribute \src "libresoc.v:204043.5-204043.29"
switch \initial
- attribute \src "libresoc.v:205099.9-205099.17"
+ attribute \src "libresoc.v:204043.9-204043.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:205108.3-205117.6"
- process $proc$libresoc.v:205108$14991
+ attribute \src "libresoc.v:204052.3-204061.6"
+ process $proc$libresoc.v:204052$14803
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:205109.5-205109.29"
+ attribute \src "libresoc.v:204053.5-204053.29"
switch \initial
- attribute \src "libresoc.v:205109.9-205109.17"
+ attribute \src "libresoc.v:204053.9-204053.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:205118.3-205127.6"
- process $proc$libresoc.v:205118$14992
+ attribute \src "libresoc.v:204062.3-204071.6"
+ process $proc$libresoc.v:204062$14804
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:205119.5-205119.29"
+ attribute \src "libresoc.v:204063.5-204063.29"
switch \initial
- attribute \src "libresoc.v:205119.9-205119.17"
+ attribute \src "libresoc.v:204063.9-204063.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:205128.3-205137.6"
- process $proc$libresoc.v:205128$14993
+ attribute \src "libresoc.v:204072.3-204081.6"
+ process $proc$libresoc.v:204072$14805
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:205129.5-205129.29"
+ attribute \src "libresoc.v:204073.5-204073.29"
switch \initial
- attribute \src "libresoc.v:205129.9-205129.17"
+ attribute \src "libresoc.v:204073.9-204073.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:205138.3-205147.6"
- process $proc$libresoc.v:205138$14994
+ attribute \src "libresoc.v:204082.3-204091.6"
+ process $proc$libresoc.v:204082$14806
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:205139.5-205139.29"
+ attribute \src "libresoc.v:204083.5-204083.29"
switch \initial
- attribute \src "libresoc.v:205139.9-205139.17"
+ attribute \src "libresoc.v:204083.9-204083.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:205148.3-205157.6"
- process $proc$libresoc.v:205148$14995
+ attribute \src "libresoc.v:204092.3-204101.6"
+ process $proc$libresoc.v:204092$14807
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:205149.5-205149.29"
+ attribute \src "libresoc.v:204093.5-204093.29"
switch \initial
- attribute \src "libresoc.v:205149.9-205149.17"
+ attribute \src "libresoc.v:204093.9-204093.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:205158.3-205167.6"
- process $proc$libresoc.v:205158$14996
+ attribute \src "libresoc.v:204102.3-204111.6"
+ process $proc$libresoc.v:204102$14808
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:205159.5-205159.29"
+ attribute \src "libresoc.v:204103.5-204103.29"
switch \initial
- attribute \src "libresoc.v:205159.9-205159.17"
+ attribute \src "libresoc.v:204103.9-204103.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:205168.3-205177.6"
- process $proc$libresoc.v:205168$14997
+ attribute \src "libresoc.v:204112.3-204121.6"
+ process $proc$libresoc.v:204112$14809
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:205169.5-205169.29"
+ attribute \src "libresoc.v:204113.5-204113.29"
switch \initial
- attribute \src "libresoc.v:205169.9-205169.17"
+ attribute \src "libresoc.v:204113.9-204113.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:205178.3-205187.6"
- process $proc$libresoc.v:205178$14998
+ attribute \src "libresoc.v:204122.3-204131.6"
+ process $proc$libresoc.v:204122$14810
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:205179.5-205179.29"
+ attribute \src "libresoc.v:204123.5-204123.29"
switch \initial
- attribute \src "libresoc.v:205179.9-205179.17"
+ attribute \src "libresoc.v:204123.9-204123.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:205188.3-205237.6"
- process $proc$libresoc.v:205188$14999
+ attribute \src "libresoc.v:204132.3-204181.6"
+ process $proc$libresoc.v:204132$14811
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:205189.5-205189.29"
+ attribute \src "libresoc.v:204133.5-204133.29"
switch \initial
- attribute \src "libresoc.v:205189.9-205189.17"
+ attribute \src "libresoc.v:204133.9-204133.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:205238.3-205247.6"
- process $proc$libresoc.v:205238$15000
+ attribute \src "libresoc.v:204182.3-204191.6"
+ process $proc$libresoc.v:204182$14812
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:205239.5-205239.29"
+ attribute \src "libresoc.v:204183.5-204183.29"
switch \initial
- attribute \src "libresoc.v:205239.9-205239.17"
+ attribute \src "libresoc.v:204183.9-204183.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:205248.3-205257.6"
- process $proc$libresoc.v:205248$15001
+ attribute \src "libresoc.v:204192.3-204201.6"
+ process $proc$libresoc.v:204192$14813
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:205249.5-205249.29"
+ attribute \src "libresoc.v:204193.5-204193.29"
switch \initial
- attribute \src "libresoc.v:205249.9-205249.17"
+ attribute \src "libresoc.v:204193.9-204193.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:205258.3-205267.6"
- process $proc$libresoc.v:205258$15002
+ attribute \src "libresoc.v:204202.3-204211.6"
+ process $proc$libresoc.v:204202$14814
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:205259.5-205259.29"
+ attribute \src "libresoc.v:204203.5-204203.29"
switch \initial
- attribute \src "libresoc.v:205259.9-205259.17"
+ attribute \src "libresoc.v:204203.9-204203.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:205268.3-205277.6"
- process $proc$libresoc.v:205268$15003
+ attribute \src "libresoc.v:204212.3-204221.6"
+ process $proc$libresoc.v:204212$14815
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:205269.5-205269.29"
+ attribute \src "libresoc.v:204213.5-204213.29"
switch \initial
- attribute \src "libresoc.v:205269.9-205269.17"
+ attribute \src "libresoc.v:204213.9-204213.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:205278.3-205286.6"
- process $proc$libresoc.v:205278$15004
+ attribute \src "libresoc.v:204222.3-204230.6"
+ process $proc$libresoc.v:204222$14816
assign { } { }
assign { } { }
- assign $0\ics_wb__dat_r$next[31:0]$15005 $1\ics_wb__dat_r$next[31:0]$15006
- attribute \src "libresoc.v:205279.5-205279.29"
+ assign $0\ics_wb__dat_r$next[31:0]$14817 $1\ics_wb__dat_r$next[31:0]$14818
+ attribute \src "libresoc.v:204223.5-204223.29"
switch \initial
- attribute \src "libresoc.v:205279.9-205279.17"
+ attribute \src "libresoc.v:204223.9-204223.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__dat_r$next[31:0]$15006 0
+ assign $1\ics_wb__dat_r$next[31:0]$14818 0
case
- assign $1\ics_wb__dat_r$next[31:0]$15006 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $1\ics_wb__dat_r$next[31:0]$14818 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
end
sync always
- update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15005
+ update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14817
end
- attribute \src "libresoc.v:205287.3-205295.6"
- process $proc$libresoc.v:205287$15007
+ attribute \src "libresoc.v:204231.3-204239.6"
+ process $proc$libresoc.v:204231$14819
assign { } { }
assign { } { }
- assign $0\ics_wb__ack$next[0:0]$15008 $1\ics_wb__ack$next[0:0]$15009
- attribute \src "libresoc.v:205288.5-205288.29"
+ assign $0\ics_wb__ack$next[0:0]$14820 $1\ics_wb__ack$next[0:0]$14821
+ attribute \src "libresoc.v:204232.5-204232.29"
switch \initial
- attribute \src "libresoc.v:205288.9-205288.17"
+ attribute \src "libresoc.v:204232.9-204232.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__ack$next[0:0]$15009 1'0
- case
- assign $1\ics_wb__ack$next[0:0]$15009 \wb_valid
- end
- sync always
- update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15008
- end
- connect \$7 $ternary$libresoc.v:204658$14762_Y
- connect \$99 $lt$libresoc.v:204659$14763_Y
- connect \$101 $and$libresoc.v:204660$14764_Y
- connect \$103 $lt$libresoc.v:204661$14765_Y
- connect \$105 $and$libresoc.v:204662$14766_Y
- connect \$107 $lt$libresoc.v:204663$14767_Y
- connect \$109 $and$libresoc.v:204664$14768_Y
- connect \$111 $lt$libresoc.v:204665$14769_Y
- connect \$113 $and$libresoc.v:204666$14770_Y
- connect \$115 $lt$libresoc.v:204667$14771_Y
- connect \$117 $and$libresoc.v:204668$14772_Y
- connect \$119 $lt$libresoc.v:204669$14773_Y
- connect \$121 $and$libresoc.v:204670$14774_Y
- connect \$123 $lt$libresoc.v:204671$14775_Y
- connect \$125 $and$libresoc.v:204672$14776_Y
- connect \$127 $lt$libresoc.v:204673$14777_Y
- connect \$12 $eq$libresoc.v:204674$14778_Y
- connect \$129 $and$libresoc.v:204675$14779_Y
- connect \$131 $lt$libresoc.v:204676$14780_Y
- connect \$133 $and$libresoc.v:204677$14781_Y
- connect \$135 $lt$libresoc.v:204678$14782_Y
- connect \$137 $and$libresoc.v:204679$14783_Y
- connect \$11 $ternary$libresoc.v:204680$14784_Y
- connect \$139 $lt$libresoc.v:204681$14785_Y
- connect \$141 $and$libresoc.v:204682$14786_Y
- connect \$143 $lt$libresoc.v:204683$14787_Y
- connect \$145 $and$libresoc.v:204684$14788_Y
- connect \$147 $lt$libresoc.v:204685$14789_Y
- connect \$149 $and$libresoc.v:204686$14790_Y
- connect \$151 $lt$libresoc.v:204687$14791_Y
- connect \$153 $and$libresoc.v:204688$14792_Y
- connect \$155 $lt$libresoc.v:204689$14793_Y
- connect \$157 $and$libresoc.v:204690$14794_Y
- connect \$159 $lt$libresoc.v:204691$14795_Y
- connect \$161 $and$libresoc.v:204692$14796_Y
- connect \$163 $lt$libresoc.v:204693$14797_Y
- connect \$165 $and$libresoc.v:204694$14798_Y
- connect \$167 $lt$libresoc.v:204695$14799_Y
- connect \$16 $eq$libresoc.v:204696$14800_Y
- connect \$169 $and$libresoc.v:204697$14801_Y
- connect \$171 $lt$libresoc.v:204698$14802_Y
- connect \$173 $and$libresoc.v:204699$14803_Y
- connect \$175 $lt$libresoc.v:204700$14804_Y
- connect \$177 $and$libresoc.v:204701$14805_Y
- connect \$15 $ternary$libresoc.v:204702$14806_Y
- connect \$179 $lt$libresoc.v:204703$14807_Y
- connect \$181 $and$libresoc.v:204704$14808_Y
- connect \$183 $lt$libresoc.v:204705$14809_Y
- connect \$185 $and$libresoc.v:204706$14810_Y
- connect \$187 $lt$libresoc.v:204707$14811_Y
- connect \$189 $and$libresoc.v:204708$14812_Y
- connect \$191 $lt$libresoc.v:204709$14813_Y
- connect \$193 $and$libresoc.v:204710$14814_Y
- connect \$195 $lt$libresoc.v:204711$14815_Y
- connect \$197 $and$libresoc.v:204712$14816_Y
- connect \$1 $eq$libresoc.v:204713$14817_Y
- connect \$199 $lt$libresoc.v:204714$14818_Y
- connect \$201 $and$libresoc.v:204715$14819_Y
- connect \$204 $eq$libresoc.v:204716$14820_Y
- connect \$203 $ternary$libresoc.v:204717$14821_Y
- connect \$20 $eq$libresoc.v:204718$14822_Y
- connect \$19 $ternary$libresoc.v:204719$14823_Y
- connect \$24 $eq$libresoc.v:204720$14824_Y
- connect \$23 $ternary$libresoc.v:204721$14825_Y
- connect \$28 $eq$libresoc.v:204722$14826_Y
- connect \$27 $ternary$libresoc.v:204723$14827_Y
- connect \$32 $eq$libresoc.v:204724$14828_Y
- connect \$31 $ternary$libresoc.v:204725$14829_Y
- connect \$36 $eq$libresoc.v:204726$14830_Y
- connect \$35 $ternary$libresoc.v:204727$14831_Y
- connect \$3 $eq$libresoc.v:204728$14832_Y
- connect \$40 $eq$libresoc.v:204729$14833_Y
- connect \$39 $ternary$libresoc.v:204730$14834_Y
- connect \$44 $eq$libresoc.v:204731$14835_Y
- connect \$43 $ternary$libresoc.v:204732$14836_Y
- connect \$48 $eq$libresoc.v:204733$14837_Y
- connect \$47 $ternary$libresoc.v:204734$14838_Y
- connect \$52 $eq$libresoc.v:204735$14839_Y
- connect \$51 $ternary$libresoc.v:204736$14840_Y
- connect \$56 $eq$libresoc.v:204737$14841_Y
- connect \$55 $ternary$libresoc.v:204738$14842_Y
- connect \$5 $and$libresoc.v:204739$14843_Y
- connect \$60 $eq$libresoc.v:204740$14844_Y
- connect \$59 $ternary$libresoc.v:204741$14845_Y
- connect \$64 $eq$libresoc.v:204742$14846_Y
- connect \$63 $ternary$libresoc.v:204743$14847_Y
- connect \$68 $eq$libresoc.v:204744$14848_Y
- connect \$67 $ternary$libresoc.v:204745$14849_Y
- connect \$71 $shr$libresoc.v:204746$14850_Y [0]
- connect \$73 $and$libresoc.v:204747$14851_Y
- connect \$75 $lt$libresoc.v:204748$14852_Y
- connect \$77 $and$libresoc.v:204749$14853_Y
- connect \$79 $lt$libresoc.v:204750$14854_Y
- connect \$81 $and$libresoc.v:204751$14855_Y
- connect \$83 $lt$libresoc.v:204752$14856_Y
- connect \$85 $and$libresoc.v:204753$14857_Y
- connect \$87 $lt$libresoc.v:204754$14858_Y
- connect \$8 $eq$libresoc.v:204755$14859_Y
- connect \$89 $and$libresoc.v:204756$14860_Y
- connect \$91 $lt$libresoc.v:204757$14861_Y
- connect \$93 $and$libresoc.v:204758$14862_Y
- connect \$95 $lt$libresoc.v:204759$14863_Y
- connect \$97 $and$libresoc.v:204760$14864_Y
+ assign $1\ics_wb__ack$next[0:0]$14821 1'0
+ case
+ assign $1\ics_wb__ack$next[0:0]$14821 \wb_valid
+ end
+ sync always
+ update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14820
+ end
+ connect \$7 $ternary$libresoc.v:203602$14574_Y
+ connect \$99 $lt$libresoc.v:203603$14575_Y
+ connect \$101 $and$libresoc.v:203604$14576_Y
+ connect \$103 $lt$libresoc.v:203605$14577_Y
+ connect \$105 $and$libresoc.v:203606$14578_Y
+ connect \$107 $lt$libresoc.v:203607$14579_Y
+ connect \$109 $and$libresoc.v:203608$14580_Y
+ connect \$111 $lt$libresoc.v:203609$14581_Y
+ connect \$113 $and$libresoc.v:203610$14582_Y
+ connect \$115 $lt$libresoc.v:203611$14583_Y
+ connect \$117 $and$libresoc.v:203612$14584_Y
+ connect \$119 $lt$libresoc.v:203613$14585_Y
+ connect \$121 $and$libresoc.v:203614$14586_Y
+ connect \$123 $lt$libresoc.v:203615$14587_Y
+ connect \$125 $and$libresoc.v:203616$14588_Y
+ connect \$127 $lt$libresoc.v:203617$14589_Y
+ connect \$12 $eq$libresoc.v:203618$14590_Y
+ connect \$129 $and$libresoc.v:203619$14591_Y
+ connect \$131 $lt$libresoc.v:203620$14592_Y
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+ connect \$97 $and$libresoc.v:203704$14676_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff